Kconfig 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393
  1. menu "Main Flash configuration"
  2. depends on !APP_BUILD_TYPE_PURE_RAM_APP
  3. menu "SPI Flash behavior when brownout"
  4. config SPI_FLASH_BROWNOUT_RESET_XMC
  5. bool "Enable sending reset when brownout for XMC flash chips"
  6. default y
  7. select SPI_FLASH_BROWNOUT_RESET
  8. help
  9. When this option is selected, the patch will be enabled for XMC.
  10. Follow the recommended flow by XMC for better stability.
  11. DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING.
  12. config SPI_FLASH_BROWNOUT_RESET
  13. bool
  14. default y
  15. select ESP_SYSTEM_BROWNOUT_INTR
  16. help
  17. When brownout happens during flash erase/write operations,
  18. send reset command to stop the flash operations to improve stability.
  19. endmenu
  20. menu "Optional and Experimental Features (READ DOCS FIRST)"
  21. comment "Features here require specific hardware (READ DOCS FIRST!)"
  22. config SPI_FLASH_UNDER_HIGH_FREQ
  23. bool
  24. default y if ESPTOOLPY_FLASHFREQ_120M
  25. help
  26. This is a helper config for HPM. Invisible for users.
  27. choice SPI_FLASH_HPM
  28. prompt "High Performance Mode (READ DOCS FIRST, > 80MHz)"
  29. # Currently, only esp32s3 allows high performance mode.
  30. depends on IDF_TARGET_ESP32S3 && !ESPTOOLPY_OCT_FLASH
  31. default SPI_FLASH_HPM_AUTO
  32. help
  33. Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually
  34. enable this option as a confirmation. To be back-compatible with earlier IDF versionn, this option is
  35. automatically enabled with warning when Flash running > 80Mhz.
  36. config SPI_FLASH_HPM_ENA
  37. # Not using name of SPI_FLASH_HPM_ENABLE because it was used as an invisible option and we don't want
  38. # to inherit the value of that one
  39. bool "Enable"
  40. config SPI_FLASH_HPM_AUTO
  41. bool "Auto (Not recommended)"
  42. config SPI_FLASH_HPM_DIS
  43. bool "Disabled"
  44. endchoice
  45. config SPI_FLASH_HPM_ON
  46. bool
  47. # For ESP32-S3, it's enabled by default. For later chips it should be disabled by default
  48. default y if IDF_TARGET_ESP32S3 && ((SPI_FLASH_HPM_ENA || SPI_FLASH_HPM_AUTO)) || \
  49. (!IDF_TARGET_ESP32S3 && SPI_FLASH_HPM_ENA)
  50. help
  51. This option is invisible, and will be selected automatically
  52. when ``ESPTOOLPY_FLASHFREQ_120M`` is selected.
  53. choice SPI_FLASH_HPM_DC
  54. prompt "Support HPM using DC (READ DOCS FIRST)"
  55. depends on SPI_FLASH_HPM_ON
  56. default SPI_FLASH_HPM_DC_AUTO
  57. help
  58. This feature needs your bootloader to be compiled DC-aware (BOOTLOADER_FLASH_DC_AWARE=y). Otherwise the
  59. chip will not be able to boot after a reset.
  60. config SPI_FLASH_HPM_DC_AUTO
  61. bool "Auto (Enable when bootloader support enabled (BOOTLOADER_FLASH_DC_AWARE))"
  62. config SPI_FLASH_HPM_DC_DISABLE
  63. bool "Disable (READ DOCS FIRST)"
  64. endchoice
  65. config SPI_FLASH_HPM_DC_ON
  66. bool
  67. default y if SPI_FLASH_HPM_DC_AUTO && BOOTLOADER_FLASH_DC_AWARE
  68. help
  69. This is a helper config for HPM. Whether HPM-DC is enabled is also determined by bootloader.
  70. Invisible for users.
  71. config SPI_FLASH_SUSPEND_QVL_SUPPORTED
  72. bool
  73. default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2
  74. default n
  75. help
  76. This is a helper config. Invisible for users.
  77. config SPI_FLASH_AUTO_SUSPEND
  78. bool "Auto suspend long erase/write operations (READ DOCS FIRST)"
  79. default n
  80. depends on SPI_FLASH_SUSPEND_QVL_SUPPORTED && !SPI_FLASH_ROM_IMPL
  81. help
  82. This option is disabled by default because it is supported only
  83. for specific flash chips and for specific Espressif chips.
  84. To evaluate if you can use this feature refer to
  85. `Optional Features for Flash` > `Auto Suspend & Resume` of the `ESP-IDF Programming Guide`.
  86. CAUTION: If you want to OTA to an app with this feature turned on, please make
  87. sure the bootloader has the support for it. (later than IDF v4.3)
  88. If you are using an official Espressif module, please contact Espressif Business support
  89. to check if the module has the flash that support this feature installed.
  90. Also refer to `Concurrency Constraints for Flash on SPI1` > `Flash Auto Suspend Feature`
  91. before enabling this option.
  92. config SPI_FLASH_SUSPEND_TSUS_VAL_US
  93. int "SPI flash tSUS value (refer to chapter AC CHARACTERISTICS)"
  94. default 50
  95. range 20 100
  96. help
  97. This config is used for setting Tsus parameter. Tsus means CS# high to next command after
  98. suspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.
  99. endmenu
  100. endmenu
  101. menu "SPI Flash driver"
  102. depends on !APP_BUILD_TYPE_PURE_RAM_APP
  103. config SPI_FLASH_VERIFY_WRITE
  104. bool "Verify SPI flash writes"
  105. depends on !SPI_FLASH_ROM_IMPL
  106. default n
  107. help
  108. If this option is enabled, any time SPI flash is written then the data will be read
  109. back and verified. This can catch hardware problems with SPI flash, or flash which
  110. was not erased before verification.
  111. config SPI_FLASH_LOG_FAILED_WRITE
  112. bool "Log errors if verification fails"
  113. depends on SPI_FLASH_VERIFY_WRITE
  114. default n
  115. help
  116. If this option is enabled, if SPI flash write verification fails then a log error line
  117. will be written with the address, expected & actual values. This can be useful when
  118. debugging hardware SPI flash problems.
  119. config SPI_FLASH_WARN_SETTING_ZERO_TO_ONE
  120. bool "Log warning if writing zero bits to ones"
  121. depends on SPI_FLASH_VERIFY_WRITE
  122. default n
  123. help
  124. If this option is enabled, any SPI flash write which tries to set zero bits in the flash to
  125. ones will log a warning. Such writes will not result in the requested data appearing identically
  126. in flash once written, as SPI NOR flash can only set bits to one when an entire sector is erased.
  127. After erasing, individual bits can only be written from one to zero.
  128. Note that some software (such as SPIFFS) which is aware of SPI NOR flash may write one bits as an
  129. optimisation, relying on the data in flash becoming a bitwise AND of the new data and any existing data.
  130. Such software will log spurious warnings if this option is enabled.
  131. config SPI_FLASH_ENABLE_COUNTERS
  132. bool "Enable operation counters"
  133. default n
  134. help
  135. This option enables the following APIs:
  136. - esp_flash_reset_counters
  137. - esp_flash_dump_counters
  138. - esp_flash_get_counters
  139. These APIs may be used to collect performance data for spi_flash APIs
  140. and to help understand behaviour of libraries which use SPI flash.
  141. config SPI_FLASH_ROM_DRIVER_PATCH
  142. bool "Enable SPI flash ROM driver patched functions"
  143. default y
  144. help
  145. Enable this flag to use patched versions of SPI flash ROM driver functions.
  146. This option should be enabled, if any one of the following is true: (1) need to write
  147. to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main
  148. SPI flash chip is manufactured by ISSI.
  149. config SPI_FLASH_ROM_IMPL
  150. bool "Use esp_flash implementation in ROM"
  151. depends on ESP_ROM_HAS_SPI_FLASH
  152. default n
  153. help
  154. Enable this flag to use new SPI flash driver functions from ROM instead of ESP-IDF.
  155. If keeping this as "n" in your project, you will have less free IRAM.
  156. But you can use all of our flash features.
  157. If making this as "y" in your project, you will increase free IRAM.
  158. But you may miss out on some flash features and support for new flash chips.
  159. Currently the ROM cannot support the following features:
  160. - SPI_FLASH_AUTO_SUSPEND (C3, S3)
  161. choice SPI_FLASH_DANGEROUS_WRITE
  162. bool "Writing to dangerous flash regions"
  163. default SPI_FLASH_DANGEROUS_WRITE_ALLOWED if APP_BUILD_TYPE_RAM
  164. default SPI_FLASH_DANGEROUS_WRITE_ABORTS
  165. help
  166. SPI flash APIs can optionally abort or return a failure code
  167. if erasing or writing addresses that fall at the beginning
  168. of flash (covering the bootloader and partition table) or that
  169. overlap the app partition that contains the running app.
  170. It is not recommended to ever write to these regions from an IDF app,
  171. and this check prevents logic errors or corrupted firmware memory from
  172. damaging these regions.
  173. Note that this feature *does not* check calls to the esp_rom_xxx SPI flash
  174. ROM functions. These functions should not be called directly from IDF
  175. applications.
  176. config SPI_FLASH_DANGEROUS_WRITE_ABORTS
  177. bool "Aborts"
  178. config SPI_FLASH_DANGEROUS_WRITE_FAILS
  179. bool "Fails"
  180. config SPI_FLASH_DANGEROUS_WRITE_ALLOWED
  181. bool "Allowed"
  182. endchoice
  183. config SPI_FLASH_SHARE_SPI1_BUS
  184. bool "Support other devices attached to SPI1 bus"
  185. default n
  186. depends on IDF_TARGET_ESP32
  187. select SPI_MASTER_ISR_IN_IRAM
  188. help
  189. Each SPI bus needs a lock for arbitration among devices. This allows multiple
  190. devices on a same bus, but may reduce the speed of esp_flash driver access to the
  191. main flash chip.
  192. If you only need to use esp_flash driver to access the main flash chip, disable
  193. this option, and the lock will be bypassed on SPI1 bus. Otherwise if extra devices
  194. are needed to attach to SPI1 bus, enable this option.
  195. config SPI_FLASH_BYPASS_BLOCK_ERASE
  196. bool "Bypass a block erase and always do sector erase"
  197. default n
  198. help
  199. Some flash chips can have very high "max" erase times, especially for block erase (32KB or 64KB).
  200. This option allows to bypass "block erase" and always do sector erase commands.
  201. This will be much slower overall in most cases, but improves latency for other code to run.
  202. config SPI_FLASH_YIELD_DURING_ERASE
  203. bool "Enables yield operation during flash erase"
  204. default y
  205. help
  206. This allows to yield the CPUs between erase commands.
  207. Prevents starvation of other tasks.
  208. Please use this configuration together with ``SPI_FLASH_ERASE_YIELD_DURATION_MS`` and
  209. ``SPI_FLASH_ERASE_YIELD_TICKS`` after carefully checking flash datasheet to avoid a
  210. watchdog timeout.
  211. For more information, please check `SPI Flash API` reference documenation
  212. under section `OS Function`.
  213. config SPI_FLASH_ERASE_YIELD_DURATION_MS
  214. int "Duration of erasing to yield CPUs (ms)"
  215. depends on SPI_FLASH_YIELD_DURING_ERASE
  216. default 20
  217. help
  218. If a duration of one erase command is large
  219. then it will yield CPUs after finishing a current command.
  220. config SPI_FLASH_ERASE_YIELD_TICKS
  221. int "CPU release time (tick) for an erase operation"
  222. depends on SPI_FLASH_YIELD_DURING_ERASE
  223. default 1
  224. help
  225. Defines how many ticks will be before returning to continue a erasing.
  226. config SPI_FLASH_WRITE_CHUNK_SIZE
  227. int "Flash write chunk size"
  228. default 8192
  229. range 256 8192
  230. help
  231. Flash write is broken down in terms of multiple (smaller) write operations.
  232. This configuration options helps to set individual write chunk size, smaller
  233. value here ensures that cache (and non-IRAM resident interrupts) remains
  234. disabled for shorter duration.
  235. config SPI_FLASH_SIZE_OVERRIDE
  236. bool "Override flash size in bootloader header by ESPTOOLPY_FLASHSIZE"
  237. default n
  238. help
  239. SPI Flash driver uses the flash size configured in bootloader header by default.
  240. Enable this option to override flash size with latest ESPTOOLPY_FLASHSIZE value from
  241. the app header if the size in the bootloader header is incorrect.
  242. config SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
  243. bool "Flash timeout checkout disabled"
  244. default n
  245. help
  246. This option is helpful if you are using a flash chip whose timeout is quite large or unpredictable.
  247. config SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST
  248. bool "Override default chip driver list"
  249. default n
  250. help
  251. This option allows the chip driver list to be customized, instead of using the default list provided by
  252. ESP-IDF.
  253. When this option is enabled, the default list is no longer compiled or linked. Instead, the
  254. `default_registered_chips` structure must be provided by the user.
  255. See example: custom_chip_driver under examples/storage for more details.
  256. menu "Auto-detect flash chips"
  257. visible if !SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST
  258. orsource "./$IDF_TARGET/Kconfig.soc_caps.in"
  259. config SPI_FLASH_SUPPORT_ISSI_CHIP
  260. bool "ISSI"
  261. default y if SPI_FLASH_VENDOR_ISSI_SUPPORTED
  262. default n
  263. help
  264. Enable this to support auto detection of ISSI chips if chip vendor not directly
  265. given by ``chip_drv`` member of the chip struct. This adds support for variant
  266. chips, however will extend detecting time.
  267. config SPI_FLASH_SUPPORT_MXIC_CHIP
  268. bool "MXIC"
  269. default y if SPI_FLASH_VENDOR_MXIC_SUPPORTED
  270. default n
  271. help
  272. Enable this to support auto detection of MXIC chips if chip vendor not directly
  273. given by ``chip_drv`` member of the chip struct. This adds support for variant
  274. chips, however will extend detecting time.
  275. config SPI_FLASH_SUPPORT_GD_CHIP
  276. bool "GigaDevice"
  277. default y if SPI_FLASH_VENDOR_GD_SUPPORTED
  278. default n
  279. help
  280. Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
  281. directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
  282. modules, please don't disable this, otherwise your flash may not work in 4-bit
  283. mode.
  284. This adds support for variant chips, however will extend detecting time and image
  285. size. Note that the default chip driver supports the GD chips with product ID
  286. 60H.
  287. config SPI_FLASH_SUPPORT_WINBOND_CHIP
  288. bool "Winbond"
  289. default y if SPI_FLASH_VENDOR_WINBOND_SUPPORTED
  290. default n
  291. help
  292. Enable this to support auto detection of Winbond chips if chip vendor not directly
  293. given by ``chip_drv`` member of the chip struct. This adds support for variant
  294. chips, however will extend detecting time.
  295. config SPI_FLASH_SUPPORT_BOYA_CHIP
  296. bool "BOYA"
  297. # ESP32 doens't usually use this chip, default n to save iram.
  298. default y if SPI_FLASH_VENDOR_BOYA_SUPPORTED
  299. default n
  300. help
  301. Enable this to support auto detection of BOYA chips if chip vendor not directly
  302. given by ``chip_drv`` member of the chip struct. This adds support for variant
  303. chips, however will extend detecting time.
  304. config SPI_FLASH_SUPPORT_TH_CHIP
  305. bool "TH"
  306. # ESP32 doens't usually use this chip, default n to save iram.
  307. default y if SPI_FLASH_VENDOR_TH_SUPPORTED
  308. default n
  309. help
  310. Enable this to support auto detection of TH chips if chip vendor not directly
  311. given by ``chip_drv`` member of the chip struct. This adds support for variant
  312. chips, however will extend detecting time.
  313. config SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
  314. bool "mxic (opi)"
  315. depends on IDF_TARGET_ESP32S3
  316. default y
  317. help
  318. Enable this to support auto detection of Octal MXIC chips if chip vendor not directly
  319. given by ``chip_drv`` member of the chip struct. This adds support for variant
  320. chips, however will extend detecting time.
  321. endmenu #auto detect flash chips
  322. config SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE
  323. bool "Enable encrypted partition read/write operations"
  324. default y
  325. help
  326. This option enables flash read/write operations to encrypted partition/s. This option
  327. is kept enabled irrespective of state of flash encryption feature. However, in case
  328. application is not using flash encryption feature and is in need of some additional
  329. memory from IRAM region (~1KB) then this config can be disabled.
  330. endmenu