adc_hal_common.c 6.3 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <sys/param.h>
  7. #include "sdkconfig.h"
  8. #include "soc/soc_caps.h"
  9. #include "hal/adc_hal_common.h"
  10. #include "hal/adc_ll.h"
  11. #include "hal/assert.h"
  12. /*---------------------------------------------------------------
  13. Controller Setting
  14. ---------------------------------------------------------------*/
  15. static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
  16. {
  17. if (unit == ADC_UNIT_1) {
  18. switch (work_mode) {
  19. #if SOC_ULP_SUPPORTED
  20. case ADC_HAL_ULP_FSM_MODE:
  21. return ADC_LL_CTRL_ULP;
  22. #endif
  23. case ADC_HAL_SINGLE_READ_MODE:
  24. #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
  25. return ADC_LL_CTRL_DIG;
  26. #elif SOC_ADC_RTC_CTRL_SUPPORTED
  27. return ADC_LL_CTRL_RTC;
  28. #endif
  29. case ADC_HAL_CONTINUOUS_READ_MODE:
  30. return ADC_LL_CTRL_DIG;
  31. default:
  32. abort();
  33. }
  34. } else {
  35. switch (work_mode) {
  36. #if SOC_ULP_SUPPORTED
  37. case ADC_HAL_ULP_FSM_MODE:
  38. return ADC_LL_CTRL_ULP;
  39. #endif
  40. #if !SOC_ADC_ARBITER_SUPPORTED //No ADC2 arbiter on ESP32
  41. #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
  42. default:
  43. return ADC_LL_CTRL_DIG;
  44. #else
  45. case ADC_HAL_SINGLE_READ_MODE:
  46. return ADC_LL_CTRL_RTC;
  47. case ADC_HAL_CONTINUOUS_READ_MODE:
  48. return ADC_LL_CTRL_DIG;
  49. case ADC_HAL_PWDET_MODE:
  50. return ADC_LL_CTRL_PWDET;
  51. default:
  52. abort();
  53. #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
  54. #else
  55. default:
  56. return ADC_LL_CTRL_ARB;
  57. #endif
  58. }
  59. }
  60. }
  61. void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
  62. {
  63. adc_ll_controller_t ctrlr = get_controller(unit, work_mode);
  64. adc_ll_set_controller(unit, ctrlr);
  65. }
  66. /*---------------------------------------------------------------
  67. Arbiter
  68. ---------------------------------------------------------------*/
  69. #if SOC_ADC_ARBITER_SUPPORTED
  70. void adc_hal_arbiter_config(adc_arbiter_t *config)
  71. {
  72. adc_ll_set_arbiter_work_mode(config->mode);
  73. adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
  74. }
  75. #endif // #if SOC_ADC_ARBITER_SUPPORTED
  76. /*---------------------------------------------------------------
  77. ADC calibration setting
  78. ---------------------------------------------------------------*/
  79. #if SOC_ADC_CALIBRATION_V1_SUPPORTED
  80. //For chips without RTC controller, Digital controller is used to trigger an ADC single read.
  81. #include "esp_rom_sys.h"
  82. void adc_hal_calibration_init(adc_unit_t adc_n)
  83. {
  84. adc_ll_calibration_init(adc_n);
  85. }
  86. static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {-1, -1};
  87. void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param)
  88. {
  89. if (param != s_previous_init_code[adc_n]) {
  90. adc_ll_set_calibration_param(adc_n, param);
  91. s_previous_init_code[adc_n] = param;
  92. }
  93. }
  94. static void cal_setup(adc_unit_t adc_n, adc_atten_t atten)
  95. {
  96. adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE);
  97. adc_oneshot_ll_disable_all_unit();
  98. // Enableinternal connect GND (for calibration).
  99. adc_oneshot_ll_disable_channel(adc_n);
  100. /**
  101. * Note:
  102. * When controlled by RTC controller, when all channels are disabled, HW auto selects channel0 atten param.
  103. * When controlled by DIG controller, unit and channel are not related to attenuation
  104. */
  105. adc_oneshot_ll_set_atten(adc_n, 0, atten);
  106. adc_oneshot_ll_enable(adc_n);
  107. }
  108. static uint32_t read_cal_channel(adc_unit_t adc_n)
  109. {
  110. uint32_t event = (adc_n == ADC_UNIT_1) ? ADC_LL_EVENT_ADC1_ONESHOT_DONE : ADC_LL_EVENT_ADC2_ONESHOT_DONE;
  111. adc_oneshot_ll_clear_event(event);
  112. #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
  113. adc_oneshot_ll_start(false);
  114. esp_rom_delay_us(5);
  115. adc_oneshot_ll_start(true);
  116. #else
  117. adc_oneshot_ll_start(adc_n);
  118. #endif
  119. while(!adc_oneshot_ll_get_event(event));
  120. uint32_t read_val = -1;
  121. read_val = adc_oneshot_ll_get_raw_result(adc_n);
  122. if (adc_oneshot_ll_raw_check_valid(adc_n, read_val) == false) {
  123. return -1;
  124. }
  125. return read_val;
  126. }
  127. #define ADC_HAL_CAL_TIMES (10)
  128. #define ADC_HAL_CAL_OFFSET_RANGE (4096)
  129. uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool internal_gnd)
  130. {
  131. if (adc_n == ADC_UNIT_2) {
  132. adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
  133. adc_hal_arbiter_config(&config);
  134. }
  135. cal_setup(adc_n, atten);
  136. adc_ll_calibration_prepare(adc_n, internal_gnd);
  137. uint32_t code_list[ADC_HAL_CAL_TIMES] = {0};
  138. uint32_t code_sum = 0;
  139. uint32_t code_h = 0;
  140. uint32_t code_l = 0;
  141. uint32_t chk_code = 0;
  142. for (uint8_t rpt = 0 ; rpt < ADC_HAL_CAL_TIMES ; rpt ++) {
  143. code_h = ADC_HAL_CAL_OFFSET_RANGE;
  144. code_l = 0;
  145. chk_code = (code_h + code_l) / 2;
  146. adc_ll_set_calibration_param(adc_n, chk_code);
  147. uint32_t self_cal = read_cal_channel(adc_n);
  148. while (code_h - code_l > 1) {
  149. if (self_cal == 0) {
  150. code_h = chk_code;
  151. } else {
  152. code_l = chk_code;
  153. }
  154. chk_code = (code_h + code_l) / 2;
  155. adc_ll_set_calibration_param(adc_n, chk_code);
  156. self_cal = read_cal_channel(adc_n);
  157. if ((code_h - code_l == 1)) {
  158. chk_code += 1;
  159. adc_ll_set_calibration_param(adc_n, chk_code);
  160. self_cal = read_cal_channel(adc_n);
  161. }
  162. }
  163. code_list[rpt] = chk_code;
  164. code_sum += chk_code;
  165. }
  166. code_l = code_list[0];
  167. code_h = code_list[0];
  168. for (uint8_t i = 0 ; i < ADC_HAL_CAL_TIMES ; i++) {
  169. code_l = MIN(code_l, code_list[i]);
  170. code_h = MAX(code_h, code_list[i]);
  171. }
  172. chk_code = code_h + code_l;
  173. uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
  174. ? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
  175. : (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
  176. adc_ll_calibration_finish(adc_n);
  177. return ret;
  178. return 0;
  179. }
  180. #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED