cache_hal.c 3.1 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <sys/param.h>
  7. #include <stdint.h>
  8. #include "sdkconfig.h"
  9. #include "esp_err.h"
  10. #include "esp_attr.h"
  11. #include "hal/assert.h"
  12. #include "hal/cache_hal.h"
  13. #include "hal/cache_types.h"
  14. #include "hal/cache_ll.h"
  15. #include "soc/soc_caps.h"
  16. #if CONFIG_IDF_TARGET_ESP32S2
  17. #include "esp32s2/rom/cache.h"
  18. #elif CONFIG_IDF_TARGET_ESP32S3
  19. #include "esp32s3/rom/cache.h"
  20. #elif CONFIG_IDF_TARGET_ESP32C3
  21. #include "esp32c3/rom/cache.h"
  22. #elif CONFIG_IDF_TARGET_ESP32C2
  23. #include "esp32c2/rom/cache.h"
  24. #elif CONFIG_IDF_TARGET_ESP32H2
  25. #include "esp32h2/rom/cache.h"
  26. #endif
  27. /*------------------------------------------------------------------------------
  28. * Unified Cache Control
  29. * See cache_hal.h for more info about these HAL APIs
  30. * This file is in internal RAM.
  31. * Now this file doesn't compile on ESP32
  32. *----------------------------------------------------------------------------*/
  33. /**
  34. * To know if autoload is enabled or not.
  35. *
  36. * We should have a unified flag for this aim, then we don't need to call following 2 functions
  37. * to know the flag.
  38. *
  39. * Suggest ROM keeping this flag value to BIT(2). Then we can replace following lines to:
  40. * #define DATA_AUTOLOAD_FLAG BIT(2)
  41. * #define INST_AUTOLOAD_FLAG BIT(2)
  42. */
  43. #define DATA_AUTOLOAD_FLAG Cache_Disable_DCache()
  44. #define INST_AUTOLOAD_FLAG Cache_Disable_ICache()
  45. /**
  46. * Necessary hal contexts, could be maintained by upper layer in the future
  47. */
  48. typedef struct {
  49. uint32_t data_autoload_flag;
  50. uint32_t inst_autoload_flag;
  51. } cache_hal_context_t;
  52. static cache_hal_context_t ctx;
  53. void cache_hal_init(void)
  54. {
  55. #if SOC_SHARED_IDCACHE_SUPPORTED
  56. ctx.data_autoload_flag = INST_AUTOLOAD_FLAG;
  57. Cache_Enable_ICache(ctx.data_autoload_flag);
  58. #else
  59. ctx.data_autoload_flag = DATA_AUTOLOAD_FLAG;
  60. Cache_Enable_DCache(ctx.data_autoload_flag);
  61. ctx.inst_autoload_flag = INST_AUTOLOAD_FLAG;
  62. Cache_Enable_ICache(ctx.inst_autoload_flag);
  63. #endif
  64. cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
  65. cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
  66. #if !CONFIG_FREERTOS_UNICORE
  67. cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
  68. cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
  69. #endif
  70. }
  71. void cache_hal_disable(cache_type_t type)
  72. {
  73. #if SOC_SHARED_IDCACHE_SUPPORTED
  74. Cache_Disable_ICache();
  75. #else
  76. if (type == CACHE_TYPE_DATA) {
  77. Cache_Disable_DCache();
  78. } else if (type == CACHE_TYPE_INSTRUCTION) {
  79. Cache_Disable_ICache();
  80. } else {
  81. Cache_Disable_ICache();
  82. Cache_Disable_DCache();
  83. }
  84. #endif
  85. }
  86. void cache_hal_enable(cache_type_t type)
  87. {
  88. #if SOC_SHARED_IDCACHE_SUPPORTED
  89. Cache_Enable_ICache(ctx.inst_autoload_flag);
  90. #else
  91. if (type == CACHE_TYPE_DATA) {
  92. Cache_Enable_DCache(ctx.data_autoload_flag);
  93. } else if (type == CACHE_TYPE_INSTRUCTION) {
  94. Cache_Enable_ICache(ctx.inst_autoload_flag);
  95. } else {
  96. Cache_Enable_ICache(ctx.inst_autoload_flag);
  97. Cache_Enable_DCache(ctx.data_autoload_flag);
  98. }
  99. #endif
  100. }