efuse_hal.c 2.0 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "sdkconfig.h"
  7. #include <sys/param.h>
  8. #include "soc/soc_caps.h"
  9. #include "hal/assert.h"
  10. #include "hal/efuse_hal.h"
  11. #include "hal/efuse_ll.h"
  12. #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
  13. uint32_t efuse_hal_get_major_chip_version(void)
  14. {
  15. return efuse_ll_get_chip_wafer_version_major();
  16. }
  17. uint32_t efuse_hal_get_minor_chip_version(void)
  18. {
  19. return efuse_ll_get_chip_wafer_version_minor();
  20. }
  21. /******************* eFuse control functions *************************/
  22. void efuse_hal_set_timing(uint32_t apb_freq_hz)
  23. {
  24. (void) apb_freq_hz;
  25. efuse_ll_set_pwr_off_num(0x190);
  26. }
  27. void efuse_hal_read(void)
  28. {
  29. efuse_hal_set_timing(0);
  30. efuse_ll_set_conf_read_op_code();
  31. efuse_ll_set_read_cmd();
  32. while (efuse_ll_get_read_cmd() != 0) { }
  33. /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
  34. while (efuse_ll_get_read_cmd() != 0) { }
  35. }
  36. void efuse_hal_clear_program_registers(void)
  37. {
  38. ets_efuse_clear_program_registers();
  39. }
  40. void efuse_hal_program(uint32_t block)
  41. {
  42. efuse_hal_set_timing(0);
  43. efuse_ll_set_conf_write_op_code();
  44. efuse_ll_set_pgm_cmd(block);
  45. while (efuse_ll_get_pgm_cmd() != 0) { }
  46. efuse_hal_clear_program_registers();
  47. efuse_hal_read();
  48. }
  49. void efuse_hal_rs_calculate(const void *data, void *rs_values)
  50. {
  51. ets_efuse_rs_calculate(data, rs_values);
  52. }
  53. /******************* eFuse control functions *************************/
  54. bool efuse_hal_is_coding_error_in_block(unsigned block)
  55. {
  56. if (block == 0) {
  57. return REG_READ(EFUSE_RD_REPEAT_ERR_REG) != 0;
  58. } else if (block <= 3) {
  59. // EFUSE_RD_RS_ERR_REG: (hi) ----, ----, ----, ----, ----, BLOCK3, BLOCK2, BLOCK1 (low)
  60. uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR_REG);
  61. return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0;
  62. }
  63. return false;
  64. }