usb_reg.h 381 KB

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  1. // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #pragma once
  15. #include <stdint.h>
  16. #include "soc/soc.h"
  17. #ifdef __cplusplus
  18. extern "C" {
  19. #endif
  20. /** Control/Status registers */
  21. /** USB_GOTGCTL_REG register
  22. * OTG Control and Status Register
  23. */
  24. #define USB_GOTGCTL_REG (SOC_DPORT_USB_BASE + 0x0)
  25. /** USB_SESREQSCS : RO; bitpos: [0]; default: 0;
  26. * Session Request Success.The core sets this bit when a session request initiation is
  27. * successful
  28. */
  29. #define USB_SESREQSCS (BIT(0))
  30. #define USB_SESREQSCS_M (USB_SESREQSCS_V << USB_SESREQSCS_S)
  31. #define USB_SESREQSCS_V 0x00000001
  32. #define USB_SESREQSCS_S 0
  33. /** USB_SESREQ : R/W; bitpos: [1]; default: 0;
  34. * Session Request.The application sets this bit to initiate a session request on the
  35. * USB. The application can clear this bit by writing a 0 when the Host Negotiation
  36. * Success Status Change bit in the OTG Interrupt register
  37. * (GOTGINT_REG.USB_HSTNEGSUCSTSCHNG) is SET. The core clears this bit when the
  38. * USB_HSTNEGSUCSTSCHNG bit is cleared
  39. */
  40. #define USB_SESREQ (BIT(1))
  41. #define USB_SESREQ_M (USB_SESREQ_V << USB_SESREQ_S)
  42. #define USB_SESREQ_V 0x00000001
  43. #define USB_SESREQ_S 1
  44. /** USB_VBVALIDOVEN : R/W; bitpos: [2]; default: 0;
  45. * VBUS Valid Override Enable
  46. * 1'b1 : Internally Bvalid received from the PHY is overridden with
  47. * GOTGCTL_REG.REG_VBVALIDOVVAl
  48. * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is
  49. * used internally by the controller
  50. */
  51. #define USB_VBVALIDOVEN (BIT(2))
  52. #define USB_VBVALIDOVEN_M (USB_VBVALIDOVEN_V << USB_VBVALIDOVEN_S)
  53. #define USB_VBVALIDOVEN_V 0x00000001
  54. #define USB_VBVALIDOVEN_S 2
  55. /** USB_VBVALIDOVVAL : R/W; bitpos: [3]; default: 0;
  56. * VBUS Valid OverrideValue
  57. * 1'b0 : vbusvalid value is 1'b0 when GOTGCTL_REG.USB_VBVALIDOVEN =1
  58. * 1'b1 : vbusvalid value is 1'b1 when GOTGCTL_REG.USB_VBVALIDOVEN =1
  59. */
  60. #define USB_VBVALIDOVVAL (BIT(3))
  61. #define USB_VBVALIDOVVAL_M (USB_VBVALIDOVVAL_V << USB_VBVALIDOVVAL_S)
  62. #define USB_VBVALIDOVVAL_V 0x00000001
  63. #define USB_VBVALIDOVVAL_S 3
  64. /** USB_AVALIDOVEN : R/W; bitpos: [4]; default: 0;
  65. * This bit is used to enable/disable the software to override the Avalid signal using
  66. * the GOTGCTL.AVALIDOVVAL
  67. * 1'b1: Internally Avalid received from the PHY is overridden with
  68. * GOTGCTL_REG.REG_AVALIDOVVAL
  69. * 1'b0: Override is disabled and avalid signal from the respective PHY selected is
  70. * used internally by the core
  71. */
  72. #define USB_AVALIDOVEN (BIT(4))
  73. #define USB_AVALIDOVEN_M (USB_AVALIDOVEN_V << USB_AVALIDOVEN_S)
  74. #define USB_AVALIDOVEN_V 0x00000001
  75. #define USB_AVALIDOVEN_S 4
  76. /** USB_AVALIDOVVAL : R/W; bitpos: [5]; default: 0;
  77. * A-Peripheral Session Valid OverrideValue
  78. * 1'b0 : Avalid value is 1'b0 when GOTGCTL_REG.USB_AVALIDOVEN =1
  79. * 1'b1 : Avalid value is 1'b1 when GOTGCTL_REG.USB_AVALIDOVEN =1
  80. */
  81. #define USB_AVALIDOVVAL (BIT(5))
  82. #define USB_AVALIDOVVAL_M (USB_AVALIDOVVAL_V << USB_AVALIDOVVAL_S)
  83. #define USB_AVALIDOVVAL_V 0x00000001
  84. #define USB_AVALIDOVVAL_S 5
  85. /** USB_BVALIDOVEN : R/W; bitpos: [6]; default: 0;
  86. * This bit is used to enable/disable the software to override the Bvalid signal using
  87. * the GOTGCTLREG.BVALIDOVVAL
  88. * 1'b1 : Internally Bvalid received from the PHY is overridden with
  89. * GOTGCTL_REG.USB_BVALIDOVVAL
  90. * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is
  91. * used internally by the force
  92. */
  93. #define USB_BVALIDOVEN (BIT(6))
  94. #define USB_BVALIDOVEN_M (USB_BVALIDOVEN_V << USB_BVALIDOVEN_S)
  95. #define USB_BVALIDOVEN_V 0x00000001
  96. #define USB_BVALIDOVEN_S 6
  97. /** USB_BVALIDOVVAL : R/W; bitpos: [7]; default: 0;
  98. * B-Peripheral Session Valid OverrideValue
  99. * 1'b0 : Bvalid value is 1'b0 when GOTGCTL_REG.USB_BVALIDOVEN =1
  100. * 1'b1 : Bvalid value is 1'b1 when GOTGCTL_REG.USB_BVALIDOVEN =1
  101. */
  102. #define USB_BVALIDOVVAL (BIT(7))
  103. #define USB_BVALIDOVVAL_M (USB_BVALIDOVVAL_V << USB_BVALIDOVVAL_S)
  104. #define USB_BVALIDOVVAL_V 0x00000001
  105. #define USB_BVALIDOVVAL_S 7
  106. /** USB_HSTNEGSCS : RO; bitpos: [8]; default: 0;
  107. * Host Negotiation Success.The controller sets this bit when host negotiation is
  108. * successful. The controller clears this bit when the HNP Request (HNPReq) bit in
  109. * this register is set.
  110. */
  111. #define USB_HSTNEGSCS (BIT(8))
  112. #define USB_HSTNEGSCS_M (USB_HSTNEGSCS_V << USB_HSTNEGSCS_S)
  113. #define USB_HSTNEGSCS_V 0x00000001
  114. #define USB_HSTNEGSCS_S 8
  115. /** USB_HNPREQ : R/W; bitpos: [9]; default: 0;
  116. * HNP Request .The application sets this bit to initiate an HNP request to the
  117. * Connected USB host. The application can clear this bit by writing a 0 when the Host
  118. * Negotiation Success Status Change bit in the OTG Interrupt register
  119. * (GOTGINT_REG.HSTNEGSUCSTSCHNG) is SET. The controller clears this bit when the
  120. * HSTNEGSUCSTSCHNG bit is cleared.
  121. */
  122. #define USB_HNPREQ (BIT(9))
  123. #define USB_HNPREQ_M (USB_HNPREQ_V << USB_HNPREQ_S)
  124. #define USB_HNPREQ_V 0x00000001
  125. #define USB_HNPREQ_S 9
  126. /** USB_HSTSETHNPEN : R/W; bitpos: [10]; default: 0;
  127. * Host Set HNP Enable.The application sets this bit when it has successfully enabled
  128. * HNP (using the SetFeature.SetHNPEnable command) on the connected device
  129. * 1'b0: Host Set HNP is not enabled
  130. * 1'b1: Host Set HNP is enabled
  131. */
  132. #define USB_HSTSETHNPEN (BIT(10))
  133. #define USB_HSTSETHNPEN_M (USB_HSTSETHNPEN_V << USB_HSTSETHNPEN_S)
  134. #define USB_HSTSETHNPEN_V 0x00000001
  135. #define USB_HSTSETHNPEN_S 10
  136. /** USB_DEVHNPEN : R/W; bitpos: [11]; default: 0;
  137. * Device HNP Enabled.The application sets this bit when it successfully receives a
  138. * SetFeature.SetHNPEnable command from the connected USB host
  139. * 1'b0: HNP is not enabled in the application
  140. * 1'b1: HNP is enabled in the application
  141. */
  142. #define USB_DEVHNPEN (BIT(11))
  143. #define USB_DEVHNPEN_M (USB_DEVHNPEN_V << USB_DEVHNPEN_S)
  144. #define USB_DEVHNPEN_V 0x00000001
  145. #define USB_DEVHNPEN_S 11
  146. /** USB_EHEN : R/W; bitpos: [12]; default: 0;
  147. * Embedded Host Enable.It is used to select between OTG A Device state Machine and
  148. * Embedded Host state machine
  149. * 1'b0: OTG A Device state machine is selected
  150. * 1'b1: Embedded Host State Machine is selected
  151. */
  152. #define USB_EHEN (BIT(12))
  153. #define USB_EHEN_M (USB_EHEN_V << USB_EHEN_S)
  154. #define USB_EHEN_V 0x00000001
  155. #define USB_EHEN_S 12
  156. /** USB_DBNCEFLTRBYPASS : R/W; bitpos: [15]; default: 0;
  157. * Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when
  158. * enabled
  159. * 1'b0: Disabled
  160. * 1'b1: Enabled
  161. */
  162. #define USB_DBNCEFLTRBYPASS (BIT(15))
  163. #define USB_DBNCEFLTRBYPASS_M (USB_DBNCEFLTRBYPASS_V << USB_DBNCEFLTRBYPASS_S)
  164. #define USB_DBNCEFLTRBYPASS_V 0x00000001
  165. #define USB_DBNCEFLTRBYPASS_S 15
  166. /** USB_CONIDSTS : RO; bitpos: [16]; default: 0;
  167. * Connector ID Status. Indicates the connector ID status on a connect event
  168. * 1'b0: The core is in A-Device mode
  169. * 1'b1: The core is in B-Device mode
  170. */
  171. #define USB_CONIDSTS (BIT(16))
  172. #define USB_CONIDSTS_M (USB_CONIDSTS_V << USB_CONIDSTS_S)
  173. #define USB_CONIDSTS_V 0x00000001
  174. #define USB_CONIDSTS_S 16
  175. /** USB_DBNCTIME : RO; bitpos: [17]; default: 0;
  176. * Long/Short Debounce Time. Indicates the debounce time of a detected connection
  177. * 1'b0: Long debounce time, used for physical connections (100ms + 2.5 micro-sec)
  178. * 1'b1: Short debounce time, used for soft connections (2.5 micro-sec)
  179. */
  180. #define USB_DBNCTIME (BIT(17))
  181. #define USB_DBNCTIME_M (USB_DBNCTIME_V << USB_DBNCTIME_S)
  182. #define USB_DBNCTIME_V 0x00000001
  183. #define USB_DBNCTIME_S 17
  184. /** USB_ASESVLD : RO; bitpos: [18]; default: 0;
  185. * A-Session Valid. Indicates the Host mode transceiver status
  186. * 1'b0: A-session is not valid
  187. * 1'b1: A-session is valid
  188. */
  189. #define USB_ASESVLD (BIT(18))
  190. #define USB_ASESVLD_M (USB_ASESVLD_V << USB_ASESVLD_S)
  191. #define USB_ASESVLD_V 0x00000001
  192. #define USB_ASESVLD_S 18
  193. /** USB_BSESVLD : RO; bitpos: [19]; default: 0;
  194. * B-Session Valid.Indicates the Device mode transceiver status
  195. * 1'b0: B-session is not valid
  196. * 1'b1: B-session is valid
  197. */
  198. #define USB_BSESVLD (BIT(19))
  199. #define USB_BSESVLD_M (USB_BSESVLD_V << USB_BSESVLD_S)
  200. #define USB_BSESVLD_V 0x00000001
  201. #define USB_BSESVLD_S 19
  202. /** USB_OTGVER : R/W; bitpos: [20]; default: 0;
  203. * OTG Version
  204. * 1'b0:Supports OTG Version 1.3
  205. * 1'b1:Supports OTG Version 2.0
  206. */
  207. #define USB_OTGVER (BIT(20))
  208. #define USB_OTGVER_M (USB_OTGVER_V << USB_OTGVER_S)
  209. #define USB_OTGVER_V 0x00000001
  210. #define USB_OTGVER_S 20
  211. /** USB_CURMOD : RO; bitpos: [21]; default: 0;
  212. * Current Mode of Operation
  213. * 1'b0: Device mode
  214. * 1'b1:Host mode
  215. */
  216. #define USB_CURMOD (BIT(21))
  217. #define USB_CURMOD_M (USB_CURMOD_V << USB_CURMOD_S)
  218. #define USB_CURMOD_V 0x00000001
  219. #define USB_CURMOD_S 21
  220. /** USB_GDFIFOCFG_REG register
  221. * Global DFIFO Configuration Register
  222. */
  223. #define USB_GDFIFOCFG_REG (SOC_DPORT_USB_BASE + 0x5c)
  224. /** USB_GDFIFOCFG : R/W; bitpos: [16:0]; default: 0;
  225. * GDFIFOCfg
  226. */
  227. #define USB_GDFIFOCFG 0x0000FFFF
  228. #define USB_GDFIFOCFG_M (USB_GDFIFOCFG_V << USB_GDFIFOCFG_S)
  229. #define USB_GDFIFOCFG_V 0x0000FFFF
  230. #define USB_GDFIFOCFG_S 0
  231. /** USB_EPINFOBASEADDR : R/W; bitpos: [32:16]; default: 0;
  232. * EPInfoBaseAddr
  233. */
  234. #define USB_EPINFOBASEADDR 0x0000FFFF
  235. #define USB_EPINFOBASEADDR_M (USB_EPINFOBASEADDR_V << USB_EPINFOBASEADDR_S)
  236. #define USB_EPINFOBASEADDR_V 0x0000FFFF
  237. #define USB_EPINFOBASEADDR_S 16
  238. /** USB_HPTXFSIZ_REG register
  239. * Host Periodic Transmit FIFO Size Register
  240. */
  241. #define USB_HPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x100)
  242. /** USB_PTXFSTADDR : R/W; bitpos: [16:0]; default: 512;
  243. * Host Periodic TxFIFO Start Address.
  244. */
  245. #define USB_PTXFSTADDR 0x0000FFFF
  246. #define USB_PTXFSTADDR_M (USB_PTXFSTADDR_V << USB_PTXFSTADDR_S)
  247. #define USB_PTXFSTADDR_V 0x0000FFFF
  248. #define USB_PTXFSTADDR_S 0
  249. /** USB_PTXFSIZE : R/W; bitpos: [32:16]; default: 4096;
  250. * Host Periodic TxFIFO Depth,This value is in terms of 32-bit words..
  251. */
  252. #define USB_PTXFSIZE 0x0000FFFF
  253. #define USB_PTXFSIZE_M (USB_PTXFSIZE_V << USB_PTXFSIZE_S)
  254. #define USB_PTXFSIZE_V 0x0000FFFF
  255. #define USB_PTXFSIZE_S 16
  256. /** USB_DIEPTXF1_REG register
  257. * Device IN Endpoint Transmit FIFO Size Register
  258. */
  259. #define USB_DIEPTXF1_REG (SOC_DPORT_USB_BASE + 0x104)
  260. /** USB_INEP1TXFSTADDR : R/W; bitpos: [16:0]; default: 512;
  261. * IN Endpoint FIFOn Transmit RAM Start Address.
  262. */
  263. #define USB_INEP1TXFSTADDR 0x0000FFFF
  264. #define USB_INEP1TXFSTADDR_M (USB_INEP1TXFSTADDR_V << USB_INEP1TXFSTADDR_S)
  265. #define USB_INEP1TXFSTADDR_V 0x0000FFFF
  266. #define USB_INEP1TXFSTADDR_S 0
  267. /** USB_INEP1TXFDEP : R/W; bitpos: [32:16]; default: 4096;
  268. * IN Endpoint TxFIFO Depth
  269. */
  270. #define USB_INEP1TXFDEP 0x0000FFFF
  271. #define USB_INEP1TXFDEP_M (USB_INEP1TXFDEP_V << USB_INEP1TXFDEP_S)
  272. #define USB_INEP1TXFDEP_V 0x0000FFFF
  273. #define USB_INEP1TXFDEP_S 16
  274. /** USB_DIEPTXF2_REG register
  275. * Device IN Endpoint Transmit FIFO Size Register
  276. */
  277. #define USB_DIEPTXF2_REG (SOC_DPORT_USB_BASE + 0x108)
  278. /** USB_INEP2TXFSTADDR : R/W; bitpos: [16:0]; default: 512;
  279. * IN Endpoint FIFOn Transmit RAM Start Address.
  280. */
  281. #define USB_INEP2TXFSTADDR 0x0000FFFF
  282. #define USB_INEP2TXFSTADDR_M (USB_INEP2TXFSTADDR_V << USB_INEP2TXFSTADDR_S)
  283. #define USB_INEP2TXFSTADDR_V 0x0000FFFF
  284. #define USB_INEP2TXFSTADDR_S 0
  285. /** USB_INEP2TXFDEP : R/W; bitpos: [32:16]; default: 4096;
  286. * IN Endpoint TxFIFO Depth
  287. */
  288. #define USB_INEP2TXFDEP 0x0000FFFF
  289. #define USB_INEP2TXFDEP_M (USB_INEP2TXFDEP_V << USB_INEP2TXFDEP_S)
  290. #define USB_INEP2TXFDEP_V 0x0000FFFF
  291. #define USB_INEP2TXFDEP_S 16
  292. /** USB_DIEPTXF3_REG register
  293. * Device IN Endpoint Transmit FIFO Size Register
  294. */
  295. #define USB_DIEPTXF3_REG (SOC_DPORT_USB_BASE + 0x10c)
  296. /** USB_INEP3TXFSTADDR : R/W; bitpos: [16:0]; default: 512;
  297. * IN Endpoint FIFOn Transmit RAM Start Address.
  298. */
  299. #define USB_INEP3TXFSTADDR 0x0000FFFF
  300. #define USB_INEP3TXFSTADDR_M (USB_INEP3TXFSTADDR_V << USB_INEP3TXFSTADDR_S)
  301. #define USB_INEP3TXFSTADDR_V 0x0000FFFF
  302. #define USB_INEP3TXFSTADDR_S 0
  303. /** USB_INEP3TXFDEP : R/W; bitpos: [32:16]; default: 4096;
  304. * IN Endpoint TxFIFO Depth
  305. */
  306. #define USB_INEP3TXFDEP 0x0000FFFF
  307. #define USB_INEP3TXFDEP_M (USB_INEP3TXFDEP_V << USB_INEP3TXFDEP_S)
  308. #define USB_INEP3TXFDEP_V 0x0000FFFF
  309. #define USB_INEP3TXFDEP_S 16
  310. /** USB_DIEPTXF4_REG register
  311. * Device IN Endpoint Transmit FIFO Size Register
  312. */
  313. #define USB_DIEPTXF4_REG (SOC_DPORT_USB_BASE + 0x110)
  314. /** USB_INEP4TXFSTADDR : R/W; bitpos: [16:0]; default: 512;
  315. * IN Endpoint FIFOn Transmit RAM Start Address.
  316. */
  317. #define USB_INEP4TXFSTADDR 0x0000FFFF
  318. #define USB_INEP4TXFSTADDR_M (USB_INEP4TXFSTADDR_V << USB_INEP4TXFSTADDR_S)
  319. #define USB_INEP4TXFSTADDR_V 0x0000FFFF
  320. #define USB_INEP4TXFSTADDR_S 0
  321. /** USB_INEP4TXFDEP : R/W; bitpos: [32:16]; default: 4096;
  322. * IN Endpoint TxFIFO Depth
  323. */
  324. #define USB_INEP4TXFDEP 0x0000FFFF
  325. #define USB_INEP4TXFDEP_M (USB_INEP4TXFDEP_V << USB_INEP4TXFDEP_S)
  326. #define USB_INEP4TXFDEP_V 0x0000FFFF
  327. #define USB_INEP4TXFDEP_S 16
  328. /** USB_HCFG_REG register
  329. * Host Configuration Register
  330. */
  331. #define USB_HCFG_REG (SOC_DPORT_USB_BASE + 0x400)
  332. /** USB_H_FSLSPCLKSEL : R/W; bitpos: [2:0]; default: 0;
  333. * 0x0 : PHY clock is running at 30/60 MHz
  334. * 0x1 : PHY clock is running at 48 MHz
  335. * 0x2 : PHY clock is running at 6 MHz
  336. */
  337. #define USB_H_FSLSPCLKSEL 0x00000003
  338. #define USB_H_FSLSPCLKSEL_M (USB_H_FSLSPCLKSEL_V << USB_H_FSLSPCLKSEL_S)
  339. #define USB_H_FSLSPCLKSEL_V 0x00000003
  340. #define USB_H_FSLSPCLKSEL_S 0
  341. /** USB_H_FSLSSUPP : R/W; bitpos: [2]; default: 0;
  342. * FS- and LS-Only Support
  343. * 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device
  344. * 1'b1: FS/LS-only, even If the connected device can support HS
  345. */
  346. #define USB_H_FSLSSUPP (BIT(2))
  347. #define USB_H_FSLSSUPP_M (USB_H_FSLSSUPP_V << USB_H_FSLSSUPP_S)
  348. #define USB_H_FSLSSUPP_V 0x00000001
  349. #define USB_H_FSLSSUPP_S 2
  350. /** USB_H_ENA32KHZS : R/W; bitpos: [7]; default: 0;
  351. * 1'b0:32 KHz Suspend mode disabled
  352. * 1'b1:32 KHz Suspend mode enabled
  353. */
  354. #define USB_H_ENA32KHZS (BIT(7))
  355. #define USB_H_ENA32KHZS_M (USB_H_ENA32KHZS_V << USB_H_ENA32KHZS_S)
  356. #define USB_H_ENA32KHZS_V 0x00000001
  357. #define USB_H_ENA32KHZS_S 7
  358. /** USB_H_DESCDMA : R/W; bitpos: [23]; default: 0;
  359. * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=0 => Slave mode
  360. * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=1 => Invalid
  361. * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=0 => Buffered DMA
  362. * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=1 => Scatter/Gather DMA mode
  363. */
  364. #define USB_H_DESCDMA (BIT(23))
  365. #define USB_H_DESCDMA_M (USB_H_DESCDMA_V << USB_H_DESCDMA_S)
  366. #define USB_H_DESCDMA_V 0x00000001
  367. #define USB_H_DESCDMA_S 23
  368. /** USB_H_FRLISTEN : R/W; bitpos: [26:24]; default: 0;
  369. * Frame List Entries
  370. * 2'b00: 8 Entries
  371. * 2'b01: 16 Entries
  372. * 2'b10: 32 Entries
  373. * 2'b11: 64 Entries
  374. */
  375. #define USB_H_FRLISTEN 0x00000003
  376. #define USB_H_FRLISTEN_M (USB_H_FRLISTEN_V << USB_H_FRLISTEN_S)
  377. #define USB_H_FRLISTEN_V 0x00000003
  378. #define USB_H_FRLISTEN_S 24
  379. /** USB_H_PERSCHEDENA : R/W; bitpos: [26]; default: 0;
  380. * 0x0 (DISABLED): Disables periodic scheduling within the core
  381. * 0x1 (ENABLED): Enables periodic scheduling within the core
  382. */
  383. #define USB_H_PERSCHEDENA (BIT(26))
  384. #define USB_H_PERSCHEDENA_M (USB_H_PERSCHEDENA_V << USB_H_PERSCHEDENA_S)
  385. #define USB_H_PERSCHEDENA_V 0x00000001
  386. #define USB_H_PERSCHEDENA_S 26
  387. /** USB_H_MODECHTIMEN : R/W; bitpos: [31]; default: 0;
  388. * Mode Change Ready Timer Enable,
  389. * 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at
  390. * the end of resume to the change the opmode from 2'b10 to 2'b00.
  391. * 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to
  392. * change the opmode from 2'b10 to 2'b00.
  393. */
  394. #define USB_H_MODECHTIMEN (BIT(31))
  395. #define USB_H_MODECHTIMEN_M (USB_H_MODECHTIMEN_V << USB_H_MODECHTIMEN_S)
  396. #define USB_H_MODECHTIMEN_V 0x00000001
  397. #define USB_H_MODECHTIMEN_S 31
  398. /** USB_HFIR_REG register
  399. * Host Frame Interval Register
  400. */
  401. #define USB_HFIR_REG (SOC_DPORT_USB_BASE + 0x404)
  402. /** USB_FRINT : R/W; bitpos: [16:0]; default: 6103;
  403. * Frame Interval . 1 ms * (PHY clock frequency for FS/LS)
  404. */
  405. #define USB_FRINT 0x0000FFFF
  406. #define USB_FRINT_M (USB_FRINT_V << USB_FRINT_S)
  407. #define USB_FRINT_V 0x0000FFFF
  408. #define USB_FRINT_S 0
  409. /** USB_HFIRRLDCTRL : R/W; bitpos: [16]; default: 0;
  410. * Reload Control
  411. * 1'b0 : The HFIR cannot be reloaded dynamically
  412. * 1'b1: the HFIR can be dynamically reloaded during runtime
  413. */
  414. #define USB_HFIRRLDCTRL (BIT(16))
  415. #define USB_HFIRRLDCTRL_M (USB_HFIRRLDCTRL_V << USB_HFIRRLDCTRL_S)
  416. #define USB_HFIRRLDCTRL_V 0x00000001
  417. #define USB_HFIRRLDCTRL_S 16
  418. /** USB_HFLBADDR_REG register
  419. * Host Frame List Base Address Register
  420. */
  421. #define USB_HFLBADDR_REG (SOC_DPORT_USB_BASE + 0x41c)
  422. /** USB_HFLBADDR : R/W; bitpos: [32:0]; default: 0;
  423. * The starting address of the Frame list. This register is used only for Isochronous
  424. * and Interrupt Channels.
  425. */
  426. #define USB_HFLBADDR 0xFFFFFFFF
  427. #define USB_HFLBADDR_M (USB_HFLBADDR_V << USB_HFLBADDR_S)
  428. #define USB_HFLBADDR_V 0xFFFFFFFF
  429. #define USB_HFLBADDR_S 0
  430. /** USB_HPRT_REG register
  431. * Host Port Control and Status Register
  432. */
  433. #define USB_HPRT_REG (SOC_DPORT_USB_BASE + 0x440)
  434. /** USB_PRTCONNSTS : RO; bitpos: [0]; default: 0;
  435. * Port Connect Status
  436. * 0x0: No device is attached to the port
  437. * 0x1: A device is attached to the port
  438. */
  439. #define USB_PRTCONNSTS (BIT(0))
  440. #define USB_PRTCONNSTS_M (USB_PRTCONNSTS_V << USB_PRTCONNSTS_S)
  441. #define USB_PRTCONNSTS_V 0x00000001
  442. #define USB_PRTCONNSTS_S 0
  443. /** USB_PRTCONNDET : R/W; bitpos: [1]; default: 0;
  444. * Port Connect Detected.
  445. * 0x1 : Device connection detected.
  446. * 0x0 : No device connection detected.
  447. */
  448. #define USB_PRTCONNDET (BIT(1))
  449. #define USB_PRTCONNDET_M (USB_PRTCONNDET_V << USB_PRTCONNDET_S)
  450. #define USB_PRTCONNDET_V 0x00000001
  451. #define USB_PRTCONNDET_S 1
  452. /** USB_PRTENA : R/W; bitpos: [2]; default: 0;
  453. * Port Enable
  454. * 1'b0: Port disabled
  455. * 1'b1: Port enabled
  456. */
  457. #define USB_PRTENA (BIT(2))
  458. #define USB_PRTENA_M (USB_PRTENA_V << USB_PRTENA_S)
  459. #define USB_PRTENA_V 0x00000001
  460. #define USB_PRTENA_S 2
  461. /** USB_PRTENCHNG : R/W; bitpos: [3]; default: 0;
  462. * Port Enable/Disable Change
  463. * 0x0 : Port Enable bit 2 has not changed
  464. * 0x1 : Port Enable bit 2 changed
  465. */
  466. #define USB_PRTENCHNG (BIT(3))
  467. #define USB_PRTENCHNG_M (USB_PRTENCHNG_V << USB_PRTENCHNG_S)
  468. #define USB_PRTENCHNG_V 0x00000001
  469. #define USB_PRTENCHNG_S 3
  470. /** USB_PRTOVRCURRACT : RO; bitpos: [4]; default: 0;
  471. * Port Overcurrent Active
  472. * 1'b0: No overcurrent condition
  473. * 1'b1: Overcurrent condition
  474. */
  475. #define USB_PRTOVRCURRACT (BIT(4))
  476. #define USB_PRTOVRCURRACT_M (USB_PRTOVRCURRACT_V << USB_PRTOVRCURRACT_S)
  477. #define USB_PRTOVRCURRACT_V 0x00000001
  478. #define USB_PRTOVRCURRACT_S 4
  479. /** USB_PRTOVRCURRCHNG : R/W; bitpos: [5]; default: 0;
  480. * Port Overcurrent Change
  481. * 0x0: Status of port overcurrent status is not changed
  482. * 0x1: Status of port overcurrent changed
  483. */
  484. #define USB_PRTOVRCURRCHNG (BIT(5))
  485. #define USB_PRTOVRCURRCHNG_M (USB_PRTOVRCURRCHNG_V << USB_PRTOVRCURRCHNG_S)
  486. #define USB_PRTOVRCURRCHNG_V 0x00000001
  487. #define USB_PRTOVRCURRCHNG_S 5
  488. /** USB_PRTRES : R/W; bitpos: [6]; default: 0;
  489. * Port Resume
  490. * 1'b0: No resume driven
  491. * 1'b1: Resume driven
  492. */
  493. #define USB_PRTRES (BIT(6))
  494. #define USB_PRTRES_M (USB_PRTRES_V << USB_PRTRES_S)
  495. #define USB_PRTRES_V 0x00000001
  496. #define USB_PRTRES_S 6
  497. /** USB_PRTSUSP : R/W; bitpos: [7]; default: 0;
  498. * Port Suspend
  499. * 1'b0: Port not in Suspend mode
  500. * 1'b1: Port in Suspend mode
  501. */
  502. #define USB_PRTSUSP (BIT(7))
  503. #define USB_PRTSUSP_M (USB_PRTSUSP_V << USB_PRTSUSP_S)
  504. #define USB_PRTSUSP_V 0x00000001
  505. #define USB_PRTSUSP_S 7
  506. /** USB_PRTRST : R/W; bitpos: [8]; default: 0;
  507. * Port Reset.
  508. * 1'b0: Port not in reset
  509. * 1'b1: Port in reset
  510. */
  511. #define USB_PRTRST (BIT(8))
  512. #define USB_PRTRST_M (USB_PRTRST_V << USB_PRTRST_S)
  513. #define USB_PRTRST_V 0x00000001
  514. #define USB_PRTRST_S 8
  515. /** USB_PRTLNSTS : RO; bitpos: [12:10]; default: 0;
  516. * Port Line Status
  517. * Bit [10]: Logic level of D+
  518. * Bit [11]: Logic level of D-
  519. */
  520. #define USB_PRTLNSTS 0x00000003
  521. #define USB_PRTLNSTS_M (USB_PRTLNSTS_V << USB_PRTLNSTS_S)
  522. #define USB_PRTLNSTS_V 0x00000003
  523. #define USB_PRTLNSTS_S 10
  524. /** USB_PRTPWR : R/W; bitpos: [12]; default: 0;
  525. * Port Power
  526. * 1'b0: Power off
  527. * 1'b1: Power on
  528. */
  529. #define USB_PRTPWR (BIT(12))
  530. #define USB_PRTPWR_M (USB_PRTPWR_V << USB_PRTPWR_S)
  531. #define USB_PRTPWR_V 0x00000001
  532. #define USB_PRTPWR_S 12
  533. /** USB_PRTTSTCTL : R/W; bitpos: [17:13]; default: 0;
  534. * Port Test Control
  535. * 4'b0000: Test mode disabled
  536. * 4'b0001: Test_J mode
  537. * 4'b0010: Test_K mode
  538. * 4'b0011: Test_SE0_NAK mode
  539. * 4'b0100: Test_Packet mode
  540. * 4'b0101: Test_Force_Enable
  541. * Others: Reserved
  542. */
  543. #define USB_PRTTSTCTL 0x0000000F
  544. #define USB_PRTTSTCTL_M (USB_PRTTSTCTL_V << USB_PRTTSTCTL_S)
  545. #define USB_PRTTSTCTL_V 0x0000000F
  546. #define USB_PRTTSTCTL_S 13
  547. /** USB_PRTSPD : RO; bitpos: [19:17]; default: 0;
  548. * Port Speed
  549. * 2'b00: High speed
  550. * 2'b01: Full speed
  551. * 2'b10: Low speed
  552. * 2'b11: Reserved
  553. */
  554. #define USB_PRTSPD 0x00000003
  555. #define USB_PRTSPD_M (USB_PRTSPD_V << USB_PRTSPD_S)
  556. #define USB_PRTSPD_V 0x00000003
  557. #define USB_PRTSPD_S 17
  558. /** USB_HCCHAR0_REG register
  559. * Host Channel 0 Characteristics Register
  560. */
  561. #define USB_HCCHAR0_REG (SOC_DPORT_USB_BASE + 0x500)
  562. /** USB_H_MPS0 : R/W; bitpos: [11:0]; default: 0;
  563. * Maximum Packet Size.
  564. */
  565. #define USB_H_MPS0 0x000007FF
  566. #define USB_H_MPS0_M (USB_H_MPS0_V << USB_H_MPS0_S)
  567. #define USB_H_MPS0_V 0x000007FF
  568. #define USB_H_MPS0_S 0
  569. /** USB_H_EPNUM0 : R/W; bitpos: [15:11]; default: 0;
  570. * Endpoint Number.
  571. */
  572. #define USB_H_EPNUM0 0x0000000F
  573. #define USB_H_EPNUM0_M (USB_H_EPNUM0_V << USB_H_EPNUM0_S)
  574. #define USB_H_EPNUM0_V 0x0000000F
  575. #define USB_H_EPNUM0_S 11
  576. /** USB_H_EPDIR0 : R/W; bitpos: [15]; default: 0;
  577. * 1'b0: OUT
  578. * 1'b1: IN
  579. */
  580. #define USB_H_EPDIR0 (BIT(15))
  581. #define USB_H_EPDIR0_M (USB_H_EPDIR0_V << USB_H_EPDIR0_S)
  582. #define USB_H_EPDIR0_V 0x00000001
  583. #define USB_H_EPDIR0_S 15
  584. /** USB_H_LSPDDEV0 : R/W; bitpos: [17]; default: 0;
  585. * 0x0: Not Communicating with low speed device
  586. * 0x1: Communicating with low speed device
  587. */
  588. #define USB_H_LSPDDEV0 (BIT(17))
  589. #define USB_H_LSPDDEV0_M (USB_H_LSPDDEV0_V << USB_H_LSPDDEV0_S)
  590. #define USB_H_LSPDDEV0_V 0x00000001
  591. #define USB_H_LSPDDEV0_S 17
  592. /** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0;
  593. * 0x0 (CTRL): Contro
  594. * 0x1 (ISOC): Isochronous
  595. * 0x2 (BULK): Bulk
  596. * 0x3 (INTERR): Interrupt
  597. */
  598. #define USB_H_EPTYPE0 0x00000003
  599. #define USB_H_EPTYPE0_M (USB_H_EPTYPE0_V << USB_H_EPTYPE0_S)
  600. #define USB_H_EPTYPE0_V 0x00000003
  601. #define USB_H_EPTYPE0_S 18
  602. /** USB_H_EC0 : R/W; bitpos: [21]; default: 0;
  603. * Multi Count (MC) / Error Count(EC)
  604. * 0x0 (RESERVED): Reserved. This field yields undefined result
  605. * 0x1 (TRANSONE): 1 transaction
  606. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  607. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  608. */
  609. #define USB_H_EC0 (BIT(21))
  610. #define USB_H_EC0_M (USB_H_EC0_V << USB_H_EC0_S)
  611. #define USB_H_EC0_V 0x00000001
  612. #define USB_H_EC0_S 21
  613. /** USB_H_DEVADDR0 : R/W; bitpos: [29:22]; default: 0;
  614. * Device Address . This field selects the specific device serving as the data
  615. * source or sink.
  616. */
  617. #define USB_H_DEVADDR0 0x0000007F
  618. #define USB_H_DEVADDR0_M (USB_H_DEVADDR0_V << USB_H_DEVADDR0_S)
  619. #define USB_H_DEVADDR0_V 0x0000007F
  620. #define USB_H_DEVADDR0_S 22
  621. /** USB_H_ODDFRM0 : R/W; bitpos: [29]; default: 0;
  622. * Odd Frame
  623. * 1'b0: Even (micro)Frame
  624. * 1'b1: Odd (micro)Frame
  625. */
  626. #define USB_H_ODDFRM0 (BIT(29))
  627. #define USB_H_ODDFRM0_M (USB_H_ODDFRM0_V << USB_H_ODDFRM0_S)
  628. #define USB_H_ODDFRM0_V 0x00000001
  629. #define USB_H_ODDFRM0_S 29
  630. /** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0;
  631. * Channel Disable
  632. * 0x0 : Transmit/Recieve norma
  633. * 0x1 : Stop transmitting/receiving data on channel
  634. */
  635. #define USB_H_CHDIS0 (BIT(30))
  636. #define USB_H_CHDIS0_M (USB_H_CHDIS0_V << USB_H_CHDIS0_S)
  637. #define USB_H_CHDIS0_V 0x00000001
  638. #define USB_H_CHDIS0_S 30
  639. /** USB_H_CHENA0 : R/W; bitpos: [31]; default: 0;
  640. * Channel Enable
  641. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  642. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  643. * disabled
  644. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  645. * and data buffer with data is set up and this channel can access the descriptor. If
  646. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  647. */
  648. #define USB_H_CHENA0 (BIT(31))
  649. #define USB_H_CHENA0_M (USB_H_CHENA0_V << USB_H_CHENA0_S)
  650. #define USB_H_CHENA0_V 0x00000001
  651. #define USB_H_CHENA0_S 31
  652. /** USB_HCDMA0_REG register
  653. * Host Channel 0 DMA Address Register
  654. */
  655. #define USB_HCDMA0_REG (SOC_DPORT_USB_BASE + 0x514)
  656. /** USB_H_DMAADDR0 : R/W; bitpos: [32:0]; default: 0;
  657. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  658. * [31:9]: DMA Address
  659. * [8:3]: Current Transfer Desc
  660. * [2:0]: Reserved
  661. */
  662. #define USB_H_DMAADDR0 0xFFFFFFFF
  663. #define USB_H_DMAADDR0_M (USB_H_DMAADDR0_V << USB_H_DMAADDR0_S)
  664. #define USB_H_DMAADDR0_V 0xFFFFFFFF
  665. #define USB_H_DMAADDR0_S 0
  666. /** USB_HCCHAR1_REG register
  667. * Host Channel 1 Characteristics Register
  668. */
  669. #define USB_HCCHAR1_REG (SOC_DPORT_USB_BASE + 0x520)
  670. /** USB_H_MPS1 : R/W; bitpos: [11:0]; default: 0;
  671. * Maximum Packet Size.
  672. */
  673. #define USB_H_MPS1 0x000007FF
  674. #define USB_H_MPS1_M (USB_H_MPS1_V << USB_H_MPS1_S)
  675. #define USB_H_MPS1_V 0x000007FF
  676. #define USB_H_MPS1_S 0
  677. /** USB_H_EPNUM1 : R/W; bitpos: [15:11]; default: 0;
  678. * Endpoint Number.
  679. */
  680. #define USB_H_EPNUM1 0x0000000F
  681. #define USB_H_EPNUM1_M (USB_H_EPNUM1_V << USB_H_EPNUM1_S)
  682. #define USB_H_EPNUM1_V 0x0000000F
  683. #define USB_H_EPNUM1_S 11
  684. /** USB_H_EPDIR1 : R/W; bitpos: [15]; default: 0;
  685. * 1'b0: OUT
  686. * 1'b1: IN
  687. */
  688. #define USB_H_EPDIR1 (BIT(15))
  689. #define USB_H_EPDIR1_M (USB_H_EPDIR1_V << USB_H_EPDIR1_S)
  690. #define USB_H_EPDIR1_V 0x00000001
  691. #define USB_H_EPDIR1_S 15
  692. /** USB_H_LSPDDEV1 : R/W; bitpos: [17]; default: 0;
  693. * 0x0: Not Communicating with low speed device
  694. * 0x1: Communicating with low speed device
  695. */
  696. #define USB_H_LSPDDEV1 (BIT(17))
  697. #define USB_H_LSPDDEV1_M (USB_H_LSPDDEV1_V << USB_H_LSPDDEV1_S)
  698. #define USB_H_LSPDDEV1_V 0x00000001
  699. #define USB_H_LSPDDEV1_S 17
  700. /** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0;
  701. * 0x0 (CTRL): Contro
  702. * 0x1 (ISOC): Isochronous
  703. * 0x2 (BULK): Bulk
  704. * 0x3 (INTERR): Interrupt
  705. */
  706. #define USB_H_EPTYPE1 0x00000003
  707. #define USB_H_EPTYPE1_M (USB_H_EPTYPE1_V << USB_H_EPTYPE1_S)
  708. #define USB_H_EPTYPE1_V 0x00000003
  709. #define USB_H_EPTYPE1_S 18
  710. /** USB_H_EC1 : R/W; bitpos: [21]; default: 0;
  711. * Multi Count (MC) / Error Count(EC)
  712. * 0x0 (RESERVED): Reserved. This field yields undefined result
  713. * 0x1 (TRANSONE): 1 transaction
  714. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  715. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  716. */
  717. #define USB_H_EC1 (BIT(21))
  718. #define USB_H_EC1_M (USB_H_EC1_V << USB_H_EC1_S)
  719. #define USB_H_EC1_V 0x00000001
  720. #define USB_H_EC1_S 21
  721. /** USB_H_DEVADDR1 : R/W; bitpos: [29:22]; default: 0;
  722. * Device Address . This field selects the specific device serving as the data
  723. * source or sink.
  724. */
  725. #define USB_H_DEVADDR1 0x0000007F
  726. #define USB_H_DEVADDR1_M (USB_H_DEVADDR1_V << USB_H_DEVADDR1_S)
  727. #define USB_H_DEVADDR1_V 0x0000007F
  728. #define USB_H_DEVADDR1_S 22
  729. /** USB_H_ODDFRM1 : R/W; bitpos: [29]; default: 0;
  730. * Odd Frame
  731. * 1'b0: Even (micro)Frame
  732. * 1'b1: Odd (micro)Frame
  733. */
  734. #define USB_H_ODDFRM1 (BIT(29))
  735. #define USB_H_ODDFRM1_M (USB_H_ODDFRM1_V << USB_H_ODDFRM1_S)
  736. #define USB_H_ODDFRM1_V 0x00000001
  737. #define USB_H_ODDFRM1_S 29
  738. /** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0;
  739. * Channel Disable
  740. * 0x0 : Transmit/Recieve norma
  741. * 0x1 : Stop transmitting/receiving data on channel
  742. */
  743. #define USB_H_CHDIS1 (BIT(30))
  744. #define USB_H_CHDIS1_M (USB_H_CHDIS1_V << USB_H_CHDIS1_S)
  745. #define USB_H_CHDIS1_V 0x00000001
  746. #define USB_H_CHDIS1_S 30
  747. /** USB_H_CHENA1 : R/W; bitpos: [31]; default: 0;
  748. * Channel Enable
  749. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  750. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  751. * disabled
  752. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  753. * and data buffer with data is set up and this channel can access the descriptor. If
  754. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  755. */
  756. #define USB_H_CHENA1 (BIT(31))
  757. #define USB_H_CHENA1_M (USB_H_CHENA1_V << USB_H_CHENA1_S)
  758. #define USB_H_CHENA1_V 0x00000001
  759. #define USB_H_CHENA1_S 31
  760. /** USB_HCDMA1_REG register
  761. * Host Channel 1 DMA Address Register
  762. */
  763. #define USB_HCDMA1_REG (SOC_DPORT_USB_BASE + 0x534)
  764. /** USB_H_DMAADDR1 : R/W; bitpos: [32:0]; default: 0;
  765. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  766. * [31:9]: DMA Address
  767. * [8:3]: Current Transfer Desc
  768. * [2:0]: Reserved
  769. */
  770. #define USB_H_DMAADDR1 0xFFFFFFFF
  771. #define USB_H_DMAADDR1_M (USB_H_DMAADDR1_V << USB_H_DMAADDR1_S)
  772. #define USB_H_DMAADDR1_V 0xFFFFFFFF
  773. #define USB_H_DMAADDR1_S 0
  774. /** USB_HCCHAR2_REG register
  775. * Host Channel 2 Characteristics Register
  776. */
  777. #define USB_HCCHAR2_REG (SOC_DPORT_USB_BASE + 0x540)
  778. /** USB_H_MPS2 : R/W; bitpos: [11:0]; default: 0;
  779. * Maximum Packet Size.
  780. */
  781. #define USB_H_MPS2 0x000007FF
  782. #define USB_H_MPS2_M (USB_H_MPS2_V << USB_H_MPS2_S)
  783. #define USB_H_MPS2_V 0x000007FF
  784. #define USB_H_MPS2_S 0
  785. /** USB_H_EPNUM2 : R/W; bitpos: [15:11]; default: 0;
  786. * Endpoint Number.
  787. */
  788. #define USB_H_EPNUM2 0x0000000F
  789. #define USB_H_EPNUM2_M (USB_H_EPNUM2_V << USB_H_EPNUM2_S)
  790. #define USB_H_EPNUM2_V 0x0000000F
  791. #define USB_H_EPNUM2_S 11
  792. /** USB_H_EPDIR2 : R/W; bitpos: [15]; default: 0;
  793. * 1'b0: OUT
  794. * 1'b1: IN
  795. */
  796. #define USB_H_EPDIR2 (BIT(15))
  797. #define USB_H_EPDIR2_M (USB_H_EPDIR2_V << USB_H_EPDIR2_S)
  798. #define USB_H_EPDIR2_V 0x00000001
  799. #define USB_H_EPDIR2_S 15
  800. /** USB_H_LSPDDEV2 : R/W; bitpos: [17]; default: 0;
  801. * 0x0: Not Communicating with low speed device
  802. * 0x1: Communicating with low speed device
  803. */
  804. #define USB_H_LSPDDEV2 (BIT(17))
  805. #define USB_H_LSPDDEV2_M (USB_H_LSPDDEV2_V << USB_H_LSPDDEV2_S)
  806. #define USB_H_LSPDDEV2_V 0x00000001
  807. #define USB_H_LSPDDEV2_S 17
  808. /** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0;
  809. * 0x0 (CTRL): Contro
  810. * 0x1 (ISOC): Isochronous
  811. * 0x2 (BULK): Bulk
  812. * 0x3 (INTERR): Interrupt
  813. */
  814. #define USB_H_EPTYPE2 0x00000003
  815. #define USB_H_EPTYPE2_M (USB_H_EPTYPE2_V << USB_H_EPTYPE2_S)
  816. #define USB_H_EPTYPE2_V 0x00000003
  817. #define USB_H_EPTYPE2_S 18
  818. /** USB_H_EC2 : R/W; bitpos: [21]; default: 0;
  819. * Multi Count (MC) / Error Count(EC)
  820. * 0x0 (RESERVED): Reserved. This field yields undefined result
  821. * 0x1 (TRANSONE): 1 transaction
  822. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  823. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  824. */
  825. #define USB_H_EC2 (BIT(21))
  826. #define USB_H_EC2_M (USB_H_EC2_V << USB_H_EC2_S)
  827. #define USB_H_EC2_V 0x00000001
  828. #define USB_H_EC2_S 21
  829. /** USB_H_DEVADDR2 : R/W; bitpos: [29:22]; default: 0;
  830. * Device Address . This field selects the specific device serving as the data
  831. * source or sink.
  832. */
  833. #define USB_H_DEVADDR2 0x0000007F
  834. #define USB_H_DEVADDR2_M (USB_H_DEVADDR2_V << USB_H_DEVADDR2_S)
  835. #define USB_H_DEVADDR2_V 0x0000007F
  836. #define USB_H_DEVADDR2_S 22
  837. /** USB_H_ODDFRM2 : R/W; bitpos: [29]; default: 0;
  838. * Odd Frame
  839. * 1'b0: Even (micro)Frame
  840. * 1'b1: Odd (micro)Frame
  841. */
  842. #define USB_H_ODDFRM2 (BIT(29))
  843. #define USB_H_ODDFRM2_M (USB_H_ODDFRM2_V << USB_H_ODDFRM2_S)
  844. #define USB_H_ODDFRM2_V 0x00000001
  845. #define USB_H_ODDFRM2_S 29
  846. /** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0;
  847. * Channel Disable
  848. * 0x0 : Transmit/Recieve norma
  849. * 0x1 : Stop transmitting/receiving data on channel
  850. */
  851. #define USB_H_CHDIS2 (BIT(30))
  852. #define USB_H_CHDIS2_M (USB_H_CHDIS2_V << USB_H_CHDIS2_S)
  853. #define USB_H_CHDIS2_V 0x00000001
  854. #define USB_H_CHDIS2_S 30
  855. /** USB_H_CHENA2 : R/W; bitpos: [31]; default: 0;
  856. * Channel Enable
  857. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  858. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  859. * disabled
  860. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  861. * and data buffer with data is set up and this channel can access the descriptor. If
  862. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  863. */
  864. #define USB_H_CHENA2 (BIT(31))
  865. #define USB_H_CHENA2_M (USB_H_CHENA2_V << USB_H_CHENA2_S)
  866. #define USB_H_CHENA2_V 0x00000001
  867. #define USB_H_CHENA2_S 31
  868. /** USB_HCDMA2_REG register
  869. * Host Channel 2 DMA Address Register
  870. */
  871. #define USB_HCDMA2_REG (SOC_DPORT_USB_BASE + 0x554)
  872. /** USB_H_DMAADDR2 : R/W; bitpos: [32:0]; default: 0;
  873. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  874. * [31:9]: DMA Address
  875. * [8:3]: Current Transfer Desc
  876. * [2:0]: Reserved
  877. */
  878. #define USB_H_DMAADDR2 0xFFFFFFFF
  879. #define USB_H_DMAADDR2_M (USB_H_DMAADDR2_V << USB_H_DMAADDR2_S)
  880. #define USB_H_DMAADDR2_V 0xFFFFFFFF
  881. #define USB_H_DMAADDR2_S 0
  882. /** USB_HCCHAR3_REG register
  883. * Host Channel 3 Characteristics Register
  884. */
  885. #define USB_HCCHAR3_REG (SOC_DPORT_USB_BASE + 0x560)
  886. /** USB_H_MPS3 : R/W; bitpos: [11:0]; default: 0;
  887. * Maximum Packet Size.
  888. */
  889. #define USB_H_MPS3 0x000007FF
  890. #define USB_H_MPS3_M (USB_H_MPS3_V << USB_H_MPS3_S)
  891. #define USB_H_MPS3_V 0x000007FF
  892. #define USB_H_MPS3_S 0
  893. /** USB_H_EPNUM3 : R/W; bitpos: [15:11]; default: 0;
  894. * Endpoint Number.
  895. */
  896. #define USB_H_EPNUM3 0x0000000F
  897. #define USB_H_EPNUM3_M (USB_H_EPNUM3_V << USB_H_EPNUM3_S)
  898. #define USB_H_EPNUM3_V 0x0000000F
  899. #define USB_H_EPNUM3_S 11
  900. /** USB_H_EPDIR3 : R/W; bitpos: [15]; default: 0;
  901. * 1'b0: OUT
  902. * 1'b1: IN
  903. */
  904. #define USB_H_EPDIR3 (BIT(15))
  905. #define USB_H_EPDIR3_M (USB_H_EPDIR3_V << USB_H_EPDIR3_S)
  906. #define USB_H_EPDIR3_V 0x00000001
  907. #define USB_H_EPDIR3_S 15
  908. /** USB_H_LSPDDEV3 : R/W; bitpos: [17]; default: 0;
  909. * 0x0: Not Communicating with low speed device
  910. * 0x1: Communicating with low speed device
  911. */
  912. #define USB_H_LSPDDEV3 (BIT(17))
  913. #define USB_H_LSPDDEV3_M (USB_H_LSPDDEV3_V << USB_H_LSPDDEV3_S)
  914. #define USB_H_LSPDDEV3_V 0x00000001
  915. #define USB_H_LSPDDEV3_S 17
  916. /** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0;
  917. * 0x0 (CTRL): Contro
  918. * 0x1 (ISOC): Isochronous
  919. * 0x2 (BULK): Bulk
  920. * 0x3 (INTERR): Interrupt
  921. */
  922. #define USB_H_EPTYPE3 0x00000003
  923. #define USB_H_EPTYPE3_M (USB_H_EPTYPE3_V << USB_H_EPTYPE3_S)
  924. #define USB_H_EPTYPE3_V 0x00000003
  925. #define USB_H_EPTYPE3_S 18
  926. /** USB_H_EC3 : R/W; bitpos: [21]; default: 0;
  927. * Multi Count (MC) / Error Count(EC)
  928. * 0x0 (RESERVED): Reserved. This field yields undefined result
  929. * 0x1 (TRANSONE): 1 transaction
  930. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  931. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  932. */
  933. #define USB_H_EC3 (BIT(21))
  934. #define USB_H_EC3_M (USB_H_EC3_V << USB_H_EC3_S)
  935. #define USB_H_EC3_V 0x00000001
  936. #define USB_H_EC3_S 21
  937. /** USB_H_DEVADDR3 : R/W; bitpos: [29:22]; default: 0;
  938. * Device Address . This field selects the specific device serving as the data
  939. * source or sink.
  940. */
  941. #define USB_H_DEVADDR3 0x0000007F
  942. #define USB_H_DEVADDR3_M (USB_H_DEVADDR3_V << USB_H_DEVADDR3_S)
  943. #define USB_H_DEVADDR3_V 0x0000007F
  944. #define USB_H_DEVADDR3_S 22
  945. /** USB_H_ODDFRM3 : R/W; bitpos: [29]; default: 0;
  946. * Odd Frame
  947. * 1'b0: Even (micro)Frame
  948. * 1'b1: Odd (micro)Frame
  949. */
  950. #define USB_H_ODDFRM3 (BIT(29))
  951. #define USB_H_ODDFRM3_M (USB_H_ODDFRM3_V << USB_H_ODDFRM3_S)
  952. #define USB_H_ODDFRM3_V 0x00000001
  953. #define USB_H_ODDFRM3_S 29
  954. /** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0;
  955. * Channel Disable
  956. * 0x0 : Transmit/Recieve norma
  957. * 0x1 : Stop transmitting/receiving data on channel
  958. */
  959. #define USB_H_CHDIS3 (BIT(30))
  960. #define USB_H_CHDIS3_M (USB_H_CHDIS3_V << USB_H_CHDIS3_S)
  961. #define USB_H_CHDIS3_V 0x00000001
  962. #define USB_H_CHDIS3_S 30
  963. /** USB_H_CHENA3 : R/W; bitpos: [31]; default: 0;
  964. * Channel Enable
  965. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  966. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  967. * disabled
  968. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  969. * and data buffer with data is set up and this channel can access the descriptor. If
  970. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  971. */
  972. #define USB_H_CHENA3 (BIT(31))
  973. #define USB_H_CHENA3_M (USB_H_CHENA3_V << USB_H_CHENA3_S)
  974. #define USB_H_CHENA3_V 0x00000001
  975. #define USB_H_CHENA3_S 31
  976. /** USB_HCDMA3_REG register
  977. * Host Channel 3 DMA Address Register
  978. */
  979. #define USB_HCDMA3_REG (SOC_DPORT_USB_BASE + 0x574)
  980. /** USB_H_DMAADDR3 : R/W; bitpos: [32:0]; default: 0;
  981. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  982. * [31:9]: DMA Address
  983. * [8:3]: Current Transfer Desc
  984. * [2:0]: Reserved
  985. */
  986. #define USB_H_DMAADDR3 0xFFFFFFFF
  987. #define USB_H_DMAADDR3_M (USB_H_DMAADDR3_V << USB_H_DMAADDR3_S)
  988. #define USB_H_DMAADDR3_V 0xFFFFFFFF
  989. #define USB_H_DMAADDR3_S 0
  990. /** USB_HCCHAR4_REG register
  991. * Host Channel 4 Characteristics Register
  992. */
  993. #define USB_HCCHAR4_REG (SOC_DPORT_USB_BASE + 0x580)
  994. /** USB_H_MPS4 : R/W; bitpos: [11:0]; default: 0;
  995. * Maximum Packet Size.
  996. */
  997. #define USB_H_MPS4 0x000007FF
  998. #define USB_H_MPS4_M (USB_H_MPS4_V << USB_H_MPS4_S)
  999. #define USB_H_MPS4_V 0x000007FF
  1000. #define USB_H_MPS4_S 0
  1001. /** USB_H_EPNUM4 : R/W; bitpos: [15:11]; default: 0;
  1002. * Endpoint Number.
  1003. */
  1004. #define USB_H_EPNUM4 0x0000000F
  1005. #define USB_H_EPNUM4_M (USB_H_EPNUM4_V << USB_H_EPNUM4_S)
  1006. #define USB_H_EPNUM4_V 0x0000000F
  1007. #define USB_H_EPNUM4_S 11
  1008. /** USB_H_EPDIR4 : R/W; bitpos: [15]; default: 0;
  1009. * 1'b0: OUT
  1010. * 1'b1: IN
  1011. */
  1012. #define USB_H_EPDIR4 (BIT(15))
  1013. #define USB_H_EPDIR4_M (USB_H_EPDIR4_V << USB_H_EPDIR4_S)
  1014. #define USB_H_EPDIR4_V 0x00000001
  1015. #define USB_H_EPDIR4_S 15
  1016. /** USB_H_LSPDDEV4 : R/W; bitpos: [17]; default: 0;
  1017. * 0x0: Not Communicating with low speed device
  1018. * 0x1: Communicating with low speed device
  1019. */
  1020. #define USB_H_LSPDDEV4 (BIT(17))
  1021. #define USB_H_LSPDDEV4_M (USB_H_LSPDDEV4_V << USB_H_LSPDDEV4_S)
  1022. #define USB_H_LSPDDEV4_V 0x00000001
  1023. #define USB_H_LSPDDEV4_S 17
  1024. /** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0;
  1025. * 0x0 (CTRL): Contro
  1026. * 0x1 (ISOC): Isochronous
  1027. * 0x2 (BULK): Bulk
  1028. * 0x3 (INTERR): Interrupt
  1029. */
  1030. #define USB_H_EPTYPE4 0x00000003
  1031. #define USB_H_EPTYPE4_M (USB_H_EPTYPE4_V << USB_H_EPTYPE4_S)
  1032. #define USB_H_EPTYPE4_V 0x00000003
  1033. #define USB_H_EPTYPE4_S 18
  1034. /** USB_H_EC4 : R/W; bitpos: [21]; default: 0;
  1035. * Multi Count (MC) / Error Count(EC)
  1036. * 0x0 (RESERVED): Reserved. This field yields undefined result
  1037. * 0x1 (TRANSONE): 1 transaction
  1038. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  1039. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  1040. */
  1041. #define USB_H_EC4 (BIT(21))
  1042. #define USB_H_EC4_M (USB_H_EC4_V << USB_H_EC4_S)
  1043. #define USB_H_EC4_V 0x00000001
  1044. #define USB_H_EC4_S 21
  1045. /** USB_H_DEVADDR4 : R/W; bitpos: [29:22]; default: 0;
  1046. * Device Address . This field selects the specific device serving as the data
  1047. * source or sink.
  1048. */
  1049. #define USB_H_DEVADDR4 0x0000007F
  1050. #define USB_H_DEVADDR4_M (USB_H_DEVADDR4_V << USB_H_DEVADDR4_S)
  1051. #define USB_H_DEVADDR4_V 0x0000007F
  1052. #define USB_H_DEVADDR4_S 22
  1053. /** USB_H_ODDFRM4 : R/W; bitpos: [29]; default: 0;
  1054. * Odd Frame
  1055. * 1'b0: Even (micro)Frame
  1056. * 1'b1: Odd (micro)Frame
  1057. */
  1058. #define USB_H_ODDFRM4 (BIT(29))
  1059. #define USB_H_ODDFRM4_M (USB_H_ODDFRM4_V << USB_H_ODDFRM4_S)
  1060. #define USB_H_ODDFRM4_V 0x00000001
  1061. #define USB_H_ODDFRM4_S 29
  1062. /** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0;
  1063. * Channel Disable
  1064. * 0x0 : Transmit/Recieve norma
  1065. * 0x1 : Stop transmitting/receiving data on channel
  1066. */
  1067. #define USB_H_CHDIS4 (BIT(30))
  1068. #define USB_H_CHDIS4_M (USB_H_CHDIS4_V << USB_H_CHDIS4_S)
  1069. #define USB_H_CHDIS4_V 0x00000001
  1070. #define USB_H_CHDIS4_S 30
  1071. /** USB_H_CHENA4 : R/W; bitpos: [31]; default: 0;
  1072. * Channel Enable
  1073. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  1074. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  1075. * disabled
  1076. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  1077. * and data buffer with data is set up and this channel can access the descriptor. If
  1078. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  1079. */
  1080. #define USB_H_CHENA4 (BIT(31))
  1081. #define USB_H_CHENA4_M (USB_H_CHENA4_V << USB_H_CHENA4_S)
  1082. #define USB_H_CHENA4_V 0x00000001
  1083. #define USB_H_CHENA4_S 31
  1084. /** USB_HCDMA4_REG register
  1085. * Host Channel 4 DMA Address Register
  1086. */
  1087. #define USB_HCDMA4_REG (SOC_DPORT_USB_BASE + 0x594)
  1088. /** USB_H_DMAADDR4 : R/W; bitpos: [32:0]; default: 0;
  1089. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  1090. * [31:9]: DMA Address
  1091. * [8:3]: Current Transfer Desc
  1092. * [2:0]: Reserved
  1093. */
  1094. #define USB_H_DMAADDR4 0xFFFFFFFF
  1095. #define USB_H_DMAADDR4_M (USB_H_DMAADDR4_V << USB_H_DMAADDR4_S)
  1096. #define USB_H_DMAADDR4_V 0xFFFFFFFF
  1097. #define USB_H_DMAADDR4_S 0
  1098. /** USB_HCCHAR5_REG register
  1099. * Host Channel 5 Characteristics Register
  1100. */
  1101. #define USB_HCCHAR5_REG (SOC_DPORT_USB_BASE + 0x5a0)
  1102. /** USB_H_MPS5 : R/W; bitpos: [11:0]; default: 0;
  1103. * Maximum Packet Size.
  1104. */
  1105. #define USB_H_MPS5 0x000007FF
  1106. #define USB_H_MPS5_M (USB_H_MPS5_V << USB_H_MPS5_S)
  1107. #define USB_H_MPS5_V 0x000007FF
  1108. #define USB_H_MPS5_S 0
  1109. /** USB_H_EPNUM5 : R/W; bitpos: [15:11]; default: 0;
  1110. * Endpoint Number.
  1111. */
  1112. #define USB_H_EPNUM5 0x0000000F
  1113. #define USB_H_EPNUM5_M (USB_H_EPNUM5_V << USB_H_EPNUM5_S)
  1114. #define USB_H_EPNUM5_V 0x0000000F
  1115. #define USB_H_EPNUM5_S 11
  1116. /** USB_H_EPDIR5 : R/W; bitpos: [15]; default: 0;
  1117. * 1'b0: OUT
  1118. * 1'b1: IN
  1119. */
  1120. #define USB_H_EPDIR5 (BIT(15))
  1121. #define USB_H_EPDIR5_M (USB_H_EPDIR5_V << USB_H_EPDIR5_S)
  1122. #define USB_H_EPDIR5_V 0x00000001
  1123. #define USB_H_EPDIR5_S 15
  1124. /** USB_H_LSPDDEV5 : R/W; bitpos: [17]; default: 0;
  1125. * 0x0: Not Communicating with low speed device
  1126. * 0x1: Communicating with low speed device
  1127. */
  1128. #define USB_H_LSPDDEV5 (BIT(17))
  1129. #define USB_H_LSPDDEV5_M (USB_H_LSPDDEV5_V << USB_H_LSPDDEV5_S)
  1130. #define USB_H_LSPDDEV5_V 0x00000001
  1131. #define USB_H_LSPDDEV5_S 17
  1132. /** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0;
  1133. * 0x0 (CTRL): Contro
  1134. * 0x1 (ISOC): Isochronous
  1135. * 0x2 (BULK): Bulk
  1136. * 0x3 (INTERR): Interrupt
  1137. */
  1138. #define USB_H_EPTYPE5 0x00000003
  1139. #define USB_H_EPTYPE5_M (USB_H_EPTYPE5_V << USB_H_EPTYPE5_S)
  1140. #define USB_H_EPTYPE5_V 0x00000003
  1141. #define USB_H_EPTYPE5_S 18
  1142. /** USB_H_EC5 : R/W; bitpos: [21]; default: 0;
  1143. * Multi Count (MC) / Error Count(EC)
  1144. * 0x0 (RESERVED): Reserved. This field yields undefined result
  1145. * 0x1 (TRANSONE): 1 transaction
  1146. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  1147. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  1148. */
  1149. #define USB_H_EC5 (BIT(21))
  1150. #define USB_H_EC5_M (USB_H_EC5_V << USB_H_EC5_S)
  1151. #define USB_H_EC5_V 0x00000001
  1152. #define USB_H_EC5_S 21
  1153. /** USB_H_DEVADDR5 : R/W; bitpos: [29:22]; default: 0;
  1154. * Device Address . This field selects the specific device serving as the data
  1155. * source or sink.
  1156. */
  1157. #define USB_H_DEVADDR5 0x0000007F
  1158. #define USB_H_DEVADDR5_M (USB_H_DEVADDR5_V << USB_H_DEVADDR5_S)
  1159. #define USB_H_DEVADDR5_V 0x0000007F
  1160. #define USB_H_DEVADDR5_S 22
  1161. /** USB_H_ODDFRM5 : R/W; bitpos: [29]; default: 0;
  1162. * Odd Frame
  1163. * 1'b0: Even (micro)Frame
  1164. * 1'b1: Odd (micro)Frame
  1165. */
  1166. #define USB_H_ODDFRM5 (BIT(29))
  1167. #define USB_H_ODDFRM5_M (USB_H_ODDFRM5_V << USB_H_ODDFRM5_S)
  1168. #define USB_H_ODDFRM5_V 0x00000001
  1169. #define USB_H_ODDFRM5_S 29
  1170. /** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0;
  1171. * Channel Disable
  1172. * 0x0 : Transmit/Recieve norma
  1173. * 0x1 : Stop transmitting/receiving data on channel
  1174. */
  1175. #define USB_H_CHDIS5 (BIT(30))
  1176. #define USB_H_CHDIS5_M (USB_H_CHDIS5_V << USB_H_CHDIS5_S)
  1177. #define USB_H_CHDIS5_V 0x00000001
  1178. #define USB_H_CHDIS5_S 30
  1179. /** USB_H_CHENA5 : R/W; bitpos: [31]; default: 0;
  1180. * Channel Enable
  1181. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  1182. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  1183. * disabled
  1184. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  1185. * and data buffer with data is set up and this channel can access the descriptor. If
  1186. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  1187. */
  1188. #define USB_H_CHENA5 (BIT(31))
  1189. #define USB_H_CHENA5_M (USB_H_CHENA5_V << USB_H_CHENA5_S)
  1190. #define USB_H_CHENA5_V 0x00000001
  1191. #define USB_H_CHENA5_S 31
  1192. /** USB_HCDMA5_REG register
  1193. * Host Channel 5 DMA Address Register
  1194. */
  1195. #define USB_HCDMA5_REG (SOC_DPORT_USB_BASE + 0x5b4)
  1196. /** USB_H_DMAADDR5 : R/W; bitpos: [32:0]; default: 0;
  1197. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  1198. * [31:9]: DMA Address
  1199. * [8:3]: Current Transfer Desc
  1200. * [2:0]: Reserved
  1201. */
  1202. #define USB_H_DMAADDR5 0xFFFFFFFF
  1203. #define USB_H_DMAADDR5_M (USB_H_DMAADDR5_V << USB_H_DMAADDR5_S)
  1204. #define USB_H_DMAADDR5_V 0xFFFFFFFF
  1205. #define USB_H_DMAADDR5_S 0
  1206. /** USB_HCCHAR6_REG register
  1207. * Host Channel 6 Characteristics Register
  1208. */
  1209. #define USB_HCCHAR6_REG (SOC_DPORT_USB_BASE + 0x5c0)
  1210. /** USB_H_MPS6 : R/W; bitpos: [11:0]; default: 0;
  1211. * Maximum Packet Size.
  1212. */
  1213. #define USB_H_MPS6 0x000007FF
  1214. #define USB_H_MPS6_M (USB_H_MPS6_V << USB_H_MPS6_S)
  1215. #define USB_H_MPS6_V 0x000007FF
  1216. #define USB_H_MPS6_S 0
  1217. /** USB_H_EPNUM6 : R/W; bitpos: [15:11]; default: 0;
  1218. * Endpoint Number.
  1219. */
  1220. #define USB_H_EPNUM6 0x0000000F
  1221. #define USB_H_EPNUM6_M (USB_H_EPNUM6_V << USB_H_EPNUM6_S)
  1222. #define USB_H_EPNUM6_V 0x0000000F
  1223. #define USB_H_EPNUM6_S 11
  1224. /** USB_H_EPDIR6 : R/W; bitpos: [15]; default: 0;
  1225. * 1'b0: OUT
  1226. * 1'b1: IN
  1227. */
  1228. #define USB_H_EPDIR6 (BIT(15))
  1229. #define USB_H_EPDIR6_M (USB_H_EPDIR6_V << USB_H_EPDIR6_S)
  1230. #define USB_H_EPDIR6_V 0x00000001
  1231. #define USB_H_EPDIR6_S 15
  1232. /** USB_H_LSPDDEV6 : R/W; bitpos: [17]; default: 0;
  1233. * 0x0: Not Communicating with low speed device
  1234. * 0x1: Communicating with low speed device
  1235. */
  1236. #define USB_H_LSPDDEV6 (BIT(17))
  1237. #define USB_H_LSPDDEV6_M (USB_H_LSPDDEV6_V << USB_H_LSPDDEV6_S)
  1238. #define USB_H_LSPDDEV6_V 0x00000001
  1239. #define USB_H_LSPDDEV6_S 17
  1240. /** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0;
  1241. * 0x0 (CTRL): Contro
  1242. * 0x1 (ISOC): Isochronous
  1243. * 0x2 (BULK): Bulk
  1244. * 0x3 (INTERR): Interrupt
  1245. */
  1246. #define USB_H_EPTYPE6 0x00000003
  1247. #define USB_H_EPTYPE6_M (USB_H_EPTYPE6_V << USB_H_EPTYPE6_S)
  1248. #define USB_H_EPTYPE6_V 0x00000003
  1249. #define USB_H_EPTYPE6_S 18
  1250. /** USB_H_EC6 : R/W; bitpos: [21]; default: 0;
  1251. * Multi Count (MC) / Error Count(EC)
  1252. * 0x0 (RESERVED): Reserved. This field yields undefined result
  1253. * 0x1 (TRANSONE): 1 transaction
  1254. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  1255. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  1256. */
  1257. #define USB_H_EC6 (BIT(21))
  1258. #define USB_H_EC6_M (USB_H_EC6_V << USB_H_EC6_S)
  1259. #define USB_H_EC6_V 0x00000001
  1260. #define USB_H_EC6_S 21
  1261. /** USB_H_DEVADDR6 : R/W; bitpos: [29:22]; default: 0;
  1262. * Device Address . This field selects the specific device serving as the data
  1263. * source or sink.
  1264. */
  1265. #define USB_H_DEVADDR6 0x0000007F
  1266. #define USB_H_DEVADDR6_M (USB_H_DEVADDR6_V << USB_H_DEVADDR6_S)
  1267. #define USB_H_DEVADDR6_V 0x0000007F
  1268. #define USB_H_DEVADDR6_S 22
  1269. /** USB_H_ODDFRM6 : R/W; bitpos: [29]; default: 0;
  1270. * Odd Frame
  1271. * 1'b0: Even (micro)Frame
  1272. * 1'b1: Odd (micro)Frame
  1273. */
  1274. #define USB_H_ODDFRM6 (BIT(29))
  1275. #define USB_H_ODDFRM6_M (USB_H_ODDFRM6_V << USB_H_ODDFRM6_S)
  1276. #define USB_H_ODDFRM6_V 0x00000001
  1277. #define USB_H_ODDFRM6_S 29
  1278. /** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0;
  1279. * Channel Disable
  1280. * 0x0 : Transmit/Recieve norma
  1281. * 0x1 : Stop transmitting/receiving data on channel
  1282. */
  1283. #define USB_H_CHDIS6 (BIT(30))
  1284. #define USB_H_CHDIS6_M (USB_H_CHDIS6_V << USB_H_CHDIS6_S)
  1285. #define USB_H_CHDIS6_V 0x00000001
  1286. #define USB_H_CHDIS6_S 30
  1287. /** USB_H_CHENA6 : R/W; bitpos: [31]; default: 0;
  1288. * Channel Enable
  1289. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  1290. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  1291. * disabled
  1292. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  1293. * and data buffer with data is set up and this channel can access the descriptor. If
  1294. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  1295. */
  1296. #define USB_H_CHENA6 (BIT(31))
  1297. #define USB_H_CHENA6_M (USB_H_CHENA6_V << USB_H_CHENA6_S)
  1298. #define USB_H_CHENA6_V 0x00000001
  1299. #define USB_H_CHENA6_S 31
  1300. /** USB_HCDMA6_REG register
  1301. * Host Channel 6 DMA Address Register
  1302. */
  1303. #define USB_HCDMA6_REG (SOC_DPORT_USB_BASE + 0x5d4)
  1304. /** USB_H_DMAADDR6 : R/W; bitpos: [32:0]; default: 0;
  1305. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  1306. * [31:9]: DMA Address
  1307. * [8:3]: Current Transfer Desc
  1308. * [2:0]: Reserved
  1309. */
  1310. #define USB_H_DMAADDR6 0xFFFFFFFF
  1311. #define USB_H_DMAADDR6_M (USB_H_DMAADDR6_V << USB_H_DMAADDR6_S)
  1312. #define USB_H_DMAADDR6_V 0xFFFFFFFF
  1313. #define USB_H_DMAADDR6_S 0
  1314. /** USB_HCCHAR7_REG register
  1315. * Host Channel 7 Characteristics Register
  1316. */
  1317. #define USB_HCCHAR7_REG (SOC_DPORT_USB_BASE + 0x5e0)
  1318. /** USB_H_MPS7 : R/W; bitpos: [11:0]; default: 0;
  1319. * Maximum Packet Size.
  1320. */
  1321. #define USB_H_MPS7 0x000007FF
  1322. #define USB_H_MPS7_M (USB_H_MPS7_V << USB_H_MPS7_S)
  1323. #define USB_H_MPS7_V 0x000007FF
  1324. #define USB_H_MPS7_S 0
  1325. /** USB_H_EPNUM7 : R/W; bitpos: [15:11]; default: 0;
  1326. * Endpoint Number.
  1327. */
  1328. #define USB_H_EPNUM7 0x0000000F
  1329. #define USB_H_EPNUM7_M (USB_H_EPNUM7_V << USB_H_EPNUM7_S)
  1330. #define USB_H_EPNUM7_V 0x0000000F
  1331. #define USB_H_EPNUM7_S 11
  1332. /** USB_H_EPDIR7 : R/W; bitpos: [15]; default: 0;
  1333. * 1'b0: OUT
  1334. * 1'b1: IN
  1335. */
  1336. #define USB_H_EPDIR7 (BIT(15))
  1337. #define USB_H_EPDIR7_M (USB_H_EPDIR7_V << USB_H_EPDIR7_S)
  1338. #define USB_H_EPDIR7_V 0x00000001
  1339. #define USB_H_EPDIR7_S 15
  1340. /** USB_H_LSPDDEV7 : R/W; bitpos: [17]; default: 0;
  1341. * 0x0: Not Communicating with low speed device
  1342. * 0x1: Communicating with low speed device
  1343. */
  1344. #define USB_H_LSPDDEV7 (BIT(17))
  1345. #define USB_H_LSPDDEV7_M (USB_H_LSPDDEV7_V << USB_H_LSPDDEV7_S)
  1346. #define USB_H_LSPDDEV7_V 0x00000001
  1347. #define USB_H_LSPDDEV7_S 17
  1348. /** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0;
  1349. * 0x0 (CTRL): Contro
  1350. * 0x1 (ISOC): Isochronous
  1351. * 0x2 (BULK): Bulk
  1352. * 0x3 (INTERR): Interrupt
  1353. */
  1354. #define USB_H_EPTYPE7 0x00000003
  1355. #define USB_H_EPTYPE7_M (USB_H_EPTYPE7_V << USB_H_EPTYPE7_S)
  1356. #define USB_H_EPTYPE7_V 0x00000003
  1357. #define USB_H_EPTYPE7_S 18
  1358. /** USB_H_EC7 : R/W; bitpos: [21]; default: 0;
  1359. * Multi Count (MC) / Error Count(EC)
  1360. * 0x0 (RESERVED): Reserved. This field yields undefined result
  1361. * 0x1 (TRANSONE): 1 transaction
  1362. * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe
  1363. * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe
  1364. */
  1365. #define USB_H_EC7 (BIT(21))
  1366. #define USB_H_EC7_M (USB_H_EC7_V << USB_H_EC7_S)
  1367. #define USB_H_EC7_V 0x00000001
  1368. #define USB_H_EC7_S 21
  1369. /** USB_H_DEVADDR7 : R/W; bitpos: [29:22]; default: 0;
  1370. * Device Address . This field selects the specific device serving as the data
  1371. * source or sink.
  1372. */
  1373. #define USB_H_DEVADDR7 0x0000007F
  1374. #define USB_H_DEVADDR7_M (USB_H_DEVADDR7_V << USB_H_DEVADDR7_S)
  1375. #define USB_H_DEVADDR7_V 0x0000007F
  1376. #define USB_H_DEVADDR7_S 22
  1377. /** USB_H_ODDFRM7 : R/W; bitpos: [29]; default: 0;
  1378. * Odd Frame
  1379. * 1'b0: Even (micro)Frame
  1380. * 1'b1: Odd (micro)Frame
  1381. */
  1382. #define USB_H_ODDFRM7 (BIT(29))
  1383. #define USB_H_ODDFRM7_M (USB_H_ODDFRM7_V << USB_H_ODDFRM7_S)
  1384. #define USB_H_ODDFRM7_V 0x00000001
  1385. #define USB_H_ODDFRM7_S 29
  1386. /** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0;
  1387. * Channel Disable
  1388. * 0x0 : Transmit/Recieve norma
  1389. * 0x1 : Stop transmitting/receiving data on channel
  1390. */
  1391. #define USB_H_CHDIS7 (BIT(30))
  1392. #define USB_H_CHDIS7_M (USB_H_CHDIS7_V << USB_H_CHDIS7_S)
  1393. #define USB_H_CHDIS7_V 0x00000001
  1394. #define USB_H_CHDIS7_S 30
  1395. /** USB_H_CHENA7 : R/W; bitpos: [31]; default: 0;
  1396. * Channel Enable
  1397. * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is
  1398. * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is
  1399. * disabled
  1400. * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure
  1401. * and data buffer with data is set up and this channel can access the descriptor. If
  1402. * Scatter/Gather mode is disabled, indicates that the channel is enabled
  1403. */
  1404. #define USB_H_CHENA7 (BIT(31))
  1405. #define USB_H_CHENA7_M (USB_H_CHENA7_V << USB_H_CHENA7_S)
  1406. #define USB_H_CHENA7_V 0x00000001
  1407. #define USB_H_CHENA7_S 31
  1408. /** USB_HCDMA7_REG register
  1409. * Host Channel 7 DMA Address Register
  1410. */
  1411. #define USB_HCDMA7_REG (SOC_DPORT_USB_BASE + 0x5f4)
  1412. /** USB_H_DMAADDR7 : R/W; bitpos: [32:0]; default: 0;
  1413. * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
  1414. * [31:9]: DMA Address
  1415. * [8:3]: Current Transfer Desc
  1416. * [2:0]: Reserved
  1417. */
  1418. #define USB_H_DMAADDR7 0xFFFFFFFF
  1419. #define USB_H_DMAADDR7_M (USB_H_DMAADDR7_V << USB_H_DMAADDR7_S)
  1420. #define USB_H_DMAADDR7_V 0xFFFFFFFF
  1421. #define USB_H_DMAADDR7_S 0
  1422. /** USB_DCFG_REG register
  1423. * Device Configuration Register
  1424. */
  1425. #define USB_DCFG_REG (SOC_DPORT_USB_BASE + 0x800)
  1426. /** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0;
  1427. * 1'b0: Send the received OUT packet to the application (zero-length or non-zero
  1428. * length) and send a handshake based on NAK and STALL bits for the endpoint in the
  1429. * Devce Endpoint Control Register
  1430. * 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not
  1431. * send the received OUT packet to the application
  1432. */
  1433. #define USB_NZSTSOUTHSHK (BIT(2))
  1434. #define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S)
  1435. #define USB_NZSTSOUTHSHK_V 0x00000001
  1436. #define USB_NZSTSOUTHSHK_S 2
  1437. /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0;
  1438. * Device Address.
  1439. */
  1440. #define USB_DEVADDR 0x0000007F
  1441. #define USB_DEVADDR_M (USB_DEVADDR_V << USB_DEVADDR_S)
  1442. #define USB_DEVADDR_V 0x0000007F
  1443. #define USB_DEVADDR_S 4
  1444. /** USB_PERFRLINT : R/W; bitpos: [13:11]; default: 0;
  1445. * 0x0 (EOPF80): 80% of the (micro)Frame interval
  1446. * 0x1 (EOPF85): 85% of the (micro)Frame interval
  1447. * 0x2 (EOPF90): 90% of the (micro)Frame interval
  1448. * 0x3 (EOPF95): 95% of the (micro)Frame interval
  1449. */
  1450. #define USB_PERFRLINT 0x00000003
  1451. #define USB_PERFRLINT_M (USB_PERFRLINT_V << USB_PERFRLINT_S)
  1452. #define USB_PERFRLINT_V 0x00000003
  1453. #define USB_PERFRLINT_S 11
  1454. /** USB_ENDEVOUTNAK : R/W; bitpos: [13]; default: 0;
  1455. * 1'b0:The core does not set NAK after Bulk OUT transfer complete
  1456. * 1'b1: The core sets NAK after Bulk OUT transfer complete
  1457. */
  1458. #define USB_ENDEVOUTNAK (BIT(13))
  1459. #define USB_ENDEVOUTNAK_M (USB_ENDEVOUTNAK_V << USB_ENDEVOUTNAK_S)
  1460. #define USB_ENDEVOUTNAK_V 0x00000001
  1461. #define USB_ENDEVOUTNAK_S 13
  1462. /** USB_XCVRDLY : R/W; bitpos: [14]; default: 0;
  1463. * 0x0 : No delay between xcvr_sel and txvalid during Device chirp
  1464. * 0x1 : Enable delay between xcvr_sel and txvalid during Device chirp
  1465. */
  1466. #define USB_XCVRDLY (BIT(14))
  1467. #define USB_XCVRDLY_M (USB_XCVRDLY_V << USB_XCVRDLY_S)
  1468. #define USB_XCVRDLY_V 0x00000001
  1469. #define USB_XCVRDLY_S 14
  1470. /** USB_ERRATICINTMSK : R/W; bitpos: [15]; default: 0;
  1471. * 0x0 : Early suspend interrupt is generated on erratic error
  1472. * 0x1: Mask early suspend interrupt on erratic error
  1473. */
  1474. #define USB_ERRATICINTMSK (BIT(15))
  1475. #define USB_ERRATICINTMSK_M (USB_ERRATICINTMSK_V << USB_ERRATICINTMSK_S)
  1476. #define USB_ERRATICINTMSK_V 0x00000001
  1477. #define USB_ERRATICINTMSK_S 15
  1478. /** USB_EPMISCNT : R/W; bitpos: [23:18]; default: 4;
  1479. * IN Endpoint Mismatch Count.
  1480. */
  1481. #define USB_EPMISCNT 0x0000001F
  1482. #define USB_EPMISCNT_M (USB_EPMISCNT_V << USB_EPMISCNT_S)
  1483. #define USB_EPMISCNT_V 0x0000001F
  1484. #define USB_EPMISCNT_S 18
  1485. /** USB_DESCDMA : R/W; bitpos: [23]; default: 0;
  1486. * 1'b0: Disable Scatter/Gather DMA
  1487. * 1'b1: Enable Scatter/Gather DMA
  1488. */
  1489. #define USB_DESCDMA (BIT(23))
  1490. #define USB_DESCDMA_M (USB_DESCDMA_V << USB_DESCDMA_S)
  1491. #define USB_DESCDMA_V 0x00000001
  1492. #define USB_DESCDMA_S 23
  1493. /** USB_PERSCHINTVL : R/W; bitpos: [26:24]; default: 0;
  1494. * Periodic Scheduling Interval
  1495. * 0x0 (MF25): 25% of (micro)Frame
  1496. * 0x1 (MF50): 50% of (micro)Frame
  1497. * 0x2 (MF75): 75% of (micro)Frame
  1498. * 0x3 (RESERVED): Reserved
  1499. */
  1500. #define USB_PERSCHINTVL 0x00000003
  1501. #define USB_PERSCHINTVL_M (USB_PERSCHINTVL_V << USB_PERSCHINTVL_S)
  1502. #define USB_PERSCHINTVL_V 0x00000003
  1503. #define USB_PERSCHINTVL_S 24
  1504. /** USB_RESVALID : R/W; bitpos: [32:26]; default: 2;
  1505. * This field is effective only when DCFG.Ena32KHzSusp is set. It controls the resume
  1506. * period when the core resumes from suspend.
  1507. * The core counts for ResValid number of clock cycles to detect a valid resume when
  1508. * this bit is set
  1509. */
  1510. #define USB_RESVALID 0x0000003F
  1511. #define USB_RESVALID_M (USB_RESVALID_V << USB_RESVALID_S)
  1512. #define USB_RESVALID_V 0x0000003F
  1513. #define USB_RESVALID_S 26
  1514. /** USB_DCTL_REG register
  1515. * Device Control Register
  1516. */
  1517. #define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804)
  1518. /** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0;
  1519. * 0x0 : Core does not send Remote Wakeup Signaling
  1520. * 0x1 : Core sends Remote Wakeup Signalin
  1521. */
  1522. #define USB_RMTWKUPSIG (BIT(0))
  1523. #define USB_RMTWKUPSIG_M (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S)
  1524. #define USB_RMTWKUPSIG_V 0x00000001
  1525. #define USB_RMTWKUPSIG_S 0
  1526. /** USB_SFTDISCON : R/W; bitpos: [1]; default: 0;
  1527. * 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core
  1528. * drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device
  1529. * connect event to the USB host. When the device is reconnected, the USB host
  1530. * restarts device enumeration
  1531. * 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which
  1532. * generates a device disconnect event to the USB host
  1533. */
  1534. #define USB_SFTDISCON (BIT(1))
  1535. #define USB_SFTDISCON_M (USB_SFTDISCON_V << USB_SFTDISCON_S)
  1536. #define USB_SFTDISCON_V 0x00000001
  1537. #define USB_SFTDISCON_S 1
  1538. /** USB_GNPINNAKSTS : RO; bitpos: [2]; default: 0;
  1539. * 0x0 : A handshake is sent out based on the data availability in the transmit FIFO
  1540. * 0x1 : A NAK handshake is sent out on all non-periodic IN endpoints, irrespective
  1541. * of the data availability in the transmit FIFO
  1542. */
  1543. #define USB_GNPINNAKSTS (BIT(2))
  1544. #define USB_GNPINNAKSTS_M (USB_GNPINNAKSTS_V << USB_GNPINNAKSTS_S)
  1545. #define USB_GNPINNAKSTS_V 0x00000001
  1546. #define USB_GNPINNAKSTS_S 2
  1547. /** USB_GOUTNAKSTS : RO; bitpos: [3]; default: 0;
  1548. * 0x0 : A handshake is sent based on the FIFO Status and the NAK and STALL bit
  1549. * settings
  1550. * 0x1 : No data is written to the RxFIFO, irrespective of space availability. Sends
  1551. * a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT
  1552. * packets are dropped
  1553. */
  1554. #define USB_GOUTNAKSTS (BIT(3))
  1555. #define USB_GOUTNAKSTS_M (USB_GOUTNAKSTS_V << USB_GOUTNAKSTS_S)
  1556. #define USB_GOUTNAKSTS_V 0x00000001
  1557. #define USB_GOUTNAKSTS_S 3
  1558. /** USB_TSTCTL : R/W; bitpos: [7:4]; default: 0;
  1559. * 0x0: Test mode disabled
  1560. * 0x1: Test_J mode
  1561. * 0x2 : Test_K mode
  1562. * 0x3 : Test_SE0_NAK mode
  1563. * 0x4 : Test_Packet mode
  1564. * 0x5 : Test_force_Enable
  1565. */
  1566. #define USB_TSTCTL 0x00000007
  1567. #define USB_TSTCTL_M (USB_TSTCTL_V << USB_TSTCTL_S)
  1568. #define USB_TSTCTL_V 0x00000007
  1569. #define USB_TSTCTL_S 4
  1570. /** USB_SGNPINNAK : WO; bitpos: [7]; default: 0;
  1571. * Set Global Non-periodic IN NAK. A write to this field sets the Global Non-periodic
  1572. * IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN
  1573. * endpoints. The core can also Set this bit when a timeout condition is detected on a
  1574. * non-periodic endpoint in shared FIFO operation. The application must Set this bit
  1575. * only after making sure that the Global IN NAK Effective bit in the Core Interrupt
  1576. * Register (GINTSTS.GINNakEff) is cleared
  1577. */
  1578. #define USB_SGNPINNAK (BIT(7))
  1579. #define USB_SGNPINNAK_M (USB_SGNPINNAK_V << USB_SGNPINNAK_S)
  1580. #define USB_SGNPINNAK_V 0x00000001
  1581. #define USB_SGNPINNAK_S 7
  1582. /** USB_CGNPINNAK : WO; bitpos: [8]; default: 0;
  1583. * Clear Global Non-periodic IN NAK. A write to this field clears the Global
  1584. * Non-periodic IN NAK.
  1585. */
  1586. #define USB_CGNPINNAK (BIT(8))
  1587. #define USB_CGNPINNAK_M (USB_CGNPINNAK_V << USB_CGNPINNAK_S)
  1588. #define USB_CGNPINNAK_V 0x00000001
  1589. #define USB_CGNPINNAK_S 8
  1590. /** USB_SGOUTNAK : WO; bitpos: [9]; default: 0;
  1591. * Set Global OUT NAK. A write to this field sets the Global OUT NAK. The application
  1592. * uses this bit to send a NAK handshake on all OUT endpoints. The application must
  1593. * set the this bit only after making sure that the Global OUT NAK Effective bit in
  1594. * the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared.
  1595. */
  1596. #define USB_SGOUTNAK (BIT(9))
  1597. #define USB_SGOUTNAK_M (USB_SGOUTNAK_V << USB_SGOUTNAK_S)
  1598. #define USB_SGOUTNAK_V 0x00000001
  1599. #define USB_SGOUTNAK_S 9
  1600. /** USB_CGOUTNAK : WO; bitpos: [10]; default: 0;
  1601. * Clear Global OUT NAK. A write to this field clears the Global OUT NAK.
  1602. */
  1603. #define USB_CGOUTNAK (BIT(10))
  1604. #define USB_CGOUTNAK_M (USB_CGOUTNAK_V << USB_CGOUTNAK_S)
  1605. #define USB_CGOUTNAK_V 0x00000001
  1606. #define USB_CGOUTNAK_S 10
  1607. /** USB_PWRONPRGDONE : R/W; bitpos: [11]; default: 0;
  1608. * 1'b0: Power-On Programming not done
  1609. * 1'b1: Power-On Programming Done
  1610. */
  1611. #define USB_PWRONPRGDONE (BIT(11))
  1612. #define USB_PWRONPRGDONE_M (USB_PWRONPRGDONE_V << USB_PWRONPRGDONE_S)
  1613. #define USB_PWRONPRGDONE_V 0x00000001
  1614. #define USB_PWRONPRGDONE_S 11
  1615. /** USB_GMC : R/W; bitpos: [15:13]; default: 1;
  1616. * Global Multi Count. applicable only for Scatter/Gather DMA mode
  1617. * 0x0 : Invalid
  1618. * 0x1 : 1 packet
  1619. * 0x2 : 2 packets
  1620. * 0x3 : 3 packets
  1621. */
  1622. #define USB_GMC 0x00000003
  1623. #define USB_GMC_M (USB_GMC_V << USB_GMC_S)
  1624. #define USB_GMC_V 0x00000003
  1625. #define USB_GMC_S 13
  1626. /** USB_IGNRFRMNUM : R/W; bitpos: [15]; default: 0;
  1627. * 0: The core transmits the packets only in the frame number in which they are
  1628. * intended to be transmitted
  1629. * 1: The core ignores the frame number, sending packets immediately as the packets
  1630. * are ready
  1631. */
  1632. #define USB_IGNRFRMNUM (BIT(15))
  1633. #define USB_IGNRFRMNUM_M (USB_IGNRFRMNUM_V << USB_IGNRFRMNUM_S)
  1634. #define USB_IGNRFRMNUM_V 0x00000001
  1635. #define USB_IGNRFRMNUM_S 15
  1636. /** USB_NAKONBBLE : R/W; bitpos: [16]; default: 0;
  1637. * 1'b0: Disable NAK on Babble Error
  1638. * 1'b1: NAK on Babble Error
  1639. */
  1640. #define USB_NAKONBBLE (BIT(16))
  1641. #define USB_NAKONBBLE_M (USB_NAKONBBLE_V << USB_NAKONBBLE_S)
  1642. #define USB_NAKONBBLE_V 0x00000001
  1643. #define USB_NAKONBBLE_S 16
  1644. /** USB_ENCOUNTONBNA : R/W; bitpos: [17]; default: 0;
  1645. * 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the
  1646. * endpoint is re-enabled by the application,the core starts processing from the
  1647. * DOEPDMA descriptor
  1648. * 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the
  1649. * endpoint is re-enabled by the application, the core starts processing from the
  1650. * descriptor that received the BNA interrupt
  1651. */
  1652. #define USB_ENCOUNTONBNA (BIT(17))
  1653. #define USB_ENCOUNTONBNA_M (USB_ENCOUNTONBNA_V << USB_ENCOUNTONBNA_S)
  1654. #define USB_ENCOUNTONBNA_V 0x00000001
  1655. #define USB_ENCOUNTONBNA_S 17
  1656. /** USB_DEEPSLEEPBESLREJECT : R/W; bitpos: [18]; default: 0;
  1657. * 1'b0: Deep Sleep BESL Reject feature is disabled
  1658. * 1'b1: Deep Sleep BESL Reject feature is enabled
  1659. */
  1660. #define USB_DEEPSLEEPBESLREJECT (BIT(18))
  1661. #define USB_DEEPSLEEPBESLREJECT_M (USB_DEEPSLEEPBESLREJECT_V << USB_DEEPSLEEPBESLREJECT_S)
  1662. #define USB_DEEPSLEEPBESLREJECT_V 0x00000001
  1663. #define USB_DEEPSLEEPBESLREJECT_S 18
  1664. /** USB_DVBUSDIS_REG register
  1665. * Device VBUS Discharge Time Register
  1666. */
  1667. #define USB_DVBUSDIS_REG (SOC_DPORT_USB_BASE + 0x828)
  1668. /** USB_DVBUSDIS : R/W; bitpos: [16:0]; default: 6103;
  1669. * Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals
  1670. * (VBUS discharge time in PHY clocks) / 1, 024. The value you use depends whether the
  1671. * PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).
  1672. * Depending on your VBUS load, this value can need adjustment.
  1673. */
  1674. #define USB_DVBUSDIS 0x0000FFFF
  1675. #define USB_DVBUSDIS_M (USB_DVBUSDIS_V << USB_DVBUSDIS_S)
  1676. #define USB_DVBUSDIS_V 0x0000FFFF
  1677. #define USB_DVBUSDIS_S 0
  1678. /** USB_DVBUSPULSE_REG register
  1679. * Device VBUS Pulsing Time Register
  1680. */
  1681. #define USB_DVBUSPULSE_REG (SOC_DPORT_USB_BASE + 0x82c)
  1682. /** USB_DVBUSPULSE : R/W; bitpos: [12:0]; default: 1464;
  1683. * Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in
  1684. * PHY clocks) / 1, 024 The value you use depends whether the PHY is operating at
  1685. * 30MHz (16-bit data width) or 60 MHz (8-bit data width).
  1686. */
  1687. #define USB_DVBUSPULSE 0x00000FFF
  1688. #define USB_DVBUSPULSE_M (USB_DVBUSPULSE_V << USB_DVBUSPULSE_S)
  1689. #define USB_DVBUSPULSE_V 0x00000FFF
  1690. #define USB_DVBUSPULSE_S 0
  1691. /** USB_DTHRCTL_REG register
  1692. * Device Threshold Control Register
  1693. */
  1694. #define USB_DTHRCTL_REG (SOC_DPORT_USB_BASE + 0x830)
  1695. /** USB_NONISOTHREN : R/W; bitpos: [0]; default: 0;
  1696. * Non-ISO IN Endpoints Threshold Enable
  1697. * 0x0 : No thresholding
  1698. * 0x1 : Enable thresholding for non-isochronous IN endpoints
  1699. */
  1700. #define USB_NONISOTHREN (BIT(0))
  1701. #define USB_NONISOTHREN_M (USB_NONISOTHREN_V << USB_NONISOTHREN_S)
  1702. #define USB_NONISOTHREN_V 0x00000001
  1703. #define USB_NONISOTHREN_S 0
  1704. /** USB_ISOTHREN : R/W; bitpos: [1]; default: 0;
  1705. * ISO IN Endpoints Threshold Enable
  1706. * 0x0 : No thresholding
  1707. * 0x1 : Enables thresholding for isochronous IN endpoints
  1708. */
  1709. #define USB_ISOTHREN (BIT(1))
  1710. #define USB_ISOTHREN_M (USB_ISOTHREN_V << USB_ISOTHREN_S)
  1711. #define USB_ISOTHREN_V 0x00000001
  1712. #define USB_ISOTHREN_S 1
  1713. /** USB_TXTHRLEN : R/W; bitpos: [11:2]; default: 8;
  1714. * This field specifies Transmit thresholding size in DWORDS. This also forms the MAC
  1715. * threshold and specifies the amount of data in bytes to be in the corresponding
  1716. * endpoint transmit FIFO, before the core can start transmit on the USB. The
  1717. * threshold length has to be at least eight DWORDS when the value of AHBThrRatio is
  1718. * 2'h00. In case the AHBThrRatio is non zero the application needs to ensure that the
  1719. * AHB Threshold value does not go below the recommended eight DWORD. This field
  1720. * controls both isochronous and non-isochronous IN endpoint thresholds. The
  1721. * recommended value for ThrLen is to be the same as the programmed AHB Burst Length
  1722. * (GAHBCFG.HBstLen).
  1723. */
  1724. #define USB_TXTHRLEN 0x000001FF
  1725. #define USB_TXTHRLEN_M (USB_TXTHRLEN_V << USB_TXTHRLEN_S)
  1726. #define USB_TXTHRLEN_V 0x000001FF
  1727. #define USB_TXTHRLEN_S 2
  1728. /** USB_AHBTHRRATIO : R/W; bitpos: [13:11]; default: 0;
  1729. * 2'b00: AHB threshold = MAC threshold
  1730. * 2'b01: AHB threshold = MAC threshold/2
  1731. * 2'b10: AHB threshold = MAC threshold/4
  1732. * 2'b11: AHB threshold = MAC threshold/8
  1733. */
  1734. #define USB_AHBTHRRATIO 0x00000003
  1735. #define USB_AHBTHRRATIO_M (USB_AHBTHRRATIO_V << USB_AHBTHRRATIO_S)
  1736. #define USB_AHBTHRRATIO_V 0x00000003
  1737. #define USB_AHBTHRRATIO_S 11
  1738. /** USB_RXTHREN : R/W; bitpos: [16]; default: 0;
  1739. * 0x0 : Disable thresholding
  1740. * 0x1 : Enable thresholding in the receive direction
  1741. */
  1742. #define USB_RXTHREN (BIT(16))
  1743. #define USB_RXTHREN_M (USB_RXTHREN_V << USB_RXTHREN_S)
  1744. #define USB_RXTHREN_V 0x00000001
  1745. #define USB_RXTHREN_S 16
  1746. /** USB_RXTHRLEN : R/W; bitpos: [26:17]; default: 1;
  1747. * Receive Threshold Length. This field specifies Receive thresholding size in
  1748. * DWORDS. This field also specifies the amount of data received on the USB before the
  1749. * core can start transmitting on the AHB. The threshold length has to be at least
  1750. * eight DWORDS. The recommended value for ThrLen is to be the same as the programmed
  1751. * AHB Burst Length(GAHBCFG.HBstLen).
  1752. */
  1753. #define USB_RXTHRLEN 0x000001FF
  1754. #define USB_RXTHRLEN_M (USB_RXTHRLEN_V << USB_RXTHRLEN_S)
  1755. #define USB_RXTHRLEN_V 0x000001FF
  1756. #define USB_RXTHRLEN_S 17
  1757. /** USB_ARBPRKEN : R/W; bitpos: [27]; default: 1;
  1758. * 0x0 : Disable DMA arbiter parking
  1759. * 0x1 : Enable DMA arbiter parking for IN endpoints
  1760. */
  1761. #define USB_ARBPRKEN (BIT(27))
  1762. #define USB_ARBPRKEN_M (USB_ARBPRKEN_V << USB_ARBPRKEN_S)
  1763. #define USB_ARBPRKEN_V 0x00000001
  1764. #define USB_ARBPRKEN_S 27
  1765. /** USB_DIEPCTL0_REG register
  1766. * Device Control IN Endpoint $n Control Register
  1767. */
  1768. #define USB_DIEPCTL0_REG (SOC_DPORT_USB_BASE + 0x900)
  1769. /** USB_D_MPS0 : R/W; bitpos: [2:0]; default: 0;
  1770. * Maximum Packet Size
  1771. * 0x0 : 64 bytes
  1772. * 0x1 : 32 bytes
  1773. * 0x2 : 16 bytes
  1774. * 0x3 : 8 bytes
  1775. */
  1776. #define USB_D_MPS0 0x00000003
  1777. #define USB_D_MPS0_M (USB_D_MPS0_V << USB_D_MPS0_S)
  1778. #define USB_D_MPS0_V 0x00000003
  1779. #define USB_D_MPS0_S 0
  1780. /** USB_D_USBACTEP0 : RO; bitpos: [15]; default: 1;
  1781. * USB Active Endpoint
  1782. * 0x1 : Control endpoint is always active
  1783. */
  1784. #define USB_D_USBACTEP0 (BIT(15))
  1785. #define USB_D_USBACTEP0_M (USB_D_USBACTEP0_V << USB_D_USBACTEP0_S)
  1786. #define USB_D_USBACTEP0_V 0x00000001
  1787. #define USB_D_USBACTEP0_S 15
  1788. /** USB_D_NAKSTS0 : RO; bitpos: [17]; default: 0;
  1789. * NAK Status
  1790. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  1791. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  1792. */
  1793. #define USB_D_NAKSTS0 (BIT(17))
  1794. #define USB_D_NAKSTS0_M (USB_D_NAKSTS0_V << USB_D_NAKSTS0_S)
  1795. #define USB_D_NAKSTS0_V 0x00000001
  1796. #define USB_D_NAKSTS0_S 17
  1797. /** USB_D_EPTYPE0 : RO; bitpos: [20:18]; default: 0;
  1798. * Endpoint Type
  1799. * 0x0 : Endpoint Control 0
  1800. */
  1801. #define USB_D_EPTYPE0 0x00000003
  1802. #define USB_D_EPTYPE0_M (USB_D_EPTYPE0_V << USB_D_EPTYPE0_S)
  1803. #define USB_D_EPTYPE0_V 0x00000003
  1804. #define USB_D_EPTYPE0_S 18
  1805. /** USB_D_STALL0 : R/W; bitpos: [21]; default: 0;
  1806. * The application can only set this bit, and the core clears it
  1807. * 0x0 : No Stall
  1808. * 0x1 : Stall Handshake
  1809. */
  1810. #define USB_D_STALL0 (BIT(21))
  1811. #define USB_D_STALL0_M (USB_D_STALL0_V << USB_D_STALL0_S)
  1812. #define USB_D_STALL0_V 0x00000001
  1813. #define USB_D_STALL0_S 21
  1814. /** USB_D_TXFNUM0 : R/W; bitpos: [26:22]; default: 0;
  1815. * TxFIFO Number.
  1816. */
  1817. #define USB_D_TXFNUM0 0x0000000F
  1818. #define USB_D_TXFNUM0_M (USB_D_TXFNUM0_V << USB_D_TXFNUM0_S)
  1819. #define USB_D_TXFNUM0_V 0x0000000F
  1820. #define USB_D_TXFNUM0_S 22
  1821. /** USB_D_CNAK0 : WO; bitpos: [26]; default: 0;
  1822. * A write to this bit clears the NAK bit for the endpoint
  1823. * 0x0 : No action
  1824. * 0x1 : Clear NAK
  1825. */
  1826. #define USB_D_CNAK0 (BIT(26))
  1827. #define USB_D_CNAK0_M (USB_D_CNAK0_V << USB_D_CNAK0_S)
  1828. #define USB_D_CNAK0_V 0x00000001
  1829. #define USB_D_CNAK0_S 26
  1830. /** USB_DI_SNAK0 : WO; bitpos: [27]; default: 0;
  1831. * A write to this bit sets the NAK bit for the endpoint
  1832. * 0x0 : No action
  1833. * 0x1 : Set NAK
  1834. */
  1835. #define USB_DI_SNAK0 (BIT(27))
  1836. #define USB_DI_SNAK0_M (USB_DI_SNAK0_V << USB_DI_SNAK0_S)
  1837. #define USB_DI_SNAK0_V 0x00000001
  1838. #define USB_DI_SNAK0_S 27
  1839. /** USB_D_EPDIS0 : R/W; bitpos: [30]; default: 0;
  1840. * Endpoint Disable
  1841. * 0x0 : No action
  1842. * 0x1 : Disabled Endpoint
  1843. */
  1844. #define USB_D_EPDIS0 (BIT(30))
  1845. #define USB_D_EPDIS0_M (USB_D_EPDIS0_V << USB_D_EPDIS0_S)
  1846. #define USB_D_EPDIS0_V 0x00000001
  1847. #define USB_D_EPDIS0_S 30
  1848. /** USB_D_EPENA0 : R/W; bitpos: [31]; default: 0;
  1849. * Endpoint Enable
  1850. * 0x0 : No action
  1851. * 0x1 : Enable Endpoint
  1852. */
  1853. #define USB_D_EPENA0 (BIT(31))
  1854. #define USB_D_EPENA0_M (USB_D_EPENA0_V << USB_D_EPENA0_S)
  1855. #define USB_D_EPENA0_V 0x00000001
  1856. #define USB_D_EPENA0_S 31
  1857. /** USB_DIEPTSIZ0_REG register
  1858. * Device IN Endpoint 0 Transfer Size Register
  1859. */
  1860. #define USB_DIEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0x910)
  1861. /** USB_D_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0;
  1862. * Transfer Size
  1863. * IN Endpoints: The core decrements this field every time a packet from the external
  1864. * memory is written to the TxFIFO
  1865. * OUT Endpoints: The core decrements this field every time a packet is read from the
  1866. * RxFIFO and written to the external memory
  1867. */
  1868. #define USB_D_XFERSIZE0 0x0000007F
  1869. #define USB_D_XFERSIZE0_M (USB_D_XFERSIZE0_V << USB_D_XFERSIZE0_S)
  1870. #define USB_D_XFERSIZE0_V 0x0000007F
  1871. #define USB_D_XFERSIZE0_S 0
  1872. /** USB_D_PKTCNT0 : R/W; bitpos: [21:19]; default: 0;
  1873. * Packet Count
  1874. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  1875. * packet) is read from the TxFIFO
  1876. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  1877. * packet) is written to the RxFIFO
  1878. */
  1879. #define USB_D_PKTCNT0 0x00000003
  1880. #define USB_D_PKTCNT0_M (USB_D_PKTCNT0_V << USB_D_PKTCNT0_S)
  1881. #define USB_D_PKTCNT0_V 0x00000003
  1882. #define USB_D_PKTCNT0_S 19
  1883. /** USB_DIEPDMA0_REG register
  1884. * Device IN Endpoint 0 DMA Address Register
  1885. */
  1886. #define USB_DIEPDMA0_REG (SOC_DPORT_USB_BASE + 0x914)
  1887. /** USB_D_DMAADDR0 : R/W; bitpos: [32:0]; default: 0;
  1888. * This field holds the start address of the external memory for storing or fetching
  1889. * endpoint data.
  1890. */
  1891. #define USB_D_DMAADDR0 0xFFFFFFFF
  1892. #define USB_D_DMAADDR0_M (USB_D_DMAADDR0_V << USB_D_DMAADDR0_S)
  1893. #define USB_D_DMAADDR0_V 0xFFFFFFFF
  1894. #define USB_D_DMAADDR0_S 0
  1895. /** USB_DIEPCTL1_REG register
  1896. * Device Control IN Endpoint $n Control Register
  1897. */
  1898. #define USB_DIEPCTL1_REG (SOC_DPORT_USB_BASE + 0x920)
  1899. /** USB_D_MPS1 : R/W; bitpos: [2:0]; default: 0;
  1900. * Maximum Packet Size
  1901. * 0x0 : 64 bytes
  1902. * 0x1 : 32 bytes
  1903. * 0x2 : 16 bytes
  1904. * 0x3 : 8 bytes
  1905. */
  1906. #define USB_D_MPS1 0x00000003
  1907. #define USB_D_MPS1_M (USB_D_MPS1_V << USB_D_MPS1_S)
  1908. #define USB_D_MPS1_V 0x00000003
  1909. #define USB_D_MPS1_S 0
  1910. /** USB_D_USBACTEP1 : RO; bitpos: [15]; default: 1;
  1911. * USB Active Endpoint
  1912. * 0x1 : Control endpoint is always active
  1913. */
  1914. #define USB_D_USBACTEP1 (BIT(15))
  1915. #define USB_D_USBACTEP1_M (USB_D_USBACTEP1_V << USB_D_USBACTEP1_S)
  1916. #define USB_D_USBACTEP1_V 0x00000001
  1917. #define USB_D_USBACTEP1_S 15
  1918. /** USB_D_NAKSTS1 : RO; bitpos: [17]; default: 0;
  1919. * NAK Status
  1920. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  1921. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  1922. */
  1923. #define USB_D_NAKSTS1 (BIT(17))
  1924. #define USB_D_NAKSTS1_M (USB_D_NAKSTS1_V << USB_D_NAKSTS1_S)
  1925. #define USB_D_NAKSTS1_V 0x00000001
  1926. #define USB_D_NAKSTS1_S 17
  1927. /** USB_D_EPTYPE1 : RO; bitpos: [20:18]; default: 0;
  1928. * Endpoint Type
  1929. * 0x0 : Endpoint Control 0
  1930. */
  1931. #define USB_D_EPTYPE1 0x00000003
  1932. #define USB_D_EPTYPE1_M (USB_D_EPTYPE1_V << USB_D_EPTYPE1_S)
  1933. #define USB_D_EPTYPE1_V 0x00000003
  1934. #define USB_D_EPTYPE1_S 18
  1935. /** USB_D_STALL1 : R/W; bitpos: [21]; default: 0;
  1936. * The application can only set this bit, and the core clears it
  1937. * 0x0 : No Stall
  1938. * 0x1 : Stall Handshake
  1939. */
  1940. #define USB_D_STALL1 (BIT(21))
  1941. #define USB_D_STALL1_M (USB_D_STALL1_V << USB_D_STALL1_S)
  1942. #define USB_D_STALL1_V 0x00000001
  1943. #define USB_D_STALL1_S 21
  1944. /** USB_D_TXFNUM1 : R/W; bitpos: [26:22]; default: 0;
  1945. * TxFIFO Number.
  1946. */
  1947. #define USB_D_TXFNUM1 0x0000000F
  1948. #define USB_D_TXFNUM1_M (USB_D_TXFNUM1_V << USB_D_TXFNUM1_S)
  1949. #define USB_D_TXFNUM1_V 0x0000000F
  1950. #define USB_D_TXFNUM1_S 22
  1951. /** USB_D_CNAK1 : WO; bitpos: [26]; default: 0;
  1952. * A write to this bit clears the NAK bit for the endpoint
  1953. * 0x0 : No action
  1954. * 0x1 : Clear NAK
  1955. */
  1956. #define USB_D_CNAK1 (BIT(26))
  1957. #define USB_D_CNAK1_M (USB_D_CNAK1_V << USB_D_CNAK1_S)
  1958. #define USB_D_CNAK1_V 0x00000001
  1959. #define USB_D_CNAK1_S 26
  1960. /** USB_DI_SNAK1 : WO; bitpos: [27]; default: 0;
  1961. * A write to this bit sets the NAK bit for the endpoint
  1962. * 0x0 : No action
  1963. * 0x1 : Set NAK
  1964. */
  1965. #define USB_DI_SNAK1 (BIT(27))
  1966. #define USB_DI_SNAK1_M (USB_DI_SNAK1_V << USB_DI_SNAK1_S)
  1967. #define USB_DI_SNAK1_V 0x00000001
  1968. #define USB_DI_SNAK1_S 27
  1969. /** USB_DI_SETD0PID1 : WO; bitpos: [28]; default: 0;
  1970. * Set DATA0 PID
  1971. */
  1972. #define USB_DI_SETD0PID1 (BIT(28))
  1973. #define USB_DI_SETD0PID1_M (USB_DI_SETD0PID1_V << USB_DI_SETD0PID1_S)
  1974. #define USB_DI_SETD0PID1_V 0x00000001
  1975. #define USB_DI_SETD0PID1_S 28
  1976. /** USB_DI_SETD1PID1 : WO; bitpos: [29]; default: 0;
  1977. * Set DATA1 PID
  1978. */
  1979. #define USB_DI_SETD1PID1 (BIT(29))
  1980. #define USB_DI_SETD1PID1_M (USB_DI_SETD1PID1_V << USB_DI_SETD1PID1_S)
  1981. #define USB_DI_SETD1PID1_V 0x00000001
  1982. #define USB_DI_SETD1PID1_S 29
  1983. /** USB_D_EPDIS1 : R/W; bitpos: [30]; default: 0;
  1984. * Endpoint Disable
  1985. * 0x0 : No action
  1986. * 0x1 : Disabled Endpoint
  1987. */
  1988. #define USB_D_EPDIS1 (BIT(30))
  1989. #define USB_D_EPDIS1_M (USB_D_EPDIS1_V << USB_D_EPDIS1_S)
  1990. #define USB_D_EPDIS1_V 0x00000001
  1991. #define USB_D_EPDIS1_S 30
  1992. /** USB_D_EPENA1 : R/W; bitpos: [31]; default: 0;
  1993. * Endpoint Enable
  1994. * 0x0 : No action
  1995. * 0x1 : Enable Endpoint
  1996. */
  1997. #define USB_D_EPENA1 (BIT(31))
  1998. #define USB_D_EPENA1_M (USB_D_EPENA1_V << USB_D_EPENA1_S)
  1999. #define USB_D_EPENA1_V 0x00000001
  2000. #define USB_D_EPENA1_S 31
  2001. /** USB_DIEPTSIZ1_REG register
  2002. * Device IN Endpoint 1 Transfer Size Register
  2003. */
  2004. #define USB_DIEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0x930)
  2005. /** USB_D_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0;
  2006. * Transfer Size
  2007. * IN Endpoints: The core decrements this field every time a packet from the external
  2008. * memory is written to the TxFIFO
  2009. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2010. * RxFIFO and written to the external memory
  2011. */
  2012. #define USB_D_XFERSIZE1 0x0000007F
  2013. #define USB_D_XFERSIZE1_M (USB_D_XFERSIZE1_V << USB_D_XFERSIZE1_S)
  2014. #define USB_D_XFERSIZE1_V 0x0000007F
  2015. #define USB_D_XFERSIZE1_S 0
  2016. /** USB_D_PKTCNT1 : R/W; bitpos: [21:19]; default: 0;
  2017. * Packet Count
  2018. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2019. * packet) is read from the TxFIFO
  2020. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2021. * packet) is written to the RxFIFO
  2022. */
  2023. #define USB_D_PKTCNT1 0x00000003
  2024. #define USB_D_PKTCNT1_M (USB_D_PKTCNT1_V << USB_D_PKTCNT1_S)
  2025. #define USB_D_PKTCNT1_V 0x00000003
  2026. #define USB_D_PKTCNT1_S 19
  2027. /** USB_DIEPDMA1_REG register
  2028. * Device IN Endpoint 1 DMA Address Register
  2029. */
  2030. #define USB_DIEPDMA1_REG (SOC_DPORT_USB_BASE + 0x934)
  2031. /** USB_D_DMAADDR1 : R/W; bitpos: [32:0]; default: 0;
  2032. * This field holds the start address of the external memory for storing or fetching
  2033. * endpoint data.
  2034. */
  2035. #define USB_D_DMAADDR1 0xFFFFFFFF
  2036. #define USB_D_DMAADDR1_M (USB_D_DMAADDR1_V << USB_D_DMAADDR1_S)
  2037. #define USB_D_DMAADDR1_V 0xFFFFFFFF
  2038. #define USB_D_DMAADDR1_S 0
  2039. /** USB_DIEPCTL2_REG register
  2040. * Device Control IN Endpoint 2 Control Register
  2041. */
  2042. #define USB_DIEPCTL2_REG (SOC_DPORT_USB_BASE + 0x940)
  2043. /** USB_D_MPS2 : R/W; bitpos: [2:0]; default: 0;
  2044. * Maximum Packet Size
  2045. * 0x0 : 64 bytes
  2046. * 0x1 : 32 bytes
  2047. * 0x2 : 16 bytes
  2048. * 0x3 : 8 bytes
  2049. */
  2050. #define USB_D_MPS2 0x00000003
  2051. #define USB_D_MPS2_M (USB_D_MPS2_V << USB_D_MPS2_S)
  2052. #define USB_D_MPS2_V 0x00000003
  2053. #define USB_D_MPS2_S 0
  2054. /** USB_D_USBACTEP2 : RO; bitpos: [15]; default: 1;
  2055. * USB Active Endpoint
  2056. * 0x1 : Control endpoint is always active
  2057. */
  2058. #define USB_D_USBACTEP2 (BIT(15))
  2059. #define USB_D_USBACTEP2_M (USB_D_USBACTEP2_V << USB_D_USBACTEP2_S)
  2060. #define USB_D_USBACTEP2_V 0x00000001
  2061. #define USB_D_USBACTEP2_S 15
  2062. /** USB_D_NAKSTS2 : RO; bitpos: [17]; default: 0;
  2063. * NAK Status
  2064. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  2065. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  2066. */
  2067. #define USB_D_NAKSTS2 (BIT(17))
  2068. #define USB_D_NAKSTS2_M (USB_D_NAKSTS2_V << USB_D_NAKSTS2_S)
  2069. #define USB_D_NAKSTS2_V 0x00000001
  2070. #define USB_D_NAKSTS2_S 17
  2071. /** USB_D_EPTYPE2 : RO; bitpos: [20:18]; default: 0;
  2072. * Endpoint Type
  2073. * 0x0 : Endpoint Control 0
  2074. */
  2075. #define USB_D_EPTYPE2 0x00000003
  2076. #define USB_D_EPTYPE2_M (USB_D_EPTYPE2_V << USB_D_EPTYPE2_S)
  2077. #define USB_D_EPTYPE2_V 0x00000003
  2078. #define USB_D_EPTYPE2_S 18
  2079. /** USB_D_STALL2 : R/W; bitpos: [21]; default: 0;
  2080. * The application can only set this bit, and the core clears it
  2081. * 0x0 : No Stall
  2082. * 0x1 : Stall Handshake
  2083. */
  2084. #define USB_D_STALL2 (BIT(21))
  2085. #define USB_D_STALL2_M (USB_D_STALL2_V << USB_D_STALL2_S)
  2086. #define USB_D_STALL2_V 0x00000001
  2087. #define USB_D_STALL2_S 21
  2088. /** USB_D_TXFNUM2 : R/W; bitpos: [26:22]; default: 0;
  2089. * TxFIFO Number.
  2090. */
  2091. #define USB_D_TXFNUM2 0x0000000F
  2092. #define USB_D_TXFNUM2_M (USB_D_TXFNUM2_V << USB_D_TXFNUM2_S)
  2093. #define USB_D_TXFNUM2_V 0x0000000F
  2094. #define USB_D_TXFNUM2_S 22
  2095. /** USB_D_CNAK2 : WO; bitpos: [26]; default: 0;
  2096. * A write to this bit clears the NAK bit for the endpoint
  2097. * 0x0 : No action
  2098. * 0x1 : Clear NAK
  2099. */
  2100. #define USB_D_CNAK2 (BIT(26))
  2101. #define USB_D_CNAK2_M (USB_D_CNAK2_V << USB_D_CNAK2_S)
  2102. #define USB_D_CNAK2_V 0x00000001
  2103. #define USB_D_CNAK2_S 26
  2104. /** USB_DI_SNAK2 : WO; bitpos: [27]; default: 0;
  2105. * A write to this bit sets the NAK bit for the endpoint
  2106. * 0x0 : No action
  2107. * 0x1 : Set NAK
  2108. */
  2109. #define USB_DI_SNAK2 (BIT(27))
  2110. #define USB_DI_SNAK2_M (USB_DI_SNAK2_V << USB_DI_SNAK2_S)
  2111. #define USB_DI_SNAK2_V 0x00000001
  2112. #define USB_DI_SNAK2_S 27
  2113. /** USB_DI_SETD0PID2 : WO; bitpos: [28]; default: 0;
  2114. * Set DATA0 PID
  2115. */
  2116. #define USB_DI_SETD0PID2 (BIT(28))
  2117. #define USB_DI_SETD0PID2_M (USB_DI_SETD0PID2_V << USB_DI_SETD0PID2_S)
  2118. #define USB_DI_SETD0PID2_V 0x00000001
  2119. #define USB_DI_SETD0PID2_S 28
  2120. /** USB_DI_SETD1PID2 : WO; bitpos: [29]; default: 0;
  2121. * Set DATA1 PID
  2122. */
  2123. #define USB_DI_SETD1PID2 (BIT(29))
  2124. #define USB_DI_SETD1PID2_M (USB_DI_SETD1PID2_V << USB_DI_SETD1PID2_S)
  2125. #define USB_DI_SETD1PID2_V 0x00000001
  2126. #define USB_DI_SETD1PID2_S 29
  2127. /** USB_D_EPDIS2 : R/W; bitpos: [30]; default: 0;
  2128. * Endpoint Disable
  2129. * 0x0 : No action
  2130. * 0x1 : Disabled Endpoint
  2131. */
  2132. #define USB_D_EPDIS2 (BIT(30))
  2133. #define USB_D_EPDIS2_M (USB_D_EPDIS2_V << USB_D_EPDIS2_S)
  2134. #define USB_D_EPDIS2_V 0x00000001
  2135. #define USB_D_EPDIS2_S 30
  2136. /** USB_D_EPENA2 : R/W; bitpos: [31]; default: 0;
  2137. * Endpoint Enable
  2138. * 0x0 : No action
  2139. * 0x1 : Enable Endpoint
  2140. */
  2141. #define USB_D_EPENA2 (BIT(31))
  2142. #define USB_D_EPENA2_M (USB_D_EPENA2_V << USB_D_EPENA2_S)
  2143. #define USB_D_EPENA2_V 0x00000001
  2144. #define USB_D_EPENA2_S 31
  2145. /** USB_DIEPTSIZ2_REG register
  2146. * Device IN Endpoint 2 Transfer Size Register
  2147. */
  2148. #define USB_DIEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0x950)
  2149. /** USB_D_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0;
  2150. * Transfer Size
  2151. * IN Endpoints: The core decrements this field every time a packet from the external
  2152. * memory is written to the TxFIFO
  2153. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2154. * RxFIFO and written to the external memory
  2155. */
  2156. #define USB_D_XFERSIZE2 0x0000007F
  2157. #define USB_D_XFERSIZE2_M (USB_D_XFERSIZE2_V << USB_D_XFERSIZE2_S)
  2158. #define USB_D_XFERSIZE2_V 0x0000007F
  2159. #define USB_D_XFERSIZE2_S 0
  2160. /** USB_D_PKTCNT2 : R/W; bitpos: [21:19]; default: 0;
  2161. * Packet Count
  2162. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2163. * packet) is read from the TxFIFO
  2164. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2165. * packet) is written to the RxFIFO
  2166. */
  2167. #define USB_D_PKTCNT2 0x00000003
  2168. #define USB_D_PKTCNT2_M (USB_D_PKTCNT2_V << USB_D_PKTCNT2_S)
  2169. #define USB_D_PKTCNT2_V 0x00000003
  2170. #define USB_D_PKTCNT2_S 19
  2171. /** USB_DIEPDMA2_REG register
  2172. * Device IN Endpoint 2 DMA Address Register
  2173. */
  2174. #define USB_DIEPDMA2_REG (SOC_DPORT_USB_BASE + 0x954)
  2175. /** USB_D_DMAADDR2 : R/W; bitpos: [32:0]; default: 0;
  2176. * This field holds the start address of the external memory for storing or fetching
  2177. * endpoint data.
  2178. */
  2179. #define USB_D_DMAADDR2 0xFFFFFFFF
  2180. #define USB_D_DMAADDR2_M (USB_D_DMAADDR2_V << USB_D_DMAADDR2_S)
  2181. #define USB_D_DMAADDR2_V 0xFFFFFFFF
  2182. #define USB_D_DMAADDR2_S 0
  2183. /** USB_DIEPCTL3_REG register
  2184. * Device Control IN Endpoint $n Control Register
  2185. */
  2186. #define USB_DIEPCTL3_REG (SOC_DPORT_USB_BASE + 0x960)
  2187. /** USB_DI_MPS3 : R/W; bitpos: [2:0]; default: 0;
  2188. * Maximum Packet Size
  2189. * 0x0 : 64 bytes
  2190. * 0x1 : 32 bytes
  2191. * 0x2 : 16 bytes
  2192. * 0x3 : 8 bytes
  2193. */
  2194. #define USB_DI_MPS3 0x00000003
  2195. #define USB_DI_MPS3_M (USB_DI_MPS3_V << USB_DI_MPS3_S)
  2196. #define USB_DI_MPS3_V 0x00000003
  2197. #define USB_DI_MPS3_S 0
  2198. /** USB_DI_USBACTEP3 : RO; bitpos: [15]; default: 1;
  2199. * USB Active Endpoint
  2200. * 0x1 : Control endpoint is always active
  2201. */
  2202. #define USB_DI_USBACTEP3 (BIT(15))
  2203. #define USB_DI_USBACTEP3_M (USB_DI_USBACTEP3_V << USB_DI_USBACTEP3_S)
  2204. #define USB_DI_USBACTEP3_V 0x00000001
  2205. #define USB_DI_USBACTEP3_S 15
  2206. /** USB_DI_NAKSTS3 : RO; bitpos: [17]; default: 0;
  2207. * NAK Status
  2208. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  2209. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  2210. */
  2211. #define USB_DI_NAKSTS3 (BIT(17))
  2212. #define USB_DI_NAKSTS3_M (USB_DI_NAKSTS3_V << USB_DI_NAKSTS3_S)
  2213. #define USB_DI_NAKSTS3_V 0x00000001
  2214. #define USB_DI_NAKSTS3_S 17
  2215. /** USB_DI_EPTYPE3 : RO; bitpos: [20:18]; default: 0;
  2216. * Endpoint Type
  2217. * 0x0 : Endpoint Control 0
  2218. */
  2219. #define USB_DI_EPTYPE3 0x00000003
  2220. #define USB_DI_EPTYPE3_M (USB_DI_EPTYPE3_V << USB_DI_EPTYPE3_S)
  2221. #define USB_DI_EPTYPE3_V 0x00000003
  2222. #define USB_DI_EPTYPE3_S 18
  2223. /** USB_DI_STALL3 : R/W; bitpos: [21]; default: 0;
  2224. * The application can only set this bit, and the core clears it
  2225. * 0x0 : No Stall
  2226. * 0x1 : Stall Handshake
  2227. */
  2228. #define USB_DI_STALL3 (BIT(21))
  2229. #define USB_DI_STALL3_M (USB_DI_STALL3_V << USB_DI_STALL3_S)
  2230. #define USB_DI_STALL3_V 0x00000001
  2231. #define USB_DI_STALL3_S 21
  2232. /** USB_DI_TXFNUM3 : R/W; bitpos: [26:22]; default: 0;
  2233. * TxFIFO Number.
  2234. */
  2235. #define USB_DI_TXFNUM3 0x0000000F
  2236. #define USB_DI_TXFNUM3_M (USB_DI_TXFNUM3_V << USB_DI_TXFNUM3_S)
  2237. #define USB_DI_TXFNUM3_V 0x0000000F
  2238. #define USB_DI_TXFNUM3_S 22
  2239. /** USB_DI_CNAK3 : WO; bitpos: [26]; default: 0;
  2240. * A write to this bit clears the NAK bit for the endpoint
  2241. * 0x0 : No action
  2242. * 0x1 : Clear NAK
  2243. */
  2244. #define USB_DI_CNAK3 (BIT(26))
  2245. #define USB_DI_CNAK3_M (USB_DI_CNAK3_V << USB_DI_CNAK3_S)
  2246. #define USB_DI_CNAK3_V 0x00000001
  2247. #define USB_DI_CNAK3_S 26
  2248. /** USB_DI_SNAK3 : WO; bitpos: [27]; default: 0;
  2249. * A write to this bit sets the NAK bit for the endpoint
  2250. * 0x0 : No action
  2251. * 0x1 : Set NAK
  2252. */
  2253. #define USB_DI_SNAK3 (BIT(27))
  2254. #define USB_DI_SNAK3_M (USB_DI_SNAK3_V << USB_DI_SNAK3_S)
  2255. #define USB_DI_SNAK3_V 0x00000001
  2256. #define USB_DI_SNAK3_S 27
  2257. /** USB_DI_SETD0PID3 : WO; bitpos: [28]; default: 0;
  2258. * Set DATA0 PID
  2259. */
  2260. #define USB_DI_SETD0PID3 (BIT(28))
  2261. #define USB_DI_SETD0PID3_M (USB_DI_SETD0PID3_V << USB_DI_SETD0PID3_S)
  2262. #define USB_DI_SETD0PID3_V 0x00000001
  2263. #define USB_DI_SETD0PID3_S 28
  2264. /** USB_DI_SETD1PID3 : WO; bitpos: [29]; default: 0;
  2265. * Set DATA1 PID
  2266. */
  2267. #define USB_DI_SETD1PID3 (BIT(29))
  2268. #define USB_DI_SETD1PID3_M (USB_DI_SETD1PID3_V << USB_DI_SETD1PID3_S)
  2269. #define USB_DI_SETD1PID3_V 0x00000001
  2270. #define USB_DI_SETD1PID3_S 29
  2271. /** USB_DI_EPDIS3 : R/W; bitpos: [30]; default: 0;
  2272. * Endpoint Disable
  2273. * 0x0 : No action
  2274. * 0x1 : Disabled Endpoint
  2275. */
  2276. #define USB_DI_EPDIS3 (BIT(30))
  2277. #define USB_DI_EPDIS3_M (USB_DI_EPDIS3_V << USB_DI_EPDIS3_S)
  2278. #define USB_DI_EPDIS3_V 0x00000001
  2279. #define USB_DI_EPDIS3_S 30
  2280. /** USB_DI_EPENA3 : R/W; bitpos: [31]; default: 0;
  2281. * Endpoint Enable
  2282. * 0x0 : No action
  2283. * 0x1 : Enable Endpoint
  2284. */
  2285. #define USB_DI_EPENA3 (BIT(31))
  2286. #define USB_DI_EPENA3_M (USB_DI_EPENA3_V << USB_DI_EPENA3_S)
  2287. #define USB_DI_EPENA3_V 0x00000001
  2288. #define USB_DI_EPENA3_S 31
  2289. /** USB_DIEPTSIZ3_REG register
  2290. * Device IN Endpoint 3 Transfer Size Register
  2291. */
  2292. #define USB_DIEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0x970)
  2293. /** USB_D_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0;
  2294. * Transfer Size
  2295. * IN Endpoints: The core decrements this field every time a packet from the external
  2296. * memory is written to the TxFIFO
  2297. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2298. * RxFIFO and written to the external memory
  2299. */
  2300. #define USB_D_XFERSIZE3 0x0000007F
  2301. #define USB_D_XFERSIZE3_M (USB_D_XFERSIZE3_V << USB_D_XFERSIZE3_S)
  2302. #define USB_D_XFERSIZE3_V 0x0000007F
  2303. #define USB_D_XFERSIZE3_S 0
  2304. /** USB_D_PKTCNT3 : R/W; bitpos: [21:19]; default: 0;
  2305. * Packet Count
  2306. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2307. * packet) is read from the TxFIFO
  2308. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2309. * packet) is written to the RxFIFO
  2310. */
  2311. #define USB_D_PKTCNT3 0x00000003
  2312. #define USB_D_PKTCNT3_M (USB_D_PKTCNT3_V << USB_D_PKTCNT3_S)
  2313. #define USB_D_PKTCNT3_V 0x00000003
  2314. #define USB_D_PKTCNT3_S 19
  2315. /** USB_DIEPDMA3_REG register
  2316. * Device IN Endpoint 3 DMA Address Register
  2317. */
  2318. #define USB_DIEPDMA3_REG (SOC_DPORT_USB_BASE + 0x974)
  2319. /** USB_D_DMAADDR3 : R/W; bitpos: [32:0]; default: 0;
  2320. * This field holds the start address of the external memory for storing or fetching
  2321. * endpoint data.
  2322. */
  2323. #define USB_D_DMAADDR3 0xFFFFFFFF
  2324. #define USB_D_DMAADDR3_M (USB_D_DMAADDR3_V << USB_D_DMAADDR3_S)
  2325. #define USB_D_DMAADDR3_V 0xFFFFFFFF
  2326. #define USB_D_DMAADDR3_S 0
  2327. /** USB_DIEPCTL4_REG register
  2328. * Device Control IN Endpoint $n Control Register
  2329. */
  2330. #define USB_DIEPCTL4_REG (SOC_DPORT_USB_BASE + 0x980)
  2331. /** USB_D_MPS4 : R/W; bitpos: [2:0]; default: 0;
  2332. * Maximum Packet Size
  2333. * 0x0 : 64 bytes
  2334. * 0x1 : 32 bytes
  2335. * 0x2 : 16 bytes
  2336. * 0x3 : 8 bytes
  2337. */
  2338. #define USB_D_MPS4 0x00000003
  2339. #define USB_D_MPS4_M (USB_D_MPS4_V << USB_D_MPS4_S)
  2340. #define USB_D_MPS4_V 0x00000003
  2341. #define USB_D_MPS4_S 0
  2342. /** USB_D_USBACTEP4 : RO; bitpos: [15]; default: 1;
  2343. * USB Active Endpoint
  2344. * 0x1 : Control endpoint is always active
  2345. */
  2346. #define USB_D_USBACTEP4 (BIT(15))
  2347. #define USB_D_USBACTEP4_M (USB_D_USBACTEP4_V << USB_D_USBACTEP4_S)
  2348. #define USB_D_USBACTEP4_V 0x00000001
  2349. #define USB_D_USBACTEP4_S 15
  2350. /** USB_D_NAKSTS4 : RO; bitpos: [17]; default: 0;
  2351. * NAK Status
  2352. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  2353. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  2354. */
  2355. #define USB_D_NAKSTS4 (BIT(17))
  2356. #define USB_D_NAKSTS4_M (USB_D_NAKSTS4_V << USB_D_NAKSTS4_S)
  2357. #define USB_D_NAKSTS4_V 0x00000001
  2358. #define USB_D_NAKSTS4_S 17
  2359. /** USB_D_EPTYPE4 : RO; bitpos: [20:18]; default: 0;
  2360. * Endpoint Type
  2361. * 0x0 : Endpoint Control 0
  2362. */
  2363. #define USB_D_EPTYPE4 0x00000003
  2364. #define USB_D_EPTYPE4_M (USB_D_EPTYPE4_V << USB_D_EPTYPE4_S)
  2365. #define USB_D_EPTYPE4_V 0x00000003
  2366. #define USB_D_EPTYPE4_S 18
  2367. /** USB_D_STALL4 : R/W; bitpos: [21]; default: 0;
  2368. * The application can only set this bit, and the core clears it
  2369. * 0x0 : No Stall
  2370. * 0x1 : Stall Handshake
  2371. */
  2372. #define USB_D_STALL4 (BIT(21))
  2373. #define USB_D_STALL4_M (USB_D_STALL4_V << USB_D_STALL4_S)
  2374. #define USB_D_STALL4_V 0x00000001
  2375. #define USB_D_STALL4_S 21
  2376. /** USB_D_TXFNUM4 : R/W; bitpos: [26:22]; default: 0;
  2377. * TxFIFO Number.
  2378. */
  2379. #define USB_D_TXFNUM4 0x0000000F
  2380. #define USB_D_TXFNUM4_M (USB_D_TXFNUM4_V << USB_D_TXFNUM4_S)
  2381. #define USB_D_TXFNUM4_V 0x0000000F
  2382. #define USB_D_TXFNUM4_S 22
  2383. /** USB_D_CNAK4 : WO; bitpos: [26]; default: 0;
  2384. * A write to this bit clears the NAK bit for the endpoint
  2385. * 0x0 : No action
  2386. * 0x1 : Clear NAK
  2387. */
  2388. #define USB_D_CNAK4 (BIT(26))
  2389. #define USB_D_CNAK4_M (USB_D_CNAK4_V << USB_D_CNAK4_S)
  2390. #define USB_D_CNAK4_V 0x00000001
  2391. #define USB_D_CNAK4_S 26
  2392. /** USB_DI_SNAK4 : WO; bitpos: [27]; default: 0;
  2393. * A write to this bit sets the NAK bit for the endpoint
  2394. * 0x0 : No action
  2395. * 0x1 : Set NAK
  2396. */
  2397. #define USB_DI_SNAK4 (BIT(27))
  2398. #define USB_DI_SNAK4_M (USB_DI_SNAK4_V << USB_DI_SNAK4_S)
  2399. #define USB_DI_SNAK4_V 0x00000001
  2400. #define USB_DI_SNAK4_S 27
  2401. /** USB_DI_SETD0PID4 : WO; bitpos: [28]; default: 0;
  2402. * Set DATA0 PID
  2403. */
  2404. #define USB_DI_SETD0PID4 (BIT(28))
  2405. #define USB_DI_SETD0PID4_M (USB_DI_SETD0PID4_V << USB_DI_SETD0PID4_S)
  2406. #define USB_DI_SETD0PID4_V 0x00000001
  2407. #define USB_DI_SETD0PID4_S 28
  2408. /** USB_DI_SETD1PID4 : WO; bitpos: [29]; default: 0;
  2409. * Set DATA1 PID
  2410. */
  2411. #define USB_DI_SETD1PID4 (BIT(29))
  2412. #define USB_DI_SETD1PID4_M (USB_DI_SETD1PID4_V << USB_DI_SETD1PID4_S)
  2413. #define USB_DI_SETD1PID4_V 0x00000001
  2414. #define USB_DI_SETD1PID4_S 29
  2415. /** USB_D_EPDIS4 : R/W; bitpos: [30]; default: 0;
  2416. * Endpoint Disable
  2417. * 0x0 : No action
  2418. * 0x1 : Disabled Endpoint
  2419. */
  2420. #define USB_D_EPDIS4 (BIT(30))
  2421. #define USB_D_EPDIS4_M (USB_D_EPDIS4_V << USB_D_EPDIS4_S)
  2422. #define USB_D_EPDIS4_V 0x00000001
  2423. #define USB_D_EPDIS4_S 30
  2424. /** USB_D_EPENA4 : R/W; bitpos: [31]; default: 0;
  2425. * Endpoint Enable
  2426. * 0x0 : No action
  2427. * 0x1 : Enable Endpoint
  2428. */
  2429. #define USB_D_EPENA4 (BIT(31))
  2430. #define USB_D_EPENA4_M (USB_D_EPENA4_V << USB_D_EPENA4_S)
  2431. #define USB_D_EPENA4_V 0x00000001
  2432. #define USB_D_EPENA4_S 31
  2433. /** USB_DIEPTSIZ4_REG register
  2434. * Device IN Endpoint 4 Transfer Size Register
  2435. */
  2436. #define USB_DIEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0x990)
  2437. /** USB_D_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0;
  2438. * Transfer Size
  2439. * IN Endpoints: The core decrements this field every time a packet from the external
  2440. * memory is written to the TxFIFO
  2441. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2442. * RxFIFO and written to the external memory
  2443. */
  2444. #define USB_D_XFERSIZE4 0x0000007F
  2445. #define USB_D_XFERSIZE4_M (USB_D_XFERSIZE4_V << USB_D_XFERSIZE4_S)
  2446. #define USB_D_XFERSIZE4_V 0x0000007F
  2447. #define USB_D_XFERSIZE4_S 0
  2448. /** USB_D_PKTCNT4 : R/W; bitpos: [21:19]; default: 0;
  2449. * Packet Count
  2450. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2451. * packet) is read from the TxFIFO
  2452. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2453. * packet) is written to the RxFIFO
  2454. */
  2455. #define USB_D_PKTCNT4 0x00000003
  2456. #define USB_D_PKTCNT4_M (USB_D_PKTCNT4_V << USB_D_PKTCNT4_S)
  2457. #define USB_D_PKTCNT4_V 0x00000003
  2458. #define USB_D_PKTCNT4_S 19
  2459. /** USB_DIEPDMA4_REG register
  2460. * Device IN Endpoint 4 DMA Address Register
  2461. */
  2462. #define USB_DIEPDMA4_REG (SOC_DPORT_USB_BASE + 0x994)
  2463. /** USB_D_DMAADDR4 : R/W; bitpos: [32:0]; default: 0;
  2464. * This field holds the start address of the external memory for storing or fetching
  2465. * endpoint data.
  2466. */
  2467. #define USB_D_DMAADDR4 0xFFFFFFFF
  2468. #define USB_D_DMAADDR4_M (USB_D_DMAADDR4_V << USB_D_DMAADDR4_S)
  2469. #define USB_D_DMAADDR4_V 0xFFFFFFFF
  2470. #define USB_D_DMAADDR4_S 0
  2471. /** USB_DIEPCTL5_REG register
  2472. * Device Control IN Endpoint $n Control Register
  2473. */
  2474. #define USB_DIEPCTL5_REG (SOC_DPORT_USB_BASE + 0x9a0)
  2475. /** USB_DI_MPS5 : R/W; bitpos: [2:0]; default: 0;
  2476. * Maximum Packet Size
  2477. * 0x0 : 64 bytes
  2478. * 0x1 : 32 bytes
  2479. * 0x2 : 16 bytes
  2480. * 0x3 : 8 bytes
  2481. */
  2482. #define USB_DI_MPS5 0x00000003
  2483. #define USB_DI_MPS5_M (USB_DI_MPS5_V << USB_DI_MPS5_S)
  2484. #define USB_DI_MPS5_V 0x00000003
  2485. #define USB_DI_MPS5_S 0
  2486. /** USB_DI_USBACTEP5 : RO; bitpos: [15]; default: 1;
  2487. * USB Active Endpoint
  2488. * 0x1 : Control endpoint is always active
  2489. */
  2490. #define USB_DI_USBACTEP5 (BIT(15))
  2491. #define USB_DI_USBACTEP5_M (USB_DI_USBACTEP5_V << USB_DI_USBACTEP5_S)
  2492. #define USB_DI_USBACTEP5_V 0x00000001
  2493. #define USB_DI_USBACTEP5_S 15
  2494. /** USB_DI_NAKSTS5 : RO; bitpos: [17]; default: 0;
  2495. * NAK Status
  2496. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  2497. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  2498. */
  2499. #define USB_DI_NAKSTS5 (BIT(17))
  2500. #define USB_DI_NAKSTS5_M (USB_DI_NAKSTS5_V << USB_DI_NAKSTS5_S)
  2501. #define USB_DI_NAKSTS5_V 0x00000001
  2502. #define USB_DI_NAKSTS5_S 17
  2503. /** USB_DI_EPTYPE5 : RO; bitpos: [20:18]; default: 0;
  2504. * Endpoint Type
  2505. * 0x0 : Endpoint Control 0
  2506. */
  2507. #define USB_DI_EPTYPE5 0x00000003
  2508. #define USB_DI_EPTYPE5_M (USB_DI_EPTYPE5_V << USB_DI_EPTYPE5_S)
  2509. #define USB_DI_EPTYPE5_V 0x00000003
  2510. #define USB_DI_EPTYPE5_S 18
  2511. /** USB_DI_STALL5 : R/W; bitpos: [21]; default: 0;
  2512. * The application can only set this bit, and the core clears it
  2513. * 0x0 : No Stall
  2514. * 0x1 : Stall Handshake
  2515. */
  2516. #define USB_DI_STALL5 (BIT(21))
  2517. #define USB_DI_STALL5_M (USB_DI_STALL5_V << USB_DI_STALL5_S)
  2518. #define USB_DI_STALL5_V 0x00000001
  2519. #define USB_DI_STALL5_S 21
  2520. /** USB_DI_TXFNUM5 : R/W; bitpos: [26:22]; default: 0;
  2521. * TxFIFO Number.
  2522. */
  2523. #define USB_DI_TXFNUM5 0x0000000F
  2524. #define USB_DI_TXFNUM5_M (USB_DI_TXFNUM5_V << USB_DI_TXFNUM5_S)
  2525. #define USB_DI_TXFNUM5_V 0x0000000F
  2526. #define USB_DI_TXFNUM5_S 22
  2527. /** USB_DI_CNAK5 : WO; bitpos: [26]; default: 0;
  2528. * A write to this bit clears the NAK bit for the endpoint
  2529. * 0x0 : No action
  2530. * 0x1 : Clear NAK
  2531. */
  2532. #define USB_DI_CNAK5 (BIT(26))
  2533. #define USB_DI_CNAK5_M (USB_DI_CNAK5_V << USB_DI_CNAK5_S)
  2534. #define USB_DI_CNAK5_V 0x00000001
  2535. #define USB_DI_CNAK5_S 26
  2536. /** USB_DI_SNAK5 : WO; bitpos: [27]; default: 0;
  2537. * A write to this bit sets the NAK bit for the endpoint
  2538. * 0x0 : No action
  2539. * 0x1 : Set NAK
  2540. */
  2541. #define USB_DI_SNAK5 (BIT(27))
  2542. #define USB_DI_SNAK5_M (USB_DI_SNAK5_V << USB_DI_SNAK5_S)
  2543. #define USB_DI_SNAK5_V 0x00000001
  2544. #define USB_DI_SNAK5_S 27
  2545. /** USB_DI_SETD0PID5 : WO; bitpos: [28]; default: 0;
  2546. * Set DATA0 PID
  2547. */
  2548. #define USB_DI_SETD0PID5 (BIT(28))
  2549. #define USB_DI_SETD0PID5_M (USB_DI_SETD0PID5_V << USB_DI_SETD0PID5_S)
  2550. #define USB_DI_SETD0PID5_V 0x00000001
  2551. #define USB_DI_SETD0PID5_S 28
  2552. /** USB_DI_SETD1PID5 : WO; bitpos: [29]; default: 0;
  2553. * Set DATA1 PID
  2554. */
  2555. #define USB_DI_SETD1PID5 (BIT(29))
  2556. #define USB_DI_SETD1PID5_M (USB_DI_SETD1PID5_V << USB_DI_SETD1PID5_S)
  2557. #define USB_DI_SETD1PID5_V 0x00000001
  2558. #define USB_DI_SETD1PID5_S 29
  2559. /** USB_DI_EPDIS5 : R/W; bitpos: [30]; default: 0;
  2560. * Endpoint Disable
  2561. * 0x0 : No action
  2562. * 0x1 : Disabled Endpoint
  2563. */
  2564. #define USB_DI_EPDIS5 (BIT(30))
  2565. #define USB_DI_EPDIS5_M (USB_DI_EPDIS5_V << USB_DI_EPDIS5_S)
  2566. #define USB_DI_EPDIS5_V 0x00000001
  2567. #define USB_DI_EPDIS5_S 30
  2568. /** USB_DI_EPENA5 : R/W; bitpos: [31]; default: 0;
  2569. * Endpoint Enable
  2570. * 0x0 : No action
  2571. * 0x1 : Enable Endpoint
  2572. */
  2573. #define USB_DI_EPENA5 (BIT(31))
  2574. #define USB_DI_EPENA5_M (USB_DI_EPENA5_V << USB_DI_EPENA5_S)
  2575. #define USB_DI_EPENA5_V 0x00000001
  2576. #define USB_DI_EPENA5_S 31
  2577. /** USB_DIEPTSIZ5_REG register
  2578. * Device IN Endpoint 5 Transfer Size Register
  2579. */
  2580. #define USB_DIEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0x9b0)
  2581. /** USB_D_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0;
  2582. * Transfer Size
  2583. * IN Endpoints: The core decrements this field every time a packet from the external
  2584. * memory is written to the TxFIFO
  2585. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2586. * RxFIFO and written to the external memory
  2587. */
  2588. #define USB_D_XFERSIZE5 0x0000007F
  2589. #define USB_D_XFERSIZE5_M (USB_D_XFERSIZE5_V << USB_D_XFERSIZE5_S)
  2590. #define USB_D_XFERSIZE5_V 0x0000007F
  2591. #define USB_D_XFERSIZE5_S 0
  2592. /** USB_D_PKTCNT5 : R/W; bitpos: [21:19]; default: 0;
  2593. * Packet Count
  2594. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2595. * packet) is read from the TxFIFO
  2596. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2597. * packet) is written to the RxFIFO
  2598. */
  2599. #define USB_D_PKTCNT5 0x00000003
  2600. #define USB_D_PKTCNT5_M (USB_D_PKTCNT5_V << USB_D_PKTCNT5_S)
  2601. #define USB_D_PKTCNT5_V 0x00000003
  2602. #define USB_D_PKTCNT5_S 19
  2603. /** USB_DIEPDMA5_REG register
  2604. * Device IN Endpoint 5 DMA Address Register
  2605. */
  2606. #define USB_DIEPDMA5_REG (SOC_DPORT_USB_BASE + 0x9b4)
  2607. /** USB_D_DMAADDR5 : R/W; bitpos: [32:0]; default: 0;
  2608. * This field holds the start address of the external memory for storing or fetching
  2609. * endpoint data.
  2610. */
  2611. #define USB_D_DMAADDR5 0xFFFFFFFF
  2612. #define USB_D_DMAADDR5_M (USB_D_DMAADDR5_V << USB_D_DMAADDR5_S)
  2613. #define USB_D_DMAADDR5_V 0xFFFFFFFF
  2614. #define USB_D_DMAADDR5_S 0
  2615. /** USB_DIEPCTL6_REG register
  2616. * Device Control IN Endpoint $n Control Register
  2617. */
  2618. #define USB_DIEPCTL6_REG (SOC_DPORT_USB_BASE + 0x9c0)
  2619. /** USB_D_MPS6 : R/W; bitpos: [2:0]; default: 0;
  2620. * Maximum Packet Size
  2621. * 0x0 : 64 bytes
  2622. * 0x1 : 32 bytes
  2623. * 0x2 : 16 bytes
  2624. * 0x3 : 8 bytes
  2625. */
  2626. #define USB_D_MPS6 0x00000003
  2627. #define USB_D_MPS6_M (USB_D_MPS6_V << USB_D_MPS6_S)
  2628. #define USB_D_MPS6_V 0x00000003
  2629. #define USB_D_MPS6_S 0
  2630. /** USB_D_USBACTEP6 : RO; bitpos: [15]; default: 1;
  2631. * USB Active Endpoint
  2632. * 0x1 : Control endpoint is always active
  2633. */
  2634. #define USB_D_USBACTEP6 (BIT(15))
  2635. #define USB_D_USBACTEP6_M (USB_D_USBACTEP6_V << USB_D_USBACTEP6_S)
  2636. #define USB_D_USBACTEP6_V 0x00000001
  2637. #define USB_D_USBACTEP6_S 15
  2638. /** USB_D_NAKSTS6 : RO; bitpos: [17]; default: 0;
  2639. * NAK Status
  2640. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status
  2641. * 0x1 : The core is transmitting NAK handshakes on this endpoint
  2642. */
  2643. #define USB_D_NAKSTS6 (BIT(17))
  2644. #define USB_D_NAKSTS6_M (USB_D_NAKSTS6_V << USB_D_NAKSTS6_S)
  2645. #define USB_D_NAKSTS6_V 0x00000001
  2646. #define USB_D_NAKSTS6_S 17
  2647. /** USB_D_EPTYPE6 : RO; bitpos: [20:18]; default: 0;
  2648. * Endpoint Type
  2649. * 0x0 : Endpoint Control 0
  2650. */
  2651. #define USB_D_EPTYPE6 0x00000003
  2652. #define USB_D_EPTYPE6_M (USB_D_EPTYPE6_V << USB_D_EPTYPE6_S)
  2653. #define USB_D_EPTYPE6_V 0x00000003
  2654. #define USB_D_EPTYPE6_S 18
  2655. /** USB_D_STALL6 : R/W; bitpos: [21]; default: 0;
  2656. * The application can only set this bit, and the core clears it
  2657. * 0x0 : No Stall
  2658. * 0x1 : Stall Handshake
  2659. */
  2660. #define USB_D_STALL6 (BIT(21))
  2661. #define USB_D_STALL6_M (USB_D_STALL6_V << USB_D_STALL6_S)
  2662. #define USB_D_STALL6_V 0x00000001
  2663. #define USB_D_STALL6_S 21
  2664. /** USB_D_TXFNUM6 : R/W; bitpos: [26:22]; default: 0;
  2665. * TxFIFO Number.
  2666. */
  2667. #define USB_D_TXFNUM6 0x0000000F
  2668. #define USB_D_TXFNUM6_M (USB_D_TXFNUM6_V << USB_D_TXFNUM6_S)
  2669. #define USB_D_TXFNUM6_V 0x0000000F
  2670. #define USB_D_TXFNUM6_S 22
  2671. /** USB_D_CNAK6 : WO; bitpos: [26]; default: 0;
  2672. * A write to this bit clears the NAK bit for the endpoint
  2673. * 0x0 : No action
  2674. * 0x1 : Clear NAK
  2675. */
  2676. #define USB_D_CNAK6 (BIT(26))
  2677. #define USB_D_CNAK6_M (USB_D_CNAK6_V << USB_D_CNAK6_S)
  2678. #define USB_D_CNAK6_V 0x00000001
  2679. #define USB_D_CNAK6_S 26
  2680. /** USB_DI_SNAK6 : WO; bitpos: [27]; default: 0;
  2681. * A write to this bit sets the NAK bit for the endpoint
  2682. * 0x0 : No action
  2683. * 0x1 : Set NAK
  2684. */
  2685. #define USB_DI_SNAK6 (BIT(27))
  2686. #define USB_DI_SNAK6_M (USB_DI_SNAK6_V << USB_DI_SNAK6_S)
  2687. #define USB_DI_SNAK6_V 0x00000001
  2688. #define USB_DI_SNAK6_S 27
  2689. /** USB_DI_SETD0PID6 : WO; bitpos: [28]; default: 0;
  2690. * Set DATA0 PID
  2691. */
  2692. #define USB_DI_SETD0PID6 (BIT(28))
  2693. #define USB_DI_SETD0PID6_M (USB_DI_SETD0PID6_V << USB_DI_SETD0PID6_S)
  2694. #define USB_DI_SETD0PID6_V 0x00000001
  2695. #define USB_DI_SETD0PID6_S 28
  2696. /** USB_DI_SETD1PID6 : WO; bitpos: [29]; default: 0;
  2697. * Set DATA1 PID
  2698. */
  2699. #define USB_DI_SETD1PID6 (BIT(29))
  2700. #define USB_DI_SETD1PID6_M (USB_DI_SETD1PID6_V << USB_DI_SETD1PID6_S)
  2701. #define USB_DI_SETD1PID6_V 0x00000001
  2702. #define USB_DI_SETD1PID6_S 29
  2703. /** USB_D_EPDIS6 : R/W; bitpos: [30]; default: 0;
  2704. * Endpoint Disable
  2705. * 0x0 : No action
  2706. * 0x1 : Disabled Endpoint
  2707. */
  2708. #define USB_D_EPDIS6 (BIT(30))
  2709. #define USB_D_EPDIS6_M (USB_D_EPDIS6_V << USB_D_EPDIS6_S)
  2710. #define USB_D_EPDIS6_V 0x00000001
  2711. #define USB_D_EPDIS6_S 30
  2712. /** USB_D_EPENA6 : R/W; bitpos: [31]; default: 0;
  2713. * Endpoint Enable
  2714. * 0x0 : No action
  2715. * 0x1 : Enable Endpoint
  2716. */
  2717. #define USB_D_EPENA6 (BIT(31))
  2718. #define USB_D_EPENA6_M (USB_D_EPENA6_V << USB_D_EPENA6_S)
  2719. #define USB_D_EPENA6_V 0x00000001
  2720. #define USB_D_EPENA6_S 31
  2721. /** USB_DIEPTSIZ6_REG register
  2722. * Device IN Endpoint 6 Transfer Size Register
  2723. */
  2724. #define USB_DIEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0x9d0)
  2725. /** USB_D_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0;
  2726. * Transfer Size
  2727. * IN Endpoints: The core decrements this field every time a packet from the external
  2728. * memory is written to the TxFIFO
  2729. * OUT Endpoints: The core decrements this field every time a packet is read from the
  2730. * RxFIFO and written to the external memory
  2731. */
  2732. #define USB_D_XFERSIZE6 0x0000007F
  2733. #define USB_D_XFERSIZE6_M (USB_D_XFERSIZE6_V << USB_D_XFERSIZE6_S)
  2734. #define USB_D_XFERSIZE6_V 0x0000007F
  2735. #define USB_D_XFERSIZE6_S 0
  2736. /** USB_D_PKTCNT6 : R/W; bitpos: [21:19]; default: 0;
  2737. * Packet Count
  2738. * IN Endpoints : This field is decremented every time a packet (maximum size or short
  2739. * packet) is read from the TxFIFO
  2740. * OUT Endpoints: This field is decremented every time a packet (maximum size or short
  2741. * packet) is written to the RxFIFO
  2742. */
  2743. #define USB_D_PKTCNT6 0x00000003
  2744. #define USB_D_PKTCNT6_M (USB_D_PKTCNT6_V << USB_D_PKTCNT6_S)
  2745. #define USB_D_PKTCNT6_V 0x00000003
  2746. #define USB_D_PKTCNT6_S 19
  2747. /** USB_DIEPDMA6_REG register
  2748. * Device IN Endpoint 6 DMA Address Register
  2749. */
  2750. #define USB_DIEPDMA6_REG (SOC_DPORT_USB_BASE + 0x9d4)
  2751. /** USB_D_DMAADDR6 : R/W; bitpos: [32:0]; default: 0;
  2752. * This field holds the start address of the external memory for storing or fetching
  2753. * endpoint data.
  2754. */
  2755. #define USB_D_DMAADDR6 0xFFFFFFFF
  2756. #define USB_D_DMAADDR6_M (USB_D_DMAADDR6_V << USB_D_DMAADDR6_S)
  2757. #define USB_D_DMAADDR6_V 0xFFFFFFFF
  2758. #define USB_D_DMAADDR6_S 0
  2759. /** USB_DOEPCTL0_REG register
  2760. * Device Control OUT Endpoint $n Control Register
  2761. */
  2762. #define USB_DOEPCTL0_REG (SOC_DPORT_USB_BASE + 0xb00)
  2763. /** USB_MPS0 : RO; bitpos: [2:0]; default: 0;
  2764. * Maximum Packet Size
  2765. * 0x0 : 64 bytes
  2766. * 0x1 : 32 bytes
  2767. * 0x2 : 16 bytes
  2768. * 0x3 : 8 bytes
  2769. */
  2770. #define USB_MPS0 0x00000003
  2771. #define USB_MPS0_M (USB_MPS0_V << USB_MPS0_S)
  2772. #define USB_MPS0_V 0x00000003
  2773. #define USB_MPS0_S 0
  2774. /** USB_USBACTEP0 : RO; bitpos: [15]; default: 1;
  2775. * 0x1: USB Active Endpoint 0
  2776. */
  2777. #define USB_USBACTEP0 (BIT(15))
  2778. #define USB_USBACTEP0_M (USB_USBACTEP0_V << USB_USBACTEP0_S)
  2779. #define USB_USBACTEP0_V 0x00000001
  2780. #define USB_USBACTEP0_S 15
  2781. /** USB_NAKSTS0 : RO; bitpos: [17]; default: 0;
  2782. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  2783. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  2784. */
  2785. #define USB_NAKSTS0 (BIT(17))
  2786. #define USB_NAKSTS0_M (USB_NAKSTS0_V << USB_NAKSTS0_S)
  2787. #define USB_NAKSTS0_V 0x00000001
  2788. #define USB_NAKSTS0_S 17
  2789. /** USB_EPTYPE0 : RO; bitpos: [20:18]; default: 0;
  2790. * Endpoint Type
  2791. * 0x0 : Endpoint Control $n
  2792. */
  2793. #define USB_EPTYPE0 0x00000003
  2794. #define USB_EPTYPE0_M (USB_EPTYPE0_V << USB_EPTYPE0_S)
  2795. #define USB_EPTYPE0_V 0x00000003
  2796. #define USB_EPTYPE0_S 18
  2797. /** USB_SNP0 : R/W; bitpos: [20]; default: 0;
  2798. * 0x0 : Reserved 0
  2799. * 0x1 : Reserved 1
  2800. */
  2801. #define USB_SNP0 (BIT(20))
  2802. #define USB_SNP0_M (USB_SNP0_V << USB_SNP0_S)
  2803. #define USB_SNP0_V 0x00000001
  2804. #define USB_SNP0_S 20
  2805. /** USB_STALL0 : R/W; bitpos: [21]; default: 0;
  2806. * The application can only set this bit, and the core clears it, when a SETUP token
  2807. * is received for this endpoint
  2808. * 0x0 (INACTIVE): No Stall
  2809. * 0x1 (ACTIVE): Stall Handshake
  2810. */
  2811. #define USB_STALL0 (BIT(21))
  2812. #define USB_STALL0_M (USB_STALL0_V << USB_STALL0_S)
  2813. #define USB_STALL0_V 0x00000001
  2814. #define USB_STALL0_S 21
  2815. /** USB_CNAK0 : WO; bitpos: [26]; default: 0;
  2816. * 0x0 : No action
  2817. * 0x1 : Clear NAK
  2818. */
  2819. #define USB_CNAK0 (BIT(26))
  2820. #define USB_CNAK0_M (USB_CNAK0_V << USB_CNAK0_S)
  2821. #define USB_CNAK0_V 0x00000001
  2822. #define USB_CNAK0_S 26
  2823. /** USB_DO_SNAK0 : WO; bitpos: [27]; default: 0;
  2824. * 0x0 : No action
  2825. * 0x1 : Set NAK
  2826. */
  2827. #define USB_DO_SNAK0 (BIT(27))
  2828. #define USB_DO_SNAK0_M (USB_DO_SNAK0_V << USB_DO_SNAK0_S)
  2829. #define USB_DO_SNAK0_V 0x00000001
  2830. #define USB_DO_SNAK0_S 27
  2831. /** USB_EPDIS0 : RO; bitpos: [30]; default: 0;
  2832. * Endpoint Disable
  2833. * 0x0 : No Endpoint disable
  2834. */
  2835. #define USB_EPDIS0 (BIT(30))
  2836. #define USB_EPDIS0_M (USB_EPDIS0_V << USB_EPDIS0_S)
  2837. #define USB_EPDIS0_V 0x00000001
  2838. #define USB_EPDIS0_S 30
  2839. /** USB_EPENA0 : R/W; bitpos: [31]; default: 0;
  2840. * Endpoint Enable
  2841. * 0x0 : No action
  2842. * 0x1 : Enable Endpoint
  2843. */
  2844. #define USB_EPENA0 (BIT(31))
  2845. #define USB_EPENA0_M (USB_EPENA0_V << USB_EPENA0_S)
  2846. #define USB_EPENA0_V 0x00000001
  2847. #define USB_EPENA0_S 31
  2848. /** USB_DOEPTSIZ0_REG register
  2849. * Device OUT Endpoint 0 Transfer Size Register
  2850. */
  2851. #define USB_DOEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0xb10)
  2852. /** USB_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0;
  2853. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT0
  2854. */
  2855. #define USB_XFERSIZE0 0x0000007F
  2856. #define USB_XFERSIZE0_M (USB_XFERSIZE0_V << USB_XFERSIZE0_S)
  2857. #define USB_XFERSIZE0_V 0x0000007F
  2858. #define USB_XFERSIZE0_S 0
  2859. /** USB_PKTCNT0 : R/W; bitpos: [19]; default: 0;
  2860. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  2861. * into the RxFIFO.
  2862. */
  2863. #define USB_PKTCNT0 (BIT(19))
  2864. #define USB_PKTCNT0_M (USB_PKTCNT0_V << USB_PKTCNT0_S)
  2865. #define USB_PKTCNT0_V 0x00000001
  2866. #define USB_PKTCNT0_S 19
  2867. /** USB_SUPCNT0 : R/W; bitpos: [31:29]; default: 0;
  2868. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  2869. * data packets the endpoint can receive
  2870. * 2'b01: 1 packet
  2871. * 2'b10: 2 packets
  2872. * 2'b11: 3 packets
  2873. */
  2874. #define USB_SUPCNT0 0x00000003
  2875. #define USB_SUPCNT0_M (USB_SUPCNT0_V << USB_SUPCNT0_S)
  2876. #define USB_SUPCNT0_V 0x00000003
  2877. #define USB_SUPCNT0_S 29
  2878. /** USB_DOEPDMA0_REG register
  2879. * Device OUT Endpoint 0 DMA Address Register
  2880. */
  2881. #define USB_DOEPDMA0_REG (SOC_DPORT_USB_BASE + 0xb14)
  2882. /** USB_DMAADDR0 : R/W; bitpos: [32:0]; default: 0;
  2883. * Holds the start address of the external memory for storing or fetching endpoint
  2884. * data.
  2885. */
  2886. #define USB_DMAADDR0 0xFFFFFFFF
  2887. #define USB_DMAADDR0_M (USB_DMAADDR0_V << USB_DMAADDR0_S)
  2888. #define USB_DMAADDR0_V 0xFFFFFFFF
  2889. #define USB_DMAADDR0_S 0
  2890. /** USB_DOEPDMAB0_REG register
  2891. * Device OUT Endpoint 16 Buffer Address Register
  2892. */
  2893. #define USB_DOEPDMAB0_REG (SOC_DPORT_USB_BASE + 0xb1c)
  2894. /** USB_DMABUFFERADDR0 : R/W; bitpos: [32:0]; default: 0;
  2895. * Holds the current buffer address.This register is updated as and when the data
  2896. * transfer for the corresponding end point is in progress. This register is present
  2897. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  2898. */
  2899. #define USB_DMABUFFERADDR0 0xFFFFFFFF
  2900. #define USB_DMABUFFERADDR0_M (USB_DMABUFFERADDR0_V << USB_DMABUFFERADDR0_S)
  2901. #define USB_DMABUFFERADDR0_V 0xFFFFFFFF
  2902. #define USB_DMABUFFERADDR0_S 0
  2903. /** USB_DOEPCTL1_REG register
  2904. * Device Control OUT Endpoint 1 Control Register
  2905. */
  2906. #define USB_DOEPCTL1_REG (SOC_DPORT_USB_BASE + 0xb20)
  2907. /** USB_MPS1 : RO; bitpos: [11:0]; default: 0;
  2908. * Maximum Packet Size in bytes
  2909. */
  2910. #define USB_MPS1 0x000007FF
  2911. #define USB_MPS1_M (USB_MPS1_V << USB_MPS1_S)
  2912. #define USB_MPS1_V 0x000007FF
  2913. #define USB_MPS1_S 0
  2914. /** USB_USBACTEP1 : RO; bitpos: [15]; default: 1;
  2915. * 0x1: USB Active Endpoint 0
  2916. */
  2917. #define USB_USBACTEP1 (BIT(15))
  2918. #define USB_USBACTEP1_M (USB_USBACTEP1_V << USB_USBACTEP1_S)
  2919. #define USB_USBACTEP1_V 0x00000001
  2920. #define USB_USBACTEP1_S 15
  2921. /** USB_NAKSTS1 : RO; bitpos: [17]; default: 0;
  2922. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  2923. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  2924. */
  2925. #define USB_NAKSTS1 (BIT(17))
  2926. #define USB_NAKSTS1_M (USB_NAKSTS1_V << USB_NAKSTS1_S)
  2927. #define USB_NAKSTS1_V 0x00000001
  2928. #define USB_NAKSTS1_S 17
  2929. /** USB_EPTYPE1 : RO; bitpos: [20:18]; default: 0;
  2930. * Endpoint Type
  2931. * 0x0 : Endpoint Control 1
  2932. */
  2933. #define USB_EPTYPE1 0x00000003
  2934. #define USB_EPTYPE1_M (USB_EPTYPE1_V << USB_EPTYPE1_S)
  2935. #define USB_EPTYPE1_V 0x00000003
  2936. #define USB_EPTYPE1_S 18
  2937. /** USB_SNP1 : R/W; bitpos: [20]; default: 0;
  2938. * 0x0 : Reserved 0
  2939. * 0x1 : Reserved 1
  2940. */
  2941. #define USB_SNP1 (BIT(20))
  2942. #define USB_SNP1_M (USB_SNP1_V << USB_SNP1_S)
  2943. #define USB_SNP1_V 0x00000001
  2944. #define USB_SNP1_S 20
  2945. /** USB_STALL1 : R/W; bitpos: [21]; default: 0;
  2946. * The application can only set this bit, and the core clears it, when a SETUP token
  2947. * is received for this endpoint
  2948. * 0x0 (INACTIVE): No Stall
  2949. * 0x1 (ACTIVE): Stall Handshake
  2950. */
  2951. #define USB_STALL1 (BIT(21))
  2952. #define USB_STALL1_M (USB_STALL1_V << USB_STALL1_S)
  2953. #define USB_STALL1_V 0x00000001
  2954. #define USB_STALL1_S 21
  2955. /** USB_CNAK1 : WO; bitpos: [26]; default: 0;
  2956. * 0x0 : No action
  2957. * 0x1 : Clear NAK
  2958. */
  2959. #define USB_CNAK1 (BIT(26))
  2960. #define USB_CNAK1_M (USB_CNAK1_V << USB_CNAK1_S)
  2961. #define USB_CNAK1_V 0x00000001
  2962. #define USB_CNAK1_S 26
  2963. /** USB_DO_SNAK1 : WO; bitpos: [27]; default: 0;
  2964. * A write to this bit sets the NAK bit for the endpoint
  2965. * 0x0 : No action
  2966. * 0x1 : Set NAK
  2967. */
  2968. #define USB_DO_SNAK1 (BIT(27))
  2969. #define USB_DO_SNAK1_M (USB_DO_SNAK1_V << USB_DO_SNAK1_S)
  2970. #define USB_DO_SNAK1_V 0x00000001
  2971. #define USB_DO_SNAK1_S 27
  2972. /** USB_DO_SETD0PID1 : WO; bitpos: [28]; default: 0;
  2973. * Set DATA0 PID
  2974. */
  2975. #define USB_DO_SETD0PID1 (BIT(28))
  2976. #define USB_DO_SETD0PID1_M (USB_DO_SETD0PID1_V << USB_DO_SETD0PID1_S)
  2977. #define USB_DO_SETD0PID1_V 0x00000001
  2978. #define USB_DO_SETD0PID1_S 28
  2979. /** USB_DO_SETD1PID1 : WO; bitpos: [29]; default: 0;
  2980. * Set DATA1 PID
  2981. */
  2982. #define USB_DO_SETD1PID1 (BIT(29))
  2983. #define USB_DO_SETD1PID1_M (USB_DO_SETD1PID1_V << USB_DO_SETD1PID1_S)
  2984. #define USB_DO_SETD1PID1_V 0x00000001
  2985. #define USB_DO_SETD1PID1_S 29
  2986. /** USB_EPDIS1 : RO; bitpos: [30]; default: 0;
  2987. * Endpoint Disable
  2988. * 0x0 : No Endpoint disable
  2989. */
  2990. #define USB_EPDIS1 (BIT(30))
  2991. #define USB_EPDIS1_M (USB_EPDIS1_V << USB_EPDIS1_S)
  2992. #define USB_EPDIS1_V 0x00000001
  2993. #define USB_EPDIS1_S 30
  2994. /** USB_EPENA1 : R/W; bitpos: [31]; default: 0;
  2995. * Endpoint Enable
  2996. * 0x0 : No action
  2997. * 0x1 : Enable Endpoint
  2998. */
  2999. #define USB_EPENA1 (BIT(31))
  3000. #define USB_EPENA1_M (USB_EPENA1_V << USB_EPENA1_S)
  3001. #define USB_EPENA1_V 0x00000001
  3002. #define USB_EPENA1_S 31
  3003. /** USB_DOEPTSIZ1_REG register
  3004. * Device OUT Endpoint 1 Transfer Size Register
  3005. */
  3006. #define USB_DOEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0xb30)
  3007. /** USB_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0;
  3008. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT1
  3009. */
  3010. #define USB_XFERSIZE1 0x0000007F
  3011. #define USB_XFERSIZE1_M (USB_XFERSIZE1_V << USB_XFERSIZE1_S)
  3012. #define USB_XFERSIZE1_V 0x0000007F
  3013. #define USB_XFERSIZE1_S 0
  3014. /** USB_PKTCNT1 : R/W; bitpos: [19]; default: 0;
  3015. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3016. * into the RxFIFO.
  3017. */
  3018. #define USB_PKTCNT1 (BIT(19))
  3019. #define USB_PKTCNT1_M (USB_PKTCNT1_V << USB_PKTCNT1_S)
  3020. #define USB_PKTCNT1_V 0x00000001
  3021. #define USB_PKTCNT1_S 19
  3022. /** USB_SUPCNT1 : R/W; bitpos: [31:29]; default: 0;
  3023. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3024. * data packets the endpoint can receive
  3025. * 2'b01: 1 packet
  3026. * 2'b10: 2 packets
  3027. * 2'b11: 3 packets
  3028. */
  3029. #define USB_SUPCNT1 0x00000003
  3030. #define USB_SUPCNT1_M (USB_SUPCNT1_V << USB_SUPCNT1_S)
  3031. #define USB_SUPCNT1_V 0x00000003
  3032. #define USB_SUPCNT1_S 29
  3033. /** USB_DOEPDMA1_REG register
  3034. * Device OUT Endpoint 1 DMA Address Register
  3035. */
  3036. #define USB_DOEPDMA1_REG (SOC_DPORT_USB_BASE + 0xb34)
  3037. /** USB_DMAADDR1 : R/W; bitpos: [32:0]; default: 0;
  3038. * Holds the start address of the external memory for storing or fetching endpoint
  3039. * data.
  3040. */
  3041. #define USB_DMAADDR1 0xFFFFFFFF
  3042. #define USB_DMAADDR1_M (USB_DMAADDR1_V << USB_DMAADDR1_S)
  3043. #define USB_DMAADDR1_V 0xFFFFFFFF
  3044. #define USB_DMAADDR1_S 0
  3045. /** USB_DOEPDMAB1_REG register
  3046. * Device OUT Endpoint 16 Buffer Address Register
  3047. */
  3048. #define USB_DOEPDMAB1_REG (SOC_DPORT_USB_BASE + 0xb3c)
  3049. /** USB_DMABUFFERADDR1 : R/W; bitpos: [32:0]; default: 0;
  3050. * Holds the current buffer address.This register is updated as and when the data
  3051. * transfer for the corresponding end point is in progress. This register is present
  3052. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3053. */
  3054. #define USB_DMABUFFERADDR1 0xFFFFFFFF
  3055. #define USB_DMABUFFERADDR1_M (USB_DMABUFFERADDR1_V << USB_DMABUFFERADDR1_S)
  3056. #define USB_DMABUFFERADDR1_V 0xFFFFFFFF
  3057. #define USB_DMABUFFERADDR1_S 0
  3058. /** USB_DOEPCTL2_REG register
  3059. * Device Control OUT Endpoint 2 Control Register
  3060. */
  3061. #define USB_DOEPCTL2_REG (SOC_DPORT_USB_BASE + 0xb40)
  3062. /** USB_MPS2 : RO; bitpos: [11:0]; default: 0;
  3063. * Maximum Packet Size in bytes
  3064. */
  3065. #define USB_MPS2 0x000007FF
  3066. #define USB_MPS2_M (USB_MPS2_V << USB_MPS2_S)
  3067. #define USB_MPS2_V 0x000007FF
  3068. #define USB_MPS2_S 0
  3069. /** USB_USBACTEP2 : RO; bitpos: [15]; default: 1;
  3070. * 0x1: USB Active Endpoint 0
  3071. */
  3072. #define USB_USBACTEP2 (BIT(15))
  3073. #define USB_USBACTEP2_M (USB_USBACTEP2_V << USB_USBACTEP2_S)
  3074. #define USB_USBACTEP2_V 0x00000001
  3075. #define USB_USBACTEP2_S 15
  3076. /** USB_NAKSTS2 : RO; bitpos: [17]; default: 0;
  3077. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  3078. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  3079. */
  3080. #define USB_NAKSTS2 (BIT(17))
  3081. #define USB_NAKSTS2_M (USB_NAKSTS2_V << USB_NAKSTS2_S)
  3082. #define USB_NAKSTS2_V 0x00000001
  3083. #define USB_NAKSTS2_S 17
  3084. /** USB_EPTYPE2 : RO; bitpos: [20:18]; default: 0;
  3085. * Endpoint Type
  3086. * 0x0 : Endpoint Control 2
  3087. */
  3088. #define USB_EPTYPE2 0x00000003
  3089. #define USB_EPTYPE2_M (USB_EPTYPE2_V << USB_EPTYPE2_S)
  3090. #define USB_EPTYPE2_V 0x00000003
  3091. #define USB_EPTYPE2_S 18
  3092. /** USB_SNP2 : R/W; bitpos: [20]; default: 0;
  3093. * 0x0 : Reserved 0
  3094. * 0x1 : Reserved 1
  3095. */
  3096. #define USB_SNP2 (BIT(20))
  3097. #define USB_SNP2_M (USB_SNP2_V << USB_SNP2_S)
  3098. #define USB_SNP2_V 0x00000001
  3099. #define USB_SNP2_S 20
  3100. /** USB_STALL2 : R/W; bitpos: [21]; default: 0;
  3101. * The application can only set this bit, and the core clears it, when a SETUP token
  3102. * is received for this endpoint
  3103. * 0x0 (INACTIVE): No Stall
  3104. * 0x1 (ACTIVE): Stall Handshake
  3105. */
  3106. #define USB_STALL2 (BIT(21))
  3107. #define USB_STALL2_M (USB_STALL2_V << USB_STALL2_S)
  3108. #define USB_STALL2_V 0x00000001
  3109. #define USB_STALL2_S 21
  3110. /** USB_CNAK2 : WO; bitpos: [26]; default: 0;
  3111. * 0x0 : No action
  3112. * 0x1 : Clear NAK
  3113. */
  3114. #define USB_CNAK2 (BIT(26))
  3115. #define USB_CNAK2_M (USB_CNAK2_V << USB_CNAK2_S)
  3116. #define USB_CNAK2_V 0x00000001
  3117. #define USB_CNAK2_S 26
  3118. /** USB_DO_SNAK2 : WO; bitpos: [27]; default: 0;
  3119. * A write to this bit sets the NAK bit for the endpoint
  3120. * 0x0 : No action
  3121. * 0x1 : Set NAK
  3122. */
  3123. #define USB_DO_SNAK2 (BIT(27))
  3124. #define USB_DO_SNAK2_M (USB_DO_SNAK2_V << USB_DO_SNAK2_S)
  3125. #define USB_DO_SNAK2_V 0x00000001
  3126. #define USB_DO_SNAK2_S 27
  3127. /** USB_DO_SETD0PID2 : WO; bitpos: [28]; default: 0;
  3128. * Set DATA0 PID
  3129. */
  3130. #define USB_DO_SETD0PID2 (BIT(28))
  3131. #define USB_DO_SETD0PID2_M (USB_DO_SETD0PID2_V << USB_DO_SETD0PID2_S)
  3132. #define USB_DO_SETD0PID2_V 0x00000001
  3133. #define USB_DO_SETD0PID2_S 28
  3134. /** USB_DO_SETD1PID2 : WO; bitpos: [29]; default: 0;
  3135. * Set DATA1 PID
  3136. */
  3137. #define USB_DO_SETD1PID2 (BIT(29))
  3138. #define USB_DO_SETD1PID2_M (USB_DO_SETD1PID2_V << USB_DO_SETD1PID2_S)
  3139. #define USB_DO_SETD1PID2_V 0x00000001
  3140. #define USB_DO_SETD1PID2_S 29
  3141. /** USB_EPDIS2 : RO; bitpos: [30]; default: 0;
  3142. * Endpoint Disable
  3143. * 0x0 : No Endpoint disable
  3144. */
  3145. #define USB_EPDIS2 (BIT(30))
  3146. #define USB_EPDIS2_M (USB_EPDIS2_V << USB_EPDIS2_S)
  3147. #define USB_EPDIS2_V 0x00000001
  3148. #define USB_EPDIS2_S 30
  3149. /** USB_EPENA2 : R/W; bitpos: [31]; default: 0;
  3150. * Endpoint Enable
  3151. * 0x0 : No action
  3152. * 0x1 : Enable Endpoint
  3153. */
  3154. #define USB_EPENA2 (BIT(31))
  3155. #define USB_EPENA2_M (USB_EPENA2_V << USB_EPENA2_S)
  3156. #define USB_EPENA2_V 0x00000001
  3157. #define USB_EPENA2_S 31
  3158. /** USB_DOEPTSIZ2_REG register
  3159. * Device OUT Endpoint 2 Transfer Size Register
  3160. */
  3161. #define USB_DOEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0xb50)
  3162. /** USB_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0;
  3163. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT2
  3164. */
  3165. #define USB_XFERSIZE2 0x0000007F
  3166. #define USB_XFERSIZE2_M (USB_XFERSIZE2_V << USB_XFERSIZE2_S)
  3167. #define USB_XFERSIZE2_V 0x0000007F
  3168. #define USB_XFERSIZE2_S 0
  3169. /** USB_PKTCNT2 : R/W; bitpos: [19]; default: 0;
  3170. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3171. * into the RxFIFO.
  3172. */
  3173. #define USB_PKTCNT2 (BIT(19))
  3174. #define USB_PKTCNT2_M (USB_PKTCNT2_V << USB_PKTCNT2_S)
  3175. #define USB_PKTCNT2_V 0x00000001
  3176. #define USB_PKTCNT2_S 19
  3177. /** USB_SUPCNT2 : R/W; bitpos: [31:29]; default: 0;
  3178. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3179. * data packets the endpoint can receive
  3180. * 2'b01: 1 packet
  3181. * 2'b10: 2 packets
  3182. * 2'b11: 3 packets
  3183. */
  3184. #define USB_SUPCNT2 0x00000003
  3185. #define USB_SUPCNT2_M (USB_SUPCNT2_V << USB_SUPCNT2_S)
  3186. #define USB_SUPCNT2_V 0x00000003
  3187. #define USB_SUPCNT2_S 29
  3188. /** USB_DOEPDMA2_REG register
  3189. * Device OUT Endpoint 2 DMA Address Register
  3190. */
  3191. #define USB_DOEPDMA2_REG (SOC_DPORT_USB_BASE + 0xb54)
  3192. /** USB_DMAADDR2 : R/W; bitpos: [32:0]; default: 0;
  3193. * Holds the start address of the external memory for storing or fetching endpoint
  3194. * data.
  3195. */
  3196. #define USB_DMAADDR2 0xFFFFFFFF
  3197. #define USB_DMAADDR2_M (USB_DMAADDR2_V << USB_DMAADDR2_S)
  3198. #define USB_DMAADDR2_V 0xFFFFFFFF
  3199. #define USB_DMAADDR2_S 0
  3200. /** USB_DOEPDMAB2_REG register
  3201. * Device OUT Endpoint 16 Buffer Address Register
  3202. */
  3203. #define USB_DOEPDMAB2_REG (SOC_DPORT_USB_BASE + 0xb5c)
  3204. /** USB_DMABUFFERADDR2 : R/W; bitpos: [32:0]; default: 0;
  3205. * Holds the current buffer address.This register is updated as and when the data
  3206. * transfer for the corresponding end point is in progress. This register is present
  3207. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3208. */
  3209. #define USB_DMABUFFERADDR2 0xFFFFFFFF
  3210. #define USB_DMABUFFERADDR2_M (USB_DMABUFFERADDR2_V << USB_DMABUFFERADDR2_S)
  3211. #define USB_DMABUFFERADDR2_V 0xFFFFFFFF
  3212. #define USB_DMABUFFERADDR2_S 0
  3213. /** USB_DOEPCTL3_REG register
  3214. * Device Control OUT Endpoint 3 Control Register
  3215. */
  3216. #define USB_DOEPCTL3_REG (SOC_DPORT_USB_BASE + 0xb60)
  3217. /** USB_MPS3 : RO; bitpos: [11:0]; default: 0;
  3218. * Maximum Packet Size in bytes
  3219. */
  3220. #define USB_MPS3 0x000007FF
  3221. #define USB_MPS3_M (USB_MPS3_V << USB_MPS3_S)
  3222. #define USB_MPS3_V 0x000007FF
  3223. #define USB_MPS3_S 0
  3224. /** USB_USBACTEP3 : RO; bitpos: [15]; default: 1;
  3225. * 0x1: USB Active Endpoint 0
  3226. */
  3227. #define USB_USBACTEP3 (BIT(15))
  3228. #define USB_USBACTEP3_M (USB_USBACTEP3_V << USB_USBACTEP3_S)
  3229. #define USB_USBACTEP3_V 0x00000001
  3230. #define USB_USBACTEP3_S 15
  3231. /** USB_NAKSTS3 : RO; bitpos: [17]; default: 0;
  3232. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  3233. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  3234. */
  3235. #define USB_NAKSTS3 (BIT(17))
  3236. #define USB_NAKSTS3_M (USB_NAKSTS3_V << USB_NAKSTS3_S)
  3237. #define USB_NAKSTS3_V 0x00000001
  3238. #define USB_NAKSTS3_S 17
  3239. /** USB_EPTYPE3 : RO; bitpos: [20:18]; default: 0;
  3240. * Endpoint Type
  3241. * 0x0 : Endpoint Control 3
  3242. */
  3243. #define USB_EPTYPE3 0x00000003
  3244. #define USB_EPTYPE3_M (USB_EPTYPE3_V << USB_EPTYPE3_S)
  3245. #define USB_EPTYPE3_V 0x00000003
  3246. #define USB_EPTYPE3_S 18
  3247. /** USB_SNP3 : R/W; bitpos: [20]; default: 0;
  3248. * 0x0 : Reserved 0
  3249. * 0x1 : Reserved 1
  3250. */
  3251. #define USB_SNP3 (BIT(20))
  3252. #define USB_SNP3_M (USB_SNP3_V << USB_SNP3_S)
  3253. #define USB_SNP3_V 0x00000001
  3254. #define USB_SNP3_S 20
  3255. /** USB_STALL3 : R/W; bitpos: [21]; default: 0;
  3256. * The application can only set this bit, and the core clears it, when a SETUP token
  3257. * is received for this endpoint
  3258. * 0x0 (INACTIVE): No Stall
  3259. * 0x1 (ACTIVE): Stall Handshake
  3260. */
  3261. #define USB_STALL3 (BIT(21))
  3262. #define USB_STALL3_M (USB_STALL3_V << USB_STALL3_S)
  3263. #define USB_STALL3_V 0x00000001
  3264. #define USB_STALL3_S 21
  3265. /** USB_CNAK3 : WO; bitpos: [26]; default: 0;
  3266. * 0x0 : No action
  3267. * 0x1 : Clear NAK
  3268. */
  3269. #define USB_CNAK3 (BIT(26))
  3270. #define USB_CNAK3_M (USB_CNAK3_V << USB_CNAK3_S)
  3271. #define USB_CNAK3_V 0x00000001
  3272. #define USB_CNAK3_S 26
  3273. /** USB_DO_SNAK3 : WO; bitpos: [27]; default: 0;
  3274. * A write to this bit sets the NAK bit for the endpoint
  3275. * 0x0 : No action
  3276. * 0x1 : Set NAK
  3277. */
  3278. #define USB_DO_SNAK3 (BIT(27))
  3279. #define USB_DO_SNAK3_M (USB_DO_SNAK3_V << USB_DO_SNAK3_S)
  3280. #define USB_DO_SNAK3_V 0x00000001
  3281. #define USB_DO_SNAK3_S 27
  3282. /** USB_DO_SETD0PID3 : WO; bitpos: [28]; default: 0;
  3283. * Set DATA0 PID
  3284. */
  3285. #define USB_DO_SETD0PID3 (BIT(28))
  3286. #define USB_DO_SETD0PID3_M (USB_DO_SETD0PID3_V << USB_DO_SETD0PID3_S)
  3287. #define USB_DO_SETD0PID3_V 0x00000001
  3288. #define USB_DO_SETD0PID3_S 28
  3289. /** USB_DO_SETD1PID3 : WO; bitpos: [29]; default: 0;
  3290. * Set DATA1 PID
  3291. */
  3292. #define USB_DO_SETD1PID3 (BIT(29))
  3293. #define USB_DO_SETD1PID3_M (USB_DO_SETD1PID3_V << USB_DO_SETD1PID3_S)
  3294. #define USB_DO_SETD1PID3_V 0x00000001
  3295. #define USB_DO_SETD1PID3_S 29
  3296. /** USB_EPDIS3 : RO; bitpos: [30]; default: 0;
  3297. * Endpoint Disable
  3298. * 0x0 : No Endpoint disable
  3299. */
  3300. #define USB_EPDIS3 (BIT(30))
  3301. #define USB_EPDIS3_M (USB_EPDIS3_V << USB_EPDIS3_S)
  3302. #define USB_EPDIS3_V 0x00000001
  3303. #define USB_EPDIS3_S 30
  3304. /** USB_EPENA3 : R/W; bitpos: [31]; default: 0;
  3305. * Endpoint Enable
  3306. * 0x0 : No action
  3307. * 0x1 : Enable Endpoint
  3308. */
  3309. #define USB_EPENA3 (BIT(31))
  3310. #define USB_EPENA3_M (USB_EPENA3_V << USB_EPENA3_S)
  3311. #define USB_EPENA3_V 0x00000001
  3312. #define USB_EPENA3_S 31
  3313. /** USB_DOEPTSIZ3_REG register
  3314. * Device OUT Endpoint 3 Transfer Size Register
  3315. */
  3316. #define USB_DOEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0xb70)
  3317. /** USB_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0;
  3318. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT3
  3319. */
  3320. #define USB_XFERSIZE3 0x0000007F
  3321. #define USB_XFERSIZE3_M (USB_XFERSIZE3_V << USB_XFERSIZE3_S)
  3322. #define USB_XFERSIZE3_V 0x0000007F
  3323. #define USB_XFERSIZE3_S 0
  3324. /** USB_PKTCNT3 : R/W; bitpos: [19]; default: 0;
  3325. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3326. * into the RxFIFO.
  3327. */
  3328. #define USB_PKTCNT3 (BIT(19))
  3329. #define USB_PKTCNT3_M (USB_PKTCNT3_V << USB_PKTCNT3_S)
  3330. #define USB_PKTCNT3_V 0x00000001
  3331. #define USB_PKTCNT3_S 19
  3332. /** USB_SUPCNT3 : R/W; bitpos: [31:29]; default: 0;
  3333. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3334. * data packets the endpoint can receive
  3335. * 2'b01: 1 packet
  3336. * 2'b10: 2 packets
  3337. * 2'b11: 3 packets
  3338. */
  3339. #define USB_SUPCNT3 0x00000003
  3340. #define USB_SUPCNT3_M (USB_SUPCNT3_V << USB_SUPCNT3_S)
  3341. #define USB_SUPCNT3_V 0x00000003
  3342. #define USB_SUPCNT3_S 29
  3343. /** USB_DOEPDMA3_REG register
  3344. * Device OUT Endpoint 3 DMA Address Register
  3345. */
  3346. #define USB_DOEPDMA3_REG (SOC_DPORT_USB_BASE + 0xb74)
  3347. /** USB_DMAADDR3 : R/W; bitpos: [32:0]; default: 0;
  3348. * Holds the start address of the external memory for storing or fetching endpoint
  3349. * data.
  3350. */
  3351. #define USB_DMAADDR3 0xFFFFFFFF
  3352. #define USB_DMAADDR3_M (USB_DMAADDR3_V << USB_DMAADDR3_S)
  3353. #define USB_DMAADDR3_V 0xFFFFFFFF
  3354. #define USB_DMAADDR3_S 0
  3355. /** USB_DOEPDMAB3_REG register
  3356. * Device OUT Endpoint 16 Buffer Address Register
  3357. */
  3358. #define USB_DOEPDMAB3_REG (SOC_DPORT_USB_BASE + 0xb7c)
  3359. /** USB_DMABUFFERADDR3 : R/W; bitpos: [32:0]; default: 0;
  3360. * Holds the current buffer address.This register is updated as and when the data
  3361. * transfer for the corresponding end point is in progress. This register is present
  3362. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3363. */
  3364. #define USB_DMABUFFERADDR3 0xFFFFFFFF
  3365. #define USB_DMABUFFERADDR3_M (USB_DMABUFFERADDR3_V << USB_DMABUFFERADDR3_S)
  3366. #define USB_DMABUFFERADDR3_V 0xFFFFFFFF
  3367. #define USB_DMABUFFERADDR3_S 0
  3368. /** USB_DOEPCTL4_REG register
  3369. * Device Control OUT Endpoint 4 Control Register
  3370. */
  3371. #define USB_DOEPCTL4_REG (SOC_DPORT_USB_BASE + 0xb80)
  3372. /** USB_MPS4 : RO; bitpos: [11:0]; default: 0;
  3373. * Maximum Packet Size in bytes
  3374. */
  3375. #define USB_MPS4 0x000007FF
  3376. #define USB_MPS4_M (USB_MPS4_V << USB_MPS4_S)
  3377. #define USB_MPS4_V 0x000007FF
  3378. #define USB_MPS4_S 0
  3379. /** USB_USBACTEP4 : RO; bitpos: [15]; default: 1;
  3380. * 0x1: USB Active Endpoint 0
  3381. */
  3382. #define USB_USBACTEP4 (BIT(15))
  3383. #define USB_USBACTEP4_M (USB_USBACTEP4_V << USB_USBACTEP4_S)
  3384. #define USB_USBACTEP4_V 0x00000001
  3385. #define USB_USBACTEP4_S 15
  3386. /** USB_NAKSTS4 : RO; bitpos: [17]; default: 0;
  3387. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  3388. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  3389. */
  3390. #define USB_NAKSTS4 (BIT(17))
  3391. #define USB_NAKSTS4_M (USB_NAKSTS4_V << USB_NAKSTS4_S)
  3392. #define USB_NAKSTS4_V 0x00000001
  3393. #define USB_NAKSTS4_S 17
  3394. /** USB_EPTYPE4 : RO; bitpos: [20:18]; default: 0;
  3395. * Endpoint Type
  3396. * 0x0 : Endpoint Control 4
  3397. */
  3398. #define USB_EPTYPE4 0x00000003
  3399. #define USB_EPTYPE4_M (USB_EPTYPE4_V << USB_EPTYPE4_S)
  3400. #define USB_EPTYPE4_V 0x00000003
  3401. #define USB_EPTYPE4_S 18
  3402. /** USB_SNP4 : R/W; bitpos: [20]; default: 0;
  3403. * 0x0 : Reserved 0
  3404. * 0x1 : Reserved 1
  3405. */
  3406. #define USB_SNP4 (BIT(20))
  3407. #define USB_SNP4_M (USB_SNP4_V << USB_SNP4_S)
  3408. #define USB_SNP4_V 0x00000001
  3409. #define USB_SNP4_S 20
  3410. /** USB_STALL4 : R/W; bitpos: [21]; default: 0;
  3411. * The application can only set this bit, and the core clears it, when a SETUP token
  3412. * is received for this endpoint
  3413. * 0x0 (INACTIVE): No Stall
  3414. * 0x1 (ACTIVE): Stall Handshake
  3415. */
  3416. #define USB_STALL4 (BIT(21))
  3417. #define USB_STALL4_M (USB_STALL4_V << USB_STALL4_S)
  3418. #define USB_STALL4_V 0x00000001
  3419. #define USB_STALL4_S 21
  3420. /** USB_CNAK4 : WO; bitpos: [26]; default: 0;
  3421. * 0x0 : No action
  3422. * 0x1 : Clear NAK
  3423. */
  3424. #define USB_CNAK4 (BIT(26))
  3425. #define USB_CNAK4_M (USB_CNAK4_V << USB_CNAK4_S)
  3426. #define USB_CNAK4_V 0x00000001
  3427. #define USB_CNAK4_S 26
  3428. /** USB_DO_SNAK4 : WO; bitpos: [27]; default: 0;
  3429. * A write to this bit sets the NAK bit for the endpoint
  3430. * 0x0 : No action
  3431. * 0x1 : Set NAK
  3432. */
  3433. #define USB_DO_SNAK4 (BIT(27))
  3434. #define USB_DO_SNAK4_M (USB_DO_SNAK4_V << USB_DO_SNAK4_S)
  3435. #define USB_DO_SNAK4_V 0x00000001
  3436. #define USB_DO_SNAK4_S 27
  3437. /** USB_DO_SETD0PID4 : WO; bitpos: [28]; default: 0;
  3438. * Set DATA0 PID
  3439. */
  3440. #define USB_DO_SETD0PID4 (BIT(28))
  3441. #define USB_DO_SETD0PID4_M (USB_DO_SETD0PID4_V << USB_DO_SETD0PID4_S)
  3442. #define USB_DO_SETD0PID4_V 0x00000001
  3443. #define USB_DO_SETD0PID4_S 28
  3444. /** USB_DO_SETD1PID4 : WO; bitpos: [29]; default: 0;
  3445. * Set DATA1 PID
  3446. */
  3447. #define USB_DO_SETD1PID4 (BIT(29))
  3448. #define USB_DO_SETD1PID4_M (USB_DO_SETD1PID4_V << USB_DO_SETD1PID4_S)
  3449. #define USB_DO_SETD1PID4_V 0x00000001
  3450. #define USB_DO_SETD1PID4_S 29
  3451. /** USB_EPDIS4 : RO; bitpos: [30]; default: 0;
  3452. * Endpoint Disable
  3453. * 0x0 : No Endpoint disable
  3454. */
  3455. #define USB_EPDIS4 (BIT(30))
  3456. #define USB_EPDIS4_M (USB_EPDIS4_V << USB_EPDIS4_S)
  3457. #define USB_EPDIS4_V 0x00000001
  3458. #define USB_EPDIS4_S 30
  3459. /** USB_EPENA4 : R/W; bitpos: [31]; default: 0;
  3460. * Endpoint Enable
  3461. * 0x0 : No action
  3462. * 0x1 : Enable Endpoint
  3463. */
  3464. #define USB_EPENA4 (BIT(31))
  3465. #define USB_EPENA4_M (USB_EPENA4_V << USB_EPENA4_S)
  3466. #define USB_EPENA4_V 0x00000001
  3467. #define USB_EPENA4_S 31
  3468. /** USB_DOEPTSIZ4_REG register
  3469. * Device OUT Endpoint 4 Transfer Size Register
  3470. */
  3471. #define USB_DOEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0xb90)
  3472. /** USB_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0;
  3473. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT4
  3474. */
  3475. #define USB_XFERSIZE4 0x0000007F
  3476. #define USB_XFERSIZE4_M (USB_XFERSIZE4_V << USB_XFERSIZE4_S)
  3477. #define USB_XFERSIZE4_V 0x0000007F
  3478. #define USB_XFERSIZE4_S 0
  3479. /** USB_PKTCNT4 : R/W; bitpos: [19]; default: 0;
  3480. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3481. * into the RxFIFO.
  3482. */
  3483. #define USB_PKTCNT4 (BIT(19))
  3484. #define USB_PKTCNT4_M (USB_PKTCNT4_V << USB_PKTCNT4_S)
  3485. #define USB_PKTCNT4_V 0x00000001
  3486. #define USB_PKTCNT4_S 19
  3487. /** USB_SUPCNT4 : R/W; bitpos: [31:29]; default: 0;
  3488. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3489. * data packets the endpoint can receive
  3490. * 2'b01: 1 packet
  3491. * 2'b10: 2 packets
  3492. * 2'b11: 3 packets
  3493. */
  3494. #define USB_SUPCNT4 0x00000003
  3495. #define USB_SUPCNT4_M (USB_SUPCNT4_V << USB_SUPCNT4_S)
  3496. #define USB_SUPCNT4_V 0x00000003
  3497. #define USB_SUPCNT4_S 29
  3498. /** USB_DOEPDMA4_REG register
  3499. * Device OUT Endpoint 4 DMA Address Register
  3500. */
  3501. #define USB_DOEPDMA4_REG (SOC_DPORT_USB_BASE + 0xb94)
  3502. /** USB_DMAADDR4 : R/W; bitpos: [32:0]; default: 0;
  3503. * Holds the start address of the external memory for storing or fetching endpoint
  3504. * data.
  3505. */
  3506. #define USB_DMAADDR4 0xFFFFFFFF
  3507. #define USB_DMAADDR4_M (USB_DMAADDR4_V << USB_DMAADDR4_S)
  3508. #define USB_DMAADDR4_V 0xFFFFFFFF
  3509. #define USB_DMAADDR4_S 0
  3510. /** USB_DOEPDMAB4_REG register
  3511. * Device OUT Endpoint 16 Buffer Address Register
  3512. */
  3513. #define USB_DOEPDMAB4_REG (SOC_DPORT_USB_BASE + 0xb9c)
  3514. /** USB_DMABUFFERADDR4 : R/W; bitpos: [32:0]; default: 0;
  3515. * Holds the current buffer address.This register is updated as and when the data
  3516. * transfer for the corresponding end point is in progress. This register is present
  3517. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3518. */
  3519. #define USB_DMABUFFERADDR4 0xFFFFFFFF
  3520. #define USB_DMABUFFERADDR4_M (USB_DMABUFFERADDR4_V << USB_DMABUFFERADDR4_S)
  3521. #define USB_DMABUFFERADDR4_V 0xFFFFFFFF
  3522. #define USB_DMABUFFERADDR4_S 0
  3523. /** USB_DOEPCTL5_REG register
  3524. * Device Control OUT Endpoint 5 Control Register
  3525. */
  3526. #define USB_DOEPCTL5_REG (SOC_DPORT_USB_BASE + 0xba0)
  3527. /** USB_MPS5 : RO; bitpos: [11:0]; default: 0;
  3528. * Maximum Packet Size in bytes
  3529. */
  3530. #define USB_MPS5 0x000007FF
  3531. #define USB_MPS5_M (USB_MPS5_V << USB_MPS5_S)
  3532. #define USB_MPS5_V 0x000007FF
  3533. #define USB_MPS5_S 0
  3534. /** USB_USBACTEP5 : RO; bitpos: [15]; default: 1;
  3535. * 0x1: USB Active Endpoint 0
  3536. */
  3537. #define USB_USBACTEP5 (BIT(15))
  3538. #define USB_USBACTEP5_M (USB_USBACTEP5_V << USB_USBACTEP5_S)
  3539. #define USB_USBACTEP5_V 0x00000001
  3540. #define USB_USBACTEP5_S 15
  3541. /** USB_NAKSTS5 : RO; bitpos: [17]; default: 0;
  3542. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  3543. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  3544. */
  3545. #define USB_NAKSTS5 (BIT(17))
  3546. #define USB_NAKSTS5_M (USB_NAKSTS5_V << USB_NAKSTS5_S)
  3547. #define USB_NAKSTS5_V 0x00000001
  3548. #define USB_NAKSTS5_S 17
  3549. /** USB_EPTYPE5 : RO; bitpos: [20:18]; default: 0;
  3550. * Endpoint Type
  3551. * 0x0 : Endpoint Control 5
  3552. */
  3553. #define USB_EPTYPE5 0x00000003
  3554. #define USB_EPTYPE5_M (USB_EPTYPE5_V << USB_EPTYPE5_S)
  3555. #define USB_EPTYPE5_V 0x00000003
  3556. #define USB_EPTYPE5_S 18
  3557. /** USB_SNP5 : R/W; bitpos: [20]; default: 0;
  3558. * 0x0 : Reserved 0
  3559. * 0x1 : Reserved 1
  3560. */
  3561. #define USB_SNP5 (BIT(20))
  3562. #define USB_SNP5_M (USB_SNP5_V << USB_SNP5_S)
  3563. #define USB_SNP5_V 0x00000001
  3564. #define USB_SNP5_S 20
  3565. /** USB_STALL5 : R/W; bitpos: [21]; default: 0;
  3566. * The application can only set this bit, and the core clears it, when a SETUP token
  3567. * is received for this endpoint
  3568. * 0x0 (INACTIVE): No Stall
  3569. * 0x1 (ACTIVE): Stall Handshake
  3570. */
  3571. #define USB_STALL5 (BIT(21))
  3572. #define USB_STALL5_M (USB_STALL5_V << USB_STALL5_S)
  3573. #define USB_STALL5_V 0x00000001
  3574. #define USB_STALL5_S 21
  3575. /** USB_CNAK5 : WO; bitpos: [26]; default: 0;
  3576. * 0x0 : No action
  3577. * 0x1 : Clear NAK
  3578. */
  3579. #define USB_CNAK5 (BIT(26))
  3580. #define USB_CNAK5_M (USB_CNAK5_V << USB_CNAK5_S)
  3581. #define USB_CNAK5_V 0x00000001
  3582. #define USB_CNAK5_S 26
  3583. /** USB_DO_SNAK5 : WO; bitpos: [27]; default: 0;
  3584. * A write to this bit sets the NAK bit for the endpoint
  3585. * 0x0 : No action
  3586. * 0x1 : Set NAK
  3587. */
  3588. #define USB_DO_SNAK5 (BIT(27))
  3589. #define USB_DO_SNAK5_M (USB_DO_SNAK5_V << USB_DO_SNAK5_S)
  3590. #define USB_DO_SNAK5_V 0x00000001
  3591. #define USB_DO_SNAK5_S 27
  3592. /** USB_DO_SETD0PID5 : WO; bitpos: [28]; default: 0;
  3593. * Set DATA0 PID
  3594. */
  3595. #define USB_DO_SETD0PID5 (BIT(28))
  3596. #define USB_DO_SETD0PID5_M (USB_DO_SETD0PID5_V << USB_DO_SETD0PID5_S)
  3597. #define USB_DO_SETD0PID5_V 0x00000001
  3598. #define USB_DO_SETD0PID5_S 28
  3599. /** USB_DO_SETD1PID5 : WO; bitpos: [29]; default: 0;
  3600. * Set DATA1 PID
  3601. */
  3602. #define USB_DO_SETD1PID5 (BIT(29))
  3603. #define USB_DO_SETD1PID5_M (USB_DO_SETD1PID5_V << USB_DO_SETD1PID5_S)
  3604. #define USB_DO_SETD1PID5_V 0x00000001
  3605. #define USB_DO_SETD1PID5_S 29
  3606. /** USB_EPDIS5 : RO; bitpos: [30]; default: 0;
  3607. * Endpoint Disable
  3608. * 0x0 : No Endpoint disable
  3609. */
  3610. #define USB_EPDIS5 (BIT(30))
  3611. #define USB_EPDIS5_M (USB_EPDIS5_V << USB_EPDIS5_S)
  3612. #define USB_EPDIS5_V 0x00000001
  3613. #define USB_EPDIS5_S 30
  3614. /** USB_EPENA5 : R/W; bitpos: [31]; default: 0;
  3615. * Endpoint Enable
  3616. * 0x0 : No action
  3617. * 0x1 : Enable Endpoint
  3618. */
  3619. #define USB_EPENA5 (BIT(31))
  3620. #define USB_EPENA5_M (USB_EPENA5_V << USB_EPENA5_S)
  3621. #define USB_EPENA5_V 0x00000001
  3622. #define USB_EPENA5_S 31
  3623. /** USB_DOEPTSIZ5_REG register
  3624. * Device OUT Endpoint 5 Transfer Size Register
  3625. */
  3626. #define USB_DOEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0xbb0)
  3627. /** USB_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0;
  3628. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT5
  3629. */
  3630. #define USB_XFERSIZE5 0x0000007F
  3631. #define USB_XFERSIZE5_M (USB_XFERSIZE5_V << USB_XFERSIZE5_S)
  3632. #define USB_XFERSIZE5_V 0x0000007F
  3633. #define USB_XFERSIZE5_S 0
  3634. /** USB_PKTCNT5 : R/W; bitpos: [19]; default: 0;
  3635. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3636. * into the RxFIFO.
  3637. */
  3638. #define USB_PKTCNT5 (BIT(19))
  3639. #define USB_PKTCNT5_M (USB_PKTCNT5_V << USB_PKTCNT5_S)
  3640. #define USB_PKTCNT5_V 0x00000001
  3641. #define USB_PKTCNT5_S 19
  3642. /** USB_SUPCNT5 : R/W; bitpos: [31:29]; default: 0;
  3643. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3644. * data packets the endpoint can receive
  3645. * 2'b01: 1 packet
  3646. * 2'b10: 2 packets
  3647. * 2'b11: 3 packets
  3648. */
  3649. #define USB_SUPCNT5 0x00000003
  3650. #define USB_SUPCNT5_M (USB_SUPCNT5_V << USB_SUPCNT5_S)
  3651. #define USB_SUPCNT5_V 0x00000003
  3652. #define USB_SUPCNT5_S 29
  3653. /** USB_DOEPDMA5_REG register
  3654. * Device OUT Endpoint 5 DMA Address Register
  3655. */
  3656. #define USB_DOEPDMA5_REG (SOC_DPORT_USB_BASE + 0xbb4)
  3657. /** USB_DMAADDR5 : R/W; bitpos: [32:0]; default: 0;
  3658. * Holds the start address of the external memory for storing or fetching endpoint
  3659. * data.
  3660. */
  3661. #define USB_DMAADDR5 0xFFFFFFFF
  3662. #define USB_DMAADDR5_M (USB_DMAADDR5_V << USB_DMAADDR5_S)
  3663. #define USB_DMAADDR5_V 0xFFFFFFFF
  3664. #define USB_DMAADDR5_S 0
  3665. /** USB_DOEPDMAB5_REG register
  3666. * Device OUT Endpoint 16 Buffer Address Register
  3667. */
  3668. #define USB_DOEPDMAB5_REG (SOC_DPORT_USB_BASE + 0xbbc)
  3669. /** USB_DMABUFFERADDR5 : R/W; bitpos: [32:0]; default: 0;
  3670. * Holds the current buffer address.This register is updated as and when the data
  3671. * transfer for the corresponding end point is in progress. This register is present
  3672. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3673. */
  3674. #define USB_DMABUFFERADDR5 0xFFFFFFFF
  3675. #define USB_DMABUFFERADDR5_M (USB_DMABUFFERADDR5_V << USB_DMABUFFERADDR5_S)
  3676. #define USB_DMABUFFERADDR5_V 0xFFFFFFFF
  3677. #define USB_DMABUFFERADDR5_S 0
  3678. /** USB_DOEPCTL6_REG register
  3679. * Device Control OUT Endpoint 6 Control Register
  3680. */
  3681. #define USB_DOEPCTL6_REG (SOC_DPORT_USB_BASE + 0xbc0)
  3682. /** USB_MPS6 : RO; bitpos: [11:0]; default: 0;
  3683. * Maximum Packet Size in bytes
  3684. */
  3685. #define USB_MPS6 0x000007FF
  3686. #define USB_MPS6_M (USB_MPS6_V << USB_MPS6_S)
  3687. #define USB_MPS6_V 0x000007FF
  3688. #define USB_MPS6_S 0
  3689. /** USB_USBACTEP6 : RO; bitpos: [15]; default: 1;
  3690. * 0x1: USB Active Endpoint 0
  3691. */
  3692. #define USB_USBACTEP6 (BIT(15))
  3693. #define USB_USBACTEP6_M (USB_USBACTEP6_V << USB_USBACTEP6_S)
  3694. #define USB_USBACTEP6_V 0x00000001
  3695. #define USB_USBACTEP6_S 15
  3696. /** USB_NAKSTS6 : RO; bitpos: [17]; default: 0;
  3697. * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status
  3698. * 0x1 :The core is transmitting NAK handshakes on this endpoint
  3699. */
  3700. #define USB_NAKSTS6 (BIT(17))
  3701. #define USB_NAKSTS6_M (USB_NAKSTS6_V << USB_NAKSTS6_S)
  3702. #define USB_NAKSTS6_V 0x00000001
  3703. #define USB_NAKSTS6_S 17
  3704. /** USB_EPTYPE6 : RO; bitpos: [20:18]; default: 0;
  3705. * Endpoint Type
  3706. * 0x0 : Endpoint Control 6
  3707. */
  3708. #define USB_EPTYPE6 0x00000003
  3709. #define USB_EPTYPE6_M (USB_EPTYPE6_V << USB_EPTYPE6_S)
  3710. #define USB_EPTYPE6_V 0x00000003
  3711. #define USB_EPTYPE6_S 18
  3712. /** USB_SNP6 : R/W; bitpos: [20]; default: 0;
  3713. * 0x0 : Reserved 0
  3714. * 0x1 : Reserved 1
  3715. */
  3716. #define USB_SNP6 (BIT(20))
  3717. #define USB_SNP6_M (USB_SNP6_V << USB_SNP6_S)
  3718. #define USB_SNP6_V 0x00000001
  3719. #define USB_SNP6_S 20
  3720. /** USB_STALL6 : R/W; bitpos: [21]; default: 0;
  3721. * The application can only set this bit, and the core clears it, when a SETUP token
  3722. * is received for this endpoint
  3723. * 0x0 (INACTIVE): No Stall
  3724. * 0x1 (ACTIVE): Stall Handshake
  3725. */
  3726. #define USB_STALL6 (BIT(21))
  3727. #define USB_STALL6_M (USB_STALL6_V << USB_STALL6_S)
  3728. #define USB_STALL6_V 0x00000001
  3729. #define USB_STALL6_S 21
  3730. /** USB_CNAK6 : WO; bitpos: [26]; default: 0;
  3731. * 0x0 : No action
  3732. * 0x1 : Clear NAK
  3733. */
  3734. #define USB_CNAK6 (BIT(26))
  3735. #define USB_CNAK6_M (USB_CNAK6_V << USB_CNAK6_S)
  3736. #define USB_CNAK6_V 0x00000001
  3737. #define USB_CNAK6_S 26
  3738. /** USB_DO_SNAK6 : WO; bitpos: [27]; default: 0;
  3739. * A write to this bit sets the NAK bit for the endpoint
  3740. * 0x0 : No action
  3741. * 0x1 : Set NAK
  3742. */
  3743. #define USB_DO_SNAK6 (BIT(27))
  3744. #define USB_DO_SNAK6_M (USB_DO_SNAK6_V << USB_DO_SNAK6_S)
  3745. #define USB_DO_SNAK6_V 0x00000001
  3746. #define USB_DO_SNAK6_S 27
  3747. /** USB_DO_SETD0PID6 : WO; bitpos: [28]; default: 0;
  3748. * Set DATA0 PID
  3749. */
  3750. #define USB_DO_SETD0PID6 (BIT(28))
  3751. #define USB_DO_SETD0PID6_M (USB_DO_SETD0PID6_V << USB_DO_SETD0PID6_S)
  3752. #define USB_DO_SETD0PID6_V 0x00000001
  3753. #define USB_DO_SETD0PID6_S 28
  3754. /** USB_DO_SETD1PID6 : WO; bitpos: [29]; default: 0;
  3755. * Set DATA1 PID
  3756. */
  3757. #define USB_DO_SETD1PID6 (BIT(29))
  3758. #define USB_DO_SETD1PID6_M (USB_DO_SETD1PID6_V << USB_DO_SETD1PID6_S)
  3759. #define USB_DO_SETD1PID6_V 0x00000001
  3760. #define USB_DO_SETD1PID6_S 29
  3761. /** USB_EPDIS6 : RO; bitpos: [30]; default: 0;
  3762. * Endpoint Disable
  3763. * 0x0 : No Endpoint disable
  3764. */
  3765. #define USB_EPDIS6 (BIT(30))
  3766. #define USB_EPDIS6_M (USB_EPDIS6_V << USB_EPDIS6_S)
  3767. #define USB_EPDIS6_V 0x00000001
  3768. #define USB_EPDIS6_S 30
  3769. /** USB_EPENA6 : R/W; bitpos: [31]; default: 0;
  3770. * Endpoint Enable
  3771. * 0x0 : No action
  3772. * 0x1 : Enable Endpoint
  3773. */
  3774. #define USB_EPENA6 (BIT(31))
  3775. #define USB_EPENA6_M (USB_EPENA6_V << USB_EPENA6_S)
  3776. #define USB_EPENA6_V 0x00000001
  3777. #define USB_EPENA6_S 31
  3778. /** USB_DOEPTSIZ6_REG register
  3779. * Device OUT Endpoint 6 Transfer Size Register
  3780. */
  3781. #define USB_DOEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0xbd0)
  3782. /** USB_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0;
  3783. * Transfer Size.Indicates the transfer size in bytes for ENDPOINT6
  3784. */
  3785. #define USB_XFERSIZE6 0x0000007F
  3786. #define USB_XFERSIZE6_M (USB_XFERSIZE6_V << USB_XFERSIZE6_S)
  3787. #define USB_XFERSIZE6_V 0x0000007F
  3788. #define USB_XFERSIZE6_S 0
  3789. /** USB_PKTCNT6 : R/W; bitpos: [19]; default: 0;
  3790. * Packet Count (PktCnt).This field is decremented to zero after a packet is written
  3791. * into the RxFIFO.
  3792. */
  3793. #define USB_PKTCNT6 (BIT(19))
  3794. #define USB_PKTCNT6_M (USB_PKTCNT6_V << USB_PKTCNT6_S)
  3795. #define USB_PKTCNT6_V 0x00000001
  3796. #define USB_PKTCNT6_S 19
  3797. /** USB_SUPCNT6 : R/W; bitpos: [31:29]; default: 0;
  3798. * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP
  3799. * data packets the endpoint can receive
  3800. * 2'b01: 1 packet
  3801. * 2'b10: 2 packets
  3802. * 2'b11: 3 packets
  3803. */
  3804. #define USB_SUPCNT6 0x00000003
  3805. #define USB_SUPCNT6_M (USB_SUPCNT6_V << USB_SUPCNT6_S)
  3806. #define USB_SUPCNT6_V 0x00000003
  3807. #define USB_SUPCNT6_S 29
  3808. /** USB_DOEPDMA6_REG register
  3809. * Device OUT Endpoint 6 DMA Address Register
  3810. */
  3811. #define USB_DOEPDMA6_REG (SOC_DPORT_USB_BASE + 0xbd4)
  3812. /** USB_DMAADDR6 : R/W; bitpos: [32:0]; default: 0;
  3813. * Holds the start address of the external memory for storing or fetching endpoint
  3814. * data.
  3815. */
  3816. #define USB_DMAADDR6 0xFFFFFFFF
  3817. #define USB_DMAADDR6_M (USB_DMAADDR6_V << USB_DMAADDR6_S)
  3818. #define USB_DMAADDR6_V 0xFFFFFFFF
  3819. #define USB_DMAADDR6_S 0
  3820. /** USB_DOEPDMAB6_REG register
  3821. * Device OUT Endpoint 16 Buffer Address Register
  3822. */
  3823. #define USB_DOEPDMAB6_REG (SOC_DPORT_USB_BASE + 0xbdc)
  3824. /** USB_DMABUFFERADDR6 : R/W; bitpos: [32:0]; default: 0;
  3825. * Holds the current buffer address.This register is updated as and when the data
  3826. * transfer for the corresponding end point is in progress. This register is present
  3827. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  3828. */
  3829. #define USB_DMABUFFERADDR6 0xFFFFFFFF
  3830. #define USB_DMABUFFERADDR6_M (USB_DMABUFFERADDR6_V << USB_DMABUFFERADDR6_S)
  3831. #define USB_DMABUFFERADDR6_V 0xFFFFFFFF
  3832. #define USB_DMABUFFERADDR6_S 0
  3833. /** USB_PCGCCTL_REG register
  3834. * Power and Clock Gating Control Register
  3835. */
  3836. #define USB_PCGCCTL_REG (SOC_DPORT_USB_BASE + 0xe00)
  3837. /** USB_STOPPCLK : R/W; bitpos: [0]; default: 0;
  3838. * 0x0 : Disable Stop Pclk
  3839. * 0x1 : Enable Stop Pclk
  3840. */
  3841. #define USB_STOPPCLK (BIT(0))
  3842. #define USB_STOPPCLK_M (USB_STOPPCLK_V << USB_STOPPCLK_S)
  3843. #define USB_STOPPCLK_V 0x00000001
  3844. #define USB_STOPPCLK_S 0
  3845. /** USB_GATEHCLK : R/W; bitpos: [1]; default: 0;
  3846. * gate hclk
  3847. * 0x0:clears this bit when USB is resumed or a new session starts
  3848. * 0x1:set this bit to gate hclk to modules, when the USB is suspended or the session
  3849. * is not valid
  3850. */
  3851. #define USB_GATEHCLK (BIT(1))
  3852. #define USB_GATEHCLK_M (USB_GATEHCLK_V << USB_GATEHCLK_S)
  3853. #define USB_GATEHCLK_V 0x00000001
  3854. #define USB_GATEHCLK_S 1
  3855. /** USB_PWRCLMP : R/W; bitpos: [2]; default: 0;
  3856. * 0x0:Clears this bit to disable the clamping before the power is turned on
  3857. * 0x1:In only Partial Power-Down mode, sets this bit to clamp the signals between the
  3858. * power-on modules and the power-off modules before the power is turned off
  3859. */
  3860. #define USB_PWRCLMP (BIT(2))
  3861. #define USB_PWRCLMP_M (USB_PWRCLMP_V << USB_PWRCLMP_S)
  3862. #define USB_PWRCLMP_V 0x00000001
  3863. #define USB_PWRCLMP_S 2
  3864. /** USB_RSTPDWNMODULE : R/W; bitpos: [3]; default: 0;
  3865. * Reset Power-Down Modules.
  3866. * 0x0 : Power is turned on
  3867. * 0x1 : Power is turned off
  3868. */
  3869. #define USB_RSTPDWNMODULE (BIT(3))
  3870. #define USB_RSTPDWNMODULE_M (USB_RSTPDWNMODULE_V << USB_RSTPDWNMODULE_S)
  3871. #define USB_RSTPDWNMODULE_V 0x00000001
  3872. #define USB_RSTPDWNMODULE_S 3
  3873. /** USB_PHYSLEEP : RO; bitpos: [6]; default: 0;
  3874. * 0x0 : Phy not in Sleep state
  3875. * 0x1 : Phy in Sleep state
  3876. */
  3877. #define USB_PHYSLEEP (BIT(6))
  3878. #define USB_PHYSLEEP_M (USB_PHYSLEEP_V << USB_PHYSLEEP_S)
  3879. #define USB_PHYSLEEP_V 0x00000001
  3880. #define USB_PHYSLEEP_S 6
  3881. /** USB_L1SUSPENDED : RO; bitpos: [7]; default: 0;
  3882. * L1 Deep Sleep
  3883. * 0x0 : Non Deep Sleep
  3884. * 0x1 : Deep Sleep
  3885. */
  3886. #define USB_L1SUSPENDED (BIT(7))
  3887. #define USB_L1SUSPENDED_M (USB_L1SUSPENDED_V << USB_L1SUSPENDED_S)
  3888. #define USB_L1SUSPENDED_V 0x00000001
  3889. #define USB_L1SUSPENDED_S 7
  3890. /** USB_RESETAFTERSUSP : R/W; bitpos: [8]; default: 0;
  3891. * Reset after suspend
  3892. * 0x0 : In Host-only mode, host issues Resume after Suspend
  3893. * 0x1 : In Host-only mode, host sets this bit before clamp is removed if the host
  3894. * needs to issue Reset after Suspend
  3895. */
  3896. #define USB_RESETAFTERSUSP (BIT(8))
  3897. #define USB_RESETAFTERSUSP_M (USB_RESETAFTERSUSP_V << USB_RESETAFTERSUSP_S)
  3898. #define USB_RESETAFTERSUSP_V 0x00000001
  3899. #define USB_RESETAFTERSUSP_S 8
  3900. /** Interrupt registers */
  3901. /** USB_GOTGINT_REG register
  3902. * OTG Interrupt Register
  3903. */
  3904. #define USB_GOTGINT_REG (SOC_DPORT_USB_BASE + 0x4)
  3905. /** USB_SESENDDET : R/W1C; bitpos: [2]; default: 0;
  3906. * Session End Detected.The controller sets this bit when the utmiotg_bvalid signal is
  3907. * deasserted. This bit can be set only by the core and the application should write 1
  3908. * to clear it
  3909. */
  3910. #define USB_SESENDDET (BIT(2))
  3911. #define USB_SESENDDET_M (USB_SESENDDET_V << USB_SESENDDET_S)
  3912. #define USB_SESENDDET_V 0x00000001
  3913. #define USB_SESENDDET_S 2
  3914. /** USB_SESREQSUCSTSCHNG : R/W1C; bitpos: [8]; default: 0;
  3915. * Session Request Success Status Change.The core sets this bit on the success or
  3916. * failure of a session request.The application must read the Session Request Success
  3917. * bit in the OTG Control and Status register (GOTGCTL_REG.USB_SESREQSCS) to check for
  3918. * success or failure. This bit can be set only by the core and the application should
  3919. * write 1 to clear it.
  3920. */
  3921. #define USB_SESREQSUCSTSCHNG (BIT(8))
  3922. #define USB_SESREQSUCSTSCHNG_M (USB_SESREQSUCSTSCHNG_V << USB_SESREQSUCSTSCHNG_S)
  3923. #define USB_SESREQSUCSTSCHNG_V 0x00000001
  3924. #define USB_SESREQSUCSTSCHNG_S 8
  3925. /** USB_HSTNEGSUCSTSCHNG : R/W1C; bitpos: [9]; default: 0;
  3926. * Host Negotiation Success Status Change. The core sets this bit on the success or
  3927. * failure of a USB host negotiation request. The application must read the Host
  3928. * Negotiation Success bit of the OTG Control and Status register
  3929. * (GOTGCTL_REG.USB_HSTNEGSCS) to check for success or failure. This bit can be set
  3930. * only by the core and the application should write 1 to clear it
  3931. */
  3932. #define USB_HSTNEGSUCSTSCHNG (BIT(9))
  3933. #define USB_HSTNEGSUCSTSCHNG_M (USB_HSTNEGSUCSTSCHNG_V << USB_HSTNEGSUCSTSCHNG_S)
  3934. #define USB_HSTNEGSUCSTSCHNG_V 0x00000001
  3935. #define USB_HSTNEGSUCSTSCHNG_S 9
  3936. /** USB_HSTNEGDET : R/W1C; bitpos: [17]; default: 0;
  3937. * Host Negotiation Detected.The core sets this bit when it detects a host negotiation
  3938. * request on the USB. This bit can be set only by the core and the application should
  3939. * write 1 to clear it.
  3940. */
  3941. #define USB_HSTNEGDET (BIT(17))
  3942. #define USB_HSTNEGDET_M (USB_HSTNEGDET_V << USB_HSTNEGDET_S)
  3943. #define USB_HSTNEGDET_V 0x00000001
  3944. #define USB_HSTNEGDET_S 17
  3945. /** USB_ADEVTOUTCHG : R/W1C; bitpos: [18]; default: 0;
  3946. * A-Device Timeout Change. The core sets this bit to indicate that the A-device has
  3947. * timed out while waiting for the B-device to connect.This bit can be set only by the
  3948. * core and the application should write 1 to clear it
  3949. */
  3950. #define USB_ADEVTOUTCHG (BIT(18))
  3951. #define USB_ADEVTOUTCHG_M (USB_ADEVTOUTCHG_V << USB_ADEVTOUTCHG_S)
  3952. #define USB_ADEVTOUTCHG_V 0x00000001
  3953. #define USB_ADEVTOUTCHG_S 18
  3954. /** USB_DBNCEDONE : R/W1C; bitpos: [19]; default: 0;
  3955. * Debounce Done. The core sets this bit when the debounce is completed after the
  3956. * device connect. The application can start driving USB reset after seeing this
  3957. * interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in
  3958. * the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap,
  3959. * respectively). This bit can be set only by the core and the application should
  3960. * write 1 to clear it
  3961. */
  3962. #define USB_DBNCEDONE (BIT(19))
  3963. #define USB_DBNCEDONE_M (USB_DBNCEDONE_V << USB_DBNCEDONE_S)
  3964. #define USB_DBNCEDONE_V 0x00000001
  3965. #define USB_DBNCEDONE_S 19
  3966. /** USB_GINTSTS_REG register
  3967. * Interrupt Register
  3968. */
  3969. #define USB_GINTSTS_REG (SOC_DPORT_USB_BASE + 0x14)
  3970. /** USB_CURMOD_INT : RO; bitpos: [0]; default: 0;
  3971. * Current Mode of Operation
  3972. * 1'b0: Device mode
  3973. * 1'b1: Host mode
  3974. */
  3975. #define USB_CURMOD_INT (BIT(0))
  3976. #define USB_CURMOD_INT_M (USB_CURMOD_INT_V << USB_CURMOD_INT_S)
  3977. #define USB_CURMOD_INT_V 0x00000001
  3978. #define USB_CURMOD_INT_S 0
  3979. /** USB_MODEMIS : R/W1C; bitpos: [1]; default: 0;
  3980. * Mode Mismatch Interrupt.The core sets this bit when the application is trying to
  3981. * access:A Host mode register, when the controller is operating in Device mode
  3982. */
  3983. #define USB_MODEMIS (BIT(1))
  3984. #define USB_MODEMIS_M (USB_MODEMIS_V << USB_MODEMIS_S)
  3985. #define USB_MODEMIS_V 0x00000001
  3986. #define USB_MODEMIS_S 1
  3987. /** USB_OTGINT : RO; bitpos: [2]; default: 0;
  3988. * OTG Interrupt.The controller sets this bit to indicate an OTG protocol event. The
  3989. * application must read the OTG Interrupt Status (GOTGINT_REG) register to determine
  3990. * the exact event that caused this interrupt. The application must clear the
  3991. * appropriate status bit in the GOTGINT_REG register to clear this bit.
  3992. */
  3993. #define USB_OTGINT (BIT(2))
  3994. #define USB_OTGINT_M (USB_OTGINT_V << USB_OTGINT_S)
  3995. #define USB_OTGINT_V 0x00000001
  3996. #define USB_OTGINT_S 2
  3997. /** USB_SOF : R/W1C; bitpos: [3]; default: 0;
  3998. * Start of (micro)Frame (Sof)
  3999. * In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS),
  4000. * or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to
  4001. * this bit to clear the interrupt
  4002. * In Device mode, the controller sets this bit to indicate that an SOF token has been
  4003. * received on the USB. The application can read the Device Status register to get the
  4004. * current (micro)Frame number. This Interrupt is seen only when the core is operating
  4005. * at either HS or FS. This bit can be set only by the core and the application must
  4006. * write 1 to clear it
  4007. */
  4008. #define USB_SOF (BIT(3))
  4009. #define USB_SOF_M (USB_SOF_V << USB_SOF_S)
  4010. #define USB_SOF_V 0x00000001
  4011. #define USB_SOF_S 3
  4012. /** USB_RXFLVI : RO; bitpos: [4]; default: 0;
  4013. * RxFIFO Non-Empty.Indicates that there is at least one packet pending to be read
  4014. * from the RxFIFO
  4015. * 1'b0: Rx Fifo is empty
  4016. * 1'b1: Rx Fifo is not empty
  4017. */
  4018. #define USB_RXFLVI (BIT(4))
  4019. #define USB_RXFLVI_M (USB_RXFLVI_V << USB_RXFLVI_S)
  4020. #define USB_RXFLVI_V 0x00000001
  4021. #define USB_RXFLVI_S 4
  4022. /** USB_NPTXFEMP : RO; bitpos: [5]; default: 0;
  4023. * Non-periodic TxFIFO Empty.This interrupt is asserted when the Non-periodic TxFIFO
  4024. * is either half or completely empty, and there is space for at least one Entry to be
  4025. * written to the Non-periodic Transmit Request Queue. The half or completely empty
  4026. * status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB
  4027. * Configuration register (GAHBCFG_REG.USB_NPTXFEMPLVL).
  4028. */
  4029. #define USB_NPTXFEMP (BIT(5))
  4030. #define USB_NPTXFEMP_M (USB_NPTXFEMP_V << USB_NPTXFEMP_S)
  4031. #define USB_NPTXFEMP_V 0x00000001
  4032. #define USB_NPTXFEMP_S 5
  4033. /** USB_GINNAKEFF : RO; bitpos: [6]; default: 0;
  4034. * Device only.Global IN Non-periodic NAK Effective.Indicates that the Set Global
  4035. * Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the
  4036. * application, has taken effect in the core. That is, the core has sampled the Global
  4037. * IN NAK bit Set by the application. This bit can be cleared by clearing the Clear
  4038. * Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak).
  4039. * This interrupt does not necessarily mean that a NAK handshake is sent out on the
  4040. * USB. The STALL bit takes precedence over the NAK bit.
  4041. */
  4042. #define USB_GINNAKEFF (BIT(6))
  4043. #define USB_GINNAKEFF_M (USB_GINNAKEFF_V << USB_GINNAKEFF_S)
  4044. #define USB_GINNAKEFF_V 0x00000001
  4045. #define USB_GINNAKEFF_S 6
  4046. /** USB_GOUTNAKEFF : RO; bitpos: [7]; default: 0;
  4047. * Device only.Global OUT NAK Effective.Indicates that the Set Global OUT NAK bit in
  4048. * the Device Control register (DCTL_REG.USB_SGOUTNAK), Set by the application, has
  4049. * taken effect in the core. This bit can be cleared by writing the Clear Global OUT
  4050. * NAK bit in the Device Control register (DCTL_REG.REG_CGOUTNAK).
  4051. */
  4052. #define USB_GOUTNAKEFF (BIT(7))
  4053. #define USB_GOUTNAKEFF_M (USB_GOUTNAKEFF_V << USB_GOUTNAKEFF_S)
  4054. #define USB_GOUTNAKEFF_V 0x00000001
  4055. #define USB_GOUTNAKEFF_S 7
  4056. /** USB_ERLYSUSP : R/W1C; bitpos: [10]; default: 0;
  4057. * Device only.Early Suspend.The controller sets this bit to indicate that an Idle
  4058. * state has been detected on the USB for 3 ms.
  4059. */
  4060. #define USB_ERLYSUSP (BIT(10))
  4061. #define USB_ERLYSUSP_M (USB_ERLYSUSP_V << USB_ERLYSUSP_S)
  4062. #define USB_ERLYSUSP_V 0x00000001
  4063. #define USB_ERLYSUSP_S 10
  4064. /** USB_USBSUSP : R/W1C; bitpos: [11]; default: 0;
  4065. * Device only.USB Suspend.The controller sets this bit to indicate that a suspend was
  4066. * detected on the USB. The controller enters the Suspended state when there is no
  4067. * activity on the linestate signal for an extended period of time.
  4068. */
  4069. #define USB_USBSUSP (BIT(11))
  4070. #define USB_USBSUSP_M (USB_USBSUSP_V << USB_USBSUSP_S)
  4071. #define USB_USBSUSP_V 0x00000001
  4072. #define USB_USBSUSP_S 11
  4073. /** USB_USBRST : R/W1C; bitpos: [12]; default: 0;
  4074. * Device only.USB Reset.The controller sets this bit to indicate that a reset is
  4075. * detected on the USB
  4076. */
  4077. #define USB_USBRST (BIT(12))
  4078. #define USB_USBRST_M (USB_USBRST_V << USB_USBRST_S)
  4079. #define USB_USBRST_V 0x00000001
  4080. #define USB_USBRST_S 12
  4081. /** USB_ENUMDONE : R/W1C; bitpos: [13]; default: 0;
  4082. * Device only.Enumeration Done.The core sets this bit to indicate that speed
  4083. * enumeration is complete. The application must read the Device Status (DSTS_REG)
  4084. * register to obtain the enumerated speed.
  4085. */
  4086. #define USB_ENUMDONE (BIT(13))
  4087. #define USB_ENUMDONE_M (USB_ENUMDONE_V << USB_ENUMDONE_S)
  4088. #define USB_ENUMDONE_V 0x00000001
  4089. #define USB_ENUMDONE_S 13
  4090. /** USB_ISOOUTDROP : R/W1C; bitpos: [14]; default: 0;
  4091. * Device only.Isochronous OUT Packet Dropped Interrupt.The controller sets this bit
  4092. * when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO
  4093. * does not have enough space to accommodate a maximum packet size packet for the
  4094. * isochronous OUT endpoint.
  4095. */
  4096. #define USB_ISOOUTDROP (BIT(14))
  4097. #define USB_ISOOUTDROP_M (USB_ISOOUTDROP_V << USB_ISOOUTDROP_S)
  4098. #define USB_ISOOUTDROP_V 0x00000001
  4099. #define USB_ISOOUTDROP_S 14
  4100. /** USB_EOPF : R/W1C; bitpos: [15]; default: 0;
  4101. * Device only.End of Periodic Frame Interrupt.Indicates that the period specified in
  4102. * the Periodic Frame Interval field of the Device Configuration register
  4103. * (DCFG_REG.REG_PERFRINT) has been reached in the current microframe.
  4104. */
  4105. #define USB_EOPF (BIT(15))
  4106. #define USB_EOPF_M (USB_EOPF_V << USB_EOPF_S)
  4107. #define USB_EOPF_V 0x00000001
  4108. #define USB_EOPF_S 15
  4109. /** USB_EPMIS : R/W1C; bitpos: [17]; default: 0;
  4110. * Device only.Endpoint Mismatch Interrupt.This interrupt is valid only in shared FIFO
  4111. * operation.Indicates that an IN token has been received for a non-periodic endpoint,
  4112. * but the data for another endpoint is present in the top of the Non-periodic
  4113. * Transmit FIFO and the IN endpoint mismatch count programmed by the application has
  4114. * expired.
  4115. */
  4116. #define USB_EPMIS (BIT(17))
  4117. #define USB_EPMIS_M (USB_EPMIS_V << USB_EPMIS_S)
  4118. #define USB_EPMIS_V 0x00000001
  4119. #define USB_EPMIS_S 17
  4120. /** USB_IEPINT : RO; bitpos: [18]; default: 0;
  4121. * Device only.IN Endpoints Interrupt.The core sets this bit to indicate that an
  4122. * interrupt is pending on one of the IN endpoints of the core (in Device mode). The
  4123. * application must read the Device All Endpoints Interrupt (DAINT) register to
  4124. * determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt
  4125. * (DIEPINTn) register to determine the exact cause of the interrupt. The application
  4126. * must clear the appropriate status bit in the corresponding DIEPINTn register to
  4127. * clear this bit.
  4128. */
  4129. #define USB_IEPINT (BIT(18))
  4130. #define USB_IEPINT_M (USB_IEPINT_V << USB_IEPINT_S)
  4131. #define USB_IEPINT_V 0x00000001
  4132. #define USB_IEPINT_S 18
  4133. /** USB_OEPINT : RO; bitpos: [19]; default: 0;
  4134. * Device only.OUT Endpoints Interrupt.The controller sets this bit to indicate that
  4135. * an interrupt is pending on one of the OUT endpoints of the core (in Device mode).
  4136. * The application must read the Device All Endpoints Interrupt (DAINT) register to
  4137. * determine the exact number of the OUT endpoint on which the interrupt occurred, and
  4138. * then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to
  4139. * determine the exact cause of the interrupt. The application must clear the
  4140. * appropriate status bit in the corresponding DOEPINTn register to clear this bit.
  4141. */
  4142. #define USB_OEPINT (BIT(19))
  4143. #define USB_OEPINT_M (USB_OEPINT_V << USB_OEPINT_S)
  4144. #define USB_OEPINT_V 0x00000001
  4145. #define USB_OEPINT_S 19
  4146. /** USB_INCOMPISOIN : R/W1C; bitpos: [20]; default: 0;
  4147. * Device only.Incomplete Isochronous IN Transfer.The core sets this interrupt to
  4148. * indicate that there is at least one isochronous IN endpoint on which the transfer
  4149. * is not completed in the current microframe. This interrupt is asserted along with
  4150. * the End of Periodic Frame Interrupt (EOPF) bit in this register.
  4151. */
  4152. #define USB_INCOMPISOIN (BIT(20))
  4153. #define USB_INCOMPISOIN_M (USB_INCOMPISOIN_V << USB_INCOMPISOIN_S)
  4154. #define USB_INCOMPISOIN_V 0x00000001
  4155. #define USB_INCOMPISOIN_S 20
  4156. /** USB_INCOMPIP : R/W1C; bitpos: [21]; default: 0;
  4157. * In Host mode, the core sets this interrupt bit when there are incomplete periodic
  4158. * transactions still pending which are scheduled for the current microframe.The
  4159. * Device mode, the core sets this interrupt to indicate that thereis at least one
  4160. * isochronous OUT endpoint on which the transfer is not completed in the current
  4161. * microframe. This interrupt is asserted along with the End of Periodic Frame
  4162. * Interrupt (EOPF) bit in this register.
  4163. */
  4164. #define USB_INCOMPIP (BIT(21))
  4165. #define USB_INCOMPIP_M (USB_INCOMPIP_V << USB_INCOMPIP_S)
  4166. #define USB_INCOMPIP_V 0x00000001
  4167. #define USB_INCOMPIP_S 21
  4168. /** USB_FETSUSP : R/W1C; bitpos: [22]; default: 0;
  4169. * Device only.Data Fetch Suspended.This interrupt is valid only in DMA mode. This
  4170. * interrupt indicates that the core has stopped fetching data. For IN endpoints due
  4171. * to the unavailability of TxFIFO space or Request Queue space. This interrupt is
  4172. * used by the application for an endpoint mismatch algorithm
  4173. */
  4174. #define USB_FETSUSP (BIT(22))
  4175. #define USB_FETSUSP_M (USB_FETSUSP_V << USB_FETSUSP_S)
  4176. #define USB_FETSUSP_V 0x00000001
  4177. #define USB_FETSUSP_S 22
  4178. /** USB_RESETDET : R/W1C; bitpos: [23]; default: 0;
  4179. * Reset detected Interrupt
  4180. * In Device mode, this interrupt is asserted when a reset is detected on the USB in
  4181. * partial power-down mode when the device is in Suspend
  4182. * In Host mode, this interrupt is not asserted
  4183. */
  4184. #define USB_RESETDET (BIT(23))
  4185. #define USB_RESETDET_M (USB_RESETDET_V << USB_RESETDET_S)
  4186. #define USB_RESETDET_V 0x00000001
  4187. #define USB_RESETDET_S 23
  4188. /** USB_PRTLNT : RO; bitpos: [24]; default: 0;
  4189. * Host only.Host Port Interrupt.The core sets this bit to indicate a change in port
  4190. * status of one of the controller ports in Host mode. The application must read the
  4191. * Host Port Control and Status (HPRT) register to determine the exact event that
  4192. * caused this interrupt. The application must clear the appropriate status bit in the
  4193. * Host Port Control and Status register to clear this bit.
  4194. */
  4195. #define USB_PRTLNT (BIT(24))
  4196. #define USB_PRTLNT_M (USB_PRTLNT_V << USB_PRTLNT_S)
  4197. #define USB_PRTLNT_V 0x00000001
  4198. #define USB_PRTLNT_S 24
  4199. /** USB_HCHLNT : RO; bitpos: [25]; default: 0;
  4200. * Host only.Host Channels Interrupt.The core sets this bit to indicate that an
  4201. * interrupt is pending on one of the channels of the core (in Host mode). The
  4202. * application must read the Host All Channels Interrupt (HAINT) register to determine
  4203. * the exact number of the channel on which the interrupt occurred,and Then read the
  4204. * corresponding Host Channel-n Interrupt (HCINTn) register to determine the exact
  4205. * cause of the interrupt.The application must clear the appropriate status bit in the
  4206. * HCINTn register to clear this bit.
  4207. */
  4208. #define USB_HCHLNT (BIT(25))
  4209. #define USB_HCHLNT_M (USB_HCHLNT_V << USB_HCHLNT_S)
  4210. #define USB_HCHLNT_V 0x00000001
  4211. #define USB_HCHLNT_S 25
  4212. /** USB_PTXFEMP : RO; bitpos: [26]; default: 0;
  4213. * Host only.Periodic TxFIFO Empty.This interrupt is asserted when the Periodic
  4214. * Transmit FIFO is either half or completely empty and there is space for at least
  4215. * one entry to be written in the Periodic Request Queue. The half or completelyempty
  4216. * status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB
  4217. * Configuration register (GAHBCFG.PTxFEmpLvl)
  4218. */
  4219. #define USB_PTXFEMP (BIT(26))
  4220. #define USB_PTXFEMP_M (USB_PTXFEMP_V << USB_PTXFEMP_S)
  4221. #define USB_PTXFEMP_V 0x00000001
  4222. #define USB_PTXFEMP_S 26
  4223. /** USB_CONIDSTSCHNG : R/W1C; bitpos: [28]; default: 0;
  4224. * Connector ID Status Change
  4225. * 1'b0:Not active
  4226. * 1'b1:Connector ID Status Change
  4227. */
  4228. #define USB_CONIDSTSCHNG (BIT(28))
  4229. #define USB_CONIDSTSCHNG_M (USB_CONIDSTSCHNG_V << USB_CONIDSTSCHNG_S)
  4230. #define USB_CONIDSTSCHNG_V 0x00000001
  4231. #define USB_CONIDSTSCHNG_S 28
  4232. /** USB_DISCONNINT : R/W1C; bitpos: [29]; default: 0;
  4233. * Disconnect Detected Interrupt
  4234. * 1'b0:Not active
  4235. * 1'b1:Disconnect Detected Interrupt
  4236. */
  4237. #define USB_DISCONNINT (BIT(29))
  4238. #define USB_DISCONNINT_M (USB_DISCONNINT_V << USB_DISCONNINT_S)
  4239. #define USB_DISCONNINT_V 0x00000001
  4240. #define USB_DISCONNINT_S 29
  4241. /** USB_SESSREQINT : R/W1C; bitpos: [30]; default: 0;
  4242. * 1'b0:Not active
  4243. * 1'b1:Session Request New Session Detected
  4244. */
  4245. #define USB_SESSREQINT (BIT(30))
  4246. #define USB_SESSREQINT_M (USB_SESSREQINT_V << USB_SESSREQINT_S)
  4247. #define USB_SESSREQINT_V 0x00000001
  4248. #define USB_SESSREQINT_S 30
  4249. /** USB_WKUPINT : R/W1C; bitpos: [31]; default: 0;
  4250. * Resume/Remote Wakeup Detected Interrupt
  4251. * 1'b0:Not active
  4252. * 1'b1:Resume or Remote Wakeup Detected Interrupt
  4253. */
  4254. #define USB_WKUPINT (BIT(31))
  4255. #define USB_WKUPINT_M (USB_WKUPINT_V << USB_WKUPINT_S)
  4256. #define USB_WKUPINT_V 0x00000001
  4257. #define USB_WKUPINT_S 31
  4258. /** USB_GINTMSK_REG register
  4259. * Interrupt Mask Register
  4260. */
  4261. #define USB_GINTMSK_REG (SOC_DPORT_USB_BASE + 0x18)
  4262. /** USB_MODEMISMSK : R/W; bitpos: [1]; default: 0;
  4263. * 1'b0:Mode Mismatch Interrupt Mask
  4264. * 1'b1:No Mode Mismatch Interrupt Mask
  4265. */
  4266. #define USB_MODEMISMSK (BIT(1))
  4267. #define USB_MODEMISMSK_M (USB_MODEMISMSK_V << USB_MODEMISMSK_S)
  4268. #define USB_MODEMISMSK_V 0x00000001
  4269. #define USB_MODEMISMSK_S 1
  4270. /** USB_OTGINTMSK : R/W; bitpos: [2]; default: 0;
  4271. * 1'b0:OTG Interrupt Mask
  4272. * 1'b1:No OTG Interrupt Mask
  4273. */
  4274. #define USB_OTGINTMSK (BIT(2))
  4275. #define USB_OTGINTMSK_M (USB_OTGINTMSK_V << USB_OTGINTMSK_S)
  4276. #define USB_OTGINTMSK_V 0x00000001
  4277. #define USB_OTGINTMSK_S 2
  4278. /** USB_SOFMSK : R/W; bitpos: [3]; default: 0;
  4279. * 1'b0:Start of (micro)Frame Mask
  4280. * 1'b1:No Start of (micro)Frame Mask
  4281. */
  4282. #define USB_SOFMSK (BIT(3))
  4283. #define USB_SOFMSK_M (USB_SOFMSK_V << USB_SOFMSK_S)
  4284. #define USB_SOFMSK_V 0x00000001
  4285. #define USB_SOFMSK_S 3
  4286. /** USB_RXFLVIMSK : R/W; bitpos: [4]; default: 0;
  4287. * 1'b0:Receive FIFO Non-Empty Mask
  4288. * 1'b1:No Receive FIFO Non-Empty Mask
  4289. */
  4290. #define USB_RXFLVIMSK (BIT(4))
  4291. #define USB_RXFLVIMSK_M (USB_RXFLVIMSK_V << USB_RXFLVIMSK_S)
  4292. #define USB_RXFLVIMSK_V 0x00000001
  4293. #define USB_RXFLVIMSK_S 4
  4294. /** USB_NPTXFEMPMSK : R/W; bitpos: [5]; default: 0;
  4295. * 1'b0:Non-periodic TxFIFO Empty Mask
  4296. * 1'b1:No Non-periodic TxFIFO Empty Mask
  4297. */
  4298. #define USB_NPTXFEMPMSK (BIT(5))
  4299. #define USB_NPTXFEMPMSK_M (USB_NPTXFEMPMSK_V << USB_NPTXFEMPMSK_S)
  4300. #define USB_NPTXFEMPMSK_V 0x00000001
  4301. #define USB_NPTXFEMPMSK_S 5
  4302. /** USB_GINNAKEFFMSK : R/W; bitpos: [6]; default: 0;
  4303. * 1'b0:Global Non-periodic IN NAK Effective Mask
  4304. * 1'b1:No Global Non-periodic IN NAK Effective Mask
  4305. */
  4306. #define USB_GINNAKEFFMSK (BIT(6))
  4307. #define USB_GINNAKEFFMSK_M (USB_GINNAKEFFMSK_V << USB_GINNAKEFFMSK_S)
  4308. #define USB_GINNAKEFFMSK_V 0x00000001
  4309. #define USB_GINNAKEFFMSK_S 6
  4310. /** USB_GOUTNACKEFFMSK : R/W; bitpos: [7]; default: 0;
  4311. * 1'b0:Global OUT NAK Effective Mask
  4312. * 1'b1:No Global OUT NAK Effective Mask
  4313. */
  4314. #define USB_GOUTNACKEFFMSK (BIT(7))
  4315. #define USB_GOUTNACKEFFMSK_M (USB_GOUTNACKEFFMSK_V << USB_GOUTNACKEFFMSK_S)
  4316. #define USB_GOUTNACKEFFMSK_V 0x00000001
  4317. #define USB_GOUTNACKEFFMSK_S 7
  4318. /** USB_ERLYSUSPMSK : R/W; bitpos: [10]; default: 0;
  4319. * 1'b0:Early Suspend Mask
  4320. * 1'b1:No Early Suspend Mask
  4321. */
  4322. #define USB_ERLYSUSPMSK (BIT(10))
  4323. #define USB_ERLYSUSPMSK_M (USB_ERLYSUSPMSK_V << USB_ERLYSUSPMSK_S)
  4324. #define USB_ERLYSUSPMSK_V 0x00000001
  4325. #define USB_ERLYSUSPMSK_S 10
  4326. /** USB_USBSUSPMSK : R/W; bitpos: [11]; default: 0;
  4327. * 1'b0:USB Suspend Mask
  4328. * 1'b1:No USB Suspend Mask
  4329. */
  4330. #define USB_USBSUSPMSK (BIT(11))
  4331. #define USB_USBSUSPMSK_M (USB_USBSUSPMSK_V << USB_USBSUSPMSK_S)
  4332. #define USB_USBSUSPMSK_V 0x00000001
  4333. #define USB_USBSUSPMSK_S 11
  4334. /** USB_USBRSTMSK : R/W; bitpos: [12]; default: 0;
  4335. * 1'b0:USB Reset Mask
  4336. * 1'b1:No USB Reset Mask
  4337. */
  4338. #define USB_USBRSTMSK (BIT(12))
  4339. #define USB_USBRSTMSK_M (USB_USBRSTMSK_V << USB_USBRSTMSK_S)
  4340. #define USB_USBRSTMSK_V 0x00000001
  4341. #define USB_USBRSTMSK_S 12
  4342. /** USB_ENUMDONEMSK : R/W; bitpos: [13]; default: 0;
  4343. * 1'b0: Enumeration Done Mask
  4344. * 1'b1: No Enumeration Done Mask
  4345. */
  4346. #define USB_ENUMDONEMSK (BIT(13))
  4347. #define USB_ENUMDONEMSK_M (USB_ENUMDONEMSK_V << USB_ENUMDONEMSK_S)
  4348. #define USB_ENUMDONEMSK_V 0x00000001
  4349. #define USB_ENUMDONEMSK_S 13
  4350. /** USB_ISOOUTDROPMSK : R/W; bitpos: [14]; default: 0;
  4351. * 1'b0: Isochronous OUT Packet Dropped Interrupt Mask
  4352. * 1'b1: No Isochronous OUT Packet Dropped Interrupt Mask
  4353. */
  4354. #define USB_ISOOUTDROPMSK (BIT(14))
  4355. #define USB_ISOOUTDROPMSK_M (USB_ISOOUTDROPMSK_V << USB_ISOOUTDROPMSK_S)
  4356. #define USB_ISOOUTDROPMSK_V 0x00000001
  4357. #define USB_ISOOUTDROPMSK_S 14
  4358. /** USB_EOPFMSK : R/W; bitpos: [15]; default: 0;
  4359. * 1'b0: End of Periodic Frame Interrupt Mask
  4360. * 1'b1: No End of Periodic Frame Interrupt Mask
  4361. */
  4362. #define USB_EOPFMSK (BIT(15))
  4363. #define USB_EOPFMSK_M (USB_EOPFMSK_V << USB_EOPFMSK_S)
  4364. #define USB_EOPFMSK_V 0x00000001
  4365. #define USB_EOPFMSK_S 15
  4366. /** USB_EPMISMSK : R/W; bitpos: [17]; default: 0;
  4367. * 1'b0: Endpoint Mismatch Interrupt Mask
  4368. * 1'b1: No Endpoint Mismatch Interrupt Mask
  4369. */
  4370. #define USB_EPMISMSK (BIT(17))
  4371. #define USB_EPMISMSK_M (USB_EPMISMSK_V << USB_EPMISMSK_S)
  4372. #define USB_EPMISMSK_V 0x00000001
  4373. #define USB_EPMISMSK_S 17
  4374. /** USB_IEPINTMSK : R/W; bitpos: [18]; default: 0;
  4375. * 1'b0: IN Endpoints Interrupt Mask
  4376. * 1'b1: No IN Endpoints Interrupt Mask
  4377. */
  4378. #define USB_IEPINTMSK (BIT(18))
  4379. #define USB_IEPINTMSK_M (USB_IEPINTMSK_V << USB_IEPINTMSK_S)
  4380. #define USB_IEPINTMSK_V 0x00000001
  4381. #define USB_IEPINTMSK_S 18
  4382. /** USB_OEPINTMSK : R/W; bitpos: [19]; default: 0;
  4383. * 1'b0: OUT Endpoints Interrupt Mask
  4384. * 1'b1: No OUT Endpoints Interrupt Mask
  4385. */
  4386. #define USB_OEPINTMSK (BIT(19))
  4387. #define USB_OEPINTMSK_M (USB_OEPINTMSK_V << USB_OEPINTMSK_S)
  4388. #define USB_OEPINTMSK_V 0x00000001
  4389. #define USB_OEPINTMSK_S 19
  4390. /** USB_INCOMPISOINMSK : R/W; bitpos: [20]; default: 0;
  4391. * 1'b0: Incomplete Isochronous IN Transfer Mask
  4392. * 1'b1: No Incomplete Isochronous IN Transfer Mask
  4393. */
  4394. #define USB_INCOMPISOINMSK (BIT(20))
  4395. #define USB_INCOMPISOINMSK_M (USB_INCOMPISOINMSK_V << USB_INCOMPISOINMSK_S)
  4396. #define USB_INCOMPISOINMSK_V 0x00000001
  4397. #define USB_INCOMPISOINMSK_S 20
  4398. /** USB_INCOMPIPMSK : R/W; bitpos: [21]; default: 0;
  4399. * 1'b0: Host mode: Incomplete Periodic Transfer Mask Device mode: Incomplete
  4400. * Isochronous OUT Transfer Mask
  4401. * 1'b1: Host mode: No Incomplete Periodic Transfer Mask Device mode: No Incomplete
  4402. * Isochronous OUT Transfer Mask
  4403. */
  4404. #define USB_INCOMPIPMSK (BIT(21))
  4405. #define USB_INCOMPIPMSK_M (USB_INCOMPIPMSK_V << USB_INCOMPIPMSK_S)
  4406. #define USB_INCOMPIPMSK_V 0x00000001
  4407. #define USB_INCOMPIPMSK_S 21
  4408. /** USB_FETSUSPMSK : R/W; bitpos: [22]; default: 0;
  4409. * 1'b0: Data Fetch Suspended Mask
  4410. * 1'b1: No Data Fetch Suspended Mask
  4411. */
  4412. #define USB_FETSUSPMSK (BIT(22))
  4413. #define USB_FETSUSPMSK_M (USB_FETSUSPMSK_V << USB_FETSUSPMSK_S)
  4414. #define USB_FETSUSPMSK_V 0x00000001
  4415. #define USB_FETSUSPMSK_S 22
  4416. /** USB_RESETDETMSK : R/W; bitpos: [23]; default: 0;
  4417. * 1'b0: Reset detected Interrupt Mask
  4418. * 1'b1: No Reset detected Interrupt Mask
  4419. */
  4420. #define USB_RESETDETMSK (BIT(23))
  4421. #define USB_RESETDETMSK_M (USB_RESETDETMSK_V << USB_RESETDETMSK_S)
  4422. #define USB_RESETDETMSK_V 0x00000001
  4423. #define USB_RESETDETMSK_S 23
  4424. /** USB_PRTLNTMSK : R/W; bitpos: [24]; default: 0;
  4425. * 1'b0: Host Port Interrupt Mask
  4426. * 1'b1: No Host Port Interrupt Mask
  4427. */
  4428. #define USB_PRTLNTMSK (BIT(24))
  4429. #define USB_PRTLNTMSK_M (USB_PRTLNTMSK_V << USB_PRTLNTMSK_S)
  4430. #define USB_PRTLNTMSK_V 0x00000001
  4431. #define USB_PRTLNTMSK_S 24
  4432. /** USB_HCHINTMSK : R/W; bitpos: [25]; default: 0;
  4433. * 1'b0: Host Channels Interrupt Mask
  4434. * 1'b1: No Host Channels Interrupt Mask
  4435. */
  4436. #define USB_HCHINTMSK (BIT(25))
  4437. #define USB_HCHINTMSK_M (USB_HCHINTMSK_V << USB_HCHINTMSK_S)
  4438. #define USB_HCHINTMSK_V 0x00000001
  4439. #define USB_HCHINTMSK_S 25
  4440. /** USB_PTXFEMPMSK : R/W; bitpos: [26]; default: 0;
  4441. * 1'b0: Periodic TxFIFO Empty Mask
  4442. * 1'b1: No Periodic TxFIFO Empty Mask
  4443. */
  4444. #define USB_PTXFEMPMSK (BIT(26))
  4445. #define USB_PTXFEMPMSK_M (USB_PTXFEMPMSK_V << USB_PTXFEMPMSK_S)
  4446. #define USB_PTXFEMPMSK_V 0x00000001
  4447. #define USB_PTXFEMPMSK_S 26
  4448. /** USB_CONIDSTSCHNGMSK : R/W; bitpos: [28]; default: 0;
  4449. * 1'b0: Connector ID Status Change Mask
  4450. * 1'b1: No Connector ID Status Change Mask
  4451. */
  4452. #define USB_CONIDSTSCHNGMSK (BIT(28))
  4453. #define USB_CONIDSTSCHNGMSK_M (USB_CONIDSTSCHNGMSK_V << USB_CONIDSTSCHNGMSK_S)
  4454. #define USB_CONIDSTSCHNGMSK_V 0x00000001
  4455. #define USB_CONIDSTSCHNGMSK_S 28
  4456. /** USB_DISCONNINTMSK : R/W; bitpos: [29]; default: 0;
  4457. * 1'b0: Disconnect Detected Interrupt Mask
  4458. * 1'b1: No Disconnect Detected Interrupt Mask
  4459. */
  4460. #define USB_DISCONNINTMSK (BIT(29))
  4461. #define USB_DISCONNINTMSK_M (USB_DISCONNINTMSK_V << USB_DISCONNINTMSK_S)
  4462. #define USB_DISCONNINTMSK_V 0x00000001
  4463. #define USB_DISCONNINTMSK_S 29
  4464. /** USB_SESSREQINTMSK : R/W; bitpos: [30]; default: 0;
  4465. * 1'b0: Session Request or New Session Detected Interrupt Mask
  4466. * 1'b1: No Session Request or New Session Detected Interrupt Mask
  4467. */
  4468. #define USB_SESSREQINTMSK (BIT(30))
  4469. #define USB_SESSREQINTMSK_M (USB_SESSREQINTMSK_V << USB_SESSREQINTMSK_S)
  4470. #define USB_SESSREQINTMSK_V 0x00000001
  4471. #define USB_SESSREQINTMSK_S 30
  4472. /** USB_WKUPINTMSK : R/W; bitpos: [31]; default: 0;
  4473. * 1'b0 : Resume or Remote Wakeup Detected Interrupt Mask
  4474. * 1'b1 : Unmask Resume Remote Wakeup Detected Interrupt
  4475. */
  4476. #define USB_WKUPINTMSK (BIT(31))
  4477. #define USB_WKUPINTMSK_M (USB_WKUPINTMSK_V << USB_WKUPINTMSK_S)
  4478. #define USB_WKUPINTMSK_V 0x00000001
  4479. #define USB_WKUPINTMSK_S 31
  4480. /** USB_HAINT_REG register
  4481. * Host All Channels Interrupt Register
  4482. */
  4483. #define USB_HAINT_REG (SOC_DPORT_USB_BASE + 0x414)
  4484. /** USB_HAINT : RO; bitpos: [8:0]; default: 0;
  4485. * Channel Interrupt for channel no.
  4486. */
  4487. #define USB_HAINT 0x000000FF
  4488. #define USB_HAINT_M (USB_HAINT_V << USB_HAINT_S)
  4489. #define USB_HAINT_V 0x000000FF
  4490. #define USB_HAINT_S 0
  4491. /** USB_HAINTMSK_REG register
  4492. * Host All Channels Interrupt Mask Register
  4493. */
  4494. #define USB_HAINTMSK_REG (SOC_DPORT_USB_BASE + 0x418)
  4495. /** USB_HAINTMSK : R/W; bitpos: [8:0]; default: 0;
  4496. * Channel Interrupt Mask (HAINTMSK_REG) One bit per channel: Bit 0 for channel 0, bit
  4497. * 15 for channel 15.
  4498. */
  4499. #define USB_HAINTMSK 0x000000FF
  4500. #define USB_HAINTMSK_M (USB_HAINTMSK_V << USB_HAINTMSK_S)
  4501. #define USB_HAINTMSK_V 0x000000FF
  4502. #define USB_HAINTMSK_S 0
  4503. /** USB_HCINT0_REG register
  4504. * Host Channel 0 Interrupt Register
  4505. */
  4506. #define USB_HCINT0_REG (SOC_DPORT_USB_BASE + 0x508)
  4507. /** USB_H_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0;
  4508. * 1'b0: Transfer in progress or No Active Transfer
  4509. * 1'b1: Transfer completed normally without any errors
  4510. */
  4511. #define USB_H_XFERCOMPL0 (BIT(0))
  4512. #define USB_H_XFERCOMPL0_M (USB_H_XFERCOMPL0_V << USB_H_XFERCOMPL0_S)
  4513. #define USB_H_XFERCOMPL0_V 0x00000001
  4514. #define USB_H_XFERCOMPL0_S 0
  4515. /** USB_H_CHHLTD0 : R/W1C; bitpos: [1]; default: 0;
  4516. * 1'b0: Channel not halted
  4517. * 1'b1: Channel Halted
  4518. */
  4519. #define USB_H_CHHLTD0 (BIT(1))
  4520. #define USB_H_CHHLTD0_M (USB_H_CHHLTD0_V << USB_H_CHHLTD0_S)
  4521. #define USB_H_CHHLTD0_V 0x00000001
  4522. #define USB_H_CHHLTD0_S 1
  4523. /** USB_H_AHBERR0 : R/W1C; bitpos: [2]; default: 0;
  4524. * 1'b0: No AHB error
  4525. * 1'b1: AHB error during AHB read/write
  4526. */
  4527. #define USB_H_AHBERR0 (BIT(2))
  4528. #define USB_H_AHBERR0_M (USB_H_AHBERR0_V << USB_H_AHBERR0_S)
  4529. #define USB_H_AHBERR0_V 0x00000001
  4530. #define USB_H_AHBERR0_S 2
  4531. /** USB_H_STALL0 : R/W1C; bitpos: [3]; default: 0;
  4532. * 1'b0: No Stall Response Received Interrupt
  4533. * 1'b1: Stall Response Received Interrupt
  4534. */
  4535. #define USB_H_STALL0 (BIT(3))
  4536. #define USB_H_STALL0_M (USB_H_STALL0_V << USB_H_STALL0_S)
  4537. #define USB_H_STALL0_V 0x00000001
  4538. #define USB_H_STALL0_S 3
  4539. /** USB_H_NACK0 : R/W1C; bitpos: [4]; default: 0;
  4540. * 1'b0: No NAK Response Received Interrupt
  4541. * 1'b1: NAK Response Received Interrupt
  4542. */
  4543. #define USB_H_NACK0 (BIT(4))
  4544. #define USB_H_NACK0_M (USB_H_NACK0_V << USB_H_NACK0_S)
  4545. #define USB_H_NACK0_V 0x00000001
  4546. #define USB_H_NACK0_S 4
  4547. /** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0;
  4548. * 1'b0: No ACK Response Received or Transmitted Interrupt
  4549. * 1'b1: ACK Response Received or Transmitted Interrup
  4550. */
  4551. #define USB_H_ACK0 (BIT(5))
  4552. #define USB_H_ACK0_M (USB_H_ACK0_V << USB_H_ACK0_S)
  4553. #define USB_H_ACK0_V 0x00000001
  4554. #define USB_H_ACK0_S 5
  4555. /** USB_H_NYET0 : R/W1C; bitpos: [6]; default: 0;
  4556. * 1'b0: No NYET Response Received Interrupt
  4557. * 1'b1: NYET Response Received Interrupt
  4558. */
  4559. #define USB_H_NYET0 (BIT(6))
  4560. #define USB_H_NYET0_M (USB_H_NYET0_V << USB_H_NYET0_S)
  4561. #define USB_H_NYET0_V 0x00000001
  4562. #define USB_H_NYET0_S 6
  4563. /** USB_H_XACTERR0 : R/W1C; bitpos: [7]; default: 0;
  4564. * Indicates one of the following errors occurred on the USB:
  4565. * CRC check failure
  4566. * Timeout
  4567. * Bit stuff error
  4568. * False EOP
  4569. */
  4570. #define USB_H_XACTERR0 (BIT(7))
  4571. #define USB_H_XACTERR0_M (USB_H_XACTERR0_V << USB_H_XACTERR0_S)
  4572. #define USB_H_XACTERR0_V 0x00000001
  4573. #define USB_H_XACTERR0_S 7
  4574. /** USB_H_BBLERR0 : R/W1C; bitpos: [8]; default: 0;
  4575. * 1'b0: No Babble Error
  4576. * 1'b1: Babble Error
  4577. */
  4578. #define USB_H_BBLERR0 (BIT(8))
  4579. #define USB_H_BBLERR0_M (USB_H_BBLERR0_V << USB_H_BBLERR0_S)
  4580. #define USB_H_BBLERR0_V 0x00000001
  4581. #define USB_H_BBLERR0_S 8
  4582. /** USB_H_FRMOVRUN0 : R/W1C; bitpos: [9]; default: 0;
  4583. * 1'b0: No Frame Overrun
  4584. * 1'b1: Frame Overrun
  4585. */
  4586. #define USB_H_FRMOVRUN0 (BIT(9))
  4587. #define USB_H_FRMOVRUN0_M (USB_H_FRMOVRUN0_V << USB_H_FRMOVRUN0_S)
  4588. #define USB_H_FRMOVRUN0_V 0x00000001
  4589. #define USB_H_FRMOVRUN0_S 9
  4590. /** USB_H_DATATGLERR0 : R/W1C; bitpos: [10]; default: 0;
  4591. * 1'b0: No Data Toggle Error
  4592. * 1'b1: Data Toggle Error
  4593. */
  4594. #define USB_H_DATATGLERR0 (BIT(10))
  4595. #define USB_H_DATATGLERR0_M (USB_H_DATATGLERR0_V << USB_H_DATATGLERR0_S)
  4596. #define USB_H_DATATGLERR0_V 0x00000001
  4597. #define USB_H_DATATGLERR0_S 10
  4598. /** USB_H_BNAINTR0 : R/W1C; bitpos: [11]; default: 0;
  4599. * 1'b0: No BNA Interrupt
  4600. * 1'b1: BNA Interrupt
  4601. */
  4602. #define USB_H_BNAINTR0 (BIT(11))
  4603. #define USB_H_BNAINTR0_M (USB_H_BNAINTR0_V << USB_H_BNAINTR0_S)
  4604. #define USB_H_BNAINTR0_V 0x00000001
  4605. #define USB_H_BNAINTR0_S 11
  4606. /** USB_H_XCS_XACT_ERR0 : R/W1C; bitpos: [12]; default: 0;
  4607. * 1'b0: No Excessive Transaction Error
  4608. * 1'b1: Excessive Transaction Error
  4609. */
  4610. #define USB_H_XCS_XACT_ERR0 (BIT(12))
  4611. #define USB_H_XCS_XACT_ERR0_M (USB_H_XCS_XACT_ERR0_V << USB_H_XCS_XACT_ERR0_S)
  4612. #define USB_H_XCS_XACT_ERR0_V 0x00000001
  4613. #define USB_H_XCS_XACT_ERR0_S 12
  4614. /** USB_H_DESC_LST_ROLLINTR0 : R/W1C; bitpos: [13]; default: 0;
  4615. * 1'b0: No Descriptor rollover interrupt
  4616. * 1'b1: Descriptor rollover interrupt
  4617. */
  4618. #define USB_H_DESC_LST_ROLLINTR0 (BIT(13))
  4619. #define USB_H_DESC_LST_ROLLINTR0_M (USB_H_DESC_LST_ROLLINTR0_V << USB_H_DESC_LST_ROLLINTR0_S)
  4620. #define USB_H_DESC_LST_ROLLINTR0_V 0x00000001
  4621. #define USB_H_DESC_LST_ROLLINTR0_S 13
  4622. /** USB_HCINTMSK0_REG register
  4623. * Host Channel 0 Interrupt Mask Register
  4624. */
  4625. #define USB_HCINTMSK0_REG (SOC_DPORT_USB_BASE + 0x50c)
  4626. /** USB_H_XFERCOMPLMSK0 : R/W; bitpos: [0]; default: 0;
  4627. * 1'b0: Transfer Completed Mask
  4628. * 1'b1: No Transfer Completed Mask
  4629. */
  4630. #define USB_H_XFERCOMPLMSK0 (BIT(0))
  4631. #define USB_H_XFERCOMPLMSK0_M (USB_H_XFERCOMPLMSK0_V << USB_H_XFERCOMPLMSK0_S)
  4632. #define USB_H_XFERCOMPLMSK0_V 0x00000001
  4633. #define USB_H_XFERCOMPLMSK0_S 0
  4634. /** USB_H_CHHLTDMSK0 : R/W; bitpos: [1]; default: 0;
  4635. * 1'b0: Channel Halted Mask
  4636. * 1'b1: No Channel Halted Mask
  4637. */
  4638. #define USB_H_CHHLTDMSK0 (BIT(1))
  4639. #define USB_H_CHHLTDMSK0_M (USB_H_CHHLTDMSK0_V << USB_H_CHHLTDMSK0_S)
  4640. #define USB_H_CHHLTDMSK0_V 0x00000001
  4641. #define USB_H_CHHLTDMSK0_S 1
  4642. /** USB_H_AHBERRMSK0 : R/W; bitpos: [2]; default: 0;
  4643. * 1'b0: AHB Error Mask
  4644. * 1'b1: No AHB Error Mask
  4645. */
  4646. #define USB_H_AHBERRMSK0 (BIT(2))
  4647. #define USB_H_AHBERRMSK0_M (USB_H_AHBERRMSK0_V << USB_H_AHBERRMSK0_S)
  4648. #define USB_H_AHBERRMSK0_V 0x00000001
  4649. #define USB_H_AHBERRMSK0_S 2
  4650. /** USB_H_STALLMSK0 : R/W; bitpos: [3]; default: 0;
  4651. * 1'b0: Mask STALL Response Received Interrupt
  4652. * 1'b1: No STALL Response Received Interrupt Mask
  4653. */
  4654. #define USB_H_STALLMSK0 (BIT(3))
  4655. #define USB_H_STALLMSK0_M (USB_H_STALLMSK0_V << USB_H_STALLMSK0_S)
  4656. #define USB_H_STALLMSK0_V 0x00000001
  4657. #define USB_H_STALLMSK0_S 3
  4658. /** USB_H_NAKMSK0 : R/W; bitpos: [4]; default: 0;
  4659. * 1'b0: Mask NAK Response Received Interrupt
  4660. * 1'b1: No NAK Response Received Interrupt Mask
  4661. */
  4662. #define USB_H_NAKMSK0 (BIT(4))
  4663. #define USB_H_NAKMSK0_M (USB_H_NAKMSK0_V << USB_H_NAKMSK0_S)
  4664. #define USB_H_NAKMSK0_V 0x00000001
  4665. #define USB_H_NAKMSK0_S 4
  4666. /** USB_H_ACKMSK0 : R/W; bitpos: [5]; default: 0;
  4667. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  4668. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  4669. */
  4670. #define USB_H_ACKMSK0 (BIT(5))
  4671. #define USB_H_ACKMSK0_M (USB_H_ACKMSK0_V << USB_H_ACKMSK0_S)
  4672. #define USB_H_ACKMSK0_V 0x00000001
  4673. #define USB_H_ACKMSK0_S 5
  4674. /** USB_H_NYETMSK0 : R/W; bitpos: [6]; default: 0;
  4675. * 1'b0: Mask NYET Response Received Interrupt
  4676. * 1'b1: No NYET Response Received Interrupt Mask
  4677. */
  4678. #define USB_H_NYETMSK0 (BIT(6))
  4679. #define USB_H_NYETMSK0_M (USB_H_NYETMSK0_V << USB_H_NYETMSK0_S)
  4680. #define USB_H_NYETMSK0_V 0x00000001
  4681. #define USB_H_NYETMSK0_S 6
  4682. /** USB_H_XACTERRMSK0 : R/W; bitpos: [7]; default: 0;
  4683. * 1'b0: Mask Transaction Error
  4684. * 1'b1: No Transaction Error Mask
  4685. */
  4686. #define USB_H_XACTERRMSK0 (BIT(7))
  4687. #define USB_H_XACTERRMSK0_M (USB_H_XACTERRMSK0_V << USB_H_XACTERRMSK0_S)
  4688. #define USB_H_XACTERRMSK0_V 0x00000001
  4689. #define USB_H_XACTERRMSK0_S 7
  4690. /** USB_H_BBLERRMSK0 : R/W; bitpos: [8]; default: 0;
  4691. * Babble Error Mask
  4692. * 1'b0: Mask Babble Error
  4693. * 1'b1: No Babble Error Mask
  4694. */
  4695. #define USB_H_BBLERRMSK0 (BIT(8))
  4696. #define USB_H_BBLERRMSK0_M (USB_H_BBLERRMSK0_V << USB_H_BBLERRMSK0_S)
  4697. #define USB_H_BBLERRMSK0_V 0x00000001
  4698. #define USB_H_BBLERRMSK0_S 8
  4699. /** USB_H_FRMOVRUNMSK0 : R/W; bitpos: [9]; default: 0;
  4700. * Frame Overrun Mask
  4701. * 0x0 (MASK): Mask Overrun Mask
  4702. * 0x1 (NOMASK): No Frame Overrun Mask
  4703. */
  4704. #define USB_H_FRMOVRUNMSK0 (BIT(9))
  4705. #define USB_H_FRMOVRUNMSK0_M (USB_H_FRMOVRUNMSK0_V << USB_H_FRMOVRUNMSK0_S)
  4706. #define USB_H_FRMOVRUNMSK0_V 0x00000001
  4707. #define USB_H_FRMOVRUNMSK0_S 9
  4708. /** USB_H_DATATGLERRMSK0 : R/W; bitpos: [10]; default: 0;
  4709. * Data Toggle Error Mask n scatter/gather DMA mode for host
  4710. * 1'b0: Mask Data Toggle Error
  4711. * 1'b1: No Data Toggle Error Mask
  4712. */
  4713. #define USB_H_DATATGLERRMSK0 (BIT(10))
  4714. #define USB_H_DATATGLERRMSK0_M (USB_H_DATATGLERRMSK0_V << USB_H_DATATGLERRMSK0_S)
  4715. #define USB_H_DATATGLERRMSK0_V 0x00000001
  4716. #define USB_H_DATATGLERRMSK0_S 10
  4717. /** USB_H_BNAINTRMSK0 : R/W; bitpos: [11]; default: 0;
  4718. * BNA (Buffer Not Available) Interrupt mask register
  4719. * 1'b0: BNA Interrupt Masked
  4720. * 1'b1: BNA Interrupt not masked
  4721. */
  4722. #define USB_H_BNAINTRMSK0 (BIT(11))
  4723. #define USB_H_BNAINTRMSK0_M (USB_H_BNAINTRMSK0_V << USB_H_BNAINTRMSK0_S)
  4724. #define USB_H_BNAINTRMSK0_V 0x00000001
  4725. #define USB_H_BNAINTRMSK0_S 11
  4726. /** USB_H_DESC_LST_ROLLINTRMSK0 : R/W; bitpos: [13]; default: 0;
  4727. * Descriptor List rollover interrupt Mask
  4728. * 1'b0: Descriptor Rollover Interrupt Mask
  4729. * 1'b1: Descriptor Rollover Interrupt not masked
  4730. */
  4731. #define USB_H_DESC_LST_ROLLINTRMSK0 (BIT(13))
  4732. #define USB_H_DESC_LST_ROLLINTRMSK0_M (USB_H_DESC_LST_ROLLINTRMSK0_V << USB_H_DESC_LST_ROLLINTRMSK0_S)
  4733. #define USB_H_DESC_LST_ROLLINTRMSK0_V 0x00000001
  4734. #define USB_H_DESC_LST_ROLLINTRMSK0_S 13
  4735. /** USB_HCINT1_REG register
  4736. * Host Channel 1 Interrupt Register
  4737. */
  4738. #define USB_HCINT1_REG (SOC_DPORT_USB_BASE + 0x528)
  4739. /** USB_H_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0;
  4740. * 1'b0: Transfer in progress or No Active Transfer
  4741. * 1'b1: Transfer completed normally without any errors
  4742. */
  4743. #define USB_H_XFERCOMPL1 (BIT(0))
  4744. #define USB_H_XFERCOMPL1_M (USB_H_XFERCOMPL1_V << USB_H_XFERCOMPL1_S)
  4745. #define USB_H_XFERCOMPL1_V 0x00000001
  4746. #define USB_H_XFERCOMPL1_S 0
  4747. /** USB_H_CHHLTD1 : R/W1C; bitpos: [1]; default: 0;
  4748. * 1'b0: Channel not halted
  4749. * 1'b1: Channel Halted
  4750. */
  4751. #define USB_H_CHHLTD1 (BIT(1))
  4752. #define USB_H_CHHLTD1_M (USB_H_CHHLTD1_V << USB_H_CHHLTD1_S)
  4753. #define USB_H_CHHLTD1_V 0x00000001
  4754. #define USB_H_CHHLTD1_S 1
  4755. /** USB_H_AHBERR1 : R/W1C; bitpos: [2]; default: 0;
  4756. * 1'b0: No AHB error
  4757. * 1'b1: AHB error during AHB read/write
  4758. */
  4759. #define USB_H_AHBERR1 (BIT(2))
  4760. #define USB_H_AHBERR1_M (USB_H_AHBERR1_V << USB_H_AHBERR1_S)
  4761. #define USB_H_AHBERR1_V 0x00000001
  4762. #define USB_H_AHBERR1_S 2
  4763. /** USB_H_STALL1 : R/W1C; bitpos: [3]; default: 0;
  4764. * 1'b0: No Stall Response Received Interrupt
  4765. * 1'b1: Stall Response Received Interrupt
  4766. */
  4767. #define USB_H_STALL1 (BIT(3))
  4768. #define USB_H_STALL1_M (USB_H_STALL1_V << USB_H_STALL1_S)
  4769. #define USB_H_STALL1_V 0x00000001
  4770. #define USB_H_STALL1_S 3
  4771. /** USB_H_NACK1 : R/W1C; bitpos: [4]; default: 0;
  4772. * 1'b0: No NAK Response Received Interrupt
  4773. * 1'b1: NAK Response Received Interrupt
  4774. */
  4775. #define USB_H_NACK1 (BIT(4))
  4776. #define USB_H_NACK1_M (USB_H_NACK1_V << USB_H_NACK1_S)
  4777. #define USB_H_NACK1_V 0x00000001
  4778. #define USB_H_NACK1_S 4
  4779. /** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0;
  4780. * 1'b0: No ACK Response Received or Transmitted Interrupt
  4781. * 1'b1: ACK Response Received or Transmitted Interrup
  4782. */
  4783. #define USB_H_ACK1 (BIT(5))
  4784. #define USB_H_ACK1_M (USB_H_ACK1_V << USB_H_ACK1_S)
  4785. #define USB_H_ACK1_V 0x00000001
  4786. #define USB_H_ACK1_S 5
  4787. /** USB_H_NYET1 : R/W1C; bitpos: [6]; default: 0;
  4788. * 1'b0: No NYET Response Received Interrupt
  4789. * 1'b1: NYET Response Received Interrupt
  4790. */
  4791. #define USB_H_NYET1 (BIT(6))
  4792. #define USB_H_NYET1_M (USB_H_NYET1_V << USB_H_NYET1_S)
  4793. #define USB_H_NYET1_V 0x00000001
  4794. #define USB_H_NYET1_S 6
  4795. /** USB_H_XACTERR1 : R/W1C; bitpos: [7]; default: 0;
  4796. * Indicates one of the following errors occurred on the USB:
  4797. * CRC check failure
  4798. * Timeout
  4799. * Bit stuff error
  4800. * False EOP
  4801. */
  4802. #define USB_H_XACTERR1 (BIT(7))
  4803. #define USB_H_XACTERR1_M (USB_H_XACTERR1_V << USB_H_XACTERR1_S)
  4804. #define USB_H_XACTERR1_V 0x00000001
  4805. #define USB_H_XACTERR1_S 7
  4806. /** USB_H_BBLERR1 : R/W1C; bitpos: [8]; default: 0;
  4807. * 1'b0: No Babble Error
  4808. * 1'b1: Babble Error
  4809. */
  4810. #define USB_H_BBLERR1 (BIT(8))
  4811. #define USB_H_BBLERR1_M (USB_H_BBLERR1_V << USB_H_BBLERR1_S)
  4812. #define USB_H_BBLERR1_V 0x00000001
  4813. #define USB_H_BBLERR1_S 8
  4814. /** USB_H_FRMOVRUN1 : R/W1C; bitpos: [9]; default: 0;
  4815. * 1'b0: No Frame Overrun
  4816. * 1'b1: Frame Overrun
  4817. */
  4818. #define USB_H_FRMOVRUN1 (BIT(9))
  4819. #define USB_H_FRMOVRUN1_M (USB_H_FRMOVRUN1_V << USB_H_FRMOVRUN1_S)
  4820. #define USB_H_FRMOVRUN1_V 0x00000001
  4821. #define USB_H_FRMOVRUN1_S 9
  4822. /** USB_H_DATATGLERR1 : R/W1C; bitpos: [10]; default: 0;
  4823. * 1'b0: No Data Toggle Error
  4824. * 1'b1: Data Toggle Error
  4825. */
  4826. #define USB_H_DATATGLERR1 (BIT(10))
  4827. #define USB_H_DATATGLERR1_M (USB_H_DATATGLERR1_V << USB_H_DATATGLERR1_S)
  4828. #define USB_H_DATATGLERR1_V 0x00000001
  4829. #define USB_H_DATATGLERR1_S 10
  4830. /** USB_H_BNAINTR1 : R/W1C; bitpos: [11]; default: 0;
  4831. * 1'b0: No BNA Interrupt
  4832. * 1'b1: BNA Interrupt
  4833. */
  4834. #define USB_H_BNAINTR1 (BIT(11))
  4835. #define USB_H_BNAINTR1_M (USB_H_BNAINTR1_V << USB_H_BNAINTR1_S)
  4836. #define USB_H_BNAINTR1_V 0x00000001
  4837. #define USB_H_BNAINTR1_S 11
  4838. /** USB_H_XCS_XACT_ERR1 : R/W1C; bitpos: [12]; default: 0;
  4839. * 1'b0: No Excessive Transaction Error
  4840. * 1'b1: Excessive Transaction Error
  4841. */
  4842. #define USB_H_XCS_XACT_ERR1 (BIT(12))
  4843. #define USB_H_XCS_XACT_ERR1_M (USB_H_XCS_XACT_ERR1_V << USB_H_XCS_XACT_ERR1_S)
  4844. #define USB_H_XCS_XACT_ERR1_V 0x00000001
  4845. #define USB_H_XCS_XACT_ERR1_S 12
  4846. /** USB_H_DESC_LST_ROLLINTR1 : R/W1C; bitpos: [13]; default: 0;
  4847. * 1'b0: No Descriptor rollover interrupt
  4848. * 1'b1: Descriptor rollover interrupt
  4849. */
  4850. #define USB_H_DESC_LST_ROLLINTR1 (BIT(13))
  4851. #define USB_H_DESC_LST_ROLLINTR1_M (USB_H_DESC_LST_ROLLINTR1_V << USB_H_DESC_LST_ROLLINTR1_S)
  4852. #define USB_H_DESC_LST_ROLLINTR1_V 0x00000001
  4853. #define USB_H_DESC_LST_ROLLINTR1_S 13
  4854. /** USB_HCINTMSK1_REG register
  4855. * Host Channel 1 Interrupt Mask Register
  4856. */
  4857. #define USB_HCINTMSK1_REG (SOC_DPORT_USB_BASE + 0x52c)
  4858. /** USB_H_XFERCOMPLMSK1 : R/W; bitpos: [0]; default: 0;
  4859. * 1'b0: Transfer Completed Mask
  4860. * 1'b1: No Transfer Completed Mask
  4861. */
  4862. #define USB_H_XFERCOMPLMSK1 (BIT(0))
  4863. #define USB_H_XFERCOMPLMSK1_M (USB_H_XFERCOMPLMSK1_V << USB_H_XFERCOMPLMSK1_S)
  4864. #define USB_H_XFERCOMPLMSK1_V 0x00000001
  4865. #define USB_H_XFERCOMPLMSK1_S 0
  4866. /** USB_H_CHHLTDMSK1 : R/W; bitpos: [1]; default: 0;
  4867. * 1'b0: Channel Halted Mask
  4868. * 1'b1: No Channel Halted Mask
  4869. */
  4870. #define USB_H_CHHLTDMSK1 (BIT(1))
  4871. #define USB_H_CHHLTDMSK1_M (USB_H_CHHLTDMSK1_V << USB_H_CHHLTDMSK1_S)
  4872. #define USB_H_CHHLTDMSK1_V 0x00000001
  4873. #define USB_H_CHHLTDMSK1_S 1
  4874. /** USB_H_AHBERRMSK1 : R/W; bitpos: [2]; default: 0;
  4875. * 1'b0: AHB Error Mask
  4876. * 1'b1: No AHB Error Mask
  4877. */
  4878. #define USB_H_AHBERRMSK1 (BIT(2))
  4879. #define USB_H_AHBERRMSK1_M (USB_H_AHBERRMSK1_V << USB_H_AHBERRMSK1_S)
  4880. #define USB_H_AHBERRMSK1_V 0x00000001
  4881. #define USB_H_AHBERRMSK1_S 2
  4882. /** USB_H_STALLMSK1 : R/W; bitpos: [3]; default: 0;
  4883. * 1'b0: Mask STALL Response Received Interrupt
  4884. * 1'b1: No STALL Response Received Interrupt Mask
  4885. */
  4886. #define USB_H_STALLMSK1 (BIT(3))
  4887. #define USB_H_STALLMSK1_M (USB_H_STALLMSK1_V << USB_H_STALLMSK1_S)
  4888. #define USB_H_STALLMSK1_V 0x00000001
  4889. #define USB_H_STALLMSK1_S 3
  4890. /** USB_H_NAKMSK1 : R/W; bitpos: [4]; default: 0;
  4891. * 1'b0: Mask NAK Response Received Interrupt
  4892. * 1'b1: No NAK Response Received Interrupt Mask
  4893. */
  4894. #define USB_H_NAKMSK1 (BIT(4))
  4895. #define USB_H_NAKMSK1_M (USB_H_NAKMSK1_V << USB_H_NAKMSK1_S)
  4896. #define USB_H_NAKMSK1_V 0x00000001
  4897. #define USB_H_NAKMSK1_S 4
  4898. /** USB_H_ACKMSK1 : R/W; bitpos: [5]; default: 0;
  4899. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  4900. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  4901. */
  4902. #define USB_H_ACKMSK1 (BIT(5))
  4903. #define USB_H_ACKMSK1_M (USB_H_ACKMSK1_V << USB_H_ACKMSK1_S)
  4904. #define USB_H_ACKMSK1_V 0x00000001
  4905. #define USB_H_ACKMSK1_S 5
  4906. /** USB_H_NYETMSK1 : R/W; bitpos: [6]; default: 0;
  4907. * 1'b0: Mask NYET Response Received Interrupt
  4908. * 1'b1: No NYET Response Received Interrupt Mask
  4909. */
  4910. #define USB_H_NYETMSK1 (BIT(6))
  4911. #define USB_H_NYETMSK1_M (USB_H_NYETMSK1_V << USB_H_NYETMSK1_S)
  4912. #define USB_H_NYETMSK1_V 0x00000001
  4913. #define USB_H_NYETMSK1_S 6
  4914. /** USB_H_XACTERRMSK1 : R/W; bitpos: [7]; default: 0;
  4915. * 1'b0: Mask Transaction Error
  4916. * 1'b1: No Transaction Error Mask
  4917. */
  4918. #define USB_H_XACTERRMSK1 (BIT(7))
  4919. #define USB_H_XACTERRMSK1_M (USB_H_XACTERRMSK1_V << USB_H_XACTERRMSK1_S)
  4920. #define USB_H_XACTERRMSK1_V 0x00000001
  4921. #define USB_H_XACTERRMSK1_S 7
  4922. /** USB_H_BBLERRMSK1 : R/W; bitpos: [8]; default: 0;
  4923. * Babble Error Mask
  4924. * 1'b0: Mask Babble Error
  4925. * 1'b1: No Babble Error Mask
  4926. */
  4927. #define USB_H_BBLERRMSK1 (BIT(8))
  4928. #define USB_H_BBLERRMSK1_M (USB_H_BBLERRMSK1_V << USB_H_BBLERRMSK1_S)
  4929. #define USB_H_BBLERRMSK1_V 0x00000001
  4930. #define USB_H_BBLERRMSK1_S 8
  4931. /** USB_H_FRMOVRUNMSK1 : R/W; bitpos: [9]; default: 0;
  4932. * Frame Overrun Mask
  4933. * 0x0 (MASK): Mask Overrun Mask
  4934. * 0x1 (NOMASK): No Frame Overrun Mask
  4935. */
  4936. #define USB_H_FRMOVRUNMSK1 (BIT(9))
  4937. #define USB_H_FRMOVRUNMSK1_M (USB_H_FRMOVRUNMSK1_V << USB_H_FRMOVRUNMSK1_S)
  4938. #define USB_H_FRMOVRUNMSK1_V 0x00000001
  4939. #define USB_H_FRMOVRUNMSK1_S 9
  4940. /** USB_H_DATATGLERRMSK1 : R/W; bitpos: [10]; default: 0;
  4941. * Data Toggle Error Mask n scatter/gather DMA mode for host
  4942. * 1'b0: Mask Data Toggle Error
  4943. * 1'b1: No Data Toggle Error Mask
  4944. */
  4945. #define USB_H_DATATGLERRMSK1 (BIT(10))
  4946. #define USB_H_DATATGLERRMSK1_M (USB_H_DATATGLERRMSK1_V << USB_H_DATATGLERRMSK1_S)
  4947. #define USB_H_DATATGLERRMSK1_V 0x00000001
  4948. #define USB_H_DATATGLERRMSK1_S 10
  4949. /** USB_H_BNAINTRMSK1 : R/W; bitpos: [11]; default: 0;
  4950. * BNA (Buffer Not Available) Interrupt mask register
  4951. * 1'b0: BNA Interrupt Masked
  4952. * 1'b1: BNA Interrupt not masked
  4953. */
  4954. #define USB_H_BNAINTRMSK1 (BIT(11))
  4955. #define USB_H_BNAINTRMSK1_M (USB_H_BNAINTRMSK1_V << USB_H_BNAINTRMSK1_S)
  4956. #define USB_H_BNAINTRMSK1_V 0x00000001
  4957. #define USB_H_BNAINTRMSK1_S 11
  4958. /** USB_H_DESC_LST_ROLLINTRMSK1 : R/W; bitpos: [13]; default: 0;
  4959. * Descriptor List rollover interrupt Mask
  4960. * 1'b0: Descriptor Rollover Interrupt Mask
  4961. * 1'b1: Descriptor Rollover Interrupt not masked
  4962. */
  4963. #define USB_H_DESC_LST_ROLLINTRMSK1 (BIT(13))
  4964. #define USB_H_DESC_LST_ROLLINTRMSK1_M (USB_H_DESC_LST_ROLLINTRMSK1_V << USB_H_DESC_LST_ROLLINTRMSK1_S)
  4965. #define USB_H_DESC_LST_ROLLINTRMSK1_V 0x00000001
  4966. #define USB_H_DESC_LST_ROLLINTRMSK1_S 13
  4967. /** USB_HCINT2_REG register
  4968. * Host Channel 2 Interrupt Register
  4969. */
  4970. #define USB_HCINT2_REG (SOC_DPORT_USB_BASE + 0x548)
  4971. /** USB_H_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0;
  4972. * 1'b0: Transfer in progress or No Active Transfer
  4973. * 1'b1: Transfer completed normally without any errors
  4974. */
  4975. #define USB_H_XFERCOMPL2 (BIT(0))
  4976. #define USB_H_XFERCOMPL2_M (USB_H_XFERCOMPL2_V << USB_H_XFERCOMPL2_S)
  4977. #define USB_H_XFERCOMPL2_V 0x00000001
  4978. #define USB_H_XFERCOMPL2_S 0
  4979. /** USB_H_CHHLTD2 : R/W1C; bitpos: [1]; default: 0;
  4980. * 1'b0: Channel not halted
  4981. * 1'b1: Channel Halted
  4982. */
  4983. #define USB_H_CHHLTD2 (BIT(1))
  4984. #define USB_H_CHHLTD2_M (USB_H_CHHLTD2_V << USB_H_CHHLTD2_S)
  4985. #define USB_H_CHHLTD2_V 0x00000001
  4986. #define USB_H_CHHLTD2_S 1
  4987. /** USB_H_AHBERR2 : R/W1C; bitpos: [2]; default: 0;
  4988. * 1'b0: No AHB error
  4989. * 1'b1: AHB error during AHB read/write
  4990. */
  4991. #define USB_H_AHBERR2 (BIT(2))
  4992. #define USB_H_AHBERR2_M (USB_H_AHBERR2_V << USB_H_AHBERR2_S)
  4993. #define USB_H_AHBERR2_V 0x00000001
  4994. #define USB_H_AHBERR2_S 2
  4995. /** USB_H_STALL2 : R/W1C; bitpos: [3]; default: 0;
  4996. * 1'b0: No Stall Response Received Interrupt
  4997. * 1'b1: Stall Response Received Interrupt
  4998. */
  4999. #define USB_H_STALL2 (BIT(3))
  5000. #define USB_H_STALL2_M (USB_H_STALL2_V << USB_H_STALL2_S)
  5001. #define USB_H_STALL2_V 0x00000001
  5002. #define USB_H_STALL2_S 3
  5003. /** USB_H_NACK2 : R/W1C; bitpos: [4]; default: 0;
  5004. * 1'b0: No NAK Response Received Interrupt
  5005. * 1'b1: NAK Response Received Interrupt
  5006. */
  5007. #define USB_H_NACK2 (BIT(4))
  5008. #define USB_H_NACK2_M (USB_H_NACK2_V << USB_H_NACK2_S)
  5009. #define USB_H_NACK2_V 0x00000001
  5010. #define USB_H_NACK2_S 4
  5011. /** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0;
  5012. * 1'b0: No ACK Response Received or Transmitted Interrupt
  5013. * 1'b1: ACK Response Received or Transmitted Interrup
  5014. */
  5015. #define USB_H_ACK2 (BIT(5))
  5016. #define USB_H_ACK2_M (USB_H_ACK2_V << USB_H_ACK2_S)
  5017. #define USB_H_ACK2_V 0x00000001
  5018. #define USB_H_ACK2_S 5
  5019. /** USB_H_NYET2 : R/W1C; bitpos: [6]; default: 0;
  5020. * 1'b0: No NYET Response Received Interrupt
  5021. * 1'b1: NYET Response Received Interrupt
  5022. */
  5023. #define USB_H_NYET2 (BIT(6))
  5024. #define USB_H_NYET2_M (USB_H_NYET2_V << USB_H_NYET2_S)
  5025. #define USB_H_NYET2_V 0x00000001
  5026. #define USB_H_NYET2_S 6
  5027. /** USB_H_XACTERR2 : R/W1C; bitpos: [7]; default: 0;
  5028. * Indicates one of the following errors occurred on the USB:
  5029. * CRC check failure
  5030. * Timeout
  5031. * Bit stuff error
  5032. * False EOP
  5033. */
  5034. #define USB_H_XACTERR2 (BIT(7))
  5035. #define USB_H_XACTERR2_M (USB_H_XACTERR2_V << USB_H_XACTERR2_S)
  5036. #define USB_H_XACTERR2_V 0x00000001
  5037. #define USB_H_XACTERR2_S 7
  5038. /** USB_H_BBLERR2 : R/W1C; bitpos: [8]; default: 0;
  5039. * 1'b0: No Babble Error
  5040. * 1'b1: Babble Error
  5041. */
  5042. #define USB_H_BBLERR2 (BIT(8))
  5043. #define USB_H_BBLERR2_M (USB_H_BBLERR2_V << USB_H_BBLERR2_S)
  5044. #define USB_H_BBLERR2_V 0x00000001
  5045. #define USB_H_BBLERR2_S 8
  5046. /** USB_H_FRMOVRUN2 : R/W1C; bitpos: [9]; default: 0;
  5047. * 1'b0: No Frame Overrun
  5048. * 1'b1: Frame Overrun
  5049. */
  5050. #define USB_H_FRMOVRUN2 (BIT(9))
  5051. #define USB_H_FRMOVRUN2_M (USB_H_FRMOVRUN2_V << USB_H_FRMOVRUN2_S)
  5052. #define USB_H_FRMOVRUN2_V 0x00000001
  5053. #define USB_H_FRMOVRUN2_S 9
  5054. /** USB_H_DATATGLERR2 : R/W1C; bitpos: [10]; default: 0;
  5055. * 1'b0: No Data Toggle Error
  5056. * 1'b1: Data Toggle Error
  5057. */
  5058. #define USB_H_DATATGLERR2 (BIT(10))
  5059. #define USB_H_DATATGLERR2_M (USB_H_DATATGLERR2_V << USB_H_DATATGLERR2_S)
  5060. #define USB_H_DATATGLERR2_V 0x00000001
  5061. #define USB_H_DATATGLERR2_S 10
  5062. /** USB_H_BNAINTR2 : R/W1C; bitpos: [11]; default: 0;
  5063. * 1'b0: No BNA Interrupt
  5064. * 1'b1: BNA Interrupt
  5065. */
  5066. #define USB_H_BNAINTR2 (BIT(11))
  5067. #define USB_H_BNAINTR2_M (USB_H_BNAINTR2_V << USB_H_BNAINTR2_S)
  5068. #define USB_H_BNAINTR2_V 0x00000001
  5069. #define USB_H_BNAINTR2_S 11
  5070. /** USB_H_XCS_XACT_ERR2 : R/W1C; bitpos: [12]; default: 0;
  5071. * 1'b0: No Excessive Transaction Error
  5072. * 1'b1: Excessive Transaction Error
  5073. */
  5074. #define USB_H_XCS_XACT_ERR2 (BIT(12))
  5075. #define USB_H_XCS_XACT_ERR2_M (USB_H_XCS_XACT_ERR2_V << USB_H_XCS_XACT_ERR2_S)
  5076. #define USB_H_XCS_XACT_ERR2_V 0x00000001
  5077. #define USB_H_XCS_XACT_ERR2_S 12
  5078. /** USB_H_DESC_LST_ROLLINTR2 : R/W1C; bitpos: [13]; default: 0;
  5079. * 1'b0: No Descriptor rollover interrupt
  5080. * 1'b1: Descriptor rollover interrupt
  5081. */
  5082. #define USB_H_DESC_LST_ROLLINTR2 (BIT(13))
  5083. #define USB_H_DESC_LST_ROLLINTR2_M (USB_H_DESC_LST_ROLLINTR2_V << USB_H_DESC_LST_ROLLINTR2_S)
  5084. #define USB_H_DESC_LST_ROLLINTR2_V 0x00000001
  5085. #define USB_H_DESC_LST_ROLLINTR2_S 13
  5086. /** USB_HCINTMSK2_REG register
  5087. * Host Channel 2 Interrupt Mask Register
  5088. */
  5089. #define USB_HCINTMSK2_REG (SOC_DPORT_USB_BASE + 0x54c)
  5090. /** USB_H_XFERCOMPLMSK2 : R/W; bitpos: [0]; default: 0;
  5091. * 1'b0: Transfer Completed Mask
  5092. * 1'b1: No Transfer Completed Mask
  5093. */
  5094. #define USB_H_XFERCOMPLMSK2 (BIT(0))
  5095. #define USB_H_XFERCOMPLMSK2_M (USB_H_XFERCOMPLMSK2_V << USB_H_XFERCOMPLMSK2_S)
  5096. #define USB_H_XFERCOMPLMSK2_V 0x00000001
  5097. #define USB_H_XFERCOMPLMSK2_S 0
  5098. /** USB_H_CHHLTDMSK2 : R/W; bitpos: [1]; default: 0;
  5099. * 1'b0: Channel Halted Mask
  5100. * 1'b1: No Channel Halted Mask
  5101. */
  5102. #define USB_H_CHHLTDMSK2 (BIT(1))
  5103. #define USB_H_CHHLTDMSK2_M (USB_H_CHHLTDMSK2_V << USB_H_CHHLTDMSK2_S)
  5104. #define USB_H_CHHLTDMSK2_V 0x00000001
  5105. #define USB_H_CHHLTDMSK2_S 1
  5106. /** USB_H_AHBERRMSK2 : R/W; bitpos: [2]; default: 0;
  5107. * 1'b0: AHB Error Mask
  5108. * 1'b1: No AHB Error Mask
  5109. */
  5110. #define USB_H_AHBERRMSK2 (BIT(2))
  5111. #define USB_H_AHBERRMSK2_M (USB_H_AHBERRMSK2_V << USB_H_AHBERRMSK2_S)
  5112. #define USB_H_AHBERRMSK2_V 0x00000001
  5113. #define USB_H_AHBERRMSK2_S 2
  5114. /** USB_H_STALLMSK2 : R/W; bitpos: [3]; default: 0;
  5115. * 1'b0: Mask STALL Response Received Interrupt
  5116. * 1'b1: No STALL Response Received Interrupt Mask
  5117. */
  5118. #define USB_H_STALLMSK2 (BIT(3))
  5119. #define USB_H_STALLMSK2_M (USB_H_STALLMSK2_V << USB_H_STALLMSK2_S)
  5120. #define USB_H_STALLMSK2_V 0x00000001
  5121. #define USB_H_STALLMSK2_S 3
  5122. /** USB_H_NAKMSK2 : R/W; bitpos: [4]; default: 0;
  5123. * 1'b0: Mask NAK Response Received Interrupt
  5124. * 1'b1: No NAK Response Received Interrupt Mask
  5125. */
  5126. #define USB_H_NAKMSK2 (BIT(4))
  5127. #define USB_H_NAKMSK2_M (USB_H_NAKMSK2_V << USB_H_NAKMSK2_S)
  5128. #define USB_H_NAKMSK2_V 0x00000001
  5129. #define USB_H_NAKMSK2_S 4
  5130. /** USB_H_ACKMSK2 : R/W; bitpos: [5]; default: 0;
  5131. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  5132. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  5133. */
  5134. #define USB_H_ACKMSK2 (BIT(5))
  5135. #define USB_H_ACKMSK2_M (USB_H_ACKMSK2_V << USB_H_ACKMSK2_S)
  5136. #define USB_H_ACKMSK2_V 0x00000001
  5137. #define USB_H_ACKMSK2_S 5
  5138. /** USB_H_NYETMSK2 : R/W; bitpos: [6]; default: 0;
  5139. * 1'b0: Mask NYET Response Received Interrupt
  5140. * 1'b1: No NYET Response Received Interrupt Mask
  5141. */
  5142. #define USB_H_NYETMSK2 (BIT(6))
  5143. #define USB_H_NYETMSK2_M (USB_H_NYETMSK2_V << USB_H_NYETMSK2_S)
  5144. #define USB_H_NYETMSK2_V 0x00000001
  5145. #define USB_H_NYETMSK2_S 6
  5146. /** USB_H_XACTERRMSK2 : R/W; bitpos: [7]; default: 0;
  5147. * 1'b0: Mask Transaction Error
  5148. * 1'b1: No Transaction Error Mask
  5149. */
  5150. #define USB_H_XACTERRMSK2 (BIT(7))
  5151. #define USB_H_XACTERRMSK2_M (USB_H_XACTERRMSK2_V << USB_H_XACTERRMSK2_S)
  5152. #define USB_H_XACTERRMSK2_V 0x00000001
  5153. #define USB_H_XACTERRMSK2_S 7
  5154. /** USB_H_BBLERRMSK2 : R/W; bitpos: [8]; default: 0;
  5155. * Babble Error Mask
  5156. * 1'b0: Mask Babble Error
  5157. * 1'b1: No Babble Error Mask
  5158. */
  5159. #define USB_H_BBLERRMSK2 (BIT(8))
  5160. #define USB_H_BBLERRMSK2_M (USB_H_BBLERRMSK2_V << USB_H_BBLERRMSK2_S)
  5161. #define USB_H_BBLERRMSK2_V 0x00000001
  5162. #define USB_H_BBLERRMSK2_S 8
  5163. /** USB_H_FRMOVRUNMSK2 : R/W; bitpos: [9]; default: 0;
  5164. * Frame Overrun Mask
  5165. * 0x0 (MASK): Mask Overrun Mask
  5166. * 0x1 (NOMASK): No Frame Overrun Mask
  5167. */
  5168. #define USB_H_FRMOVRUNMSK2 (BIT(9))
  5169. #define USB_H_FRMOVRUNMSK2_M (USB_H_FRMOVRUNMSK2_V << USB_H_FRMOVRUNMSK2_S)
  5170. #define USB_H_FRMOVRUNMSK2_V 0x00000001
  5171. #define USB_H_FRMOVRUNMSK2_S 9
  5172. /** USB_H_DATATGLERRMSK2 : R/W; bitpos: [10]; default: 0;
  5173. * Data Toggle Error Mask n scatter/gather DMA mode for host
  5174. * 1'b0: Mask Data Toggle Error
  5175. * 1'b1: No Data Toggle Error Mask
  5176. */
  5177. #define USB_H_DATATGLERRMSK2 (BIT(10))
  5178. #define USB_H_DATATGLERRMSK2_M (USB_H_DATATGLERRMSK2_V << USB_H_DATATGLERRMSK2_S)
  5179. #define USB_H_DATATGLERRMSK2_V 0x00000001
  5180. #define USB_H_DATATGLERRMSK2_S 10
  5181. /** USB_H_BNAINTRMSK2 : R/W; bitpos: [11]; default: 0;
  5182. * BNA (Buffer Not Available) Interrupt mask register
  5183. * 1'b0: BNA Interrupt Masked
  5184. * 1'b1: BNA Interrupt not masked
  5185. */
  5186. #define USB_H_BNAINTRMSK2 (BIT(11))
  5187. #define USB_H_BNAINTRMSK2_M (USB_H_BNAINTRMSK2_V << USB_H_BNAINTRMSK2_S)
  5188. #define USB_H_BNAINTRMSK2_V 0x00000001
  5189. #define USB_H_BNAINTRMSK2_S 11
  5190. /** USB_H_DESC_LST_ROLLINTRMSK2 : R/W; bitpos: [13]; default: 0;
  5191. * Descriptor List rollover interrupt Mask
  5192. * 1'b0: Descriptor Rollover Interrupt Mask
  5193. * 1'b1: Descriptor Rollover Interrupt not masked
  5194. */
  5195. #define USB_H_DESC_LST_ROLLINTRMSK2 (BIT(13))
  5196. #define USB_H_DESC_LST_ROLLINTRMSK2_M (USB_H_DESC_LST_ROLLINTRMSK2_V << USB_H_DESC_LST_ROLLINTRMSK2_S)
  5197. #define USB_H_DESC_LST_ROLLINTRMSK2_V 0x00000001
  5198. #define USB_H_DESC_LST_ROLLINTRMSK2_S 13
  5199. /** USB_HCINT3_REG register
  5200. * Host Channel 3 Interrupt Register
  5201. */
  5202. #define USB_HCINT3_REG (SOC_DPORT_USB_BASE + 0x568)
  5203. /** USB_H_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0;
  5204. * 1'b0: Transfer in progress or No Active Transfer
  5205. * 1'b1: Transfer completed normally without any errors
  5206. */
  5207. #define USB_H_XFERCOMPL3 (BIT(0))
  5208. #define USB_H_XFERCOMPL3_M (USB_H_XFERCOMPL3_V << USB_H_XFERCOMPL3_S)
  5209. #define USB_H_XFERCOMPL3_V 0x00000001
  5210. #define USB_H_XFERCOMPL3_S 0
  5211. /** USB_H_CHHLTD3 : R/W1C; bitpos: [1]; default: 0;
  5212. * 1'b0: Channel not halted
  5213. * 1'b1: Channel Halted
  5214. */
  5215. #define USB_H_CHHLTD3 (BIT(1))
  5216. #define USB_H_CHHLTD3_M (USB_H_CHHLTD3_V << USB_H_CHHLTD3_S)
  5217. #define USB_H_CHHLTD3_V 0x00000001
  5218. #define USB_H_CHHLTD3_S 1
  5219. /** USB_H_AHBERR3 : R/W1C; bitpos: [2]; default: 0;
  5220. * 1'b0: No AHB error
  5221. * 1'b1: AHB error during AHB read/write
  5222. */
  5223. #define USB_H_AHBERR3 (BIT(2))
  5224. #define USB_H_AHBERR3_M (USB_H_AHBERR3_V << USB_H_AHBERR3_S)
  5225. #define USB_H_AHBERR3_V 0x00000001
  5226. #define USB_H_AHBERR3_S 2
  5227. /** USB_H_STALL3 : R/W1C; bitpos: [3]; default: 0;
  5228. * 1'b0: No Stall Response Received Interrupt
  5229. * 1'b1: Stall Response Received Interrupt
  5230. */
  5231. #define USB_H_STALL3 (BIT(3))
  5232. #define USB_H_STALL3_M (USB_H_STALL3_V << USB_H_STALL3_S)
  5233. #define USB_H_STALL3_V 0x00000001
  5234. #define USB_H_STALL3_S 3
  5235. /** USB_H_NACK3 : R/W1C; bitpos: [4]; default: 0;
  5236. * 1'b0: No NAK Response Received Interrupt
  5237. * 1'b1: NAK Response Received Interrupt
  5238. */
  5239. #define USB_H_NACK3 (BIT(4))
  5240. #define USB_H_NACK3_M (USB_H_NACK3_V << USB_H_NACK3_S)
  5241. #define USB_H_NACK3_V 0x00000001
  5242. #define USB_H_NACK3_S 4
  5243. /** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0;
  5244. * 1'b0: No ACK Response Received or Transmitted Interrupt
  5245. * 1'b1: ACK Response Received or Transmitted Interrup
  5246. */
  5247. #define USB_H_ACK3 (BIT(5))
  5248. #define USB_H_ACK3_M (USB_H_ACK3_V << USB_H_ACK3_S)
  5249. #define USB_H_ACK3_V 0x00000001
  5250. #define USB_H_ACK3_S 5
  5251. /** USB_H_NYET3 : R/W1C; bitpos: [6]; default: 0;
  5252. * 1'b0: No NYET Response Received Interrupt
  5253. * 1'b1: NYET Response Received Interrupt
  5254. */
  5255. #define USB_H_NYET3 (BIT(6))
  5256. #define USB_H_NYET3_M (USB_H_NYET3_V << USB_H_NYET3_S)
  5257. #define USB_H_NYET3_V 0x00000001
  5258. #define USB_H_NYET3_S 6
  5259. /** USB_H_XACTERR3 : R/W1C; bitpos: [7]; default: 0;
  5260. * Indicates one of the following errors occurred on the USB:
  5261. * CRC check failure
  5262. * Timeout
  5263. * Bit stuff error
  5264. * False EOP
  5265. */
  5266. #define USB_H_XACTERR3 (BIT(7))
  5267. #define USB_H_XACTERR3_M (USB_H_XACTERR3_V << USB_H_XACTERR3_S)
  5268. #define USB_H_XACTERR3_V 0x00000001
  5269. #define USB_H_XACTERR3_S 7
  5270. /** USB_H_BBLERR3 : R/W1C; bitpos: [8]; default: 0;
  5271. * 1'b0: No Babble Error
  5272. * 1'b1: Babble Error
  5273. */
  5274. #define USB_H_BBLERR3 (BIT(8))
  5275. #define USB_H_BBLERR3_M (USB_H_BBLERR3_V << USB_H_BBLERR3_S)
  5276. #define USB_H_BBLERR3_V 0x00000001
  5277. #define USB_H_BBLERR3_S 8
  5278. /** USB_H_FRMOVRUN3 : R/W1C; bitpos: [9]; default: 0;
  5279. * 1'b0: No Frame Overrun
  5280. * 1'b1: Frame Overrun
  5281. */
  5282. #define USB_H_FRMOVRUN3 (BIT(9))
  5283. #define USB_H_FRMOVRUN3_M (USB_H_FRMOVRUN3_V << USB_H_FRMOVRUN3_S)
  5284. #define USB_H_FRMOVRUN3_V 0x00000001
  5285. #define USB_H_FRMOVRUN3_S 9
  5286. /** USB_H_DATATGLERR3 : R/W1C; bitpos: [10]; default: 0;
  5287. * 1'b0: No Data Toggle Error
  5288. * 1'b1: Data Toggle Error
  5289. */
  5290. #define USB_H_DATATGLERR3 (BIT(10))
  5291. #define USB_H_DATATGLERR3_M (USB_H_DATATGLERR3_V << USB_H_DATATGLERR3_S)
  5292. #define USB_H_DATATGLERR3_V 0x00000001
  5293. #define USB_H_DATATGLERR3_S 10
  5294. /** USB_H_BNAINTR3 : R/W1C; bitpos: [11]; default: 0;
  5295. * 1'b0: No BNA Interrupt
  5296. * 1'b1: BNA Interrupt
  5297. */
  5298. #define USB_H_BNAINTR3 (BIT(11))
  5299. #define USB_H_BNAINTR3_M (USB_H_BNAINTR3_V << USB_H_BNAINTR3_S)
  5300. #define USB_H_BNAINTR3_V 0x00000001
  5301. #define USB_H_BNAINTR3_S 11
  5302. /** USB_H_XCS_XACT_ERR3 : R/W1C; bitpos: [12]; default: 0;
  5303. * 1'b0: No Excessive Transaction Error
  5304. * 1'b1: Excessive Transaction Error
  5305. */
  5306. #define USB_H_XCS_XACT_ERR3 (BIT(12))
  5307. #define USB_H_XCS_XACT_ERR3_M (USB_H_XCS_XACT_ERR3_V << USB_H_XCS_XACT_ERR3_S)
  5308. #define USB_H_XCS_XACT_ERR3_V 0x00000001
  5309. #define USB_H_XCS_XACT_ERR3_S 12
  5310. /** USB_H_DESC_LST_ROLLINTR3 : R/W1C; bitpos: [13]; default: 0;
  5311. * 1'b0: No Descriptor rollover interrupt
  5312. * 1'b1: Descriptor rollover interrupt
  5313. */
  5314. #define USB_H_DESC_LST_ROLLINTR3 (BIT(13))
  5315. #define USB_H_DESC_LST_ROLLINTR3_M (USB_H_DESC_LST_ROLLINTR3_V << USB_H_DESC_LST_ROLLINTR3_S)
  5316. #define USB_H_DESC_LST_ROLLINTR3_V 0x00000001
  5317. #define USB_H_DESC_LST_ROLLINTR3_S 13
  5318. /** USB_HCINTMSK3_REG register
  5319. * Host Channel 3 Interrupt Mask Register
  5320. */
  5321. #define USB_HCINTMSK3_REG (SOC_DPORT_USB_BASE + 0x56c)
  5322. /** USB_H_XFERCOMPLMSK3 : R/W; bitpos: [0]; default: 0;
  5323. * 1'b0: Transfer Completed Mask
  5324. * 1'b1: No Transfer Completed Mask
  5325. */
  5326. #define USB_H_XFERCOMPLMSK3 (BIT(0))
  5327. #define USB_H_XFERCOMPLMSK3_M (USB_H_XFERCOMPLMSK3_V << USB_H_XFERCOMPLMSK3_S)
  5328. #define USB_H_XFERCOMPLMSK3_V 0x00000001
  5329. #define USB_H_XFERCOMPLMSK3_S 0
  5330. /** USB_H_CHHLTDMSK3 : R/W; bitpos: [1]; default: 0;
  5331. * 1'b0: Channel Halted Mask
  5332. * 1'b1: No Channel Halted Mask
  5333. */
  5334. #define USB_H_CHHLTDMSK3 (BIT(1))
  5335. #define USB_H_CHHLTDMSK3_M (USB_H_CHHLTDMSK3_V << USB_H_CHHLTDMSK3_S)
  5336. #define USB_H_CHHLTDMSK3_V 0x00000001
  5337. #define USB_H_CHHLTDMSK3_S 1
  5338. /** USB_H_AHBERRMSK3 : R/W; bitpos: [2]; default: 0;
  5339. * 1'b0: AHB Error Mask
  5340. * 1'b1: No AHB Error Mask
  5341. */
  5342. #define USB_H_AHBERRMSK3 (BIT(2))
  5343. #define USB_H_AHBERRMSK3_M (USB_H_AHBERRMSK3_V << USB_H_AHBERRMSK3_S)
  5344. #define USB_H_AHBERRMSK3_V 0x00000001
  5345. #define USB_H_AHBERRMSK3_S 2
  5346. /** USB_H_STALLMSK3 : R/W; bitpos: [3]; default: 0;
  5347. * 1'b0: Mask STALL Response Received Interrupt
  5348. * 1'b1: No STALL Response Received Interrupt Mask
  5349. */
  5350. #define USB_H_STALLMSK3 (BIT(3))
  5351. #define USB_H_STALLMSK3_M (USB_H_STALLMSK3_V << USB_H_STALLMSK3_S)
  5352. #define USB_H_STALLMSK3_V 0x00000001
  5353. #define USB_H_STALLMSK3_S 3
  5354. /** USB_H_NAKMSK3 : R/W; bitpos: [4]; default: 0;
  5355. * 1'b0: Mask NAK Response Received Interrupt
  5356. * 1'b1: No NAK Response Received Interrupt Mask
  5357. */
  5358. #define USB_H_NAKMSK3 (BIT(4))
  5359. #define USB_H_NAKMSK3_M (USB_H_NAKMSK3_V << USB_H_NAKMSK3_S)
  5360. #define USB_H_NAKMSK3_V 0x00000001
  5361. #define USB_H_NAKMSK3_S 4
  5362. /** USB_H_ACKMSK3 : R/W; bitpos: [5]; default: 0;
  5363. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  5364. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  5365. */
  5366. #define USB_H_ACKMSK3 (BIT(5))
  5367. #define USB_H_ACKMSK3_M (USB_H_ACKMSK3_V << USB_H_ACKMSK3_S)
  5368. #define USB_H_ACKMSK3_V 0x00000001
  5369. #define USB_H_ACKMSK3_S 5
  5370. /** USB_H_NYETMSK3 : R/W; bitpos: [6]; default: 0;
  5371. * 1'b0: Mask NYET Response Received Interrupt
  5372. * 1'b1: No NYET Response Received Interrupt Mask
  5373. */
  5374. #define USB_H_NYETMSK3 (BIT(6))
  5375. #define USB_H_NYETMSK3_M (USB_H_NYETMSK3_V << USB_H_NYETMSK3_S)
  5376. #define USB_H_NYETMSK3_V 0x00000001
  5377. #define USB_H_NYETMSK3_S 6
  5378. /** USB_H_XACTERRMSK3 : R/W; bitpos: [7]; default: 0;
  5379. * 1'b0: Mask Transaction Error
  5380. * 1'b1: No Transaction Error Mask
  5381. */
  5382. #define USB_H_XACTERRMSK3 (BIT(7))
  5383. #define USB_H_XACTERRMSK3_M (USB_H_XACTERRMSK3_V << USB_H_XACTERRMSK3_S)
  5384. #define USB_H_XACTERRMSK3_V 0x00000001
  5385. #define USB_H_XACTERRMSK3_S 7
  5386. /** USB_H_BBLERRMSK3 : R/W; bitpos: [8]; default: 0;
  5387. * Babble Error Mask
  5388. * 1'b0: Mask Babble Error
  5389. * 1'b1: No Babble Error Mask
  5390. */
  5391. #define USB_H_BBLERRMSK3 (BIT(8))
  5392. #define USB_H_BBLERRMSK3_M (USB_H_BBLERRMSK3_V << USB_H_BBLERRMSK3_S)
  5393. #define USB_H_BBLERRMSK3_V 0x00000001
  5394. #define USB_H_BBLERRMSK3_S 8
  5395. /** USB_H_FRMOVRUNMSK3 : R/W; bitpos: [9]; default: 0;
  5396. * Frame Overrun Mask
  5397. * 0x0 (MASK): Mask Overrun Mask
  5398. * 0x1 (NOMASK): No Frame Overrun Mask
  5399. */
  5400. #define USB_H_FRMOVRUNMSK3 (BIT(9))
  5401. #define USB_H_FRMOVRUNMSK3_M (USB_H_FRMOVRUNMSK3_V << USB_H_FRMOVRUNMSK3_S)
  5402. #define USB_H_FRMOVRUNMSK3_V 0x00000001
  5403. #define USB_H_FRMOVRUNMSK3_S 9
  5404. /** USB_H_DATATGLERRMSK3 : R/W; bitpos: [10]; default: 0;
  5405. * Data Toggle Error Mask n scatter/gather DMA mode for host
  5406. * 1'b0: Mask Data Toggle Error
  5407. * 1'b1: No Data Toggle Error Mask
  5408. */
  5409. #define USB_H_DATATGLERRMSK3 (BIT(10))
  5410. #define USB_H_DATATGLERRMSK3_M (USB_H_DATATGLERRMSK3_V << USB_H_DATATGLERRMSK3_S)
  5411. #define USB_H_DATATGLERRMSK3_V 0x00000001
  5412. #define USB_H_DATATGLERRMSK3_S 10
  5413. /** USB_H_BNAINTRMSK3 : R/W; bitpos: [11]; default: 0;
  5414. * BNA (Buffer Not Available) Interrupt mask register
  5415. * 1'b0: BNA Interrupt Masked
  5416. * 1'b1: BNA Interrupt not masked
  5417. */
  5418. #define USB_H_BNAINTRMSK3 (BIT(11))
  5419. #define USB_H_BNAINTRMSK3_M (USB_H_BNAINTRMSK3_V << USB_H_BNAINTRMSK3_S)
  5420. #define USB_H_BNAINTRMSK3_V 0x00000001
  5421. #define USB_H_BNAINTRMSK3_S 11
  5422. /** USB_H_DESC_LST_ROLLINTRMSK3 : R/W; bitpos: [13]; default: 0;
  5423. * Descriptor List rollover interrupt Mask
  5424. * 1'b0: Descriptor Rollover Interrupt Mask
  5425. * 1'b1: Descriptor Rollover Interrupt not masked
  5426. */
  5427. #define USB_H_DESC_LST_ROLLINTRMSK3 (BIT(13))
  5428. #define USB_H_DESC_LST_ROLLINTRMSK3_M (USB_H_DESC_LST_ROLLINTRMSK3_V << USB_H_DESC_LST_ROLLINTRMSK3_S)
  5429. #define USB_H_DESC_LST_ROLLINTRMSK3_V 0x00000001
  5430. #define USB_H_DESC_LST_ROLLINTRMSK3_S 13
  5431. /** USB_HCINT4_REG register
  5432. * Host Channel 4 Interrupt Register
  5433. */
  5434. #define USB_HCINT4_REG (SOC_DPORT_USB_BASE + 0x588)
  5435. /** USB_H_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0;
  5436. * 1'b0: Transfer in progress or No Active Transfer
  5437. * 1'b1: Transfer completed normally without any errors
  5438. */
  5439. #define USB_H_XFERCOMPL4 (BIT(0))
  5440. #define USB_H_XFERCOMPL4_M (USB_H_XFERCOMPL4_V << USB_H_XFERCOMPL4_S)
  5441. #define USB_H_XFERCOMPL4_V 0x00000001
  5442. #define USB_H_XFERCOMPL4_S 0
  5443. /** USB_H_CHHLTD4 : R/W1C; bitpos: [1]; default: 0;
  5444. * 1'b0: Channel not halted
  5445. * 1'b1: Channel Halted
  5446. */
  5447. #define USB_H_CHHLTD4 (BIT(1))
  5448. #define USB_H_CHHLTD4_M (USB_H_CHHLTD4_V << USB_H_CHHLTD4_S)
  5449. #define USB_H_CHHLTD4_V 0x00000001
  5450. #define USB_H_CHHLTD4_S 1
  5451. /** USB_H_AHBERR4 : R/W1C; bitpos: [2]; default: 0;
  5452. * 1'b0: No AHB error
  5453. * 1'b1: AHB error during AHB read/write
  5454. */
  5455. #define USB_H_AHBERR4 (BIT(2))
  5456. #define USB_H_AHBERR4_M (USB_H_AHBERR4_V << USB_H_AHBERR4_S)
  5457. #define USB_H_AHBERR4_V 0x00000001
  5458. #define USB_H_AHBERR4_S 2
  5459. /** USB_H_STALL4 : R/W1C; bitpos: [3]; default: 0;
  5460. * 1'b0: No Stall Response Received Interrupt
  5461. * 1'b1: Stall Response Received Interrupt
  5462. */
  5463. #define USB_H_STALL4 (BIT(3))
  5464. #define USB_H_STALL4_M (USB_H_STALL4_V << USB_H_STALL4_S)
  5465. #define USB_H_STALL4_V 0x00000001
  5466. #define USB_H_STALL4_S 3
  5467. /** USB_H_NACK4 : R/W1C; bitpos: [4]; default: 0;
  5468. * 1'b0: No NAK Response Received Interrupt
  5469. * 1'b1: NAK Response Received Interrupt
  5470. */
  5471. #define USB_H_NACK4 (BIT(4))
  5472. #define USB_H_NACK4_M (USB_H_NACK4_V << USB_H_NACK4_S)
  5473. #define USB_H_NACK4_V 0x00000001
  5474. #define USB_H_NACK4_S 4
  5475. /** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0;
  5476. * 1'b0: No ACK Response Received or Transmitted Interrupt
  5477. * 1'b1: ACK Response Received or Transmitted Interrup
  5478. */
  5479. #define USB_H_ACK4 (BIT(5))
  5480. #define USB_H_ACK4_M (USB_H_ACK4_V << USB_H_ACK4_S)
  5481. #define USB_H_ACK4_V 0x00000001
  5482. #define USB_H_ACK4_S 5
  5483. /** USB_H_NYET4 : R/W1C; bitpos: [6]; default: 0;
  5484. * 1'b0: No NYET Response Received Interrupt
  5485. * 1'b1: NYET Response Received Interrupt
  5486. */
  5487. #define USB_H_NYET4 (BIT(6))
  5488. #define USB_H_NYET4_M (USB_H_NYET4_V << USB_H_NYET4_S)
  5489. #define USB_H_NYET4_V 0x00000001
  5490. #define USB_H_NYET4_S 6
  5491. /** USB_H_XACTERR4 : R/W1C; bitpos: [7]; default: 0;
  5492. * Indicates one of the following errors occurred on the USB:
  5493. * CRC check failure
  5494. * Timeout
  5495. * Bit stuff error
  5496. * False EOP
  5497. */
  5498. #define USB_H_XACTERR4 (BIT(7))
  5499. #define USB_H_XACTERR4_M (USB_H_XACTERR4_V << USB_H_XACTERR4_S)
  5500. #define USB_H_XACTERR4_V 0x00000001
  5501. #define USB_H_XACTERR4_S 7
  5502. /** USB_H_BBLERR4 : R/W1C; bitpos: [8]; default: 0;
  5503. * 1'b0: No Babble Error
  5504. * 1'b1: Babble Error
  5505. */
  5506. #define USB_H_BBLERR4 (BIT(8))
  5507. #define USB_H_BBLERR4_M (USB_H_BBLERR4_V << USB_H_BBLERR4_S)
  5508. #define USB_H_BBLERR4_V 0x00000001
  5509. #define USB_H_BBLERR4_S 8
  5510. /** USB_H_FRMOVRUN4 : R/W1C; bitpos: [9]; default: 0;
  5511. * 1'b0: No Frame Overrun
  5512. * 1'b1: Frame Overrun
  5513. */
  5514. #define USB_H_FRMOVRUN4 (BIT(9))
  5515. #define USB_H_FRMOVRUN4_M (USB_H_FRMOVRUN4_V << USB_H_FRMOVRUN4_S)
  5516. #define USB_H_FRMOVRUN4_V 0x00000001
  5517. #define USB_H_FRMOVRUN4_S 9
  5518. /** USB_H_DATATGLERR4 : R/W1C; bitpos: [10]; default: 0;
  5519. * 1'b0: No Data Toggle Error
  5520. * 1'b1: Data Toggle Error
  5521. */
  5522. #define USB_H_DATATGLERR4 (BIT(10))
  5523. #define USB_H_DATATGLERR4_M (USB_H_DATATGLERR4_V << USB_H_DATATGLERR4_S)
  5524. #define USB_H_DATATGLERR4_V 0x00000001
  5525. #define USB_H_DATATGLERR4_S 10
  5526. /** USB_H_BNAINTR4 : R/W1C; bitpos: [11]; default: 0;
  5527. * 1'b0: No BNA Interrupt
  5528. * 1'b1: BNA Interrupt
  5529. */
  5530. #define USB_H_BNAINTR4 (BIT(11))
  5531. #define USB_H_BNAINTR4_M (USB_H_BNAINTR4_V << USB_H_BNAINTR4_S)
  5532. #define USB_H_BNAINTR4_V 0x00000001
  5533. #define USB_H_BNAINTR4_S 11
  5534. /** USB_H_XCS_XACT_ERR4 : R/W1C; bitpos: [12]; default: 0;
  5535. * 1'b0: No Excessive Transaction Error
  5536. * 1'b1: Excessive Transaction Error
  5537. */
  5538. #define USB_H_XCS_XACT_ERR4 (BIT(12))
  5539. #define USB_H_XCS_XACT_ERR4_M (USB_H_XCS_XACT_ERR4_V << USB_H_XCS_XACT_ERR4_S)
  5540. #define USB_H_XCS_XACT_ERR4_V 0x00000001
  5541. #define USB_H_XCS_XACT_ERR4_S 12
  5542. /** USB_H_DESC_LST_ROLLINTR4 : R/W1C; bitpos: [13]; default: 0;
  5543. * 1'b0: No Descriptor rollover interrupt
  5544. * 1'b1: Descriptor rollover interrupt
  5545. */
  5546. #define USB_H_DESC_LST_ROLLINTR4 (BIT(13))
  5547. #define USB_H_DESC_LST_ROLLINTR4_M (USB_H_DESC_LST_ROLLINTR4_V << USB_H_DESC_LST_ROLLINTR4_S)
  5548. #define USB_H_DESC_LST_ROLLINTR4_V 0x00000001
  5549. #define USB_H_DESC_LST_ROLLINTR4_S 13
  5550. /** USB_HCINTMSK4_REG register
  5551. * Host Channel 4 Interrupt Mask Register
  5552. */
  5553. #define USB_HCINTMSK4_REG (SOC_DPORT_USB_BASE + 0x58c)
  5554. /** USB_H_XFERCOMPLMSK4 : R/W; bitpos: [0]; default: 0;
  5555. * 1'b0: Transfer Completed Mask
  5556. * 1'b1: No Transfer Completed Mask
  5557. */
  5558. #define USB_H_XFERCOMPLMSK4 (BIT(0))
  5559. #define USB_H_XFERCOMPLMSK4_M (USB_H_XFERCOMPLMSK4_V << USB_H_XFERCOMPLMSK4_S)
  5560. #define USB_H_XFERCOMPLMSK4_V 0x00000001
  5561. #define USB_H_XFERCOMPLMSK4_S 0
  5562. /** USB_H_CHHLTDMSK4 : R/W; bitpos: [1]; default: 0;
  5563. * 1'b0: Channel Halted Mask
  5564. * 1'b1: No Channel Halted Mask
  5565. */
  5566. #define USB_H_CHHLTDMSK4 (BIT(1))
  5567. #define USB_H_CHHLTDMSK4_M (USB_H_CHHLTDMSK4_V << USB_H_CHHLTDMSK4_S)
  5568. #define USB_H_CHHLTDMSK4_V 0x00000001
  5569. #define USB_H_CHHLTDMSK4_S 1
  5570. /** USB_H_AHBERRMSK4 : R/W; bitpos: [2]; default: 0;
  5571. * 1'b0: AHB Error Mask
  5572. * 1'b1: No AHB Error Mask
  5573. */
  5574. #define USB_H_AHBERRMSK4 (BIT(2))
  5575. #define USB_H_AHBERRMSK4_M (USB_H_AHBERRMSK4_V << USB_H_AHBERRMSK4_S)
  5576. #define USB_H_AHBERRMSK4_V 0x00000001
  5577. #define USB_H_AHBERRMSK4_S 2
  5578. /** USB_H_STALLMSK4 : R/W; bitpos: [3]; default: 0;
  5579. * 1'b0: Mask STALL Response Received Interrupt
  5580. * 1'b1: No STALL Response Received Interrupt Mask
  5581. */
  5582. #define USB_H_STALLMSK4 (BIT(3))
  5583. #define USB_H_STALLMSK4_M (USB_H_STALLMSK4_V << USB_H_STALLMSK4_S)
  5584. #define USB_H_STALLMSK4_V 0x00000001
  5585. #define USB_H_STALLMSK4_S 3
  5586. /** USB_H_NAKMSK4 : R/W; bitpos: [4]; default: 0;
  5587. * 1'b0: Mask NAK Response Received Interrupt
  5588. * 1'b1: No NAK Response Received Interrupt Mask
  5589. */
  5590. #define USB_H_NAKMSK4 (BIT(4))
  5591. #define USB_H_NAKMSK4_M (USB_H_NAKMSK4_V << USB_H_NAKMSK4_S)
  5592. #define USB_H_NAKMSK4_V 0x00000001
  5593. #define USB_H_NAKMSK4_S 4
  5594. /** USB_H_ACKMSK4 : R/W; bitpos: [5]; default: 0;
  5595. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  5596. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  5597. */
  5598. #define USB_H_ACKMSK4 (BIT(5))
  5599. #define USB_H_ACKMSK4_M (USB_H_ACKMSK4_V << USB_H_ACKMSK4_S)
  5600. #define USB_H_ACKMSK4_V 0x00000001
  5601. #define USB_H_ACKMSK4_S 5
  5602. /** USB_H_NYETMSK4 : R/W; bitpos: [6]; default: 0;
  5603. * 1'b0: Mask NYET Response Received Interrupt
  5604. * 1'b1: No NYET Response Received Interrupt Mask
  5605. */
  5606. #define USB_H_NYETMSK4 (BIT(6))
  5607. #define USB_H_NYETMSK4_M (USB_H_NYETMSK4_V << USB_H_NYETMSK4_S)
  5608. #define USB_H_NYETMSK4_V 0x00000001
  5609. #define USB_H_NYETMSK4_S 6
  5610. /** USB_H_XACTERRMSK4 : R/W; bitpos: [7]; default: 0;
  5611. * 1'b0: Mask Transaction Error
  5612. * 1'b1: No Transaction Error Mask
  5613. */
  5614. #define USB_H_XACTERRMSK4 (BIT(7))
  5615. #define USB_H_XACTERRMSK4_M (USB_H_XACTERRMSK4_V << USB_H_XACTERRMSK4_S)
  5616. #define USB_H_XACTERRMSK4_V 0x00000001
  5617. #define USB_H_XACTERRMSK4_S 7
  5618. /** USB_H_BBLERRMSK4 : R/W; bitpos: [8]; default: 0;
  5619. * Babble Error Mask
  5620. * 1'b0: Mask Babble Error
  5621. * 1'b1: No Babble Error Mask
  5622. */
  5623. #define USB_H_BBLERRMSK4 (BIT(8))
  5624. #define USB_H_BBLERRMSK4_M (USB_H_BBLERRMSK4_V << USB_H_BBLERRMSK4_S)
  5625. #define USB_H_BBLERRMSK4_V 0x00000001
  5626. #define USB_H_BBLERRMSK4_S 8
  5627. /** USB_H_FRMOVRUNMSK4 : R/W; bitpos: [9]; default: 0;
  5628. * Frame Overrun Mask
  5629. * 0x0 (MASK): Mask Overrun Mask
  5630. * 0x1 (NOMASK): No Frame Overrun Mask
  5631. */
  5632. #define USB_H_FRMOVRUNMSK4 (BIT(9))
  5633. #define USB_H_FRMOVRUNMSK4_M (USB_H_FRMOVRUNMSK4_V << USB_H_FRMOVRUNMSK4_S)
  5634. #define USB_H_FRMOVRUNMSK4_V 0x00000001
  5635. #define USB_H_FRMOVRUNMSK4_S 9
  5636. /** USB_H_DATATGLERRMSK4 : R/W; bitpos: [10]; default: 0;
  5637. * Data Toggle Error Mask n scatter/gather DMA mode for host
  5638. * 1'b0: Mask Data Toggle Error
  5639. * 1'b1: No Data Toggle Error Mask
  5640. */
  5641. #define USB_H_DATATGLERRMSK4 (BIT(10))
  5642. #define USB_H_DATATGLERRMSK4_M (USB_H_DATATGLERRMSK4_V << USB_H_DATATGLERRMSK4_S)
  5643. #define USB_H_DATATGLERRMSK4_V 0x00000001
  5644. #define USB_H_DATATGLERRMSK4_S 10
  5645. /** USB_H_BNAINTRMSK4 : R/W; bitpos: [11]; default: 0;
  5646. * BNA (Buffer Not Available) Interrupt mask register
  5647. * 1'b0: BNA Interrupt Masked
  5648. * 1'b1: BNA Interrupt not masked
  5649. */
  5650. #define USB_H_BNAINTRMSK4 (BIT(11))
  5651. #define USB_H_BNAINTRMSK4_M (USB_H_BNAINTRMSK4_V << USB_H_BNAINTRMSK4_S)
  5652. #define USB_H_BNAINTRMSK4_V 0x00000001
  5653. #define USB_H_BNAINTRMSK4_S 11
  5654. /** USB_H_DESC_LST_ROLLINTRMSK4 : R/W; bitpos: [13]; default: 0;
  5655. * Descriptor List rollover interrupt Mask
  5656. * 1'b0: Descriptor Rollover Interrupt Mask
  5657. * 1'b1: Descriptor Rollover Interrupt not masked
  5658. */
  5659. #define USB_H_DESC_LST_ROLLINTRMSK4 (BIT(13))
  5660. #define USB_H_DESC_LST_ROLLINTRMSK4_M (USB_H_DESC_LST_ROLLINTRMSK4_V << USB_H_DESC_LST_ROLLINTRMSK4_S)
  5661. #define USB_H_DESC_LST_ROLLINTRMSK4_V 0x00000001
  5662. #define USB_H_DESC_LST_ROLLINTRMSK4_S 13
  5663. /** USB_HCINT5_REG register
  5664. * Host Channel 5 Interrupt Register
  5665. */
  5666. #define USB_HCINT5_REG (SOC_DPORT_USB_BASE + 0x5a8)
  5667. /** USB_H_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0;
  5668. * 1'b0: Transfer in progress or No Active Transfer
  5669. * 1'b1: Transfer completed normally without any errors
  5670. */
  5671. #define USB_H_XFERCOMPL5 (BIT(0))
  5672. #define USB_H_XFERCOMPL5_M (USB_H_XFERCOMPL5_V << USB_H_XFERCOMPL5_S)
  5673. #define USB_H_XFERCOMPL5_V 0x00000001
  5674. #define USB_H_XFERCOMPL5_S 0
  5675. /** USB_H_CHHLTD5 : R/W1C; bitpos: [1]; default: 0;
  5676. * 1'b0: Channel not halted
  5677. * 1'b1: Channel Halted
  5678. */
  5679. #define USB_H_CHHLTD5 (BIT(1))
  5680. #define USB_H_CHHLTD5_M (USB_H_CHHLTD5_V << USB_H_CHHLTD5_S)
  5681. #define USB_H_CHHLTD5_V 0x00000001
  5682. #define USB_H_CHHLTD5_S 1
  5683. /** USB_H_AHBERR5 : R/W1C; bitpos: [2]; default: 0;
  5684. * 1'b0: No AHB error
  5685. * 1'b1: AHB error during AHB read/write
  5686. */
  5687. #define USB_H_AHBERR5 (BIT(2))
  5688. #define USB_H_AHBERR5_M (USB_H_AHBERR5_V << USB_H_AHBERR5_S)
  5689. #define USB_H_AHBERR5_V 0x00000001
  5690. #define USB_H_AHBERR5_S 2
  5691. /** USB_H_STALL5 : R/W1C; bitpos: [3]; default: 0;
  5692. * 1'b0: No Stall Response Received Interrupt
  5693. * 1'b1: Stall Response Received Interrupt
  5694. */
  5695. #define USB_H_STALL5 (BIT(3))
  5696. #define USB_H_STALL5_M (USB_H_STALL5_V << USB_H_STALL5_S)
  5697. #define USB_H_STALL5_V 0x00000001
  5698. #define USB_H_STALL5_S 3
  5699. /** USB_H_NACK5 : R/W1C; bitpos: [4]; default: 0;
  5700. * 1'b0: No NAK Response Received Interrupt
  5701. * 1'b1: NAK Response Received Interrupt
  5702. */
  5703. #define USB_H_NACK5 (BIT(4))
  5704. #define USB_H_NACK5_M (USB_H_NACK5_V << USB_H_NACK5_S)
  5705. #define USB_H_NACK5_V 0x00000001
  5706. #define USB_H_NACK5_S 4
  5707. /** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0;
  5708. * 1'b0: No ACK Response Received or Transmitted Interrupt
  5709. * 1'b1: ACK Response Received or Transmitted Interrup
  5710. */
  5711. #define USB_H_ACK5 (BIT(5))
  5712. #define USB_H_ACK5_M (USB_H_ACK5_V << USB_H_ACK5_S)
  5713. #define USB_H_ACK5_V 0x00000001
  5714. #define USB_H_ACK5_S 5
  5715. /** USB_H_NYET5 : R/W1C; bitpos: [6]; default: 0;
  5716. * 1'b0: No NYET Response Received Interrupt
  5717. * 1'b1: NYET Response Received Interrupt
  5718. */
  5719. #define USB_H_NYET5 (BIT(6))
  5720. #define USB_H_NYET5_M (USB_H_NYET5_V << USB_H_NYET5_S)
  5721. #define USB_H_NYET5_V 0x00000001
  5722. #define USB_H_NYET5_S 6
  5723. /** USB_H_XACTERR5 : R/W1C; bitpos: [7]; default: 0;
  5724. * Indicates one of the following errors occurred on the USB:
  5725. * CRC check failure
  5726. * Timeout
  5727. * Bit stuff error
  5728. * False EOP
  5729. */
  5730. #define USB_H_XACTERR5 (BIT(7))
  5731. #define USB_H_XACTERR5_M (USB_H_XACTERR5_V << USB_H_XACTERR5_S)
  5732. #define USB_H_XACTERR5_V 0x00000001
  5733. #define USB_H_XACTERR5_S 7
  5734. /** USB_H_BBLERR5 : R/W1C; bitpos: [8]; default: 0;
  5735. * 1'b0: No Babble Error
  5736. * 1'b1: Babble Error
  5737. */
  5738. #define USB_H_BBLERR5 (BIT(8))
  5739. #define USB_H_BBLERR5_M (USB_H_BBLERR5_V << USB_H_BBLERR5_S)
  5740. #define USB_H_BBLERR5_V 0x00000001
  5741. #define USB_H_BBLERR5_S 8
  5742. /** USB_H_FRMOVRUN5 : R/W1C; bitpos: [9]; default: 0;
  5743. * 1'b0: No Frame Overrun
  5744. * 1'b1: Frame Overrun
  5745. */
  5746. #define USB_H_FRMOVRUN5 (BIT(9))
  5747. #define USB_H_FRMOVRUN5_M (USB_H_FRMOVRUN5_V << USB_H_FRMOVRUN5_S)
  5748. #define USB_H_FRMOVRUN5_V 0x00000001
  5749. #define USB_H_FRMOVRUN5_S 9
  5750. /** USB_H_DATATGLERR5 : R/W1C; bitpos: [10]; default: 0;
  5751. * 1'b0: No Data Toggle Error
  5752. * 1'b1: Data Toggle Error
  5753. */
  5754. #define USB_H_DATATGLERR5 (BIT(10))
  5755. #define USB_H_DATATGLERR5_M (USB_H_DATATGLERR5_V << USB_H_DATATGLERR5_S)
  5756. #define USB_H_DATATGLERR5_V 0x00000001
  5757. #define USB_H_DATATGLERR5_S 10
  5758. /** USB_H_BNAINTR5 : R/W1C; bitpos: [11]; default: 0;
  5759. * 1'b0: No BNA Interrupt
  5760. * 1'b1: BNA Interrupt
  5761. */
  5762. #define USB_H_BNAINTR5 (BIT(11))
  5763. #define USB_H_BNAINTR5_M (USB_H_BNAINTR5_V << USB_H_BNAINTR5_S)
  5764. #define USB_H_BNAINTR5_V 0x00000001
  5765. #define USB_H_BNAINTR5_S 11
  5766. /** USB_H_XCS_XACT_ERR5 : R/W1C; bitpos: [12]; default: 0;
  5767. * 1'b0: No Excessive Transaction Error
  5768. * 1'b1: Excessive Transaction Error
  5769. */
  5770. #define USB_H_XCS_XACT_ERR5 (BIT(12))
  5771. #define USB_H_XCS_XACT_ERR5_M (USB_H_XCS_XACT_ERR5_V << USB_H_XCS_XACT_ERR5_S)
  5772. #define USB_H_XCS_XACT_ERR5_V 0x00000001
  5773. #define USB_H_XCS_XACT_ERR5_S 12
  5774. /** USB_H_DESC_LST_ROLLINTR5 : R/W1C; bitpos: [13]; default: 0;
  5775. * 1'b0: No Descriptor rollover interrupt
  5776. * 1'b1: Descriptor rollover interrupt
  5777. */
  5778. #define USB_H_DESC_LST_ROLLINTR5 (BIT(13))
  5779. #define USB_H_DESC_LST_ROLLINTR5_M (USB_H_DESC_LST_ROLLINTR5_V << USB_H_DESC_LST_ROLLINTR5_S)
  5780. #define USB_H_DESC_LST_ROLLINTR5_V 0x00000001
  5781. #define USB_H_DESC_LST_ROLLINTR5_S 13
  5782. /** USB_HCINTMSK5_REG register
  5783. * Host Channel 5 Interrupt Mask Register
  5784. */
  5785. #define USB_HCINTMSK5_REG (SOC_DPORT_USB_BASE + 0x5ac)
  5786. /** USB_H_XFERCOMPLMSK5 : R/W; bitpos: [0]; default: 0;
  5787. * 1'b0: Transfer Completed Mask
  5788. * 1'b1: No Transfer Completed Mask
  5789. */
  5790. #define USB_H_XFERCOMPLMSK5 (BIT(0))
  5791. #define USB_H_XFERCOMPLMSK5_M (USB_H_XFERCOMPLMSK5_V << USB_H_XFERCOMPLMSK5_S)
  5792. #define USB_H_XFERCOMPLMSK5_V 0x00000001
  5793. #define USB_H_XFERCOMPLMSK5_S 0
  5794. /** USB_H_CHHLTDMSK5 : R/W; bitpos: [1]; default: 0;
  5795. * 1'b0: Channel Halted Mask
  5796. * 1'b1: No Channel Halted Mask
  5797. */
  5798. #define USB_H_CHHLTDMSK5 (BIT(1))
  5799. #define USB_H_CHHLTDMSK5_M (USB_H_CHHLTDMSK5_V << USB_H_CHHLTDMSK5_S)
  5800. #define USB_H_CHHLTDMSK5_V 0x00000001
  5801. #define USB_H_CHHLTDMSK5_S 1
  5802. /** USB_H_AHBERRMSK5 : R/W; bitpos: [2]; default: 0;
  5803. * 1'b0: AHB Error Mask
  5804. * 1'b1: No AHB Error Mask
  5805. */
  5806. #define USB_H_AHBERRMSK5 (BIT(2))
  5807. #define USB_H_AHBERRMSK5_M (USB_H_AHBERRMSK5_V << USB_H_AHBERRMSK5_S)
  5808. #define USB_H_AHBERRMSK5_V 0x00000001
  5809. #define USB_H_AHBERRMSK5_S 2
  5810. /** USB_H_STALLMSK5 : R/W; bitpos: [3]; default: 0;
  5811. * 1'b0: Mask STALL Response Received Interrupt
  5812. * 1'b1: No STALL Response Received Interrupt Mask
  5813. */
  5814. #define USB_H_STALLMSK5 (BIT(3))
  5815. #define USB_H_STALLMSK5_M (USB_H_STALLMSK5_V << USB_H_STALLMSK5_S)
  5816. #define USB_H_STALLMSK5_V 0x00000001
  5817. #define USB_H_STALLMSK5_S 3
  5818. /** USB_H_NAKMSK5 : R/W; bitpos: [4]; default: 0;
  5819. * 1'b0: Mask NAK Response Received Interrupt
  5820. * 1'b1: No NAK Response Received Interrupt Mask
  5821. */
  5822. #define USB_H_NAKMSK5 (BIT(4))
  5823. #define USB_H_NAKMSK5_M (USB_H_NAKMSK5_V << USB_H_NAKMSK5_S)
  5824. #define USB_H_NAKMSK5_V 0x00000001
  5825. #define USB_H_NAKMSK5_S 4
  5826. /** USB_H_ACKMSK5 : R/W; bitpos: [5]; default: 0;
  5827. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  5828. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  5829. */
  5830. #define USB_H_ACKMSK5 (BIT(5))
  5831. #define USB_H_ACKMSK5_M (USB_H_ACKMSK5_V << USB_H_ACKMSK5_S)
  5832. #define USB_H_ACKMSK5_V 0x00000001
  5833. #define USB_H_ACKMSK5_S 5
  5834. /** USB_H_NYETMSK5 : R/W; bitpos: [6]; default: 0;
  5835. * 1'b0: Mask NYET Response Received Interrupt
  5836. * 1'b1: No NYET Response Received Interrupt Mask
  5837. */
  5838. #define USB_H_NYETMSK5 (BIT(6))
  5839. #define USB_H_NYETMSK5_M (USB_H_NYETMSK5_V << USB_H_NYETMSK5_S)
  5840. #define USB_H_NYETMSK5_V 0x00000001
  5841. #define USB_H_NYETMSK5_S 6
  5842. /** USB_H_XACTERRMSK5 : R/W; bitpos: [7]; default: 0;
  5843. * 1'b0: Mask Transaction Error
  5844. * 1'b1: No Transaction Error Mask
  5845. */
  5846. #define USB_H_XACTERRMSK5 (BIT(7))
  5847. #define USB_H_XACTERRMSK5_M (USB_H_XACTERRMSK5_V << USB_H_XACTERRMSK5_S)
  5848. #define USB_H_XACTERRMSK5_V 0x00000001
  5849. #define USB_H_XACTERRMSK5_S 7
  5850. /** USB_H_BBLERRMSK5 : R/W; bitpos: [8]; default: 0;
  5851. * Babble Error Mask
  5852. * 1'b0: Mask Babble Error
  5853. * 1'b1: No Babble Error Mask
  5854. */
  5855. #define USB_H_BBLERRMSK5 (BIT(8))
  5856. #define USB_H_BBLERRMSK5_M (USB_H_BBLERRMSK5_V << USB_H_BBLERRMSK5_S)
  5857. #define USB_H_BBLERRMSK5_V 0x00000001
  5858. #define USB_H_BBLERRMSK5_S 8
  5859. /** USB_H_FRMOVRUNMSK5 : R/W; bitpos: [9]; default: 0;
  5860. * Frame Overrun Mask
  5861. * 0x0 (MASK): Mask Overrun Mask
  5862. * 0x1 (NOMASK): No Frame Overrun Mask
  5863. */
  5864. #define USB_H_FRMOVRUNMSK5 (BIT(9))
  5865. #define USB_H_FRMOVRUNMSK5_M (USB_H_FRMOVRUNMSK5_V << USB_H_FRMOVRUNMSK5_S)
  5866. #define USB_H_FRMOVRUNMSK5_V 0x00000001
  5867. #define USB_H_FRMOVRUNMSK5_S 9
  5868. /** USB_H_DATATGLERRMSK5 : R/W; bitpos: [10]; default: 0;
  5869. * Data Toggle Error Mask n scatter/gather DMA mode for host
  5870. * 1'b0: Mask Data Toggle Error
  5871. * 1'b1: No Data Toggle Error Mask
  5872. */
  5873. #define USB_H_DATATGLERRMSK5 (BIT(10))
  5874. #define USB_H_DATATGLERRMSK5_M (USB_H_DATATGLERRMSK5_V << USB_H_DATATGLERRMSK5_S)
  5875. #define USB_H_DATATGLERRMSK5_V 0x00000001
  5876. #define USB_H_DATATGLERRMSK5_S 10
  5877. /** USB_H_BNAINTRMSK5 : R/W; bitpos: [11]; default: 0;
  5878. * BNA (Buffer Not Available) Interrupt mask register
  5879. * 1'b0: BNA Interrupt Masked
  5880. * 1'b1: BNA Interrupt not masked
  5881. */
  5882. #define USB_H_BNAINTRMSK5 (BIT(11))
  5883. #define USB_H_BNAINTRMSK5_M (USB_H_BNAINTRMSK5_V << USB_H_BNAINTRMSK5_S)
  5884. #define USB_H_BNAINTRMSK5_V 0x00000001
  5885. #define USB_H_BNAINTRMSK5_S 11
  5886. /** USB_H_DESC_LST_ROLLINTRMSK5 : R/W; bitpos: [13]; default: 0;
  5887. * Descriptor List rollover interrupt Mask
  5888. * 1'b0: Descriptor Rollover Interrupt Mask
  5889. * 1'b1: Descriptor Rollover Interrupt not masked
  5890. */
  5891. #define USB_H_DESC_LST_ROLLINTRMSK5 (BIT(13))
  5892. #define USB_H_DESC_LST_ROLLINTRMSK5_M (USB_H_DESC_LST_ROLLINTRMSK5_V << USB_H_DESC_LST_ROLLINTRMSK5_S)
  5893. #define USB_H_DESC_LST_ROLLINTRMSK5_V 0x00000001
  5894. #define USB_H_DESC_LST_ROLLINTRMSK5_S 13
  5895. /** USB_HCINT6_REG register
  5896. * Host Channel 6 Interrupt Register
  5897. */
  5898. #define USB_HCINT6_REG (SOC_DPORT_USB_BASE + 0x5c8)
  5899. /** USB_H_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0;
  5900. * 1'b0: Transfer in progress or No Active Transfer
  5901. * 1'b1: Transfer completed normally without any errors
  5902. */
  5903. #define USB_H_XFERCOMPL6 (BIT(0))
  5904. #define USB_H_XFERCOMPL6_M (USB_H_XFERCOMPL6_V << USB_H_XFERCOMPL6_S)
  5905. #define USB_H_XFERCOMPL6_V 0x00000001
  5906. #define USB_H_XFERCOMPL6_S 0
  5907. /** USB_H_CHHLTD6 : R/W1C; bitpos: [1]; default: 0;
  5908. * 1'b0: Channel not halted
  5909. * 1'b1: Channel Halted
  5910. */
  5911. #define USB_H_CHHLTD6 (BIT(1))
  5912. #define USB_H_CHHLTD6_M (USB_H_CHHLTD6_V << USB_H_CHHLTD6_S)
  5913. #define USB_H_CHHLTD6_V 0x00000001
  5914. #define USB_H_CHHLTD6_S 1
  5915. /** USB_H_AHBERR6 : R/W1C; bitpos: [2]; default: 0;
  5916. * 1'b0: No AHB error
  5917. * 1'b1: AHB error during AHB read/write
  5918. */
  5919. #define USB_H_AHBERR6 (BIT(2))
  5920. #define USB_H_AHBERR6_M (USB_H_AHBERR6_V << USB_H_AHBERR6_S)
  5921. #define USB_H_AHBERR6_V 0x00000001
  5922. #define USB_H_AHBERR6_S 2
  5923. /** USB_H_STALL6 : R/W1C; bitpos: [3]; default: 0;
  5924. * 1'b0: No Stall Response Received Interrupt
  5925. * 1'b1: Stall Response Received Interrupt
  5926. */
  5927. #define USB_H_STALL6 (BIT(3))
  5928. #define USB_H_STALL6_M (USB_H_STALL6_V << USB_H_STALL6_S)
  5929. #define USB_H_STALL6_V 0x00000001
  5930. #define USB_H_STALL6_S 3
  5931. /** USB_H_NACK6 : R/W1C; bitpos: [4]; default: 0;
  5932. * 1'b0: No NAK Response Received Interrupt
  5933. * 1'b1: NAK Response Received Interrupt
  5934. */
  5935. #define USB_H_NACK6 (BIT(4))
  5936. #define USB_H_NACK6_M (USB_H_NACK6_V << USB_H_NACK6_S)
  5937. #define USB_H_NACK6_V 0x00000001
  5938. #define USB_H_NACK6_S 4
  5939. /** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0;
  5940. * 1'b0: No ACK Response Received or Transmitted Interrupt
  5941. * 1'b1: ACK Response Received or Transmitted Interrup
  5942. */
  5943. #define USB_H_ACK6 (BIT(5))
  5944. #define USB_H_ACK6_M (USB_H_ACK6_V << USB_H_ACK6_S)
  5945. #define USB_H_ACK6_V 0x00000001
  5946. #define USB_H_ACK6_S 5
  5947. /** USB_H_NYET6 : R/W1C; bitpos: [6]; default: 0;
  5948. * 1'b0: No NYET Response Received Interrupt
  5949. * 1'b1: NYET Response Received Interrupt
  5950. */
  5951. #define USB_H_NYET6 (BIT(6))
  5952. #define USB_H_NYET6_M (USB_H_NYET6_V << USB_H_NYET6_S)
  5953. #define USB_H_NYET6_V 0x00000001
  5954. #define USB_H_NYET6_S 6
  5955. /** USB_H_XACTERR6 : R/W1C; bitpos: [7]; default: 0;
  5956. * Indicates one of the following errors occurred on the USB:
  5957. * CRC check failure
  5958. * Timeout
  5959. * Bit stuff error
  5960. * False EOP
  5961. */
  5962. #define USB_H_XACTERR6 (BIT(7))
  5963. #define USB_H_XACTERR6_M (USB_H_XACTERR6_V << USB_H_XACTERR6_S)
  5964. #define USB_H_XACTERR6_V 0x00000001
  5965. #define USB_H_XACTERR6_S 7
  5966. /** USB_H_BBLERR6 : R/W1C; bitpos: [8]; default: 0;
  5967. * 1'b0: No Babble Error
  5968. * 1'b1: Babble Error
  5969. */
  5970. #define USB_H_BBLERR6 (BIT(8))
  5971. #define USB_H_BBLERR6_M (USB_H_BBLERR6_V << USB_H_BBLERR6_S)
  5972. #define USB_H_BBLERR6_V 0x00000001
  5973. #define USB_H_BBLERR6_S 8
  5974. /** USB_H_FRMOVRUN6 : R/W1C; bitpos: [9]; default: 0;
  5975. * 1'b0: No Frame Overrun
  5976. * 1'b1: Frame Overrun
  5977. */
  5978. #define USB_H_FRMOVRUN6 (BIT(9))
  5979. #define USB_H_FRMOVRUN6_M (USB_H_FRMOVRUN6_V << USB_H_FRMOVRUN6_S)
  5980. #define USB_H_FRMOVRUN6_V 0x00000001
  5981. #define USB_H_FRMOVRUN6_S 9
  5982. /** USB_H_DATATGLERR6 : R/W1C; bitpos: [10]; default: 0;
  5983. * 1'b0: No Data Toggle Error
  5984. * 1'b1: Data Toggle Error
  5985. */
  5986. #define USB_H_DATATGLERR6 (BIT(10))
  5987. #define USB_H_DATATGLERR6_M (USB_H_DATATGLERR6_V << USB_H_DATATGLERR6_S)
  5988. #define USB_H_DATATGLERR6_V 0x00000001
  5989. #define USB_H_DATATGLERR6_S 10
  5990. /** USB_H_BNAINTR6 : R/W1C; bitpos: [11]; default: 0;
  5991. * 1'b0: No BNA Interrupt
  5992. * 1'b1: BNA Interrupt
  5993. */
  5994. #define USB_H_BNAINTR6 (BIT(11))
  5995. #define USB_H_BNAINTR6_M (USB_H_BNAINTR6_V << USB_H_BNAINTR6_S)
  5996. #define USB_H_BNAINTR6_V 0x00000001
  5997. #define USB_H_BNAINTR6_S 11
  5998. /** USB_H_XCS_XACT_ERR6 : R/W1C; bitpos: [12]; default: 0;
  5999. * 1'b0: No Excessive Transaction Error
  6000. * 1'b1: Excessive Transaction Error
  6001. */
  6002. #define USB_H_XCS_XACT_ERR6 (BIT(12))
  6003. #define USB_H_XCS_XACT_ERR6_M (USB_H_XCS_XACT_ERR6_V << USB_H_XCS_XACT_ERR6_S)
  6004. #define USB_H_XCS_XACT_ERR6_V 0x00000001
  6005. #define USB_H_XCS_XACT_ERR6_S 12
  6006. /** USB_H_DESC_LST_ROLLINTR6 : R/W1C; bitpos: [13]; default: 0;
  6007. * 1'b0: No Descriptor rollover interrupt
  6008. * 1'b1: Descriptor rollover interrupt
  6009. */
  6010. #define USB_H_DESC_LST_ROLLINTR6 (BIT(13))
  6011. #define USB_H_DESC_LST_ROLLINTR6_M (USB_H_DESC_LST_ROLLINTR6_V << USB_H_DESC_LST_ROLLINTR6_S)
  6012. #define USB_H_DESC_LST_ROLLINTR6_V 0x00000001
  6013. #define USB_H_DESC_LST_ROLLINTR6_S 13
  6014. /** USB_HCINTMSK6_REG register
  6015. * Host Channel 6 Interrupt Mask Register
  6016. */
  6017. #define USB_HCINTMSK6_REG (SOC_DPORT_USB_BASE + 0x5cc)
  6018. /** USB_H_XFERCOMPLMSK6 : R/W; bitpos: [0]; default: 0;
  6019. * 1'b0: Transfer Completed Mask
  6020. * 1'b1: No Transfer Completed Mask
  6021. */
  6022. #define USB_H_XFERCOMPLMSK6 (BIT(0))
  6023. #define USB_H_XFERCOMPLMSK6_M (USB_H_XFERCOMPLMSK6_V << USB_H_XFERCOMPLMSK6_S)
  6024. #define USB_H_XFERCOMPLMSK6_V 0x00000001
  6025. #define USB_H_XFERCOMPLMSK6_S 0
  6026. /** USB_H_CHHLTDMSK6 : R/W; bitpos: [1]; default: 0;
  6027. * 1'b0: Channel Halted Mask
  6028. * 1'b1: No Channel Halted Mask
  6029. */
  6030. #define USB_H_CHHLTDMSK6 (BIT(1))
  6031. #define USB_H_CHHLTDMSK6_M (USB_H_CHHLTDMSK6_V << USB_H_CHHLTDMSK6_S)
  6032. #define USB_H_CHHLTDMSK6_V 0x00000001
  6033. #define USB_H_CHHLTDMSK6_S 1
  6034. /** USB_H_AHBERRMSK6 : R/W; bitpos: [2]; default: 0;
  6035. * 1'b0: AHB Error Mask
  6036. * 1'b1: No AHB Error Mask
  6037. */
  6038. #define USB_H_AHBERRMSK6 (BIT(2))
  6039. #define USB_H_AHBERRMSK6_M (USB_H_AHBERRMSK6_V << USB_H_AHBERRMSK6_S)
  6040. #define USB_H_AHBERRMSK6_V 0x00000001
  6041. #define USB_H_AHBERRMSK6_S 2
  6042. /** USB_H_STALLMSK6 : R/W; bitpos: [3]; default: 0;
  6043. * 1'b0: Mask STALL Response Received Interrupt
  6044. * 1'b1: No STALL Response Received Interrupt Mask
  6045. */
  6046. #define USB_H_STALLMSK6 (BIT(3))
  6047. #define USB_H_STALLMSK6_M (USB_H_STALLMSK6_V << USB_H_STALLMSK6_S)
  6048. #define USB_H_STALLMSK6_V 0x00000001
  6049. #define USB_H_STALLMSK6_S 3
  6050. /** USB_H_NAKMSK6 : R/W; bitpos: [4]; default: 0;
  6051. * 1'b0: Mask NAK Response Received Interrupt
  6052. * 1'b1: No NAK Response Received Interrupt Mask
  6053. */
  6054. #define USB_H_NAKMSK6 (BIT(4))
  6055. #define USB_H_NAKMSK6_M (USB_H_NAKMSK6_V << USB_H_NAKMSK6_S)
  6056. #define USB_H_NAKMSK6_V 0x00000001
  6057. #define USB_H_NAKMSK6_S 4
  6058. /** USB_H_ACKMSK6 : R/W; bitpos: [5]; default: 0;
  6059. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  6060. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  6061. */
  6062. #define USB_H_ACKMSK6 (BIT(5))
  6063. #define USB_H_ACKMSK6_M (USB_H_ACKMSK6_V << USB_H_ACKMSK6_S)
  6064. #define USB_H_ACKMSK6_V 0x00000001
  6065. #define USB_H_ACKMSK6_S 5
  6066. /** USB_H_NYETMSK6 : R/W; bitpos: [6]; default: 0;
  6067. * 1'b0: Mask NYET Response Received Interrupt
  6068. * 1'b1: No NYET Response Received Interrupt Mask
  6069. */
  6070. #define USB_H_NYETMSK6 (BIT(6))
  6071. #define USB_H_NYETMSK6_M (USB_H_NYETMSK6_V << USB_H_NYETMSK6_S)
  6072. #define USB_H_NYETMSK6_V 0x00000001
  6073. #define USB_H_NYETMSK6_S 6
  6074. /** USB_H_XACTERRMSK6 : R/W; bitpos: [7]; default: 0;
  6075. * 1'b0: Mask Transaction Error
  6076. * 1'b1: No Transaction Error Mask
  6077. */
  6078. #define USB_H_XACTERRMSK6 (BIT(7))
  6079. #define USB_H_XACTERRMSK6_M (USB_H_XACTERRMSK6_V << USB_H_XACTERRMSK6_S)
  6080. #define USB_H_XACTERRMSK6_V 0x00000001
  6081. #define USB_H_XACTERRMSK6_S 7
  6082. /** USB_H_BBLERRMSK6 : R/W; bitpos: [8]; default: 0;
  6083. * Babble Error Mask
  6084. * 1'b0: Mask Babble Error
  6085. * 1'b1: No Babble Error Mask
  6086. */
  6087. #define USB_H_BBLERRMSK6 (BIT(8))
  6088. #define USB_H_BBLERRMSK6_M (USB_H_BBLERRMSK6_V << USB_H_BBLERRMSK6_S)
  6089. #define USB_H_BBLERRMSK6_V 0x00000001
  6090. #define USB_H_BBLERRMSK6_S 8
  6091. /** USB_H_FRMOVRUNMSK6 : R/W; bitpos: [9]; default: 0;
  6092. * Frame Overrun Mask
  6093. * 0x0 (MASK): Mask Overrun Mask
  6094. * 0x1 (NOMASK): No Frame Overrun Mask
  6095. */
  6096. #define USB_H_FRMOVRUNMSK6 (BIT(9))
  6097. #define USB_H_FRMOVRUNMSK6_M (USB_H_FRMOVRUNMSK6_V << USB_H_FRMOVRUNMSK6_S)
  6098. #define USB_H_FRMOVRUNMSK6_V 0x00000001
  6099. #define USB_H_FRMOVRUNMSK6_S 9
  6100. /** USB_H_DATATGLERRMSK6 : R/W; bitpos: [10]; default: 0;
  6101. * Data Toggle Error Mask n scatter/gather DMA mode for host
  6102. * 1'b0: Mask Data Toggle Error
  6103. * 1'b1: No Data Toggle Error Mask
  6104. */
  6105. #define USB_H_DATATGLERRMSK6 (BIT(10))
  6106. #define USB_H_DATATGLERRMSK6_M (USB_H_DATATGLERRMSK6_V << USB_H_DATATGLERRMSK6_S)
  6107. #define USB_H_DATATGLERRMSK6_V 0x00000001
  6108. #define USB_H_DATATGLERRMSK6_S 10
  6109. /** USB_H_BNAINTRMSK6 : R/W; bitpos: [11]; default: 0;
  6110. * BNA (Buffer Not Available) Interrupt mask register
  6111. * 1'b0: BNA Interrupt Masked
  6112. * 1'b1: BNA Interrupt not masked
  6113. */
  6114. #define USB_H_BNAINTRMSK6 (BIT(11))
  6115. #define USB_H_BNAINTRMSK6_M (USB_H_BNAINTRMSK6_V << USB_H_BNAINTRMSK6_S)
  6116. #define USB_H_BNAINTRMSK6_V 0x00000001
  6117. #define USB_H_BNAINTRMSK6_S 11
  6118. /** USB_H_DESC_LST_ROLLINTRMSK6 : R/W; bitpos: [13]; default: 0;
  6119. * Descriptor List rollover interrupt Mask
  6120. * 1'b0: Descriptor Rollover Interrupt Mask
  6121. * 1'b1: Descriptor Rollover Interrupt not masked
  6122. */
  6123. #define USB_H_DESC_LST_ROLLINTRMSK6 (BIT(13))
  6124. #define USB_H_DESC_LST_ROLLINTRMSK6_M (USB_H_DESC_LST_ROLLINTRMSK6_V << USB_H_DESC_LST_ROLLINTRMSK6_S)
  6125. #define USB_H_DESC_LST_ROLLINTRMSK6_V 0x00000001
  6126. #define USB_H_DESC_LST_ROLLINTRMSK6_S 13
  6127. /** USB_HCINT7_REG register
  6128. * Host Channel 7 Interrupt Register
  6129. */
  6130. #define USB_HCINT7_REG (SOC_DPORT_USB_BASE + 0x5e8)
  6131. /** USB_H_XFERCOMPL7 : R/W1C; bitpos: [0]; default: 0;
  6132. * 1'b0: Transfer in progress or No Active Transfer
  6133. * 1'b1: Transfer completed normally without any errors
  6134. */
  6135. #define USB_H_XFERCOMPL7 (BIT(0))
  6136. #define USB_H_XFERCOMPL7_M (USB_H_XFERCOMPL7_V << USB_H_XFERCOMPL7_S)
  6137. #define USB_H_XFERCOMPL7_V 0x00000001
  6138. #define USB_H_XFERCOMPL7_S 0
  6139. /** USB_H_CHHLTD7 : R/W1C; bitpos: [1]; default: 0;
  6140. * 1'b0: Channel not halted
  6141. * 1'b1: Channel Halted
  6142. */
  6143. #define USB_H_CHHLTD7 (BIT(1))
  6144. #define USB_H_CHHLTD7_M (USB_H_CHHLTD7_V << USB_H_CHHLTD7_S)
  6145. #define USB_H_CHHLTD7_V 0x00000001
  6146. #define USB_H_CHHLTD7_S 1
  6147. /** USB_H_AHBERR7 : R/W1C; bitpos: [2]; default: 0;
  6148. * 1'b0: No AHB error
  6149. * 1'b1: AHB error during AHB read/write
  6150. */
  6151. #define USB_H_AHBERR7 (BIT(2))
  6152. #define USB_H_AHBERR7_M (USB_H_AHBERR7_V << USB_H_AHBERR7_S)
  6153. #define USB_H_AHBERR7_V 0x00000001
  6154. #define USB_H_AHBERR7_S 2
  6155. /** USB_H_STALL7 : R/W1C; bitpos: [3]; default: 0;
  6156. * 1'b0: No Stall Response Received Interrupt
  6157. * 1'b1: Stall Response Received Interrupt
  6158. */
  6159. #define USB_H_STALL7 (BIT(3))
  6160. #define USB_H_STALL7_M (USB_H_STALL7_V << USB_H_STALL7_S)
  6161. #define USB_H_STALL7_V 0x00000001
  6162. #define USB_H_STALL7_S 3
  6163. /** USB_H_NACK7 : R/W1C; bitpos: [4]; default: 0;
  6164. * 1'b0: No NAK Response Received Interrupt
  6165. * 1'b1: NAK Response Received Interrupt
  6166. */
  6167. #define USB_H_NACK7 (BIT(4))
  6168. #define USB_H_NACK7_M (USB_H_NACK7_V << USB_H_NACK7_S)
  6169. #define USB_H_NACK7_V 0x00000001
  6170. #define USB_H_NACK7_S 4
  6171. /** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0;
  6172. * 1'b0: No ACK Response Received or Transmitted Interrupt
  6173. * 1'b1: ACK Response Received or Transmitted Interrup
  6174. */
  6175. #define USB_H_ACK7 (BIT(5))
  6176. #define USB_H_ACK7_M (USB_H_ACK7_V << USB_H_ACK7_S)
  6177. #define USB_H_ACK7_V 0x00000001
  6178. #define USB_H_ACK7_S 5
  6179. /** USB_H_NYET7 : R/W1C; bitpos: [6]; default: 0;
  6180. * 1'b0: No NYET Response Received Interrupt
  6181. * 1'b1: NYET Response Received Interrupt
  6182. */
  6183. #define USB_H_NYET7 (BIT(6))
  6184. #define USB_H_NYET7_M (USB_H_NYET7_V << USB_H_NYET7_S)
  6185. #define USB_H_NYET7_V 0x00000001
  6186. #define USB_H_NYET7_S 6
  6187. /** USB_H_XACTERR7 : R/W1C; bitpos: [7]; default: 0;
  6188. * Indicates one of the following errors occurred on the USB:
  6189. * CRC check failure
  6190. * Timeout
  6191. * Bit stuff error
  6192. * False EOP
  6193. */
  6194. #define USB_H_XACTERR7 (BIT(7))
  6195. #define USB_H_XACTERR7_M (USB_H_XACTERR7_V << USB_H_XACTERR7_S)
  6196. #define USB_H_XACTERR7_V 0x00000001
  6197. #define USB_H_XACTERR7_S 7
  6198. /** USB_H_BBLERR7 : R/W1C; bitpos: [8]; default: 0;
  6199. * 1'b0: No Babble Error
  6200. * 1'b1: Babble Error
  6201. */
  6202. #define USB_H_BBLERR7 (BIT(8))
  6203. #define USB_H_BBLERR7_M (USB_H_BBLERR7_V << USB_H_BBLERR7_S)
  6204. #define USB_H_BBLERR7_V 0x00000001
  6205. #define USB_H_BBLERR7_S 8
  6206. /** USB_H_FRMOVRUN7 : R/W1C; bitpos: [9]; default: 0;
  6207. * 1'b0: No Frame Overrun
  6208. * 1'b1: Frame Overrun
  6209. */
  6210. #define USB_H_FRMOVRUN7 (BIT(9))
  6211. #define USB_H_FRMOVRUN7_M (USB_H_FRMOVRUN7_V << USB_H_FRMOVRUN7_S)
  6212. #define USB_H_FRMOVRUN7_V 0x00000001
  6213. #define USB_H_FRMOVRUN7_S 9
  6214. /** USB_H_DATATGLERR7 : R/W1C; bitpos: [10]; default: 0;
  6215. * 1'b0: No Data Toggle Error
  6216. * 1'b1: Data Toggle Error
  6217. */
  6218. #define USB_H_DATATGLERR7 (BIT(10))
  6219. #define USB_H_DATATGLERR7_M (USB_H_DATATGLERR7_V << USB_H_DATATGLERR7_S)
  6220. #define USB_H_DATATGLERR7_V 0x00000001
  6221. #define USB_H_DATATGLERR7_S 10
  6222. /** USB_H_BNAINTR7 : R/W1C; bitpos: [11]; default: 0;
  6223. * 1'b0: No BNA Interrupt
  6224. * 1'b1: BNA Interrupt
  6225. */
  6226. #define USB_H_BNAINTR7 (BIT(11))
  6227. #define USB_H_BNAINTR7_M (USB_H_BNAINTR7_V << USB_H_BNAINTR7_S)
  6228. #define USB_H_BNAINTR7_V 0x00000001
  6229. #define USB_H_BNAINTR7_S 11
  6230. /** USB_H_XCS_XACT_ERR7 : R/W1C; bitpos: [12]; default: 0;
  6231. * 1'b0: No Excessive Transaction Error
  6232. * 1'b1: Excessive Transaction Error
  6233. */
  6234. #define USB_H_XCS_XACT_ERR7 (BIT(12))
  6235. #define USB_H_XCS_XACT_ERR7_M (USB_H_XCS_XACT_ERR7_V << USB_H_XCS_XACT_ERR7_S)
  6236. #define USB_H_XCS_XACT_ERR7_V 0x00000001
  6237. #define USB_H_XCS_XACT_ERR7_S 12
  6238. /** USB_H_DESC_LST_ROLLINTR7 : R/W1C; bitpos: [13]; default: 0;
  6239. * 1'b0: No Descriptor rollover interrupt
  6240. * 1'b1: Descriptor rollover interrupt
  6241. */
  6242. #define USB_H_DESC_LST_ROLLINTR7 (BIT(13))
  6243. #define USB_H_DESC_LST_ROLLINTR7_M (USB_H_DESC_LST_ROLLINTR7_V << USB_H_DESC_LST_ROLLINTR7_S)
  6244. #define USB_H_DESC_LST_ROLLINTR7_V 0x00000001
  6245. #define USB_H_DESC_LST_ROLLINTR7_S 13
  6246. /** USB_HCINTMSK7_REG register
  6247. * Host Channel 7 Interrupt Mask Register
  6248. */
  6249. #define USB_HCINTMSK7_REG (SOC_DPORT_USB_BASE + 0x5ec)
  6250. /** USB_H_XFERCOMPLMSK7 : R/W; bitpos: [0]; default: 0;
  6251. * 1'b0: Transfer Completed Mask
  6252. * 1'b1: No Transfer Completed Mask
  6253. */
  6254. #define USB_H_XFERCOMPLMSK7 (BIT(0))
  6255. #define USB_H_XFERCOMPLMSK7_M (USB_H_XFERCOMPLMSK7_V << USB_H_XFERCOMPLMSK7_S)
  6256. #define USB_H_XFERCOMPLMSK7_V 0x00000001
  6257. #define USB_H_XFERCOMPLMSK7_S 0
  6258. /** USB_H_CHHLTDMSK7 : R/W; bitpos: [1]; default: 0;
  6259. * 1'b0: Channel Halted Mask
  6260. * 1'b1: No Channel Halted Mask
  6261. */
  6262. #define USB_H_CHHLTDMSK7 (BIT(1))
  6263. #define USB_H_CHHLTDMSK7_M (USB_H_CHHLTDMSK7_V << USB_H_CHHLTDMSK7_S)
  6264. #define USB_H_CHHLTDMSK7_V 0x00000001
  6265. #define USB_H_CHHLTDMSK7_S 1
  6266. /** USB_H_AHBERRMSK7 : R/W; bitpos: [2]; default: 0;
  6267. * 1'b0: AHB Error Mask
  6268. * 1'b1: No AHB Error Mask
  6269. */
  6270. #define USB_H_AHBERRMSK7 (BIT(2))
  6271. #define USB_H_AHBERRMSK7_M (USB_H_AHBERRMSK7_V << USB_H_AHBERRMSK7_S)
  6272. #define USB_H_AHBERRMSK7_V 0x00000001
  6273. #define USB_H_AHBERRMSK7_S 2
  6274. /** USB_H_STALLMSK7 : R/W; bitpos: [3]; default: 0;
  6275. * 1'b0: Mask STALL Response Received Interrupt
  6276. * 1'b1: No STALL Response Received Interrupt Mask
  6277. */
  6278. #define USB_H_STALLMSK7 (BIT(3))
  6279. #define USB_H_STALLMSK7_M (USB_H_STALLMSK7_V << USB_H_STALLMSK7_S)
  6280. #define USB_H_STALLMSK7_V 0x00000001
  6281. #define USB_H_STALLMSK7_S 3
  6282. /** USB_H_NAKMSK7 : R/W; bitpos: [4]; default: 0;
  6283. * 1'b0: Mask NAK Response Received Interrupt
  6284. * 1'b1: No NAK Response Received Interrupt Mask
  6285. */
  6286. #define USB_H_NAKMSK7 (BIT(4))
  6287. #define USB_H_NAKMSK7_M (USB_H_NAKMSK7_V << USB_H_NAKMSK7_S)
  6288. #define USB_H_NAKMSK7_V 0x00000001
  6289. #define USB_H_NAKMSK7_S 4
  6290. /** USB_H_ACKMSK7 : R/W; bitpos: [5]; default: 0;
  6291. * 1'b0: Mask ACK Response Received/Transmitted Interrupt
  6292. * 1'b1: No ACK Response Received/Transmitted Interrupt Mask
  6293. */
  6294. #define USB_H_ACKMSK7 (BIT(5))
  6295. #define USB_H_ACKMSK7_M (USB_H_ACKMSK7_V << USB_H_ACKMSK7_S)
  6296. #define USB_H_ACKMSK7_V 0x00000001
  6297. #define USB_H_ACKMSK7_S 5
  6298. /** USB_H_NYETMSK7 : R/W; bitpos: [6]; default: 0;
  6299. * 1'b0: Mask NYET Response Received Interrupt
  6300. * 1'b1: No NYET Response Received Interrupt Mask
  6301. */
  6302. #define USB_H_NYETMSK7 (BIT(6))
  6303. #define USB_H_NYETMSK7_M (USB_H_NYETMSK7_V << USB_H_NYETMSK7_S)
  6304. #define USB_H_NYETMSK7_V 0x00000001
  6305. #define USB_H_NYETMSK7_S 6
  6306. /** USB_H_XACTERRMSK7 : R/W; bitpos: [7]; default: 0;
  6307. * 1'b0: Mask Transaction Error
  6308. * 1'b1: No Transaction Error Mask
  6309. */
  6310. #define USB_H_XACTERRMSK7 (BIT(7))
  6311. #define USB_H_XACTERRMSK7_M (USB_H_XACTERRMSK7_V << USB_H_XACTERRMSK7_S)
  6312. #define USB_H_XACTERRMSK7_V 0x00000001
  6313. #define USB_H_XACTERRMSK7_S 7
  6314. /** USB_H_BBLERRMSK7 : R/W; bitpos: [8]; default: 0;
  6315. * Babble Error Mask
  6316. * 1'b0: Mask Babble Error
  6317. * 1'b1: No Babble Error Mask
  6318. */
  6319. #define USB_H_BBLERRMSK7 (BIT(8))
  6320. #define USB_H_BBLERRMSK7_M (USB_H_BBLERRMSK7_V << USB_H_BBLERRMSK7_S)
  6321. #define USB_H_BBLERRMSK7_V 0x00000001
  6322. #define USB_H_BBLERRMSK7_S 8
  6323. /** USB_H_FRMOVRUNMSK7 : R/W; bitpos: [9]; default: 0;
  6324. * Frame Overrun Mask
  6325. * 0x0 (MASK): Mask Overrun Mask
  6326. * 0x1 (NOMASK): No Frame Overrun Mask
  6327. */
  6328. #define USB_H_FRMOVRUNMSK7 (BIT(9))
  6329. #define USB_H_FRMOVRUNMSK7_M (USB_H_FRMOVRUNMSK7_V << USB_H_FRMOVRUNMSK7_S)
  6330. #define USB_H_FRMOVRUNMSK7_V 0x00000001
  6331. #define USB_H_FRMOVRUNMSK7_S 9
  6332. /** USB_H_DATATGLERRMSK7 : R/W; bitpos: [10]; default: 0;
  6333. * Data Toggle Error Mask n scatter/gather DMA mode for host
  6334. * 1'b0: Mask Data Toggle Error
  6335. * 1'b1: No Data Toggle Error Mask
  6336. */
  6337. #define USB_H_DATATGLERRMSK7 (BIT(10))
  6338. #define USB_H_DATATGLERRMSK7_M (USB_H_DATATGLERRMSK7_V << USB_H_DATATGLERRMSK7_S)
  6339. #define USB_H_DATATGLERRMSK7_V 0x00000001
  6340. #define USB_H_DATATGLERRMSK7_S 10
  6341. /** USB_H_BNAINTRMSK7 : R/W; bitpos: [11]; default: 0;
  6342. * BNA (Buffer Not Available) Interrupt mask register
  6343. * 1'b0: BNA Interrupt Masked
  6344. * 1'b1: BNA Interrupt not masked
  6345. */
  6346. #define USB_H_BNAINTRMSK7 (BIT(11))
  6347. #define USB_H_BNAINTRMSK7_M (USB_H_BNAINTRMSK7_V << USB_H_BNAINTRMSK7_S)
  6348. #define USB_H_BNAINTRMSK7_V 0x00000001
  6349. #define USB_H_BNAINTRMSK7_S 11
  6350. /** USB_H_DESC_LST_ROLLINTRMSK7 : R/W; bitpos: [13]; default: 0;
  6351. * Descriptor List rollover interrupt Mask
  6352. * 1'b0: Descriptor Rollover Interrupt Mask
  6353. * 1'b1: Descriptor Rollover Interrupt not masked
  6354. */
  6355. #define USB_H_DESC_LST_ROLLINTRMSK7 (BIT(13))
  6356. #define USB_H_DESC_LST_ROLLINTRMSK7_M (USB_H_DESC_LST_ROLLINTRMSK7_V << USB_H_DESC_LST_ROLLINTRMSK7_S)
  6357. #define USB_H_DESC_LST_ROLLINTRMSK7_V 0x00000001
  6358. #define USB_H_DESC_LST_ROLLINTRMSK7_S 13
  6359. /** USB_DIEPMSK_REG register
  6360. * Device IN Endpoint Common Interrupt Mask Register
  6361. */
  6362. #define USB_DIEPMSK_REG (SOC_DPORT_USB_BASE + 0x810)
  6363. /** USB_DI_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0;
  6364. * 0x0 : Mask Transfer Completed Interrupt
  6365. * 0x1 : No Transfer Completed Interrupt Mask
  6366. */
  6367. #define USB_DI_XFERCOMPLMSK (BIT(0))
  6368. #define USB_DI_XFERCOMPLMSK_M (USB_DI_XFERCOMPLMSK_V << USB_DI_XFERCOMPLMSK_S)
  6369. #define USB_DI_XFERCOMPLMSK_V 0x00000001
  6370. #define USB_DI_XFERCOMPLMSK_S 0
  6371. /** USB_DI_EPDISBLDMSK : R/W; bitpos: [1]; default: 0;
  6372. * 0x0 : Mask Endpoint Disabled Interrupt
  6373. * 0x1 : No Endpoint Disabled Interrupt Mask
  6374. */
  6375. #define USB_DI_EPDISBLDMSK (BIT(1))
  6376. #define USB_DI_EPDISBLDMSK_M (USB_DI_EPDISBLDMSK_V << USB_DI_EPDISBLDMSK_S)
  6377. #define USB_DI_EPDISBLDMSK_V 0x00000001
  6378. #define USB_DI_EPDISBLDMSK_S 1
  6379. /** USB_DI_AHBERMSK : R/W; bitpos: [2]; default: 0;
  6380. * 0x0 : Mask AHB Error Interrupt
  6381. * 0x1 : No AHB Error Interrupt Mask
  6382. */
  6383. #define USB_DI_AHBERMSK (BIT(2))
  6384. #define USB_DI_AHBERMSK_M (USB_DI_AHBERMSK_V << USB_DI_AHBERMSK_S)
  6385. #define USB_DI_AHBERMSK_V 0x00000001
  6386. #define USB_DI_AHBERMSK_S 2
  6387. /** USB_TIMEOUTMSK : R/W; bitpos: [3]; default: 0;
  6388. * 0x0 : Mask Timeout Condition Interrupt
  6389. * 0x1 : No Timeout Condition Interrupt Mask
  6390. */
  6391. #define USB_TIMEOUTMSK (BIT(3))
  6392. #define USB_TIMEOUTMSK_M (USB_TIMEOUTMSK_V << USB_TIMEOUTMSK_S)
  6393. #define USB_TIMEOUTMSK_V 0x00000001
  6394. #define USB_TIMEOUTMSK_S 3
  6395. /** USB_INTKNTXFEMPMSK : R/W; bitpos: [4]; default: 0;
  6396. * 0x0 : Mask IN Token Received When TxFIFO Empty Interrupt
  6397. * 0x1 : No IN Token Received When TxFIFO Empty Interrupt
  6398. */
  6399. #define USB_INTKNTXFEMPMSK (BIT(4))
  6400. #define USB_INTKNTXFEMPMSK_M (USB_INTKNTXFEMPMSK_V << USB_INTKNTXFEMPMSK_S)
  6401. #define USB_INTKNTXFEMPMSK_V 0x00000001
  6402. #define USB_INTKNTXFEMPMSK_S 4
  6403. /** USB_INTKNEPMISMSK : R/W; bitpos: [5]; default: 0;
  6404. * 0x0 : Mask IN Token received with EP Mismatch Interrupt
  6405. * 0x1 : No Mask IN Token received with EP Mismatch Interrupt
  6406. */
  6407. #define USB_INTKNEPMISMSK (BIT(5))
  6408. #define USB_INTKNEPMISMSK_M (USB_INTKNEPMISMSK_V << USB_INTKNEPMISMSK_S)
  6409. #define USB_INTKNEPMISMSK_V 0x00000001
  6410. #define USB_INTKNEPMISMSK_S 5
  6411. /** USB_INEPNAKEFFMSK : R/W; bitpos: [6]; default: 0;
  6412. * 0x0 : Mask IN Endpoint NAK Effective Interrupt
  6413. * 0x1 : No IN Endpoint NAK Effective Interrupt Mask
  6414. */
  6415. #define USB_INEPNAKEFFMSK (BIT(6))
  6416. #define USB_INEPNAKEFFMSK_M (USB_INEPNAKEFFMSK_V << USB_INEPNAKEFFMSK_S)
  6417. #define USB_INEPNAKEFFMSK_V 0x00000001
  6418. #define USB_INEPNAKEFFMSK_S 6
  6419. /** USB_TXFIFOUNDRNMSK : R/W; bitpos: [8]; default: 0;
  6420. * 0x0 : Mask Fifo Underrun Interrupt
  6421. * 0x1 : No Fifo Underrun Interrupt Mask
  6422. */
  6423. #define USB_TXFIFOUNDRNMSK (BIT(8))
  6424. #define USB_TXFIFOUNDRNMSK_M (USB_TXFIFOUNDRNMSK_V << USB_TXFIFOUNDRNMSK_S)
  6425. #define USB_TXFIFOUNDRNMSK_V 0x00000001
  6426. #define USB_TXFIFOUNDRNMSK_S 8
  6427. /** USB_BNAININTRMSK : R/W; bitpos: [9]; default: 0;
  6428. * 0x0 : Mask BNA Interrupt
  6429. * 0x1 : No BNA Interrupt Mask
  6430. */
  6431. #define USB_BNAININTRMSK (BIT(9))
  6432. #define USB_BNAININTRMSK_M (USB_BNAININTRMSK_V << USB_BNAININTRMSK_S)
  6433. #define USB_BNAININTRMSK_V 0x00000001
  6434. #define USB_BNAININTRMSK_S 9
  6435. /** USB_DI_NAKMSK : R/W; bitpos: [13]; default: 0;
  6436. * 0x0 : Mask NAK Interrupt
  6437. * 0x1 : No Mask NAK Interrupt
  6438. */
  6439. #define USB_DI_NAKMSK (BIT(13))
  6440. #define USB_DI_NAKMSK_M (USB_DI_NAKMSK_V << USB_DI_NAKMSK_S)
  6441. #define USB_DI_NAKMSK_V 0x00000001
  6442. #define USB_DI_NAKMSK_S 13
  6443. /** USB_DOEPMSK_REG register
  6444. * Device OUT Endpoint Common Interrupt Mask Register
  6445. */
  6446. #define USB_DOEPMSK_REG (SOC_DPORT_USB_BASE + 0x814)
  6447. /** USB_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0;
  6448. * 0x0 : Mask Transfer Completed Interrupt
  6449. * 0x1 : No Transfer Completed Interrupt Mask
  6450. */
  6451. #define USB_XFERCOMPLMSK (BIT(0))
  6452. #define USB_XFERCOMPLMSK_M (USB_XFERCOMPLMSK_V << USB_XFERCOMPLMSK_S)
  6453. #define USB_XFERCOMPLMSK_V 0x00000001
  6454. #define USB_XFERCOMPLMSK_S 0
  6455. /** USB_EPDISBLDMSK : R/W; bitpos: [1]; default: 0;
  6456. * 0x0 : Mask Endpoint Disabled Interrupt
  6457. * 0x1 : No Endpoint Disabled Interrupt Mask
  6458. */
  6459. #define USB_EPDISBLDMSK (BIT(1))
  6460. #define USB_EPDISBLDMSK_M (USB_EPDISBLDMSK_V << USB_EPDISBLDMSK_S)
  6461. #define USB_EPDISBLDMSK_V 0x00000001
  6462. #define USB_EPDISBLDMSK_S 1
  6463. /** USB_AHBERMSK : R/W; bitpos: [2]; default: 0;
  6464. * 0x0 : Mask AHB Error Interrupt
  6465. * 0x1 : No AHB Error Interrupt Mask
  6466. */
  6467. #define USB_AHBERMSK (BIT(2))
  6468. #define USB_AHBERMSK_M (USB_AHBERMSK_V << USB_AHBERMSK_S)
  6469. #define USB_AHBERMSK_V 0x00000001
  6470. #define USB_AHBERMSK_S 2
  6471. /** USB_SETUPMSK : R/W; bitpos: [3]; default: 0;
  6472. * 0x0 : Mask SETUP Phase Done Interrupt
  6473. * 0x1 : No SETUP Phase Done Interrupt Mask
  6474. */
  6475. #define USB_SETUPMSK (BIT(3))
  6476. #define USB_SETUPMSK_M (USB_SETUPMSK_V << USB_SETUPMSK_S)
  6477. #define USB_SETUPMSK_V 0x00000001
  6478. #define USB_SETUPMSK_S 3
  6479. /** USB_OUTTKNEPDISMSK : R/W; bitpos: [4]; default: 0;
  6480. * 0x0 : Mask OUT Token Received when Endpoint Disabled Interrupt
  6481. * 0x1 : No OUT Token Received when Endpoint Disabled Interrupt Mask
  6482. */
  6483. #define USB_OUTTKNEPDISMSK (BIT(4))
  6484. #define USB_OUTTKNEPDISMSK_M (USB_OUTTKNEPDISMSK_V << USB_OUTTKNEPDISMSK_S)
  6485. #define USB_OUTTKNEPDISMSK_V 0x00000001
  6486. #define USB_OUTTKNEPDISMSK_S 4
  6487. /** USB_STSPHSERCVDMSK : R/W; bitpos: [5]; default: 0;
  6488. * 0x0 : Status Phase Received Mask
  6489. * 0x1 : No Status Phase Received Mask
  6490. */
  6491. #define USB_STSPHSERCVDMSK (BIT(5))
  6492. #define USB_STSPHSERCVDMSK_M (USB_STSPHSERCVDMSK_V << USB_STSPHSERCVDMSK_S)
  6493. #define USB_STSPHSERCVDMSK_V 0x00000001
  6494. #define USB_STSPHSERCVDMSK_S 5
  6495. /** USB_BACK2BACKSETUP : R/W; bitpos: [6]; default: 0;
  6496. * 0x0 : Mask Back-to-Back SETUP Packets Received Interrupt
  6497. * 0x1 : No Back-to-Back SETUP Packets Received Interrupt Mask
  6498. */
  6499. #define USB_BACK2BACKSETUP (BIT(6))
  6500. #define USB_BACK2BACKSETUP_M (USB_BACK2BACKSETUP_V << USB_BACK2BACKSETUP_S)
  6501. #define USB_BACK2BACKSETUP_V 0x00000001
  6502. #define USB_BACK2BACKSETUP_S 6
  6503. /** USB_OUTPKTERRMSK : R/W; bitpos: [8]; default: 0;
  6504. * 0x0 : Mask OUT Packet Error Interrupt
  6505. * 0x1 : No OUT Packet Error Interrupt Mask
  6506. */
  6507. #define USB_OUTPKTERRMSK (BIT(8))
  6508. #define USB_OUTPKTERRMSK_M (USB_OUTPKTERRMSK_V << USB_OUTPKTERRMSK_S)
  6509. #define USB_OUTPKTERRMSK_V 0x00000001
  6510. #define USB_OUTPKTERRMSK_S 8
  6511. /** USB_BNAOUTINTRMSK : R/W; bitpos: [9]; default: 0;
  6512. * 0x0 : Mask BNA Interrupt
  6513. * 0x1 : No BNA Interrupt Mask
  6514. */
  6515. #define USB_BNAOUTINTRMSK (BIT(9))
  6516. #define USB_BNAOUTINTRMSK_M (USB_BNAOUTINTRMSK_V << USB_BNAOUTINTRMSK_S)
  6517. #define USB_BNAOUTINTRMSK_V 0x00000001
  6518. #define USB_BNAOUTINTRMSK_S 9
  6519. /** USB_BBLEERRMSK : R/W; bitpos: [12]; default: 0;
  6520. * 0x0 : Mask Babble Error Interrupt
  6521. * 0x1 : No Babble Error Interrupt Mask
  6522. */
  6523. #define USB_BBLEERRMSK (BIT(12))
  6524. #define USB_BBLEERRMSK_M (USB_BBLEERRMSK_V << USB_BBLEERRMSK_S)
  6525. #define USB_BBLEERRMSK_V 0x00000001
  6526. #define USB_BBLEERRMSK_S 12
  6527. /** USB_NAKMSK : R/W; bitpos: [13]; default: 0;
  6528. * 0x0 : Mask NAK Interrupt
  6529. * 0x1 : No NAK Interrupt Mask
  6530. */
  6531. #define USB_NAKMSK (BIT(13))
  6532. #define USB_NAKMSK_M (USB_NAKMSK_V << USB_NAKMSK_S)
  6533. #define USB_NAKMSK_V 0x00000001
  6534. #define USB_NAKMSK_S 13
  6535. /** USB_NYETMSK : R/W; bitpos: [14]; default: 0;
  6536. * NYET interrupt Mask
  6537. * 0x0 : Mask NYET Interrupt
  6538. * 0x1 : No NYET Interrupt Mask
  6539. */
  6540. #define USB_NYETMSK (BIT(14))
  6541. #define USB_NYETMSK_M (USB_NYETMSK_V << USB_NYETMSK_S)
  6542. #define USB_NYETMSK_V 0x00000001
  6543. #define USB_NYETMSK_S 14
  6544. /** USB_DAINT_REG register
  6545. * Device All Endpoints Interrupt Register
  6546. */
  6547. #define USB_DAINT_REG (SOC_DPORT_USB_BASE + 0x818)
  6548. /** USB_INEPINT0 : RO; bitpos: [0]; default: 0;
  6549. * IN Endpoint 0 Interrupt Bit.
  6550. */
  6551. #define USB_INEPINT0 (BIT(0))
  6552. #define USB_INEPINT0_M (USB_INEPINT0_V << USB_INEPINT0_S)
  6553. #define USB_INEPINT0_V 0x00000001
  6554. #define USB_INEPINT0_S 0
  6555. /** USB_INEPINT1 : RO; bitpos: [1]; default: 0;
  6556. * IN Endpoint 1 Interrupt Bit.
  6557. */
  6558. #define USB_INEPINT1 (BIT(1))
  6559. #define USB_INEPINT1_M (USB_INEPINT1_V << USB_INEPINT1_S)
  6560. #define USB_INEPINT1_V 0x00000001
  6561. #define USB_INEPINT1_S 1
  6562. /** USB_INEPINT2 : RO; bitpos: [2]; default: 0;
  6563. * IN Endpoint 2 Interrupt Bit.
  6564. */
  6565. #define USB_INEPINT2 (BIT(2))
  6566. #define USB_INEPINT2_M (USB_INEPINT2_V << USB_INEPINT2_S)
  6567. #define USB_INEPINT2_V 0x00000001
  6568. #define USB_INEPINT2_S 2
  6569. /** USB_INEPINT3 : RO; bitpos: [3]; default: 0;
  6570. * IN Endpoint 3 Interrupt Bit.
  6571. */
  6572. #define USB_INEPINT3 (BIT(3))
  6573. #define USB_INEPINT3_M (USB_INEPINT3_V << USB_INEPINT3_S)
  6574. #define USB_INEPINT3_V 0x00000001
  6575. #define USB_INEPINT3_S 3
  6576. /** USB_INEPINT4 : RO; bitpos: [4]; default: 0;
  6577. * IN Endpoint 4 Interrupt Bit.
  6578. */
  6579. #define USB_INEPINT4 (BIT(4))
  6580. #define USB_INEPINT4_M (USB_INEPINT4_V << USB_INEPINT4_S)
  6581. #define USB_INEPINT4_V 0x00000001
  6582. #define USB_INEPINT4_S 4
  6583. /** USB_INEPINT5 : RO; bitpos: [5]; default: 0;
  6584. * IN Endpoint 5 Interrupt Bit.
  6585. */
  6586. #define USB_INEPINT5 (BIT(5))
  6587. #define USB_INEPINT5_M (USB_INEPINT5_V << USB_INEPINT5_S)
  6588. #define USB_INEPINT5_V 0x00000001
  6589. #define USB_INEPINT5_S 5
  6590. /** USB_INEPINT6 : RO; bitpos: [6]; default: 0;
  6591. * IN Endpoint 6 Interrupt Bit.
  6592. */
  6593. #define USB_INEPINT6 (BIT(6))
  6594. #define USB_INEPINT6_M (USB_INEPINT6_V << USB_INEPINT6_S)
  6595. #define USB_INEPINT6_V 0x00000001
  6596. #define USB_INEPINT6_S 6
  6597. /** USB_OUTEPINT0 : RO; bitpos: [16]; default: 0;
  6598. * OUT Endpoint 0 Interrupt Bit.
  6599. */
  6600. #define USB_OUTEPINT0 (BIT(16))
  6601. #define USB_OUTEPINT0_M (USB_OUTEPINT0_V << USB_OUTEPINT0_S)
  6602. #define USB_OUTEPINT0_V 0x00000001
  6603. #define USB_OUTEPINT0_S 16
  6604. /** USB_OUTEPINT1 : RO; bitpos: [17]; default: 0;
  6605. * OUT Endpoint 1 Interrupt Bit.
  6606. */
  6607. #define USB_OUTEPINT1 (BIT(17))
  6608. #define USB_OUTEPINT1_M (USB_OUTEPINT1_V << USB_OUTEPINT1_S)
  6609. #define USB_OUTEPINT1_V 0x00000001
  6610. #define USB_OUTEPINT1_S 17
  6611. /** USB_OUTEPINT2 : RO; bitpos: [18]; default: 0;
  6612. * OUT Endpoint 2 Interrupt Bit.
  6613. */
  6614. #define USB_OUTEPINT2 (BIT(18))
  6615. #define USB_OUTEPINT2_M (USB_OUTEPINT2_V << USB_OUTEPINT2_S)
  6616. #define USB_OUTEPINT2_V 0x00000001
  6617. #define USB_OUTEPINT2_S 18
  6618. /** USB_OUTEPINT3 : RO; bitpos: [19]; default: 0;
  6619. * OUT Endpoint 3 Interrupt Bit.
  6620. */
  6621. #define USB_OUTEPINT3 (BIT(19))
  6622. #define USB_OUTEPINT3_M (USB_OUTEPINT3_V << USB_OUTEPINT3_S)
  6623. #define USB_OUTEPINT3_V 0x00000001
  6624. #define USB_OUTEPINT3_S 19
  6625. /** USB_OUTEPINT4 : RO; bitpos: [20]; default: 0;
  6626. * OUT Endpoint 4 Interrupt Bit.
  6627. */
  6628. #define USB_OUTEPINT4 (BIT(20))
  6629. #define USB_OUTEPINT4_M (USB_OUTEPINT4_V << USB_OUTEPINT4_S)
  6630. #define USB_OUTEPINT4_V 0x00000001
  6631. #define USB_OUTEPINT4_S 20
  6632. /** USB_OUTEPINT5 : RO; bitpos: [21]; default: 0;
  6633. * OUT Endpoint 5 Interrupt Bit.
  6634. */
  6635. #define USB_OUTEPINT5 (BIT(21))
  6636. #define USB_OUTEPINT5_M (USB_OUTEPINT5_V << USB_OUTEPINT5_S)
  6637. #define USB_OUTEPINT5_V 0x00000001
  6638. #define USB_OUTEPINT5_S 21
  6639. /** USB_OUTEPINT6 : RO; bitpos: [22]; default: 0;
  6640. * OUT Endpoint 6 Interrupt Bit.
  6641. */
  6642. #define USB_OUTEPINT6 (BIT(22))
  6643. #define USB_OUTEPINT6_M (USB_OUTEPINT6_V << USB_OUTEPINT6_S)
  6644. #define USB_OUTEPINT6_V 0x00000001
  6645. #define USB_OUTEPINT6_S 22
  6646. /** USB_DAINTMSK_REG register
  6647. * Device All Endpoints Interrupt Mask Register
  6648. */
  6649. #define USB_DAINTMSK_REG (SOC_DPORT_USB_BASE + 0x81c)
  6650. /** USB_INEPMSK0 : R/W; bitpos: [0]; default: 0;
  6651. * IN Endpoint 0 Interrupt mask Bit.
  6652. */
  6653. #define USB_INEPMSK0 (BIT(0))
  6654. #define USB_INEPMSK0_M (USB_INEPMSK0_V << USB_INEPMSK0_S)
  6655. #define USB_INEPMSK0_V 0x00000001
  6656. #define USB_INEPMSK0_S 0
  6657. /** USB_INEPMSK1 : R/W; bitpos: [1]; default: 0;
  6658. * IN Endpoint 1 Interrupt mask Bit.
  6659. */
  6660. #define USB_INEPMSK1 (BIT(1))
  6661. #define USB_INEPMSK1_M (USB_INEPMSK1_V << USB_INEPMSK1_S)
  6662. #define USB_INEPMSK1_V 0x00000001
  6663. #define USB_INEPMSK1_S 1
  6664. /** USB_INEPMSK2 : R/W; bitpos: [2]; default: 0;
  6665. * IN Endpoint 2 Interrupt mask Bit.
  6666. */
  6667. #define USB_INEPMSK2 (BIT(2))
  6668. #define USB_INEPMSK2_M (USB_INEPMSK2_V << USB_INEPMSK2_S)
  6669. #define USB_INEPMSK2_V 0x00000001
  6670. #define USB_INEPMSK2_S 2
  6671. /** USB_INEPMSK3 : R/W; bitpos: [3]; default: 0;
  6672. * IN Endpoint 3 Interrupt mask Bit.
  6673. */
  6674. #define USB_INEPMSK3 (BIT(3))
  6675. #define USB_INEPMSK3_M (USB_INEPMSK3_V << USB_INEPMSK3_S)
  6676. #define USB_INEPMSK3_V 0x00000001
  6677. #define USB_INEPMSK3_S 3
  6678. /** USB_INEPMSK4 : R/W; bitpos: [4]; default: 0;
  6679. * IN Endpoint 4 Interrupt mask Bit.
  6680. */
  6681. #define USB_INEPMSK4 (BIT(4))
  6682. #define USB_INEPMSK4_M (USB_INEPMSK4_V << USB_INEPMSK4_S)
  6683. #define USB_INEPMSK4_V 0x00000001
  6684. #define USB_INEPMSK4_S 4
  6685. /** USB_INEPMSK5 : R/W; bitpos: [5]; default: 0;
  6686. * IN Endpoint 5 Interrupt mask Bit.
  6687. */
  6688. #define USB_INEPMSK5 (BIT(5))
  6689. #define USB_INEPMSK5_M (USB_INEPMSK5_V << USB_INEPMSK5_S)
  6690. #define USB_INEPMSK5_V 0x00000001
  6691. #define USB_INEPMSK5_S 5
  6692. /** USB_INEPMSK6 : R/W; bitpos: [6]; default: 0;
  6693. * IN Endpoint 6 Interrupt mask Bit.
  6694. */
  6695. #define USB_INEPMSK6 (BIT(6))
  6696. #define USB_INEPMSK6_M (USB_INEPMSK6_V << USB_INEPMSK6_S)
  6697. #define USB_INEPMSK6_V 0x00000001
  6698. #define USB_INEPMSK6_S 6
  6699. /** USB_OUTEPMSK0 : R/W; bitpos: [16]; default: 0;
  6700. * OUT Endpoint 0 Interrupt mask Bit.
  6701. */
  6702. #define USB_OUTEPMSK0 (BIT(16))
  6703. #define USB_OUTEPMSK0_M (USB_OUTEPMSK0_V << USB_OUTEPMSK0_S)
  6704. #define USB_OUTEPMSK0_V 0x00000001
  6705. #define USB_OUTEPMSK0_S 16
  6706. /** USB_OUTEPMSK1 : R/W; bitpos: [17]; default: 0;
  6707. * OUT Endpoint 1 Interrupt mask Bit.
  6708. */
  6709. #define USB_OUTEPMSK1 (BIT(17))
  6710. #define USB_OUTEPMSK1_M (USB_OUTEPMSK1_V << USB_OUTEPMSK1_S)
  6711. #define USB_OUTEPMSK1_V 0x00000001
  6712. #define USB_OUTEPMSK1_S 17
  6713. /** USB_OUTEPMSK2 : R/W; bitpos: [18]; default: 0;
  6714. * OUT Endpoint 2 Interrupt mask Bit.
  6715. */
  6716. #define USB_OUTEPMSK2 (BIT(18))
  6717. #define USB_OUTEPMSK2_M (USB_OUTEPMSK2_V << USB_OUTEPMSK2_S)
  6718. #define USB_OUTEPMSK2_V 0x00000001
  6719. #define USB_OUTEPMSK2_S 18
  6720. /** USB_OUTEPMSK3 : R/W; bitpos: [19]; default: 0;
  6721. * OUT Endpoint 3 Interrupt mask Bit.
  6722. */
  6723. #define USB_OUTEPMSK3 (BIT(19))
  6724. #define USB_OUTEPMSK3_M (USB_OUTEPMSK3_V << USB_OUTEPMSK3_S)
  6725. #define USB_OUTEPMSK3_V 0x00000001
  6726. #define USB_OUTEPMSK3_S 19
  6727. /** USB_OUTEPMSK4 : R/W; bitpos: [20]; default: 0;
  6728. * OUT Endpoint 4 Interrupt mask Bit.
  6729. */
  6730. #define USB_OUTEPMSK4 (BIT(20))
  6731. #define USB_OUTEPMSK4_M (USB_OUTEPMSK4_V << USB_OUTEPMSK4_S)
  6732. #define USB_OUTEPMSK4_V 0x00000001
  6733. #define USB_OUTEPMSK4_S 20
  6734. /** USB_OUTEPMSK5 : R/W; bitpos: [21]; default: 0;
  6735. * OUT Endpoint 5 Interrupt mask Bit.
  6736. */
  6737. #define USB_OUTEPMSK5 (BIT(21))
  6738. #define USB_OUTEPMSK5_M (USB_OUTEPMSK5_V << USB_OUTEPMSK5_S)
  6739. #define USB_OUTEPMSK5_V 0x00000001
  6740. #define USB_OUTEPMSK5_S 21
  6741. /** USB_OUTEPMSK6 : R/W; bitpos: [22]; default: 0;
  6742. * OUT Endpoint 6 Interrupt mask Bit.
  6743. */
  6744. #define USB_OUTEPMSK6 (BIT(22))
  6745. #define USB_OUTEPMSK6_M (USB_OUTEPMSK6_V << USB_OUTEPMSK6_S)
  6746. #define USB_OUTEPMSK6_V 0x00000001
  6747. #define USB_OUTEPMSK6_S 22
  6748. /** USB_DIEPEMPMSK_REG register
  6749. * Device IN Endpoint FIFO Empty Interrupt Mask Register
  6750. */
  6751. #define USB_DIEPEMPMSK_REG (SOC_DPORT_USB_BASE + 0x834)
  6752. /** USB_D_INEPTXFEMPMSK : R/W; bitpos: [16:0]; default: 0;
  6753. * IN EP Tx FIFO Empty Interrupt Mask Bits
  6754. * 0x1 (EP0_MASK): Mask IN EP0 Tx FIFO Empty Interrupt
  6755. * 0x2 (EP1_MASK): Mask IN EP1 Tx FIFO Empty Interrupt
  6756. * 0x4 (EP2_MASK): Mask IN EP2 Tx FIFO Empty Interrupt
  6757. * 0x8 (EP3_MASK): Mask IN EP3 Tx FIFO Empty Interrupt
  6758. * 0x10 (EP4_MASK): Mask IN EP4 Tx FIFO Empty Interrupt
  6759. * 0x20 (EP5_MASK): Mask IN EP5 Tx FIFO Empty Interrupt
  6760. * 0x40 (EP6_MASK): Mask IN EP6 Tx FIFO Empty Interrupt
  6761. * 0x80 (EP7_MASK): Mask IN EP7 Tx FIFO Empty Interrupt
  6762. * 0x100 (EP8_MASK): Mask IN EP8 Tx FIFO Empty Interrupt
  6763. * 0x200 (EP9_MASK): Mask IN EP9 Tx FIFO Empty Interrupt
  6764. * 0x400 (EP10_MASK): Mask IN EP10 Tx FIFO Empty Interrupt
  6765. * 0x800 (EP11_MASK): Mask IN EP11 Tx FIFO Empty Interrupt
  6766. * 0x1000 (EP12_MASK): Mask IN EP12 Tx FIFO Empty Interrupt
  6767. * 0x2000 (EP13_MASK): Mask IN EP13 Tx FIFO Empty Interrupt
  6768. * 0x4000 (EP14_MASK): Mask IN EP14 Tx FIFO Empty Interrupt
  6769. * 0x8000 (EP15_MASK): Mask IN EP15 Tx FIFO Empty Interrupt
  6770. */
  6771. #define USB_D_INEPTXFEMPMSK 0x0000FFFF
  6772. #define USB_D_INEPTXFEMPMSK_M (USB_D_INEPTXFEMPMSK_V << USB_D_INEPTXFEMPMSK_S)
  6773. #define USB_D_INEPTXFEMPMSK_V 0x0000FFFF
  6774. #define USB_D_INEPTXFEMPMSK_S 0
  6775. /** USB_DIEPINT0_REG register
  6776. * Device IN Endpoint 0 Interrupt Register
  6777. */
  6778. #define USB_DIEPINT0_REG (SOC_DPORT_USB_BASE + 0x908)
  6779. /** USB_D_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0;
  6780. * 0x0 : No Transfer Complete Interrupt
  6781. * 0x1 : Transfer Completed Interrupt
  6782. */
  6783. #define USB_D_XFERCOMPL0 (BIT(0))
  6784. #define USB_D_XFERCOMPL0_M (USB_D_XFERCOMPL0_V << USB_D_XFERCOMPL0_S)
  6785. #define USB_D_XFERCOMPL0_V 0x00000001
  6786. #define USB_D_XFERCOMPL0_S 0
  6787. /** USB_D_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0;
  6788. * 0x0 : No Endpoint Disabled Interrupt
  6789. * 0x1 : Endpoint Disabled Interrupt
  6790. */
  6791. #define USB_D_EPDISBLD0 (BIT(1))
  6792. #define USB_D_EPDISBLD0_M (USB_D_EPDISBLD0_V << USB_D_EPDISBLD0_S)
  6793. #define USB_D_EPDISBLD0_V 0x00000001
  6794. #define USB_D_EPDISBLD0_S 1
  6795. /** USB_D_AHBERR0 : R/W1C; bitpos: [2]; default: 0;
  6796. * 0x0 : No AHB Error Interrupt
  6797. * 0x1 : AHB Error interrupt
  6798. */
  6799. #define USB_D_AHBERR0 (BIT(2))
  6800. #define USB_D_AHBERR0_M (USB_D_AHBERR0_V << USB_D_AHBERR0_S)
  6801. #define USB_D_AHBERR0_V 0x00000001
  6802. #define USB_D_AHBERR0_S 2
  6803. /** USB_D_TIMEOUT0 : R/W1C; bitpos: [3]; default: 0;
  6804. * 0x0 : No Timeout interrupt
  6805. * 0x1 : Timeout interrupt
  6806. */
  6807. #define USB_D_TIMEOUT0 (BIT(3))
  6808. #define USB_D_TIMEOUT0_M (USB_D_TIMEOUT0_V << USB_D_TIMEOUT0_S)
  6809. #define USB_D_TIMEOUT0_V 0x00000001
  6810. #define USB_D_TIMEOUT0_S 3
  6811. /** USB_D_INTKNTXFEMP0 : R/W1C; bitpos: [4]; default: 0;
  6812. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  6813. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  6814. */
  6815. #define USB_D_INTKNTXFEMP0 (BIT(4))
  6816. #define USB_D_INTKNTXFEMP0_M (USB_D_INTKNTXFEMP0_V << USB_D_INTKNTXFEMP0_S)
  6817. #define USB_D_INTKNTXFEMP0_V 0x00000001
  6818. #define USB_D_INTKNTXFEMP0_S 4
  6819. /** USB_D_INTKNEPMIS0 : R/W1C; bitpos: [5]; default: 0;
  6820. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  6821. * 0x1 : IN Token Received with EP Mismatch interrupt
  6822. */
  6823. #define USB_D_INTKNEPMIS0 (BIT(5))
  6824. #define USB_D_INTKNEPMIS0_M (USB_D_INTKNEPMIS0_V << USB_D_INTKNEPMIS0_S)
  6825. #define USB_D_INTKNEPMIS0_V 0x00000001
  6826. #define USB_D_INTKNEPMIS0_S 5
  6827. /** USB_D_INEPNAKEFF0 : R/W1C; bitpos: [6]; default: 0;
  6828. * IN Endpoint NAK Effective
  6829. * 0x0 : No IN Endpoint NAK Effective interrupt
  6830. * 0x1 : IN Endpoint NAK Effective interrupt
  6831. */
  6832. #define USB_D_INEPNAKEFF0 (BIT(6))
  6833. #define USB_D_INEPNAKEFF0_M (USB_D_INEPNAKEFF0_V << USB_D_INEPNAKEFF0_S)
  6834. #define USB_D_INEPNAKEFF0_V 0x00000001
  6835. #define USB_D_INEPNAKEFF0_S 6
  6836. /** USB_D_TXFEMP0 : RO; bitpos: [7]; default: 0;
  6837. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  6838. * completely empty
  6839. * 0x0 : No Transmit FIFO Empty interrupt
  6840. * 0x1 : Transmit FIFO Empty interrupt
  6841. */
  6842. #define USB_D_TXFEMP0 (BIT(7))
  6843. #define USB_D_TXFEMP0_M (USB_D_TXFEMP0_V << USB_D_TXFEMP0_S)
  6844. #define USB_D_TXFEMP0_V 0x00000001
  6845. #define USB_D_TXFEMP0_S 7
  6846. /** USB_D_TXFIFOUNDRN0 : R/W1C; bitpos: [8]; default: 0;
  6847. * The core generates this interrupt when it detects a transmit FIFO underrun
  6848. * condition in threshold mode for this endpoint
  6849. * 0x0 : No Fifo Underrun interrupt
  6850. * 0x1 : Fifo Underrun interrupt
  6851. */
  6852. #define USB_D_TXFIFOUNDRN0 (BIT(8))
  6853. #define USB_D_TXFIFOUNDRN0_M (USB_D_TXFIFOUNDRN0_V << USB_D_TXFIFOUNDRN0_S)
  6854. #define USB_D_TXFIFOUNDRN0_V 0x00000001
  6855. #define USB_D_TXFIFOUNDRN0_S 8
  6856. /** USB_D_BNAINTR0 : R/W1C; bitpos: [9]; default: 0;
  6857. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  6858. * this interrupt when the descriptor accessed is not ready for the Core to process,
  6859. * such as Host busy or DMA done
  6860. * 0x0 : No BNA interrupt
  6861. * 0x1 : BNA interrupt
  6862. */
  6863. #define USB_D_BNAINTR0 (BIT(9))
  6864. #define USB_D_BNAINTR0_M (USB_D_BNAINTR0_V << USB_D_BNAINTR0_S)
  6865. #define USB_D_BNAINTR0_V 0x00000001
  6866. #define USB_D_BNAINTR0_S 9
  6867. /** USB_D_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0;
  6868. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  6869. * has been dropped. This bit does not have an associated mask bit and does not
  6870. * generate an interrupt
  6871. * 0x0 : No interrupt
  6872. * 0x1 : Packet Drop Status
  6873. */
  6874. #define USB_D_PKTDRPSTS0 (BIT(11))
  6875. #define USB_D_PKTDRPSTS0_M (USB_D_PKTDRPSTS0_V << USB_D_PKTDRPSTS0_S)
  6876. #define USB_D_PKTDRPSTS0_V 0x00000001
  6877. #define USB_D_PKTDRPSTS0_S 11
  6878. /** USB_D_BBLEERR0 : R/W1C; bitpos: [12]; default: 0;
  6879. * The core generates this interrupt when babble is received for the endpoint
  6880. * 0x0 : No interrupt
  6881. * 0x1 : BbleErr interrupt
  6882. */
  6883. #define USB_D_BBLEERR0 (BIT(12))
  6884. #define USB_D_BBLEERR0_M (USB_D_BBLEERR0_V << USB_D_BBLEERR0_S)
  6885. #define USB_D_BBLEERR0_V 0x00000001
  6886. #define USB_D_BBLEERR0_S 12
  6887. /** USB_D_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0;
  6888. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  6889. * received by the device
  6890. * 0x0 : No interrupt
  6891. * 0x1 : NAK Interrupt
  6892. */
  6893. #define USB_D_NAKINTRPT0 (BIT(13))
  6894. #define USB_D_NAKINTRPT0_M (USB_D_NAKINTRPT0_V << USB_D_NAKINTRPT0_S)
  6895. #define USB_D_NAKINTRPT0_V 0x00000001
  6896. #define USB_D_NAKINTRPT0_S 13
  6897. /** USB_D_NYETINTRPT0 : R/W1C; bitpos: [14]; default: 0;
  6898. * NYET Interrupt. The core generates this interrupt when a NYET response is
  6899. * transmitted for a non isochronous OUT endpoint
  6900. * 0x0 : No interrupt
  6901. * 0x1 : NYET Interrupt
  6902. */
  6903. #define USB_D_NYETINTRPT0 (BIT(14))
  6904. #define USB_D_NYETINTRPT0_M (USB_D_NYETINTRPT0_V << USB_D_NYETINTRPT0_S)
  6905. #define USB_D_NYETINTRPT0_V 0x00000001
  6906. #define USB_D_NYETINTRPT0_S 14
  6907. /** USB_DIEPINT1_REG register
  6908. * Device IN Endpoint 1 Interrupt Register
  6909. */
  6910. #define USB_DIEPINT1_REG (SOC_DPORT_USB_BASE + 0x928)
  6911. /** USB_D_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0;
  6912. * 0x0 : No Transfer Complete Interrupt
  6913. * 0x1 : Transfer Completed Interrupt
  6914. */
  6915. #define USB_D_XFERCOMPL1 (BIT(0))
  6916. #define USB_D_XFERCOMPL1_M (USB_D_XFERCOMPL1_V << USB_D_XFERCOMPL1_S)
  6917. #define USB_D_XFERCOMPL1_V 0x00000001
  6918. #define USB_D_XFERCOMPL1_S 0
  6919. /** USB_D_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0;
  6920. * 0x0 : No Endpoint Disabled Interrupt
  6921. * 0x1 : Endpoint Disabled Interrupt
  6922. */
  6923. #define USB_D_EPDISBLD1 (BIT(1))
  6924. #define USB_D_EPDISBLD1_M (USB_D_EPDISBLD1_V << USB_D_EPDISBLD1_S)
  6925. #define USB_D_EPDISBLD1_V 0x00000001
  6926. #define USB_D_EPDISBLD1_S 1
  6927. /** USB_D_AHBERR1 : R/W1C; bitpos: [2]; default: 0;
  6928. * 0x0 : No AHB Error Interrupt
  6929. * 0x1 : AHB Error interrupt
  6930. */
  6931. #define USB_D_AHBERR1 (BIT(2))
  6932. #define USB_D_AHBERR1_M (USB_D_AHBERR1_V << USB_D_AHBERR1_S)
  6933. #define USB_D_AHBERR1_V 0x00000001
  6934. #define USB_D_AHBERR1_S 2
  6935. /** USB_D_TIMEOUT1 : R/W1C; bitpos: [3]; default: 0;
  6936. * 0x0 : No Timeout interrupt
  6937. * 0x1 : Timeout interrupt
  6938. */
  6939. #define USB_D_TIMEOUT1 (BIT(3))
  6940. #define USB_D_TIMEOUT1_M (USB_D_TIMEOUT1_V << USB_D_TIMEOUT1_S)
  6941. #define USB_D_TIMEOUT1_V 0x00000001
  6942. #define USB_D_TIMEOUT1_S 3
  6943. /** USB_D_INTKNTXFEMP1 : R/W1C; bitpos: [4]; default: 0;
  6944. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  6945. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  6946. */
  6947. #define USB_D_INTKNTXFEMP1 (BIT(4))
  6948. #define USB_D_INTKNTXFEMP1_M (USB_D_INTKNTXFEMP1_V << USB_D_INTKNTXFEMP1_S)
  6949. #define USB_D_INTKNTXFEMP1_V 0x00000001
  6950. #define USB_D_INTKNTXFEMP1_S 4
  6951. /** USB_D_INTKNEPMIS1 : R/W1C; bitpos: [5]; default: 0;
  6952. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  6953. * 0x1 : IN Token Received with EP Mismatch interrupt
  6954. */
  6955. #define USB_D_INTKNEPMIS1 (BIT(5))
  6956. #define USB_D_INTKNEPMIS1_M (USB_D_INTKNEPMIS1_V << USB_D_INTKNEPMIS1_S)
  6957. #define USB_D_INTKNEPMIS1_V 0x00000001
  6958. #define USB_D_INTKNEPMIS1_S 5
  6959. /** USB_D_INEPNAKEFF1 : R/W1C; bitpos: [6]; default: 0;
  6960. * IN Endpoint NAK Effective
  6961. * 0x0 : No IN Endpoint NAK Effective interrupt
  6962. * 0x1 : IN Endpoint NAK Effective interrupt
  6963. */
  6964. #define USB_D_INEPNAKEFF1 (BIT(6))
  6965. #define USB_D_INEPNAKEFF1_M (USB_D_INEPNAKEFF1_V << USB_D_INEPNAKEFF1_S)
  6966. #define USB_D_INEPNAKEFF1_V 0x00000001
  6967. #define USB_D_INEPNAKEFF1_S 6
  6968. /** USB_D_TXFEMP1 : RO; bitpos: [7]; default: 0;
  6969. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  6970. * completely empty
  6971. * 0x0 : No Transmit FIFO Empty interrupt
  6972. * 0x1 : Transmit FIFO Empty interrupt
  6973. */
  6974. #define USB_D_TXFEMP1 (BIT(7))
  6975. #define USB_D_TXFEMP1_M (USB_D_TXFEMP1_V << USB_D_TXFEMP1_S)
  6976. #define USB_D_TXFEMP1_V 0x00000001
  6977. #define USB_D_TXFEMP1_S 7
  6978. /** USB_D_TXFIFOUNDRN1 : R/W1C; bitpos: [8]; default: 0;
  6979. * The core generates this interrupt when it detects a transmit FIFO underrun
  6980. * condition in threshold mode for this endpoint
  6981. * 0x0 : No Fifo Underrun interrupt
  6982. * 0x1 : Fifo Underrun interrupt
  6983. */
  6984. #define USB_D_TXFIFOUNDRN1 (BIT(8))
  6985. #define USB_D_TXFIFOUNDRN1_M (USB_D_TXFIFOUNDRN1_V << USB_D_TXFIFOUNDRN1_S)
  6986. #define USB_D_TXFIFOUNDRN1_V 0x00000001
  6987. #define USB_D_TXFIFOUNDRN1_S 8
  6988. /** USB_D_BNAINTR1 : R/W1C; bitpos: [9]; default: 0;
  6989. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  6990. * this interrupt when the descriptor accessed is not ready for the Core to process,
  6991. * such as Host busy or DMA done
  6992. * 0x0 : No BNA interrupt
  6993. * 0x1 : BNA interrupt
  6994. */
  6995. #define USB_D_BNAINTR1 (BIT(9))
  6996. #define USB_D_BNAINTR1_M (USB_D_BNAINTR1_V << USB_D_BNAINTR1_S)
  6997. #define USB_D_BNAINTR1_V 0x00000001
  6998. #define USB_D_BNAINTR1_S 9
  6999. /** USB_D_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0;
  7000. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7001. * has been dropped. This bit does not have an associated mask bit and does not
  7002. * generate an interrupt
  7003. * 0x0 : No interrupt
  7004. * 0x1 : Packet Drop Status
  7005. */
  7006. #define USB_D_PKTDRPSTS1 (BIT(11))
  7007. #define USB_D_PKTDRPSTS1_M (USB_D_PKTDRPSTS1_V << USB_D_PKTDRPSTS1_S)
  7008. #define USB_D_PKTDRPSTS1_V 0x00000001
  7009. #define USB_D_PKTDRPSTS1_S 11
  7010. /** USB_D_BBLEERR1 : R/W1C; bitpos: [12]; default: 0;
  7011. * The core generates this interrupt when babble is received for the endpoint
  7012. * 0x0 : No interrupt
  7013. * 0x1 : BbleErr interrupt
  7014. */
  7015. #define USB_D_BBLEERR1 (BIT(12))
  7016. #define USB_D_BBLEERR1_M (USB_D_BBLEERR1_V << USB_D_BBLEERR1_S)
  7017. #define USB_D_BBLEERR1_V 0x00000001
  7018. #define USB_D_BBLEERR1_S 12
  7019. /** USB_D_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0;
  7020. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7021. * received by the device
  7022. * 0x0 : No interrupt
  7023. * 0x1 : NAK Interrupt
  7024. */
  7025. #define USB_D_NAKINTRPT1 (BIT(13))
  7026. #define USB_D_NAKINTRPT1_M (USB_D_NAKINTRPT1_V << USB_D_NAKINTRPT1_S)
  7027. #define USB_D_NAKINTRPT1_V 0x00000001
  7028. #define USB_D_NAKINTRPT1_S 13
  7029. /** USB_D_NYETINTRPT1 : R/W1C; bitpos: [14]; default: 0;
  7030. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7031. * transmitted for a non isochronous OUT endpoint
  7032. * 0x0 : No interrupt
  7033. * 0x1 : NYET Interrupt
  7034. */
  7035. #define USB_D_NYETINTRPT1 (BIT(14))
  7036. #define USB_D_NYETINTRPT1_M (USB_D_NYETINTRPT1_V << USB_D_NYETINTRPT1_S)
  7037. #define USB_D_NYETINTRPT1_V 0x00000001
  7038. #define USB_D_NYETINTRPT1_S 14
  7039. /** USB_DIEPINT2_REG register
  7040. * Device IN Endpoint 2 Interrupt Register
  7041. */
  7042. #define USB_DIEPINT2_REG (SOC_DPORT_USB_BASE + 0x948)
  7043. /** USB_D_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0;
  7044. * 0x0 : No Transfer Complete Interrupt
  7045. * 0x1 : Transfer Completed Interrupt
  7046. */
  7047. #define USB_D_XFERCOMPL2 (BIT(0))
  7048. #define USB_D_XFERCOMPL2_M (USB_D_XFERCOMPL2_V << USB_D_XFERCOMPL2_S)
  7049. #define USB_D_XFERCOMPL2_V 0x00000001
  7050. #define USB_D_XFERCOMPL2_S 0
  7051. /** USB_D_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0;
  7052. * 0x0 : No Endpoint Disabled Interrupt
  7053. * 0x1 : Endpoint Disabled Interrupt
  7054. */
  7055. #define USB_D_EPDISBLD2 (BIT(1))
  7056. #define USB_D_EPDISBLD2_M (USB_D_EPDISBLD2_V << USB_D_EPDISBLD2_S)
  7057. #define USB_D_EPDISBLD2_V 0x00000001
  7058. #define USB_D_EPDISBLD2_S 1
  7059. /** USB_D_AHBERR2 : R/W1C; bitpos: [2]; default: 0;
  7060. * 0x0 : No AHB Error Interrupt
  7061. * 0x1 : AHB Error interrupt
  7062. */
  7063. #define USB_D_AHBERR2 (BIT(2))
  7064. #define USB_D_AHBERR2_M (USB_D_AHBERR2_V << USB_D_AHBERR2_S)
  7065. #define USB_D_AHBERR2_V 0x00000001
  7066. #define USB_D_AHBERR2_S 2
  7067. /** USB_D_TIMEOUT2 : R/W1C; bitpos: [3]; default: 0;
  7068. * 0x0 : No Timeout interrupt
  7069. * 0x1 : Timeout interrupt
  7070. */
  7071. #define USB_D_TIMEOUT2 (BIT(3))
  7072. #define USB_D_TIMEOUT2_M (USB_D_TIMEOUT2_V << USB_D_TIMEOUT2_S)
  7073. #define USB_D_TIMEOUT2_V 0x00000001
  7074. #define USB_D_TIMEOUT2_S 3
  7075. /** USB_D_INTKNTXFEMP2 : R/W1C; bitpos: [4]; default: 0;
  7076. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  7077. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  7078. */
  7079. #define USB_D_INTKNTXFEMP2 (BIT(4))
  7080. #define USB_D_INTKNTXFEMP2_M (USB_D_INTKNTXFEMP2_V << USB_D_INTKNTXFEMP2_S)
  7081. #define USB_D_INTKNTXFEMP2_V 0x00000001
  7082. #define USB_D_INTKNTXFEMP2_S 4
  7083. /** USB_D_INTKNEPMIS2 : R/W1C; bitpos: [5]; default: 0;
  7084. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  7085. * 0x1 : IN Token Received with EP Mismatch interrupt
  7086. */
  7087. #define USB_D_INTKNEPMIS2 (BIT(5))
  7088. #define USB_D_INTKNEPMIS2_M (USB_D_INTKNEPMIS2_V << USB_D_INTKNEPMIS2_S)
  7089. #define USB_D_INTKNEPMIS2_V 0x00000001
  7090. #define USB_D_INTKNEPMIS2_S 5
  7091. /** USB_D_INEPNAKEFF2 : R/W1C; bitpos: [6]; default: 0;
  7092. * IN Endpoint NAK Effective
  7093. * 0x0 : No IN Endpoint NAK Effective interrupt
  7094. * 0x1 : IN Endpoint NAK Effective interrupt
  7095. */
  7096. #define USB_D_INEPNAKEFF2 (BIT(6))
  7097. #define USB_D_INEPNAKEFF2_M (USB_D_INEPNAKEFF2_V << USB_D_INEPNAKEFF2_S)
  7098. #define USB_D_INEPNAKEFF2_V 0x00000001
  7099. #define USB_D_INEPNAKEFF2_S 6
  7100. /** USB_D_TXFEMP2 : RO; bitpos: [7]; default: 0;
  7101. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  7102. * completely empty
  7103. * 0x0 : No Transmit FIFO Empty interrupt
  7104. * 0x1 : Transmit FIFO Empty interrupt
  7105. */
  7106. #define USB_D_TXFEMP2 (BIT(7))
  7107. #define USB_D_TXFEMP2_M (USB_D_TXFEMP2_V << USB_D_TXFEMP2_S)
  7108. #define USB_D_TXFEMP2_V 0x00000001
  7109. #define USB_D_TXFEMP2_S 7
  7110. /** USB_D_TXFIFOUNDRN2 : R/W1C; bitpos: [8]; default: 0;
  7111. * The core generates this interrupt when it detects a transmit FIFO underrun
  7112. * condition in threshold mode for this endpoint
  7113. * 0x0 : No Fifo Underrun interrupt
  7114. * 0x1 : Fifo Underrun interrupt
  7115. */
  7116. #define USB_D_TXFIFOUNDRN2 (BIT(8))
  7117. #define USB_D_TXFIFOUNDRN2_M (USB_D_TXFIFOUNDRN2_V << USB_D_TXFIFOUNDRN2_S)
  7118. #define USB_D_TXFIFOUNDRN2_V 0x00000001
  7119. #define USB_D_TXFIFOUNDRN2_S 8
  7120. /** USB_D_BNAINTR2 : R/W1C; bitpos: [9]; default: 0;
  7121. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  7122. * this interrupt when the descriptor accessed is not ready for the Core to process,
  7123. * such as Host busy or DMA done
  7124. * 0x0 : No BNA interrupt
  7125. * 0x1 : BNA interrupt
  7126. */
  7127. #define USB_D_BNAINTR2 (BIT(9))
  7128. #define USB_D_BNAINTR2_M (USB_D_BNAINTR2_V << USB_D_BNAINTR2_S)
  7129. #define USB_D_BNAINTR2_V 0x00000001
  7130. #define USB_D_BNAINTR2_S 9
  7131. /** USB_D_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0;
  7132. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7133. * has been dropped. This bit does not have an associated mask bit and does not
  7134. * generate an interrupt
  7135. * 0x0 : No interrupt
  7136. * 0x1 : Packet Drop Status
  7137. */
  7138. #define USB_D_PKTDRPSTS2 (BIT(11))
  7139. #define USB_D_PKTDRPSTS2_M (USB_D_PKTDRPSTS2_V << USB_D_PKTDRPSTS2_S)
  7140. #define USB_D_PKTDRPSTS2_V 0x00000001
  7141. #define USB_D_PKTDRPSTS2_S 11
  7142. /** USB_D_BBLEERR2 : R/W1C; bitpos: [12]; default: 0;
  7143. * The core generates this interrupt when babble is received for the endpoint
  7144. * 0x0 : No interrupt
  7145. * 0x1 : BbleErr interrupt
  7146. */
  7147. #define USB_D_BBLEERR2 (BIT(12))
  7148. #define USB_D_BBLEERR2_M (USB_D_BBLEERR2_V << USB_D_BBLEERR2_S)
  7149. #define USB_D_BBLEERR2_V 0x00000001
  7150. #define USB_D_BBLEERR2_S 12
  7151. /** USB_D_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0;
  7152. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7153. * received by the device
  7154. * 0x0 : No interrupt
  7155. * 0x1 : NAK Interrupt
  7156. */
  7157. #define USB_D_NAKINTRPT2 (BIT(13))
  7158. #define USB_D_NAKINTRPT2_M (USB_D_NAKINTRPT2_V << USB_D_NAKINTRPT2_S)
  7159. #define USB_D_NAKINTRPT2_V 0x00000001
  7160. #define USB_D_NAKINTRPT2_S 13
  7161. /** USB_D_NYETINTRPT2 : R/W1C; bitpos: [14]; default: 0;
  7162. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7163. * transmitted for a non isochronous OUT endpoint
  7164. * 0x0 : No interrupt
  7165. * 0x1 : NYET Interrupt
  7166. */
  7167. #define USB_D_NYETINTRPT2 (BIT(14))
  7168. #define USB_D_NYETINTRPT2_M (USB_D_NYETINTRPT2_V << USB_D_NYETINTRPT2_S)
  7169. #define USB_D_NYETINTRPT2_V 0x00000001
  7170. #define USB_D_NYETINTRPT2_S 14
  7171. /** USB_DIEPINT3_REG register
  7172. * Device IN Endpoint 3 Interrupt Register
  7173. */
  7174. #define USB_DIEPINT3_REG (SOC_DPORT_USB_BASE + 0x968)
  7175. /** USB_D_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0;
  7176. * 0x0 : No Transfer Complete Interrupt
  7177. * 0x1 : Transfer Completed Interrupt
  7178. */
  7179. #define USB_D_XFERCOMPL3 (BIT(0))
  7180. #define USB_D_XFERCOMPL3_M (USB_D_XFERCOMPL3_V << USB_D_XFERCOMPL3_S)
  7181. #define USB_D_XFERCOMPL3_V 0x00000001
  7182. #define USB_D_XFERCOMPL3_S 0
  7183. /** USB_D_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0;
  7184. * 0x0 : No Endpoint Disabled Interrupt
  7185. * 0x1 : Endpoint Disabled Interrupt
  7186. */
  7187. #define USB_D_EPDISBLD3 (BIT(1))
  7188. #define USB_D_EPDISBLD3_M (USB_D_EPDISBLD3_V << USB_D_EPDISBLD3_S)
  7189. #define USB_D_EPDISBLD3_V 0x00000001
  7190. #define USB_D_EPDISBLD3_S 1
  7191. /** USB_D_AHBERR3 : R/W1C; bitpos: [2]; default: 0;
  7192. * 0x0 : No AHB Error Interrupt
  7193. * 0x1 : AHB Error interrupt
  7194. */
  7195. #define USB_D_AHBERR3 (BIT(2))
  7196. #define USB_D_AHBERR3_M (USB_D_AHBERR3_V << USB_D_AHBERR3_S)
  7197. #define USB_D_AHBERR3_V 0x00000001
  7198. #define USB_D_AHBERR3_S 2
  7199. /** USB_D_TIMEOUT3 : R/W1C; bitpos: [3]; default: 0;
  7200. * 0x0 : No Timeout interrupt
  7201. * 0x1 : Timeout interrupt
  7202. */
  7203. #define USB_D_TIMEOUT3 (BIT(3))
  7204. #define USB_D_TIMEOUT3_M (USB_D_TIMEOUT3_V << USB_D_TIMEOUT3_S)
  7205. #define USB_D_TIMEOUT3_V 0x00000001
  7206. #define USB_D_TIMEOUT3_S 3
  7207. /** USB_D_INTKNTXFEMP3 : R/W1C; bitpos: [4]; default: 0;
  7208. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  7209. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  7210. */
  7211. #define USB_D_INTKNTXFEMP3 (BIT(4))
  7212. #define USB_D_INTKNTXFEMP3_M (USB_D_INTKNTXFEMP3_V << USB_D_INTKNTXFEMP3_S)
  7213. #define USB_D_INTKNTXFEMP3_V 0x00000001
  7214. #define USB_D_INTKNTXFEMP3_S 4
  7215. /** USB_D_INTKNEPMIS3 : R/W1C; bitpos: [5]; default: 0;
  7216. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  7217. * 0x1 : IN Token Received with EP Mismatch interrupt
  7218. */
  7219. #define USB_D_INTKNEPMIS3 (BIT(5))
  7220. #define USB_D_INTKNEPMIS3_M (USB_D_INTKNEPMIS3_V << USB_D_INTKNEPMIS3_S)
  7221. #define USB_D_INTKNEPMIS3_V 0x00000001
  7222. #define USB_D_INTKNEPMIS3_S 5
  7223. /** USB_D_INEPNAKEFF3 : R/W1C; bitpos: [6]; default: 0;
  7224. * IN Endpoint NAK Effective
  7225. * 0x0 : No IN Endpoint NAK Effective interrupt
  7226. * 0x1 : IN Endpoint NAK Effective interrupt
  7227. */
  7228. #define USB_D_INEPNAKEFF3 (BIT(6))
  7229. #define USB_D_INEPNAKEFF3_M (USB_D_INEPNAKEFF3_V << USB_D_INEPNAKEFF3_S)
  7230. #define USB_D_INEPNAKEFF3_V 0x00000001
  7231. #define USB_D_INEPNAKEFF3_S 6
  7232. /** USB_D_TXFEMP3 : RO; bitpos: [7]; default: 0;
  7233. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  7234. * completely empty
  7235. * 0x0 : No Transmit FIFO Empty interrupt
  7236. * 0x1 : Transmit FIFO Empty interrupt
  7237. */
  7238. #define USB_D_TXFEMP3 (BIT(7))
  7239. #define USB_D_TXFEMP3_M (USB_D_TXFEMP3_V << USB_D_TXFEMP3_S)
  7240. #define USB_D_TXFEMP3_V 0x00000001
  7241. #define USB_D_TXFEMP3_S 7
  7242. /** USB_D_TXFIFOUNDRN3 : R/W1C; bitpos: [8]; default: 0;
  7243. * The core generates this interrupt when it detects a transmit FIFO underrun
  7244. * condition in threshold mode for this endpoint
  7245. * 0x0 : No Fifo Underrun interrupt
  7246. * 0x1 : Fifo Underrun interrupt
  7247. */
  7248. #define USB_D_TXFIFOUNDRN3 (BIT(8))
  7249. #define USB_D_TXFIFOUNDRN3_M (USB_D_TXFIFOUNDRN3_V << USB_D_TXFIFOUNDRN3_S)
  7250. #define USB_D_TXFIFOUNDRN3_V 0x00000001
  7251. #define USB_D_TXFIFOUNDRN3_S 8
  7252. /** USB_D_BNAINTR3 : R/W1C; bitpos: [9]; default: 0;
  7253. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  7254. * this interrupt when the descriptor accessed is not ready for the Core to process,
  7255. * such as Host busy or DMA done
  7256. * 0x0 : No BNA interrupt
  7257. * 0x1 : BNA interrupt
  7258. */
  7259. #define USB_D_BNAINTR3 (BIT(9))
  7260. #define USB_D_BNAINTR3_M (USB_D_BNAINTR3_V << USB_D_BNAINTR3_S)
  7261. #define USB_D_BNAINTR3_V 0x00000001
  7262. #define USB_D_BNAINTR3_S 9
  7263. /** USB_D_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0;
  7264. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7265. * has been dropped. This bit does not have an associated mask bit and does not
  7266. * generate an interrupt
  7267. * 0x0 : No interrupt
  7268. * 0x1 : Packet Drop Status
  7269. */
  7270. #define USB_D_PKTDRPSTS3 (BIT(11))
  7271. #define USB_D_PKTDRPSTS3_M (USB_D_PKTDRPSTS3_V << USB_D_PKTDRPSTS3_S)
  7272. #define USB_D_PKTDRPSTS3_V 0x00000001
  7273. #define USB_D_PKTDRPSTS3_S 11
  7274. /** USB_D_BBLEERR3 : R/W1C; bitpos: [12]; default: 0;
  7275. * The core generates this interrupt when babble is received for the endpoint
  7276. * 0x0 : No interrupt
  7277. * 0x1 : BbleErr interrupt
  7278. */
  7279. #define USB_D_BBLEERR3 (BIT(12))
  7280. #define USB_D_BBLEERR3_M (USB_D_BBLEERR3_V << USB_D_BBLEERR3_S)
  7281. #define USB_D_BBLEERR3_V 0x00000001
  7282. #define USB_D_BBLEERR3_S 12
  7283. /** USB_D_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0;
  7284. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7285. * received by the device
  7286. * 0x0 : No interrupt
  7287. * 0x1 : NAK Interrupt
  7288. */
  7289. #define USB_D_NAKINTRPT3 (BIT(13))
  7290. #define USB_D_NAKINTRPT3_M (USB_D_NAKINTRPT3_V << USB_D_NAKINTRPT3_S)
  7291. #define USB_D_NAKINTRPT3_V 0x00000001
  7292. #define USB_D_NAKINTRPT3_S 13
  7293. /** USB_D_NYETINTRPT3 : R/W1C; bitpos: [14]; default: 0;
  7294. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7295. * transmitted for a non isochronous OUT endpoint
  7296. * 0x0 : No interrupt
  7297. * 0x1 : NYET Interrupt
  7298. */
  7299. #define USB_D_NYETINTRPT3 (BIT(14))
  7300. #define USB_D_NYETINTRPT3_M (USB_D_NYETINTRPT3_V << USB_D_NYETINTRPT3_S)
  7301. #define USB_D_NYETINTRPT3_V 0x00000001
  7302. #define USB_D_NYETINTRPT3_S 14
  7303. /** USB_DIEPINT4_REG register
  7304. * Device IN Endpoint 4 Interrupt Register
  7305. */
  7306. #define USB_DIEPINT4_REG (SOC_DPORT_USB_BASE + 0x988)
  7307. /** USB_D_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0;
  7308. * 0x0 : No Transfer Complete Interrupt
  7309. * 0x1 : Transfer Completed Interrupt
  7310. */
  7311. #define USB_D_XFERCOMPL4 (BIT(0))
  7312. #define USB_D_XFERCOMPL4_M (USB_D_XFERCOMPL4_V << USB_D_XFERCOMPL4_S)
  7313. #define USB_D_XFERCOMPL4_V 0x00000001
  7314. #define USB_D_XFERCOMPL4_S 0
  7315. /** USB_D_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0;
  7316. * 0x0 : No Endpoint Disabled Interrupt
  7317. * 0x1 : Endpoint Disabled Interrupt
  7318. */
  7319. #define USB_D_EPDISBLD4 (BIT(1))
  7320. #define USB_D_EPDISBLD4_M (USB_D_EPDISBLD4_V << USB_D_EPDISBLD4_S)
  7321. #define USB_D_EPDISBLD4_V 0x00000001
  7322. #define USB_D_EPDISBLD4_S 1
  7323. /** USB_D_AHBERR4 : R/W1C; bitpos: [2]; default: 0;
  7324. * 0x0 : No AHB Error Interrupt
  7325. * 0x1 : AHB Error interrupt
  7326. */
  7327. #define USB_D_AHBERR4 (BIT(2))
  7328. #define USB_D_AHBERR4_M (USB_D_AHBERR4_V << USB_D_AHBERR4_S)
  7329. #define USB_D_AHBERR4_V 0x00000001
  7330. #define USB_D_AHBERR4_S 2
  7331. /** USB_D_TIMEOUT4 : R/W1C; bitpos: [3]; default: 0;
  7332. * 0x0 : No Timeout interrupt
  7333. * 0x1 : Timeout interrupt
  7334. */
  7335. #define USB_D_TIMEOUT4 (BIT(3))
  7336. #define USB_D_TIMEOUT4_M (USB_D_TIMEOUT4_V << USB_D_TIMEOUT4_S)
  7337. #define USB_D_TIMEOUT4_V 0x00000001
  7338. #define USB_D_TIMEOUT4_S 3
  7339. /** USB_D_INTKNTXFEMP4 : R/W1C; bitpos: [4]; default: 0;
  7340. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  7341. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  7342. */
  7343. #define USB_D_INTKNTXFEMP4 (BIT(4))
  7344. #define USB_D_INTKNTXFEMP4_M (USB_D_INTKNTXFEMP4_V << USB_D_INTKNTXFEMP4_S)
  7345. #define USB_D_INTKNTXFEMP4_V 0x00000001
  7346. #define USB_D_INTKNTXFEMP4_S 4
  7347. /** USB_D_INTKNEPMIS4 : R/W1C; bitpos: [5]; default: 0;
  7348. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  7349. * 0x1 : IN Token Received with EP Mismatch interrupt
  7350. */
  7351. #define USB_D_INTKNEPMIS4 (BIT(5))
  7352. #define USB_D_INTKNEPMIS4_M (USB_D_INTKNEPMIS4_V << USB_D_INTKNEPMIS4_S)
  7353. #define USB_D_INTKNEPMIS4_V 0x00000001
  7354. #define USB_D_INTKNEPMIS4_S 5
  7355. /** USB_D_INEPNAKEFF4 : R/W1C; bitpos: [6]; default: 0;
  7356. * IN Endpoint NAK Effective
  7357. * 0x0 : No IN Endpoint NAK Effective interrupt
  7358. * 0x1 : IN Endpoint NAK Effective interrupt
  7359. */
  7360. #define USB_D_INEPNAKEFF4 (BIT(6))
  7361. #define USB_D_INEPNAKEFF4_M (USB_D_INEPNAKEFF4_V << USB_D_INEPNAKEFF4_S)
  7362. #define USB_D_INEPNAKEFF4_V 0x00000001
  7363. #define USB_D_INEPNAKEFF4_S 6
  7364. /** USB_D_TXFEMP4 : RO; bitpos: [7]; default: 0;
  7365. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  7366. * completely empty
  7367. * 0x0 : No Transmit FIFO Empty interrupt
  7368. * 0x1 : Transmit FIFO Empty interrupt
  7369. */
  7370. #define USB_D_TXFEMP4 (BIT(7))
  7371. #define USB_D_TXFEMP4_M (USB_D_TXFEMP4_V << USB_D_TXFEMP4_S)
  7372. #define USB_D_TXFEMP4_V 0x00000001
  7373. #define USB_D_TXFEMP4_S 7
  7374. /** USB_D_TXFIFOUNDRN4 : R/W1C; bitpos: [8]; default: 0;
  7375. * The core generates this interrupt when it detects a transmit FIFO underrun
  7376. * condition in threshold mode for this endpoint
  7377. * 0x0 : No Fifo Underrun interrupt
  7378. * 0x1 : Fifo Underrun interrupt
  7379. */
  7380. #define USB_D_TXFIFOUNDRN4 (BIT(8))
  7381. #define USB_D_TXFIFOUNDRN4_M (USB_D_TXFIFOUNDRN4_V << USB_D_TXFIFOUNDRN4_S)
  7382. #define USB_D_TXFIFOUNDRN4_V 0x00000001
  7383. #define USB_D_TXFIFOUNDRN4_S 8
  7384. /** USB_D_BNAINTR4 : R/W1C; bitpos: [9]; default: 0;
  7385. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  7386. * this interrupt when the descriptor accessed is not ready for the Core to process,
  7387. * such as Host busy or DMA done
  7388. * 0x0 : No BNA interrupt
  7389. * 0x1 : BNA interrupt
  7390. */
  7391. #define USB_D_BNAINTR4 (BIT(9))
  7392. #define USB_D_BNAINTR4_M (USB_D_BNAINTR4_V << USB_D_BNAINTR4_S)
  7393. #define USB_D_BNAINTR4_V 0x00000001
  7394. #define USB_D_BNAINTR4_S 9
  7395. /** USB_D_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0;
  7396. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7397. * has been dropped. This bit does not have an associated mask bit and does not
  7398. * generate an interrupt
  7399. * 0x0 : No interrupt
  7400. * 0x1 : Packet Drop Status
  7401. */
  7402. #define USB_D_PKTDRPSTS4 (BIT(11))
  7403. #define USB_D_PKTDRPSTS4_M (USB_D_PKTDRPSTS4_V << USB_D_PKTDRPSTS4_S)
  7404. #define USB_D_PKTDRPSTS4_V 0x00000001
  7405. #define USB_D_PKTDRPSTS4_S 11
  7406. /** USB_D_BBLEERR4 : R/W1C; bitpos: [12]; default: 0;
  7407. * The core generates this interrupt when babble is received for the endpoint
  7408. * 0x0 : No interrupt
  7409. * 0x1 : BbleErr interrupt
  7410. */
  7411. #define USB_D_BBLEERR4 (BIT(12))
  7412. #define USB_D_BBLEERR4_M (USB_D_BBLEERR4_V << USB_D_BBLEERR4_S)
  7413. #define USB_D_BBLEERR4_V 0x00000001
  7414. #define USB_D_BBLEERR4_S 12
  7415. /** USB_D_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0;
  7416. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7417. * received by the device
  7418. * 0x0 : No interrupt
  7419. * 0x1 : NAK Interrupt
  7420. */
  7421. #define USB_D_NAKINTRPT4 (BIT(13))
  7422. #define USB_D_NAKINTRPT4_M (USB_D_NAKINTRPT4_V << USB_D_NAKINTRPT4_S)
  7423. #define USB_D_NAKINTRPT4_V 0x00000001
  7424. #define USB_D_NAKINTRPT4_S 13
  7425. /** USB_D_NYETINTRPT4 : R/W1C; bitpos: [14]; default: 0;
  7426. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7427. * transmitted for a non isochronous OUT endpoint
  7428. * 0x0 : No interrupt
  7429. * 0x1 : NYET Interrupt
  7430. */
  7431. #define USB_D_NYETINTRPT4 (BIT(14))
  7432. #define USB_D_NYETINTRPT4_M (USB_D_NYETINTRPT4_V << USB_D_NYETINTRPT4_S)
  7433. #define USB_D_NYETINTRPT4_V 0x00000001
  7434. #define USB_D_NYETINTRPT4_S 14
  7435. /** USB_DIEPINT5_REG register
  7436. * Device IN Endpoint 5 Interrupt Register
  7437. */
  7438. #define USB_DIEPINT5_REG (SOC_DPORT_USB_BASE + 0x9a8)
  7439. /** USB_D_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0;
  7440. * 0x0 : No Transfer Complete Interrupt
  7441. * 0x1 : Transfer Completed Interrupt
  7442. */
  7443. #define USB_D_XFERCOMPL5 (BIT(0))
  7444. #define USB_D_XFERCOMPL5_M (USB_D_XFERCOMPL5_V << USB_D_XFERCOMPL5_S)
  7445. #define USB_D_XFERCOMPL5_V 0x00000001
  7446. #define USB_D_XFERCOMPL5_S 0
  7447. /** USB_D_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0;
  7448. * 0x0 : No Endpoint Disabled Interrupt
  7449. * 0x1 : Endpoint Disabled Interrupt
  7450. */
  7451. #define USB_D_EPDISBLD5 (BIT(1))
  7452. #define USB_D_EPDISBLD5_M (USB_D_EPDISBLD5_V << USB_D_EPDISBLD5_S)
  7453. #define USB_D_EPDISBLD5_V 0x00000001
  7454. #define USB_D_EPDISBLD5_S 1
  7455. /** USB_D_AHBERR5 : R/W1C; bitpos: [2]; default: 0;
  7456. * 0x0 : No AHB Error Interrupt
  7457. * 0x1 : AHB Error interrupt
  7458. */
  7459. #define USB_D_AHBERR5 (BIT(2))
  7460. #define USB_D_AHBERR5_M (USB_D_AHBERR5_V << USB_D_AHBERR5_S)
  7461. #define USB_D_AHBERR5_V 0x00000001
  7462. #define USB_D_AHBERR5_S 2
  7463. /** USB_D_TIMEOUT5 : R/W1C; bitpos: [3]; default: 0;
  7464. * 0x0 : No Timeout interrupt
  7465. * 0x1 : Timeout interrupt
  7466. */
  7467. #define USB_D_TIMEOUT5 (BIT(3))
  7468. #define USB_D_TIMEOUT5_M (USB_D_TIMEOUT5_V << USB_D_TIMEOUT5_S)
  7469. #define USB_D_TIMEOUT5_V 0x00000001
  7470. #define USB_D_TIMEOUT5_S 3
  7471. /** USB_D_INTKNTXFEMP5 : R/W1C; bitpos: [4]; default: 0;
  7472. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  7473. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  7474. */
  7475. #define USB_D_INTKNTXFEMP5 (BIT(4))
  7476. #define USB_D_INTKNTXFEMP5_M (USB_D_INTKNTXFEMP5_V << USB_D_INTKNTXFEMP5_S)
  7477. #define USB_D_INTKNTXFEMP5_V 0x00000001
  7478. #define USB_D_INTKNTXFEMP5_S 4
  7479. /** USB_D_INTKNEPMIS5 : R/W1C; bitpos: [5]; default: 0;
  7480. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  7481. * 0x1 : IN Token Received with EP Mismatch interrupt
  7482. */
  7483. #define USB_D_INTKNEPMIS5 (BIT(5))
  7484. #define USB_D_INTKNEPMIS5_M (USB_D_INTKNEPMIS5_V << USB_D_INTKNEPMIS5_S)
  7485. #define USB_D_INTKNEPMIS5_V 0x00000001
  7486. #define USB_D_INTKNEPMIS5_S 5
  7487. /** USB_D_INEPNAKEFF5 : R/W1C; bitpos: [6]; default: 0;
  7488. * IN Endpoint NAK Effective
  7489. * 0x0 : No IN Endpoint NAK Effective interrupt
  7490. * 0x1 : IN Endpoint NAK Effective interrupt
  7491. */
  7492. #define USB_D_INEPNAKEFF5 (BIT(6))
  7493. #define USB_D_INEPNAKEFF5_M (USB_D_INEPNAKEFF5_V << USB_D_INEPNAKEFF5_S)
  7494. #define USB_D_INEPNAKEFF5_V 0x00000001
  7495. #define USB_D_INEPNAKEFF5_S 6
  7496. /** USB_D_TXFEMP5 : RO; bitpos: [7]; default: 0;
  7497. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  7498. * completely empty
  7499. * 0x0 : No Transmit FIFO Empty interrupt
  7500. * 0x1 : Transmit FIFO Empty interrupt
  7501. */
  7502. #define USB_D_TXFEMP5 (BIT(7))
  7503. #define USB_D_TXFEMP5_M (USB_D_TXFEMP5_V << USB_D_TXFEMP5_S)
  7504. #define USB_D_TXFEMP5_V 0x00000001
  7505. #define USB_D_TXFEMP5_S 7
  7506. /** USB_D_TXFIFOUNDRN5 : R/W1C; bitpos: [8]; default: 0;
  7507. * The core generates this interrupt when it detects a transmit FIFO underrun
  7508. * condition in threshold mode for this endpoint
  7509. * 0x0 : No Fifo Underrun interrupt
  7510. * 0x1 : Fifo Underrun interrupt
  7511. */
  7512. #define USB_D_TXFIFOUNDRN5 (BIT(8))
  7513. #define USB_D_TXFIFOUNDRN5_M (USB_D_TXFIFOUNDRN5_V << USB_D_TXFIFOUNDRN5_S)
  7514. #define USB_D_TXFIFOUNDRN5_V 0x00000001
  7515. #define USB_D_TXFIFOUNDRN5_S 8
  7516. /** USB_D_BNAINTR5 : R/W1C; bitpos: [9]; default: 0;
  7517. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  7518. * this interrupt when the descriptor accessed is not ready for the Core to process,
  7519. * such as Host busy or DMA done
  7520. * 0x0 : No BNA interrupt
  7521. * 0x1 : BNA interrupt
  7522. */
  7523. #define USB_D_BNAINTR5 (BIT(9))
  7524. #define USB_D_BNAINTR5_M (USB_D_BNAINTR5_V << USB_D_BNAINTR5_S)
  7525. #define USB_D_BNAINTR5_V 0x00000001
  7526. #define USB_D_BNAINTR5_S 9
  7527. /** USB_D_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0;
  7528. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7529. * has been dropped. This bit does not have an associated mask bit and does not
  7530. * generate an interrupt
  7531. * 0x0 : No interrupt
  7532. * 0x1 : Packet Drop Status
  7533. */
  7534. #define USB_D_PKTDRPSTS5 (BIT(11))
  7535. #define USB_D_PKTDRPSTS5_M (USB_D_PKTDRPSTS5_V << USB_D_PKTDRPSTS5_S)
  7536. #define USB_D_PKTDRPSTS5_V 0x00000001
  7537. #define USB_D_PKTDRPSTS5_S 11
  7538. /** USB_D_BBLEERR5 : R/W1C; bitpos: [12]; default: 0;
  7539. * The core generates this interrupt when babble is received for the endpoint
  7540. * 0x0 : No interrupt
  7541. * 0x1 : BbleErr interrupt
  7542. */
  7543. #define USB_D_BBLEERR5 (BIT(12))
  7544. #define USB_D_BBLEERR5_M (USB_D_BBLEERR5_V << USB_D_BBLEERR5_S)
  7545. #define USB_D_BBLEERR5_V 0x00000001
  7546. #define USB_D_BBLEERR5_S 12
  7547. /** USB_D_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0;
  7548. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7549. * received by the device
  7550. * 0x0 : No interrupt
  7551. * 0x1 : NAK Interrupt
  7552. */
  7553. #define USB_D_NAKINTRPT5 (BIT(13))
  7554. #define USB_D_NAKINTRPT5_M (USB_D_NAKINTRPT5_V << USB_D_NAKINTRPT5_S)
  7555. #define USB_D_NAKINTRPT5_V 0x00000001
  7556. #define USB_D_NAKINTRPT5_S 13
  7557. /** USB_D_NYETINTRPT5 : R/W1C; bitpos: [14]; default: 0;
  7558. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7559. * transmitted for a non isochronous OUT endpoint
  7560. * 0x0 : No interrupt
  7561. * 0x1 : NYET Interrupt
  7562. */
  7563. #define USB_D_NYETINTRPT5 (BIT(14))
  7564. #define USB_D_NYETINTRPT5_M (USB_D_NYETINTRPT5_V << USB_D_NYETINTRPT5_S)
  7565. #define USB_D_NYETINTRPT5_V 0x00000001
  7566. #define USB_D_NYETINTRPT5_S 14
  7567. /** USB_DIEPINT6_REG register
  7568. * Device IN Endpoint 6 Interrupt Register
  7569. */
  7570. #define USB_DIEPINT6_REG (SOC_DPORT_USB_BASE + 0x9c8)
  7571. /** USB_D_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0;
  7572. * 0x0 : No Transfer Complete Interrupt
  7573. * 0x1 : Transfer Completed Interrupt
  7574. */
  7575. #define USB_D_XFERCOMPL6 (BIT(0))
  7576. #define USB_D_XFERCOMPL6_M (USB_D_XFERCOMPL6_V << USB_D_XFERCOMPL6_S)
  7577. #define USB_D_XFERCOMPL6_V 0x00000001
  7578. #define USB_D_XFERCOMPL6_S 0
  7579. /** USB_D_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0;
  7580. * 0x0 : No Endpoint Disabled Interrupt
  7581. * 0x1 : Endpoint Disabled Interrupt
  7582. */
  7583. #define USB_D_EPDISBLD6 (BIT(1))
  7584. #define USB_D_EPDISBLD6_M (USB_D_EPDISBLD6_V << USB_D_EPDISBLD6_S)
  7585. #define USB_D_EPDISBLD6_V 0x00000001
  7586. #define USB_D_EPDISBLD6_S 1
  7587. /** USB_D_AHBERR6 : R/W1C; bitpos: [2]; default: 0;
  7588. * 0x0 : No AHB Error Interrupt
  7589. * 0x1 : AHB Error interrupt
  7590. */
  7591. #define USB_D_AHBERR6 (BIT(2))
  7592. #define USB_D_AHBERR6_M (USB_D_AHBERR6_V << USB_D_AHBERR6_S)
  7593. #define USB_D_AHBERR6_V 0x00000001
  7594. #define USB_D_AHBERR6_S 2
  7595. /** USB_D_TIMEOUT6 : R/W1C; bitpos: [3]; default: 0;
  7596. * 0x0 : No Timeout interrupt
  7597. * 0x1 : Timeout interrupt
  7598. */
  7599. #define USB_D_TIMEOUT6 (BIT(3))
  7600. #define USB_D_TIMEOUT6_M (USB_D_TIMEOUT6_V << USB_D_TIMEOUT6_S)
  7601. #define USB_D_TIMEOUT6_V 0x00000001
  7602. #define USB_D_TIMEOUT6_S 3
  7603. /** USB_D_INTKNTXFEMP6 : R/W1C; bitpos: [4]; default: 0;
  7604. * 0x0 : No IN Token Received when TxFIFO Empty Interrupt
  7605. * 0x1 : IN Token Received when TxFIFO Empty Interrupt
  7606. */
  7607. #define USB_D_INTKNTXFEMP6 (BIT(4))
  7608. #define USB_D_INTKNTXFEMP6_M (USB_D_INTKNTXFEMP6_V << USB_D_INTKNTXFEMP6_S)
  7609. #define USB_D_INTKNTXFEMP6_V 0x00000001
  7610. #define USB_D_INTKNTXFEMP6_S 4
  7611. /** USB_D_INTKNEPMIS6 : R/W1C; bitpos: [5]; default: 0;
  7612. * 0x0 : No IN Token Received with EP Mismatch Interrupt
  7613. * 0x1 : IN Token Received with EP Mismatch interrupt
  7614. */
  7615. #define USB_D_INTKNEPMIS6 (BIT(5))
  7616. #define USB_D_INTKNEPMIS6_M (USB_D_INTKNEPMIS6_V << USB_D_INTKNEPMIS6_S)
  7617. #define USB_D_INTKNEPMIS6_V 0x00000001
  7618. #define USB_D_INTKNEPMIS6_S 5
  7619. /** USB_D_INEPNAKEFF6 : R/W1C; bitpos: [6]; default: 0;
  7620. * IN Endpoint NAK Effective
  7621. * 0x0 : No IN Endpoint NAK Effective interrupt
  7622. * 0x1 : IN Endpoint NAK Effective interrupt
  7623. */
  7624. #define USB_D_INEPNAKEFF6 (BIT(6))
  7625. #define USB_D_INEPNAKEFF6_M (USB_D_INEPNAKEFF6_V << USB_D_INEPNAKEFF6_S)
  7626. #define USB_D_INEPNAKEFF6_V 0x00000001
  7627. #define USB_D_INEPNAKEFF6_S 6
  7628. /** USB_D_TXFEMP6 : RO; bitpos: [7]; default: 0;
  7629. * This interrupt is asserted when the TxFIFO for this endpoint is either half or
  7630. * completely empty
  7631. * 0x0 : No Transmit FIFO Empty interrupt
  7632. * 0x1 : Transmit FIFO Empty interrupt
  7633. */
  7634. #define USB_D_TXFEMP6 (BIT(7))
  7635. #define USB_D_TXFEMP6_M (USB_D_TXFEMP6_V << USB_D_TXFEMP6_S)
  7636. #define USB_D_TXFEMP6_V 0x00000001
  7637. #define USB_D_TXFEMP6_S 7
  7638. /** USB_D_TXFIFOUNDRN6 : R/W1C; bitpos: [8]; default: 0;
  7639. * The core generates this interrupt when it detects a transmit FIFO underrun
  7640. * condition in threshold mode for this endpoint
  7641. * 0x0 : No Fifo Underrun interrupt
  7642. * 0x1 : Fifo Underrun interrupt
  7643. */
  7644. #define USB_D_TXFIFOUNDRN6 (BIT(8))
  7645. #define USB_D_TXFIFOUNDRN6_M (USB_D_TXFIFOUNDRN6_V << USB_D_TXFIFOUNDRN6_S)
  7646. #define USB_D_TXFIFOUNDRN6_V 0x00000001
  7647. #define USB_D_TXFIFOUNDRN6_S 8
  7648. /** USB_D_BNAINTR6 : R/W1C; bitpos: [9]; default: 0;
  7649. * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates
  7650. * this interrupt when the descriptor accessed is not ready for the Core to process,
  7651. * such as Host busy or DMA done
  7652. * 0x0 : No BNA interrupt
  7653. * 0x1 : BNA interrupt
  7654. */
  7655. #define USB_D_BNAINTR6 (BIT(9))
  7656. #define USB_D_BNAINTR6_M (USB_D_BNAINTR6_V << USB_D_BNAINTR6_S)
  7657. #define USB_D_BNAINTR6_V 0x00000001
  7658. #define USB_D_BNAINTR6_S 9
  7659. /** USB_D_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0;
  7660. * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet
  7661. * has been dropped. This bit does not have an associated mask bit and does not
  7662. * generate an interrupt
  7663. * 0x0 : No interrupt
  7664. * 0x1 : Packet Drop Status
  7665. */
  7666. #define USB_D_PKTDRPSTS6 (BIT(11))
  7667. #define USB_D_PKTDRPSTS6_M (USB_D_PKTDRPSTS6_V << USB_D_PKTDRPSTS6_S)
  7668. #define USB_D_PKTDRPSTS6_V 0x00000001
  7669. #define USB_D_PKTDRPSTS6_S 11
  7670. /** USB_D_BBLEERR6 : R/W1C; bitpos: [12]; default: 0;
  7671. * The core generates this interrupt when babble is received for the endpoint
  7672. * 0x0 : No interrupt
  7673. * 0x1 : BbleErr interrupt
  7674. */
  7675. #define USB_D_BBLEERR6 (BIT(12))
  7676. #define USB_D_BBLEERR6_M (USB_D_BBLEERR6_V << USB_D_BBLEERR6_S)
  7677. #define USB_D_BBLEERR6_V 0x00000001
  7678. #define USB_D_BBLEERR6_S 12
  7679. /** USB_D_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0;
  7680. * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or
  7681. * received by the device
  7682. * 0x0 : No interrupt
  7683. * 0x1 : NAK Interrupt
  7684. */
  7685. #define USB_D_NAKINTRPT6 (BIT(13))
  7686. #define USB_D_NAKINTRPT6_M (USB_D_NAKINTRPT6_V << USB_D_NAKINTRPT6_S)
  7687. #define USB_D_NAKINTRPT6_V 0x00000001
  7688. #define USB_D_NAKINTRPT6_S 13
  7689. /** USB_D_NYETINTRPT6 : R/W1C; bitpos: [14]; default: 0;
  7690. * NYET Interrupt. The core generates this interrupt when a NYET response is
  7691. * transmitted for a non isochronous OUT endpoint
  7692. * 0x0 : No interrupt
  7693. * 0x1 : NYET Interrupt
  7694. */
  7695. #define USB_D_NYETINTRPT6 (BIT(14))
  7696. #define USB_D_NYETINTRPT6_M (USB_D_NYETINTRPT6_V << USB_D_NYETINTRPT6_S)
  7697. #define USB_D_NYETINTRPT6_V 0x00000001
  7698. #define USB_D_NYETINTRPT6_S 14
  7699. /** USB_DOEPINT0_REG register
  7700. * Device OUT Endpoint 0 Interrupt Register
  7701. */
  7702. #define USB_DOEPINT0_REG (SOC_DPORT_USB_BASE + 0xb08)
  7703. /** USB_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0;
  7704. * Transfer Completed Interrupt
  7705. * 0x0 : No Transfer Complete Interrupt
  7706. * 0x1 : Transfer Complete Interrupt
  7707. */
  7708. #define USB_XFERCOMPL0 (BIT(0))
  7709. #define USB_XFERCOMPL0_M (USB_XFERCOMPL0_V << USB_XFERCOMPL0_S)
  7710. #define USB_XFERCOMPL0_V 0x00000001
  7711. #define USB_XFERCOMPL0_S 0
  7712. /** USB_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0;
  7713. * Endpoint Disabled Interrupt
  7714. * 0x0 : No Endpoint Disabled Interrupt
  7715. * 0x1 : Endpoint Disabled Interrupt
  7716. */
  7717. #define USB_EPDISBLD0 (BIT(1))
  7718. #define USB_EPDISBLD0_M (USB_EPDISBLD0_V << USB_EPDISBLD0_S)
  7719. #define USB_EPDISBLD0_V 0x00000001
  7720. #define USB_EPDISBLD0_S 1
  7721. /** USB_AHBERR0 : R/W1C; bitpos: [2]; default: 0;
  7722. * AHB Error
  7723. * 0x0 : No AHB Error Interrupt
  7724. * 0x1 : AHB Error interrupt
  7725. */
  7726. #define USB_AHBERR0 (BIT(2))
  7727. #define USB_AHBERR0_M (USB_AHBERR0_V << USB_AHBERR0_S)
  7728. #define USB_AHBERR0_V 0x00000001
  7729. #define USB_AHBERR0_S 2
  7730. /** USB_SETUP0 : R/W1C; bitpos: [3]; default: 0;
  7731. * SETUP Phase Done
  7732. * 0x0 : No SETUP Phase Done
  7733. * 0x1 : SETUP Phase Done
  7734. */
  7735. #define USB_SETUP0 (BIT(3))
  7736. #define USB_SETUP0_M (USB_SETUP0_V << USB_SETUP0_S)
  7737. #define USB_SETUP0_V 0x00000001
  7738. #define USB_SETUP0_S 3
  7739. /** USB_OUTTKNEPDIS0 : R/W1C; bitpos: [4]; default: 0;
  7740. * OUT Token Received When Endpoint Disabled
  7741. * 0x0 : No OUT Token Received When Endpoint Disabled
  7742. * 0x1 : OUT Token Received When Endpoint Disabled
  7743. */
  7744. #define USB_OUTTKNEPDIS0 (BIT(4))
  7745. #define USB_OUTTKNEPDIS0_M (USB_OUTTKNEPDIS0_V << USB_OUTTKNEPDIS0_S)
  7746. #define USB_OUTTKNEPDIS0_V 0x00000001
  7747. #define USB_OUTTKNEPDIS0_S 4
  7748. /** USB_STSPHSERCVD0 : R/W1C; bitpos: [5]; default: 0;
  7749. * Status Phase Received for Control Write
  7750. * 0x0 : No Status Phase Received for Control Write
  7751. * 0x1 : Status Phase Received for Control Write
  7752. */
  7753. #define USB_STSPHSERCVD0 (BIT(5))
  7754. #define USB_STSPHSERCVD0_M (USB_STSPHSERCVD0_V << USB_STSPHSERCVD0_S)
  7755. #define USB_STSPHSERCVD0_V 0x00000001
  7756. #define USB_STSPHSERCVD0_S 5
  7757. /** USB_BACK2BACKSETUP0 : R/W1C; bitpos: [6]; default: 0;
  7758. * Back-to-Back SETUP Packets Received
  7759. * 0x0 : No Back-to-Back SETUP Packets Received
  7760. * 0x1 : Back-to-Back SETUP Packets Received
  7761. */
  7762. #define USB_BACK2BACKSETUP0 (BIT(6))
  7763. #define USB_BACK2BACKSETUP0_M (USB_BACK2BACKSETUP0_V << USB_BACK2BACKSETUP0_S)
  7764. #define USB_BACK2BACKSETUP0_V 0x00000001
  7765. #define USB_BACK2BACKSETUP0_S 6
  7766. /** USB_OUTPKTERR0 : R/W1C; bitpos: [8]; default: 0;
  7767. * OUT Packet Error
  7768. * 0x0 : No OUT Packet Error
  7769. * 0x1 : OUT Packet Error
  7770. */
  7771. #define USB_OUTPKTERR0 (BIT(8))
  7772. #define USB_OUTPKTERR0_M (USB_OUTPKTERR0_V << USB_OUTPKTERR0_S)
  7773. #define USB_OUTPKTERR0_V 0x00000001
  7774. #define USB_OUTPKTERR0_S 8
  7775. /** USB_BNAINTR0 : R/W1C; bitpos: [9]; default: 0;
  7776. * Buffer Not Available Interrupt
  7777. * 0x0 : No BNA interrupt
  7778. * 0x1 : BNA interrupt
  7779. */
  7780. #define USB_BNAINTR0 (BIT(9))
  7781. #define USB_BNAINTR0_M (USB_BNAINTR0_V << USB_BNAINTR0_S)
  7782. #define USB_BNAINTR0_V 0x00000001
  7783. #define USB_BNAINTR0_S 9
  7784. /** USB_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0;
  7785. * 0x0 : No interrupt
  7786. * 0x1 : Packet Drop Status interrupt
  7787. */
  7788. #define USB_PKTDRPSTS0 (BIT(11))
  7789. #define USB_PKTDRPSTS0_M (USB_PKTDRPSTS0_V << USB_PKTDRPSTS0_S)
  7790. #define USB_PKTDRPSTS0_V 0x00000001
  7791. #define USB_PKTDRPSTS0_S 11
  7792. /** USB_BBLEERR0 : R/W1C; bitpos: [12]; default: 0;
  7793. * 0x0 : No BbleErr interrupt
  7794. * 0x1 : BbleErr interrupt
  7795. */
  7796. #define USB_BBLEERR0 (BIT(12))
  7797. #define USB_BBLEERR0_M (USB_BBLEERR0_V << USB_BBLEERR0_S)
  7798. #define USB_BBLEERR0_V 0x00000001
  7799. #define USB_BBLEERR0_S 12
  7800. /** USB_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0;
  7801. * 0x0 : No NAK interrupt
  7802. * 0x1 : NAK Interrupt
  7803. */
  7804. #define USB_NAKINTRPT0 (BIT(13))
  7805. #define USB_NAKINTRPT0_M (USB_NAKINTRPT0_V << USB_NAKINTRPT0_S)
  7806. #define USB_NAKINTRPT0_V 0x00000001
  7807. #define USB_NAKINTRPT0_S 13
  7808. /** USB_NYEPINTRPT0 : R/W1C; bitpos: [14]; default: 0;
  7809. * 0x0 : No NYET interrupt
  7810. * 0x1 : NYET Interrupt
  7811. */
  7812. #define USB_NYEPINTRPT0 (BIT(14))
  7813. #define USB_NYEPINTRPT0_M (USB_NYEPINTRPT0_V << USB_NYEPINTRPT0_S)
  7814. #define USB_NYEPINTRPT0_V 0x00000001
  7815. #define USB_NYEPINTRPT0_S 14
  7816. /** USB_STUPPKTRCVD0 : R/W1C; bitpos: [15]; default: 0;
  7817. * 0x0 : No Setup packet received
  7818. * 0x1 : Setup packet received
  7819. */
  7820. #define USB_STUPPKTRCVD0 (BIT(15))
  7821. #define USB_STUPPKTRCVD0_M (USB_STUPPKTRCVD0_V << USB_STUPPKTRCVD0_S)
  7822. #define USB_STUPPKTRCVD0_V 0x00000001
  7823. #define USB_STUPPKTRCVD0_S 15
  7824. /** USB_DOEPINT1_REG register
  7825. * Device OUT Endpoint 1 Interrupt Register
  7826. */
  7827. #define USB_DOEPINT1_REG (SOC_DPORT_USB_BASE + 0xb28)
  7828. /** USB_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0;
  7829. * Transfer Completed Interrupt
  7830. * 0x0 : No Transfer Complete Interrupt
  7831. * 0x1 : Transfer Complete Interrupt
  7832. */
  7833. #define USB_XFERCOMPL1 (BIT(0))
  7834. #define USB_XFERCOMPL1_M (USB_XFERCOMPL1_V << USB_XFERCOMPL1_S)
  7835. #define USB_XFERCOMPL1_V 0x00000001
  7836. #define USB_XFERCOMPL1_S 0
  7837. /** USB_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0;
  7838. * Endpoint Disabled Interrupt
  7839. * 0x0 : No Endpoint Disabled Interrupt
  7840. * 0x1 : Endpoint Disabled Interrupt
  7841. */
  7842. #define USB_EPDISBLD1 (BIT(1))
  7843. #define USB_EPDISBLD1_M (USB_EPDISBLD1_V << USB_EPDISBLD1_S)
  7844. #define USB_EPDISBLD1_V 0x00000001
  7845. #define USB_EPDISBLD1_S 1
  7846. /** USB_AHBERR1 : R/W1C; bitpos: [2]; default: 0;
  7847. * AHB Error
  7848. * 0x0 : No AHB Error Interrupt
  7849. * 0x1 : AHB Error interrupt
  7850. */
  7851. #define USB_AHBERR1 (BIT(2))
  7852. #define USB_AHBERR1_M (USB_AHBERR1_V << USB_AHBERR1_S)
  7853. #define USB_AHBERR1_V 0x00000001
  7854. #define USB_AHBERR1_S 2
  7855. /** USB_SETUP1 : R/W1C; bitpos: [3]; default: 0;
  7856. * SETUP Phase Done
  7857. * 0x0 : No SETUP Phase Done
  7858. * 0x1 : SETUP Phase Done
  7859. */
  7860. #define USB_SETUP1 (BIT(3))
  7861. #define USB_SETUP1_M (USB_SETUP1_V << USB_SETUP1_S)
  7862. #define USB_SETUP1_V 0x00000001
  7863. #define USB_SETUP1_S 3
  7864. /** USB_OUTTKNEPDIS1 : R/W1C; bitpos: [4]; default: 0;
  7865. * OUT Token Received When Endpoint Disabled
  7866. * 0x0 : No OUT Token Received When Endpoint Disabled
  7867. * 0x1 : OUT Token Received When Endpoint Disabled
  7868. */
  7869. #define USB_OUTTKNEPDIS1 (BIT(4))
  7870. #define USB_OUTTKNEPDIS1_M (USB_OUTTKNEPDIS1_V << USB_OUTTKNEPDIS1_S)
  7871. #define USB_OUTTKNEPDIS1_V 0x00000001
  7872. #define USB_OUTTKNEPDIS1_S 4
  7873. /** USB_STSPHSERCVD1 : R/W1C; bitpos: [5]; default: 0;
  7874. * Status Phase Received for Control Write
  7875. * 0x0 : No Status Phase Received for Control Write
  7876. * 0x1 : Status Phase Received for Control Write
  7877. */
  7878. #define USB_STSPHSERCVD1 (BIT(5))
  7879. #define USB_STSPHSERCVD1_M (USB_STSPHSERCVD1_V << USB_STSPHSERCVD1_S)
  7880. #define USB_STSPHSERCVD1_V 0x00000001
  7881. #define USB_STSPHSERCVD1_S 5
  7882. /** USB_BACK2BACKSETUP1 : R/W1C; bitpos: [6]; default: 0;
  7883. * Back-to-Back SETUP Packets Received
  7884. * 0x0 : No Back-to-Back SETUP Packets Received
  7885. * 0x1 : Back-to-Back SETUP Packets Received
  7886. */
  7887. #define USB_BACK2BACKSETUP1 (BIT(6))
  7888. #define USB_BACK2BACKSETUP1_M (USB_BACK2BACKSETUP1_V << USB_BACK2BACKSETUP1_S)
  7889. #define USB_BACK2BACKSETUP1_V 0x00000001
  7890. #define USB_BACK2BACKSETUP1_S 6
  7891. /** USB_OUTPKTERR1 : R/W1C; bitpos: [8]; default: 0;
  7892. * OUT Packet Error
  7893. * 0x0 : No OUT Packet Error
  7894. * 0x1 : OUT Packet Error
  7895. */
  7896. #define USB_OUTPKTERR1 (BIT(8))
  7897. #define USB_OUTPKTERR1_M (USB_OUTPKTERR1_V << USB_OUTPKTERR1_S)
  7898. #define USB_OUTPKTERR1_V 0x00000001
  7899. #define USB_OUTPKTERR1_S 8
  7900. /** USB_BNAINTR1 : R/W1C; bitpos: [9]; default: 0;
  7901. * Buffer Not Available Interrupt
  7902. * 0x0 : No BNA interrupt
  7903. * 0x1 : BNA interrupt
  7904. */
  7905. #define USB_BNAINTR1 (BIT(9))
  7906. #define USB_BNAINTR1_M (USB_BNAINTR1_V << USB_BNAINTR1_S)
  7907. #define USB_BNAINTR1_V 0x00000001
  7908. #define USB_BNAINTR1_S 9
  7909. /** USB_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0;
  7910. * 0x0 : No interrupt
  7911. * 0x1 : Packet Drop Status interrupt
  7912. */
  7913. #define USB_PKTDRPSTS1 (BIT(11))
  7914. #define USB_PKTDRPSTS1_M (USB_PKTDRPSTS1_V << USB_PKTDRPSTS1_S)
  7915. #define USB_PKTDRPSTS1_V 0x00000001
  7916. #define USB_PKTDRPSTS1_S 11
  7917. /** USB_BBLEERR1 : R/W1C; bitpos: [12]; default: 0;
  7918. * 0x0 : No BbleErr interrupt
  7919. * 0x1 : BbleErr interrupt
  7920. */
  7921. #define USB_BBLEERR1 (BIT(12))
  7922. #define USB_BBLEERR1_M (USB_BBLEERR1_V << USB_BBLEERR1_S)
  7923. #define USB_BBLEERR1_V 0x00000001
  7924. #define USB_BBLEERR1_S 12
  7925. /** USB_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0;
  7926. * 0x0 : No NAK interrupt
  7927. * 0x1 : NAK Interrupt
  7928. */
  7929. #define USB_NAKINTRPT1 (BIT(13))
  7930. #define USB_NAKINTRPT1_M (USB_NAKINTRPT1_V << USB_NAKINTRPT1_S)
  7931. #define USB_NAKINTRPT1_V 0x00000001
  7932. #define USB_NAKINTRPT1_S 13
  7933. /** USB_NYEPINTRPT1 : R/W1C; bitpos: [14]; default: 0;
  7934. * 0x0 : No NYET interrupt
  7935. * 0x1 : NYET Interrupt
  7936. */
  7937. #define USB_NYEPINTRPT1 (BIT(14))
  7938. #define USB_NYEPINTRPT1_M (USB_NYEPINTRPT1_V << USB_NYEPINTRPT1_S)
  7939. #define USB_NYEPINTRPT1_V 0x00000001
  7940. #define USB_NYEPINTRPT1_S 14
  7941. /** USB_STUPPKTRCVD1 : R/W1C; bitpos: [15]; default: 0;
  7942. * 0x0 : No Setup packet received
  7943. * 0x1 : Setup packet received
  7944. */
  7945. #define USB_STUPPKTRCVD1 (BIT(15))
  7946. #define USB_STUPPKTRCVD1_M (USB_STUPPKTRCVD1_V << USB_STUPPKTRCVD1_S)
  7947. #define USB_STUPPKTRCVD1_V 0x00000001
  7948. #define USB_STUPPKTRCVD1_S 15
  7949. /** USB_DOEPINT2_REG register
  7950. * Device OUT Endpoint 2 Interrupt Register
  7951. */
  7952. #define USB_DOEPINT2_REG (SOC_DPORT_USB_BASE + 0xb48)
  7953. /** USB_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0;
  7954. * Transfer Completed Interrupt
  7955. * 0x0 : No Transfer Complete Interrupt
  7956. * 0x1 : Transfer Complete Interrupt
  7957. */
  7958. #define USB_XFERCOMPL2 (BIT(0))
  7959. #define USB_XFERCOMPL2_M (USB_XFERCOMPL2_V << USB_XFERCOMPL2_S)
  7960. #define USB_XFERCOMPL2_V 0x00000001
  7961. #define USB_XFERCOMPL2_S 0
  7962. /** USB_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0;
  7963. * Endpoint Disabled Interrupt
  7964. * 0x0 : No Endpoint Disabled Interrupt
  7965. * 0x1 : Endpoint Disabled Interrupt
  7966. */
  7967. #define USB_EPDISBLD2 (BIT(1))
  7968. #define USB_EPDISBLD2_M (USB_EPDISBLD2_V << USB_EPDISBLD2_S)
  7969. #define USB_EPDISBLD2_V 0x00000001
  7970. #define USB_EPDISBLD2_S 1
  7971. /** USB_AHBERR2 : R/W1C; bitpos: [2]; default: 0;
  7972. * AHB Error
  7973. * 0x0 : No AHB Error Interrupt
  7974. * 0x1 : AHB Error interrupt
  7975. */
  7976. #define USB_AHBERR2 (BIT(2))
  7977. #define USB_AHBERR2_M (USB_AHBERR2_V << USB_AHBERR2_S)
  7978. #define USB_AHBERR2_V 0x00000001
  7979. #define USB_AHBERR2_S 2
  7980. /** USB_SETUP2 : R/W1C; bitpos: [3]; default: 0;
  7981. * SETUP Phase Done
  7982. * 0x0 : No SETUP Phase Done
  7983. * 0x1 : SETUP Phase Done
  7984. */
  7985. #define USB_SETUP2 (BIT(3))
  7986. #define USB_SETUP2_M (USB_SETUP2_V << USB_SETUP2_S)
  7987. #define USB_SETUP2_V 0x00000001
  7988. #define USB_SETUP2_S 3
  7989. /** USB_OUTTKNEPDIS2 : R/W1C; bitpos: [4]; default: 0;
  7990. * OUT Token Received When Endpoint Disabled
  7991. * 0x0 : No OUT Token Received When Endpoint Disabled
  7992. * 0x1 : OUT Token Received When Endpoint Disabled
  7993. */
  7994. #define USB_OUTTKNEPDIS2 (BIT(4))
  7995. #define USB_OUTTKNEPDIS2_M (USB_OUTTKNEPDIS2_V << USB_OUTTKNEPDIS2_S)
  7996. #define USB_OUTTKNEPDIS2_V 0x00000001
  7997. #define USB_OUTTKNEPDIS2_S 4
  7998. /** USB_STSPHSERCVD2 : R/W1C; bitpos: [5]; default: 0;
  7999. * Status Phase Received for Control Write
  8000. * 0x0 : No Status Phase Received for Control Write
  8001. * 0x1 : Status Phase Received for Control Write
  8002. */
  8003. #define USB_STSPHSERCVD2 (BIT(5))
  8004. #define USB_STSPHSERCVD2_M (USB_STSPHSERCVD2_V << USB_STSPHSERCVD2_S)
  8005. #define USB_STSPHSERCVD2_V 0x00000001
  8006. #define USB_STSPHSERCVD2_S 5
  8007. /** USB_BACK2BACKSETUP2 : R/W1C; bitpos: [6]; default: 0;
  8008. * Back-to-Back SETUP Packets Received
  8009. * 0x0 : No Back-to-Back SETUP Packets Received
  8010. * 0x1 : Back-to-Back SETUP Packets Received
  8011. */
  8012. #define USB_BACK2BACKSETUP2 (BIT(6))
  8013. #define USB_BACK2BACKSETUP2_M (USB_BACK2BACKSETUP2_V << USB_BACK2BACKSETUP2_S)
  8014. #define USB_BACK2BACKSETUP2_V 0x00000001
  8015. #define USB_BACK2BACKSETUP2_S 6
  8016. /** USB_OUTPKTERR2 : R/W1C; bitpos: [8]; default: 0;
  8017. * OUT Packet Error
  8018. * 0x0 : No OUT Packet Error
  8019. * 0x1 : OUT Packet Error
  8020. */
  8021. #define USB_OUTPKTERR2 (BIT(8))
  8022. #define USB_OUTPKTERR2_M (USB_OUTPKTERR2_V << USB_OUTPKTERR2_S)
  8023. #define USB_OUTPKTERR2_V 0x00000001
  8024. #define USB_OUTPKTERR2_S 8
  8025. /** USB_BNAINTR2 : R/W1C; bitpos: [9]; default: 0;
  8026. * Buffer Not Available Interrupt
  8027. * 0x0 : No BNA interrupt
  8028. * 0x1 : BNA interrupt
  8029. */
  8030. #define USB_BNAINTR2 (BIT(9))
  8031. #define USB_BNAINTR2_M (USB_BNAINTR2_V << USB_BNAINTR2_S)
  8032. #define USB_BNAINTR2_V 0x00000001
  8033. #define USB_BNAINTR2_S 9
  8034. /** USB_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0;
  8035. * 0x0 : No interrupt
  8036. * 0x1 : Packet Drop Status interrupt
  8037. */
  8038. #define USB_PKTDRPSTS2 (BIT(11))
  8039. #define USB_PKTDRPSTS2_M (USB_PKTDRPSTS2_V << USB_PKTDRPSTS2_S)
  8040. #define USB_PKTDRPSTS2_V 0x00000001
  8041. #define USB_PKTDRPSTS2_S 11
  8042. /** USB_BBLEERR2 : R/W1C; bitpos: [12]; default: 0;
  8043. * 0x0 : No BbleErr interrupt
  8044. * 0x1 : BbleErr interrupt
  8045. */
  8046. #define USB_BBLEERR2 (BIT(12))
  8047. #define USB_BBLEERR2_M (USB_BBLEERR2_V << USB_BBLEERR2_S)
  8048. #define USB_BBLEERR2_V 0x00000001
  8049. #define USB_BBLEERR2_S 12
  8050. /** USB_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0;
  8051. * 0x0 : No NAK interrupt
  8052. * 0x1 : NAK Interrupt
  8053. */
  8054. #define USB_NAKINTRPT2 (BIT(13))
  8055. #define USB_NAKINTRPT2_M (USB_NAKINTRPT2_V << USB_NAKINTRPT2_S)
  8056. #define USB_NAKINTRPT2_V 0x00000001
  8057. #define USB_NAKINTRPT2_S 13
  8058. /** USB_NYEPINTRPT2 : R/W1C; bitpos: [14]; default: 0;
  8059. * 0x0 : No NYET interrupt
  8060. * 0x1 : NYET Interrupt
  8061. */
  8062. #define USB_NYEPINTRPT2 (BIT(14))
  8063. #define USB_NYEPINTRPT2_M (USB_NYEPINTRPT2_V << USB_NYEPINTRPT2_S)
  8064. #define USB_NYEPINTRPT2_V 0x00000001
  8065. #define USB_NYEPINTRPT2_S 14
  8066. /** USB_STUPPKTRCVD2 : R/W1C; bitpos: [15]; default: 0;
  8067. * 0x0 : No Setup packet received
  8068. * 0x1 : Setup packet received
  8069. */
  8070. #define USB_STUPPKTRCVD2 (BIT(15))
  8071. #define USB_STUPPKTRCVD2_M (USB_STUPPKTRCVD2_V << USB_STUPPKTRCVD2_S)
  8072. #define USB_STUPPKTRCVD2_V 0x00000001
  8073. #define USB_STUPPKTRCVD2_S 15
  8074. /** USB_DOEPINT3_REG register
  8075. * Device OUT Endpoint 3 Interrupt Register
  8076. */
  8077. #define USB_DOEPINT3_REG (SOC_DPORT_USB_BASE + 0xb68)
  8078. /** USB_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0;
  8079. * Transfer Completed Interrupt
  8080. * 0x0 : No Transfer Complete Interrupt
  8081. * 0x1 : Transfer Complete Interrupt
  8082. */
  8083. #define USB_XFERCOMPL3 (BIT(0))
  8084. #define USB_XFERCOMPL3_M (USB_XFERCOMPL3_V << USB_XFERCOMPL3_S)
  8085. #define USB_XFERCOMPL3_V 0x00000001
  8086. #define USB_XFERCOMPL3_S 0
  8087. /** USB_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0;
  8088. * Endpoint Disabled Interrupt
  8089. * 0x0 : No Endpoint Disabled Interrupt
  8090. * 0x1 : Endpoint Disabled Interrupt
  8091. */
  8092. #define USB_EPDISBLD3 (BIT(1))
  8093. #define USB_EPDISBLD3_M (USB_EPDISBLD3_V << USB_EPDISBLD3_S)
  8094. #define USB_EPDISBLD3_V 0x00000001
  8095. #define USB_EPDISBLD3_S 1
  8096. /** USB_AHBERR3 : R/W1C; bitpos: [2]; default: 0;
  8097. * AHB Error
  8098. * 0x0 : No AHB Error Interrupt
  8099. * 0x1 : AHB Error interrupt
  8100. */
  8101. #define USB_AHBERR3 (BIT(2))
  8102. #define USB_AHBERR3_M (USB_AHBERR3_V << USB_AHBERR3_S)
  8103. #define USB_AHBERR3_V 0x00000001
  8104. #define USB_AHBERR3_S 2
  8105. /** USB_SETUP3 : R/W1C; bitpos: [3]; default: 0;
  8106. * SETUP Phase Done
  8107. * 0x0 : No SETUP Phase Done
  8108. * 0x1 : SETUP Phase Done
  8109. */
  8110. #define USB_SETUP3 (BIT(3))
  8111. #define USB_SETUP3_M (USB_SETUP3_V << USB_SETUP3_S)
  8112. #define USB_SETUP3_V 0x00000001
  8113. #define USB_SETUP3_S 3
  8114. /** USB_OUTTKNEPDIS3 : R/W1C; bitpos: [4]; default: 0;
  8115. * OUT Token Received When Endpoint Disabled
  8116. * 0x0 : No OUT Token Received When Endpoint Disabled
  8117. * 0x1 : OUT Token Received When Endpoint Disabled
  8118. */
  8119. #define USB_OUTTKNEPDIS3 (BIT(4))
  8120. #define USB_OUTTKNEPDIS3_M (USB_OUTTKNEPDIS3_V << USB_OUTTKNEPDIS3_S)
  8121. #define USB_OUTTKNEPDIS3_V 0x00000001
  8122. #define USB_OUTTKNEPDIS3_S 4
  8123. /** USB_STSPHSERCVD3 : R/W1C; bitpos: [5]; default: 0;
  8124. * Status Phase Received for Control Write
  8125. * 0x0 : No Status Phase Received for Control Write
  8126. * 0x1 : Status Phase Received for Control Write
  8127. */
  8128. #define USB_STSPHSERCVD3 (BIT(5))
  8129. #define USB_STSPHSERCVD3_M (USB_STSPHSERCVD3_V << USB_STSPHSERCVD3_S)
  8130. #define USB_STSPHSERCVD3_V 0x00000001
  8131. #define USB_STSPHSERCVD3_S 5
  8132. /** USB_BACK2BACKSETUP3 : R/W1C; bitpos: [6]; default: 0;
  8133. * Back-to-Back SETUP Packets Received
  8134. * 0x0 : No Back-to-Back SETUP Packets Received
  8135. * 0x1 : Back-to-Back SETUP Packets Received
  8136. */
  8137. #define USB_BACK2BACKSETUP3 (BIT(6))
  8138. #define USB_BACK2BACKSETUP3_M (USB_BACK2BACKSETUP3_V << USB_BACK2BACKSETUP3_S)
  8139. #define USB_BACK2BACKSETUP3_V 0x00000001
  8140. #define USB_BACK2BACKSETUP3_S 6
  8141. /** USB_OUTPKTERR3 : R/W1C; bitpos: [8]; default: 0;
  8142. * OUT Packet Error
  8143. * 0x0 : No OUT Packet Error
  8144. * 0x1 : OUT Packet Error
  8145. */
  8146. #define USB_OUTPKTERR3 (BIT(8))
  8147. #define USB_OUTPKTERR3_M (USB_OUTPKTERR3_V << USB_OUTPKTERR3_S)
  8148. #define USB_OUTPKTERR3_V 0x00000001
  8149. #define USB_OUTPKTERR3_S 8
  8150. /** USB_BNAINTR3 : R/W1C; bitpos: [9]; default: 0;
  8151. * Buffer Not Available Interrupt
  8152. * 0x0 : No BNA interrupt
  8153. * 0x1 : BNA interrupt
  8154. */
  8155. #define USB_BNAINTR3 (BIT(9))
  8156. #define USB_BNAINTR3_M (USB_BNAINTR3_V << USB_BNAINTR3_S)
  8157. #define USB_BNAINTR3_V 0x00000001
  8158. #define USB_BNAINTR3_S 9
  8159. /** USB_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0;
  8160. * 0x0 : No interrupt
  8161. * 0x1 : Packet Drop Status interrupt
  8162. */
  8163. #define USB_PKTDRPSTS3 (BIT(11))
  8164. #define USB_PKTDRPSTS3_M (USB_PKTDRPSTS3_V << USB_PKTDRPSTS3_S)
  8165. #define USB_PKTDRPSTS3_V 0x00000001
  8166. #define USB_PKTDRPSTS3_S 11
  8167. /** USB_BBLEERR3 : R/W1C; bitpos: [12]; default: 0;
  8168. * 0x0 : No BbleErr interrupt
  8169. * 0x1 : BbleErr interrupt
  8170. */
  8171. #define USB_BBLEERR3 (BIT(12))
  8172. #define USB_BBLEERR3_M (USB_BBLEERR3_V << USB_BBLEERR3_S)
  8173. #define USB_BBLEERR3_V 0x00000001
  8174. #define USB_BBLEERR3_S 12
  8175. /** USB_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0;
  8176. * 0x0 : No NAK interrupt
  8177. * 0x1 : NAK Interrupt
  8178. */
  8179. #define USB_NAKINTRPT3 (BIT(13))
  8180. #define USB_NAKINTRPT3_M (USB_NAKINTRPT3_V << USB_NAKINTRPT3_S)
  8181. #define USB_NAKINTRPT3_V 0x00000001
  8182. #define USB_NAKINTRPT3_S 13
  8183. /** USB_NYEPINTRPT3 : R/W1C; bitpos: [14]; default: 0;
  8184. * 0x0 : No NYET interrupt
  8185. * 0x1 : NYET Interrupt
  8186. */
  8187. #define USB_NYEPINTRPT3 (BIT(14))
  8188. #define USB_NYEPINTRPT3_M (USB_NYEPINTRPT3_V << USB_NYEPINTRPT3_S)
  8189. #define USB_NYEPINTRPT3_V 0x00000001
  8190. #define USB_NYEPINTRPT3_S 14
  8191. /** USB_STUPPKTRCVD3 : R/W1C; bitpos: [15]; default: 0;
  8192. * 0x0 : No Setup packet received
  8193. * 0x1 : Setup packet received
  8194. */
  8195. #define USB_STUPPKTRCVD3 (BIT(15))
  8196. #define USB_STUPPKTRCVD3_M (USB_STUPPKTRCVD3_V << USB_STUPPKTRCVD3_S)
  8197. #define USB_STUPPKTRCVD3_V 0x00000001
  8198. #define USB_STUPPKTRCVD3_S 15
  8199. /** USB_DOEPINT4_REG register
  8200. * Device OUT Endpoint 4 Interrupt Register
  8201. */
  8202. #define USB_DOEPINT4_REG (SOC_DPORT_USB_BASE + 0xb88)
  8203. /** USB_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0;
  8204. * Transfer Completed Interrupt
  8205. * 0x0 : No Transfer Complete Interrupt
  8206. * 0x1 : Transfer Complete Interrupt
  8207. */
  8208. #define USB_XFERCOMPL4 (BIT(0))
  8209. #define USB_XFERCOMPL4_M (USB_XFERCOMPL4_V << USB_XFERCOMPL4_S)
  8210. #define USB_XFERCOMPL4_V 0x00000001
  8211. #define USB_XFERCOMPL4_S 0
  8212. /** USB_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0;
  8213. * Endpoint Disabled Interrupt
  8214. * 0x0 : No Endpoint Disabled Interrupt
  8215. * 0x1 : Endpoint Disabled Interrupt
  8216. */
  8217. #define USB_EPDISBLD4 (BIT(1))
  8218. #define USB_EPDISBLD4_M (USB_EPDISBLD4_V << USB_EPDISBLD4_S)
  8219. #define USB_EPDISBLD4_V 0x00000001
  8220. #define USB_EPDISBLD4_S 1
  8221. /** USB_AHBERR4 : R/W1C; bitpos: [2]; default: 0;
  8222. * AHB Error
  8223. * 0x0 : No AHB Error Interrupt
  8224. * 0x1 : AHB Error interrupt
  8225. */
  8226. #define USB_AHBERR4 (BIT(2))
  8227. #define USB_AHBERR4_M (USB_AHBERR4_V << USB_AHBERR4_S)
  8228. #define USB_AHBERR4_V 0x00000001
  8229. #define USB_AHBERR4_S 2
  8230. /** USB_SETUP4 : R/W1C; bitpos: [3]; default: 0;
  8231. * SETUP Phase Done
  8232. * 0x0 : No SETUP Phase Done
  8233. * 0x1 : SETUP Phase Done
  8234. */
  8235. #define USB_SETUP4 (BIT(3))
  8236. #define USB_SETUP4_M (USB_SETUP4_V << USB_SETUP4_S)
  8237. #define USB_SETUP4_V 0x00000001
  8238. #define USB_SETUP4_S 3
  8239. /** USB_OUTTKNEPDIS4 : R/W1C; bitpos: [4]; default: 0;
  8240. * OUT Token Received When Endpoint Disabled
  8241. * 0x0 : No OUT Token Received When Endpoint Disabled
  8242. * 0x1 : OUT Token Received When Endpoint Disabled
  8243. */
  8244. #define USB_OUTTKNEPDIS4 (BIT(4))
  8245. #define USB_OUTTKNEPDIS4_M (USB_OUTTKNEPDIS4_V << USB_OUTTKNEPDIS4_S)
  8246. #define USB_OUTTKNEPDIS4_V 0x00000001
  8247. #define USB_OUTTKNEPDIS4_S 4
  8248. /** USB_STSPHSERCVD4 : R/W1C; bitpos: [5]; default: 0;
  8249. * Status Phase Received for Control Write
  8250. * 0x0 : No Status Phase Received for Control Write
  8251. * 0x1 : Status Phase Received for Control Write
  8252. */
  8253. #define USB_STSPHSERCVD4 (BIT(5))
  8254. #define USB_STSPHSERCVD4_M (USB_STSPHSERCVD4_V << USB_STSPHSERCVD4_S)
  8255. #define USB_STSPHSERCVD4_V 0x00000001
  8256. #define USB_STSPHSERCVD4_S 5
  8257. /** USB_BACK2BACKSETUP4 : R/W1C; bitpos: [6]; default: 0;
  8258. * Back-to-Back SETUP Packets Received
  8259. * 0x0 : No Back-to-Back SETUP Packets Received
  8260. * 0x1 : Back-to-Back SETUP Packets Received
  8261. */
  8262. #define USB_BACK2BACKSETUP4 (BIT(6))
  8263. #define USB_BACK2BACKSETUP4_M (USB_BACK2BACKSETUP4_V << USB_BACK2BACKSETUP4_S)
  8264. #define USB_BACK2BACKSETUP4_V 0x00000001
  8265. #define USB_BACK2BACKSETUP4_S 6
  8266. /** USB_OUTPKTERR4 : R/W1C; bitpos: [8]; default: 0;
  8267. * OUT Packet Error
  8268. * 0x0 : No OUT Packet Error
  8269. * 0x1 : OUT Packet Error
  8270. */
  8271. #define USB_OUTPKTERR4 (BIT(8))
  8272. #define USB_OUTPKTERR4_M (USB_OUTPKTERR4_V << USB_OUTPKTERR4_S)
  8273. #define USB_OUTPKTERR4_V 0x00000001
  8274. #define USB_OUTPKTERR4_S 8
  8275. /** USB_BNAINTR4 : R/W1C; bitpos: [9]; default: 0;
  8276. * Buffer Not Available Interrupt
  8277. * 0x0 : No BNA interrupt
  8278. * 0x1 : BNA interrupt
  8279. */
  8280. #define USB_BNAINTR4 (BIT(9))
  8281. #define USB_BNAINTR4_M (USB_BNAINTR4_V << USB_BNAINTR4_S)
  8282. #define USB_BNAINTR4_V 0x00000001
  8283. #define USB_BNAINTR4_S 9
  8284. /** USB_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0;
  8285. * 0x0 : No interrupt
  8286. * 0x1 : Packet Drop Status interrupt
  8287. */
  8288. #define USB_PKTDRPSTS4 (BIT(11))
  8289. #define USB_PKTDRPSTS4_M (USB_PKTDRPSTS4_V << USB_PKTDRPSTS4_S)
  8290. #define USB_PKTDRPSTS4_V 0x00000001
  8291. #define USB_PKTDRPSTS4_S 11
  8292. /** USB_BBLEERR4 : R/W1C; bitpos: [12]; default: 0;
  8293. * 0x0 : No BbleErr interrupt
  8294. * 0x1 : BbleErr interrupt
  8295. */
  8296. #define USB_BBLEERR4 (BIT(12))
  8297. #define USB_BBLEERR4_M (USB_BBLEERR4_V << USB_BBLEERR4_S)
  8298. #define USB_BBLEERR4_V 0x00000001
  8299. #define USB_BBLEERR4_S 12
  8300. /** USB_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0;
  8301. * 0x0 : No NAK interrupt
  8302. * 0x1 : NAK Interrupt
  8303. */
  8304. #define USB_NAKINTRPT4 (BIT(13))
  8305. #define USB_NAKINTRPT4_M (USB_NAKINTRPT4_V << USB_NAKINTRPT4_S)
  8306. #define USB_NAKINTRPT4_V 0x00000001
  8307. #define USB_NAKINTRPT4_S 13
  8308. /** USB_NYEPINTRPT4 : R/W1C; bitpos: [14]; default: 0;
  8309. * 0x0 : No NYET interrupt
  8310. * 0x1 : NYET Interrupt
  8311. */
  8312. #define USB_NYEPINTRPT4 (BIT(14))
  8313. #define USB_NYEPINTRPT4_M (USB_NYEPINTRPT4_V << USB_NYEPINTRPT4_S)
  8314. #define USB_NYEPINTRPT4_V 0x00000001
  8315. #define USB_NYEPINTRPT4_S 14
  8316. /** USB_STUPPKTRCVD4 : R/W1C; bitpos: [15]; default: 0;
  8317. * 0x0 : No Setup packet received
  8318. * 0x1 : Setup packet received
  8319. */
  8320. #define USB_STUPPKTRCVD4 (BIT(15))
  8321. #define USB_STUPPKTRCVD4_M (USB_STUPPKTRCVD4_V << USB_STUPPKTRCVD4_S)
  8322. #define USB_STUPPKTRCVD4_V 0x00000001
  8323. #define USB_STUPPKTRCVD4_S 15
  8324. /** USB_DOEPINT5_REG register
  8325. * Device OUT Endpoint 5 Interrupt Register
  8326. */
  8327. #define USB_DOEPINT5_REG (SOC_DPORT_USB_BASE + 0xba8)
  8328. /** USB_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0;
  8329. * Transfer Completed Interrupt
  8330. * 0x0 : No Transfer Complete Interrupt
  8331. * 0x1 : Transfer Complete Interrupt
  8332. */
  8333. #define USB_XFERCOMPL5 (BIT(0))
  8334. #define USB_XFERCOMPL5_M (USB_XFERCOMPL5_V << USB_XFERCOMPL5_S)
  8335. #define USB_XFERCOMPL5_V 0x00000001
  8336. #define USB_XFERCOMPL5_S 0
  8337. /** USB_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0;
  8338. * Endpoint Disabled Interrupt
  8339. * 0x0 : No Endpoint Disabled Interrupt
  8340. * 0x1 : Endpoint Disabled Interrupt
  8341. */
  8342. #define USB_EPDISBLD5 (BIT(1))
  8343. #define USB_EPDISBLD5_M (USB_EPDISBLD5_V << USB_EPDISBLD5_S)
  8344. #define USB_EPDISBLD5_V 0x00000001
  8345. #define USB_EPDISBLD5_S 1
  8346. /** USB_AHBERR5 : R/W1C; bitpos: [2]; default: 0;
  8347. * AHB Error
  8348. * 0x0 : No AHB Error Interrupt
  8349. * 0x1 : AHB Error interrupt
  8350. */
  8351. #define USB_AHBERR5 (BIT(2))
  8352. #define USB_AHBERR5_M (USB_AHBERR5_V << USB_AHBERR5_S)
  8353. #define USB_AHBERR5_V 0x00000001
  8354. #define USB_AHBERR5_S 2
  8355. /** USB_SETUP5 : R/W1C; bitpos: [3]; default: 0;
  8356. * SETUP Phase Done
  8357. * 0x0 : No SETUP Phase Done
  8358. * 0x1 : SETUP Phase Done
  8359. */
  8360. #define USB_SETUP5 (BIT(3))
  8361. #define USB_SETUP5_M (USB_SETUP5_V << USB_SETUP5_S)
  8362. #define USB_SETUP5_V 0x00000001
  8363. #define USB_SETUP5_S 3
  8364. /** USB_OUTTKNEPDIS5 : R/W1C; bitpos: [4]; default: 0;
  8365. * OUT Token Received When Endpoint Disabled
  8366. * 0x0 : No OUT Token Received When Endpoint Disabled
  8367. * 0x1 : OUT Token Received When Endpoint Disabled
  8368. */
  8369. #define USB_OUTTKNEPDIS5 (BIT(4))
  8370. #define USB_OUTTKNEPDIS5_M (USB_OUTTKNEPDIS5_V << USB_OUTTKNEPDIS5_S)
  8371. #define USB_OUTTKNEPDIS5_V 0x00000001
  8372. #define USB_OUTTKNEPDIS5_S 4
  8373. /** USB_STSPHSERCVD5 : R/W1C; bitpos: [5]; default: 0;
  8374. * Status Phase Received for Control Write
  8375. * 0x0 : No Status Phase Received for Control Write
  8376. * 0x1 : Status Phase Received for Control Write
  8377. */
  8378. #define USB_STSPHSERCVD5 (BIT(5))
  8379. #define USB_STSPHSERCVD5_M (USB_STSPHSERCVD5_V << USB_STSPHSERCVD5_S)
  8380. #define USB_STSPHSERCVD5_V 0x00000001
  8381. #define USB_STSPHSERCVD5_S 5
  8382. /** USB_BACK2BACKSETUP5 : R/W1C; bitpos: [6]; default: 0;
  8383. * Back-to-Back SETUP Packets Received
  8384. * 0x0 : No Back-to-Back SETUP Packets Received
  8385. * 0x1 : Back-to-Back SETUP Packets Received
  8386. */
  8387. #define USB_BACK2BACKSETUP5 (BIT(6))
  8388. #define USB_BACK2BACKSETUP5_M (USB_BACK2BACKSETUP5_V << USB_BACK2BACKSETUP5_S)
  8389. #define USB_BACK2BACKSETUP5_V 0x00000001
  8390. #define USB_BACK2BACKSETUP5_S 6
  8391. /** USB_OUTPKTERR5 : R/W1C; bitpos: [8]; default: 0;
  8392. * OUT Packet Error
  8393. * 0x0 : No OUT Packet Error
  8394. * 0x1 : OUT Packet Error
  8395. */
  8396. #define USB_OUTPKTERR5 (BIT(8))
  8397. #define USB_OUTPKTERR5_M (USB_OUTPKTERR5_V << USB_OUTPKTERR5_S)
  8398. #define USB_OUTPKTERR5_V 0x00000001
  8399. #define USB_OUTPKTERR5_S 8
  8400. /** USB_BNAINTR5 : R/W1C; bitpos: [9]; default: 0;
  8401. * Buffer Not Available Interrupt
  8402. * 0x0 : No BNA interrupt
  8403. * 0x1 : BNA interrupt
  8404. */
  8405. #define USB_BNAINTR5 (BIT(9))
  8406. #define USB_BNAINTR5_M (USB_BNAINTR5_V << USB_BNAINTR5_S)
  8407. #define USB_BNAINTR5_V 0x00000001
  8408. #define USB_BNAINTR5_S 9
  8409. /** USB_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0;
  8410. * 0x0 : No interrupt
  8411. * 0x1 : Packet Drop Status interrupt
  8412. */
  8413. #define USB_PKTDRPSTS5 (BIT(11))
  8414. #define USB_PKTDRPSTS5_M (USB_PKTDRPSTS5_V << USB_PKTDRPSTS5_S)
  8415. #define USB_PKTDRPSTS5_V 0x00000001
  8416. #define USB_PKTDRPSTS5_S 11
  8417. /** USB_BBLEERR5 : R/W1C; bitpos: [12]; default: 0;
  8418. * 0x0 : No BbleErr interrupt
  8419. * 0x1 : BbleErr interrupt
  8420. */
  8421. #define USB_BBLEERR5 (BIT(12))
  8422. #define USB_BBLEERR5_M (USB_BBLEERR5_V << USB_BBLEERR5_S)
  8423. #define USB_BBLEERR5_V 0x00000001
  8424. #define USB_BBLEERR5_S 12
  8425. /** USB_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0;
  8426. * 0x0 : No NAK interrupt
  8427. * 0x1 : NAK Interrupt
  8428. */
  8429. #define USB_NAKINTRPT5 (BIT(13))
  8430. #define USB_NAKINTRPT5_M (USB_NAKINTRPT5_V << USB_NAKINTRPT5_S)
  8431. #define USB_NAKINTRPT5_V 0x00000001
  8432. #define USB_NAKINTRPT5_S 13
  8433. /** USB_NYEPINTRPT5 : R/W1C; bitpos: [14]; default: 0;
  8434. * 0x0 : No NYET interrupt
  8435. * 0x1 : NYET Interrupt
  8436. */
  8437. #define USB_NYEPINTRPT5 (BIT(14))
  8438. #define USB_NYEPINTRPT5_M (USB_NYEPINTRPT5_V << USB_NYEPINTRPT5_S)
  8439. #define USB_NYEPINTRPT5_V 0x00000001
  8440. #define USB_NYEPINTRPT5_S 14
  8441. /** USB_STUPPKTRCVD5 : R/W1C; bitpos: [15]; default: 0;
  8442. * 0x0 : No Setup packet received
  8443. * 0x1 : Setup packet received
  8444. */
  8445. #define USB_STUPPKTRCVD5 (BIT(15))
  8446. #define USB_STUPPKTRCVD5_M (USB_STUPPKTRCVD5_V << USB_STUPPKTRCVD5_S)
  8447. #define USB_STUPPKTRCVD5_V 0x00000001
  8448. #define USB_STUPPKTRCVD5_S 15
  8449. /** USB_DOEPINT6_REG register
  8450. * Device OUT Endpoint 6 Interrupt Register
  8451. */
  8452. #define USB_DOEPINT6_REG (SOC_DPORT_USB_BASE + 0xbc8)
  8453. /** USB_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0;
  8454. * Transfer Completed Interrupt
  8455. * 0x0 : No Transfer Complete Interrupt
  8456. * 0x1 : Transfer Complete Interrupt
  8457. */
  8458. #define USB_XFERCOMPL6 (BIT(0))
  8459. #define USB_XFERCOMPL6_M (USB_XFERCOMPL6_V << USB_XFERCOMPL6_S)
  8460. #define USB_XFERCOMPL6_V 0x00000001
  8461. #define USB_XFERCOMPL6_S 0
  8462. /** USB_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0;
  8463. * Endpoint Disabled Interrupt
  8464. * 0x0 : No Endpoint Disabled Interrupt
  8465. * 0x1 : Endpoint Disabled Interrupt
  8466. */
  8467. #define USB_EPDISBLD6 (BIT(1))
  8468. #define USB_EPDISBLD6_M (USB_EPDISBLD6_V << USB_EPDISBLD6_S)
  8469. #define USB_EPDISBLD6_V 0x00000001
  8470. #define USB_EPDISBLD6_S 1
  8471. /** USB_AHBERR6 : R/W1C; bitpos: [2]; default: 0;
  8472. * AHB Error
  8473. * 0x0 : No AHB Error Interrupt
  8474. * 0x1 : AHB Error interrupt
  8475. */
  8476. #define USB_AHBERR6 (BIT(2))
  8477. #define USB_AHBERR6_M (USB_AHBERR6_V << USB_AHBERR6_S)
  8478. #define USB_AHBERR6_V 0x00000001
  8479. #define USB_AHBERR6_S 2
  8480. /** USB_SETUP6 : R/W1C; bitpos: [3]; default: 0;
  8481. * SETUP Phase Done
  8482. * 0x0 : No SETUP Phase Done
  8483. * 0x1 : SETUP Phase Done
  8484. */
  8485. #define USB_SETUP6 (BIT(3))
  8486. #define USB_SETUP6_M (USB_SETUP6_V << USB_SETUP6_S)
  8487. #define USB_SETUP6_V 0x00000001
  8488. #define USB_SETUP6_S 3
  8489. /** USB_OUTTKNEPDIS6 : R/W1C; bitpos: [4]; default: 0;
  8490. * OUT Token Received When Endpoint Disabled
  8491. * 0x0 : No OUT Token Received When Endpoint Disabled
  8492. * 0x1 : OUT Token Received When Endpoint Disabled
  8493. */
  8494. #define USB_OUTTKNEPDIS6 (BIT(4))
  8495. #define USB_OUTTKNEPDIS6_M (USB_OUTTKNEPDIS6_V << USB_OUTTKNEPDIS6_S)
  8496. #define USB_OUTTKNEPDIS6_V 0x00000001
  8497. #define USB_OUTTKNEPDIS6_S 4
  8498. /** USB_STSPHSERCVD6 : R/W1C; bitpos: [5]; default: 0;
  8499. * Status Phase Received for Control Write
  8500. * 0x0 : No Status Phase Received for Control Write
  8501. * 0x1 : Status Phase Received for Control Write
  8502. */
  8503. #define USB_STSPHSERCVD6 (BIT(5))
  8504. #define USB_STSPHSERCVD6_M (USB_STSPHSERCVD6_V << USB_STSPHSERCVD6_S)
  8505. #define USB_STSPHSERCVD6_V 0x00000001
  8506. #define USB_STSPHSERCVD6_S 5
  8507. /** USB_BACK2BACKSETUP6 : R/W1C; bitpos: [6]; default: 0;
  8508. * Back-to-Back SETUP Packets Received
  8509. * 0x0 : No Back-to-Back SETUP Packets Received
  8510. * 0x1 : Back-to-Back SETUP Packets Received
  8511. */
  8512. #define USB_BACK2BACKSETUP6 (BIT(6))
  8513. #define USB_BACK2BACKSETUP6_M (USB_BACK2BACKSETUP6_V << USB_BACK2BACKSETUP6_S)
  8514. #define USB_BACK2BACKSETUP6_V 0x00000001
  8515. #define USB_BACK2BACKSETUP6_S 6
  8516. /** USB_OUTPKTERR6 : R/W1C; bitpos: [8]; default: 0;
  8517. * OUT Packet Error
  8518. * 0x0 : No OUT Packet Error
  8519. * 0x1 : OUT Packet Error
  8520. */
  8521. #define USB_OUTPKTERR6 (BIT(8))
  8522. #define USB_OUTPKTERR6_M (USB_OUTPKTERR6_V << USB_OUTPKTERR6_S)
  8523. #define USB_OUTPKTERR6_V 0x00000001
  8524. #define USB_OUTPKTERR6_S 8
  8525. /** USB_BNAINTR6 : R/W1C; bitpos: [9]; default: 0;
  8526. * Buffer Not Available Interrupt
  8527. * 0x0 : No BNA interrupt
  8528. * 0x1 : BNA interrupt
  8529. */
  8530. #define USB_BNAINTR6 (BIT(9))
  8531. #define USB_BNAINTR6_M (USB_BNAINTR6_V << USB_BNAINTR6_S)
  8532. #define USB_BNAINTR6_V 0x00000001
  8533. #define USB_BNAINTR6_S 9
  8534. /** USB_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0;
  8535. * 0x0 : No interrupt
  8536. * 0x1 : Packet Drop Status interrupt
  8537. */
  8538. #define USB_PKTDRPSTS6 (BIT(11))
  8539. #define USB_PKTDRPSTS6_M (USB_PKTDRPSTS6_V << USB_PKTDRPSTS6_S)
  8540. #define USB_PKTDRPSTS6_V 0x00000001
  8541. #define USB_PKTDRPSTS6_S 11
  8542. /** USB_BBLEERR6 : R/W1C; bitpos: [12]; default: 0;
  8543. * 0x0 : No BbleErr interrupt
  8544. * 0x1 : BbleErr interrupt
  8545. */
  8546. #define USB_BBLEERR6 (BIT(12))
  8547. #define USB_BBLEERR6_M (USB_BBLEERR6_V << USB_BBLEERR6_S)
  8548. #define USB_BBLEERR6_V 0x00000001
  8549. #define USB_BBLEERR6_S 12
  8550. /** USB_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0;
  8551. * 0x0 : No NAK interrupt
  8552. * 0x1 : NAK Interrupt
  8553. */
  8554. #define USB_NAKINTRPT6 (BIT(13))
  8555. #define USB_NAKINTRPT6_M (USB_NAKINTRPT6_V << USB_NAKINTRPT6_S)
  8556. #define USB_NAKINTRPT6_V 0x00000001
  8557. #define USB_NAKINTRPT6_S 13
  8558. /** USB_NYEPINTRPT6 : R/W1C; bitpos: [14]; default: 0;
  8559. * 0x0 : No NYET interrupt
  8560. * 0x1 : NYET Interrupt
  8561. */
  8562. #define USB_NYEPINTRPT6 (BIT(14))
  8563. #define USB_NYEPINTRPT6_M (USB_NYEPINTRPT6_V << USB_NYEPINTRPT6_S)
  8564. #define USB_NYEPINTRPT6_V 0x00000001
  8565. #define USB_NYEPINTRPT6_S 14
  8566. /** USB_STUPPKTRCVD6 : R/W1C; bitpos: [15]; default: 0;
  8567. * 0x0 : No Setup packet received
  8568. * 0x1 : Setup packet received
  8569. */
  8570. #define USB_STUPPKTRCVD6 (BIT(15))
  8571. #define USB_STUPPKTRCVD6_M (USB_STUPPKTRCVD6_V << USB_STUPPKTRCVD6_S)
  8572. #define USB_STUPPKTRCVD6_V 0x00000001
  8573. #define USB_STUPPKTRCVD6_S 15
  8574. /** configuration registers */
  8575. /** USB_GAHBCFG_REG register
  8576. * AHB Configuration Register
  8577. */
  8578. #define USB_GAHBCFG_REG (SOC_DPORT_USB_BASE + 0x8)
  8579. /** USB_GLBLLNTRMSK : R/W; bitpos: [0]; default: 0;
  8580. * 1'b0: Mask the interrupt assertion to the application.
  8581. * 1'b1: Unmask the interrupt assertion to the application
  8582. */
  8583. #define USB_GLBLLNTRMSK (BIT(0))
  8584. #define USB_GLBLLNTRMSK_M (USB_GLBLLNTRMSK_V << USB_GLBLLNTRMSK_S)
  8585. #define USB_GLBLLNTRMSK_V 0x00000001
  8586. #define USB_GLBLLNTRMSK_S 0
  8587. /** USB_HBSTLEN : R/W; bitpos: [5:1]; default: 0;
  8588. * this field is used in Internal DMA modes
  8589. * 4'b0000 Single
  8590. * 4'b0001: INCR
  8591. * 4'b0011 INCR4
  8592. * 4'b0101 INCR8
  8593. * 4'b0111 INCR16
  8594. * Others: Reserved
  8595. */
  8596. #define USB_HBSTLEN 0x0000000F
  8597. #define USB_HBSTLEN_M (USB_HBSTLEN_V << USB_HBSTLEN_S)
  8598. #define USB_HBSTLEN_V 0x0000000F
  8599. #define USB_HBSTLEN_S 1
  8600. /** USB_DMAEN : R/W; bitpos: [5]; default: 0;
  8601. * This bit is always 0 when Slave-Only mode has been selected
  8602. * 1'b0:Core operates in Slave mode
  8603. * 1'b1:Core operates in a DMA mode
  8604. */
  8605. #define USB_DMAEN (BIT(5))
  8606. #define USB_DMAEN_M (USB_DMAEN_V << USB_DMAEN_S)
  8607. #define USB_DMAEN_V 0x00000001
  8608. #define USB_DMAEN_S 5
  8609. /** USB_NPTXFEMPLVL : R/W; bitpos: [7]; default: 0;
  8610. * Non-Periodic TxFIFO Empty Level
  8611. * 1'b0: DIEPINTn_REG.REG_TXFEMP interrupt indicates that the Non-Periodic TxFIFO is
  8612. * half empty or that the IN Endpoint TxFIFO is half empty
  8613. * 1'b1: GINTSTS_REG.USB_NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is
  8614. * completely empty or that the IN Endpoint TxFIFO is completely empty
  8615. */
  8616. #define USB_NPTXFEMPLVL (BIT(7))
  8617. #define USB_NPTXFEMPLVL_M (USB_NPTXFEMPLVL_V << USB_NPTXFEMPLVL_S)
  8618. #define USB_NPTXFEMPLVL_V 0x00000001
  8619. #define USB_NPTXFEMPLVL_S 7
  8620. /** USB_PTXFEMPLVL : R/W; bitpos: [8]; default: 0;
  8621. * Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt
  8622. * register (GINTSTS_REG.USB_PTXFEMP) is triggered. This bit is used only in Slave
  8623. * mode
  8624. * 1'b0: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is half
  8625. * empty
  8626. * 1'b1: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is
  8627. * completely empty
  8628. */
  8629. #define USB_PTXFEMPLVL (BIT(8))
  8630. #define USB_PTXFEMPLVL_M (USB_PTXFEMPLVL_V << USB_PTXFEMPLVL_S)
  8631. #define USB_PTXFEMPLVL_V 0x00000001
  8632. #define USB_PTXFEMPLVL_S 8
  8633. /** USB_REMMEMSUPP : R/W; bitpos: [21]; default: 0;
  8634. * Remote Memory Support (RemMemSupp) This bit is programmed to enable the
  8635. * functionality to wait for thesystem DMA Done Signal for the DMA Write Transfers
  8636. * 1'b0:Remote Memory Support Feature disabled
  8637. * 1'b1:Remote Memory Support Feature enabled
  8638. */
  8639. #define USB_REMMEMSUPP (BIT(21))
  8640. #define USB_REMMEMSUPP_M (USB_REMMEMSUPP_V << USB_REMMEMSUPP_S)
  8641. #define USB_REMMEMSUPP_V 0x00000001
  8642. #define USB_REMMEMSUPP_S 21
  8643. /** USB_NOTIALLDMAWRIT : R/W; bitpos: [22]; default: 0;
  8644. * Notify All DMA Write Transactions (NotiAllDmaWrit) This bit is programmed to enable
  8645. * the System DMA Done functionality for all the DMA write Transactions corresponding
  8646. * to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1
  8647. */
  8648. #define USB_NOTIALLDMAWRIT (BIT(22))
  8649. #define USB_NOTIALLDMAWRIT_M (USB_NOTIALLDMAWRIT_V << USB_NOTIALLDMAWRIT_S)
  8650. #define USB_NOTIALLDMAWRIT_V 0x00000001
  8651. #define USB_NOTIALLDMAWRIT_S 22
  8652. /** USB_AHBSINGLE : R/W; bitpos: [23]; default: 0;
  8653. * AHB Single Support (AHBSingle) This bit when programmed supports Single transfers
  8654. * for the remaining data in a transfer when the core is operating in DMA mode
  8655. * 1'b0: The remaining data in the transfer is sent using INCR burst size
  8656. * 1'b1: The remaining data in the transfer is sent using Single burst size
  8657. */
  8658. #define USB_AHBSINGLE (BIT(23))
  8659. #define USB_AHBSINGLE_M (USB_AHBSINGLE_V << USB_AHBSINGLE_S)
  8660. #define USB_AHBSINGLE_V 0x00000001
  8661. #define USB_AHBSINGLE_S 23
  8662. /** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0;
  8663. * Invert Descriptor Endianess
  8664. * 1'b0: Descriptor Endianness is same as AHB Master Endianness
  8665. * 1'b1:Invert Descriptor Endianess according to AHB Master endianness
  8666. */
  8667. #define USB_INVDESCENDIANESS (BIT(24))
  8668. #define USB_INVDESCENDIANESS_M (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S)
  8669. #define USB_INVDESCENDIANESS_V 0x00000001
  8670. #define USB_INVDESCENDIANESS_S 24
  8671. /** USB_GUSBCFG_REG register
  8672. * USB Configuration Register
  8673. */
  8674. #define USB_GUSBCFG_REG (SOC_DPORT_USB_BASE + 0xc)
  8675. /** USB_TOUTCAL : R/W; bitpos: [3:0]; default: 0;
  8676. * FS Timeout Calibration
  8677. */
  8678. #define USB_TOUTCAL 0x00000007
  8679. #define USB_TOUTCAL_M (USB_TOUTCAL_V << USB_TOUTCAL_S)
  8680. #define USB_TOUTCAL_V 0x00000007
  8681. #define USB_TOUTCAL_S 0
  8682. /** USB_PHYIF : R/W; bitpos: [3]; default: 0;
  8683. * The application uses this bit to configure the core to support a
  8684. * UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is
  8685. * chosen, this must be Set to 8-bit mode
  8686. * 1'b0: 8 bits
  8687. * 1'b1: 16 bits
  8688. */
  8689. #define USB_PHYIF (BIT(3))
  8690. #define USB_PHYIF_M (USB_PHYIF_V << USB_PHYIF_S)
  8691. #define USB_PHYIF_V 0x00000001
  8692. #define USB_PHYIF_S 3
  8693. /** USB_ULPI_UTMI_SEL : RO; bitpos: [4]; default: 0;
  8694. * 1'b0: UTMI+ Interface
  8695. * 1'b1: ULPI Interface
  8696. */
  8697. #define USB_ULPI_UTMI_SEL (BIT(4))
  8698. #define USB_ULPI_UTMI_SEL_M (USB_ULPI_UTMI_SEL_V << USB_ULPI_UTMI_SEL_S)
  8699. #define USB_ULPI_UTMI_SEL_V 0x00000001
  8700. #define USB_ULPI_UTMI_SEL_S 4
  8701. /** USB_FSINTF : R/W; bitpos: [5]; default: 0;
  8702. * 1'b0: 6-pin unidirectional full-speed serial interface
  8703. * 1'b1: 3-pin bidirectional full-speed serial interface
  8704. */
  8705. #define USB_FSINTF (BIT(5))
  8706. #define USB_FSINTF_M (USB_FSINTF_V << USB_FSINTF_S)
  8707. #define USB_FSINTF_V 0x00000001
  8708. #define USB_FSINTF_S 5
  8709. /** USB_PHYSEL : RO; bitpos: [6]; default: 1;
  8710. * 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
  8711. * 1'b1: USB 1.1 full-speed serial transceiver
  8712. */
  8713. #define USB_PHYSEL (BIT(6))
  8714. #define USB_PHYSEL_M (USB_PHYSEL_V << USB_PHYSEL_S)
  8715. #define USB_PHYSEL_V 0x00000001
  8716. #define USB_PHYSEL_S 6
  8717. /** USB_SRPCAP : R/W; bitpos: [8]; default: 0;
  8718. * 1'b0: SRP capability is not enabled
  8719. * 1'b1: SRP capability is enabled
  8720. */
  8721. #define USB_SRPCAP (BIT(8))
  8722. #define USB_SRPCAP_M (USB_SRPCAP_V << USB_SRPCAP_S)
  8723. #define USB_SRPCAP_V 0x00000001
  8724. #define USB_SRPCAP_S 8
  8725. /** USB_HNPCAP : R/W; bitpos: [9]; default: 0;
  8726. * 1'b0: HNP capability is not enabled
  8727. * 1'b1: HNP capability is enabled
  8728. */
  8729. #define USB_HNPCAP (BIT(9))
  8730. #define USB_HNPCAP_M (USB_HNPCAP_V << USB_HNPCAP_S)
  8731. #define USB_HNPCAP_V 0x00000001
  8732. #define USB_HNPCAP_S 9
  8733. /** USB_USBTRDTIM : R/W; bitpos: [14:10]; default: 5;
  8734. * 4'h5: When the MAC interface is 16-bit UTMI+
  8735. * 4'h9: When the MAC interface is 8-bit UTMI+
  8736. */
  8737. #define USB_USBTRDTIM 0x0000000F
  8738. #define USB_USBTRDTIM_M (USB_USBTRDTIM_V << USB_USBTRDTIM_S)
  8739. #define USB_USBTRDTIM_V 0x0000000F
  8740. #define USB_USBTRDTIM_S 10
  8741. /** USB_TERMSELDLPULSE : R/W; bitpos: [22]; default: 0;
  8742. * TermSel DLine Pulsing Selection
  8743. * 1'b0: Data line pulsing using utmi_txvalid (Default)
  8744. * 1'b1: Data line pulsing using utmi_termsel
  8745. */
  8746. #define USB_TERMSELDLPULSE (BIT(22))
  8747. #define USB_TERMSELDLPULSE_M (USB_TERMSELDLPULSE_V << USB_TERMSELDLPULSE_S)
  8748. #define USB_TERMSELDLPULSE_V 0x00000001
  8749. #define USB_TERMSELDLPULSE_S 22
  8750. /** USB_TXENDDELAY : R/W; bitpos: [28]; default: 0;
  8751. * 1'b0 : Normal Mode
  8752. * 1'b1 : Tx End delay
  8753. */
  8754. #define USB_TXENDDELAY (BIT(28))
  8755. #define USB_TXENDDELAY_M (USB_TXENDDELAY_V << USB_TXENDDELAY_S)
  8756. #define USB_TXENDDELAY_V 0x00000001
  8757. #define USB_TXENDDELAY_S 28
  8758. /** USB_FORCEHSTMODE : R/W; bitpos: [29]; default: 0;
  8759. * 1'b0 : Normal Mode
  8760. * 1'b1 : Force Host Mode
  8761. */
  8762. #define USB_FORCEHSTMODE (BIT(29))
  8763. #define USB_FORCEHSTMODE_M (USB_FORCEHSTMODE_V << USB_FORCEHSTMODE_S)
  8764. #define USB_FORCEHSTMODE_V 0x00000001
  8765. #define USB_FORCEHSTMODE_S 29
  8766. /** USB_FORCEDEVMODE : R/W; bitpos: [30]; default: 0;
  8767. * 1'b0 : Normal Mode
  8768. * 1'b1 : Force Device Mode
  8769. */
  8770. #define USB_FORCEDEVMODE (BIT(30))
  8771. #define USB_FORCEDEVMODE_M (USB_FORCEDEVMODE_V << USB_FORCEDEVMODE_S)
  8772. #define USB_FORCEDEVMODE_V 0x00000001
  8773. #define USB_FORCEDEVMODE_S 30
  8774. /** USB_CORRUPTTXPKT : R/W; bitpos: [31]; default: 0;
  8775. * This bit is for debug purposes only. Never Set this bit to 1. The application
  8776. * should always write 1'b0 to this bit
  8777. * 1'b0:Normal Mode
  8778. * 1'b1:Debug Mode
  8779. */
  8780. #define USB_CORRUPTTXPKT (BIT(31))
  8781. #define USB_CORRUPTTXPKT_M (USB_CORRUPTTXPKT_V << USB_CORRUPTTXPKT_S)
  8782. #define USB_CORRUPTTXPKT_V 0x00000001
  8783. #define USB_CORRUPTTXPKT_S 31
  8784. /** USB_GRSTCTL_REG register
  8785. * Reset Register
  8786. */
  8787. #define USB_GRSTCTL_REG (SOC_DPORT_USB_BASE + 0x10)
  8788. /** USB_CSFTRST : R_WS_SC; bitpos: [0]; default: 0;
  8789. * Core Soft Reset
  8790. */
  8791. #define USB_CSFTRST (BIT(0))
  8792. #define USB_CSFTRST_M (USB_CSFTRST_V << USB_CSFTRST_S)
  8793. #define USB_CSFTRST_V 0x00000001
  8794. #define USB_CSFTRST_S 0
  8795. /** USB_PIUFSSFTRST : R_WS_SC; bitpos: [1]; default: 0;
  8796. * 1'b0: No Reset
  8797. * 1'b1:PIU FS Dedicated Controller Soft Reset
  8798. */
  8799. #define USB_PIUFSSFTRST (BIT(1))
  8800. #define USB_PIUFSSFTRST_M (USB_PIUFSSFTRST_V << USB_PIUFSSFTRST_S)
  8801. #define USB_PIUFSSFTRST_V 0x00000001
  8802. #define USB_PIUFSSFTRST_S 1
  8803. /** USB_FRMCNTRRST : R/W1S; bitpos: [2]; default: 0;
  8804. * Host only. Host Frame Counter Reset.The application writes this bit to reset the
  8805. * (micro)Frame number counter inside the core. When the (micro)Frame counter is
  8806. * reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0
  8807. */
  8808. #define USB_FRMCNTRRST (BIT(2))
  8809. #define USB_FRMCNTRRST_M (USB_FRMCNTRRST_V << USB_FRMCNTRRST_S)
  8810. #define USB_FRMCNTRRST_V 0x00000001
  8811. #define USB_FRMCNTRRST_S 2
  8812. /** USB_RXFFLSH : R/W1S; bitpos: [4]; default: 0;
  8813. * RxFIFO Flush. The application can flush the entire RxFIFO using this bit, but must
  8814. * first ensure that the core is not in the middle of a transaction.The application
  8815. * must only write to this bit after checking that the controller is neither reading
  8816. * from the RxFIFO nor writing to the RxFIFO
  8817. * 1'b0:Does not flush the entire RxFIFO
  8818. * 1'b1:flushes the entire RxFIFO
  8819. */
  8820. #define USB_RXFFLSH (BIT(4))
  8821. #define USB_RXFFLSH_M (USB_RXFFLSH_V << USB_RXFFLSH_S)
  8822. #define USB_RXFFLSH_V 0x00000001
  8823. #define USB_RXFFLSH_S 4
  8824. /** USB_TXFFLSH : R/W1S; bitpos: [5]; default: 0;
  8825. * TxFIFO Flush.This bit selectively flushes a single or all transmit FIFOs, but
  8826. * cannot do so If the core is in the midst of a transaction.The application must
  8827. * write this bit only after checking that the core is neither writing to the TxFIFO
  8828. * nor reading from the TxFIFO.
  8829. */
  8830. #define USB_TXFFLSH (BIT(5))
  8831. #define USB_TXFFLSH_M (USB_TXFFLSH_V << USB_TXFFLSH_S)
  8832. #define USB_TXFFLSH_V 0x00000001
  8833. #define USB_TXFFLSH_S 5
  8834. /** USB_TXFNUM : R/W; bitpos: [11:6]; default: 0;
  8835. * TxFIFO Number.This is the FIFO number that must be flushed using the TxFIFO Flush
  8836. * bit. This field must not be changed until the core clears the TxFIFO Flush bit
  8837. */
  8838. #define USB_TXFNUM 0x0000001F
  8839. #define USB_TXFNUM_M (USB_TXFNUM_V << USB_TXFNUM_S)
  8840. #define USB_TXFNUM_V 0x0000001F
  8841. #define USB_TXFNUM_S 6
  8842. /** USB_DMAREQ : RO; bitpos: [30]; default: 0;
  8843. * DMA Request Signal
  8844. * 1'b0:No DMA request
  8845. * 1'b1:DMA request is in progress
  8846. */
  8847. #define USB_DMAREQ (BIT(30))
  8848. #define USB_DMAREQ_M (USB_DMAREQ_V << USB_DMAREQ_S)
  8849. #define USB_DMAREQ_V 0x00000001
  8850. #define USB_DMAREQ_S 30
  8851. /** USB_AHBIDLE : RO; bitpos: [31]; default: 0;
  8852. * AHB Master Idle
  8853. * 1'b0:Not Idle
  8854. * 1'b1:AHB Master Idle
  8855. */
  8856. #define USB_AHBIDLE (BIT(31))
  8857. #define USB_AHBIDLE_M (USB_AHBIDLE_V << USB_AHBIDLE_S)
  8858. #define USB_AHBIDLE_V 0x00000001
  8859. #define USB_AHBIDLE_S 31
  8860. /** USB_GRXFSIZ_REG register
  8861. * Receive FIFO Size Register
  8862. */
  8863. #define USB_GRXFSIZ_REG (SOC_DPORT_USB_BASE + 0x24)
  8864. /** USB_RXFDEP : R/W; bitpos: [16:0]; default: 256;
  8865. * RxFIFO Depth.This value is in terms of 32-bit words.Minimum value is 16,Maximum
  8866. * value is 32,768
  8867. */
  8868. #define USB_RXFDEP 0x0000FFFF
  8869. #define USB_RXFDEP_M (USB_RXFDEP_V << USB_RXFDEP_S)
  8870. #define USB_RXFDEP_V 0x0000FFFF
  8871. #define USB_RXFDEP_S 0
  8872. /** USB_GNPTXFSIZ_REG register
  8873. * Non-periodic Transmit FIFO Size Register
  8874. */
  8875. #define USB_GNPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x28)
  8876. /** USB_NPTXFSTADDR : R/W; bitpos: [16:0]; default: 256;
  8877. * The NPTxFStAddr field description is valid only for host mode.This field contains
  8878. * the memory start address for Non-periodic Transmit FIFO RAM.
  8879. */
  8880. #define USB_NPTXFSTADDR 0x0000FFFF
  8881. #define USB_NPTXFSTADDR_M (USB_NPTXFSTADDR_V << USB_NPTXFSTADDR_S)
  8882. #define USB_NPTXFSTADDR_V 0x0000FFFF
  8883. #define USB_NPTXFSTADDR_S 0
  8884. /** USB_NPTXFDEP : R/W; bitpos: [32:16]; default: 256;
  8885. * The NPTxFDep field description is valid only for host mode or device mode when
  8886. * OTG_EN_DED_TX_FIFO=0.Minimum value is 16,Maximum value is 32,768.
  8887. */
  8888. #define USB_NPTXFDEP 0x0000FFFF
  8889. #define USB_NPTXFDEP_M (USB_NPTXFDEP_V << USB_NPTXFDEP_S)
  8890. #define USB_NPTXFDEP_V 0x0000FFFF
  8891. #define USB_NPTXFDEP_S 16
  8892. /** USB_GNPTXSTS_REG register
  8893. * Non-periodic Transmit FIFO/Queue Status Register
  8894. */
  8895. #define USB_GNPTXSTS_REG (SOC_DPORT_USB_BASE + 0x2c)
  8896. /** USB_NPTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256;
  8897. * Non-periodic TxFIFO Space Avail.Indicates the amount of free space available in the
  8898. * Non-periodic TxFIFO.Values are in terms of 32-bit words.
  8899. */
  8900. #define USB_NPTXFSPCAVAIL 0x0000FFFF
  8901. #define USB_NPTXFSPCAVAIL_M (USB_NPTXFSPCAVAIL_V << USB_NPTXFSPCAVAIL_S)
  8902. #define USB_NPTXFSPCAVAIL_V 0x0000FFFF
  8903. #define USB_NPTXFSPCAVAIL_S 0
  8904. /** USB_NPTXQSPCAVAIL : RO; bitpos: [20:16]; default: 4;
  8905. * Non-periodic Transmit Request Queue Space Available.Indicates the amount of free
  8906. * space available in the Non-periodic Transmit Request Queue. This queue holds both
  8907. * IN and OUT requests in Host mode. Device mode has only IN requests.
  8908. */
  8909. #define USB_NPTXQSPCAVAIL 0x0000000F
  8910. #define USB_NPTXQSPCAVAIL_M (USB_NPTXQSPCAVAIL_V << USB_NPTXQSPCAVAIL_S)
  8911. #define USB_NPTXQSPCAVAIL_V 0x0000000F
  8912. #define USB_NPTXQSPCAVAIL_S 16
  8913. /** USB_NPTXQTOP : RO; bitpos: [31:24]; default: 0;
  8914. * Top of the Non-periodic Transmit Request Queue.
  8915. * Bits [30:27]: Channel/endpoint number.
  8916. * Bits [26:25]: 2'b00: IN/OUT token 2'b01: Zero-length transmit packet (device
  8917. * IN/host OUT) 2'b10: PING/CSPLIT token 2'b11: Channel halt command.
  8918. * Bit [24]: Terminate (last Entry for selected channel/endpoint).
  8919. */
  8920. #define USB_NPTXQTOP 0x0000007F
  8921. #define USB_NPTXQTOP_M (USB_NPTXQTOP_V << USB_NPTXQTOP_S)
  8922. #define USB_NPTXQTOP_V 0x0000007F
  8923. #define USB_NPTXQTOP_S 24
  8924. /** USB_HCTSIZ0_REG register
  8925. * Host Channel 0Transfer Size Register
  8926. */
  8927. #define USB_HCTSIZ0_REG (SOC_DPORT_USB_BASE + 0x510)
  8928. /** USB_H_XFERSIZE0 : R/W; bitpos: [19:0]; default: 0;
  8929. * Non-Scatter/Gather DMA Mode: Transfer Size.
  8930. * Scatter/Gather DMA Mode:
  8931. * [18:16]: Reserved
  8932. * [15:8]: NTD (Number of Transfer Descriptors)
  8933. */
  8934. #define USB_H_XFERSIZE0 0x0007FFFF
  8935. #define USB_H_XFERSIZE0_M (USB_H_XFERSIZE0_V << USB_H_XFERSIZE0_S)
  8936. #define USB_H_XFERSIZE0_V 0x0007FFFF
  8937. #define USB_H_XFERSIZE0_S 0
  8938. /** USB_H_PKTCNT0 : R/W; bitpos: [29:19]; default: 0;
  8939. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  8940. * application with the expected number of packets to be transmitted (OUT) or received
  8941. * (IN).
  8942. * Scatter/Gather DMA Mode: Reserved.
  8943. */
  8944. #define USB_H_PKTCNT0 0x000003FF
  8945. #define USB_H_PKTCNT0_M (USB_H_PKTCNT0_V << USB_H_PKTCNT0_S)
  8946. #define USB_H_PKTCNT0_V 0x000003FF
  8947. #define USB_H_PKTCNT0_S 19
  8948. /** USB_H_PID0 : R/W; bitpos: [31:29]; default: 0;
  8949. * 2'b00: DATA0
  8950. * 2'b01: DATA2
  8951. * 2'b10: DATA1
  8952. * 2'b11: MDATA (non-control)/SETUP (control)
  8953. */
  8954. #define USB_H_PID0 0x00000003
  8955. #define USB_H_PID0_M (USB_H_PID0_V << USB_H_PID0_S)
  8956. #define USB_H_PID0_V 0x00000003
  8957. #define USB_H_PID0_S 29
  8958. /** USB_H_DOPNG0 : R/W; bitpos: [31]; default: 0;
  8959. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  8960. * to do PING protocol
  8961. * 1'b0: No ping protocol
  8962. * 1'b1: Ping protocol
  8963. */
  8964. #define USB_H_DOPNG0 (BIT(31))
  8965. #define USB_H_DOPNG0_M (USB_H_DOPNG0_V << USB_H_DOPNG0_S)
  8966. #define USB_H_DOPNG0_V 0x00000001
  8967. #define USB_H_DOPNG0_S 31
  8968. /** USB_HCTSIZ1_REG register
  8969. * Host Channel 1Transfer Size Register
  8970. */
  8971. #define USB_HCTSIZ1_REG (SOC_DPORT_USB_BASE + 0x530)
  8972. /** USB_H_XFERSIZE1 : R/W; bitpos: [19:0]; default: 0;
  8973. * Non-Scatter/Gather DMA Mode: Transfer Size.
  8974. * Scatter/Gather DMA Mode:
  8975. * [18:16]: Reserved
  8976. * [15:8]: NTD (Number of Transfer Descriptors)
  8977. */
  8978. #define USB_H_XFERSIZE1 0x0007FFFF
  8979. #define USB_H_XFERSIZE1_M (USB_H_XFERSIZE1_V << USB_H_XFERSIZE1_S)
  8980. #define USB_H_XFERSIZE1_V 0x0007FFFF
  8981. #define USB_H_XFERSIZE1_S 0
  8982. /** USB_H_PKTCNT1 : R/W; bitpos: [29:19]; default: 0;
  8983. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  8984. * application with the expected number of packets to be transmitted (OUT) or received
  8985. * (IN).
  8986. * Scatter/Gather DMA Mode: Reserved.
  8987. */
  8988. #define USB_H_PKTCNT1 0x000003FF
  8989. #define USB_H_PKTCNT1_M (USB_H_PKTCNT1_V << USB_H_PKTCNT1_S)
  8990. #define USB_H_PKTCNT1_V 0x000003FF
  8991. #define USB_H_PKTCNT1_S 19
  8992. /** USB_H_PID1 : R/W; bitpos: [31:29]; default: 0;
  8993. * 2'b00: DATA0
  8994. * 2'b01: DATA2
  8995. * 2'b10: DATA1
  8996. * 2'b11: MDATA (non-control)/SETUP (control)
  8997. */
  8998. #define USB_H_PID1 0x00000003
  8999. #define USB_H_PID1_M (USB_H_PID1_V << USB_H_PID1_S)
  9000. #define USB_H_PID1_V 0x00000003
  9001. #define USB_H_PID1_S 29
  9002. /** USB_H_DOPNG1 : R/W; bitpos: [31]; default: 0;
  9003. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9004. * to do PING protocol
  9005. * 1'b0: No ping protocol
  9006. * 1'b1: Ping protocol
  9007. */
  9008. #define USB_H_DOPNG1 (BIT(31))
  9009. #define USB_H_DOPNG1_M (USB_H_DOPNG1_V << USB_H_DOPNG1_S)
  9010. #define USB_H_DOPNG1_V 0x00000001
  9011. #define USB_H_DOPNG1_S 31
  9012. /** USB_HCTSIZ2_REG register
  9013. * Host Channel 2Transfer Size Register
  9014. */
  9015. #define USB_HCTSIZ2_REG (SOC_DPORT_USB_BASE + 0x550)
  9016. /** USB_H_XFERSIZE2 : R/W; bitpos: [19:0]; default: 0;
  9017. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9018. * Scatter/Gather DMA Mode:
  9019. * [18:16]: Reserved
  9020. * [15:8]: NTD (Number of Transfer Descriptors)
  9021. */
  9022. #define USB_H_XFERSIZE2 0x0007FFFF
  9023. #define USB_H_XFERSIZE2_M (USB_H_XFERSIZE2_V << USB_H_XFERSIZE2_S)
  9024. #define USB_H_XFERSIZE2_V 0x0007FFFF
  9025. #define USB_H_XFERSIZE2_S 0
  9026. /** USB_H_PKTCNT2 : R/W; bitpos: [29:19]; default: 0;
  9027. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9028. * application with the expected number of packets to be transmitted (OUT) or received
  9029. * (IN).
  9030. * Scatter/Gather DMA Mode: Reserved.
  9031. */
  9032. #define USB_H_PKTCNT2 0x000003FF
  9033. #define USB_H_PKTCNT2_M (USB_H_PKTCNT2_V << USB_H_PKTCNT2_S)
  9034. #define USB_H_PKTCNT2_V 0x000003FF
  9035. #define USB_H_PKTCNT2_S 19
  9036. /** USB_H_PID2 : R/W; bitpos: [31:29]; default: 0;
  9037. * 2'b00: DATA0
  9038. * 2'b01: DATA2
  9039. * 2'b10: DATA1
  9040. * 2'b11: MDATA (non-control)/SETUP (control)
  9041. */
  9042. #define USB_H_PID2 0x00000003
  9043. #define USB_H_PID2_M (USB_H_PID2_V << USB_H_PID2_S)
  9044. #define USB_H_PID2_V 0x00000003
  9045. #define USB_H_PID2_S 29
  9046. /** USB_H_DOPNG2 : R/W; bitpos: [31]; default: 0;
  9047. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9048. * to do PING protocol
  9049. * 1'b0: No ping protocol
  9050. * 1'b1: Ping protocol
  9051. */
  9052. #define USB_H_DOPNG2 (BIT(31))
  9053. #define USB_H_DOPNG2_M (USB_H_DOPNG2_V << USB_H_DOPNG2_S)
  9054. #define USB_H_DOPNG2_V 0x00000001
  9055. #define USB_H_DOPNG2_S 31
  9056. /** USB_HCTSIZ3_REG register
  9057. * Host Channel 3Transfer Size Register
  9058. */
  9059. #define USB_HCTSIZ3_REG (SOC_DPORT_USB_BASE + 0x570)
  9060. /** USB_H_XFERSIZE3 : R/W; bitpos: [19:0]; default: 0;
  9061. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9062. * Scatter/Gather DMA Mode:
  9063. * [18:16]: Reserved
  9064. * [15:8]: NTD (Number of Transfer Descriptors)
  9065. */
  9066. #define USB_H_XFERSIZE3 0x0007FFFF
  9067. #define USB_H_XFERSIZE3_M (USB_H_XFERSIZE3_V << USB_H_XFERSIZE3_S)
  9068. #define USB_H_XFERSIZE3_V 0x0007FFFF
  9069. #define USB_H_XFERSIZE3_S 0
  9070. /** USB_H_PKTCNT3 : R/W; bitpos: [29:19]; default: 0;
  9071. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9072. * application with the expected number of packets to be transmitted (OUT) or received
  9073. * (IN).
  9074. * Scatter/Gather DMA Mode: Reserved.
  9075. */
  9076. #define USB_H_PKTCNT3 0x000003FF
  9077. #define USB_H_PKTCNT3_M (USB_H_PKTCNT3_V << USB_H_PKTCNT3_S)
  9078. #define USB_H_PKTCNT3_V 0x000003FF
  9079. #define USB_H_PKTCNT3_S 19
  9080. /** USB_H_PID3 : R/W; bitpos: [31:29]; default: 0;
  9081. * 2'b00: DATA0
  9082. * 2'b01: DATA2
  9083. * 2'b10: DATA1
  9084. * 2'b11: MDATA (non-control)/SETUP (control)
  9085. */
  9086. #define USB_H_PID3 0x00000003
  9087. #define USB_H_PID3_M (USB_H_PID3_V << USB_H_PID3_S)
  9088. #define USB_H_PID3_V 0x00000003
  9089. #define USB_H_PID3_S 29
  9090. /** USB_H_DOPNG3 : R/W; bitpos: [31]; default: 0;
  9091. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9092. * to do PING protocol
  9093. * 1'b0: No ping protocol
  9094. * 1'b1: Ping protocol
  9095. */
  9096. #define USB_H_DOPNG3 (BIT(31))
  9097. #define USB_H_DOPNG3_M (USB_H_DOPNG3_V << USB_H_DOPNG3_S)
  9098. #define USB_H_DOPNG3_V 0x00000001
  9099. #define USB_H_DOPNG3_S 31
  9100. /** USB_HCTSIZ4_REG register
  9101. * Host Channel 4Transfer Size Register
  9102. */
  9103. #define USB_HCTSIZ4_REG (SOC_DPORT_USB_BASE + 0x590)
  9104. /** USB_H_XFERSIZE4 : R/W; bitpos: [19:0]; default: 0;
  9105. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9106. * Scatter/Gather DMA Mode:
  9107. * [18:16]: Reserved
  9108. * [15:8]: NTD (Number of Transfer Descriptors)
  9109. */
  9110. #define USB_H_XFERSIZE4 0x0007FFFF
  9111. #define USB_H_XFERSIZE4_M (USB_H_XFERSIZE4_V << USB_H_XFERSIZE4_S)
  9112. #define USB_H_XFERSIZE4_V 0x0007FFFF
  9113. #define USB_H_XFERSIZE4_S 0
  9114. /** USB_H_PKTCNT4 : R/W; bitpos: [29:19]; default: 0;
  9115. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9116. * application with the expected number of packets to be transmitted (OUT) or received
  9117. * (IN).
  9118. * Scatter/Gather DMA Mode: Reserved.
  9119. */
  9120. #define USB_H_PKTCNT4 0x000003FF
  9121. #define USB_H_PKTCNT4_M (USB_H_PKTCNT4_V << USB_H_PKTCNT4_S)
  9122. #define USB_H_PKTCNT4_V 0x000003FF
  9123. #define USB_H_PKTCNT4_S 19
  9124. /** USB_H_PID4 : R/W; bitpos: [31:29]; default: 0;
  9125. * 2'b00: DATA0
  9126. * 2'b01: DATA2
  9127. * 2'b10: DATA1
  9128. * 2'b11: MDATA (non-control)/SETUP (control)
  9129. */
  9130. #define USB_H_PID4 0x00000003
  9131. #define USB_H_PID4_M (USB_H_PID4_V << USB_H_PID4_S)
  9132. #define USB_H_PID4_V 0x00000003
  9133. #define USB_H_PID4_S 29
  9134. /** USB_H_DOPNG4 : R/W; bitpos: [31]; default: 0;
  9135. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9136. * to do PING protocol
  9137. * 1'b0: No ping protocol
  9138. * 1'b1: Ping protocol
  9139. */
  9140. #define USB_H_DOPNG4 (BIT(31))
  9141. #define USB_H_DOPNG4_M (USB_H_DOPNG4_V << USB_H_DOPNG4_S)
  9142. #define USB_H_DOPNG4_V 0x00000001
  9143. #define USB_H_DOPNG4_S 31
  9144. /** USB_HCTSIZ5_REG register
  9145. * Host Channel 5Transfer Size Register
  9146. */
  9147. #define USB_HCTSIZ5_REG (SOC_DPORT_USB_BASE + 0x5b0)
  9148. /** USB_H_XFERSIZE5 : R/W; bitpos: [19:0]; default: 0;
  9149. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9150. * Scatter/Gather DMA Mode:
  9151. * [18:16]: Reserved
  9152. * [15:8]: NTD (Number of Transfer Descriptors)
  9153. */
  9154. #define USB_H_XFERSIZE5 0x0007FFFF
  9155. #define USB_H_XFERSIZE5_M (USB_H_XFERSIZE5_V << USB_H_XFERSIZE5_S)
  9156. #define USB_H_XFERSIZE5_V 0x0007FFFF
  9157. #define USB_H_XFERSIZE5_S 0
  9158. /** USB_H_PKTCNT5 : R/W; bitpos: [29:19]; default: 0;
  9159. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9160. * application with the expected number of packets to be transmitted (OUT) or received
  9161. * (IN).
  9162. * Scatter/Gather DMA Mode: Reserved.
  9163. */
  9164. #define USB_H_PKTCNT5 0x000003FF
  9165. #define USB_H_PKTCNT5_M (USB_H_PKTCNT5_V << USB_H_PKTCNT5_S)
  9166. #define USB_H_PKTCNT5_V 0x000003FF
  9167. #define USB_H_PKTCNT5_S 19
  9168. /** USB_H_PID5 : R/W; bitpos: [31:29]; default: 0;
  9169. * 2'b00: DATA0
  9170. * 2'b01: DATA2
  9171. * 2'b10: DATA1
  9172. * 2'b11: MDATA (non-control)/SETUP (control)
  9173. */
  9174. #define USB_H_PID5 0x00000003
  9175. #define USB_H_PID5_M (USB_H_PID5_V << USB_H_PID5_S)
  9176. #define USB_H_PID5_V 0x00000003
  9177. #define USB_H_PID5_S 29
  9178. /** USB_H_DOPNG5 : R/W; bitpos: [31]; default: 0;
  9179. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9180. * to do PING protocol
  9181. * 1'b0: No ping protocol
  9182. * 1'b1: Ping protocol
  9183. */
  9184. #define USB_H_DOPNG5 (BIT(31))
  9185. #define USB_H_DOPNG5_M (USB_H_DOPNG5_V << USB_H_DOPNG5_S)
  9186. #define USB_H_DOPNG5_V 0x00000001
  9187. #define USB_H_DOPNG5_S 31
  9188. /** USB_HCTSIZ6_REG register
  9189. * Host Channel 6Transfer Size Register
  9190. */
  9191. #define USB_HCTSIZ6_REG (SOC_DPORT_USB_BASE + 0x5d0)
  9192. /** USB_H_XFERSIZE6 : R/W; bitpos: [19:0]; default: 0;
  9193. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9194. * Scatter/Gather DMA Mode:
  9195. * [18:16]: Reserved
  9196. * [15:8]: NTD (Number of Transfer Descriptors)
  9197. */
  9198. #define USB_H_XFERSIZE6 0x0007FFFF
  9199. #define USB_H_XFERSIZE6_M (USB_H_XFERSIZE6_V << USB_H_XFERSIZE6_S)
  9200. #define USB_H_XFERSIZE6_V 0x0007FFFF
  9201. #define USB_H_XFERSIZE6_S 0
  9202. /** USB_H_PKTCNT6 : R/W; bitpos: [29:19]; default: 0;
  9203. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9204. * application with the expected number of packets to be transmitted (OUT) or received
  9205. * (IN).
  9206. * Scatter/Gather DMA Mode: Reserved.
  9207. */
  9208. #define USB_H_PKTCNT6 0x000003FF
  9209. #define USB_H_PKTCNT6_M (USB_H_PKTCNT6_V << USB_H_PKTCNT6_S)
  9210. #define USB_H_PKTCNT6_V 0x000003FF
  9211. #define USB_H_PKTCNT6_S 19
  9212. /** USB_H_PID6 : R/W; bitpos: [31:29]; default: 0;
  9213. * 2'b00: DATA0
  9214. * 2'b01: DATA2
  9215. * 2'b10: DATA1
  9216. * 2'b11: MDATA (non-control)/SETUP (control)
  9217. */
  9218. #define USB_H_PID6 0x00000003
  9219. #define USB_H_PID6_M (USB_H_PID6_V << USB_H_PID6_S)
  9220. #define USB_H_PID6_V 0x00000003
  9221. #define USB_H_PID6_S 29
  9222. /** USB_H_DOPNG6 : R/W; bitpos: [31]; default: 0;
  9223. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9224. * to do PING protocol
  9225. * 1'b0: No ping protocol
  9226. * 1'b1: Ping protocol
  9227. */
  9228. #define USB_H_DOPNG6 (BIT(31))
  9229. #define USB_H_DOPNG6_M (USB_H_DOPNG6_V << USB_H_DOPNG6_S)
  9230. #define USB_H_DOPNG6_V 0x00000001
  9231. #define USB_H_DOPNG6_S 31
  9232. /** USB_HCTSIZ7_REG register
  9233. * Host Channel 7Transfer Size Register
  9234. */
  9235. #define USB_HCTSIZ7_REG (SOC_DPORT_USB_BASE + 0x5f0)
  9236. /** USB_H_XFERSIZE7 : R/W; bitpos: [19:0]; default: 0;
  9237. * Non-Scatter/Gather DMA Mode: Transfer Size.
  9238. * Scatter/Gather DMA Mode:
  9239. * [18:16]: Reserved
  9240. * [15:8]: NTD (Number of Transfer Descriptors)
  9241. */
  9242. #define USB_H_XFERSIZE7 0x0007FFFF
  9243. #define USB_H_XFERSIZE7_M (USB_H_XFERSIZE7_V << USB_H_XFERSIZE7_S)
  9244. #define USB_H_XFERSIZE7_V 0x0007FFFF
  9245. #define USB_H_XFERSIZE7_S 0
  9246. /** USB_H_PKTCNT7 : R/W; bitpos: [29:19]; default: 0;
  9247. * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the
  9248. * application with the expected number of packets to be transmitted (OUT) or received
  9249. * (IN).
  9250. * Scatter/Gather DMA Mode: Reserved.
  9251. */
  9252. #define USB_H_PKTCNT7 0x000003FF
  9253. #define USB_H_PKTCNT7_M (USB_H_PKTCNT7_V << USB_H_PKTCNT7_S)
  9254. #define USB_H_PKTCNT7_V 0x000003FF
  9255. #define USB_H_PKTCNT7_S 19
  9256. /** USB_H_PID7 : R/W; bitpos: [31:29]; default: 0;
  9257. * 2'b00: DATA0
  9258. * 2'b01: DATA2
  9259. * 2'b10: DATA1
  9260. * 2'b11: MDATA (non-control)/SETUP (control)
  9261. */
  9262. #define USB_H_PID7 0x00000003
  9263. #define USB_H_PID7_M (USB_H_PID7_V << USB_H_PID7_S)
  9264. #define USB_H_PID7_V 0x00000003
  9265. #define USB_H_PID7_S 29
  9266. /** USB_H_DOPNG7 : R/W; bitpos: [31]; default: 0;
  9267. * This bit is used only for OUT transfers. Setting this field to 1 directs the host
  9268. * to do PING protocol
  9269. * 1'b0: No ping protocol
  9270. * 1'b1: Ping protocol
  9271. */
  9272. #define USB_H_DOPNG7 (BIT(31))
  9273. #define USB_H_DOPNG7_M (USB_H_DOPNG7_V << USB_H_DOPNG7_S)
  9274. #define USB_H_DOPNG7_V 0x00000001
  9275. #define USB_H_DOPNG7_S 31
  9276. /** Status registers */
  9277. /** USB_GRXSTSR_REG register
  9278. * Receive Status Debug Read Register
  9279. */
  9280. #define USB_GRXSTSR_REG (SOC_DPORT_USB_BASE + 0x1c)
  9281. /** USB_G_CHNUM : RO; bitpos: [4:0]; default: 0;
  9282. * Channel Number: Host only. Indicates the channel number to which the current
  9283. * received packet belongs.
  9284. * Endpoint Number: Device only Indicates the endpoint number to which the current
  9285. * received packet belongs
  9286. */
  9287. #define USB_G_CHNUM 0x0000000F
  9288. #define USB_G_CHNUM_M (USB_G_CHNUM_V << USB_G_CHNUM_S)
  9289. #define USB_G_CHNUM_V 0x0000000F
  9290. #define USB_G_CHNUM_S 0
  9291. /** USB_G_BCNT : RO; bitpos: [15:4]; default: 0;
  9292. * In host mode, indicates the byte count of the received IN data Packet
  9293. * In device mode, indicates the byte count of the received data packet
  9294. */
  9295. #define USB_G_BCNT 0x000007FF
  9296. #define USB_G_BCNT_M (USB_G_BCNT_V << USB_G_BCNT_S)
  9297. #define USB_G_BCNT_V 0x000007FF
  9298. #define USB_G_BCNT_S 4
  9299. /** USB_G_DPID : RO; bitpos: [17:15]; default: 0;
  9300. * Data PID
  9301. * 0x0 (DATA0): DATA0
  9302. * 0x2 (DATA1): DATA1
  9303. * 0x1 (DATA2): DATA2
  9304. * 0x3 (MDATA): MDATA
  9305. */
  9306. #define USB_G_DPID 0x00000003
  9307. #define USB_G_DPID_M (USB_G_DPID_V << USB_G_DPID_S)
  9308. #define USB_G_DPID_V 0x00000003
  9309. #define USB_G_DPID_S 15
  9310. /** USB_G_PKTSTS : RO; bitpos: [21:17]; default: 0;
  9311. * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt)
  9312. * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data received in
  9313. * device mode
  9314. * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device (triggers
  9315. * an interrupt)
  9316. * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt)
  9317. * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode
  9318. * 0x6 (DSETUPRX): SETUP data packet received in device mode
  9319. * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt)
  9320. */
  9321. #define USB_G_PKTSTS 0x0000000F
  9322. #define USB_G_PKTSTS_M (USB_G_PKTSTS_V << USB_G_PKTSTS_S)
  9323. #define USB_G_PKTSTS_V 0x0000000F
  9324. #define USB_G_PKTSTS_S 17
  9325. /** USB_G_FN : RO; bitpos: [25:21]; default: 0;
  9326. * This is the least significant 4 bits of the (micro)Frame number in which the packet
  9327. * is received on the USB. This field is supported only when isochronous OUT endpoints
  9328. * are supported
  9329. */
  9330. #define USB_G_FN 0x0000000F
  9331. #define USB_G_FN_M (USB_G_FN_V << USB_G_FN_S)
  9332. #define USB_G_FN_V 0x0000000F
  9333. #define USB_G_FN_S 21
  9334. /** USB_GRXSTSP_REG register
  9335. * Receive Status Read/Pop Register
  9336. */
  9337. #define USB_GRXSTSP_REG (SOC_DPORT_USB_BASE + 0x20)
  9338. /** USB_CHNUM : RO; bitpos: [4:0]; default: 0;
  9339. * Channel Number: Host only. Indicates the channel number to which the current
  9340. * received packet belongs.
  9341. * Endpoint Number: Device only Indicates the endpoint number to which the current
  9342. * received packet belongs
  9343. */
  9344. #define USB_CHNUM 0x0000000F
  9345. #define USB_CHNUM_M (USB_CHNUM_V << USB_CHNUM_S)
  9346. #define USB_CHNUM_V 0x0000000F
  9347. #define USB_CHNUM_S 0
  9348. /** USB_BCNT : RO; bitpos: [15:4]; default: 0;
  9349. * In host mode, indicates the byte count of the received IN data Packet
  9350. * In device mode, indicates the byte count of the received data packet
  9351. */
  9352. #define USB_BCNT 0x000007FF
  9353. #define USB_BCNT_M (USB_BCNT_V << USB_BCNT_S)
  9354. #define USB_BCNT_V 0x000007FF
  9355. #define USB_BCNT_S 4
  9356. /** USB_DPID : RO; bitpos: [17:15]; default: 0;
  9357. * Data PID
  9358. * 0x0 (DATA0): DATA0
  9359. * 0x2 (DATA1): DATA1
  9360. * 0x1 (DATA2): DATA2
  9361. * 0x3 (MDATA): MDATA
  9362. */
  9363. #define USB_DPID 0x00000003
  9364. #define USB_DPID_M (USB_DPID_V << USB_DPID_S)
  9365. #define USB_DPID_V 0x00000003
  9366. #define USB_DPID_S 15
  9367. /** USB_PKTSTS : RO; bitpos: [21:17]; default: 0;
  9368. * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt)
  9369. * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data packet received
  9370. * in device mode
  9371. * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device mode
  9372. * (triggers an interrupt)
  9373. * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt)
  9374. * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode
  9375. * 0x6 (DSETUPRX): SETUP data packet received in device mode
  9376. * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt)
  9377. */
  9378. #define USB_PKTSTS 0x0000000F
  9379. #define USB_PKTSTS_M (USB_PKTSTS_V << USB_PKTSTS_S)
  9380. #define USB_PKTSTS_V 0x0000000F
  9381. #define USB_PKTSTS_S 17
  9382. /** USB_FN : RO; bitpos: [25:21]; default: 0;
  9383. * This is the least significant 4 bits of the (micro)Frame number in which the packet
  9384. * is received on the USB. This field is supported only when isochronous OUT endpoints
  9385. * are supported
  9386. */
  9387. #define USB_FN 0x0000000F
  9388. #define USB_FN_M (USB_FN_V << USB_FN_S)
  9389. #define USB_FN_V 0x0000000F
  9390. #define USB_FN_S 21
  9391. /** USB_GSNPSID_REG register
  9392. * Synopsys ID Register
  9393. */
  9394. #define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40)
  9395. /** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482;
  9396. * ID register
  9397. */
  9398. #define USB_SYNOPSYSID 0xFFFFFFFF
  9399. #define USB_SYNOPSYSID_M (USB_SYNOPSYSID_V << USB_SYNOPSYSID_S)
  9400. #define USB_SYNOPSYSID_V 0xFFFFFFFF
  9401. #define USB_SYNOPSYSID_S 0
  9402. /** USB_GHWCFG1_REG register
  9403. * User Hardware Configuration 1 Register
  9404. */
  9405. #define USB_GHWCFG1_REG (SOC_DPORT_USB_BASE + 0x44)
  9406. /** USB_EPDIR : RO; bitpos: [32:0]; default: 0;
  9407. * This 32-bit field uses two bits per endpoint to determine the endpoint direction.
  9408. * Bits [31:30]: Endpoint 15 direction
  9409. * Bits [29:28]: Endpoint 14 direction
  9410. * ...
  9411. * Direction:
  9412. * 2'b00: BIDIR (IN and OUT) endpoint
  9413. * 2'b01: IN endpoint
  9414. * 2'b10: OUT endpoint
  9415. * 2'b11: Reserved
  9416. */
  9417. #define USB_EPDIR 0xFFFFFFFF
  9418. #define USB_EPDIR_M (USB_EPDIR_V << USB_EPDIR_S)
  9419. #define USB_EPDIR_V 0xFFFFFFFF
  9420. #define USB_EPDIR_S 0
  9421. /** USB_GHWCFG2_REG register
  9422. * User Hardware Configuration 2 Register
  9423. */
  9424. #define USB_GHWCFG2_REG (SOC_DPORT_USB_BASE + 0x48)
  9425. /** USB_OTGMODE : RO; bitpos: [3:0]; default: 0;
  9426. * 3'b000: HNP- and SRP-Capable OTG (Host Device)
  9427. */
  9428. #define USB_OTGMODE 0x00000007
  9429. #define USB_OTGMODE_M (USB_OTGMODE_V << USB_OTGMODE_S)
  9430. #define USB_OTGMODE_V 0x00000007
  9431. #define USB_OTGMODE_S 0
  9432. /** USB_OTGARCH : RO; bitpos: [5:3]; default: 2;
  9433. * 2'b10: Internal DMA
  9434. */
  9435. #define USB_OTGARCH 0x00000003
  9436. #define USB_OTGARCH_M (USB_OTGARCH_V << USB_OTGARCH_S)
  9437. #define USB_OTGARCH_V 0x00000003
  9438. #define USB_OTGARCH_S 3
  9439. /** USB_SINGPNT : RO; bitpos: [5]; default: 1;
  9440. * Point-to-Point
  9441. * 1'b1: Single-point application (no hub and split support).
  9442. */
  9443. #define USB_SINGPNT (BIT(5))
  9444. #define USB_SINGPNT_M (USB_SINGPNT_V << USB_SINGPNT_S)
  9445. #define USB_SINGPNT_V 0x00000001
  9446. #define USB_SINGPNT_S 5
  9447. /** USB_HSPHYTYPE : RO; bitpos: [8:6]; default: 0;
  9448. * High-Speed PHY Interface Type
  9449. * 2'b00: High-Speed interface not supported
  9450. */
  9451. #define USB_HSPHYTYPE 0x00000003
  9452. #define USB_HSPHYTYPE_M (USB_HSPHYTYPE_V << USB_HSPHYTYPE_S)
  9453. #define USB_HSPHYTYPE_V 0x00000003
  9454. #define USB_HSPHYTYPE_S 6
  9455. /** USB_FSPHYTYPE : RO; bitpos: [10:8]; default: 1;
  9456. * Full-Speed PHY Interface Type.
  9457. */
  9458. #define USB_FSPHYTYPE 0x00000003
  9459. #define USB_FSPHYTYPE_M (USB_FSPHYTYPE_V << USB_FSPHYTYPE_S)
  9460. #define USB_FSPHYTYPE_V 0x00000003
  9461. #define USB_FSPHYTYPE_S 8
  9462. /** USB_NUMDEVEPS : RO; bitpos: [14:10]; default: 6;
  9463. * Number of Device Endpoints.
  9464. */
  9465. #define USB_NUMDEVEPS 0x0000000F
  9466. #define USB_NUMDEVEPS_M (USB_NUMDEVEPS_V << USB_NUMDEVEPS_S)
  9467. #define USB_NUMDEVEPS_V 0x0000000F
  9468. #define USB_NUMDEVEPS_S 10
  9469. /** USB_NUMHSTCHNL : RO; bitpos: [18:14]; default: 7;
  9470. * Number of Host Channels.
  9471. */
  9472. #define USB_NUMHSTCHNL 0x0000000F
  9473. #define USB_NUMHSTCHNL_M (USB_NUMHSTCHNL_V << USB_NUMHSTCHNL_S)
  9474. #define USB_NUMHSTCHNL_V 0x0000000F
  9475. #define USB_NUMHSTCHNL_S 14
  9476. /** USB_PERIOSUPPORT : RO; bitpos: [18]; default: 1;
  9477. * 1'b0:Periodic OUT Channels is not Supported in Host Mode
  9478. * 1'b1:Periodic OUT Channels Supported in Host Mode
  9479. */
  9480. #define USB_PERIOSUPPORT (BIT(18))
  9481. #define USB_PERIOSUPPORT_M (USB_PERIOSUPPORT_V << USB_PERIOSUPPORT_S)
  9482. #define USB_PERIOSUPPORT_V 0x00000001
  9483. #define USB_PERIOSUPPORT_S 18
  9484. /** USB_DYNFIFOSIZING : RO; bitpos: [19]; default: 1;
  9485. * 1'b0:Dynamic FIFO Sizing Disabled
  9486. * 1'b1:Dynamic FIFO Sizing Enabled
  9487. */
  9488. #define USB_DYNFIFOSIZING (BIT(19))
  9489. #define USB_DYNFIFOSIZING_M (USB_DYNFIFOSIZING_V << USB_DYNFIFOSIZING_S)
  9490. #define USB_DYNFIFOSIZING_V 0x00000001
  9491. #define USB_DYNFIFOSIZING_S 19
  9492. /** USB_MULTIPROCINTRPT : RO; bitpos: [20]; default: 0;
  9493. * 1'b0: No Multi Processor Interrupt Enabled
  9494. * 1'b1:Multi Processor Interrupt Enabled
  9495. */
  9496. #define USB_MULTIPROCINTRPT (BIT(20))
  9497. #define USB_MULTIPROCINTRPT_M (USB_MULTIPROCINTRPT_V << USB_MULTIPROCINTRPT_S)
  9498. #define USB_MULTIPROCINTRPT_V 0x00000001
  9499. #define USB_MULTIPROCINTRPT_S 20
  9500. /** USB_NPTXQDEPTH : RO; bitpos: [24:22]; default: 1;
  9501. * Non-periodic Request Queue Depth
  9502. * 2'b01: 4
  9503. */
  9504. #define USB_NPTXQDEPTH 0x00000003
  9505. #define USB_NPTXQDEPTH_M (USB_NPTXQDEPTH_V << USB_NPTXQDEPTH_S)
  9506. #define USB_NPTXQDEPTH_V 0x00000003
  9507. #define USB_NPTXQDEPTH_S 22
  9508. /** USB_PTXQDEPTH : RO; bitpos: [26:24]; default: 2;
  9509. * Host Mode Periodic Request Queue Depth.
  9510. * 2'b10: 8
  9511. */
  9512. #define USB_PTXQDEPTH 0x00000003
  9513. #define USB_PTXQDEPTH_M (USB_PTXQDEPTH_V << USB_PTXQDEPTH_S)
  9514. #define USB_PTXQDEPTH_V 0x00000003
  9515. #define USB_PTXQDEPTH_S 24
  9516. /** USB_TKNQDEPTH : RO; bitpos: [31:26]; default: 8;
  9517. * Device Mode IN Token Sequence Learning Queue Depth.
  9518. */
  9519. #define USB_TKNQDEPTH 0x0000001F
  9520. #define USB_TKNQDEPTH_M (USB_TKNQDEPTH_V << USB_TKNQDEPTH_S)
  9521. #define USB_TKNQDEPTH_V 0x0000001F
  9522. #define USB_TKNQDEPTH_S 26
  9523. /** USB_OTG_ENABLE_IC_USB : RO; bitpos: [31]; default: 0;
  9524. * 0x0 (DISABLE): Disabled the IC_USB Full-Speed Serial Transceiver interface
  9525. * 0x1 (ENABLE): Enabled the IC_USB Full-Speed Serial Transceiver interface
  9526. */
  9527. #define USB_OTG_ENABLE_IC_USB (BIT(31))
  9528. #define USB_OTG_ENABLE_IC_USB_M (USB_OTG_ENABLE_IC_USB_V << USB_OTG_ENABLE_IC_USB_S)
  9529. #define USB_OTG_ENABLE_IC_USB_V 0x00000001
  9530. #define USB_OTG_ENABLE_IC_USB_S 31
  9531. /** USB_GHWCFG3_REG register
  9532. * User Hardware Configuration 3 Register
  9533. */
  9534. #define USB_GHWCFG3_REG (SOC_DPORT_USB_BASE + 0x4c)
  9535. /** USB_XFERSIZEWIDTH : RO; bitpos: [4:0]; default: 5;
  9536. * Width of Transfer Size Counters
  9537. * 0x5 (WIDTH16): Width of Transfer Size Counter 16 bits
  9538. */
  9539. #define USB_XFERSIZEWIDTH 0x0000000F
  9540. #define USB_XFERSIZEWIDTH_M (USB_XFERSIZEWIDTH_V << USB_XFERSIZEWIDTH_S)
  9541. #define USB_XFERSIZEWIDTH_V 0x0000000F
  9542. #define USB_XFERSIZEWIDTH_S 0
  9543. /** USB_PKTSIZEWIDTH : RO; bitpos: [7:4]; default: 3;
  9544. * Width of Packet Size Counters
  9545. * 3'b011: 7 bits
  9546. */
  9547. #define USB_PKTSIZEWIDTH 0x00000007
  9548. #define USB_PKTSIZEWIDTH_M (USB_PKTSIZEWIDTH_V << USB_PKTSIZEWIDTH_S)
  9549. #define USB_PKTSIZEWIDTH_V 0x00000007
  9550. #define USB_PKTSIZEWIDTH_S 4
  9551. /** USB_OTGEN : RO; bitpos: [7]; default: 1;
  9552. * OTG Function Enabled.
  9553. */
  9554. #define USB_OTGEN (BIT(7))
  9555. #define USB_OTGEN_M (USB_OTGEN_V << USB_OTGEN_S)
  9556. #define USB_OTGEN_V 0x00000001
  9557. #define USB_OTGEN_S 7
  9558. /** USB_I2CINTSEL : RO; bitpos: [8]; default: 0;
  9559. * 1'b0: I2C Interface is not available on the controller.
  9560. */
  9561. #define USB_I2CINTSEL (BIT(8))
  9562. #define USB_I2CINTSEL_M (USB_I2CINTSEL_V << USB_I2CINTSEL_S)
  9563. #define USB_I2CINTSEL_V 0x00000001
  9564. #define USB_I2CINTSEL_S 8
  9565. /** USB_VNDCTLSUPT : RO; bitpos: [9]; default: 0;
  9566. * Vendor Control Interface is not available .
  9567. */
  9568. #define USB_VNDCTLSUPT (BIT(9))
  9569. #define USB_VNDCTLSUPT_M (USB_VNDCTLSUPT_V << USB_VNDCTLSUPT_S)
  9570. #define USB_VNDCTLSUPT_V 0x00000001
  9571. #define USB_VNDCTLSUPT_S 9
  9572. /** USB_OPTFEATURE : RO; bitpos: [10]; default: 1;
  9573. * Optional Features have been Removed.
  9574. */
  9575. #define USB_OPTFEATURE (BIT(10))
  9576. #define USB_OPTFEATURE_M (USB_OPTFEATURE_V << USB_OPTFEATURE_S)
  9577. #define USB_OPTFEATURE_V 0x00000001
  9578. #define USB_OPTFEATURE_S 10
  9579. /** USB_RSTTYPE : RO; bitpos: [11]; default: 0;
  9580. * Asynchronous reset is used in the core
  9581. */
  9582. #define USB_RSTTYPE (BIT(11))
  9583. #define USB_RSTTYPE_M (USB_RSTTYPE_V << USB_RSTTYPE_S)
  9584. #define USB_RSTTYPE_V 0x00000001
  9585. #define USB_RSTTYPE_S 11
  9586. /** USB_ADPSUPPORT : RO; bitpos: [12]; default: 0;
  9587. * ADP logic is not present along with the controller.
  9588. */
  9589. #define USB_ADPSUPPORT (BIT(12))
  9590. #define USB_ADPSUPPORT_M (USB_ADPSUPPORT_V << USB_ADPSUPPORT_S)
  9591. #define USB_ADPSUPPORT_V 0x00000001
  9592. #define USB_ADPSUPPORT_S 12
  9593. /** USB_HSICMODE : RO; bitpos: [13]; default: 0;
  9594. * HSIC mode specified for Mode of Operation.
  9595. * 1'b0: Non-HSIC-capable
  9596. */
  9597. #define USB_HSICMODE (BIT(13))
  9598. #define USB_HSICMODE_M (USB_HSICMODE_V << USB_HSICMODE_S)
  9599. #define USB_HSICMODE_V 0x00000001
  9600. #define USB_HSICMODE_S 13
  9601. /** USB_BCSUPPORT : RO; bitpos: [14]; default: 0;
  9602. * 1'b0: No Battery Charger Support
  9603. */
  9604. #define USB_BCSUPPORT (BIT(14))
  9605. #define USB_BCSUPPORT_M (USB_BCSUPPORT_V << USB_BCSUPPORT_S)
  9606. #define USB_BCSUPPORT_V 0x00000001
  9607. #define USB_BCSUPPORT_S 14
  9608. /** USB_LPMMODE : RO; bitpos: [15]; default: 0;
  9609. * LPM mode specified for Mode of Operation.
  9610. */
  9611. #define USB_LPMMODE (BIT(15))
  9612. #define USB_LPMMODE_M (USB_LPMMODE_V << USB_LPMMODE_S)
  9613. #define USB_LPMMODE_V 0x00000001
  9614. #define USB_LPMMODE_S 15
  9615. /** USB_DFIFODEPTH : RO; bitpos: [32:16]; default: 256;
  9616. * DFIFO Depth.This value is in terms of 32-bit words.
  9617. */
  9618. #define USB_DFIFODEPTH 0x0000FFFF
  9619. #define USB_DFIFODEPTH_M (USB_DFIFODEPTH_V << USB_DFIFODEPTH_S)
  9620. #define USB_DFIFODEPTH_V 0x0000FFFF
  9621. #define USB_DFIFODEPTH_S 16
  9622. /** USB_GHWCFG4_REG register
  9623. * User Hardware Configuration 4 Register
  9624. */
  9625. #define USB_GHWCFG4_REG (SOC_DPORT_USB_BASE + 0x50)
  9626. /** USB_G_NUMDEVPERIOEPS : RO; bitpos: [4:0]; default: 0;
  9627. * Number of Device Mode Periodic IN Endpoints.
  9628. */
  9629. #define USB_G_NUMDEVPERIOEPS 0x0000000F
  9630. #define USB_G_NUMDEVPERIOEPS_M (USB_G_NUMDEVPERIOEPS_V << USB_G_NUMDEVPERIOEPS_S)
  9631. #define USB_G_NUMDEVPERIOEPS_V 0x0000000F
  9632. #define USB_G_NUMDEVPERIOEPS_S 0
  9633. /** USB_G_PARTIALPWRDN : RO; bitpos: [4]; default: 1;
  9634. * Enable Partial Power Down.
  9635. */
  9636. #define USB_G_PARTIALPWRDN (BIT(4))
  9637. #define USB_G_PARTIALPWRDN_M (USB_G_PARTIALPWRDN_V << USB_G_PARTIALPWRDN_S)
  9638. #define USB_G_PARTIALPWRDN_V 0x00000001
  9639. #define USB_G_PARTIALPWRDN_S 4
  9640. /** USB_G_AHBFREQ : RO; bitpos: [5]; default: 1;
  9641. * Minimum AHB Frequency Less Than 60 MHz
  9642. */
  9643. #define USB_G_AHBFREQ (BIT(5))
  9644. #define USB_G_AHBFREQ_M (USB_G_AHBFREQ_V << USB_G_AHBFREQ_S)
  9645. #define USB_G_AHBFREQ_V 0x00000001
  9646. #define USB_G_AHBFREQ_S 5
  9647. /** USB_G_HIBERNATION : RO; bitpos: [6]; default: 0;
  9648. * 1'b0: Hibernation feature not enabled.
  9649. */
  9650. #define USB_G_HIBERNATION (BIT(6))
  9651. #define USB_G_HIBERNATION_M (USB_G_HIBERNATION_V << USB_G_HIBERNATION_S)
  9652. #define USB_G_HIBERNATION_V 0x00000001
  9653. #define USB_G_HIBERNATION_S 6
  9654. /** USB_G_EXTENDEDHIBERNATION : RO; bitpos: [7]; default: 0;
  9655. * Extended Hibernation feature not enabled
  9656. */
  9657. #define USB_G_EXTENDEDHIBERNATION (BIT(7))
  9658. #define USB_G_EXTENDEDHIBERNATION_M (USB_G_EXTENDEDHIBERNATION_V << USB_G_EXTENDEDHIBERNATION_S)
  9659. #define USB_G_EXTENDEDHIBERNATION_V 0x00000001
  9660. #define USB_G_EXTENDEDHIBERNATION_S 7
  9661. /** USB_G_ACGSUPT : RO; bitpos: [12]; default: 0;
  9662. * Active Clock Gating is not enabled.
  9663. */
  9664. #define USB_G_ACGSUPT (BIT(12))
  9665. #define USB_G_ACGSUPT_M (USB_G_ACGSUPT_V << USB_G_ACGSUPT_S)
  9666. #define USB_G_ACGSUPT_V 0x00000001
  9667. #define USB_G_ACGSUPT_S 12
  9668. /** USB_G_ENHANCEDLPMSUPT : RO; bitpos: [13]; default: 1;
  9669. * Enhanced LPM Support.
  9670. */
  9671. #define USB_G_ENHANCEDLPMSUPT (BIT(13))
  9672. #define USB_G_ENHANCEDLPMSUPT_M (USB_G_ENHANCEDLPMSUPT_V << USB_G_ENHANCEDLPMSUPT_S)
  9673. #define USB_G_ENHANCEDLPMSUPT_V 0x00000001
  9674. #define USB_G_ENHANCEDLPMSUPT_S 13
  9675. /** USB_G_PHYDATAWIDTH : RO; bitpos: [16:14]; default: 2;
  9676. * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width (PhyDataWidth) When a ULPI PHY
  9677. * is used, an internal wrapper converts ULPI to UTMI+
  9678. * 2'b10: 8/16 bits, software selectable
  9679. */
  9680. #define USB_G_PHYDATAWIDTH 0x00000003
  9681. #define USB_G_PHYDATAWIDTH_M (USB_G_PHYDATAWIDTH_V << USB_G_PHYDATAWIDTH_S)
  9682. #define USB_G_PHYDATAWIDTH_V 0x00000003
  9683. #define USB_G_PHYDATAWIDTH_S 14
  9684. /** USB_G_NUMCTLEPS : RO; bitpos: [20:16]; default: 0;
  9685. * Number of Device Mode Control Endpoints in Addition to Endpoint 0
  9686. */
  9687. #define USB_G_NUMCTLEPS 0x0000000F
  9688. #define USB_G_NUMCTLEPS_M (USB_G_NUMCTLEPS_V << USB_G_NUMCTLEPS_S)
  9689. #define USB_G_NUMCTLEPS_V 0x0000000F
  9690. #define USB_G_NUMCTLEPS_S 16
  9691. /** USB_G_IDDQFLTR : RO; bitpos: [20]; default: 1;
  9692. * IDDIG Filter Enable.
  9693. */
  9694. #define USB_G_IDDQFLTR (BIT(20))
  9695. #define USB_G_IDDQFLTR_M (USB_G_IDDQFLTR_V << USB_G_IDDQFLTR_S)
  9696. #define USB_G_IDDQFLTR_V 0x00000001
  9697. #define USB_G_IDDQFLTR_S 20
  9698. /** USB_G_VBUSVALIDFLTR : RO; bitpos: [21]; default: 1;
  9699. * VBUS Valid Filter Enabled.
  9700. */
  9701. #define USB_G_VBUSVALIDFLTR (BIT(21))
  9702. #define USB_G_VBUSVALIDFLTR_M (USB_G_VBUSVALIDFLTR_V << USB_G_VBUSVALIDFLTR_S)
  9703. #define USB_G_VBUSVALIDFLTR_V 0x00000001
  9704. #define USB_G_VBUSVALIDFLTR_S 21
  9705. /** USB_G_AVALIDFLTR : RO; bitpos: [22]; default: 1;
  9706. * a_valid Filter Enabled.
  9707. */
  9708. #define USB_G_AVALIDFLTR (BIT(22))
  9709. #define USB_G_AVALIDFLTR_M (USB_G_AVALIDFLTR_V << USB_G_AVALIDFLTR_S)
  9710. #define USB_G_AVALIDFLTR_V 0x00000001
  9711. #define USB_G_AVALIDFLTR_S 22
  9712. /** USB_G_BVALIDFLTR : RO; bitpos: [23]; default: 1;
  9713. * b_valid Filter Enabled.
  9714. */
  9715. #define USB_G_BVALIDFLTR (BIT(23))
  9716. #define USB_G_BVALIDFLTR_M (USB_G_BVALIDFLTR_V << USB_G_BVALIDFLTR_S)
  9717. #define USB_G_BVALIDFLTR_V 0x00000001
  9718. #define USB_G_BVALIDFLTR_S 23
  9719. /** USB_G_SESSENDFLTR : RO; bitpos: [24]; default: 1;
  9720. * session_end Filter Enabled.
  9721. */
  9722. #define USB_G_SESSENDFLTR (BIT(24))
  9723. #define USB_G_SESSENDFLTR_M (USB_G_SESSENDFLTR_V << USB_G_SESSENDFLTR_S)
  9724. #define USB_G_SESSENDFLTR_V 0x00000001
  9725. #define USB_G_SESSENDFLTR_S 24
  9726. /** USB_G_DEDFIFOMODE : RO; bitpos: [25]; default: 1;
  9727. * Enable Dedicated Transmit FIFO for device IN Endpoints
  9728. */
  9729. #define USB_G_DEDFIFOMODE (BIT(25))
  9730. #define USB_G_DEDFIFOMODE_M (USB_G_DEDFIFOMODE_V << USB_G_DEDFIFOMODE_S)
  9731. #define USB_G_DEDFIFOMODE_V 0x00000001
  9732. #define USB_G_DEDFIFOMODE_S 25
  9733. /** USB_G_INEPS : RO; bitpos: [30:26]; default: 4;
  9734. * Number of Device Mode IN Endpoints Including Control Endpoints.
  9735. */
  9736. #define USB_G_INEPS 0x0000000F
  9737. #define USB_G_INEPS_M (USB_G_INEPS_V << USB_G_INEPS_S)
  9738. #define USB_G_INEPS_V 0x0000000F
  9739. #define USB_G_INEPS_S 26
  9740. /** USB_G_DESCDMAENABLED : RO; bitpos: [30]; default: 1;
  9741. * 0x1: Scatter/Gather DMA configuration.
  9742. */
  9743. #define USB_G_DESCDMAENABLED (BIT(30))
  9744. #define USB_G_DESCDMAENABLED_M (USB_G_DESCDMAENABLED_V << USB_G_DESCDMAENABLED_S)
  9745. #define USB_G_DESCDMAENABLED_V 0x00000001
  9746. #define USB_G_DESCDMAENABLED_S 30
  9747. /** USB_G_DESCDMA : RO; bitpos: [31]; default: 1;
  9748. * Scatter/Gather DMA configuration
  9749. * 1'b1: Dynamic configuration
  9750. */
  9751. #define USB_G_DESCDMA (BIT(31))
  9752. #define USB_G_DESCDMA_M (USB_G_DESCDMA_V << USB_G_DESCDMA_S)
  9753. #define USB_G_DESCDMA_V 0x00000001
  9754. #define USB_G_DESCDMA_S 31
  9755. /** USB_HFNUM_REG register
  9756. * Frame Number configure Resigster
  9757. */
  9758. #define USB_HFNUM_REG (SOC_DPORT_USB_BASE + 0x408)
  9759. /** USB_FRNUM : RO; bitpos: [14:0]; default: 16383;
  9760. * Frame Number
  9761. * 0x0 (INACTIVE): No SOF is transmitted
  9762. * 0x1 (ACTIVE): SOF is transmitted
  9763. */
  9764. #define USB_FRNUM 0x00003FFF
  9765. #define USB_FRNUM_M (USB_FRNUM_V << USB_FRNUM_S)
  9766. #define USB_FRNUM_V 0x00003FFF
  9767. #define USB_FRNUM_S 0
  9768. /** USB_FRREM : RO; bitpos: [32:16]; default: 0;
  9769. * Frame Time Remaining.ndicates the amount of time remaining in the current
  9770. * microframe
  9771. * (HS) or Frame (FS/LS), in terms of PHY clocks.
  9772. */
  9773. #define USB_FRREM 0x0000FFFF
  9774. #define USB_FRREM_M (USB_FRREM_V << USB_FRREM_S)
  9775. #define USB_FRREM_V 0x0000FFFF
  9776. #define USB_FRREM_S 16
  9777. /** USB_HPTXSTS_REG register
  9778. * Host Periodic Transmit FIFO/Queue Status Register
  9779. */
  9780. #define USB_HPTXSTS_REG (SOC_DPORT_USB_BASE + 0x410)
  9781. /** USB_PTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256;
  9782. * Periodic Transmit Data FIFO Space Available. Values are in terms of 32-bit words.
  9783. */
  9784. #define USB_PTXFSPCAVAIL 0x0000FFFF
  9785. #define USB_PTXFSPCAVAIL_M (USB_PTXFSPCAVAIL_V << USB_PTXFSPCAVAIL_S)
  9786. #define USB_PTXFSPCAVAIL_V 0x0000FFFF
  9787. #define USB_PTXFSPCAVAIL_S 0
  9788. /** USB_PTXQSPCAVAIL : RO; bitpos: [21:16]; default: 8;
  9789. * Periodic Transmit Request Queue Space Available.
  9790. */
  9791. #define USB_PTXQSPCAVAIL 0x0000001F
  9792. #define USB_PTXQSPCAVAIL_M (USB_PTXQSPCAVAIL_V << USB_PTXQSPCAVAIL_S)
  9793. #define USB_PTXQSPCAVAIL_V 0x0000001F
  9794. #define USB_PTXQSPCAVAIL_S 16
  9795. /** USB_PTXQTOP : RO; bitpos: [32:24]; default: 0;
  9796. * Bit [31]: Odd/Even (micro)Frame. 1'b0: send in even (micro)Frame
  9797. * Bits [30:27]: Channel/endpoint number
  9798. * Bits [26:25]: Type. 2'b00: IN/OUT. 2'b01: Zero-length packet. 2'b10: CSPLIT
  9799. * 2'b11: Disable channel command
  9800. * Bit [24]: Terminate
  9801. */
  9802. #define USB_PTXQTOP 0x000000FF
  9803. #define USB_PTXQTOP_M (USB_PTXQTOP_V << USB_PTXQTOP_S)
  9804. #define USB_PTXQTOP_V 0x000000FF
  9805. #define USB_PTXQTOP_S 24
  9806. /** USB_HCDMAB$n_REG register
  9807. * Host Channel $n DMA Buffer Address Register
  9808. */
  9809. #define USB_HCDMAB$N_REG (SOC_DPORT_USB_BASE + 0x51c)
  9810. /** USB_H_HCDMAB0 : RO; bitpos: [32:0]; default: 0;
  9811. * Holds the current buffer address
  9812. */
  9813. #define USB_H_HCDMAB0 0xFFFFFFFF
  9814. #define USB_H_HCDMAB0_M (USB_H_HCDMAB0_V << USB_H_HCDMAB0_S)
  9815. #define USB_H_HCDMAB0_V 0xFFFFFFFF
  9816. #define USB_H_HCDMAB0_S 0
  9817. /** USB_HCDMAB1_REG register
  9818. * Host Channel 1 DMA Buffer Address Register
  9819. */
  9820. #define USB_HCDMAB1_REG (SOC_DPORT_USB_BASE + 0x53c)
  9821. /** USB_H_HCDMAB1 : RO; bitpos: [32:0]; default: 0;
  9822. * Holds the current buffer address
  9823. */
  9824. #define USB_H_HCDMAB1 0xFFFFFFFF
  9825. #define USB_H_HCDMAB1_M (USB_H_HCDMAB1_V << USB_H_HCDMAB1_S)
  9826. #define USB_H_HCDMAB1_V 0xFFFFFFFF
  9827. #define USB_H_HCDMAB1_S 0
  9828. /** USB_HCDMAB2_REG register
  9829. * Host Channel 2 DMA Buffer Address Register
  9830. */
  9831. #define USB_HCDMAB2_REG (SOC_DPORT_USB_BASE + 0x55c)
  9832. /** USB_H_HCDMAB2 : RO; bitpos: [32:0]; default: 0;
  9833. * Holds the current buffer address
  9834. */
  9835. #define USB_H_HCDMAB2 0xFFFFFFFF
  9836. #define USB_H_HCDMAB2_M (USB_H_HCDMAB2_V << USB_H_HCDMAB2_S)
  9837. #define USB_H_HCDMAB2_V 0xFFFFFFFF
  9838. #define USB_H_HCDMAB2_S 0
  9839. /** USB_HCDMAB3_REG register
  9840. * Host Channel 3 DMA Buffer Address Register
  9841. */
  9842. #define USB_HCDMAB3_REG (SOC_DPORT_USB_BASE + 0x57c)
  9843. /** USB_H_HCDMAB3 : RO; bitpos: [32:0]; default: 0;
  9844. * Holds the current buffer address
  9845. */
  9846. #define USB_H_HCDMAB3 0xFFFFFFFF
  9847. #define USB_H_HCDMAB3_M (USB_H_HCDMAB3_V << USB_H_HCDMAB3_S)
  9848. #define USB_H_HCDMAB3_V 0xFFFFFFFF
  9849. #define USB_H_HCDMAB3_S 0
  9850. /** USB_HCDMAB4_REG register
  9851. * Host Channel 4 DMA Buffer Address Register
  9852. */
  9853. #define USB_HCDMAB4_REG (SOC_DPORT_USB_BASE + 0x59c)
  9854. /** USB_H_HCDMAB4 : RO; bitpos: [32:0]; default: 0;
  9855. * Holds the current buffer address
  9856. */
  9857. #define USB_H_HCDMAB4 0xFFFFFFFF
  9858. #define USB_H_HCDMAB4_M (USB_H_HCDMAB4_V << USB_H_HCDMAB4_S)
  9859. #define USB_H_HCDMAB4_V 0xFFFFFFFF
  9860. #define USB_H_HCDMAB4_S 0
  9861. /** USB_HCDMAB5_REG register
  9862. * Host Channel 5 DMA Buffer Address Register
  9863. */
  9864. #define USB_HCDMAB5_REG (SOC_DPORT_USB_BASE + 0x5bc)
  9865. /** USB_H_HCDMAB5 : RO; bitpos: [32:0]; default: 0;
  9866. * Holds the current buffer address
  9867. */
  9868. #define USB_H_HCDMAB5 0xFFFFFFFF
  9869. #define USB_H_HCDMAB5_M (USB_H_HCDMAB5_V << USB_H_HCDMAB5_S)
  9870. #define USB_H_HCDMAB5_V 0xFFFFFFFF
  9871. #define USB_H_HCDMAB5_S 0
  9872. /** USB_HCDMAB6_REG register
  9873. * Host Channel 6 DMA Buffer Address Register
  9874. */
  9875. #define USB_HCDMAB6_REG (SOC_DPORT_USB_BASE + 0x5dc)
  9876. /** USB_H_HCDMAB6 : RO; bitpos: [32:0]; default: 0;
  9877. * Holds the current buffer address
  9878. */
  9879. #define USB_H_HCDMAB6 0xFFFFFFFF
  9880. #define USB_H_HCDMAB6_M (USB_H_HCDMAB6_V << USB_H_HCDMAB6_S)
  9881. #define USB_H_HCDMAB6_V 0xFFFFFFFF
  9882. #define USB_H_HCDMAB6_S 0
  9883. /** USB_HCDMAB7_REG register
  9884. * Host Channel 7 DMA Buffer Address Register
  9885. */
  9886. #define USB_HCDMAB7_REG (SOC_DPORT_USB_BASE + 0x5fc)
  9887. /** USB_H_HCDMAB7 : RO; bitpos: [32:0]; default: 0;
  9888. * Holds the current buffer address
  9889. */
  9890. #define USB_H_HCDMAB7 0xFFFFFFFF
  9891. #define USB_H_HCDMAB7_M (USB_H_HCDMAB7_V << USB_H_HCDMAB7_S)
  9892. #define USB_H_HCDMAB7_V 0xFFFFFFFF
  9893. #define USB_H_HCDMAB7_S 0
  9894. /** USB_DSTS_REG register
  9895. * Device Status Register
  9896. */
  9897. #define USB_DSTS_REG (SOC_DPORT_USB_BASE + 0x808)
  9898. /** USB_SUSPSTS : RO; bitpos: [0]; default: 0;
  9899. * Suspend Status
  9900. * 0x0 : No suspend state
  9901. * 0x1 : Suspend state
  9902. */
  9903. #define USB_SUSPSTS (BIT(0))
  9904. #define USB_SUSPSTS_M (USB_SUSPSTS_V << USB_SUSPSTS_S)
  9905. #define USB_SUSPSTS_V 0x00000001
  9906. #define USB_SUSPSTS_S 0
  9907. /** USB_ENUMSPD : RO; bitpos: [3:1]; default: 1;
  9908. * 0x0 : High speed (PHY clock is running at 30 or 60 MHz)
  9909. * 0x1 : Full speed (PHY clock is running at 30 or 60 MHz)
  9910. * 0x2 : Low speed (PHY clock is running at 6 MHz)
  9911. * 0x3 : Full speed (PHY clock is running at 48 MHz)
  9912. */
  9913. #define USB_ENUMSPD 0x00000003
  9914. #define USB_ENUMSPD_M (USB_ENUMSPD_V << USB_ENUMSPD_S)
  9915. #define USB_ENUMSPD_V 0x00000003
  9916. #define USB_ENUMSPD_S 1
  9917. /** USB_ERRTICERR : RO; bitpos: [3]; default: 0;
  9918. * 0x0 : No Erratic Error
  9919. * 0x1 : Erratic Error
  9920. */
  9921. #define USB_ERRTICERR (BIT(3))
  9922. #define USB_ERRTICERR_M (USB_ERRTICERR_V << USB_ERRTICERR_S)
  9923. #define USB_ERRTICERR_V 0x00000001
  9924. #define USB_ERRTICERR_S 3
  9925. /** USB_SOFFN : RO; bitpos: [22:8]; default: 0;
  9926. * Frame or Microframe Number of the Received SOF (SOFFN). This field contains a
  9927. * Frame number.
  9928. */
  9929. #define USB_SOFFN 0x00003FFF
  9930. #define USB_SOFFN_M (USB_SOFFN_V << USB_SOFFN_S)
  9931. #define USB_SOFFN_V 0x00003FFF
  9932. #define USB_SOFFN_S 8
  9933. /** USB_DEVLNSTS : RO; bitpos: [24:22]; default: 0;
  9934. * Device Line Status
  9935. * DevLnSts[1]: Logic level of D+
  9936. * DevLnSts[0]: Logic level of D-
  9937. */
  9938. #define USB_DEVLNSTS 0x00000003
  9939. #define USB_DEVLNSTS_M (USB_DEVLNSTS_V << USB_DEVLNSTS_S)
  9940. #define USB_DEVLNSTS_V 0x00000003
  9941. #define USB_DEVLNSTS_S 22
  9942. /** USB_DTXFSTS0_REG register
  9943. * Device IN Endpoint Transmit FIFO Status Register 0
  9944. */
  9945. #define USB_DTXFSTS0_REG (SOC_DPORT_USB_BASE + 0x918)
  9946. /** USB_D_INEPTXFSPCAVAIL0 : RO; bitpos: [16:0]; default: 0;
  9947. * Indicates the amount of free space available in the Endpoint TxFIFO.
  9948. */
  9949. #define USB_D_INEPTXFSPCAVAIL0 0x0000FFFF
  9950. #define USB_D_INEPTXFSPCAVAIL0_M (USB_D_INEPTXFSPCAVAIL0_V << USB_D_INEPTXFSPCAVAIL0_S)
  9951. #define USB_D_INEPTXFSPCAVAIL0_V 0x0000FFFF
  9952. #define USB_D_INEPTXFSPCAVAIL0_S 0
  9953. /** USB_DIEPDMAB0_REG register
  9954. * Device IN Endpoint 16 Buffer Address Register
  9955. */
  9956. #define USB_DIEPDMAB0_REG (SOC_DPORT_USB_BASE + 0x91c)
  9957. /** USB_D_DMABUFFERADDR0 : RO; bitpos: [32:0]; default: 0;
  9958. * Holds the current buffer address.This register is updated as and when the data
  9959. * transfer for the corresponding end point is in progress. This register is present
  9960. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  9961. */
  9962. #define USB_D_DMABUFFERADDR0 0xFFFFFFFF
  9963. #define USB_D_DMABUFFERADDR0_M (USB_D_DMABUFFERADDR0_V << USB_D_DMABUFFERADDR0_S)
  9964. #define USB_D_DMABUFFERADDR0_V 0xFFFFFFFF
  9965. #define USB_D_DMABUFFERADDR0_S 0
  9966. /** USB_DTXFSTS1_REG register
  9967. * Device IN Endpoint Transmit FIFO Status Register 1
  9968. */
  9969. #define USB_DTXFSTS1_REG (SOC_DPORT_USB_BASE + 0x938)
  9970. /** USB_D_INEPTXFSPCAVAIL1 : RO; bitpos: [16:0]; default: 0;
  9971. * Indicates the amount of free space available in the Endpoint TxFIFO.
  9972. */
  9973. #define USB_D_INEPTXFSPCAVAIL1 0x0000FFFF
  9974. #define USB_D_INEPTXFSPCAVAIL1_M (USB_D_INEPTXFSPCAVAIL1_V << USB_D_INEPTXFSPCAVAIL1_S)
  9975. #define USB_D_INEPTXFSPCAVAIL1_V 0x0000FFFF
  9976. #define USB_D_INEPTXFSPCAVAIL1_S 0
  9977. /** USB_DIEPDMAB1_REG register
  9978. * Device IN Endpoint 16 Buffer Address Register
  9979. */
  9980. #define USB_DIEPDMAB1_REG (SOC_DPORT_USB_BASE + 0x93c)
  9981. /** USB_D_DMABUFFERADDR1 : RO; bitpos: [32:0]; default: 0;
  9982. * Holds the current buffer address.This register is updated as and when the data
  9983. * transfer for the corresponding end point is in progress. This register is present
  9984. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  9985. */
  9986. #define USB_D_DMABUFFERADDR1 0xFFFFFFFF
  9987. #define USB_D_DMABUFFERADDR1_M (USB_D_DMABUFFERADDR1_V << USB_D_DMABUFFERADDR1_S)
  9988. #define USB_D_DMABUFFERADDR1_V 0xFFFFFFFF
  9989. #define USB_D_DMABUFFERADDR1_S 0
  9990. /** USB_DTXFSTS2_REG register
  9991. * Device IN Endpoint Transmit FIFO Status Register 2
  9992. */
  9993. #define USB_DTXFSTS2_REG (SOC_DPORT_USB_BASE + 0x958)
  9994. /** USB_D_INEPTXFSPCAVAIL2 : RO; bitpos: [16:0]; default: 0;
  9995. * Indicates the amount of free space available in the Endpoint TxFIFO.
  9996. */
  9997. #define USB_D_INEPTXFSPCAVAIL2 0x0000FFFF
  9998. #define USB_D_INEPTXFSPCAVAIL2_M (USB_D_INEPTXFSPCAVAIL2_V << USB_D_INEPTXFSPCAVAIL2_S)
  9999. #define USB_D_INEPTXFSPCAVAIL2_V 0x0000FFFF
  10000. #define USB_D_INEPTXFSPCAVAIL2_S 0
  10001. /** USB_DIEPDMAB2_REG register
  10002. * Device IN Endpoint 16 Buffer Address Register
  10003. */
  10004. #define USB_DIEPDMAB2_REG (SOC_DPORT_USB_BASE + 0x95c)
  10005. /** USB_D_DMABUFFERADDR2 : RO; bitpos: [32:0]; default: 0;
  10006. * Holds the current buffer address.This register is updated as and when the data
  10007. * transfer for the corresponding end point is in progress. This register is present
  10008. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  10009. */
  10010. #define USB_D_DMABUFFERADDR2 0xFFFFFFFF
  10011. #define USB_D_DMABUFFERADDR2_M (USB_D_DMABUFFERADDR2_V << USB_D_DMABUFFERADDR2_S)
  10012. #define USB_D_DMABUFFERADDR2_V 0xFFFFFFFF
  10013. #define USB_D_DMABUFFERADDR2_S 0
  10014. /** USB_DTXFSTS3_REG register
  10015. * Device IN Endpoint Transmit FIFO Status Register 3
  10016. */
  10017. #define USB_DTXFSTS3_REG (SOC_DPORT_USB_BASE + 0x978)
  10018. /** USB_D_INEPTXFSPCAVAIL3 : RO; bitpos: [16:0]; default: 0;
  10019. * Indicates the amount of free space available in the Endpoint TxFIFO.
  10020. */
  10021. #define USB_D_INEPTXFSPCAVAIL3 0x0000FFFF
  10022. #define USB_D_INEPTXFSPCAVAIL3_M (USB_D_INEPTXFSPCAVAIL3_V << USB_D_INEPTXFSPCAVAIL3_S)
  10023. #define USB_D_INEPTXFSPCAVAIL3_V 0x0000FFFF
  10024. #define USB_D_INEPTXFSPCAVAIL3_S 0
  10025. /** USB_DIEPDMAB3_REG register
  10026. * Device IN Endpoint 16 Buffer Address Register
  10027. */
  10028. #define USB_DIEPDMAB3_REG (SOC_DPORT_USB_BASE + 0x97c)
  10029. /** USB_D_DMABUFFERADDR3 : RO; bitpos: [32:0]; default: 0;
  10030. * Holds the current buffer address.This register is updated as and when the data
  10031. * transfer for the corresponding end point is in progress. This register is present
  10032. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  10033. */
  10034. #define USB_D_DMABUFFERADDR3 0xFFFFFFFF
  10035. #define USB_D_DMABUFFERADDR3_M (USB_D_DMABUFFERADDR3_V << USB_D_DMABUFFERADDR3_S)
  10036. #define USB_D_DMABUFFERADDR3_V 0xFFFFFFFF
  10037. #define USB_D_DMABUFFERADDR3_S 0
  10038. /** USB_DTXFSTS4_REG register
  10039. * Device IN Endpoint Transmit FIFO Status Register 4
  10040. */
  10041. #define USB_DTXFSTS4_REG (SOC_DPORT_USB_BASE + 0x998)
  10042. /** USB_D_INEPTXFSPCAVAIL4 : RO; bitpos: [16:0]; default: 0;
  10043. * Indicates the amount of free space available in the Endpoint TxFIFO.
  10044. */
  10045. #define USB_D_INEPTXFSPCAVAIL4 0x0000FFFF
  10046. #define USB_D_INEPTXFSPCAVAIL4_M (USB_D_INEPTXFSPCAVAIL4_V << USB_D_INEPTXFSPCAVAIL4_S)
  10047. #define USB_D_INEPTXFSPCAVAIL4_V 0x0000FFFF
  10048. #define USB_D_INEPTXFSPCAVAIL4_S 0
  10049. /** USB_DIEPDMAB4_REG register
  10050. * Device IN Endpoint 16 Buffer Address Register
  10051. */
  10052. #define USB_DIEPDMAB4_REG (SOC_DPORT_USB_BASE + 0x99c)
  10053. /** USB_D_DMABUFFERADDR4 : RO; bitpos: [32:0]; default: 0;
  10054. * Holds the current buffer address.This register is updated as and when the data
  10055. * transfer for the corresponding end point is in progress. This register is present
  10056. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  10057. */
  10058. #define USB_D_DMABUFFERADDR4 0xFFFFFFFF
  10059. #define USB_D_DMABUFFERADDR4_M (USB_D_DMABUFFERADDR4_V << USB_D_DMABUFFERADDR4_S)
  10060. #define USB_D_DMABUFFERADDR4_V 0xFFFFFFFF
  10061. #define USB_D_DMABUFFERADDR4_S 0
  10062. /** USB_DTXFSTS5_REG register
  10063. * Device IN Endpoint Transmit FIFO Status Register 5
  10064. */
  10065. #define USB_DTXFSTS5_REG (SOC_DPORT_USB_BASE + 0x9b8)
  10066. /** USB_D_INEPTXFSPCAVAIL5 : RO; bitpos: [16:0]; default: 0;
  10067. * Indicates the amount of free space available in the Endpoint TxFIFO.
  10068. */
  10069. #define USB_D_INEPTXFSPCAVAIL5 0x0000FFFF
  10070. #define USB_D_INEPTXFSPCAVAIL5_M (USB_D_INEPTXFSPCAVAIL5_V << USB_D_INEPTXFSPCAVAIL5_S)
  10071. #define USB_D_INEPTXFSPCAVAIL5_V 0x0000FFFF
  10072. #define USB_D_INEPTXFSPCAVAIL5_S 0
  10073. /** USB_DIEPDMAB5_REG register
  10074. * Device IN Endpoint 16 Buffer Address Register
  10075. */
  10076. #define USB_DIEPDMAB5_REG (SOC_DPORT_USB_BASE + 0x9bc)
  10077. /** USB_D_DMABUFFERADDR5 : RO; bitpos: [32:0]; default: 0;
  10078. * Holds the current buffer address.This register is updated as and when the data
  10079. * transfer for the corresponding end point is in progress. This register is present
  10080. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  10081. */
  10082. #define USB_D_DMABUFFERADDR5 0xFFFFFFFF
  10083. #define USB_D_DMABUFFERADDR5_M (USB_D_DMABUFFERADDR5_V << USB_D_DMABUFFERADDR5_S)
  10084. #define USB_D_DMABUFFERADDR5_V 0xFFFFFFFF
  10085. #define USB_D_DMABUFFERADDR5_S 0
  10086. /** USB_DTXFSTS6_REG register
  10087. * Device IN Endpoint Transmit FIFO Status Register 6
  10088. */
  10089. #define USB_DTXFSTS6_REG (SOC_DPORT_USB_BASE + 0x9d8)
  10090. /** USB_D_INEPTXFSPCAVAIL6 : RO; bitpos: [16:0]; default: 0;
  10091. * Indicates the amount of free space available in the Endpoint TxFIFO.
  10092. */
  10093. #define USB_D_INEPTXFSPCAVAIL6 0x0000FFFF
  10094. #define USB_D_INEPTXFSPCAVAIL6_M (USB_D_INEPTXFSPCAVAIL6_V << USB_D_INEPTXFSPCAVAIL6_S)
  10095. #define USB_D_INEPTXFSPCAVAIL6_V 0x0000FFFF
  10096. #define USB_D_INEPTXFSPCAVAIL6_S 0
  10097. /** USB_DIEPDMAB6_REG register
  10098. * Device IN Endpoint 16 Buffer Address Register
  10099. */
  10100. #define USB_DIEPDMAB6_REG (SOC_DPORT_USB_BASE + 0x9dc)
  10101. /** USB_D_DMABUFFERADDR6 : RO; bitpos: [32:0]; default: 0;
  10102. * Holds the current buffer address.This register is updated as and when the data
  10103. * transfer for the corresponding end point is in progress. This register is present
  10104. * only in Scatter/Gather DMA mode. Otherwise this field is reserved.
  10105. */
  10106. #define USB_D_DMABUFFERADDR6 0xFFFFFFFF
  10107. #define USB_D_DMABUFFERADDR6_M (USB_D_DMABUFFERADDR6_V << USB_D_DMABUFFERADDR6_S)
  10108. #define USB_D_DMABUFFERADDR6_V 0xFFFFFFFF
  10109. #define USB_D_DMABUFFERADDR6_S 0
  10110. #ifdef __cplusplus
  10111. }
  10112. #endif