phy_common.c 2.7 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include "eth_phy/phy.h"
  14. #include "eth_phy/phy_reg.h"
  15. #include "driver/gpio.h"
  16. #include "esp_log.h"
  17. static const char *TAG = "phy_common";
  18. void phy_rmii_configure_data_interface_pins(void)
  19. {
  20. // CRS_DRV to GPIO27
  21. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
  22. // TXD0 to GPIO19
  23. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
  24. // TX_EN to GPIO21
  25. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN);
  26. // TXD1 to GPIO22
  27. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1);
  28. // RXD0 to GPIO25
  29. gpio_set_direction(25, GPIO_MODE_INPUT);
  30. // RXD1 to GPIO26
  31. gpio_set_direction(26, GPIO_MODE_INPUT);
  32. // RMII CLK to GPIO0
  33. gpio_set_direction(0, GPIO_MODE_INPUT);
  34. }
  35. void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio)
  36. {
  37. // setup SMI MDC pin
  38. gpio_set_direction(mdc_gpio, GPIO_MODE_OUTPUT);
  39. gpio_matrix_out(mdc_gpio, EMAC_MDC_O_IDX, 0, 0);
  40. PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[mdc_gpio], PIN_FUNC_GPIO);
  41. // setup SMI MDIO pin
  42. gpio_set_direction(mdio_gpio, GPIO_MODE_INPUT_OUTPUT);
  43. gpio_matrix_out(mdio_gpio, EMAC_MDO_O_IDX, 0, 0);
  44. gpio_matrix_in(mdio_gpio, EMAC_MDI_I_IDX, 0);
  45. PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[mdio_gpio], PIN_FUNC_GPIO);
  46. }
  47. void phy_mii_enable_flow_ctrl(void)
  48. {
  49. uint32_t data = esp_eth_smi_read(MII_AUTO_NEG_ADVERTISEMENT_REG);
  50. data |= MII_ASM_DIR | MII_PAUSE;
  51. esp_eth_smi_write(MII_AUTO_NEG_ADVERTISEMENT_REG, data);
  52. }
  53. bool phy_mii_check_link_status(void)
  54. {
  55. if ((esp_eth_smi_read(MII_BASIC_MODE_STATUS_REG) & MII_LINK_STATUS)) {
  56. ESP_LOGD(TAG, "phy_mii_check_link_status(UP)");
  57. return true;
  58. } else {
  59. ESP_LOGD(TAG, "phy_mii_check_link_status(DOWN)");
  60. return false;
  61. }
  62. }
  63. bool phy_mii_get_partner_pause_enable(void)
  64. {
  65. if ((esp_eth_smi_read(MII_PHY_LINK_PARTNER_ABILITY_REG) & MII_PARTNER_PAUSE)) {
  66. ESP_LOGD(TAG, "phy_mii_get_partner_pause_enable(TRUE)");
  67. return true;
  68. } else {
  69. ESP_LOGD(TAG, "phy_mii_get_partner_pause_enable(FALSE)");
  70. return false;
  71. }
  72. }