cache_utils.h 2.3 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #ifndef ESP_SPI_FLASH_CACHE_UTILS_H
  15. #define ESP_SPI_FLASH_CACHE_UTILS_H
  16. /**
  17. * This header file contains declarations of cache manipulation functions
  18. * used both in flash_ops.c and flash_mmap.c.
  19. *
  20. * These functions are considered internal and are not designed to be called from applications.
  21. */
  22. // Init mutex protecting access to spi_flash_* APIs
  23. void spi_flash_init_lock();
  24. // Take mutex protecting access to spi_flash_* APIs
  25. void spi_flash_op_lock();
  26. // Release said mutex
  27. void spi_flash_op_unlock();
  28. // Suspend the scheduler on both CPUs, disable cache.
  29. // Contrary to its name this doesn't do anything with interrupts, yet.
  30. // Interrupt disabling capability will be added once we implement
  31. // interrupt allocation API.
  32. void spi_flash_disable_interrupts_caches_and_other_cpu();
  33. // Enable cache, enable interrupts (to be added in future), resume scheduler
  34. void spi_flash_enable_interrupts_caches_and_other_cpu();
  35. // Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
  36. // This function is implied to be called when other CPU is not running or running code from IRAM.
  37. void spi_flash_disable_interrupts_caches_and_other_cpu_no_os();
  38. // Enable cache, enable interrupts on current CPU.
  39. // This function is implied to be called when other CPU is not running or running code from IRAM.
  40. void spi_flash_enable_interrupts_caches_no_os();
  41. // Flushes cache if address range has corresponding valid cache mappings
  42. // Recommended to use post flash program operation (erase or write)
  43. // Only call this while holding spi_flash_op_lock()
  44. // Returns true if cache was flushed, false otherwise
  45. bool spi_flash_check_and_flush_cache(uint32_t start_addr, uint32_t length);
  46. #endif //ESP_SPI_FLASH_CACHE_UTILS_H