test_i2s.c 12 KB

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  1. /**
  2. * I2S test environment UT_T1_I2S:
  3. * connect GPIO18 and GPIO19, GPIO25 and GPIO26, GPIO21 and GPIO22
  4. */
  5. #include <stdio.h>
  6. #include <string.h>
  7. #include "freertos/FreeRTOS.h"
  8. #include "freertos/task.h"
  9. #include "driver/i2s.h"
  10. #include "unity.h"
  11. #include "math.h"
  12. #define SAMPLE_RATE (36000)
  13. #define SAMPLE_BITS (16)
  14. #define MASTER_BCK_IO 18
  15. #define MASTER_WS_IO 25
  16. #define SLAVE_BCK_IO 19
  17. #define SLAVE_WS_IO 26
  18. #define DATA_IN_IO 21
  19. #define DATA_OUT_IO 22
  20. #define PERCENT_DIFF 0.0001
  21. /**
  22. * i2s initialize test
  23. * 1. i2s_driver_install
  24. * 2. i2s_set_pin
  25. */
  26. TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
  27. {
  28. // dac, adc i2s
  29. i2s_config_t i2s_config = {
  30. .mode = I2S_MODE_MASTER | I2S_MODE_TX,
  31. .sample_rate = SAMPLE_RATE,
  32. .bits_per_sample = SAMPLE_BITS,
  33. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  34. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  35. .dma_buf_count = 6,
  36. .dma_buf_len = 60,
  37. .use_apll = 0,
  38. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  39. };
  40. //install and start i2s driver
  41. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
  42. //for internal DAC, this will enable both of the internal channels
  43. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, NULL));
  44. //stop & destroy i2s driver
  45. TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
  46. // normal i2s
  47. i2s_pin_config_t pin_config = {
  48. .bck_io_num = MASTER_BCK_IO,
  49. .ws_io_num = MASTER_WS_IO,
  50. .data_out_num = DATA_OUT_IO,
  51. .data_in_num = -1
  52. };
  53. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
  54. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
  55. TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
  56. //error param test
  57. TEST_ASSERT(i2s_driver_install(I2S_NUM_MAX, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
  58. TEST_ASSERT(i2s_driver_install(I2S_NUM_0, NULL, 0, NULL) == ESP_ERR_INVALID_ARG);
  59. i2s_config.dma_buf_count = 1;
  60. TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
  61. i2s_config.dma_buf_count = 129;
  62. TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
  63. TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
  64. }
  65. TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")
  66. {
  67. // master driver installed and send data
  68. i2s_config_t master_i2s_config = {
  69. .mode = I2S_MODE_MASTER | I2S_MODE_TX,
  70. .sample_rate = SAMPLE_RATE,
  71. .bits_per_sample = SAMPLE_BITS,
  72. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  73. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  74. .dma_buf_count = 6,
  75. .dma_buf_len = 100,
  76. .use_apll = 0,
  77. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  78. };
  79. i2s_pin_config_t master_pin_config = {
  80. .bck_io_num = MASTER_BCK_IO,
  81. .ws_io_num = MASTER_WS_IO,
  82. .data_out_num = DATA_OUT_IO,
  83. .data_in_num = -1
  84. };
  85. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
  86. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
  87. printf("\r\nheap size: %d\n", esp_get_free_heap_size());
  88. i2s_config_t slave_i2s_config = {
  89. .mode = I2S_MODE_SLAVE | I2S_MODE_RX,
  90. .sample_rate = SAMPLE_RATE,
  91. .bits_per_sample = SAMPLE_BITS,
  92. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  93. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  94. .dma_buf_count = 6,
  95. .dma_buf_len = 100,
  96. .use_apll = 0,
  97. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  98. };
  99. i2s_pin_config_t slave_pin_config = {
  100. .bck_io_num = SLAVE_BCK_IO,
  101. .ws_io_num = SLAVE_WS_IO,
  102. .data_out_num = -1,
  103. .data_in_num = DATA_IN_IO,
  104. };
  105. // slave driver installed and receive data
  106. TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
  107. TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
  108. printf("\r\nheap size: %d\n", esp_get_free_heap_size());
  109. uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
  110. size_t i2s_bytes_write = 0;
  111. size_t bytes_read = 0;
  112. int length = 0;
  113. uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*10000);
  114. for(int i=0; i<100; i++) {
  115. data_wr[i] = i+1;
  116. }
  117. int flag=0; // break loop flag
  118. int end_position = 0;
  119. // write data to slave
  120. i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
  121. while(!flag){
  122. i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t)*500, &bytes_read, 1000/portMAX_DELAY);
  123. if(bytes_read>0) {
  124. printf("read data size: %d\n", bytes_read);
  125. for(int i=length; i<length + bytes_read; i++) {
  126. if(i2s_read_buff[i] == 100) {
  127. flag=1;
  128. end_position = i;
  129. break;
  130. }
  131. }
  132. }
  133. length = length + bytes_read;
  134. }
  135. // test the readed data right or not
  136. for(int i=end_position-99; i<=end_position; i++) {
  137. TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
  138. }
  139. free(data_wr);
  140. free(i2s_read_buff);
  141. i2s_driver_uninstall(I2S_NUM_0);
  142. i2s_driver_uninstall(I2S_NUM_1);
  143. }
  144. TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s][test_env=UT_T1_I2S]")
  145. {
  146. // master driver installed and send data
  147. i2s_config_t master_i2s_config = {
  148. .mode = I2S_MODE_MASTER | I2S_MODE_RX,
  149. .sample_rate = SAMPLE_RATE,
  150. .bits_per_sample = SAMPLE_BITS,
  151. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  152. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  153. .dma_buf_count = 6,
  154. .dma_buf_len = 100,
  155. .use_apll = 0,
  156. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  157. };
  158. i2s_pin_config_t master_pin_config = {
  159. .bck_io_num = MASTER_BCK_IO,
  160. .ws_io_num = MASTER_WS_IO,
  161. .data_out_num = -1,
  162. .data_in_num = DATA_IN_IO,
  163. };
  164. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
  165. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
  166. printf("\r\nheap size: %d\n", esp_get_free_heap_size());
  167. i2s_config_t slave_i2s_config = {
  168. .mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
  169. .sample_rate = SAMPLE_RATE,
  170. .bits_per_sample = SAMPLE_BITS,
  171. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
  172. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  173. .dma_buf_count = 6,
  174. .dma_buf_len = 100,
  175. .use_apll = 0,
  176. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  177. };
  178. i2s_pin_config_t slave_pin_config = {
  179. .bck_io_num = SLAVE_BCK_IO,
  180. .ws_io_num = SLAVE_WS_IO,
  181. .data_out_num = DATA_OUT_IO,
  182. .data_in_num = -1
  183. };
  184. // slave driver installed and receive data
  185. TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
  186. TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
  187. uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
  188. size_t i2s_bytes_write = 0;
  189. size_t bytes_read = 0;
  190. int length = 0;
  191. uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*100000);
  192. for(int i=0; i<100; i++) {
  193. data_wr[i] = i+1;
  194. }
  195. // slave write data to master
  196. i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
  197. int flag=0; // break loop flag
  198. int end_position = 0;
  199. // write data to slave
  200. while(!flag){
  201. TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000-length, &bytes_read, 1000/portMAX_DELAY));
  202. if(bytes_read > 0) {
  203. for(int i=length; i<length+bytes_read; i++) {
  204. if(i2s_read_buff[i] == 100) {
  205. flag=1;
  206. end_position = i;
  207. break;
  208. }
  209. }
  210. }
  211. length = length + bytes_read;
  212. }
  213. // test the readed data right or not
  214. for(int i=end_position-99; i<=end_position; i++) {
  215. TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
  216. }
  217. free(data_wr);
  218. free(i2s_read_buff);
  219. i2s_driver_uninstall(I2S_NUM_0);
  220. i2s_driver_uninstall(I2S_NUM_1);
  221. }
  222. TEST_CASE("I2S memory leaking test", "[i2s]")
  223. {
  224. i2s_config_t master_i2s_config = {
  225. .mode = I2S_MODE_MASTER | I2S_MODE_RX,
  226. .sample_rate = SAMPLE_RATE,
  227. .bits_per_sample = SAMPLE_BITS,
  228. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  229. .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
  230. .dma_buf_count = 6,
  231. .dma_buf_len = 100,
  232. .use_apll = 0,
  233. .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
  234. };
  235. i2s_pin_config_t master_pin_config = {
  236. .bck_io_num = MASTER_BCK_IO,
  237. .ws_io_num = MASTER_WS_IO,
  238. .data_out_num = -1,
  239. .data_in_num = DATA_IN_IO
  240. };
  241. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
  242. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
  243. i2s_driver_uninstall(I2S_NUM_0);
  244. int initial_size = esp_get_free_heap_size();
  245. for(int i=0; i<100; i++) {
  246. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
  247. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
  248. i2s_driver_uninstall(I2S_NUM_0);
  249. TEST_ASSERT(initial_size == esp_get_free_heap_size());
  250. }
  251. vTaskDelay(100 / portTICK_PERIOD_MS);
  252. TEST_ASSERT(initial_size == esp_get_free_heap_size());
  253. }
  254. /*
  255. * The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample
  256. * and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock
  257. * The percentage difference calculated as (mod((obtained clock rate - desired clock rate)/(desired clock rate))) * 100.
  258. */
  259. TEST_CASE("I2S APLL clock variation test", "[i2s]")
  260. {
  261. i2s_pin_config_t pin_config = {
  262. .bck_io_num = MASTER_BCK_IO,
  263. .ws_io_num = MASTER_WS_IO,
  264. .data_out_num = DATA_OUT_IO,
  265. .data_in_num = -1
  266. };
  267. i2s_config_t i2s_config = {
  268. .mode = I2S_MODE_MASTER | I2S_MODE_TX,
  269. .sample_rate = SAMPLE_RATE,
  270. .bits_per_sample = SAMPLE_BITS,
  271. .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
  272. .communication_format = I2S_COMM_FORMAT_I2S,
  273. .dma_buf_count = 6,
  274. .dma_buf_len = 60,
  275. .use_apll = true,
  276. .intr_alloc_flags = 0,
  277. };
  278. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
  279. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
  280. TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
  281. int initial_size = esp_get_free_heap_size();
  282. uint32_t sample_rate_arr[8] = { 10675, 11025, 16000, 22050, 32000, 44100, 48000, 96000 };
  283. int bits_per_sample_arr[3] = { 16, 24, 32 };
  284. for (int i = 0; i < (sizeof(sample_rate_arr)/sizeof(sample_rate_arr[0])); i++) {
  285. for (int j = 0; j < (sizeof(bits_per_sample_arr)/sizeof(bits_per_sample_arr[0])); j++) {
  286. i2s_config.sample_rate = sample_rate_arr[i];
  287. i2s_config.bits_per_sample = bits_per_sample_arr[j];
  288. TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
  289. TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
  290. TEST_ASSERT((fabs((i2s_get_clk(I2S_NUM_0) - sample_rate_arr[i]))/(sample_rate_arr[i]))*100 < PERCENT_DIFF);
  291. TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
  292. TEST_ASSERT(initial_size == esp_get_free_heap_size());
  293. }
  294. }
  295. vTaskDelay(100 / portTICK_PERIOD_MS);
  296. TEST_ASSERT(initial_size == esp_get_free_heap_size());
  297. }