test_rmt.c 25 KB

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  1. /**
  2. * @brief To run this unit test, MAKE SURE GPIO18(TX) is connected to GPIO19(RX)!
  3. *
  4. */
  5. #include <stdio.h>
  6. #include <string.h>
  7. #include "sdkconfig.h"
  8. #include "unity.h"
  9. #include "test_utils.h"
  10. #include "driver/rmt.h"
  11. #include "driver/periph_ctrl.h"
  12. #include "freertos/FreeRTOS.h"
  13. #include "freertos/task.h"
  14. #include "freertos/queue.h"
  15. #include "freertos/semphr.h"
  16. #include "esp_err.h"
  17. #include "esp_log.h"
  18. #include "soc/soc.h"
  19. #include "soc/rmt_periph.h"
  20. #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
  21. //No runners
  22. static const char *TAG = "RMT.test";
  23. #define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */
  24. #define RMT_TX_CARRIER_EN 0 /*!< Disable carrier for self test mode */
  25. #define RMT_TX_CHANNEL 1 /*!< RMT channel for transmitter */
  26. #define RMT_TX_GPIO_NUM 18 /*!< GPIO number for transmitter signal */
  27. #define RMT_RX_CHANNEL 0 /*!< RMT channel for receiver */
  28. #define RMT_RX_GPIO_NUM 19 /*!< GPIO number for receiver */
  29. #define RMT_CLK_DIV 100 /*!< RMT counter clock divider */
  30. #define RMT_TICK_10_US (APB_CLK_FREQ / RMT_CLK_DIV / 100000) /*!< RMT counter value for 10 us */
  31. // NEC protocol related parameters
  32. #define HEADER_HIGH_US 9000 /*!< NEC protocol header: positive 9ms */
  33. #define HEADER_LOW_US 4500 /*!< NEC protocol header: negative 4.5ms*/
  34. #define BIT_ONE_HIGH_US 560 /*!< NEC protocol data bit 1: positive 0.56ms */
  35. #define BIT_ONE_LOW_US (2250 - BIT_ONE_HIGH_US) /*!< NEC protocol data bit 1: negative 1.69ms */
  36. #define BIT_ZERO_HIGH_US 560 /*!< NEC protocol data bit 0: positive 0.56ms */
  37. #define BIT_ZERO_LOW_US (1120 - BIT_ZERO_HIGH_US) /*!< NEC protocol data bit 0: negative 0.56ms */
  38. #define BIT_END 560 /*!< NEC protocol end: positive 0.56ms */
  39. #define BIT_MARGIN 160 /*!< NEC parse margin time */
  40. #define ITEM_DURATION(d) ((d & 0x7fff) * 10 / RMT_TICK_10_US) /*!< Parse duration time from memory register value */
  41. #define DATA_ITEM_NUM 34 /*!< NEC code item number: header + 32bit data + end */
  42. #define RMT_TX_DATA_NUM 50 /*!< NEC tx test data number */
  43. #define RMT_ITEM32_TIMEOUT_US 9500 /*!< RMT receiver timeout value(us) */
  44. /**
  45. * @brief Build register value of waveform for NEC one data bit
  46. */
  47. static inline void fill_item_level(rmt_item32_t *item, int high_us, int low_us)
  48. {
  49. item->level0 = 1;
  50. item->duration0 = (high_us) / 10 * RMT_TICK_10_US;
  51. item->level1 = 0;
  52. item->duration1 = (low_us) / 10 * RMT_TICK_10_US;
  53. }
  54. /**
  55. * @brief Generate NEC header value: active 9ms + negative 4.5ms
  56. */
  57. static void fill_item_header(rmt_item32_t *item)
  58. {
  59. fill_item_level(item, HEADER_HIGH_US, HEADER_LOW_US);
  60. }
  61. /*
  62. * @brief Generate NEC data bit 1: positive 0.56ms + negative 1.69ms
  63. */
  64. static void fill_item_bit_one(rmt_item32_t *item)
  65. {
  66. fill_item_level(item, BIT_ONE_HIGH_US, BIT_ONE_LOW_US);
  67. }
  68. /**
  69. * @brief Generate NEC data bit 0: positive 0.56ms + negative 0.56ms
  70. */
  71. static void fill_item_bit_zero(rmt_item32_t *item)
  72. {
  73. fill_item_level(item, BIT_ZERO_HIGH_US, BIT_ZERO_LOW_US);
  74. }
  75. /**
  76. * @brief Generate NEC end signal: positive 0.56ms
  77. */
  78. static void fill_item_end(rmt_item32_t *item)
  79. {
  80. fill_item_level(item, BIT_END, 0x7fff);
  81. }
  82. /**
  83. * @brief Check whether duration is around target_us
  84. */
  85. static inline bool check_in_range(int duration_ticks, int target_us, int margin_us)
  86. {
  87. if ((ITEM_DURATION(duration_ticks) < (target_us + margin_us)) &&
  88. (ITEM_DURATION(duration_ticks) > (target_us - margin_us))) {
  89. return true;
  90. } else {
  91. return false;
  92. }
  93. }
  94. /**
  95. * @brief Check whether this value represents an NEC header
  96. */
  97. static bool header_if(rmt_item32_t *item)
  98. {
  99. if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
  100. check_in_range(item->duration0, HEADER_HIGH_US, BIT_MARGIN) &&
  101. check_in_range(item->duration1, HEADER_LOW_US, BIT_MARGIN)) {
  102. return true;
  103. }
  104. return false;
  105. }
  106. /**
  107. * @brief Check whether this value represents an NEC data bit 1
  108. */
  109. static bool bit_one_if(rmt_item32_t *item)
  110. {
  111. if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
  112. check_in_range(item->duration0, BIT_ONE_HIGH_US, BIT_MARGIN) &&
  113. check_in_range(item->duration1, BIT_ONE_LOW_US, BIT_MARGIN)) {
  114. return true;
  115. }
  116. return false;
  117. }
  118. /**
  119. * @brief Check whether this value represents an NEC data bit 0
  120. */
  121. static bool bit_zero_if(rmt_item32_t *item)
  122. {
  123. if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
  124. check_in_range(item->duration0, BIT_ZERO_HIGH_US, BIT_MARGIN) &&
  125. check_in_range(item->duration1, BIT_ZERO_LOW_US, BIT_MARGIN)) {
  126. return true;
  127. }
  128. return false;
  129. }
  130. /**
  131. * @brief Parse NEC 32 bit waveform to address and command.
  132. */
  133. static int parse_items(rmt_item32_t *item, int item_num, uint16_t *addr, uint16_t *data)
  134. {
  135. int w_len = item_num;
  136. if (w_len < DATA_ITEM_NUM) {
  137. return -1;
  138. }
  139. int i = 0, j = 0;
  140. if (!header_if(item++)) {
  141. return -1;
  142. }
  143. uint16_t addr_t = 0;
  144. for (j = 0; j < 16; j++) {
  145. if (bit_one_if(item)) {
  146. addr_t |= (1 << j);
  147. } else if (bit_zero_if(item)) {
  148. addr_t |= (0 << j);
  149. } else {
  150. return -1;
  151. }
  152. item++;
  153. i++;
  154. }
  155. uint16_t data_t = 0;
  156. for (j = 0; j < 16; j++) {
  157. if (bit_one_if(item)) {
  158. data_t |= (1 << j);
  159. } else if (bit_zero_if(item)) {
  160. data_t |= (0 << j);
  161. } else {
  162. return -1;
  163. }
  164. item++;
  165. i++;
  166. }
  167. *addr = addr_t;
  168. *data = data_t;
  169. return i;
  170. }
  171. /**
  172. * @brief Build NEC 32bit waveform.
  173. */
  174. static int build_items(int channel, rmt_item32_t *item, int item_num, uint16_t addr, uint16_t cmd_data)
  175. {
  176. int i = 0, j = 0;
  177. if (item_num < DATA_ITEM_NUM) {
  178. return -1;
  179. }
  180. fill_item_header(item++);
  181. i++;
  182. for (j = 0; j < 16; j++) {
  183. if (addr & 0x1) {
  184. fill_item_bit_one(item);
  185. } else {
  186. fill_item_bit_zero(item);
  187. }
  188. item++;
  189. i++;
  190. addr >>= 1;
  191. }
  192. for (j = 0; j < 16; j++) {
  193. if (cmd_data & 0x1) {
  194. fill_item_bit_one(item);
  195. } else {
  196. fill_item_bit_zero(item);
  197. }
  198. item++;
  199. i++;
  200. cmd_data >>= 1;
  201. }
  202. fill_item_end(item);
  203. i++;
  204. return i;
  205. }
  206. static void set_tx_data(int tx_channel, uint16_t cmd, uint16_t addr, int item_num, rmt_item32_t *item, int offset)
  207. {
  208. while (1) {
  209. int i = build_items(tx_channel, item + offset, item_num - offset, ((~addr) << 8) | addr, cmd);
  210. if (i < 0) {
  211. break;
  212. }
  213. cmd++;
  214. addr++;
  215. offset += i;
  216. }
  217. }
  218. static int get_rx_data(RingbufHandle_t rb)
  219. {
  220. uint16_t tmp = 0;
  221. while (rb) {
  222. size_t rx_size = 0;
  223. rmt_item32_t *rx_item = (rmt_item32_t *)xRingbufferReceive(rb, &rx_size, 1000);
  224. if (rx_item) {
  225. uint16_t rmt_addr;
  226. uint16_t rmt_cmd;
  227. int rx_offset = 0;
  228. while (1) {
  229. int res = parse_items(rx_item + rx_offset, rx_size / 4 - rx_offset, &rmt_addr, &rmt_cmd);
  230. if (res > 0) {
  231. rx_offset += res + 1;
  232. ESP_LOGI(TAG, "receive cmd %d from addr %d", rmt_cmd, rmt_addr & 0xFF);
  233. TEST_ASSERT(rmt_cmd == tmp);
  234. tmp++;
  235. } else {
  236. break;
  237. }
  238. }
  239. vRingbufferReturnItem(rb, (void *)rx_item);
  240. } else {
  241. break;
  242. }
  243. }
  244. return tmp;
  245. }
  246. /**
  247. * @brief RMT transmitter initialization
  248. */
  249. static void tx_init(void)
  250. {
  251. // the sender once it send something, its frq is 38kHz, and the duty cycle is 50%
  252. rmt_tx_config_t tx_cfg = {
  253. .loop_en = false,
  254. .carrier_duty_percent = 50,
  255. .carrier_freq_hz = 38000,
  256. .carrier_level = 1,
  257. .carrier_en = RMT_TX_CARRIER_EN,
  258. .idle_level = 0,
  259. .idle_output_en = true,
  260. };
  261. rmt_config_t rmt_tx = {
  262. .channel = RMT_TX_CHANNEL,
  263. .gpio_num = RMT_TX_GPIO_NUM,
  264. .mem_block_num = 1,
  265. .clk_div = RMT_CLK_DIV,
  266. .tx_config = tx_cfg,
  267. .rmt_mode = 0,
  268. };
  269. rmt_config(&rmt_tx);
  270. rmt_driver_install(rmt_tx.channel, 0, 0);
  271. }
  272. /**
  273. * @brief RMT receiver initialization
  274. */
  275. static void rx_init(void)
  276. {
  277. rmt_rx_config_t rx_cfg = {
  278. .filter_en = true,
  279. .filter_ticks_thresh = 100,
  280. .idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US),
  281. };
  282. rmt_config_t rmt_rx = {
  283. .channel = RMT_RX_CHANNEL,
  284. .gpio_num = RMT_RX_GPIO_NUM,
  285. .clk_div = RMT_CLK_DIV,
  286. .mem_block_num = 1,
  287. .rmt_mode = RMT_MODE_RX,
  288. .rx_config = rx_cfg,
  289. };
  290. rmt_config(&rmt_rx);
  291. rmt_driver_install(rmt_rx.channel, (sizeof(rmt_item32_t) * DATA_ITEM_NUM * (RMT_TX_DATA_NUM + 6)), 0);
  292. }
  293. //A sample case to test if sending 63 data will cause crash in error interrupt.
  294. TEST_CASE("RMT tx test", "[rmt][test_env=UT_T1_RMT]")
  295. {
  296. tx_init();
  297. rmt_item32_t *items = (rmt_item32_t*)malloc(sizeof(rmt_item32_t) * 63);
  298. for(int i = 0; i < 63; i++) {
  299. items[i] = (rmt_item32_t){{{200, 1, 200, 0}}};
  300. }
  301. TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
  302. 63, /* Number of items */
  303. 1 /* wait till done */));
  304. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  305. free(items);
  306. }
  307. TEST_CASE("RMT init config", "[rmt][test_env=UT_T1_RMT]")
  308. {
  309. // tx settings
  310. rmt_tx_config_t tx_cfg = {
  311. .loop_en = false,
  312. .carrier_duty_percent = 50,
  313. .carrier_freq_hz = 38000,
  314. .carrier_level = 1,
  315. .carrier_en = RMT_TX_CARRIER_EN,
  316. .idle_level = 0,
  317. .idle_output_en = true,
  318. };
  319. rmt_config_t rmt_tx = {
  320. .channel = RMT_TX_CHANNEL,
  321. .gpio_num = RMT_TX_GPIO_NUM,
  322. .mem_block_num = 1,
  323. .clk_div = RMT_CLK_DIV,
  324. .tx_config = tx_cfg,
  325. };
  326. TEST_ESP_OK(rmt_config(&rmt_tx));
  327. TEST_ESP_OK(rmt_driver_install(rmt_tx.channel, 0, 0));
  328. TEST_ESP_OK(rmt_driver_uninstall(rmt_tx.channel));
  329. //rx settings
  330. rmt_rx_config_t rx_cfg = {
  331. .filter_en = true,
  332. .filter_ticks_thresh = 100,
  333. .idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US),
  334. };
  335. rmt_config_t rmt_rx = {
  336. .channel = RMT_RX_CHANNEL,
  337. .gpio_num = RMT_RX_GPIO_NUM,
  338. .clk_div = RMT_CLK_DIV,
  339. .mem_block_num = 1,
  340. .rmt_mode = RMT_MODE_RX,
  341. .rx_config = rx_cfg,
  342. };
  343. TEST_ESP_OK(rmt_config(&rmt_rx));
  344. TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
  345. TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
  346. //error param setting
  347. rmt_config_t temp_rmt_rx1 = {
  348. .channel = 2,
  349. .gpio_num = 15,
  350. .clk_div = RMT_CLK_DIV,
  351. .mem_block_num = 1,
  352. .rmt_mode = RMT_MODE_RX,
  353. .rx_config = rx_cfg,
  354. };
  355. rmt_config_t temp_rmt_rx2 = temp_rmt_rx1;
  356. temp_rmt_rx2.clk_div = 0; // only invalid parameter to test
  357. TEST_ASSERT(rmt_config(&temp_rmt_rx2) == ESP_ERR_INVALID_ARG);
  358. temp_rmt_rx2 = temp_rmt_rx1;
  359. temp_rmt_rx2.channel = RMT_CHANNEL_MAX;
  360. TEST_ASSERT(rmt_config(&temp_rmt_rx2) == ESP_ERR_INVALID_ARG);
  361. temp_rmt_rx2 = temp_rmt_rx1;
  362. temp_rmt_rx2.channel = 2;
  363. temp_rmt_rx2.mem_block_num = 8;
  364. TEST_ASSERT(rmt_config(&temp_rmt_rx2) == ESP_ERR_INVALID_ARG);
  365. }
  366. TEST_CASE("RMT init set function", "[rmt][test_env=UT_T1_RMT]")
  367. {
  368. rmt_channel_t channel = 7;
  369. TEST_ESP_OK(rmt_driver_install(channel, 0, 0));
  370. TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, RMT_RX_GPIO_NUM));
  371. TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
  372. TEST_ESP_OK(rmt_set_mem_block_num(channel, 1));
  373. TEST_ESP_OK(rmt_set_rx_filter(channel, 1, 100));
  374. TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2));
  375. TEST_ESP_OK(rmt_driver_uninstall(channel));
  376. }
  377. // need to make sure its phenomenon by logic analyzer, can't run in CI
  378. TEST_CASE("RMT clock devider, clock source set(logic analyzer)", "[rmt][ignore]")
  379. {
  380. uint8_t div_cnt;
  381. rmt_source_clk_t src_clk;
  382. rmt_config_t rmt_tx;
  383. rmt_tx.channel = RMT_TX_CHANNEL;
  384. rmt_tx.mem_block_num = 1;
  385. rmt_tx.gpio_num = RMT_TX_GPIO_NUM;
  386. rmt_tx.clk_div = RMT_CLK_DIV;
  387. rmt_tx.tx_config.loop_en = true;
  388. rmt_tx.tx_config.carrier_duty_percent = 50;
  389. rmt_tx.tx_config.carrier_freq_hz = 38000;
  390. rmt_tx.tx_config.carrier_level = 1;
  391. rmt_tx.tx_config.carrier_en = RMT_TX_CARRIER_EN;
  392. rmt_tx.tx_config.idle_level = 0;
  393. rmt_tx.tx_config.idle_output_en = true;
  394. rmt_tx.rmt_mode = RMT_MODE_TX;
  395. TEST_ESP_OK(rmt_config(&rmt_tx));
  396. TEST_ESP_OK(rmt_driver_install(rmt_tx.channel, 0, 0));
  397. TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
  398. TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
  399. vTaskDelay(1000 / portTICK_PERIOD_MS);
  400. // reset it and check it
  401. TEST_ESP_OK(rmt_set_clk_div(RMT_TX_CHANNEL, 160));
  402. TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
  403. vTaskDelay(1000 / portTICK_PERIOD_MS);
  404. TEST_ESP_OK(rmt_set_source_clk(RMT_TX_CHANNEL, RMT_BASECLK_APB));
  405. TEST_ESP_OK(rmt_get_source_clk(RMT_TX_CHANNEL, &src_clk));
  406. TEST_ASSERT_EQUAL_UINT8(div_cnt, 160);
  407. TEST_ASSERT_EQUAL_INT(src_clk, RMT_BASECLK_APB);
  408. TEST_ESP_OK(rmt_driver_uninstall(rmt_tx.channel));
  409. }
  410. TEST_CASE("RMT rx set and get properties", "[rmt][test_env=UT_T1_RMT]")
  411. {
  412. rmt_channel_t channel = RMT_RX_CHANNEL;
  413. uint8_t memNum;
  414. uint8_t div_cnt;
  415. uint16_t idleThreshold;
  416. rmt_mem_owner_t owner;
  417. rx_init();
  418. TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
  419. TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
  420. TEST_ESP_OK(rmt_get_rx_idle_thresh(channel, &idleThreshold));
  421. TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
  422. TEST_ASSERT_EQUAL_UINT8(memNum, 1);
  423. TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US));
  424. TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, 22));
  425. TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
  426. TEST_ESP_OK(rmt_set_mem_block_num(channel, 2));
  427. TEST_ESP_OK(rmt_set_rx_filter(channel, 1, 100));
  428. TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2));
  429. TEST_ESP_OK(rmt_set_memory_owner(channel, RMT_MEM_OWNER_RX));
  430. TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
  431. TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
  432. TEST_ESP_OK(rmt_get_rx_idle_thresh(channel, &idleThreshold));
  433. TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
  434. TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV * 2);
  435. TEST_ASSERT_EQUAL_UINT8(memNum, 2);
  436. TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2);
  437. TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_RX);
  438. TEST_ESP_OK(rmt_driver_uninstall(channel));
  439. }
  440. TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
  441. {
  442. rmt_channel_t channel = RMT_TX_CHANNEL;
  443. uint8_t memNum;
  444. uint8_t div_cnt;
  445. bool loop_en;
  446. rmt_mem_owner_t owner;
  447. tx_init();
  448. TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
  449. TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
  450. TEST_ESP_OK(rmt_get_tx_loop_mode(channel, &loop_en));
  451. TEST_ASSERT_EQUAL_INT8(loop_en, 0);
  452. TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
  453. TEST_ASSERT_EQUAL_UINT8(memNum, 1);
  454. //reset by "set"
  455. TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_TX, RMT_TX_GPIO_NUM));
  456. TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
  457. TEST_ESP_OK(rmt_set_mem_block_num(channel, 2));
  458. TEST_ESP_OK(rmt_set_tx_loop_mode(channel, 1));
  459. TEST_ESP_OK(rmt_set_tx_carrier(channel, 0, 1, 0, 1));
  460. TEST_ESP_OK(rmt_set_idle_level(channel, 1, 0));
  461. TEST_ESP_OK(rmt_set_memory_owner(channel, RMT_MEM_OWNER_TX));
  462. TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
  463. TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
  464. TEST_ESP_OK(rmt_get_tx_loop_mode(channel, &loop_en));
  465. TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
  466. TEST_ASSERT_EQUAL_INT8(loop_en, 1);
  467. TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV * 2);
  468. TEST_ASSERT_EQUAL_UINT8(memNum, 2);
  469. TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_TX);
  470. rmt_item32_t item;
  471. item.duration0 = 300 / 10 * RMT_TICK_10_US; //300us
  472. item.level0 = 1;
  473. item.duration1 = 0;
  474. item.level1 = 0;
  475. for (int i = 0; i < 100; i++) {
  476. TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, &item,
  477. 1, /* Number of items */
  478. 1 /* wait till done */));
  479. vTaskDelay(10 / portTICK_PERIOD_MS); //every 10ms to write the item
  480. }
  481. TEST_ESP_OK(rmt_driver_uninstall(channel));
  482. }
  483. TEST_CASE("RMT use multi channel", "[rmt][test_env=UT_T1_RMT]")
  484. {
  485. rmt_tx_config_t tx_cfg = {
  486. .loop_en = true, // set it as true
  487. .carrier_duty_percent = 50,
  488. .carrier_freq_hz = 38000,
  489. .carrier_level = 1,
  490. .carrier_en = RMT_TX_CARRIER_EN,
  491. .idle_level = 0,
  492. .idle_output_en = true,
  493. };
  494. rmt_config_t rmt_tx1 = {
  495. .channel = RMT_TX_CHANNEL,
  496. .gpio_num = RMT_TX_GPIO_NUM,
  497. .mem_block_num = 4,
  498. .clk_div = RMT_CLK_DIV,
  499. .tx_config = tx_cfg,
  500. .rmt_mode = 0,
  501. };
  502. rmt_config(&rmt_tx1);
  503. rmt_driver_install(rmt_tx1.channel, 0, 0);
  504. rmt_config_t rmt_tx2 = rmt_tx1;
  505. rmt_tx2.channel = 2;
  506. rmt_config(&rmt_tx2);
  507. rmt_driver_install(rmt_tx2.channel, 0, 0);
  508. rmt_config_t rmt_tx3 = rmt_tx1;
  509. rmt_tx3.channel = 7;
  510. rmt_tx3.mem_block_num = 1;
  511. rmt_config(&rmt_tx3);
  512. rmt_driver_install(rmt_tx3.channel, 0, 0);
  513. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  514. TEST_ESP_OK(rmt_driver_uninstall(2));
  515. TEST_ESP_OK(rmt_driver_uninstall(7));
  516. }
  517. TEST_CASE("RMT memory test", "[rmt][test_env=UT_T1_RMT]")
  518. {
  519. rmt_config_t rmt_rx;
  520. rmt_rx.channel = RMT_RX_CHANNEL;
  521. rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
  522. rmt_rx.clk_div = RMT_CLK_DIV;
  523. rmt_rx.mem_block_num = 1;
  524. rmt_rx.rmt_mode = RMT_MODE_RX;
  525. rmt_rx.rx_config.filter_en = true;
  526. rmt_rx.rx_config.filter_ticks_thresh = 100;
  527. rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
  528. TEST_ESP_OK(rmt_config(&rmt_rx));
  529. for (int i = 0; i < 100; i++) {
  530. TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
  531. TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
  532. }
  533. }
  534. // RMT channel num and memory block relationship
  535. TEST_CASE("RMT memory block test", "[rmt][test_env=UT_T1_RMT]")
  536. {
  537. rmt_channel_t channel = 0;
  538. rmt_config_t rmt_rx;
  539. rmt_rx.channel = channel;
  540. rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
  541. rmt_rx.clk_div = RMT_CLK_DIV;
  542. rmt_rx.mem_block_num = 1;
  543. rmt_rx.rmt_mode = RMT_MODE_RX;
  544. rmt_rx.rx_config.filter_en = true;
  545. rmt_rx.rx_config.filter_ticks_thresh = 100;
  546. rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
  547. TEST_ESP_OK(rmt_config(&rmt_rx));
  548. TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
  549. TEST_ESP_OK(rmt_set_mem_block_num(channel, 8));
  550. TEST_ASSERT(rmt_set_mem_block_num(channel, 9) == ESP_ERR_INVALID_ARG);
  551. TEST_ASSERT(rmt_set_mem_block_num(channel, -1) == ESP_ERR_INVALID_ARG);
  552. TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
  553. rmt_rx.channel = 7;
  554. TEST_ESP_OK(rmt_config(&rmt_rx));
  555. TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
  556. TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, 2) == ESP_ERR_INVALID_ARG);
  557. TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, -1) == ESP_ERR_INVALID_ARG);
  558. TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
  559. }
  560. TEST_CASE("RMT send waveform(logic analyzer)", "[rmt][test_env=UT_T1_RMT][ignore]")
  561. {
  562. tx_init();
  563. rmt_item32_t items[1];
  564. items[0].duration0 = 300 / 10 * RMT_TICK_10_US; //300us
  565. items[0].level0 = 1;
  566. for (int i = 0; i < 500; i++) {
  567. TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
  568. 1, /* Number of items */
  569. 1 /* wait till done */));
  570. vTaskDelay(10 / portTICK_PERIOD_MS); //every 10ms to write the item
  571. }
  572. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  573. }
  574. TEST_CASE("RMT basic TX and RX", "[rmt][test_env=UT_T1_RMT]")
  575. {
  576. rx_init();
  577. RingbufHandle_t rb = NULL;
  578. rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
  579. rmt_rx_start(RMT_RX_CHANNEL, 1);
  580. ESP_LOGI(TAG, "Star receiving RMT data...");
  581. tx_init();
  582. uint16_t cmd = 0x0;
  583. uint16_t addr = 0x11;
  584. int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
  585. rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
  586. vTaskDelay(pdMS_TO_TICKS(2000));
  587. ESP_LOGI(TAG, "Sending RMT data...");
  588. // send data
  589. set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
  590. // wait until tx done
  591. rmt_write_items(RMT_TX_CHANNEL, items, num_items, 1);
  592. free(items);
  593. // receive data
  594. uint16_t tmp = get_rx_data(rb);
  595. TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
  596. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  597. TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
  598. }
  599. TEST_CASE("RMT TX write item wait some ticks", "[rmt][test_env=UT_T1_RMT]")
  600. {
  601. rx_init();
  602. RingbufHandle_t rb = NULL;
  603. rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
  604. rmt_rx_start(RMT_RX_CHANNEL, 1);
  605. ESP_LOGI(TAG, "Star receiving RMT data...");
  606. tx_init();
  607. uint16_t cmd = 0x0;
  608. uint16_t addr = 0x11;
  609. int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
  610. rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
  611. vTaskDelay(pdMS_TO_TICKS(2000));
  612. ESP_LOGI(TAG, "Sending RMT data...");
  613. // send data
  614. set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
  615. rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
  616. rmt_wait_tx_done(RMT_TX_CHANNEL, portMAX_DELAY);
  617. free(items);
  618. // receive data
  619. uint16_t tmp = get_rx_data(rb);
  620. TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
  621. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  622. TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
  623. }
  624. TEST_CASE("RMT TX stop test", "[rmt][test_env=UT_T1_RMT]")
  625. {
  626. rx_init();
  627. RingbufHandle_t rb = NULL;
  628. rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
  629. rmt_rx_start(RMT_RX_CHANNEL, 1);
  630. ESP_LOGI(TAG, "Star receiving RMT data...");
  631. tx_init();
  632. uint16_t cmd = 0x0;
  633. uint16_t addr = 0x11;
  634. int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
  635. rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
  636. vTaskDelay(pdMS_TO_TICKS(2000));
  637. ESP_LOGI(TAG, "Sending RMT data...");
  638. // send data
  639. set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
  640. rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
  641. vTaskDelay(1000 / portTICK_PERIOD_MS);
  642. rmt_tx_stop(RMT_TX_CHANNEL);
  643. free(items);
  644. // receive data
  645. uint16_t tmp = get_rx_data(rb);
  646. TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
  647. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  648. TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
  649. }
  650. TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
  651. {
  652. rmt_tx_config_t tx_cfg = {
  653. .loop_en = true, // set it as true
  654. .carrier_duty_percent = 50,
  655. .carrier_freq_hz = 38000,
  656. .carrier_level = 1,
  657. .carrier_en = RMT_TX_CARRIER_EN,
  658. .idle_level = 0,
  659. .idle_output_en = true,
  660. };
  661. rmt_config_t rmt_tx = {
  662. .channel = RMT_TX_CHANNEL,
  663. .gpio_num = RMT_TX_GPIO_NUM,
  664. .mem_block_num = 1,
  665. .clk_div = RMT_CLK_DIV,
  666. .tx_config = tx_cfg,
  667. .rmt_mode = 0,
  668. };
  669. rmt_config(&rmt_tx);
  670. rmt_driver_install(rmt_tx.channel, 0, 0);
  671. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  672. int rx_channel = RMT_RX_CHANNEL;
  673. rx_init();
  674. RingbufHandle_t rb = NULL;
  675. rmt_get_ringbuf_handle(rx_channel, &rb);
  676. rmt_rx_start(rx_channel, 1);
  677. vTaskDelay(10);
  678. tx_init();
  679. int tx_channel = RMT_TX_CHANNEL;
  680. int tx_num = RMT_TX_DATA_NUM;
  681. ESP_LOGI(TAG, "RMT TX DATA");
  682. size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
  683. rmt_item32_t *item = (rmt_item32_t *)malloc(size);
  684. int item_num = DATA_ITEM_NUM * tx_num;
  685. memset((void *)item, 0, size);
  686. int offset = 0;
  687. uint16_t cmd = 0x0;
  688. uint16_t addr = 0x11;
  689. // send data
  690. set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
  691. rmt_write_items(tx_channel, item, item_num, 0);
  692. vTaskDelay(1000 / portTICK_PERIOD_MS);
  693. rmt_tx_stop(tx_channel);
  694. free(item);
  695. // receive data
  696. uint16_t tmp = get_rx_data(rb);
  697. TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
  698. TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
  699. TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
  700. }
  701. #endif //DISABLED_FOR_TARGETS(ESP32S2BETA)