esp_efuse_table.c 33 KB

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  1. // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at",
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License
  14. #include "sdkconfig.h"
  15. #include "esp_efuse.h"
  16. #include <assert.h>
  17. #include "esp_efuse_table.h"
  18. // md5_digest_table fe80e03d1417e5757ef89923f8d01d33
  19. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  20. // If you want to change some fields, you need to change esp_efuse_table.csv file
  21. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  22. // To show efuse_table run the command 'show_efuse_table'.
  23. static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
  24. {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
  25. };
  26. static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
  27. {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
  28. };
  29. static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
  30. {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL,
  31. };
  32. static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  33. {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT,
  34. };
  35. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  36. {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0,
  37. };
  38. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  39. {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1,
  40. };
  41. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  42. {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2,
  43. };
  44. static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
  45. {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0,
  46. };
  47. static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
  48. {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1,
  49. };
  50. static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
  51. {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2,
  52. };
  53. static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
  54. {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3,
  55. };
  56. static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
  57. {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4,
  58. };
  59. static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
  60. {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5,
  61. };
  62. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
  63. {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN,
  64. };
  65. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  66. {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
  67. };
  68. static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
  69. {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
  70. };
  71. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  72. {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS,
  73. };
  74. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
  75. {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1,
  76. };
  77. static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
  78. {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA,
  79. };
  80. static const esp_efuse_desc_t WR_DIS_KEY0[] = {
  81. {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0,
  82. };
  83. static const esp_efuse_desc_t WR_DIS_KEY1[] = {
  84. {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1,
  85. };
  86. static const esp_efuse_desc_t WR_DIS_KEY2[] = {
  87. {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2,
  88. };
  89. static const esp_efuse_desc_t WR_DIS_KEY3[] = {
  90. {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3,
  91. };
  92. static const esp_efuse_desc_t WR_DIS_KEY4[] = {
  93. {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4,
  94. };
  95. static const esp_efuse_desc_t WR_DIS_KEY5[] = {
  96. {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5,
  97. };
  98. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
  99. {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
  100. };
  101. static const esp_efuse_desc_t RD_DIS_KEY0[] = {
  102. {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0,
  103. };
  104. static const esp_efuse_desc_t RD_DIS_KEY1[] = {
  105. {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1,
  106. };
  107. static const esp_efuse_desc_t RD_DIS_KEY2[] = {
  108. {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2,
  109. };
  110. static const esp_efuse_desc_t RD_DIS_KEY3[] = {
  111. {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3,
  112. };
  113. static const esp_efuse_desc_t RD_DIS_KEY4[] = {
  114. {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4,
  115. };
  116. static const esp_efuse_desc_t RD_DIS_KEY5[] = {
  117. {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5,
  118. };
  119. static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
  120. {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
  121. };
  122. static const esp_efuse_desc_t DIS_ICACHE[] = {
  123. {EFUSE_BLK0, 40, 1}, // Disable Icache,
  124. };
  125. static const esp_efuse_desc_t DIS_USB_JTAG[] = {
  126. {EFUSE_BLK0, 41, 1}, // Disable USB JTAG,
  127. };
  128. static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
  129. {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode,
  130. };
  131. static const esp_efuse_desc_t DIS_USB_DEVICE[] = {
  132. {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE,
  133. };
  134. static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
  135. {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
  136. };
  137. static const esp_efuse_desc_t DIS_USB[] = {
  138. {EFUSE_BLK0, 45, 1}, // Disable USB function,
  139. };
  140. static const esp_efuse_desc_t DIS_CAN[] = {
  141. {EFUSE_BLK0, 46, 1}, // Disable CAN function,
  142. };
  143. static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
  144. {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.,
  145. };
  146. static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
  147. {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.,
  148. };
  149. static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
  150. {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently.,
  151. };
  152. static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  153. {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes.,
  154. };
  155. static const esp_efuse_desc_t USB_DREFH[] = {
  156. {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.,
  157. };
  158. static const esp_efuse_desc_t USB_DREFL[] = {
  159. {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.,
  160. };
  161. static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
  162. {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins,
  163. };
  164. static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
  165. {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio,
  166. };
  167. static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = {
  168. {EFUSE_BLK0, 59, 2}, // Enable btlc gpio,
  169. };
  170. static const esp_efuse_desc_t POWERGLITCH_EN[] = {
  171. {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function,
  172. };
  173. static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = {
  174. {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch,
  175. };
  176. static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
  177. {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold,
  178. };
  179. static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
  180. {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
  181. };
  182. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
  183. {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key,
  184. };
  185. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
  186. {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key,
  187. };
  188. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
  189. {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key,
  190. };
  191. static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
  192. {EFUSE_BLK0, 88, 4}, // Key0 purpose,
  193. };
  194. static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
  195. {EFUSE_BLK0, 92, 4}, // Key1 purpose,
  196. };
  197. static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
  198. {EFUSE_BLK0, 96, 4}, // Key2 purpose,
  199. };
  200. static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
  201. {EFUSE_BLK0, 100, 4}, // Key3 purpose,
  202. };
  203. static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
  204. {EFUSE_BLK0, 104, 4}, // Key4 purpose,
  205. };
  206. static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
  207. {EFUSE_BLK0, 108, 4}, // Key5 purpose,
  208. };
  209. static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
  210. {EFUSE_BLK0, 116, 1}, // Secure boot enable,
  211. };
  212. static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  213. {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke,
  214. };
  215. static const esp_efuse_desc_t FLASH_TPUW[] = {
  216. {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
  217. };
  218. static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
  219. {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
  220. };
  221. static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
  222. {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
  223. };
  224. static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
  225. {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1,
  226. };
  227. static const esp_efuse_desc_t FLASH_ECC_MODE[] = {
  228. {EFUSE_BLK0, 131, 1}, // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode,
  229. };
  230. static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
  231. {EFUSE_BLK0, 132, 1}, // Disable download through USB,
  232. };
  233. static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
  234. {EFUSE_BLK0, 133, 1}, // Enable security download mode,
  235. };
  236. static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
  237. {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.,
  238. };
  239. static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
  240. {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
  241. };
  242. static const esp_efuse_desc_t FLASH_TYPE[] = {
  243. {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
  244. };
  245. static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
  246. {EFUSE_BLK0, 138, 2}, // Flash page size,
  247. };
  248. static const esp_efuse_desc_t FLASH_ECC_EN[] = {
  249. {EFUSE_BLK0, 140, 1}, // Enable ECC for flash boot,
  250. };
  251. static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
  252. {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot,
  253. };
  254. static const esp_efuse_desc_t SECURE_VERSION[] = {
  255. {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
  256. };
  257. static const esp_efuse_desc_t MAC_FACTORY[] = {
  258. {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
  259. {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
  260. {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2],
  261. {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3],
  262. {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4],
  263. {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
  264. };
  265. static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
  266. {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
  267. };
  268. static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
  269. {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
  270. };
  271. static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
  272. {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
  273. };
  274. static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
  275. {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
  276. };
  277. static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
  278. {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
  279. };
  280. static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
  281. {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
  282. };
  283. static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
  284. {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
  285. };
  286. static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
  287. {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
  288. };
  289. static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
  290. {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
  291. };
  292. static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
  293. {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
  294. };
  295. static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
  296. {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
  297. };
  298. static const esp_efuse_desc_t WAFER_VERSION[] = {
  299. {EFUSE_BLK1, 114, 3}, // WAFER version,
  300. };
  301. static const esp_efuse_desc_t PKG_VERSION[] = {
  302. {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3,
  303. };
  304. static const esp_efuse_desc_t BLOCK1_VERSION[] = {
  305. {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
  306. };
  307. static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
  308. {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
  309. };
  310. static const esp_efuse_desc_t BLOCK2_VERSION[] = {
  311. {EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
  312. };
  313. static const esp_efuse_desc_t TEMP_CALIB[] = {
  314. {EFUSE_BLK2, 131, 9}, // Temperature calibration data,
  315. };
  316. static const esp_efuse_desc_t OCODE[] = {
  317. {EFUSE_BLK2, 140, 8}, // ADC OCode,
  318. };
  319. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
  320. {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0,
  321. };
  322. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
  323. {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1,
  324. };
  325. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
  326. {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2,
  327. };
  328. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
  329. {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3,
  330. };
  331. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
  332. {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0,
  333. };
  334. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
  335. {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1,
  336. };
  337. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
  338. {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2,
  339. };
  340. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
  341. {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3,
  342. };
  343. static const esp_efuse_desc_t USER_DATA[] = {
  344. {EFUSE_BLK3, 0, 256}, // User data,
  345. };
  346. static const esp_efuse_desc_t KEY0[] = {
  347. {EFUSE_BLK4, 0, 256}, // Key0 or user data,
  348. };
  349. static const esp_efuse_desc_t KEY1[] = {
  350. {EFUSE_BLK5, 0, 256}, // Key1 or user data,
  351. };
  352. static const esp_efuse_desc_t KEY2[] = {
  353. {EFUSE_BLK6, 0, 256}, // Key2 or user data,
  354. };
  355. static const esp_efuse_desc_t KEY3[] = {
  356. {EFUSE_BLK7, 0, 256}, // Key3 or user data,
  357. };
  358. static const esp_efuse_desc_t KEY4[] = {
  359. {EFUSE_BLK8, 0, 256}, // Key4 or user data,
  360. };
  361. static const esp_efuse_desc_t KEY5[] = {
  362. {EFUSE_BLK9, 0, 256}, // Key5 or user data,
  363. };
  364. static const esp_efuse_desc_t SYS_DATA_PART2[] = {
  365. {EFUSE_BLK10, 0, 256}, // System configuration,
  366. };
  367. static const esp_efuse_desc_t K_RTC_LDO[] = {
  368. {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO,
  369. };
  370. static const esp_efuse_desc_t K_DIG_LDO[] = {
  371. {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO,
  372. };
  373. static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
  374. {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20,
  375. };
  376. static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
  377. {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20,
  378. };
  379. static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
  380. {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt,
  381. };
  382. static const esp_efuse_desc_t THRES_HVT[] = {
  383. {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt,
  384. };
  385. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
  386. &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
  387. NULL
  388. };
  389. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
  390. &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
  391. NULL
  392. };
  393. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
  394. &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL
  395. NULL
  396. };
  397. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  398. &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT
  399. NULL
  400. };
  401. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  402. &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0
  403. NULL
  404. };
  405. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  406. &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1
  407. NULL
  408. };
  409. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  410. &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2
  411. NULL
  412. };
  413. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
  414. &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0
  415. NULL
  416. };
  417. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
  418. &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1
  419. NULL
  420. };
  421. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
  422. &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2
  423. NULL
  424. };
  425. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
  426. &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3
  427. NULL
  428. };
  429. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
  430. &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4
  431. NULL
  432. };
  433. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
  434. &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5
  435. NULL
  436. };
  437. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
  438. &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN
  439. NULL
  440. };
  441. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  442. &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
  443. NULL
  444. };
  445. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
  446. &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
  447. NULL
  448. };
  449. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  450. &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
  451. NULL
  452. };
  453. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
  454. &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1
  455. NULL
  456. };
  457. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
  458. &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA
  459. NULL
  460. };
  461. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
  462. &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0
  463. NULL
  464. };
  465. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
  466. &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1
  467. NULL
  468. };
  469. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
  470. &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2
  471. NULL
  472. };
  473. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
  474. &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3
  475. NULL
  476. };
  477. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
  478. &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4
  479. NULL
  480. };
  481. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
  482. &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5
  483. NULL
  484. };
  485. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
  486. &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2
  487. NULL
  488. };
  489. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
  490. &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0
  491. NULL
  492. };
  493. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
  494. &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1
  495. NULL
  496. };
  497. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
  498. &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2
  499. NULL
  500. };
  501. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
  502. &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3
  503. NULL
  504. };
  505. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
  506. &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4
  507. NULL
  508. };
  509. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
  510. &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5
  511. NULL
  512. };
  513. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
  514. &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2
  515. NULL
  516. };
  517. const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
  518. &DIS_ICACHE[0], // Disable Icache
  519. NULL
  520. };
  521. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
  522. &DIS_USB_JTAG[0], // Disable USB JTAG
  523. NULL
  524. };
  525. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
  526. &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode
  527. NULL
  528. };
  529. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = {
  530. &DIS_USB_DEVICE[0], // Disable USB_DEVICE
  531. NULL
  532. };
  533. const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
  534. &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function
  535. NULL
  536. };
  537. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
  538. &DIS_USB[0], // Disable USB function
  539. NULL
  540. };
  541. const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
  542. &DIS_CAN[0], // Disable CAN function
  543. NULL
  544. };
  545. const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
  546. &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
  547. NULL
  548. };
  549. const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
  550. &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
  551. NULL
  552. };
  553. const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
  554. &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently.
  555. NULL
  556. };
  557. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  558. &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes.
  559. NULL
  560. };
  561. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = {
  562. &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
  563. NULL
  564. };
  565. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = {
  566. &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
  567. NULL
  568. };
  569. const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
  570. &USB_EXCHG_PINS[0], // Exchange D+ D- pins
  571. NULL
  572. };
  573. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
  574. &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio
  575. NULL
  576. };
  577. const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = {
  578. &BTLC_GPIO_ENABLE[0], // Enable btlc gpio
  579. NULL
  580. };
  581. const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
  582. &POWERGLITCH_EN[0], // Set this bit to enable power glitch function
  583. NULL
  584. };
  585. const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = {
  586. &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch
  587. NULL
  588. };
  589. const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
  590. &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold
  591. NULL
  592. };
  593. const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
  594. &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
  595. NULL
  596. };
  597. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
  598. &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key
  599. NULL
  600. };
  601. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
  602. &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key
  603. NULL
  604. };
  605. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
  606. &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key
  607. NULL
  608. };
  609. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
  610. &KEY_PURPOSE_0[0], // Key0 purpose
  611. NULL
  612. };
  613. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
  614. &KEY_PURPOSE_1[0], // Key1 purpose
  615. NULL
  616. };
  617. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
  618. &KEY_PURPOSE_2[0], // Key2 purpose
  619. NULL
  620. };
  621. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
  622. &KEY_PURPOSE_3[0], // Key3 purpose
  623. NULL
  624. };
  625. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
  626. &KEY_PURPOSE_4[0], // Key4 purpose
  627. NULL
  628. };
  629. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
  630. &KEY_PURPOSE_5[0], // Key5 purpose
  631. NULL
  632. };
  633. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
  634. &SECURE_BOOT_EN[0], // Secure boot enable
  635. NULL
  636. };
  637. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  638. &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke
  639. NULL
  640. };
  641. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
  642. &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
  643. NULL
  644. };
  645. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
  646. &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
  647. NULL
  648. };
  649. const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
  650. &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
  651. NULL
  652. };
  653. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
  654. &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1
  655. NULL
  656. };
  657. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = {
  658. &FLASH_ECC_MODE[0], // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode
  659. NULL
  660. };
  661. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
  662. &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
  663. NULL
  664. };
  665. const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
  666. &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
  667. NULL
  668. };
  669. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
  670. &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
  671. NULL
  672. };
  673. const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
  674. &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
  675. NULL
  676. };
  677. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
  678. &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line
  679. NULL
  680. };
  681. const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
  682. &FLASH_PAGE_SIZE[0], // Flash page size
  683. NULL
  684. };
  685. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
  686. &FLASH_ECC_EN[0], // Enable ECC for flash boot
  687. NULL
  688. };
  689. const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
  690. &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot
  691. NULL
  692. };
  693. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  694. &SECURE_VERSION[0], // Secure version for anti-rollback
  695. NULL
  696. };
  697. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
  698. &MAC_FACTORY[0], // Factory MAC addr [0]
  699. &MAC_FACTORY[1], // Factory MAC addr [1]
  700. &MAC_FACTORY[2], // Factory MAC addr [2]
  701. &MAC_FACTORY[3], // Factory MAC addr [3]
  702. &MAC_FACTORY[4], // Factory MAC addr [4]
  703. &MAC_FACTORY[5], // Factory MAC addr [5]
  704. NULL
  705. };
  706. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
  707. &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
  708. NULL
  709. };
  710. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
  711. &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
  712. NULL
  713. };
  714. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
  715. &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
  716. NULL
  717. };
  718. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
  719. &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
  720. NULL
  721. };
  722. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
  723. &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
  724. NULL
  725. };
  726. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
  727. &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
  728. NULL
  729. };
  730. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
  731. &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
  732. NULL
  733. };
  734. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
  735. &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
  736. NULL
  737. };
  738. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
  739. &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
  740. NULL
  741. };
  742. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
  743. &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
  744. NULL
  745. };
  746. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
  747. &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
  748. NULL
  749. };
  750. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
  751. &WAFER_VERSION[0], // WAFER version
  752. NULL
  753. };
  754. const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
  755. &PKG_VERSION[0], // Package version 0:ESP32C3
  756. NULL
  757. };
  758. const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
  759. &BLOCK1_VERSION[0], // BLOCK1 efuse version
  760. NULL
  761. };
  762. const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
  763. &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
  764. NULL
  765. };
  766. const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
  767. &BLOCK2_VERSION[0], // Version of BLOCK2
  768. NULL
  769. };
  770. const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
  771. &TEMP_CALIB[0], // Temperature calibration data
  772. NULL
  773. };
  774. const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
  775. &OCODE[0], // ADC OCode
  776. NULL
  777. };
  778. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
  779. &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0
  780. NULL
  781. };
  782. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
  783. &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1
  784. NULL
  785. };
  786. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
  787. &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2
  788. NULL
  789. };
  790. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
  791. &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3
  792. NULL
  793. };
  794. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
  795. &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0
  796. NULL
  797. };
  798. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
  799. &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1
  800. NULL
  801. };
  802. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
  803. &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2
  804. NULL
  805. };
  806. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
  807. &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3
  808. NULL
  809. };
  810. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
  811. &USER_DATA[0], // User data
  812. NULL
  813. };
  814. const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
  815. &KEY0[0], // Key0 or user data
  816. NULL
  817. };
  818. const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
  819. &KEY1[0], // Key1 or user data
  820. NULL
  821. };
  822. const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
  823. &KEY2[0], // Key2 or user data
  824. NULL
  825. };
  826. const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
  827. &KEY3[0], // Key3 or user data
  828. NULL
  829. };
  830. const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
  831. &KEY4[0], // Key4 or user data
  832. NULL
  833. };
  834. const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
  835. &KEY5[0], // Key5 or user data
  836. NULL
  837. };
  838. const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
  839. &SYS_DATA_PART2[0], // System configuration
  840. NULL
  841. };
  842. const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
  843. &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO
  844. NULL
  845. };
  846. const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
  847. &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO
  848. NULL
  849. };
  850. const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
  851. &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20
  852. NULL
  853. };
  854. const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
  855. &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20
  856. NULL
  857. };
  858. const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
  859. &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt
  860. NULL
  861. };
  862. const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = {
  863. &THRES_HVT[0], // BLOCK1 pvt threshold when hvt
  864. NULL
  865. };