esp_efuse_table.c 29 KB

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  1. // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at",
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License
  14. #include "sdkconfig.h"
  15. #include "esp_efuse.h"
  16. #include <assert.h>
  17. #include "esp_efuse_table.h"
  18. // md5_digest_table c345ec20bb033bf5d071108ae644b54c
  19. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  20. // If you want to change some fields, you need to change esp_efuse_table.csv file
  21. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  22. // To show efuse_table run the command 'show_efuse_table'.
  23. static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
  24. {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
  25. };
  26. static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = {
  27. {EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT,
  28. };
  29. static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
  30. {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
  31. };
  32. static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
  33. {EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL,
  34. };
  35. static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  36. {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT,
  37. };
  38. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  39. {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0,
  40. };
  41. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  42. {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1,
  43. };
  44. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  45. {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2,
  46. };
  47. static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
  48. {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0,
  49. };
  50. static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
  51. {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1,
  52. };
  53. static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
  54. {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2,
  55. };
  56. static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
  57. {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3,
  58. };
  59. static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
  60. {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4,
  61. };
  62. static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
  63. {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5,
  64. };
  65. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
  66. {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN,
  67. };
  68. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  69. {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
  70. };
  71. static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
  72. {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
  73. };
  74. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  75. {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS,
  76. };
  77. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
  78. {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1,
  79. };
  80. static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
  81. {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA,
  82. };
  83. static const esp_efuse_desc_t WR_DIS_KEY0[] = {
  84. {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0,
  85. };
  86. static const esp_efuse_desc_t WR_DIS_KEY1[] = {
  87. {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1,
  88. };
  89. static const esp_efuse_desc_t WR_DIS_KEY2[] = {
  90. {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2,
  91. };
  92. static const esp_efuse_desc_t WR_DIS_KEY3[] = {
  93. {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3,
  94. };
  95. static const esp_efuse_desc_t WR_DIS_KEY4[] = {
  96. {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4,
  97. };
  98. static const esp_efuse_desc_t WR_DIS_KEY5[] = {
  99. {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5,
  100. };
  101. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
  102. {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
  103. };
  104. static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
  105. {EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS,
  106. };
  107. static const esp_efuse_desc_t RD_DIS_KEY0[] = {
  108. {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0,
  109. };
  110. static const esp_efuse_desc_t RD_DIS_KEY1[] = {
  111. {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1,
  112. };
  113. static const esp_efuse_desc_t RD_DIS_KEY2[] = {
  114. {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2,
  115. };
  116. static const esp_efuse_desc_t RD_DIS_KEY3[] = {
  117. {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3,
  118. };
  119. static const esp_efuse_desc_t RD_DIS_KEY4[] = {
  120. {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4,
  121. };
  122. static const esp_efuse_desc_t RD_DIS_KEY5[] = {
  123. {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5,
  124. };
  125. static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
  126. {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
  127. };
  128. static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = {
  129. {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM,
  130. };
  131. static const esp_efuse_desc_t DIS_ICACHE[] = {
  132. {EFUSE_BLK0, 40, 1}, // Disable Icache,
  133. };
  134. static const esp_efuse_desc_t DIS_DCACHE[] = {
  135. {EFUSE_BLK0, 41, 1}, // Disable Dcace,
  136. };
  137. static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
  138. {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7,
  139. };
  140. static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = {
  141. {EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7,
  142. };
  143. static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
  144. {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
  145. };
  146. static const esp_efuse_desc_t DIS_USB[] = {
  147. {EFUSE_BLK0, 45, 1}, // Disable USB function,
  148. };
  149. static const esp_efuse_desc_t DIS_CAN[] = {
  150. {EFUSE_BLK0, 46, 1}, // Disable CAN function,
  151. };
  152. static const esp_efuse_desc_t DIS_BOOT_REMAP[] = {
  153. {EFUSE_BLK0, 47, 1}, // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function,
  154. };
  155. static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
  156. {EFUSE_BLK0, 49, 1}, // Software disable jtag jtag can be activated again by hmac module,
  157. };
  158. static const esp_efuse_desc_t HARD_DIS_JTAG[] = {
  159. {EFUSE_BLK0, 50, 1}, // Hardware disable jtag permanently disable jtag function,
  160. };
  161. static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  162. {EFUSE_BLK0, 51, 1}, // Disable flash encrypt function,
  163. };
  164. static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
  165. {EFUSE_BLK0, 56, 1}, // Exchange D+ D- pins,
  166. };
  167. static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = {
  168. {EFUSE_BLK0, 57, 1}, // Enable external PHY,
  169. };
  170. static const esp_efuse_desc_t BLOCK0_VERSION[] = {
  171. {EFUSE_BLK0, 59, 2}, // BLOCK0 efuse version,
  172. };
  173. static const esp_efuse_desc_t VDD_SPI_XPD[] = {
  174. {EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up,
  175. };
  176. static const esp_efuse_desc_t VDD_SPI_TIEH[] = {
  177. {EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda,
  178. };
  179. static const esp_efuse_desc_t VDD_SPI_FORCE[] = {
  180. {EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI,
  181. };
  182. static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
  183. {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold,
  184. };
  185. static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
  186. {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
  187. };
  188. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
  189. {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key,
  190. };
  191. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
  192. {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key,
  193. };
  194. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
  195. {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key,
  196. };
  197. static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
  198. {EFUSE_BLK0, 88, 4}, // Key0 purpose,
  199. };
  200. static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
  201. {EFUSE_BLK0, 92, 4}, // Key1 purpose,
  202. };
  203. static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
  204. {EFUSE_BLK0, 96, 4}, // Key2 purpose,
  205. };
  206. static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
  207. {EFUSE_BLK0, 100, 4}, // Key3 purpose,
  208. };
  209. static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
  210. {EFUSE_BLK0, 104, 4}, // Key4 purpose,
  211. };
  212. static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
  213. {EFUSE_BLK0, 108, 4}, // Key5 purpose,
  214. };
  215. static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
  216. {EFUSE_BLK0, 116, 1}, // Secure boot enable,
  217. };
  218. static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  219. {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke,
  220. };
  221. static const esp_efuse_desc_t FLASH_TPUW[] = {
  222. {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
  223. };
  224. static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
  225. {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
  226. };
  227. static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
  228. {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
  229. };
  230. static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
  231. {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1,
  232. };
  233. static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
  234. {EFUSE_BLK0, 132, 1}, // Disable download through USB,
  235. };
  236. static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
  237. {EFUSE_BLK0, 133, 1}, // Enable security download mode,
  238. };
  239. static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
  240. {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.,
  241. };
  242. static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
  243. {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
  244. };
  245. static const esp_efuse_desc_t FLASH_TYPE[] = {
  246. {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
  247. };
  248. static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
  249. {EFUSE_BLK0, 138, 1}, // Force ROM code to send a resume command during SPI boot,
  250. };
  251. static const esp_efuse_desc_t SECURE_VERSION[] = {
  252. {EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback,
  253. };
  254. static const esp_efuse_desc_t MAC_FACTORY[] = {
  255. {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
  256. {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
  257. {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2],
  258. {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3],
  259. {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4],
  260. {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
  261. };
  262. static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
  263. {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
  264. };
  265. static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
  266. {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
  267. };
  268. static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
  269. {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
  270. };
  271. static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
  272. {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
  273. };
  274. static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
  275. {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
  276. };
  277. static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
  278. {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
  279. };
  280. static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
  281. {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
  282. };
  283. static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
  284. {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
  285. };
  286. static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
  287. {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
  288. };
  289. static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
  290. {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
  291. };
  292. static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
  293. {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
  294. };
  295. static const esp_efuse_desc_t WAFER_VERSION[] = {
  296. {EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
  297. };
  298. static const esp_efuse_desc_t FLASH_VERSION[] = {
  299. {EFUSE_BLK1, 117, 4}, // Flash_version,
  300. };
  301. static const esp_efuse_desc_t BLOCK1_VERSION[] = {
  302. {EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
  303. };
  304. static const esp_efuse_desc_t PSRAM_VERSION[] = {
  305. {EFUSE_BLK1, 124, 4}, // PSRAM version,
  306. };
  307. static const esp_efuse_desc_t PKG_VERSION[] = {
  308. {EFUSE_BLK1, 128, 4}, // Package version,
  309. };
  310. static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
  311. {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
  312. };
  313. static const esp_efuse_desc_t BLOCK2_VERSION[] = {
  314. {EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
  315. };
  316. static const esp_efuse_desc_t USER_DATA[] = {
  317. {EFUSE_BLK3, 0, 256}, // User data,
  318. };
  319. static const esp_efuse_desc_t KEY0[] = {
  320. {EFUSE_BLK4, 0, 256}, // Key0 or user data,
  321. };
  322. static const esp_efuse_desc_t KEY1[] = {
  323. {EFUSE_BLK5, 0, 256}, // Key1 or user data,
  324. };
  325. static const esp_efuse_desc_t KEY2[] = {
  326. {EFUSE_BLK6, 0, 256}, // Key2 or user data,
  327. };
  328. static const esp_efuse_desc_t KEY3[] = {
  329. {EFUSE_BLK7, 0, 256}, // Key3 or user data,
  330. };
  331. static const esp_efuse_desc_t KEY4[] = {
  332. {EFUSE_BLK8, 0, 256}, // Key4 or user data,
  333. };
  334. static const esp_efuse_desc_t KEY5[] = {
  335. {EFUSE_BLK9, 0, 256}, // Key5 or user data,
  336. };
  337. static const esp_efuse_desc_t SYS_DATA_PART2[] = {
  338. {EFUSE_BLK10, 0, 256}, // System configuration,
  339. };
  340. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
  341. &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
  342. NULL
  343. };
  344. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = {
  345. &WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT
  346. NULL
  347. };
  348. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
  349. &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
  350. NULL
  351. };
  352. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
  353. &WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
  354. NULL
  355. };
  356. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  357. &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT
  358. NULL
  359. };
  360. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  361. &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0
  362. NULL
  363. };
  364. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  365. &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1
  366. NULL
  367. };
  368. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  369. &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2
  370. NULL
  371. };
  372. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
  373. &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0
  374. NULL
  375. };
  376. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
  377. &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1
  378. NULL
  379. };
  380. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
  381. &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2
  382. NULL
  383. };
  384. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
  385. &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3
  386. NULL
  387. };
  388. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
  389. &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4
  390. NULL
  391. };
  392. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
  393. &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5
  394. NULL
  395. };
  396. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
  397. &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN
  398. NULL
  399. };
  400. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  401. &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
  402. NULL
  403. };
  404. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
  405. &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
  406. NULL
  407. };
  408. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  409. &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
  410. NULL
  411. };
  412. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
  413. &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1
  414. NULL
  415. };
  416. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
  417. &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA
  418. NULL
  419. };
  420. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
  421. &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0
  422. NULL
  423. };
  424. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
  425. &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1
  426. NULL
  427. };
  428. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
  429. &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2
  430. NULL
  431. };
  432. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
  433. &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3
  434. NULL
  435. };
  436. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
  437. &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4
  438. NULL
  439. };
  440. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
  441. &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5
  442. NULL
  443. };
  444. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
  445. &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2
  446. NULL
  447. };
  448. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
  449. &WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS
  450. NULL
  451. };
  452. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
  453. &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0
  454. NULL
  455. };
  456. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
  457. &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1
  458. NULL
  459. };
  460. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
  461. &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2
  462. NULL
  463. };
  464. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
  465. &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3
  466. NULL
  467. };
  468. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
  469. &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4
  470. NULL
  471. };
  472. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
  473. &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5
  474. NULL
  475. };
  476. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
  477. &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2
  478. NULL
  479. };
  480. const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = {
  481. &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM
  482. NULL
  483. };
  484. const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
  485. &DIS_ICACHE[0], // Disable Icache
  486. NULL
  487. };
  488. const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = {
  489. &DIS_DCACHE[0], // Disable Dcace
  490. NULL
  491. };
  492. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
  493. &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7
  494. NULL
  495. };
  496. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = {
  497. &DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
  498. NULL
  499. };
  500. const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
  501. &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function
  502. NULL
  503. };
  504. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
  505. &DIS_USB[0], // Disable USB function
  506. NULL
  507. };
  508. const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
  509. &DIS_CAN[0], // Disable CAN function
  510. NULL
  511. };
  512. const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[] = {
  513. &DIS_BOOT_REMAP[0], // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function
  514. NULL
  515. };
  516. const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
  517. &SOFT_DIS_JTAG[0], // Software disable jtag jtag can be activated again by hmac module
  518. NULL
  519. };
  520. const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = {
  521. &HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function
  522. NULL
  523. };
  524. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  525. &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function
  526. NULL
  527. };
  528. const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
  529. &USB_EXCHG_PINS[0], // Exchange D+ D- pins
  530. NULL
  531. };
  532. const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = {
  533. &USB_EXT_PHY_ENABLE[0], // Enable external PHY
  534. NULL
  535. };
  536. const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[] = {
  537. &BLOCK0_VERSION[0], // BLOCK0 efuse version
  538. NULL
  539. };
  540. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = {
  541. &VDD_SPI_XPD[0], // VDD_SPI regulator power up
  542. NULL
  543. };
  544. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = {
  545. &VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda
  546. NULL
  547. };
  548. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = {
  549. &VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI
  550. NULL
  551. };
  552. const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
  553. &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold
  554. NULL
  555. };
  556. const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
  557. &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
  558. NULL
  559. };
  560. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
  561. &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key
  562. NULL
  563. };
  564. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
  565. &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key
  566. NULL
  567. };
  568. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
  569. &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key
  570. NULL
  571. };
  572. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
  573. &KEY_PURPOSE_0[0], // Key0 purpose
  574. NULL
  575. };
  576. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
  577. &KEY_PURPOSE_1[0], // Key1 purpose
  578. NULL
  579. };
  580. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
  581. &KEY_PURPOSE_2[0], // Key2 purpose
  582. NULL
  583. };
  584. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
  585. &KEY_PURPOSE_3[0], // Key3 purpose
  586. NULL
  587. };
  588. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
  589. &KEY_PURPOSE_4[0], // Key4 purpose
  590. NULL
  591. };
  592. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
  593. &KEY_PURPOSE_5[0], // Key5 purpose
  594. NULL
  595. };
  596. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
  597. &SECURE_BOOT_EN[0], // Secure boot enable
  598. NULL
  599. };
  600. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  601. &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke
  602. NULL
  603. };
  604. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
  605. &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
  606. NULL
  607. };
  608. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
  609. &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
  610. NULL
  611. };
  612. const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
  613. &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
  614. NULL
  615. };
  616. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
  617. &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1
  618. NULL
  619. };
  620. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
  621. &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
  622. NULL
  623. };
  624. const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
  625. &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
  626. NULL
  627. };
  628. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
  629. &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
  630. NULL
  631. };
  632. const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
  633. &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
  634. NULL
  635. };
  636. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
  637. &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line
  638. NULL
  639. };
  640. const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
  641. &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot
  642. NULL
  643. };
  644. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  645. &SECURE_VERSION[0], // Secure version for anti-rollback
  646. NULL
  647. };
  648. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
  649. &MAC_FACTORY[0], // Factory MAC addr [0]
  650. &MAC_FACTORY[1], // Factory MAC addr [1]
  651. &MAC_FACTORY[2], // Factory MAC addr [2]
  652. &MAC_FACTORY[3], // Factory MAC addr [3]
  653. &MAC_FACTORY[4], // Factory MAC addr [4]
  654. &MAC_FACTORY[5], // Factory MAC addr [5]
  655. NULL
  656. };
  657. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
  658. &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
  659. NULL
  660. };
  661. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
  662. &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
  663. NULL
  664. };
  665. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
  666. &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
  667. NULL
  668. };
  669. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
  670. &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
  671. NULL
  672. };
  673. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
  674. &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
  675. NULL
  676. };
  677. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
  678. &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
  679. NULL
  680. };
  681. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
  682. &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
  683. NULL
  684. };
  685. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
  686. &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
  687. NULL
  688. };
  689. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
  690. &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
  691. NULL
  692. };
  693. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
  694. &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
  695. NULL
  696. };
  697. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
  698. &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
  699. NULL
  700. };
  701. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
  702. &WAFER_VERSION[0], // WAFER version 0:A
  703. NULL
  704. };
  705. const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
  706. &FLASH_VERSION[0], // Flash_version
  707. NULL
  708. };
  709. const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
  710. &BLOCK1_VERSION[0], // BLOCK1 efuse version
  711. NULL
  712. };
  713. const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[] = {
  714. &PSRAM_VERSION[0], // PSRAM version
  715. NULL
  716. };
  717. const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
  718. &PKG_VERSION[0], // Package version
  719. NULL
  720. };
  721. const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
  722. &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
  723. NULL
  724. };
  725. const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
  726. &BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
  727. NULL
  728. };
  729. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
  730. &USER_DATA[0], // User data
  731. NULL
  732. };
  733. const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
  734. &KEY0[0], // Key0 or user data
  735. NULL
  736. };
  737. const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
  738. &KEY1[0], // Key1 or user data
  739. NULL
  740. };
  741. const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
  742. &KEY2[0], // Key2 or user data
  743. NULL
  744. };
  745. const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
  746. &KEY3[0], // Key3 or user data
  747. NULL
  748. };
  749. const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
  750. &KEY4[0], // Key4 or user data
  751. NULL
  752. };
  753. const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
  754. &KEY5[0], // Key5 or user data
  755. NULL
  756. };
  757. const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
  758. &SYS_DATA_PART2[0], // System configuration
  759. NULL
  760. };