esp_flash_spi_init.c 10 KB

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  1. // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include "sdkconfig.h"
  15. #include "esp_flash.h"
  16. #include "memspi_host_driver.h"
  17. #include "esp_flash_spi_init.h"
  18. #include "driver/gpio.h"
  19. #include "esp_rom_gpio.h"
  20. #include "esp_rom_efuse.h"
  21. #include "esp_log.h"
  22. #include "esp_heap_caps.h"
  23. #include "hal/spi_types.h"
  24. #include "driver/spi_common_internal.h"
  25. #include "hal/spi_flash_hal.h"
  26. #include "hal/gpio_hal.h"
  27. #include "esp_flash_internal.h"
  28. #include "esp_rom_gpio.h"
  29. #if CONFIG_IDF_TARGET_ESP32
  30. #include "esp32/rom/spi_flash.h"
  31. #elif CONFIG_IDF_TARGET_ESP32S2
  32. #include "esp32s2/rom/spi_flash.h"
  33. #elif CONFIG_IDF_TARGET_ESP32S3
  34. #include "esp32s3/rom/spi_flash.h"
  35. #elif CONFIG_IDF_TARGET_ESP32C3
  36. #include "esp32c3/rom/spi_flash.h"
  37. #endif
  38. __attribute__((unused)) static const char TAG[] = "spi_flash";
  39. #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
  40. #define DEFAULT_FLASH_SPEED ESP_FLASH_80MHZ
  41. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
  42. #define DEFAULT_FLASH_SPEED ESP_FLASH_40MHZ
  43. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
  44. #define DEFAULT_FLASH_SPEED ESP_FLASH_26MHZ
  45. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
  46. #define DEFAULT_FLASH_SPEED ESP_FLASH_20MHZ
  47. #else
  48. #error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
  49. #endif
  50. #if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
  51. #define DEFAULT_FLASH_MODE SPI_FLASH_QIO
  52. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
  53. #define DEFAULT_FLASH_MODE SPI_FLASH_QOUT
  54. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
  55. #define DEFAULT_FLASH_MODE SPI_FLASH_DIO
  56. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
  57. #define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
  58. #else
  59. #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
  60. #endif
  61. //TODO: modify cs hold to meet requirements of all chips!!!
  62. #if CONFIG_IDF_TARGET_ESP32
  63. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  64. .host_id = SPI1_HOST,\
  65. .speed = DEFAULT_FLASH_SPEED, \
  66. .cs_num = 0, \
  67. .iomux = false, \
  68. .input_delay_ns = 0,\
  69. .cs_setup = 1,\
  70. }
  71. #elif CONFIG_IDF_TARGET_ESP32S2
  72. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  73. .host_id = SPI1_HOST,\
  74. .speed = DEFAULT_FLASH_SPEED, \
  75. .cs_num = 0, \
  76. .iomux = true, \
  77. .input_delay_ns = 0,\
  78. .cs_setup = 1,\
  79. }
  80. #elif CONFIG_IDF_TARGET_ESP32S3
  81. #include "esp32s3/rom/efuse.h"
  82. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  83. .host_id = SPI1_HOST,\
  84. .speed = DEFAULT_FLASH_SPEED, \
  85. .cs_num = 0, \
  86. .iomux = true, \
  87. .input_delay_ns = 0,\
  88. .cs_setup = 1,\
  89. }
  90. #elif CONFIG_IDF_TARGET_ESP32C3
  91. #include "esp32c3/rom/efuse.h"
  92. #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
  93. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  94. .host_id = SPI1_HOST,\
  95. .speed = DEFAULT_FLASH_SPEED, \
  96. .cs_num = 0, \
  97. .iomux = true, \
  98. .input_delay_ns = 0,\
  99. .cs_setup = 1,\
  100. }
  101. #else
  102. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  103. .host_id = SPI1_HOST,\
  104. .speed = DEFAULT_FLASH_SPEED, \
  105. .cs_num = 0, \
  106. .iomux = true, \
  107. .input_delay_ns = 0,\
  108. .auto_sus_en = true,\
  109. .cs_setup = 1,\
  110. }
  111. #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
  112. #endif
  113. static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id)
  114. {
  115. //Not using spicommon_cs_initialize since we don't want to put the whole
  116. //spi_periph_signal into the DRAM. Copy these data from flash before the
  117. //cache disabling
  118. int cs_io_num = config->cs_io_num;
  119. int spics_in = spi_periph_signal[config->host_id].spics_in;
  120. int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
  121. int spics_func = spi_periph_signal[config->host_id].func;
  122. uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
  123. //To avoid the panic caused by flash data line conflicts during cs line
  124. //initialization, disable the cache temporarily
  125. chip->os_func->start(chip->os_func_data);
  126. PIN_INPUT_ENABLE(iomux_reg);
  127. if (use_iomux) {
  128. gpio_hal_iomux_func_sel(iomux_reg, spics_func);
  129. } else {
  130. #if SOC_GPIO_PIN_COUNT <= 32
  131. GPIO.enable_w1ts.val = (0x1 << cs_io_num);
  132. #else
  133. if (cs_io_num < 32) {
  134. GPIO.enable_w1ts = (0x1 << cs_io_num);
  135. } else {
  136. GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
  137. }
  138. #endif
  139. GPIO.pin[cs_io_num].pad_driver = 0;
  140. esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
  141. if (cs_id == 0) {
  142. esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
  143. }
  144. gpio_hal_iomux_func_sel(iomux_reg, PIN_FUNC_GPIO);
  145. }
  146. chip->os_func->end(chip->os_func_data);
  147. }
  148. esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
  149. {
  150. if (out_chip == NULL) {
  151. return ESP_ERR_INVALID_ARG;
  152. }
  153. if (!GPIO_IS_VALID_OUTPUT_GPIO(config->cs_io_num)) {
  154. return ESP_ERR_INVALID_ARG;
  155. }
  156. esp_flash_t *chip = NULL;
  157. memspi_host_inst_t *host = NULL;
  158. esp_err_t ret = ESP_OK;
  159. uint32_t caps = MALLOC_CAP_DEFAULT;
  160. if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
  161. chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
  162. if (!chip) {
  163. ret = ESP_ERR_NO_MEM;
  164. goto fail;
  165. }
  166. host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
  167. *chip = (esp_flash_t) {
  168. .read_mode = config->io_mode,
  169. .host = (spi_flash_host_inst_t*)host,
  170. };
  171. if (!host) {
  172. ret = ESP_ERR_NO_MEM;
  173. goto fail;
  174. }
  175. int dev_id = -1;
  176. esp_err_t err = esp_flash_init_os_functions(chip, config->host_id, &dev_id);
  177. if (err == ESP_ERR_NOT_SUPPORTED) {
  178. ESP_LOGE(TAG, "Init os functions failed! No free CS.");
  179. } else if (err == ESP_ERR_INVALID_ARG) {
  180. ESP_LOGE(TAG, "Init os functions failed! Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
  181. }
  182. if (err != ESP_OK) {
  183. ret = err;
  184. goto fail;
  185. }
  186. // When `CONFIG_SPI_FLASH_SHARE_SPI1_BUS` is not enabled on SPI1 bus, the
  187. // `esp_flash_init_os_functions` will not be able to assign a new device ID. In this case, we
  188. // use the `cs_id` in the config structure.
  189. if (dev_id == -1 && config->host_id == SPI1_HOST) {
  190. dev_id = config->cs_id;
  191. }
  192. assert(dev_id < SOC_SPI_PERIPH_CS_NUM(config->host_id) && dev_id >= 0);
  193. bool use_iomux = spicommon_bus_using_iomux(config->host_id);
  194. memspi_host_config_t host_cfg = {
  195. .host_id = config->host_id,
  196. .cs_num = dev_id,
  197. .iomux = use_iomux,
  198. .input_delay_ns = config->input_delay_ns,
  199. .speed = config->speed,
  200. };
  201. err = memspi_host_init_pointers(host, &host_cfg);
  202. if (err != ESP_OK) {
  203. ret = err;
  204. goto fail;
  205. }
  206. // The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
  207. cs_initialize(chip, config, use_iomux, dev_id);
  208. *out_chip = chip;
  209. return ret;
  210. fail:
  211. // The memory allocated are free'd in the `spi_bus_remove_flash_device`.
  212. spi_bus_remove_flash_device(chip);
  213. return ret;
  214. }
  215. esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
  216. {
  217. if (chip==NULL) {
  218. return ESP_ERR_INVALID_ARG;
  219. }
  220. esp_flash_deinit_os_functions(chip);
  221. free(chip->host);
  222. free(chip);
  223. return ESP_OK;
  224. }
  225. /* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
  226. extern const esp_flash_os_functions_t esp_flash_noos_functions;
  227. /* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
  228. #if !CONFIG_SPI_FLASH_ROM_IMPL
  229. esp_flash_t *esp_flash_default_chip = NULL;
  230. #endif
  231. #ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
  232. static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
  233. static DRAM_ATTR esp_flash_t default_chip = {
  234. .read_mode = DEFAULT_FLASH_MODE,
  235. .host = (spi_flash_host_inst_t*)&esp_flash_default_host,
  236. .os_func = &esp_flash_noos_functions,
  237. };
  238. extern esp_err_t esp_flash_suspend_cmd_init(esp_flash_t* chip);
  239. esp_err_t esp_flash_init_default_chip(void)
  240. {
  241. const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
  242. memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
  243. #if !CONFIG_IDF_TARGET_ESP32
  244. // For esp32s2 spi IOs are configured as from IO MUX by default
  245. cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
  246. #endif
  247. //the host is already initialized, only do init for the data and load it to the host
  248. esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
  249. if (err != ESP_OK) {
  250. return err;
  251. }
  252. // ROM TODO: account for non-standard default pins in efuse
  253. // ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
  254. err = esp_flash_init(&default_chip);
  255. if (err != ESP_OK) {
  256. return err;
  257. }
  258. if (default_chip.size < legacy_chip->chip_size) {
  259. ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, legacy_chip->chip_size/1024);
  260. return ESP_ERR_FLASH_SIZE_NOT_MATCH;
  261. }
  262. if (default_chip.size > legacy_chip->chip_size) {
  263. ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, legacy_chip->chip_size/1024);
  264. }
  265. default_chip.size = legacy_chip->chip_size;
  266. esp_flash_default_chip = &default_chip;
  267. #ifdef CONFIG_SPI_FLASH_AUTO_SUSPEND
  268. err = esp_flash_suspend_cmd_init(&default_chip);
  269. if (err != ESP_OK) {
  270. return err;
  271. }
  272. #endif
  273. return ESP_OK;
  274. }
  275. esp_err_t esp_flash_app_init(void)
  276. {
  277. esp_err_t err = ESP_OK;
  278. #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
  279. err = esp_flash_init_main_bus_lock();
  280. if (err != ESP_OK) return err;
  281. #endif
  282. err = esp_flash_app_enable_os_functions(&default_chip);
  283. return err;
  284. }
  285. #endif //!CONFIG_SPI_FLASH_USE_LEGACY_IMPL