esp_system.c 3.0 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "esp_system.h"
  7. #include "esp_private/system_internal.h"
  8. #include "esp_heap_caps.h"
  9. #include "freertos/FreeRTOS.h"
  10. #include "freertos/task.h"
  11. #include "soc/cpu.h"
  12. #include "soc/rtc.h"
  13. #include "soc/rtc_cntl_reg.h"
  14. #include "esp_private/panic_internal.h"
  15. #include "esp_rom_uart.h"
  16. #if CONFIG_IDF_TARGET_ESP32S2
  17. #include "esp32s2/memprot.h"
  18. #elif CONFIG_IDF_TARGET_ESP32S3
  19. #include "esp32s3/memprot.h"
  20. #elif CONFIG_IDF_TARGET_ESP32C3
  21. #include "esp32c3/memprot.h"
  22. #elif CONFIG_IDF_TARGET_ESP32H2
  23. #include "esp32h2/memprot.h"
  24. #endif
  25. #define SHUTDOWN_HANDLERS_NO 5
  26. static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
  27. void IRAM_ATTR esp_restart_noos_dig(void)
  28. {
  29. // make sure all the panic handler output is sent from UART FIFO
  30. if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
  31. esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
  32. }
  33. // switch to XTAL (otherwise we will keep running from the PLL)
  34. rtc_clk_cpu_freq_set_xtal();
  35. #if CONFIG_IDF_TARGET_ESP32
  36. esp_cpu_unstall(PRO_CPU_NUM);
  37. #endif
  38. // reset the digital part
  39. SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
  40. while (true) {
  41. ;
  42. }
  43. }
  44. esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
  45. {
  46. for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
  47. if (shutdown_handlers[i] == handler) {
  48. return ESP_ERR_INVALID_STATE;
  49. } else if (shutdown_handlers[i] == NULL) {
  50. shutdown_handlers[i] = handler;
  51. return ESP_OK;
  52. }
  53. }
  54. return ESP_ERR_NO_MEM;
  55. }
  56. esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
  57. {
  58. for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
  59. if (shutdown_handlers[i] == handler) {
  60. shutdown_handlers[i] = NULL;
  61. return ESP_OK;
  62. }
  63. }
  64. return ESP_ERR_INVALID_STATE;
  65. }
  66. void IRAM_ATTR esp_restart(void)
  67. {
  68. for (int i = SHUTDOWN_HANDLERS_NO - 1; i >= 0; i--) {
  69. if (shutdown_handlers[i]) {
  70. shutdown_handlers[i]();
  71. }
  72. }
  73. // Disable scheduler on this core.
  74. vTaskSuspendAll();
  75. bool digital_reset_needed = false;
  76. #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
  77. if (esp_memprot_is_intr_ena_any() || esp_memprot_is_locked_any()) {
  78. digital_reset_needed = true;
  79. }
  80. #endif
  81. if (digital_reset_needed) {
  82. esp_restart_noos_dig();
  83. }
  84. esp_restart_noos();
  85. }
  86. uint32_t esp_get_free_heap_size( void )
  87. {
  88. return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
  89. }
  90. uint32_t esp_get_free_internal_heap_size( void )
  91. {
  92. return heap_caps_get_free_size( MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL );
  93. }
  94. uint32_t esp_get_minimum_free_heap_size( void )
  95. {
  96. return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
  97. }
  98. const char *esp_get_idf_version(void)
  99. {
  100. return IDF_VER;
  101. }
  102. void __attribute__((noreturn)) esp_system_abort(const char *details)
  103. {
  104. panic_abort(details);
  105. }