rmt.c 56 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stdlib.h>
  7. #include <string.h>
  8. #include <sys/lock.h>
  9. #include <sys/cdefs.h>
  10. #include "esp_compiler.h"
  11. #include "esp_intr_alloc.h"
  12. #include "esp_log.h"
  13. #include "esp_check.h"
  14. #include "driver/gpio.h"
  15. #include "driver/periph_ctrl.h"
  16. #include "driver/rmt.h"
  17. #include "freertos/FreeRTOS.h"
  18. #include "freertos/task.h"
  19. #include "freertos/semphr.h"
  20. #include "freertos/ringbuf.h"
  21. #include "soc/soc_memory_layout.h"
  22. #include "soc/rmt_periph.h"
  23. #include "soc/rtc.h"
  24. #include "hal/rmt_hal.h"
  25. #include "hal/rmt_ll.h"
  26. #include "hal/gpio_hal.h"
  27. #include "esp_rom_gpio.h"
  28. #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
  29. #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
  30. #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
  31. #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
  32. #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
  33. #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
  34. #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
  35. #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
  36. #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
  37. #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
  38. #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
  39. #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
  40. #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
  41. #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
  42. #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
  43. #define RMT_PARAM_ERR_STR "RMT param error"
  44. static const char *TAG = "rmt";
  45. // Spinlock for protecting concurrent register-level access only
  46. #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
  47. #define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
  48. #define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP)
  49. #define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1)
  50. #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START)
  51. #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END)
  52. #define RMT_DECODE_RX_CHANNEL(encode_chan) ((encode_chan - RMT_RX_CHANNEL_ENCODING_START))
  53. #define RMT_ENCODE_RX_CHANNEL(decode_chan) ((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
  54. typedef struct {
  55. rmt_hal_context_t hal;
  56. _lock_t rmt_driver_isr_lock;
  57. portMUX_TYPE rmt_spinlock; // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
  58. rmt_isr_handle_t rmt_driver_intr_handle;
  59. rmt_tx_end_callback_t rmt_tx_end_callback;// Event called when transmission is ended
  60. uint8_t rmt_driver_channels; // Bitmask of installed drivers' channels
  61. bool rmt_module_enabled;
  62. uint32_t synchro_channel_mask; // Bitmap of channels already added in the synchronous group
  63. } rmt_contex_t;
  64. typedef struct {
  65. size_t tx_offset;
  66. size_t tx_len_rem;
  67. size_t tx_sub_len;
  68. bool translator;
  69. bool wait_done; //Mark whether wait tx done.
  70. bool loop_autostop; // mark whether loop auto-stop is enabled
  71. rmt_channel_t channel;
  72. const rmt_item32_t *tx_data;
  73. xSemaphoreHandle tx_sem;
  74. #if CONFIG_SPIRAM_USE_MALLOC
  75. int intr_alloc_flags;
  76. StaticSemaphore_t tx_sem_buffer;
  77. #endif
  78. rmt_item32_t *tx_buf;
  79. RingbufHandle_t rx_buf;
  80. #if SOC_RMT_SUPPORT_RX_PINGPONG
  81. rmt_item32_t *rx_item_buf;
  82. uint32_t rx_item_buf_size;
  83. uint32_t rx_item_len;
  84. int rx_item_start_idx;
  85. #endif
  86. sample_to_rmt_t sample_to_rmt;
  87. void *tx_context;
  88. size_t sample_size_remain;
  89. const uint8_t *sample_cur;
  90. } rmt_obj_t;
  91. static rmt_contex_t rmt_contex = {
  92. .hal.regs = RMT_LL_HW_BASE,
  93. .hal.mem = RMT_LL_MEM_BASE,
  94. .rmt_spinlock = portMUX_INITIALIZER_UNLOCKED,
  95. .rmt_driver_intr_handle = NULL,
  96. .rmt_tx_end_callback = {
  97. .function = NULL,
  98. },
  99. .rmt_driver_channels = 0,
  100. .rmt_module_enabled = false,
  101. .synchro_channel_mask = 0
  102. };
  103. static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0};
  104. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  105. static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX];
  106. #else
  107. static uint32_t s_rmt_source_clock_hz;
  108. #endif
  109. //Enable RMT module
  110. static void rmt_module_enable(void)
  111. {
  112. RMT_ENTER_CRITICAL();
  113. if (rmt_contex.rmt_module_enabled == false) {
  114. periph_module_reset(rmt_periph_signals.groups[0].module);
  115. periph_module_enable(rmt_periph_signals.groups[0].module);
  116. rmt_contex.rmt_module_enabled = true;
  117. }
  118. RMT_EXIT_CRITICAL();
  119. }
  120. //Disable RMT module
  121. static void rmt_module_disable(void)
  122. {
  123. RMT_ENTER_CRITICAL();
  124. if (rmt_contex.rmt_module_enabled == true) {
  125. periph_module_disable(rmt_periph_signals.groups[0].module);
  126. rmt_contex.rmt_module_enabled = false;
  127. }
  128. RMT_EXIT_CRITICAL();
  129. }
  130. esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
  131. {
  132. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  133. RMT_ENTER_CRITICAL();
  134. if (RMT_IS_RX_CHANNEL(channel)) {
  135. rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt);
  136. } else {
  137. rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt);
  138. }
  139. RMT_EXIT_CRITICAL();
  140. return ESP_OK;
  141. }
  142. esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt)
  143. {
  144. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  145. ESP_RETURN_ON_FALSE(div_cnt, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  146. RMT_ENTER_CRITICAL();
  147. if (RMT_IS_RX_CHANNEL(channel)) {
  148. *div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  149. } else {
  150. *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
  151. }
  152. RMT_EXIT_CRITICAL();
  153. return ESP_OK;
  154. }
  155. esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
  156. {
  157. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  158. RMT_ENTER_CRITICAL();
  159. rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
  160. RMT_EXIT_CRITICAL();
  161. return ESP_OK;
  162. }
  163. esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
  164. {
  165. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  166. ESP_RETURN_ON_FALSE(thresh, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  167. RMT_ENTER_CRITICAL();
  168. *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  169. RMT_EXIT_CRITICAL();
  170. return ESP_OK;
  171. }
  172. esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
  173. {
  174. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  175. ESP_RETURN_ON_FALSE(rmt_mem_num <= RMT_CHANNEL_MAX - channel, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
  176. RMT_ENTER_CRITICAL();
  177. if (RMT_IS_RX_CHANNEL(channel)) {
  178. rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num);
  179. } else {
  180. rmt_ll_tx_set_mem_blocks(rmt_contex.hal.regs, channel, rmt_mem_num);
  181. }
  182. RMT_EXIT_CRITICAL();
  183. return ESP_OK;
  184. }
  185. esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num)
  186. {
  187. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  188. ESP_RETURN_ON_FALSE(rmt_mem_num, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  189. RMT_ENTER_CRITICAL();
  190. if (RMT_IS_RX_CHANNEL(channel)) {
  191. *rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  192. } else {
  193. *rmt_mem_num = (uint8_t)rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  194. }
  195. RMT_EXIT_CRITICAL();
  196. return ESP_OK;
  197. }
  198. esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
  199. rmt_carrier_level_t carrier_level)
  200. {
  201. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  202. ESP_RETURN_ON_FALSE(carrier_level < RMT_CARRIER_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CARRIER_ERROR_STR);
  203. RMT_ENTER_CRITICAL();
  204. rmt_ll_tx_set_carrier_high_low_ticks(rmt_contex.hal.regs, channel, high_level, low_level);
  205. rmt_ll_tx_set_carrier_level(rmt_contex.hal.regs, channel, carrier_level);
  206. rmt_ll_tx_enable_carrier_modulation(rmt_contex.hal.regs, channel, carrier_en);
  207. RMT_EXIT_CRITICAL();
  208. return ESP_OK;
  209. }
  210. esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
  211. {
  212. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  213. RMT_ENTER_CRITICAL();
  214. rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en);
  215. RMT_EXIT_CRITICAL();
  216. return ESP_OK;
  217. }
  218. esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
  219. {
  220. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  221. RMT_ENTER_CRITICAL();
  222. *pd_en = rmt_ll_is_mem_power_down(rmt_contex.hal.regs);
  223. RMT_EXIT_CRITICAL();
  224. return ESP_OK;
  225. }
  226. esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
  227. {
  228. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  229. RMT_ENTER_CRITICAL();
  230. if (tx_idx_rst) {
  231. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  232. }
  233. rmt_ll_clear_tx_end_interrupt(rmt_contex.hal.regs, channel);
  234. // enable tx end interrupt in non-loop mode
  235. if (!rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
  236. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, true);
  237. } else {
  238. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  239. rmt_ll_tx_reset_loop(rmt_contex.hal.regs, channel);
  240. rmt_ll_tx_enable_loop_count(rmt_contex.hal.regs, channel, true);
  241. rmt_ll_clear_tx_loop_interrupt(rmt_contex.hal.regs, channel);
  242. rmt_ll_enable_tx_loop_interrupt(rmt_contex.hal.regs, channel, true);
  243. #endif
  244. }
  245. rmt_ll_tx_start(rmt_contex.hal.regs, channel);
  246. RMT_EXIT_CRITICAL();
  247. return ESP_OK;
  248. }
  249. esp_err_t rmt_tx_stop(rmt_channel_t channel)
  250. {
  251. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  252. RMT_ENTER_CRITICAL();
  253. rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
  254. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  255. RMT_EXIT_CRITICAL();
  256. return ESP_OK;
  257. }
  258. esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
  259. {
  260. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  261. RMT_ENTER_CRITICAL();
  262. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  263. if (rx_idx_rst) {
  264. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  265. }
  266. rmt_ll_clear_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  267. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  268. #if SOC_RMT_SUPPORT_RX_PINGPONG
  269. const uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
  270. p_rmt_obj[channel]->rx_item_start_idx = 0;
  271. p_rmt_obj[channel]->rx_item_len = 0;
  272. rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2);
  273. #endif
  274. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  275. RMT_EXIT_CRITICAL();
  276. return ESP_OK;
  277. }
  278. esp_err_t rmt_rx_stop(rmt_channel_t channel)
  279. {
  280. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  281. RMT_ENTER_CRITICAL();
  282. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  283. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  284. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  285. #if SOC_RMT_SUPPORT_RX_PINGPONG
  286. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  287. #endif
  288. RMT_EXIT_CRITICAL();
  289. return ESP_OK;
  290. }
  291. esp_err_t rmt_tx_memory_reset(rmt_channel_t channel)
  292. {
  293. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  294. RMT_ENTER_CRITICAL();
  295. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  296. RMT_EXIT_CRITICAL();
  297. return ESP_OK;
  298. }
  299. esp_err_t rmt_rx_memory_reset(rmt_channel_t channel)
  300. {
  301. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  302. RMT_ENTER_CRITICAL();
  303. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  304. RMT_EXIT_CRITICAL();
  305. return ESP_OK;
  306. }
  307. esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
  308. {
  309. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  310. ESP_RETURN_ON_FALSE(owner < RMT_MEM_OWNER_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
  311. RMT_ENTER_CRITICAL();
  312. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), owner);
  313. RMT_EXIT_CRITICAL();
  314. return ESP_OK;
  315. }
  316. esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner)
  317. {
  318. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  319. ESP_RETURN_ON_FALSE(owner, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
  320. RMT_ENTER_CRITICAL();
  321. *owner = (rmt_mem_owner_t)rmt_ll_rx_get_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  322. RMT_EXIT_CRITICAL();
  323. return ESP_OK;
  324. }
  325. esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
  326. {
  327. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  328. RMT_ENTER_CRITICAL();
  329. rmt_ll_tx_enable_loop(rmt_contex.hal.regs, channel, loop_en);
  330. RMT_EXIT_CRITICAL();
  331. return ESP_OK;
  332. }
  333. esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
  334. {
  335. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  336. RMT_ENTER_CRITICAL();
  337. *loop_en = rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel);
  338. RMT_EXIT_CRITICAL();
  339. return ESP_OK;
  340. }
  341. esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
  342. {
  343. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  344. RMT_ENTER_CRITICAL();
  345. rmt_ll_rx_enable_filter(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rx_filter_en);
  346. rmt_ll_rx_set_filter_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
  347. RMT_EXIT_CRITICAL();
  348. return ESP_OK;
  349. }
  350. esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
  351. {
  352. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  353. ESP_RETURN_ON_FALSE(base_clk < RMT_BASECLK_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_BASECLK_ERROR_STR);
  354. RMT_ENTER_CRITICAL();
  355. rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0);
  356. RMT_EXIT_CRITICAL();
  357. return ESP_OK;
  358. }
  359. esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
  360. {
  361. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  362. RMT_ENTER_CRITICAL();
  363. *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel);
  364. RMT_EXIT_CRITICAL();
  365. return ESP_OK;
  366. }
  367. esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
  368. {
  369. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  370. ESP_RETURN_ON_FALSE(level < RMT_IDLE_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, "RMT IDLE LEVEL ERR");
  371. RMT_ENTER_CRITICAL();
  372. rmt_ll_tx_enable_idle(rmt_contex.hal.regs, channel, idle_out_en);
  373. rmt_ll_tx_set_idle_level(rmt_contex.hal.regs, channel, level);
  374. RMT_EXIT_CRITICAL();
  375. return ESP_OK;
  376. }
  377. esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
  378. {
  379. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  380. RMT_ENTER_CRITICAL();
  381. *idle_out_en = rmt_ll_is_tx_idle_enabled(rmt_contex.hal.regs, channel);
  382. *level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
  383. RMT_EXIT_CRITICAL();
  384. return ESP_OK;
  385. }
  386. esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
  387. {
  388. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  389. RMT_ENTER_CRITICAL();
  390. if (RMT_IS_RX_CHANNEL(channel)) {
  391. *status = rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  392. } else {
  393. *status = rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel);
  394. }
  395. RMT_EXIT_CRITICAL();
  396. return ESP_OK;
  397. }
  398. void rmt_set_intr_enable_mask(uint32_t mask)
  399. {
  400. RMT_ENTER_CRITICAL();
  401. rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, true);
  402. RMT_EXIT_CRITICAL();
  403. }
  404. void rmt_clr_intr_enable_mask(uint32_t mask)
  405. {
  406. RMT_ENTER_CRITICAL();
  407. rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, false);
  408. RMT_EXIT_CRITICAL();
  409. }
  410. esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
  411. {
  412. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  413. RMT_ENTER_CRITICAL();
  414. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
  415. RMT_EXIT_CRITICAL();
  416. return ESP_OK;
  417. }
  418. #if SOC_RMT_SUPPORT_RX_PINGPONG
  419. esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  420. {
  421. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  422. if (en) {
  423. uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
  424. ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
  425. RMT_ENTER_CRITICAL();
  426. rmt_ll_rx_set_limit(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), evt_thresh);
  427. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  428. RMT_EXIT_CRITICAL();
  429. } else {
  430. RMT_ENTER_CRITICAL();
  431. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  432. RMT_EXIT_CRITICAL();
  433. }
  434. return ESP_OK;
  435. }
  436. #endif
  437. esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
  438. {
  439. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  440. RMT_ENTER_CRITICAL();
  441. if (RMT_IS_RX_CHANNEL(channel)) {
  442. rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
  443. } else {
  444. rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, en);
  445. }
  446. RMT_EXIT_CRITICAL();
  447. return ESP_OK;
  448. }
  449. esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
  450. {
  451. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  452. RMT_ENTER_CRITICAL();
  453. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, en);
  454. RMT_EXIT_CRITICAL();
  455. return ESP_OK;
  456. }
  457. esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  458. {
  459. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  460. if (en) {
  461. uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  462. ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
  463. RMT_ENTER_CRITICAL();
  464. rmt_ll_tx_set_limit(rmt_contex.hal.regs, channel, evt_thresh);
  465. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, true);
  466. RMT_EXIT_CRITICAL();
  467. } else {
  468. RMT_ENTER_CRITICAL();
  469. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
  470. RMT_EXIT_CRITICAL();
  471. }
  472. return ESP_OK;
  473. }
  474. esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal)
  475. {
  476. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  477. ESP_RETURN_ON_FALSE(mode < RMT_MODE_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MODE_ERROR_STR);
  478. ESP_RETURN_ON_FALSE(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
  479. (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), ESP_ERR_INVALID_ARG, TAG, RMT_GPIO_ERROR_STR);
  480. gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
  481. if (mode == RMT_MODE_TX) {
  482. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  483. gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
  484. esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].tx_sig, invert_signal, 0);
  485. } else {
  486. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  487. gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
  488. esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].rx_sig, invert_signal);
  489. }
  490. return ESP_OK;
  491. }
  492. esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num)
  493. {
  494. // only for backword compatibility
  495. return rmt_set_gpio(channel, mode, gpio_num, false);
  496. }
  497. static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode)
  498. {
  499. // RX mode
  500. if (mode == RMT_MODE_RX) {
  501. return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX);
  502. }
  503. // TX mode
  504. return (channel >= 0) && RMT_IS_TX_CHANNEL(channel);
  505. }
  506. static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
  507. {
  508. uint8_t mode = rmt_param->rmt_mode;
  509. uint8_t channel = rmt_param->channel;
  510. uint8_t gpio_num = rmt_param->gpio_num;
  511. uint8_t mem_cnt = rmt_param->mem_block_num;
  512. uint8_t clk_div = rmt_param->clk_div;
  513. uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
  514. bool carrier_en = rmt_param->tx_config.carrier_en;
  515. uint32_t rmt_source_clk_hz;
  516. ESP_RETURN_ON_FALSE(rmt_is_channel_number_valid(channel, mode), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  517. ESP_RETURN_ON_FALSE(mem_cnt + channel <= 8 && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
  518. ESP_RETURN_ON_FALSE(clk_div > 0, ESP_ERR_INVALID_ARG, TAG, RMT_CLK_DIV_ERROR_STR);
  519. if (mode == RMT_MODE_TX) {
  520. ESP_RETURN_ON_FALSE(!carrier_en || carrier_freq_hz > 0, ESP_ERR_INVALID_ARG, TAG, "RMT carrier frequency can't be zero");
  521. }
  522. RMT_ENTER_CRITICAL();
  523. rmt_ll_enable_mem_access(dev, true);
  524. if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
  525. #if SOC_RMT_SUPPORT_XTAL
  526. // clock src: XTAL_CLK
  527. rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000;
  528. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_XTAL, 0, 0, 0);
  529. #elif SOC_RMT_SUPPORT_REF_TICK
  530. // clock src: REF_CLK
  531. rmt_source_clk_hz = REF_CLK_FREQ;
  532. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_REF, 0, 0, 0);
  533. #endif
  534. } else {
  535. // clock src: APB_CLK
  536. rmt_source_clk_hz = APB_CLK_FREQ;
  537. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_APB, 0, 0, 0);
  538. }
  539. RMT_EXIT_CRITICAL();
  540. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  541. s_rmt_source_clock_hz[channel] = rmt_source_clk_hz;
  542. #else
  543. if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) {
  544. ESP_LOGW(TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz);
  545. }
  546. s_rmt_source_clock_hz = rmt_source_clk_hz;
  547. #endif
  548. ESP_LOGD(TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz);
  549. if (mode == RMT_MODE_TX) {
  550. uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
  551. uint8_t carrier_level = rmt_param->tx_config.carrier_level;
  552. uint8_t idle_level = rmt_param->tx_config.idle_level;
  553. RMT_ENTER_CRITICAL();
  554. rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div);
  555. rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt);
  556. rmt_ll_tx_reset_pointer(dev, channel);
  557. rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en);
  558. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  559. if (rmt_param->tx_config.loop_en) {
  560. rmt_ll_tx_set_loop_count(dev, channel, rmt_param->tx_config.loop_count);
  561. }
  562. #endif
  563. /* always enable tx ping-pong */
  564. rmt_ll_tx_enable_pingpong(dev, channel, true);
  565. /*Set idle level */
  566. rmt_ll_tx_enable_idle(dev, channel, rmt_param->tx_config.idle_output_en);
  567. rmt_ll_tx_set_idle_level(dev, channel, idle_level);
  568. /*Set carrier*/
  569. rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en);
  570. if (carrier_en) {
  571. uint32_t duty_div, duty_h, duty_l;
  572. duty_div = rmt_source_clk_hz / carrier_freq_hz;
  573. duty_h = duty_div * carrier_duty_percent / 100;
  574. duty_l = duty_div - duty_h;
  575. rmt_ll_tx_set_carrier_level(dev, channel, carrier_level);
  576. rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
  577. } else {
  578. rmt_ll_tx_set_carrier_level(dev, channel, 0);
  579. rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, 0, 0);
  580. }
  581. RMT_EXIT_CRITICAL();
  582. ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
  583. channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
  584. } else if (RMT_MODE_RX == mode) {
  585. uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
  586. uint16_t threshold = rmt_param->rx_config.idle_threshold;
  587. RMT_ENTER_CRITICAL();
  588. rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div);
  589. rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt);
  590. rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel));
  591. rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), RMT_MEM_OWNER_HW);
  592. /*Set idle threshold*/
  593. rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), threshold);
  594. /* Set RX filter */
  595. rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), filter_cnt);
  596. rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.filter_en);
  597. #if SOC_RMT_SUPPORT_RX_PINGPONG
  598. /* always enable rx ping-pong */
  599. rmt_ll_rx_enable_pingpong(dev, RMT_DECODE_RX_CHANNEL(channel), true);
  600. #endif
  601. #if SOC_RMT_SUPPORT_RX_DEMODULATION
  602. rmt_ll_rx_enable_carrier_demodulation(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.rm_carrier);
  603. if (rmt_param->rx_config.rm_carrier) {
  604. uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz;
  605. uint32_t duty_high = duty_total * rmt_param->rx_config.carrier_duty_percent / 100;
  606. // there could be residual in timing the carrier pulse, so double enlarge the theoretical value
  607. rmt_ll_rx_set_carrier_high_low_ticks(dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, (duty_total - duty_high) * 2);
  608. rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.carrier_level);
  609. }
  610. #endif
  611. RMT_EXIT_CRITICAL();
  612. ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
  613. channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
  614. }
  615. return ESP_OK;
  616. }
  617. esp_err_t rmt_config(const rmt_config_t *rmt_param)
  618. {
  619. rmt_module_enable();
  620. ESP_RETURN_ON_ERROR(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG), TAG, "set gpio for RMT driver failed");
  621. ESP_RETURN_ON_ERROR(rmt_internal_config(&RMT, rmt_param), TAG, "initialize RMT driver failed");
  622. return ESP_OK;
  623. }
  624. static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
  625. uint16_t item_num, uint16_t mem_offset)
  626. {
  627. RMT_ENTER_CRITICAL();
  628. rmt_ll_write_memory(rmt_contex.hal.mem, channel, item, item_num, mem_offset);
  629. RMT_EXIT_CRITICAL();
  630. }
  631. esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
  632. {
  633. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), (0), TAG, RMT_CHANNEL_ERROR_STR);
  634. ESP_RETURN_ON_FALSE(item, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  635. ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
  636. /*Each block has 64 x 32 bits of data*/
  637. uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  638. ESP_RETURN_ON_FALSE(mem_cnt * RMT_MEM_ITEM_NUM >= item_num, ESP_ERR_INVALID_ARG, TAG, RMT_WR_MEM_OVF_ERROR_STR);
  639. rmt_fill_memory(channel, item, item_num, mem_offset);
  640. return ESP_OK;
  641. }
  642. esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
  643. {
  644. ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  645. ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels == 0, ESP_FAIL, TAG, "RMT driver installed, can not install generic ISR handler");
  646. return esp_intr_alloc(rmt_periph_signals.groups[0].irq, intr_alloc_flags, fn, arg, handle);
  647. }
  648. esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
  649. {
  650. return esp_intr_free(handle);
  651. }
  652. static int IRAM_ATTR rmt_rx_get_mem_len_in_isr(rmt_channel_t channel)
  653. {
  654. int block_num = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel);
  655. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  656. volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
  657. int idx;
  658. for (idx = 0; idx < item_block_len; idx++) {
  659. if (data[idx].duration0 == 0) {
  660. return idx;
  661. } else if (data[idx].duration1 == 0) {
  662. return idx + 1;
  663. }
  664. }
  665. return idx;
  666. }
  667. static void IRAM_ATTR rmt_driver_isr_default(void *arg)
  668. {
  669. uint32_t status = 0;
  670. rmt_item32_t volatile *addr = NULL;
  671. uint8_t channel = 0;
  672. rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
  673. portBASE_TYPE HPTaskAwoken = pdFALSE;
  674. // Tx end interrupt
  675. status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
  676. while (status) {
  677. channel = __builtin_ffs(status) - 1;
  678. status &= ~(1 << channel);
  679. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  680. if (p_rmt) {
  681. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  682. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  683. p_rmt->tx_data = NULL;
  684. p_rmt->tx_len_rem = 0;
  685. p_rmt->tx_offset = 0;
  686. p_rmt->tx_sub_len = 0;
  687. p_rmt->sample_cur = NULL;
  688. p_rmt->translator = false;
  689. if (rmt_contex.rmt_tx_end_callback.function) {
  690. rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
  691. }
  692. }
  693. rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
  694. }
  695. // Tx thres interrupt
  696. status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
  697. while (status) {
  698. channel = __builtin_ffs(status) - 1;
  699. status &= ~(1 << channel);
  700. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  701. if (p_rmt) {
  702. if (p_rmt->translator) {
  703. if (p_rmt->sample_size_remain > 0) {
  704. size_t translated_size = 0;
  705. p_rmt->sample_to_rmt((void *)p_rmt->sample_cur,
  706. p_rmt->tx_buf,
  707. p_rmt->sample_size_remain,
  708. p_rmt->tx_sub_len,
  709. &translated_size,
  710. &p_rmt->tx_len_rem);
  711. p_rmt->sample_size_remain -= translated_size;
  712. p_rmt->sample_cur += translated_size;
  713. p_rmt->tx_data = p_rmt->tx_buf;
  714. } else {
  715. p_rmt->sample_cur = NULL;
  716. p_rmt->translator = false;
  717. }
  718. }
  719. const rmt_item32_t *pdata = p_rmt->tx_data;
  720. size_t len_rem = p_rmt->tx_len_rem;
  721. if (len_rem >= p_rmt->tx_sub_len) {
  722. rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
  723. p_rmt->tx_data += p_rmt->tx_sub_len;
  724. p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
  725. } else if (len_rem == 0) {
  726. rmt_item32_t stop_data = {0};
  727. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset);
  728. } else {
  729. rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
  730. rmt_item32_t stop_data = {0};
  731. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
  732. p_rmt->tx_data += len_rem;
  733. p_rmt->tx_len_rem -= len_rem;
  734. }
  735. if (p_rmt->tx_offset == 0) {
  736. p_rmt->tx_offset = p_rmt->tx_sub_len;
  737. } else {
  738. p_rmt->tx_offset = 0;
  739. }
  740. }
  741. rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
  742. }
  743. // Rx end interrupt
  744. status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
  745. while (status) {
  746. channel = __builtin_ffs(status) - 1;
  747. status &= ~(1 << channel);
  748. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  749. if (p_rmt) {
  750. rmt_ll_rx_enable(rmt_contex.hal.regs, channel, false);
  751. int item_len = rmt_rx_get_mem_len_in_isr(channel);
  752. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
  753. if (p_rmt->rx_buf) {
  754. addr = RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
  755. #if SOC_RMT_SUPPORT_RX_PINGPONG
  756. if (item_len > p_rmt->rx_item_start_idx) {
  757. item_len = item_len - p_rmt->rx_item_start_idx;
  758. }
  759. memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(addr + p_rmt->rx_item_start_idx), item_len * 4);
  760. p_rmt->rx_item_len += item_len;
  761. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)(p_rmt->rx_item_buf), p_rmt->rx_item_len * 4, &HPTaskAwoken);
  762. #else
  763. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
  764. #endif
  765. if (res == pdFALSE) {
  766. ESP_EARLY_LOGE(TAG, "RMT RX BUFFER FULL");
  767. }
  768. } else {
  769. ESP_EARLY_LOGE(TAG, "RMT RX BUFFER ERROR");
  770. }
  771. #if SOC_RMT_SUPPORT_RX_PINGPONG
  772. p_rmt->rx_item_start_idx = 0;
  773. p_rmt->rx_item_len = 0;
  774. memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size);
  775. #endif
  776. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
  777. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
  778. rmt_ll_rx_enable(rmt_contex.hal.regs, channel, true);
  779. }
  780. rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
  781. }
  782. #if SOC_RMT_SUPPORT_RX_PINGPONG
  783. // Rx thres interrupt
  784. status = rmt_ll_get_rx_thres_interrupt_status(hal->regs);
  785. while (status) {
  786. channel = __builtin_ffs(status) - 1;
  787. status &= ~(1 << channel);
  788. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  789. int mem_item_size = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  790. int rx_thres_lim = rmt_ll_rx_get_limit(rmt_contex.hal.regs, channel);
  791. int item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : (mem_item_size - rx_thres_lim);
  792. if ((p_rmt->rx_item_len + item_len) < (p_rmt->rx_item_buf_size / 4)) {
  793. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
  794. memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 + p_rmt->rx_item_start_idx), item_len * 4);
  795. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
  796. p_rmt->rx_item_len += item_len;
  797. p_rmt->rx_item_start_idx += item_len;
  798. if (p_rmt->rx_item_start_idx >= mem_item_size) {
  799. p_rmt->rx_item_start_idx = 0;
  800. }
  801. } else {
  802. ESP_EARLY_LOGE(TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf));
  803. }
  804. rmt_ll_clear_rx_thres_interrupt(hal->regs, channel);
  805. }
  806. #endif
  807. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  808. // loop count interrupt
  809. status = rmt_ll_get_tx_loop_interrupt_status(hal->regs);
  810. while (status) {
  811. channel = __builtin_ffs(status) - 1;
  812. status &= ~(1 << channel);
  813. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  814. if (p_rmt) {
  815. if (p_rmt->loop_autostop) {
  816. #ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTOSTOP
  817. // hardware doesn't support automatically stop output so driver should stop output here (possibility already overshotted several us)
  818. rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
  819. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  820. #endif
  821. }
  822. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  823. if (rmt_contex.rmt_tx_end_callback.function) {
  824. rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
  825. }
  826. }
  827. rmt_ll_clear_tx_loop_interrupt(hal->regs, channel);
  828. }
  829. #endif
  830. // RX Err interrupt
  831. status = rmt_ll_get_rx_err_interrupt_status(hal->regs);
  832. while (status) {
  833. channel = __builtin_ffs(status) - 1;
  834. status &= ~(1 << channel);
  835. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  836. if (p_rmt) {
  837. // Reset the receiver's write/read addresses to prevent endless err interrupts.
  838. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
  839. ESP_EARLY_LOGD(TAG, "RMT RX channel %d error", channel);
  840. ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, channel));
  841. }
  842. rmt_ll_clear_rx_err_interrupt(hal->regs, channel);
  843. }
  844. // TX Err interrupt
  845. status = rmt_ll_get_tx_err_interrupt_status(hal->regs);
  846. while (status) {
  847. channel = __builtin_ffs(status) - 1;
  848. status &= ~(1 << channel);
  849. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  850. if (p_rmt) {
  851. // Reset the transmitter's write/read addresses to prevent endless err interrupts.
  852. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  853. ESP_EARLY_LOGD(TAG, "RMT TX channel %d error", channel);
  854. ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel));
  855. }
  856. rmt_ll_clear_tx_err_interrupt(hal->regs, channel);
  857. }
  858. if (HPTaskAwoken == pdTRUE) {
  859. portYIELD_FROM_ISR();
  860. }
  861. }
  862. esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
  863. {
  864. esp_err_t err = ESP_OK;
  865. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  866. ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels & BIT(channel), ESP_ERR_INVALID_STATE, TAG, "No RMT driver for this channel");
  867. if (p_rmt_obj[channel] == NULL) {
  868. return ESP_OK;
  869. }
  870. //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
  871. if (p_rmt_obj[channel]->wait_done) {
  872. xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
  873. }
  874. RMT_ENTER_CRITICAL();
  875. // check channel's working mode
  876. if (p_rmt_obj[channel]->rx_buf) {
  877. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  878. rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  879. #if SOC_RMT_SUPPORT_RX_PINGPONG
  880. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  881. #endif
  882. } else {
  883. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, 0);
  884. rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, 0);
  885. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
  886. }
  887. RMT_EXIT_CRITICAL();
  888. _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
  889. rmt_contex.rmt_driver_channels &= ~BIT(channel);
  890. if (rmt_contex.rmt_driver_channels == 0) {
  891. rmt_module_disable();
  892. // all channels have driver disabled
  893. err = rmt_isr_deregister(rmt_contex.rmt_driver_intr_handle);
  894. rmt_contex.rmt_driver_intr_handle = NULL;
  895. }
  896. _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
  897. if (err != ESP_OK) {
  898. return err;
  899. }
  900. if (p_rmt_obj[channel]->tx_sem) {
  901. vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
  902. p_rmt_obj[channel]->tx_sem = NULL;
  903. }
  904. if (p_rmt_obj[channel]->rx_buf) {
  905. vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
  906. p_rmt_obj[channel]->rx_buf = NULL;
  907. }
  908. if (p_rmt_obj[channel]->tx_buf) {
  909. free(p_rmt_obj[channel]->tx_buf);
  910. p_rmt_obj[channel]->tx_buf = NULL;
  911. }
  912. if (p_rmt_obj[channel]->sample_to_rmt) {
  913. p_rmt_obj[channel]->sample_to_rmt = NULL;
  914. }
  915. #if SOC_RMT_SUPPORT_RX_PINGPONG
  916. if (p_rmt_obj[channel]->rx_item_buf) {
  917. free(p_rmt_obj[channel]->rx_item_buf);
  918. p_rmt_obj[channel]->rx_item_buf = NULL;
  919. p_rmt_obj[channel]->rx_item_buf_size = 0;
  920. }
  921. #endif
  922. free(p_rmt_obj[channel]);
  923. p_rmt_obj[channel] = NULL;
  924. return ESP_OK;
  925. }
  926. esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
  927. {
  928. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  929. ESP_RETURN_ON_FALSE((rmt_contex.rmt_driver_channels & BIT(channel)) == 0, ESP_ERR_INVALID_STATE, TAG, "RMT driver already installed for channel");
  930. esp_err_t err = ESP_OK;
  931. if (p_rmt_obj[channel]) {
  932. ESP_LOGD(TAG, "RMT driver already installed");
  933. return ESP_ERR_INVALID_STATE;
  934. }
  935. #if !CONFIG_SPIRAM_USE_MALLOC
  936. p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
  937. #else
  938. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  939. p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
  940. } else {
  941. p_rmt_obj[channel] = heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  942. }
  943. #endif
  944. if (p_rmt_obj[channel] == NULL) {
  945. ESP_LOGE(TAG, "RMT driver malloc error");
  946. return ESP_ERR_NO_MEM;
  947. }
  948. p_rmt_obj[channel]->tx_len_rem = 0;
  949. p_rmt_obj[channel]->tx_data = NULL;
  950. p_rmt_obj[channel]->channel = channel;
  951. p_rmt_obj[channel]->tx_offset = 0;
  952. p_rmt_obj[channel]->tx_sub_len = 0;
  953. p_rmt_obj[channel]->wait_done = false;
  954. p_rmt_obj[channel]->loop_autostop = false;
  955. p_rmt_obj[channel]->translator = false;
  956. p_rmt_obj[channel]->sample_to_rmt = NULL;
  957. if (p_rmt_obj[channel]->tx_sem == NULL) {
  958. #if !CONFIG_SPIRAM_USE_MALLOC
  959. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  960. #else
  961. p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
  962. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  963. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  964. } else {
  965. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
  966. }
  967. #endif
  968. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  969. }
  970. if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
  971. p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
  972. }
  973. #if SOC_RMT_SUPPORT_RX_PINGPONG
  974. if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) {
  975. #if !CONFIG_SPIRAM_USE_MALLOC
  976. p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
  977. #else
  978. if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  979. p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
  980. } else {
  981. p_rmt_obj[channel]->rx_item_buf = heap_caps_calloc(1, rx_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  982. }
  983. #endif
  984. if (p_rmt_obj[channel]->rx_item_buf == NULL) {
  985. ESP_LOGE(TAG, "RMT malloc fail");
  986. return ESP_FAIL;
  987. }
  988. p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size;
  989. }
  990. #endif
  991. _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
  992. if (rmt_contex.rmt_driver_channels == 0) {
  993. // first RMT channel using driver
  994. err = rmt_isr_register(rmt_driver_isr_default, &rmt_contex.hal, intr_alloc_flags, &(rmt_contex.rmt_driver_intr_handle));
  995. }
  996. if (err == ESP_OK) {
  997. rmt_contex.rmt_driver_channels |= BIT(channel);
  998. }
  999. _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
  1000. rmt_module_enable();
  1001. if (RMT_IS_RX_CHANNEL(channel)) {
  1002. rmt_hal_rx_channel_reset(&rmt_contex.hal, RMT_DECODE_RX_CHANNEL(channel));
  1003. } else {
  1004. rmt_hal_tx_channel_reset(&rmt_contex.hal, channel);
  1005. }
  1006. return err;
  1007. }
  1008. esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done)
  1009. {
  1010. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1011. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1012. ESP_RETURN_ON_FALSE(rmt_item, ESP_FAIL, TAG, RMT_ADDR_ERROR_STR);
  1013. ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
  1014. #if CONFIG_SPIRAM_USE_MALLOC
  1015. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1016. if (!esp_ptr_internal(rmt_item)) {
  1017. ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
  1018. return ESP_ERR_INVALID_ARG;
  1019. }
  1020. }
  1021. #endif
  1022. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  1023. int block_num = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  1024. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  1025. int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
  1026. int len_rem = item_num;
  1027. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1028. // fill the memory block first
  1029. if (item_num >= item_block_len) {
  1030. rmt_fill_memory(channel, rmt_item, item_block_len, 0);
  1031. len_rem -= item_block_len;
  1032. rmt_set_tx_loop_mode(channel, false);
  1033. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  1034. p_rmt->tx_data = rmt_item + item_block_len;
  1035. p_rmt->tx_len_rem = len_rem;
  1036. p_rmt->tx_offset = 0;
  1037. p_rmt->tx_sub_len = item_sub_len;
  1038. } else {
  1039. rmt_fill_memory(channel, rmt_item, len_rem, 0);
  1040. rmt_item32_t stop_data = {0};
  1041. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, len_rem);
  1042. p_rmt->tx_len_rem = 0;
  1043. }
  1044. rmt_tx_start(channel, true);
  1045. p_rmt->wait_done = wait_tx_done;
  1046. if (wait_tx_done) {
  1047. // wait loop done
  1048. if (rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
  1049. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  1050. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1051. xSemaphoreGive(p_rmt->tx_sem);
  1052. #endif
  1053. } else {
  1054. // wait tx end
  1055. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1056. xSemaphoreGive(p_rmt->tx_sem);
  1057. }
  1058. }
  1059. return ESP_OK;
  1060. }
  1061. esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
  1062. {
  1063. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1064. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1065. if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
  1066. p_rmt_obj[channel]->wait_done = false;
  1067. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  1068. return ESP_OK;
  1069. } else {
  1070. if (wait_time != 0) {
  1071. // Don't emit error message if just polling.
  1072. ESP_LOGE(TAG, "Timeout on wait_tx_done");
  1073. }
  1074. return ESP_ERR_TIMEOUT;
  1075. }
  1076. }
  1077. esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle)
  1078. {
  1079. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1080. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1081. ESP_RETURN_ON_FALSE(buf_handle, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  1082. *buf_handle = p_rmt_obj[channel]->rx_buf;
  1083. return ESP_OK;
  1084. }
  1085. rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
  1086. {
  1087. rmt_tx_end_callback_t previous = rmt_contex.rmt_tx_end_callback;
  1088. rmt_contex.rmt_tx_end_callback.function = function;
  1089. rmt_contex.rmt_tx_end_callback.arg = arg;
  1090. return previous;
  1091. }
  1092. esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
  1093. {
  1094. ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_TRANSLATOR_NULL_STR);
  1095. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1096. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1097. const uint32_t block_size = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) *
  1098. RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
  1099. if (p_rmt_obj[channel]->tx_buf == NULL) {
  1100. #if !CONFIG_SPIRAM_USE_MALLOC
  1101. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  1102. #else
  1103. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1104. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  1105. } else {
  1106. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  1107. }
  1108. #endif
  1109. if (p_rmt_obj[channel]->tx_buf == NULL) {
  1110. ESP_LOGE(TAG, "RMT translator buffer create fail");
  1111. return ESP_FAIL;
  1112. }
  1113. }
  1114. p_rmt_obj[channel]->sample_to_rmt = fn;
  1115. p_rmt_obj[channel]->tx_context = NULL;
  1116. p_rmt_obj[channel]->sample_size_remain = 0;
  1117. p_rmt_obj[channel]->sample_cur = NULL;
  1118. ESP_LOGD(TAG, "RMT translator init done");
  1119. return ESP_OK;
  1120. }
  1121. esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context)
  1122. {
  1123. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1124. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1125. p_rmt_obj[channel]->tx_context = context;
  1126. return ESP_OK;
  1127. }
  1128. esp_err_t rmt_translator_get_context(const size_t *item_num, void **context)
  1129. {
  1130. ESP_RETURN_ON_FALSE(item_num && context, ESP_ERR_INVALID_ARG, TAG, "invalid arguments");
  1131. // the address of tx_len_rem is directlly passed to the callback,
  1132. // so it's possible to get the object address from that
  1133. rmt_obj_t *obj = __containerof(item_num, rmt_obj_t, tx_len_rem);
  1134. *context = obj->tx_context;
  1135. return ESP_OK;
  1136. }
  1137. esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
  1138. {
  1139. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1140. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1141. ESP_RETURN_ON_FALSE(p_rmt_obj[channel]->sample_to_rmt, ESP_FAIL, TAG, RMT_TRANSLATOR_UNINIT_STR);
  1142. #if CONFIG_SPIRAM_USE_MALLOC
  1143. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1144. if (!esp_ptr_internal(src)) {
  1145. ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
  1146. return ESP_ERR_INVALID_ARG;
  1147. }
  1148. }
  1149. #endif
  1150. size_t translated_size = 0;
  1151. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  1152. const uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  1153. const uint32_t item_sub_len = item_block_len / 2;
  1154. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1155. p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &p_rmt->tx_len_rem);
  1156. p_rmt->sample_size_remain = src_size - translated_size;
  1157. p_rmt->sample_cur = src + translated_size;
  1158. rmt_fill_memory(channel, p_rmt->tx_buf, p_rmt->tx_len_rem, 0);
  1159. if (p_rmt->tx_len_rem == item_block_len) {
  1160. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  1161. p_rmt->tx_data = p_rmt->tx_buf;
  1162. p_rmt->tx_offset = 0;
  1163. p_rmt->tx_sub_len = item_sub_len;
  1164. p_rmt->translator = true;
  1165. } else {
  1166. rmt_item32_t stop_data = {0};
  1167. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_len_rem);
  1168. p_rmt->tx_len_rem = 0;
  1169. p_rmt->sample_cur = NULL;
  1170. p_rmt->translator = false;
  1171. }
  1172. rmt_tx_start(channel, true);
  1173. p_rmt->wait_done = wait_tx_done;
  1174. if (wait_tx_done) {
  1175. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1176. xSemaphoreGive(p_rmt->tx_sem);
  1177. }
  1178. return ESP_OK;
  1179. }
  1180. esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
  1181. {
  1182. ESP_RETURN_ON_FALSE(channel_status, ESP_ERR_INVALID_ARG, TAG, RMT_PARAM_ERR_STR);
  1183. for (int i = 0; i < RMT_CHANNEL_MAX; i++) {
  1184. channel_status->status[i] = RMT_CHANNEL_UNINIT;
  1185. if (p_rmt_obj[i]) {
  1186. if (p_rmt_obj[i]->tx_sem) {
  1187. if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) {
  1188. channel_status->status[i] = RMT_CHANNEL_IDLE;
  1189. xSemaphoreGive(p_rmt_obj[i]->tx_sem);
  1190. } else {
  1191. channel_status->status[i] = RMT_CHANNEL_BUSY;
  1192. }
  1193. }
  1194. }
  1195. }
  1196. return ESP_OK;
  1197. }
  1198. esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
  1199. {
  1200. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1201. ESP_RETURN_ON_FALSE(clock_hz, ESP_ERR_INVALID_ARG, TAG, "parameter clock_hz can't be null");
  1202. RMT_ENTER_CRITICAL();
  1203. uint32_t rmt_source_clk_hz = 0;
  1204. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  1205. rmt_source_clk_hz = s_rmt_source_clock_hz[channel];
  1206. #else
  1207. rmt_source_clk_hz = s_rmt_source_clock_hz;
  1208. #endif
  1209. if (RMT_IS_RX_CHANNEL(channel)) {
  1210. *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  1211. } else {
  1212. *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
  1213. }
  1214. RMT_EXIT_CRITICAL();
  1215. return ESP_OK;
  1216. }
  1217. #if SOC_RMT_SUPPORT_TX_SYNCHRO
  1218. esp_err_t rmt_add_channel_to_group(rmt_channel_t channel)
  1219. {
  1220. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1221. RMT_ENTER_CRITICAL();
  1222. rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true);
  1223. rmt_contex.synchro_channel_mask |= (1 << channel);
  1224. rmt_ll_tx_add_to_sync_group(rmt_contex.hal.regs, channel);
  1225. rmt_ll_tx_reset_channels_clock_div(rmt_contex.hal.regs, rmt_contex.synchro_channel_mask);
  1226. RMT_EXIT_CRITICAL();
  1227. return ESP_OK;
  1228. }
  1229. esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel)
  1230. {
  1231. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1232. RMT_ENTER_CRITICAL();
  1233. rmt_contex.synchro_channel_mask &= ~(1 << channel);
  1234. rmt_ll_tx_remove_from_sync_group(rmt_contex.hal.regs, channel);
  1235. if (rmt_contex.synchro_channel_mask == 0) {
  1236. rmt_ll_tx_enable_sync(rmt_contex.hal.regs, false);
  1237. }
  1238. RMT_EXIT_CRITICAL();
  1239. return ESP_OK;
  1240. }
  1241. #endif
  1242. esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
  1243. {
  1244. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1245. RMT_ENTER_CRITICAL();
  1246. if (RMT_IS_RX_CHANNEL(channel)) {
  1247. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  1248. } else {
  1249. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  1250. }
  1251. RMT_EXIT_CRITICAL();
  1252. return ESP_OK;
  1253. }
  1254. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  1255. esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count)
  1256. {
  1257. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1258. ESP_RETURN_ON_FALSE(count <= RMT_LL_MAX_LOOP_COUNT, ESP_ERR_INVALID_ARG, TAG, "Invalid count value");
  1259. RMT_ENTER_CRITICAL();
  1260. rmt_ll_tx_set_loop_count(rmt_contex.hal.regs, channel, count);
  1261. RMT_EXIT_CRITICAL();
  1262. return ESP_OK;
  1263. }
  1264. esp_err_t rmt_enable_tx_loop_autostop(rmt_channel_t channel, bool en)
  1265. {
  1266. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1267. p_rmt_obj[channel]->loop_autostop = en;
  1268. #if SOC_RMT_SUPPORT_TX_LOOP_AUTOSTOP
  1269. RMT_ENTER_CRITICAL();
  1270. rmt_ll_tx_enable_loop_autostop(rmt_contex.hal.regs, channel, en);
  1271. RMT_EXIT_CRITICAL();
  1272. #endif
  1273. return ESP_OK;
  1274. }
  1275. #endif