esp_efuse_table.c 33 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "sdkconfig.h"
  7. #include "esp_efuse.h"
  8. #include <assert.h>
  9. #include "esp_efuse_table.h"
  10. // md5_digest_table ef33779021404fbaddc878eefebaddc1
  11. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  12. // If you want to change some fields, you need to change esp_efuse_table.csv file
  13. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  14. // To show efuse_table run the command 'show_efuse_table'.
  15. static const esp_efuse_desc_t WR_DIS[] = {
  16. {EFUSE_BLK0, 0, 32}, // Write protection,
  17. };
  18. static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
  19. {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
  20. };
  21. static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
  22. {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
  23. };
  24. static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
  25. {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL,
  26. };
  27. static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  28. {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT,
  29. };
  30. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  31. {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0,
  32. };
  33. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  34. {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1,
  35. };
  36. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  37. {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2,
  38. };
  39. static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
  40. {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0,
  41. };
  42. static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
  43. {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1,
  44. };
  45. static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
  46. {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2,
  47. };
  48. static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
  49. {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3,
  50. };
  51. static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
  52. {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4,
  53. };
  54. static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
  55. {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5,
  56. };
  57. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
  58. {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN,
  59. };
  60. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  61. {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
  62. };
  63. static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
  64. {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
  65. };
  66. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  67. {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS,
  68. };
  69. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
  70. {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1,
  71. };
  72. static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
  73. {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA,
  74. };
  75. static const esp_efuse_desc_t WR_DIS_KEY0[] = {
  76. {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0,
  77. };
  78. static const esp_efuse_desc_t WR_DIS_KEY1[] = {
  79. {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1,
  80. };
  81. static const esp_efuse_desc_t WR_DIS_KEY2[] = {
  82. {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2,
  83. };
  84. static const esp_efuse_desc_t WR_DIS_KEY3[] = {
  85. {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3,
  86. };
  87. static const esp_efuse_desc_t WR_DIS_KEY4[] = {
  88. {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4,
  89. };
  90. static const esp_efuse_desc_t WR_DIS_KEY5[] = {
  91. {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5,
  92. };
  93. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
  94. {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
  95. };
  96. static const esp_efuse_desc_t RD_DIS[] = {
  97. {EFUSE_BLK0, 32, 7}, // Read protection,
  98. };
  99. static const esp_efuse_desc_t RD_DIS_KEY0[] = {
  100. {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0,
  101. };
  102. static const esp_efuse_desc_t RD_DIS_KEY1[] = {
  103. {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1,
  104. };
  105. static const esp_efuse_desc_t RD_DIS_KEY2[] = {
  106. {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2,
  107. };
  108. static const esp_efuse_desc_t RD_DIS_KEY3[] = {
  109. {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3,
  110. };
  111. static const esp_efuse_desc_t RD_DIS_KEY4[] = {
  112. {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4,
  113. };
  114. static const esp_efuse_desc_t RD_DIS_KEY5[] = {
  115. {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5,
  116. };
  117. static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
  118. {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
  119. };
  120. static const esp_efuse_desc_t DIS_ICACHE[] = {
  121. {EFUSE_BLK0, 40, 1}, // Disable Icache,
  122. };
  123. static const esp_efuse_desc_t DIS_USB_JTAG[] = {
  124. {EFUSE_BLK0, 41, 1}, // Disable USB JTAG,
  125. };
  126. static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
  127. {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode,
  128. };
  129. static const esp_efuse_desc_t DIS_USB_DEVICE[] = {
  130. {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE,
  131. };
  132. static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
  133. {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
  134. };
  135. static const esp_efuse_desc_t DIS_USB[] = {
  136. {EFUSE_BLK0, 45, 1}, // Disable USB function,
  137. };
  138. static const esp_efuse_desc_t DIS_CAN[] = {
  139. {EFUSE_BLK0, 46, 1}, // Disable CAN function,
  140. };
  141. static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
  142. {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.,
  143. };
  144. static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
  145. {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.,
  146. };
  147. static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
  148. {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently.,
  149. };
  150. static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  151. {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes.,
  152. };
  153. static const esp_efuse_desc_t USB_DREFH[] = {
  154. {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.,
  155. };
  156. static const esp_efuse_desc_t USB_DREFL[] = {
  157. {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.,
  158. };
  159. static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
  160. {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins,
  161. };
  162. static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
  163. {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio,
  164. };
  165. static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = {
  166. {EFUSE_BLK0, 59, 2}, // Enable btlc gpio,
  167. };
  168. static const esp_efuse_desc_t POWERGLITCH_EN[] = {
  169. {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function,
  170. };
  171. static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = {
  172. {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch,
  173. };
  174. static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
  175. {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold,
  176. };
  177. static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
  178. {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
  179. };
  180. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
  181. {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key,
  182. };
  183. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
  184. {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key,
  185. };
  186. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
  187. {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key,
  188. };
  189. static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
  190. {EFUSE_BLK0, 88, 4}, // Key0 purpose,
  191. };
  192. static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
  193. {EFUSE_BLK0, 92, 4}, // Key1 purpose,
  194. };
  195. static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
  196. {EFUSE_BLK0, 96, 4}, // Key2 purpose,
  197. };
  198. static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
  199. {EFUSE_BLK0, 100, 4}, // Key3 purpose,
  200. };
  201. static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
  202. {EFUSE_BLK0, 104, 4}, // Key4 purpose,
  203. };
  204. static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
  205. {EFUSE_BLK0, 108, 4}, // Key5 purpose,
  206. };
  207. static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
  208. {EFUSE_BLK0, 116, 1}, // Secure boot enable,
  209. };
  210. static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  211. {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke,
  212. };
  213. static const esp_efuse_desc_t FLASH_TPUW[] = {
  214. {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
  215. };
  216. static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
  217. {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
  218. };
  219. static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
  220. {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
  221. };
  222. static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
  223. {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1,
  224. };
  225. static const esp_efuse_desc_t FLASH_ECC_MODE[] = {
  226. {EFUSE_BLK0, 131, 1}, // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode,
  227. };
  228. static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
  229. {EFUSE_BLK0, 132, 1}, // Disable download through USB,
  230. };
  231. static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
  232. {EFUSE_BLK0, 133, 1}, // Enable security download mode,
  233. };
  234. static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
  235. {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.,
  236. };
  237. static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
  238. {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
  239. };
  240. static const esp_efuse_desc_t FLASH_TYPE[] = {
  241. {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
  242. };
  243. static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
  244. {EFUSE_BLK0, 138, 2}, // Flash page size,
  245. };
  246. static const esp_efuse_desc_t FLASH_ECC_EN[] = {
  247. {EFUSE_BLK0, 140, 1}, // Enable ECC for flash boot,
  248. };
  249. static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
  250. {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot,
  251. };
  252. static const esp_efuse_desc_t SECURE_VERSION[] = {
  253. {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
  254. };
  255. static const esp_efuse_desc_t MAC_FACTORY[] = {
  256. {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
  257. {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
  258. {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2],
  259. {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3],
  260. {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4],
  261. {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
  262. };
  263. static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
  264. {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
  265. };
  266. static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
  267. {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
  268. };
  269. static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
  270. {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
  271. };
  272. static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
  273. {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
  274. };
  275. static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
  276. {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
  277. };
  278. static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
  279. {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
  280. };
  281. static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
  282. {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
  283. };
  284. static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
  285. {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
  286. };
  287. static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
  288. {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
  289. };
  290. static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
  291. {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
  292. };
  293. static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
  294. {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
  295. };
  296. static const esp_efuse_desc_t WAFER_VERSION[] = {
  297. {EFUSE_BLK1, 114, 3}, // WAFER version,
  298. };
  299. static const esp_efuse_desc_t PKG_VERSION[] = {
  300. {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3,
  301. };
  302. static const esp_efuse_desc_t BLOCK1_VERSION[] = {
  303. {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
  304. };
  305. static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
  306. {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
  307. };
  308. static const esp_efuse_desc_t BLOCK2_VERSION[] = {
  309. {EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
  310. };
  311. static const esp_efuse_desc_t TEMP_CALIB[] = {
  312. {EFUSE_BLK2, 131, 9}, // Temperature calibration data,
  313. };
  314. static const esp_efuse_desc_t OCODE[] = {
  315. {EFUSE_BLK2, 140, 8}, // ADC OCode,
  316. };
  317. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
  318. {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0,
  319. };
  320. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
  321. {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1,
  322. };
  323. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
  324. {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2,
  325. };
  326. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
  327. {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3,
  328. };
  329. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
  330. {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0,
  331. };
  332. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
  333. {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1,
  334. };
  335. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
  336. {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2,
  337. };
  338. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
  339. {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3,
  340. };
  341. static const esp_efuse_desc_t USER_DATA[] = {
  342. {EFUSE_BLK3, 0, 256}, // User data,
  343. };
  344. static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
  345. {EFUSE_BLK3, 200, 48}, // Custom MAC,
  346. };
  347. static const esp_efuse_desc_t KEY0[] = {
  348. {EFUSE_BLK4, 0, 256}, // Key0 or user data,
  349. };
  350. static const esp_efuse_desc_t KEY1[] = {
  351. {EFUSE_BLK5, 0, 256}, // Key1 or user data,
  352. };
  353. static const esp_efuse_desc_t KEY2[] = {
  354. {EFUSE_BLK6, 0, 256}, // Key2 or user data,
  355. };
  356. static const esp_efuse_desc_t KEY3[] = {
  357. {EFUSE_BLK7, 0, 256}, // Key3 or user data,
  358. };
  359. static const esp_efuse_desc_t KEY4[] = {
  360. {EFUSE_BLK8, 0, 256}, // Key4 or user data,
  361. };
  362. static const esp_efuse_desc_t KEY5[] = {
  363. {EFUSE_BLK9, 0, 256}, // Key5 or user data,
  364. };
  365. static const esp_efuse_desc_t SYS_DATA_PART2[] = {
  366. {EFUSE_BLK10, 0, 256}, // System configuration,
  367. };
  368. static const esp_efuse_desc_t K_RTC_LDO[] = {
  369. {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO,
  370. };
  371. static const esp_efuse_desc_t K_DIG_LDO[] = {
  372. {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO,
  373. };
  374. static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
  375. {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20,
  376. };
  377. static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
  378. {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20,
  379. };
  380. static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
  381. {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt,
  382. };
  383. static const esp_efuse_desc_t THRES_HVT[] = {
  384. {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt,
  385. };
  386. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
  387. &WR_DIS[0], // Write protection
  388. NULL
  389. };
  390. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
  391. &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
  392. NULL
  393. };
  394. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
  395. &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
  396. NULL
  397. };
  398. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
  399. &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL
  400. NULL
  401. };
  402. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  403. &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT
  404. NULL
  405. };
  406. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  407. &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0
  408. NULL
  409. };
  410. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  411. &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1
  412. NULL
  413. };
  414. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  415. &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2
  416. NULL
  417. };
  418. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
  419. &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0
  420. NULL
  421. };
  422. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
  423. &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1
  424. NULL
  425. };
  426. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
  427. &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2
  428. NULL
  429. };
  430. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
  431. &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3
  432. NULL
  433. };
  434. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
  435. &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4
  436. NULL
  437. };
  438. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
  439. &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5
  440. NULL
  441. };
  442. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
  443. &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN
  444. NULL
  445. };
  446. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  447. &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
  448. NULL
  449. };
  450. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
  451. &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
  452. NULL
  453. };
  454. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  455. &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
  456. NULL
  457. };
  458. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
  459. &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1
  460. NULL
  461. };
  462. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
  463. &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA
  464. NULL
  465. };
  466. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
  467. &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0
  468. NULL
  469. };
  470. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
  471. &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1
  472. NULL
  473. };
  474. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
  475. &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2
  476. NULL
  477. };
  478. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
  479. &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3
  480. NULL
  481. };
  482. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
  483. &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4
  484. NULL
  485. };
  486. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
  487. &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5
  488. NULL
  489. };
  490. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
  491. &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2
  492. NULL
  493. };
  494. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
  495. &RD_DIS[0], // Read protection
  496. NULL
  497. };
  498. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
  499. &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0
  500. NULL
  501. };
  502. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
  503. &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1
  504. NULL
  505. };
  506. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
  507. &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2
  508. NULL
  509. };
  510. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
  511. &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3
  512. NULL
  513. };
  514. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
  515. &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4
  516. NULL
  517. };
  518. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
  519. &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5
  520. NULL
  521. };
  522. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
  523. &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2
  524. NULL
  525. };
  526. const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
  527. &DIS_ICACHE[0], // Disable Icache
  528. NULL
  529. };
  530. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
  531. &DIS_USB_JTAG[0], // Disable USB JTAG
  532. NULL
  533. };
  534. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
  535. &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode
  536. NULL
  537. };
  538. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = {
  539. &DIS_USB_DEVICE[0], // Disable USB_DEVICE
  540. NULL
  541. };
  542. const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
  543. &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function
  544. NULL
  545. };
  546. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
  547. &DIS_USB[0], // Disable USB function
  548. NULL
  549. };
  550. const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
  551. &DIS_CAN[0], // Disable CAN function
  552. NULL
  553. };
  554. const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
  555. &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
  556. NULL
  557. };
  558. const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
  559. &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
  560. NULL
  561. };
  562. const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
  563. &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently.
  564. NULL
  565. };
  566. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  567. &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes.
  568. NULL
  569. };
  570. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = {
  571. &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
  572. NULL
  573. };
  574. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = {
  575. &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
  576. NULL
  577. };
  578. const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
  579. &USB_EXCHG_PINS[0], // Exchange D+ D- pins
  580. NULL
  581. };
  582. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
  583. &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio
  584. NULL
  585. };
  586. const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = {
  587. &BTLC_GPIO_ENABLE[0], // Enable btlc gpio
  588. NULL
  589. };
  590. const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
  591. &POWERGLITCH_EN[0], // Set this bit to enable power glitch function
  592. NULL
  593. };
  594. const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = {
  595. &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch
  596. NULL
  597. };
  598. const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
  599. &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold
  600. NULL
  601. };
  602. const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
  603. &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
  604. NULL
  605. };
  606. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
  607. &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key
  608. NULL
  609. };
  610. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
  611. &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key
  612. NULL
  613. };
  614. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
  615. &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key
  616. NULL
  617. };
  618. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
  619. &KEY_PURPOSE_0[0], // Key0 purpose
  620. NULL
  621. };
  622. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
  623. &KEY_PURPOSE_1[0], // Key1 purpose
  624. NULL
  625. };
  626. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
  627. &KEY_PURPOSE_2[0], // Key2 purpose
  628. NULL
  629. };
  630. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
  631. &KEY_PURPOSE_3[0], // Key3 purpose
  632. NULL
  633. };
  634. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
  635. &KEY_PURPOSE_4[0], // Key4 purpose
  636. NULL
  637. };
  638. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
  639. &KEY_PURPOSE_5[0], // Key5 purpose
  640. NULL
  641. };
  642. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
  643. &SECURE_BOOT_EN[0], // Secure boot enable
  644. NULL
  645. };
  646. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  647. &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke
  648. NULL
  649. };
  650. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
  651. &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
  652. NULL
  653. };
  654. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
  655. &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
  656. NULL
  657. };
  658. const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
  659. &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
  660. NULL
  661. };
  662. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
  663. &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1
  664. NULL
  665. };
  666. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = {
  667. &FLASH_ECC_MODE[0], // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode
  668. NULL
  669. };
  670. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
  671. &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
  672. NULL
  673. };
  674. const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
  675. &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
  676. NULL
  677. };
  678. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
  679. &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
  680. NULL
  681. };
  682. const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
  683. &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
  684. NULL
  685. };
  686. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
  687. &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line
  688. NULL
  689. };
  690. const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
  691. &FLASH_PAGE_SIZE[0], // Flash page size
  692. NULL
  693. };
  694. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
  695. &FLASH_ECC_EN[0], // Enable ECC for flash boot
  696. NULL
  697. };
  698. const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
  699. &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot
  700. NULL
  701. };
  702. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  703. &SECURE_VERSION[0], // Secure version for anti-rollback
  704. NULL
  705. };
  706. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
  707. &MAC_FACTORY[0], // Factory MAC addr [0]
  708. &MAC_FACTORY[1], // Factory MAC addr [1]
  709. &MAC_FACTORY[2], // Factory MAC addr [2]
  710. &MAC_FACTORY[3], // Factory MAC addr [3]
  711. &MAC_FACTORY[4], // Factory MAC addr [4]
  712. &MAC_FACTORY[5], // Factory MAC addr [5]
  713. NULL
  714. };
  715. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
  716. &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
  717. NULL
  718. };
  719. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
  720. &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
  721. NULL
  722. };
  723. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
  724. &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
  725. NULL
  726. };
  727. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
  728. &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
  729. NULL
  730. };
  731. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
  732. &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
  733. NULL
  734. };
  735. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
  736. &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
  737. NULL
  738. };
  739. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
  740. &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
  741. NULL
  742. };
  743. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
  744. &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
  745. NULL
  746. };
  747. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
  748. &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
  749. NULL
  750. };
  751. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
  752. &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
  753. NULL
  754. };
  755. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
  756. &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
  757. NULL
  758. };
  759. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
  760. &WAFER_VERSION[0], // WAFER version
  761. NULL
  762. };
  763. const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
  764. &PKG_VERSION[0], // Package version 0:ESP32C3
  765. NULL
  766. };
  767. const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
  768. &BLOCK1_VERSION[0], // BLOCK1 efuse version
  769. NULL
  770. };
  771. const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
  772. &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
  773. NULL
  774. };
  775. const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
  776. &BLOCK2_VERSION[0], // Version of BLOCK2
  777. NULL
  778. };
  779. const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
  780. &TEMP_CALIB[0], // Temperature calibration data
  781. NULL
  782. };
  783. const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
  784. &OCODE[0], // ADC OCode
  785. NULL
  786. };
  787. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
  788. &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0
  789. NULL
  790. };
  791. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
  792. &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1
  793. NULL
  794. };
  795. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
  796. &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2
  797. NULL
  798. };
  799. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
  800. &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3
  801. NULL
  802. };
  803. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
  804. &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0
  805. NULL
  806. };
  807. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
  808. &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1
  809. NULL
  810. };
  811. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
  812. &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2
  813. NULL
  814. };
  815. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
  816. &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3
  817. NULL
  818. };
  819. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
  820. &USER_DATA[0], // User data
  821. NULL
  822. };
  823. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
  824. &USER_DATA_MAC_CUSTOM[0], // Custom MAC
  825. NULL
  826. };
  827. const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
  828. &KEY0[0], // Key0 or user data
  829. NULL
  830. };
  831. const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
  832. &KEY1[0], // Key1 or user data
  833. NULL
  834. };
  835. const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
  836. &KEY2[0], // Key2 or user data
  837. NULL
  838. };
  839. const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
  840. &KEY3[0], // Key3 or user data
  841. NULL
  842. };
  843. const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
  844. &KEY4[0], // Key4 or user data
  845. NULL
  846. };
  847. const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
  848. &KEY5[0], // Key5 or user data
  849. NULL
  850. };
  851. const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
  852. &SYS_DATA_PART2[0], // System configuration
  853. NULL
  854. };
  855. const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
  856. &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO
  857. NULL
  858. };
  859. const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
  860. &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO
  861. NULL
  862. };
  863. const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
  864. &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20
  865. NULL
  866. };
  867. const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
  868. &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20
  869. NULL
  870. };
  871. const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
  872. &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt
  873. NULL
  874. };
  875. const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = {
  876. &THRES_HVT[0], // BLOCK1 pvt threshold when hvt
  877. NULL
  878. };