esp_efuse_table.c 32 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "sdkconfig.h"
  7. #include "esp_efuse.h"
  8. #include <assert.h>
  9. #include "esp_efuse_table.h"
  10. // md5_digest_table a007943ae37fe41884a23d505a6e7dbb
  11. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  12. // If you want to change some fields, you need to change esp_efuse_table.csv file
  13. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  14. // To show efuse_table run the command 'show_efuse_table'.
  15. static const esp_efuse_desc_t WR_DIS[] = {
  16. {EFUSE_BLK0, 0, 32}, // Write protection,
  17. };
  18. static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
  19. {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
  20. };
  21. static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
  22. {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
  23. };
  24. static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
  25. {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL,
  26. };
  27. static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  28. {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT,
  29. };
  30. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  31. {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0,
  32. };
  33. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  34. {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1,
  35. };
  36. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  37. {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2,
  38. };
  39. static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
  40. {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0,
  41. };
  42. static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
  43. {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1,
  44. };
  45. static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
  46. {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2,
  47. };
  48. static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
  49. {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3,
  50. };
  51. static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
  52. {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4,
  53. };
  54. static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
  55. {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5,
  56. };
  57. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
  58. {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN,
  59. };
  60. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  61. {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
  62. };
  63. static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
  64. {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
  65. };
  66. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  67. {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS,
  68. };
  69. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
  70. {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1,
  71. };
  72. static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
  73. {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA,
  74. };
  75. static const esp_efuse_desc_t WR_DIS_KEY0[] = {
  76. {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0,
  77. };
  78. static const esp_efuse_desc_t WR_DIS_KEY1[] = {
  79. {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1,
  80. };
  81. static const esp_efuse_desc_t WR_DIS_KEY2[] = {
  82. {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2,
  83. };
  84. static const esp_efuse_desc_t WR_DIS_KEY3[] = {
  85. {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3,
  86. };
  87. static const esp_efuse_desc_t WR_DIS_KEY4[] = {
  88. {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4,
  89. };
  90. static const esp_efuse_desc_t WR_DIS_KEY5[] = {
  91. {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5,
  92. };
  93. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
  94. {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
  95. };
  96. static const esp_efuse_desc_t RD_DIS[] = {
  97. {EFUSE_BLK0, 32, 7}, // Read protection,
  98. };
  99. static const esp_efuse_desc_t RD_DIS_KEY0[] = {
  100. {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0,
  101. };
  102. static const esp_efuse_desc_t RD_DIS_KEY1[] = {
  103. {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1,
  104. };
  105. static const esp_efuse_desc_t RD_DIS_KEY2[] = {
  106. {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2,
  107. };
  108. static const esp_efuse_desc_t RD_DIS_KEY3[] = {
  109. {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3,
  110. };
  111. static const esp_efuse_desc_t RD_DIS_KEY4[] = {
  112. {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4,
  113. };
  114. static const esp_efuse_desc_t RD_DIS_KEY5[] = {
  115. {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5,
  116. };
  117. static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
  118. {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
  119. };
  120. static const esp_efuse_desc_t DIS_ICACHE[] = {
  121. {EFUSE_BLK0, 40, 1}, // Disable Icache,
  122. };
  123. static const esp_efuse_desc_t DIS_USB_JTAG[] = {
  124. {EFUSE_BLK0, 41, 1}, // Disable USB JTAG,
  125. };
  126. static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
  127. {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode,
  128. };
  129. static const esp_efuse_desc_t DIS_USB_DEVICE[] = {
  130. {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE,
  131. };
  132. static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
  133. {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
  134. };
  135. static const esp_efuse_desc_t DIS_USB[] = {
  136. {EFUSE_BLK0, 45, 1}, // Disable USB function,
  137. };
  138. static const esp_efuse_desc_t DIS_CAN[] = {
  139. {EFUSE_BLK0, 46, 1}, // Disable CAN function,
  140. };
  141. static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
  142. {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.,
  143. };
  144. static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
  145. {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.,
  146. };
  147. static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
  148. {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently.,
  149. };
  150. static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  151. {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes.,
  152. };
  153. static const esp_efuse_desc_t USB_DREFH[] = {
  154. {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.,
  155. };
  156. static const esp_efuse_desc_t USB_DREFL[] = {
  157. {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.,
  158. };
  159. static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
  160. {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins,
  161. };
  162. static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
  163. {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio,
  164. };
  165. static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = {
  166. {EFUSE_BLK0, 59, 2}, // Enable btlc gpio,
  167. };
  168. static const esp_efuse_desc_t POWERGLITCH_EN[] = {
  169. {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function,
  170. };
  171. static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = {
  172. {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch,
  173. };
  174. static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
  175. {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold,
  176. };
  177. static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
  178. {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
  179. };
  180. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
  181. {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key,
  182. };
  183. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
  184. {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key,
  185. };
  186. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
  187. {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key,
  188. };
  189. static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
  190. {EFUSE_BLK0, 88, 4}, // Key0 purpose,
  191. };
  192. static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
  193. {EFUSE_BLK0, 92, 4}, // Key1 purpose,
  194. };
  195. static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
  196. {EFUSE_BLK0, 96, 4}, // Key2 purpose,
  197. };
  198. static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
  199. {EFUSE_BLK0, 100, 4}, // Key3 purpose,
  200. };
  201. static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
  202. {EFUSE_BLK0, 104, 4}, // Key4 purpose,
  203. };
  204. static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
  205. {EFUSE_BLK0, 108, 4}, // Key5 purpose,
  206. };
  207. static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
  208. {EFUSE_BLK0, 116, 1}, // Secure boot enable,
  209. };
  210. static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  211. {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke,
  212. };
  213. static const esp_efuse_desc_t FLASH_TPUW[] = {
  214. {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
  215. };
  216. static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
  217. {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
  218. };
  219. static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
  220. {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
  221. };
  222. static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
  223. {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1,
  224. };
  225. static const esp_efuse_desc_t FLASH_ECC_MODE[] = {
  226. {EFUSE_BLK0, 131, 1}, // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode,
  227. };
  228. static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
  229. {EFUSE_BLK0, 132, 1}, // Disable download through USB,
  230. };
  231. static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
  232. {EFUSE_BLK0, 133, 1}, // Enable security download mode,
  233. };
  234. static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
  235. {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.,
  236. };
  237. static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
  238. {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
  239. };
  240. static const esp_efuse_desc_t FLASH_TYPE[] = {
  241. {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
  242. };
  243. static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
  244. {EFUSE_BLK0, 138, 2}, // Flash page size,
  245. };
  246. static const esp_efuse_desc_t FLASH_ECC_EN[] = {
  247. {EFUSE_BLK0, 140, 1}, // Enable ECC for flash boot,
  248. };
  249. static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
  250. {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot,
  251. };
  252. static const esp_efuse_desc_t SECURE_VERSION[] = {
  253. {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
  254. };
  255. static const esp_efuse_desc_t BOOT_DISABLE_FAST_WAKE[] = {
  256. {EFUSE_BLK0, 158, 1}, // Fast verify on wake option in ROM for Secure Boot,
  257. };
  258. static const esp_efuse_desc_t MAC_FACTORY[] = {
  259. {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
  260. {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
  261. {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2],
  262. {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3],
  263. {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4],
  264. {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
  265. };
  266. static const esp_efuse_desc_t MAC_EXT[] = {
  267. {EFUSE_BLK1, 123, 8}, // Factory MAC addr [6],
  268. {EFUSE_BLK1, 131, 8}, // Factory MAC addr [7],
  269. };
  270. static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
  271. {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
  272. };
  273. static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
  274. {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
  275. };
  276. static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
  277. {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
  278. };
  279. static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
  280. {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
  281. };
  282. static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
  283. {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
  284. };
  285. static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
  286. {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
  287. };
  288. static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
  289. {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
  290. };
  291. static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
  292. {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
  293. };
  294. static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
  295. {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
  296. };
  297. static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
  298. {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
  299. };
  300. static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
  301. {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
  302. };
  303. static const esp_efuse_desc_t WAFER_VERSION[] = {
  304. {EFUSE_BLK1, 114, 3}, // WAFER version,
  305. };
  306. static const esp_efuse_desc_t PKG_VERSION[] = {
  307. {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H2,
  308. };
  309. static const esp_efuse_desc_t BLOCK1_VERSION[] = {
  310. {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
  311. };
  312. static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
  313. {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
  314. };
  315. static const esp_efuse_desc_t BLOCK2_VERSION[] = {
  316. {EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
  317. };
  318. static const esp_efuse_desc_t TEMP_CALIB[] = {
  319. {EFUSE_BLK2, 131, 9}, // Temperature calibration data,
  320. };
  321. static const esp_efuse_desc_t OCODE[] = {
  322. {EFUSE_BLK2, 140, 8}, // ADC OCode,
  323. };
  324. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
  325. {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0,
  326. };
  327. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
  328. {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1,
  329. };
  330. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
  331. {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2,
  332. };
  333. static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
  334. {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3,
  335. };
  336. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
  337. {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0,
  338. };
  339. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
  340. {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1,
  341. };
  342. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
  343. {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2,
  344. };
  345. static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
  346. {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3,
  347. };
  348. static const esp_efuse_desc_t USER_DATA[] = {
  349. {EFUSE_BLK3, 0, 256}, // User data,
  350. };
  351. static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
  352. {EFUSE_BLK3, 200, 48}, // Custom MAC,
  353. };
  354. static const esp_efuse_desc_t KEY0[] = {
  355. {EFUSE_BLK4, 0, 256}, // Key0 or user data,
  356. };
  357. static const esp_efuse_desc_t KEY1[] = {
  358. {EFUSE_BLK5, 0, 256}, // Key1 or user data,
  359. };
  360. static const esp_efuse_desc_t KEY2[] = {
  361. {EFUSE_BLK6, 0, 256}, // Key2 or user data,
  362. };
  363. static const esp_efuse_desc_t KEY3[] = {
  364. {EFUSE_BLK7, 0, 256}, // Key3 or user data,
  365. };
  366. static const esp_efuse_desc_t KEY4[] = {
  367. {EFUSE_BLK8, 0, 256}, // Key4 or user data,
  368. };
  369. static const esp_efuse_desc_t KEY5[] = {
  370. {EFUSE_BLK9, 0, 256}, // Key5 or user data,
  371. };
  372. static const esp_efuse_desc_t SYS_DATA_PART2[] = {
  373. {EFUSE_BLK10, 0, 256}, // System configuration,
  374. };
  375. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
  376. &WR_DIS[0], // Write protection
  377. NULL
  378. };
  379. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
  380. &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
  381. NULL
  382. };
  383. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
  384. &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
  385. NULL
  386. };
  387. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
  388. &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL
  389. NULL
  390. };
  391. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  392. &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT
  393. NULL
  394. };
  395. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  396. &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0
  397. NULL
  398. };
  399. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  400. &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1
  401. NULL
  402. };
  403. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  404. &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2
  405. NULL
  406. };
  407. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
  408. &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0
  409. NULL
  410. };
  411. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
  412. &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1
  413. NULL
  414. };
  415. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
  416. &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2
  417. NULL
  418. };
  419. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
  420. &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3
  421. NULL
  422. };
  423. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
  424. &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4
  425. NULL
  426. };
  427. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
  428. &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5
  429. NULL
  430. };
  431. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
  432. &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN
  433. NULL
  434. };
  435. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  436. &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
  437. NULL
  438. };
  439. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
  440. &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
  441. NULL
  442. };
  443. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  444. &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
  445. NULL
  446. };
  447. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
  448. &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1
  449. NULL
  450. };
  451. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
  452. &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA
  453. NULL
  454. };
  455. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
  456. &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0
  457. NULL
  458. };
  459. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
  460. &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1
  461. NULL
  462. };
  463. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
  464. &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2
  465. NULL
  466. };
  467. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
  468. &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3
  469. NULL
  470. };
  471. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
  472. &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4
  473. NULL
  474. };
  475. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
  476. &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5
  477. NULL
  478. };
  479. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
  480. &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2
  481. NULL
  482. };
  483. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
  484. &RD_DIS[0], // Read protection
  485. NULL
  486. };
  487. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
  488. &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0
  489. NULL
  490. };
  491. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
  492. &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1
  493. NULL
  494. };
  495. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
  496. &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2
  497. NULL
  498. };
  499. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
  500. &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3
  501. NULL
  502. };
  503. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
  504. &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4
  505. NULL
  506. };
  507. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
  508. &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5
  509. NULL
  510. };
  511. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
  512. &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2
  513. NULL
  514. };
  515. const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
  516. &DIS_ICACHE[0], // Disable Icache
  517. NULL
  518. };
  519. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
  520. &DIS_USB_JTAG[0], // Disable USB JTAG
  521. NULL
  522. };
  523. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
  524. &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode
  525. NULL
  526. };
  527. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = {
  528. &DIS_USB_DEVICE[0], // Disable USB_DEVICE
  529. NULL
  530. };
  531. const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
  532. &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function
  533. NULL
  534. };
  535. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
  536. &DIS_USB[0], // Disable USB function
  537. NULL
  538. };
  539. const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
  540. &DIS_CAN[0], // Disable CAN function
  541. NULL
  542. };
  543. const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
  544. &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
  545. NULL
  546. };
  547. const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
  548. &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
  549. NULL
  550. };
  551. const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
  552. &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently.
  553. NULL
  554. };
  555. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  556. &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes.
  557. NULL
  558. };
  559. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = {
  560. &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
  561. NULL
  562. };
  563. const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = {
  564. &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
  565. NULL
  566. };
  567. const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
  568. &USB_EXCHG_PINS[0], // Exchange D+ D- pins
  569. NULL
  570. };
  571. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
  572. &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio
  573. NULL
  574. };
  575. const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = {
  576. &BTLC_GPIO_ENABLE[0], // Enable btlc gpio
  577. NULL
  578. };
  579. const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
  580. &POWERGLITCH_EN[0], // Set this bit to enable power glitch function
  581. NULL
  582. };
  583. const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = {
  584. &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch
  585. NULL
  586. };
  587. const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
  588. &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold
  589. NULL
  590. };
  591. const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
  592. &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
  593. NULL
  594. };
  595. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
  596. &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key
  597. NULL
  598. };
  599. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
  600. &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key
  601. NULL
  602. };
  603. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
  604. &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key
  605. NULL
  606. };
  607. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
  608. &KEY_PURPOSE_0[0], // Key0 purpose
  609. NULL
  610. };
  611. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
  612. &KEY_PURPOSE_1[0], // Key1 purpose
  613. NULL
  614. };
  615. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
  616. &KEY_PURPOSE_2[0], // Key2 purpose
  617. NULL
  618. };
  619. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
  620. &KEY_PURPOSE_3[0], // Key3 purpose
  621. NULL
  622. };
  623. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
  624. &KEY_PURPOSE_4[0], // Key4 purpose
  625. NULL
  626. };
  627. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
  628. &KEY_PURPOSE_5[0], // Key5 purpose
  629. NULL
  630. };
  631. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
  632. &SECURE_BOOT_EN[0], // Secure boot enable
  633. NULL
  634. };
  635. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  636. &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke
  637. NULL
  638. };
  639. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
  640. &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
  641. NULL
  642. };
  643. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
  644. &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
  645. NULL
  646. };
  647. const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
  648. &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
  649. NULL
  650. };
  651. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
  652. &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1
  653. NULL
  654. };
  655. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = {
  656. &FLASH_ECC_MODE[0], // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode
  657. NULL
  658. };
  659. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
  660. &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
  661. NULL
  662. };
  663. const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
  664. &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
  665. NULL
  666. };
  667. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
  668. &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
  669. NULL
  670. };
  671. const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
  672. &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
  673. NULL
  674. };
  675. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
  676. &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line
  677. NULL
  678. };
  679. const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
  680. &FLASH_PAGE_SIZE[0], // Flash page size
  681. NULL
  682. };
  683. const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
  684. &FLASH_ECC_EN[0], // Enable ECC for flash boot
  685. NULL
  686. };
  687. const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
  688. &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot
  689. NULL
  690. };
  691. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  692. &SECURE_VERSION[0], // Secure version for anti-rollback
  693. NULL
  694. };
  695. const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[] = {
  696. &BOOT_DISABLE_FAST_WAKE[0], // Fast verify on wake option in ROM for Secure Boot
  697. NULL
  698. };
  699. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
  700. &MAC_FACTORY[0], // Factory MAC addr [0]
  701. &MAC_FACTORY[1], // Factory MAC addr [1]
  702. &MAC_FACTORY[2], // Factory MAC addr [2]
  703. &MAC_FACTORY[3], // Factory MAC addr [3]
  704. &MAC_FACTORY[4], // Factory MAC addr [4]
  705. &MAC_FACTORY[5], // Factory MAC addr [5]
  706. NULL
  707. };
  708. const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
  709. &MAC_EXT[6], // Factory MAC addr [6]
  710. &MAC_EXT[7], // Factory MAC addr [7]
  711. NULL
  712. };
  713. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
  714. &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
  715. NULL
  716. };
  717. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
  718. &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
  719. NULL
  720. };
  721. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
  722. &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
  723. NULL
  724. };
  725. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
  726. &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
  727. NULL
  728. };
  729. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
  730. &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
  731. NULL
  732. };
  733. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
  734. &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
  735. NULL
  736. };
  737. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
  738. &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
  739. NULL
  740. };
  741. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
  742. &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
  743. NULL
  744. };
  745. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
  746. &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
  747. NULL
  748. };
  749. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
  750. &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
  751. NULL
  752. };
  753. const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
  754. &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
  755. NULL
  756. };
  757. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
  758. &WAFER_VERSION[0], // WAFER version
  759. NULL
  760. };
  761. const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
  762. &PKG_VERSION[0], // Package version 0:ESP32H2
  763. NULL
  764. };
  765. const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
  766. &BLOCK1_VERSION[0], // BLOCK1 efuse version
  767. NULL
  768. };
  769. const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
  770. &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
  771. NULL
  772. };
  773. const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
  774. &BLOCK2_VERSION[0], // Version of BLOCK2
  775. NULL
  776. };
  777. const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
  778. &TEMP_CALIB[0], // Temperature calibration data
  779. NULL
  780. };
  781. const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
  782. &OCODE[0], // ADC OCode
  783. NULL
  784. };
  785. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
  786. &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0
  787. NULL
  788. };
  789. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
  790. &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1
  791. NULL
  792. };
  793. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
  794. &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2
  795. NULL
  796. };
  797. const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
  798. &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3
  799. NULL
  800. };
  801. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
  802. &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0
  803. NULL
  804. };
  805. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
  806. &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1
  807. NULL
  808. };
  809. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
  810. &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2
  811. NULL
  812. };
  813. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
  814. &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3
  815. NULL
  816. };
  817. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
  818. &USER_DATA[0], // User data
  819. NULL
  820. };
  821. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
  822. &USER_DATA_MAC_CUSTOM[0], // Custom MAC
  823. NULL
  824. };
  825. const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
  826. &KEY0[0], // Key0 or user data
  827. NULL
  828. };
  829. const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
  830. &KEY1[0], // Key1 or user data
  831. NULL
  832. };
  833. const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
  834. &KEY2[0], // Key2 or user data
  835. NULL
  836. };
  837. const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
  838. &KEY3[0], // Key3 or user data
  839. NULL
  840. };
  841. const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
  842. &KEY4[0], // Key4 or user data
  843. NULL
  844. };
  845. const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
  846. &KEY5[0], // Key5 or user data
  847. NULL
  848. };
  849. const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
  850. &SYS_DATA_PART2[0], // System configuration
  851. NULL
  852. };