cache_utils.h 2.8 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #ifndef ESP_SPI_FLASH_CACHE_UTILS_H
  15. #define ESP_SPI_FLASH_CACHE_UTILS_H
  16. #include "sdkconfig.h"
  17. #include <stdbool.h>
  18. /**
  19. * This header file contains declarations of cache manipulation functions
  20. * used both in flash_ops.c and flash_mmap.c.
  21. *
  22. * These functions are considered internal and are not designed to be called from applications.
  23. */
  24. // Init mutex protecting access to spi_flash_* APIs
  25. void spi_flash_init_lock(void);
  26. // Take mutex protecting access to spi_flash_* APIs
  27. void spi_flash_op_lock(void);
  28. // Release said mutex
  29. void spi_flash_op_unlock(void);
  30. // Suspend the scheduler on both CPUs, disable cache.
  31. // Contrary to its name this doesn't do anything with interrupts, yet.
  32. // Interrupt disabling capability will be added once we implement
  33. // interrupt allocation API.
  34. void spi_flash_disable_interrupts_caches_and_other_cpu(void);
  35. // Enable cache, enable interrupts (to be added in future), resume scheduler
  36. void spi_flash_enable_interrupts_caches_and_other_cpu(void);
  37. // Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
  38. // This function is implied to be called when other CPU is not running or running code from IRAM.
  39. void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void);
  40. // Enable cache, enable interrupts on current CPU.
  41. // This function is implied to be called when other CPU is not running or running code from IRAM.
  42. void spi_flash_enable_interrupts_caches_no_os(void);
  43. // Mark the pages containing a flash region as having been
  44. // erased or written to. This means the flash cache needs
  45. // to be evicted before these pages can be flash_mmap()ed again,
  46. // as they may contain stale data
  47. //
  48. // Only call this while holding spi_flash_op_lock()
  49. // Returns true if cache was flushed, false otherwise
  50. bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length);
  51. //config cache mode
  52. #if !CONFIG_IDF_TARGET_ESP32
  53. //config instrcutin cache size and cache block size by menuconfig
  54. void esp_config_instruction_cache_mode(void);
  55. //config data cache size and cache block size by menuconfig
  56. void esp_config_data_cache_mode(void);
  57. //enable cache wrap mode for instruction cache and data cache
  58. esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable);
  59. #endif
  60. #endif //ESP_SPI_FLASH_CACHE_UTILS_H