esp_flash_spi_init.c 11 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "sdkconfig.h"
  7. #include "esp_flash.h"
  8. #include "memspi_host_driver.h"
  9. #include "esp_flash_spi_init.h"
  10. #include "driver/gpio.h"
  11. #include "esp_rom_gpio.h"
  12. #include "esp_rom_efuse.h"
  13. #include "esp_log.h"
  14. #include "esp_heap_caps.h"
  15. #include "hal/spi_types.h"
  16. #include "driver/spi_common_internal.h"
  17. #include "hal/spi_flash_hal.h"
  18. #include "hal/gpio_hal.h"
  19. #include "esp_flash_internal.h"
  20. #include "esp_rom_gpio.h"
  21. #include "esp_private/spi_flash_os.h"
  22. #if CONFIG_IDF_TARGET_ESP32
  23. #include "esp32/rom/spi_flash.h"
  24. #elif CONFIG_IDF_TARGET_ESP32S2
  25. #include "esp32s2/rom/spi_flash.h"
  26. #elif CONFIG_IDF_TARGET_ESP32S3
  27. #include "esp32s3/rom/spi_flash.h"
  28. #elif CONFIG_IDF_TARGET_ESP32C3
  29. #include "esp32c3/rom/spi_flash.h"
  30. #elif CONFIG_IDF_TARGET_ESP32H2
  31. #include "esp32h2/rom/spi_flash.h"
  32. #endif
  33. __attribute__((unused)) static const char TAG[] = "spi_flash";
  34. /* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
  35. #if !CONFIG_SPI_FLASH_ROM_IMPL
  36. esp_flash_t *esp_flash_default_chip = NULL;
  37. #endif
  38. #ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
  39. #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
  40. #define DEFAULT_FLASH_SPEED ESP_FLASH_80MHZ
  41. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
  42. #define DEFAULT_FLASH_SPEED ESP_FLASH_40MHZ
  43. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
  44. #define DEFAULT_FLASH_SPEED ESP_FLASH_26MHZ
  45. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
  46. #define DEFAULT_FLASH_SPEED ESP_FLASH_20MHZ
  47. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_120M
  48. #define DEFAULT_FLASH_SPEED ESP_FLASH_120MHZ
  49. #else
  50. #error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
  51. #endif
  52. #if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
  53. #define DEFAULT_FLASH_MODE SPI_FLASH_QIO
  54. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
  55. #define DEFAULT_FLASH_MODE SPI_FLASH_QOUT
  56. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
  57. #define DEFAULT_FLASH_MODE SPI_FLASH_DIO
  58. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
  59. #define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
  60. #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR)
  61. #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_STR
  62. #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR)
  63. #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_DTR
  64. #else
  65. #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
  66. #endif
  67. //TODO: modify cs hold to meet requirements of all chips!!!
  68. #if CONFIG_IDF_TARGET_ESP32
  69. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  70. .host_id = SPI1_HOST,\
  71. .speed = DEFAULT_FLASH_SPEED, \
  72. .cs_num = 0, \
  73. .iomux = false, \
  74. .input_delay_ns = 0,\
  75. .cs_setup = 1,\
  76. }
  77. #elif CONFIG_IDF_TARGET_ESP32S2
  78. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  79. .host_id = SPI1_HOST,\
  80. .speed = DEFAULT_FLASH_SPEED, \
  81. .cs_num = 0, \
  82. .iomux = true, \
  83. .input_delay_ns = 0,\
  84. .cs_setup = 1,\
  85. }
  86. #elif CONFIG_IDF_TARGET_ESP32S3
  87. #include "esp32s3/rom/efuse.h"
  88. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  89. .host_id = SPI1_HOST,\
  90. .speed = DEFAULT_FLASH_SPEED, \
  91. .cs_num = 0, \
  92. .iomux = true, \
  93. .input_delay_ns = 0,\
  94. .cs_setup = 1,\
  95. }
  96. #elif CONFIG_IDF_TARGET_ESP32C3
  97. #include "esp32c3/rom/efuse.h"
  98. #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
  99. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  100. .host_id = SPI1_HOST,\
  101. .speed = DEFAULT_FLASH_SPEED, \
  102. .cs_num = 0, \
  103. .iomux = true, \
  104. .input_delay_ns = 0,\
  105. .cs_setup = 1,\
  106. }
  107. #else
  108. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  109. .host_id = SPI1_HOST,\
  110. .speed = DEFAULT_FLASH_SPEED, \
  111. .cs_num = 0, \
  112. .iomux = true, \
  113. .input_delay_ns = 0,\
  114. .auto_sus_en = true,\
  115. .cs_setup = 1,\
  116. }
  117. #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
  118. #elif CONFIG_IDF_TARGET_ESP32H2
  119. #include "esp32h2/rom/efuse.h"
  120. #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
  121. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  122. .host_id = SPI1_HOST,\
  123. .speed = DEFAULT_FLASH_SPEED, \
  124. .cs_num = 0, \
  125. .iomux = true, \
  126. .input_delay_ns = 0,\
  127. }
  128. #else
  129. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  130. .host_id = SPI1_HOST,\
  131. .speed = DEFAULT_FLASH_SPEED, \
  132. .cs_num = 0, \
  133. .iomux = true, \
  134. .input_delay_ns = 0,\
  135. .auto_sus_en = true,\
  136. }
  137. #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
  138. #endif
  139. static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id)
  140. {
  141. //Not using spicommon_cs_initialize since we don't want to put the whole
  142. //spi_periph_signal into the DRAM. Copy these data from flash before the
  143. //cache disabling
  144. int cs_io_num = config->cs_io_num;
  145. int spics_in = spi_periph_signal[config->host_id].spics_in;
  146. int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
  147. int spics_func = spi_periph_signal[config->host_id].func;
  148. uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
  149. //To avoid the panic caused by flash data line conflicts during cs line
  150. //initialization, disable the cache temporarily
  151. chip->os_func->start(chip->os_func_data);
  152. PIN_INPUT_ENABLE(iomux_reg);
  153. if (use_iomux) {
  154. gpio_hal_iomux_func_sel(iomux_reg, spics_func);
  155. } else {
  156. #if SOC_GPIO_PIN_COUNT <= 32
  157. GPIO.enable_w1ts.val = (0x1 << cs_io_num);
  158. #else
  159. if (cs_io_num < 32) {
  160. GPIO.enable_w1ts = (0x1 << cs_io_num);
  161. } else {
  162. GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
  163. }
  164. #endif
  165. GPIO.pin[cs_io_num].pad_driver = 0;
  166. esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
  167. if (cs_id == 0) {
  168. esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
  169. }
  170. gpio_hal_iomux_func_sel(iomux_reg, PIN_FUNC_GPIO);
  171. }
  172. chip->os_func->end(chip->os_func_data);
  173. }
  174. esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
  175. {
  176. if (out_chip == NULL) {
  177. return ESP_ERR_INVALID_ARG;
  178. }
  179. if (!GPIO_IS_VALID_OUTPUT_GPIO(config->cs_io_num)) {
  180. return ESP_ERR_INVALID_ARG;
  181. }
  182. esp_flash_t *chip = NULL;
  183. memspi_host_inst_t *host = NULL;
  184. esp_err_t ret = ESP_OK;
  185. uint32_t caps = MALLOC_CAP_DEFAULT;
  186. if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
  187. chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
  188. if (!chip) {
  189. ret = ESP_ERR_NO_MEM;
  190. goto fail;
  191. }
  192. host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
  193. *chip = (esp_flash_t) {
  194. .read_mode = config->io_mode,
  195. .host = (spi_flash_host_inst_t*)host,
  196. };
  197. if (!host) {
  198. ret = ESP_ERR_NO_MEM;
  199. goto fail;
  200. }
  201. int dev_id = -1;
  202. esp_err_t err = esp_flash_init_os_functions(chip, config->host_id, &dev_id);
  203. if (err == ESP_ERR_NOT_SUPPORTED) {
  204. ESP_LOGE(TAG, "Init os functions failed! No free CS.");
  205. } else if (err == ESP_ERR_INVALID_ARG) {
  206. ESP_LOGE(TAG, "Init os functions failed! Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
  207. }
  208. if (err != ESP_OK) {
  209. ret = err;
  210. goto fail;
  211. }
  212. // When `CONFIG_SPI_FLASH_SHARE_SPI1_BUS` is not enabled on SPI1 bus, the
  213. // `esp_flash_init_os_functions` will not be able to assign a new device ID. In this case, we
  214. // use the `cs_id` in the config structure.
  215. if (dev_id == -1 && config->host_id == SPI1_HOST) {
  216. dev_id = config->cs_id;
  217. }
  218. assert(dev_id < SOC_SPI_PERIPH_CS_NUM(config->host_id) && dev_id >= 0);
  219. bool use_iomux = spicommon_bus_using_iomux(config->host_id);
  220. memspi_host_config_t host_cfg = {
  221. .host_id = config->host_id,
  222. .cs_num = dev_id,
  223. .iomux = use_iomux,
  224. .input_delay_ns = config->input_delay_ns,
  225. .speed = config->speed,
  226. };
  227. err = memspi_host_init_pointers(host, &host_cfg);
  228. if (err != ESP_OK) {
  229. ret = err;
  230. goto fail;
  231. }
  232. // The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
  233. cs_initialize(chip, config, use_iomux, dev_id);
  234. *out_chip = chip;
  235. return ret;
  236. fail:
  237. // The memory allocated are free'd in the `spi_bus_remove_flash_device`.
  238. spi_bus_remove_flash_device(chip);
  239. return ret;
  240. }
  241. esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
  242. {
  243. if (chip==NULL) {
  244. return ESP_ERR_INVALID_ARG;
  245. }
  246. esp_flash_deinit_os_functions(chip);
  247. free(chip->host);
  248. free(chip);
  249. return ESP_OK;
  250. }
  251. /* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
  252. extern const esp_flash_os_functions_t esp_flash_noos_functions;
  253. static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
  254. static DRAM_ATTR esp_flash_t default_chip = {
  255. .read_mode = DEFAULT_FLASH_MODE,
  256. .host = (spi_flash_host_inst_t*)&esp_flash_default_host,
  257. .os_func = &esp_flash_noos_functions,
  258. };
  259. extern esp_err_t esp_flash_suspend_cmd_init(esp_flash_t* chip);
  260. esp_err_t esp_flash_init_default_chip(void)
  261. {
  262. const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
  263. memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
  264. #if !CONFIG_IDF_TARGET_ESP32
  265. // For esp32s2 spi IOs are configured as from IO MUX by default
  266. cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
  267. #endif
  268. #if CONFIG_ESPTOOLPY_OCT_FLASH
  269. cfg.octal_mode_en = 1;
  270. cfg.default_io_mode = DEFAULT_FLASH_MODE;
  271. #endif
  272. // For chips need time tuning, get value directely from system here.
  273. #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
  274. if (spi_timing_is_tuned()) {
  275. cfg.using_timing_tuning = 1;
  276. spi_timing_get_flash_timing_param(&cfg.timing_reg);
  277. }
  278. #endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
  279. //the host is already initialized, only do init for the data and load it to the host
  280. esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
  281. if (err != ESP_OK) {
  282. return err;
  283. }
  284. // ROM TODO: account for non-standard default pins in efuse
  285. // ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
  286. err = esp_flash_init_main(&default_chip);
  287. if (err != ESP_OK) {
  288. return err;
  289. }
  290. if (default_chip.size < legacy_chip->chip_size) {
  291. ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, legacy_chip->chip_size/1024);
  292. return ESP_ERR_FLASH_SIZE_NOT_MATCH;
  293. }
  294. if (default_chip.size > legacy_chip->chip_size) {
  295. ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, legacy_chip->chip_size/1024);
  296. }
  297. default_chip.size = legacy_chip->chip_size;
  298. esp_flash_default_chip = &default_chip;
  299. #ifdef CONFIG_SPI_FLASH_AUTO_SUSPEND
  300. err = esp_flash_suspend_cmd_init(&default_chip);
  301. if (err != ESP_OK) {
  302. return err;
  303. }
  304. #endif
  305. return ESP_OK;
  306. }
  307. esp_err_t esp_flash_app_init(void)
  308. {
  309. esp_err_t err = ESP_OK;
  310. #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
  311. err = esp_flash_init_main_bus_lock();
  312. if (err != ESP_OK) return err;
  313. #endif
  314. err = esp_flash_app_enable_os_functions(&default_chip);
  315. return err;
  316. }
  317. #endif //!CONFIG_SPI_FLASH_USE_LEGACY_IMPL