test_ulp_riscv.c 3.1 KB

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  1. // Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include <stdio.h>
  15. #include <string.h>
  16. #include "esp_sleep.h"
  17. #include "soc/rtc_cntl_reg.h"
  18. #include "soc/sens_reg.h"
  19. #include "soc/rtc_periph.h"
  20. #include "esp32s2/ulp.h"
  21. #include "esp32s2/ulp_riscv.h"
  22. #include "ulp_test_app.h"
  23. #include "unity.h"
  24. typedef enum{
  25. RISCV_READ_WRITE_TEST = 1,
  26. RISCV_DEEP_SLEEP_WAKEUP_TEST,
  27. RISCV_LIGHT_SLEEP_WAKEUP_TEST,
  28. RISCV_NO_COMMAND,
  29. } riscv_test_commands_t;
  30. typedef enum {
  31. RISCV_COMMAND_OK = 1,
  32. RISCV_COMMAND_NOK,
  33. } riscv_test_command_reply_t;
  34. #define XOR_MASK 0xDEADBEEF
  35. extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start");
  36. extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_test_app_bin_end");
  37. static bool firmware_loaded = false;
  38. static void load_and_start_ulp_firmware(void)
  39. {
  40. if (!firmware_loaded) {
  41. TEST_ASSERT(ulp_riscv_load_binary(ulp_main_bin_start,
  42. (ulp_main_bin_end - ulp_main_bin_start)) == ESP_OK);
  43. TEST_ASSERT(ulp_set_wakeup_period(0, 1000000) == ESP_OK);
  44. TEST_ASSERT(ulp_riscv_run() == ESP_OK);
  45. firmware_loaded = true;
  46. }
  47. }
  48. TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp][ignore]")
  49. {
  50. const uint32_t test_data = 0x12345678;
  51. load_and_start_ulp_firmware();
  52. TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
  53. ulp_riscv_test_data_in = test_data ^ XOR_MASK;
  54. ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
  55. TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
  56. TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
  57. TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
  58. printf("data out: 0x%X, expected: 0x%X \n", ulp_riscv_test_data_out, test_data);
  59. TEST_ASSERT(test_data == ulp_riscv_test_data_out);
  60. }
  61. TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp][ignore]")
  62. {
  63. load_and_start_ulp_firmware();
  64. TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
  65. ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
  66. TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
  67. TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
  68. TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
  69. }
  70. TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=SW_CPU_RESET][ignore]")
  71. {
  72. load_and_start_ulp_firmware();
  73. TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
  74. ulp_main_cpu_command = RISCV_DEEP_SLEEP_WAKEUP_TEST;
  75. esp_deep_sleep_start();
  76. UNITY_TEST_FAIL(__LINE__, "Should not get here!");
  77. }