wdt.c 3.4 KB

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  1. /* Copyright 2018 Canaan Inc.
  2. *
  3. * Licensed under the Apache License, Version 2.0 (the "License");
  4. * you may not use this file except in compliance with the License.
  5. * You may obtain a copy of the License at
  6. *
  7. * http://www.apache.org/licenses/LICENSE-2.0
  8. *
  9. * Unless required by applicable law or agreed to in writing, software
  10. * distributed under the License is distributed on an "AS IS" BASIS,
  11. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. * See the License for the specific language governing permissions and
  13. * limitations under the License.
  14. */
  15. #include "math.h"
  16. #include "platform.h"
  17. #include "plic.h"
  18. #include "stddef.h"
  19. #include "sysctl.h"
  20. #include "utils.h"
  21. #include "wdt.h"
  22. volatile wdt_t *const wdt[2] =
  23. {
  24. (volatile wdt_t *)WDT0_BASE_ADDR,
  25. (volatile wdt_t *)WDT1_BASE_ADDR};
  26. static void wdt_enable(wdt_device_number_t id)
  27. {
  28. wdt[id]->crr = WDT_CRR_MASK;
  29. wdt[id]->cr |= WDT_CR_ENABLE;
  30. }
  31. static void wdt_disable(wdt_device_number_t id)
  32. {
  33. wdt[id]->crr = WDT_CRR_MASK;
  34. wdt[id]->cr &= (~WDT_CR_ENABLE);
  35. }
  36. static void wdt_set_timeout(wdt_device_number_t id, uint8_t timeout)
  37. {
  38. wdt[id]->torr = WDT_TORR_TOP(timeout);
  39. }
  40. static void wdt_response_mode(wdt_device_number_t id, uint8_t mode)
  41. {
  42. wdt[id]->cr &= (~WDT_CR_RMOD_MASK);
  43. wdt[id]->cr |= mode;
  44. }
  45. static uint64_t wdt_get_pclk(wdt_device_number_t id)
  46. {
  47. return id ? sysctl_clock_get_freq(SYSCTL_CLOCK_WDT1) : sysctl_clock_get_freq(SYSCTL_CLOCK_WDT0);
  48. }
  49. static uint8_t wdt_get_top(wdt_device_number_t id, uint64_t timeout_ms)
  50. {
  51. uint64_t wdt_clk = wdt_get_pclk(id);
  52. uint64_t ret = (timeout_ms * wdt_clk / 1000) >> 16;
  53. if(ret)
  54. ret = (uint32_t)log2(ret);
  55. if(ret > 0xf)
  56. ret = 0xf;
  57. return (uint8_t)ret;
  58. }
  59. void wdt_feed(wdt_device_number_t id)
  60. {
  61. wdt[id]->crr = WDT_CRR_MASK;
  62. }
  63. void wdt_clear_interrupt(wdt_device_number_t id)
  64. {
  65. wdt[id]->eoi = wdt[id]->eoi;
  66. }
  67. void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq)
  68. {
  69. sysctl_reset(id ? SYSCTL_RESET_WDT1 : SYSCTL_RESET_WDT0);
  70. sysctl_clock_set_threshold(id ? SYSCTL_THRESHOLD_WDT1 : SYSCTL_THRESHOLD_WDT0, 0);
  71. sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0);
  72. plic_set_priority(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, 1);
  73. plic_irq_enable(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT);
  74. plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, on_irq, NULL);
  75. wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT);
  76. uint8_t m_top = wdt_get_top(id, time_out_ms);
  77. wdt_set_timeout(id, m_top);
  78. wdt_enable(id);
  79. }
  80. uint32_t wdt_init(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq, void *ctx)
  81. {
  82. sysctl_reset(id ? SYSCTL_RESET_WDT1 : SYSCTL_RESET_WDT0);
  83. sysctl_clock_set_threshold(id ? SYSCTL_THRESHOLD_WDT1 : SYSCTL_THRESHOLD_WDT0, 0);
  84. sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0);
  85. plic_set_priority(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, 1);
  86. plic_irq_enable(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT);
  87. plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, on_irq, ctx);
  88. wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT);
  89. uint8_t m_top = wdt_get_top(id, time_out_ms);
  90. wdt_set_timeout(id, m_top);
  91. wdt_enable(id);
  92. return (1UL << (m_top + 16 + 1)) * 1000UL / wdt_get_pclk(id);
  93. }
  94. void wdt_stop(wdt_device_number_t id)
  95. {
  96. wdt_disable(id);
  97. }