同步上游到 21d59b8b40c2 , 添加 RT-Thread UART 对接 HCI 层 (#19)

* 同步到上游 21d59b8b40c2 tag-v1.5，调整文件

* 完成 rt-thread uart 到 HCI 层的对接，修改编译描述文件

* 对接rtdbg日志; debug 部分例程; menuconfig 配置 HCI uart 设备

* 调整文件, 增加 firmwares 及 同步上游代码说明文档

.rat-excludes

@@ -16,6 +16,7 @@ pts-sm.txt
 94654-20170317-085441153.pts
 uncrustify.cfg
 .style_ignored_dirs
+.mailmap
 
 # tinycrypt - BSD License.
 tinycrypt
@@ -31,3 +32,6 @@ os_mbuf.c
 
 # Bluetooth Mesh badge sample - Apache 2.0 License
 mesh_badge
+
+#BabbleSim and EDDT - Apache 2.0 License
+babblesim

.travis.yml

@@ -26,6 +26,7 @@ _addons: &addon_conf
     packages:
       - gcc-multilib
       - gcc-7-multilib
+      - g++-multilib
 
 go:
   - "1.16"
@@ -34,6 +35,11 @@ git:
   depth: false
 
 matrix:
+  allow_failures:
+    - env:
+        - TEST=BUILD_PORTS
+        - VM_AMOUNT=1
+        - TARGET_SET=1
   include:
     # Style checking
     - os: linux
@@ -96,25 +102,6 @@ matrix:
         - VM_AMOUNT=1
         - TARGET_SET=1
 
-    # newt test all
-    - os: osx
-      osx_image: xcode9.2
-      env:
-        - TEST=TEST_ALL
-        - VM_AMOUNT=3
-        - TARGET_SET=1
-    - os: osx
-      osx_image: xcode9.2
-      env:
-        - TEST=TEST_ALL
-        - VM_AMOUNT=3
-        - TARGET_SET=2
-    - os: osx
-      osx_image: xcode9.2
-      env:
-        - TEST=TEST_ALL
-        - VM_AMOUNT=3
-        - TARGET_SET=3
     - os: windows
       env:
         - TEST=BUILD_TARGETS_WINDOWS

NOTICE

@@ -1,5 +1,5 @@
 Apache Mynewt NimBLE
-Copyright 2015-2021 The Apache Software Foundation
+Copyright 2015-2022 The Apache Software Foundation
 
 This product includes software developed at
 The Apache Software Foundation (http://www.apache.org/).

RELEASE_NOTES.md

@@ -1,21 +1,24 @@
 # RELEASE NOTES
 
-24 March 2021 - Apache NimBLE v1.4.0
+20 April 2022 - Apache NimBLE v1.5.0
 
 For full release notes, please visit the
 [Apache Mynewt Wiki](https://cwiki.apache.org/confluence/display/MYNEWT/Release+Notes).
 
-Apache NimBLE is an open-source Bluetooth 5.1 stack (both Host & Controller) that completely
+Apache NimBLE is an open-source Bluetooth 5.3 stack (both Host & Controller) that completely
 replaces the proprietary SoftDevice on Nordic chipsets.
 
 New features in this version of NimBLE include:
 
-* Support for PHY on Dialog Configurable MAC (CMAC)
-* Support for PHY on Nordic nRF5340
-* Support for Apache NuttX port of NimBLE
-* Controller-to-host flow control support
-* Support for USB transport
-* Various bugfixes
+* Fake dual-mode option for controller
+* LLCP tracing via HCI events
+* Code size optimization for disabled GAP roles
+* Support for PA/LNA
+* LE Secure Connections Only mode
+* Support for Bluetooth Core Specification 5.3
+* Connection subrating
+* BabbleSim support
+* Various bugfixes and improvements
 
 If working on next-generation RTOS and Bluetooth protocol stack
 sounds exciting to you, get in touch, by sending a mail to the Apache Mynewt

SConscript

@@ -19,8 +19,10 @@ path += [
     cwd + '/nimble/host/services/tps/include',
     cwd + '/nimble/host/store/ram/include',
     cwd + '/nimble/host/util/include',
-    cwd + '/porting/nimble/include',
-    cwd + '/porting/npl/rtthread/include']
+    cwd + '/nimble/transport/include',
+    cwd + '/nimble/transport/common/hci_h4/include',
+    cwd + '/porting/npl/rtthread/include',
+    cwd + '/porting/nimble/include']
 
 # Host stack
 src += Split('''
@@ -57,7 +59,6 @@ src += Split('''
     nimble/host/src/ble_l2cap_coc.c
     nimble/host/src/ble_l2cap_sig.c
     nimble/host/src/ble_l2cap_sig_cmd.c
-    nimble/host/src/ble_monitor.c
     nimble/host/src/ble_sm_alg.c
     nimble/host/src/ble_sm.c
     nimble/host/src/ble_sm_cmd.c
@@ -77,6 +78,62 @@ src += Split('''
     nimble/host/util/src/addr.c
     ''')
 
+# HCI transport
+src += Split('''
+    nimble/transport/src/monitor.c
+    nimble/transport/src/transport.c
+    nimble/transport/common/hci_h4/src/hci_h4.c
+    ''')
+
+if GetDepend(['PKG_NIMBLE_HCI_USING_RTT_UART']):
+    src += Split("""
+        nimble/transport/rtthread/src/ble_hci_rtthread_uart.c
+    """)
+
+# mesh
+if GetDepend(['PKG_NIMBLE_MESH']):
+    path += [cwd + '/nimble/host/mesh/include']
+
+    src += Split('''
+        nimble/host/mesh/src/access.c
+        nimble/host/mesh/src/adv_ext.c
+        nimble/host/mesh/src/adv_legacy.c
+        nimble/host/mesh/src/adv.c
+        nimble/host/mesh/src/aes-ccm.c
+        nimble/host/mesh/src/app_keys.c
+        nimble/host/mesh/src/beacon.c
+        nimble/host/mesh/src/cdb.c
+        nimble/host/mesh/src/cfg_cli.c
+        nimble/host/mesh/src/cfg_srv.c
+        nimble/host/mesh/src/cfg.c
+        nimble/host/mesh/src/crypto.c
+        nimble/host/mesh/src/friend.c
+        nimble/host/mesh/src/glue.c
+        nimble/host/mesh/src/health_cli.c
+        nimble/host/mesh/src/health_srv.c
+        nimble/host/mesh/src/heartbeat.c
+        nimble/host/mesh/src/light_model.c
+        nimble/host/mesh/src/lpn.c
+        nimble/host/mesh/src/mesh.c
+        nimble/host/mesh/src/model_cli.c
+        nimble/host/mesh/src/model_srv.c
+        nimble/host/mesh/src/msg.c
+        nimble/host/mesh/src/net.c
+        nimble/host/mesh/src/pb_adv.c
+        nimble/host/mesh/src/pb_gatt_srv.c
+        nimble/host/mesh/src/pb_gatt.c
+        nimble/host/mesh/src/prov_device.c
+        nimble/host/mesh/src/prov.c
+        nimble/host/mesh/src/provisioner.c
+        nimble/host/mesh/src/proxy_msg.c
+        nimble/host/mesh/src/proxy_srv.c
+        nimble/host/mesh/src/rpl.c
+        nimble/host/mesh/src/settings.c
+        nimble/host/mesh/src/shell.c
+        nimble/host/mesh/src/subnet.c
+        nimble/host/mesh/src/transport.c
+    ''')
+
 # Few utils and data structures copied from Mynewt
 src += Split('''
     porting/nimble/src/nimble_port.c''')
@@ -112,9 +169,7 @@ else:
     CPPDEFINES = ['']
 
 if GetDepend(['PKG_NIMBLE_CTLR']):
-    path += [
-        cwd + '/nimble/transport/ram/include',
-        cwd + '/nimble/controller/include']
+    path += [cwd + '/nimble/controller/include']
         
 
     if GetDepend(['PKG_NIMBLE_BSP_NRF51']):
@@ -131,7 +186,6 @@ if GetDepend(['PKG_NIMBLE_CTLR']):
             """)
 
     src += Split("""
-        nimble/transport/ram/src/ble_hci_ram.c
         nimble/controller/src/ble_ll_sched.c
         nimble/controller/src/ble_ll_whitelist.c
         nimble/controller/src/ble_ll_ctrl.c
@@ -146,6 +200,7 @@ if GetDepend(['PKG_NIMBLE_CTLR']):
         nimble/controller/src/ble_ll_scan.c
         nimble/controller/src/ble_ll_dtm.c
         nimble/controller/src/ble_ll_hci_ev.c
+        nimble/controller/src/ble_ll_hci_vs.c
         nimble/controller/src/ble_ll_iso.c
         nimble/controller/src/ble_ll_rfmgmt.c
         nimble/controller/src/ble_ll_scan_aux.c
@@ -157,6 +212,12 @@ if GetDepend(['PKG_NIMBLE_CTLR']):
         porting/npl/rtthread/src/nrf5x_isr.c
         """)
 
+# advertiser sample
+if GetDepend(['PKG_NIMBLE_SAMPLE_ADVERTISER']):
+    src += Split("""
+        apps/advertiser/src/advertiser.c
+    """)
+
 # central sample
 if GetDepend(['PKG_NIMBLE_SAMPLE_CENTRAL']):
     path += [cwd + '/apps/blecent/src']
@@ -240,7 +301,7 @@ if GetDepend(['PKG_NIMBLE_SAMPLE_EXT_ADVERTISER']):
 if GetDepend(['PKG_NIMBLE_SAMPLE_BEACON']):
     src += Glob('apps/ibeacon/src/ibeacon.c')
 
-LOCAL_CCFLAGS = ''
+LOCAL_CCFLAGS = '-Wno-format -Wno-unused-variable -Wno-unused-but-set-variable'
 
 if rtconfig.CROSS_TOOL == 'keil':
     LOCAL_CCFLAGS += ' --gnu --diag_suppress=111'

apps/advertiser/pkg.yml

@@ -0,0 +1,33 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: "apps/advertiser"
+pkg.type: app
+pkg.description: "Basic advertiser application"
+pkg.author: "Krzysztof Kopyściński <krzysztof.kopyscinski@codecoup.pl>"
+
+pkg.deps:
+    - "@apache-mynewt-core/kernel/os"
+    - "@apache-mynewt-core/sys/console/full"
+    - "@apache-mynewt-core/sys/log/full"
+    - "@apache-mynewt-core/sys/stats/full"
+    - "@apache-mynewt-core/sys/log/modlog"
+    - "@apache-mynewt-nimble/nimble/host"
+    - "@apache-mynewt-nimble/nimble/host/util"
+    - "@apache-mynewt-nimble/nimble/host/services/gap"

apps/advertiser/src/advertiser.c

@@ -0,0 +1,131 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "os/os.h"
+#include "sysinit/sysinit.h"
+#include "log/log.h"
+#include "host/ble_hs.h"
+#include "host/util/util.h"
+#include "services/gap/ble_svc_gap.h"
+
+static const char *device_name = "Apache Mynewt";
+
+/* adv_event() calls advertise(), so forward declaration is required */
+static void advertise(void);
+
+static void
+set_ble_addr(void)
+{
+    int rc;
+    ble_addr_t addr;
+
+    /* generate new non-resolvable private address */
+    rc = ble_hs_id_gen_rnd(1, &addr);
+    assert(rc == 0);
+
+    /* set generated address */
+    rc = ble_hs_id_set_rnd(addr.val);
+    assert(rc == 0);
+}
+
+static int
+adv_event(struct ble_gap_event *event, void *arg)
+{
+    switch (event->type) {
+    case BLE_GAP_EVENT_ADV_COMPLETE:
+        MODLOG_DFLT(INFO, "Advertising completed, termination code: %d\n",
+                    event->adv_complete.reason);
+        advertise();
+        return 0;
+    default:
+        MODLOG_DFLT(ERROR, "Advertising event not handled\n");
+        return 0;
+    }
+}
+
+static void
+advertise(void)
+{
+    int rc;
+    struct ble_gap_adv_params adv_params;
+    struct ble_hs_adv_fields fields;
+
+    /* set adv parameters */
+    memset(&adv_params, 0, sizeof(adv_params));
+    adv_params.conn_mode = BLE_GAP_CONN_MODE_NON;
+    adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
+
+    memset(&fields, 0, sizeof(fields));
+
+    /* Fill the fields with advertising data - flags, tx power level, name */
+    fields.flags = BLE_HS_ADV_F_DISC_GEN;
+    fields.tx_pwr_lvl_is_present = 1;
+    fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO;
+    fields.name = (uint8_t *)device_name;
+    fields.name_len = strlen(device_name);
+    fields.name_is_complete = 1;
+
+    rc = ble_gap_adv_set_fields(&fields);
+    assert(rc == 0);
+
+    MODLOG_DFLT(INFO, "Starting advertising...\n");
+
+    /* As own address type we use hard-coded value, because we generate
+       NRPA and by definition it's random */
+    rc = ble_gap_adv_start(BLE_OWN_ADDR_RANDOM, NULL, 10000,
+                           &adv_params, adv_event, NULL);
+    assert(rc == 0);
+}
+
+static void
+on_sync(void)
+{
+    set_ble_addr();
+
+    /* begin advertising */
+    advertise();
+}
+
+static void
+on_reset(int reason)
+{
+    MODLOG_DFLT(INFO, "Resetting state; reason=%d\n", reason);
+}
+
+static int ble_adv()
+{
+    int rc;
+
+    ble_hs_cfg.sync_cb = on_sync;
+    ble_hs_cfg.reset_cb = on_reset;
+
+    rc = ble_svc_gap_device_name_set(device_name);
+    assert(rc == 0);
+
+    /* startup bluetooth host stack*/
+    ble_hs_thread_startup();
+
+    return 0;
+}
+MSH_CMD_EXPORT_ALIAS(ble_adv, ble_adv, "bluetoooth advertise sample");

apps/advertiser/syscfg.yml

@@ -0,0 +1,23 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+
+syscfg.vals:
+    BLE_ROLE_BROADCASTER: 1
+    BLE_ROLE_CENTRAL: 0
+    BLE_ROLE_OBSERVER: 0
+    BLE_ROLE_PERIPHERAL: 0

apps/blecent/pkg.yml

@@ -28,10 +28,8 @@ pkg.deps:
     - "@apache-mynewt-core/sys/log/full"
     - "@apache-mynewt-core/sys/log/modlog"
     - "@apache-mynewt-core/sys/stats/full"
-    - nimble/controller
     - nimble/host
     - nimble/host/util
     - nimble/host/services/gap
     - nimble/host/services/gatt
-    - nimble/host/store/ram
-    - nimble/transport/ram
+    - nimble/host/store/config

apps/blecent/src/blecent.c

@@ -27,9 +27,6 @@
 #include "host/ble_hs.h"
 #include "host/util/util.h"
 
-/* HCI transport. */
-#include "nimble/ble_hci_trans.h"
-
 /* Mandatory services. */
 #include "services/gap/ble_svc_gap.h"
 #include "services/gatt/ble_svc_gatt.h"

apps/blecent/src/peer.c

@@ -21,6 +21,7 @@
 #include <string.h>
 #include "host/ble_hs.h"
 #include "blecent.h"
+#include <stdlib.h>
 
 static void *peer_svc_mem;
 static struct os_mempool peer_svc_pool;

apps/blecsc/src/blecsc_sens.c

@@ -29,6 +29,7 @@
 #include "host/ble_hs.h"
 #include "services/gap/ble_svc_gap.h"
 #include "blecsc_sens.h"
+#include "nimble/host/util/include/host/util/util.h"
 
 /* Wheel size for simulation calculations */
 #define CSC_SIM_WHEEL_CIRCUMFERENCE_MM            2000
@@ -262,6 +263,9 @@ blecsc_on_sync(void)
     int rc;
 
     /* Figure out address to use while advertising (no privacy) */
+    rc = ble_hs_util_ensure_addr(0);
+    assert(rc == 0);
+
     rc = ble_hs_id_infer_auto(0, &blecsc_addr_type);
     assert(rc == 0);
 

apps/blehr/src/blehr.c

@@ -27,6 +27,7 @@
 #include "host/ble_hs.h"
 #include "services/gap/ble_svc_gap.h"
 #include "blehr_sens.h"
+#include "nimble/host/util/include/host/util/util.h"
 
 static bool notify_state;
 static uint16_t notify_conn_handle;
@@ -208,6 +209,9 @@ blehr_on_sync(void)
     int rc;
 
     /* Use privacy */
+    rc = ble_hs_util_ensure_addr(0);
+    assert(rc == 0);
+
     rc = ble_hs_id_infer_auto(0, &blehr_addr_type);
     assert(rc == 0);
 

apps/bleprph/src/bleprph.c

@@ -315,6 +315,8 @@ int bleprph_entry(void)
 
     /* startup bluetooth host stack*/
     ble_hs_thread_startup();
+    
+    return 0;
 }
 
 MSH_CMD_EXPORT_ALIAS(bleprph_entry, bleprph, "bluetooth peripheral role sample");

apps/bleprph/src/gatt_svr.c

@@ -20,6 +20,7 @@
 #include <assert.h>
 #include <stdio.h>
 #include <string.h>
+#include <stdlib.h>
 #include "host/ble_hs.h"
 #include "host/ble_uuid.h"
 #include "bleprph.h"

apps/bleprph/src/misc.c

@@ -18,6 +18,7 @@
  */
 
 #include "bleprph.h"
+#include "host/ble_hs.h"
 
 /**
  * Utility function to log an array of bytes.

babblesim/README.md

@@ -0,0 +1 @@
+BabbleSim support for Apache NimBLE

babblesim/core/include/argparse.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BSIM_NRF_ARGS_H
+#define BSIM_NRF_ARGS_H
+
+#include <stdint.h>
+#include "NRF_hw_args.h"
+#include "bs_cmd_line.h"
+#include "bs_cmd_line_typical.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct nrf52_bsim_args_t {
+    BS_BASIC_DEVICE_OPTIONS_FIELDS
+    nrf_hw_sub_args_t nrf_hw;
+};
+
+struct nrf52_bsim_args_t *nrfbsim_argsparse(int argc, char *argv[]);
+void nrfbsim_register_args(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

babblesim/core/include/cmsis.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This header defines replacements for inline
+ * ARM Cortex-M CMSIS intrinsics.
+ */
+
+#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_H
+#define BOARDS_POSIX_NRF52_BSIM_CMSIS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Implement the following ARM intrinsics as no-op:
+ * - ARM Data Synchronization Barrier
+ * - ARM Data Memory Synchronization Barrier
+ * - ARM Instruction Synchronization Barrier
+ * - ARM No Operation
+ */
+#ifndef __DMB
+#define __DMB()
+#endif
+
+#ifndef __DSB
+#define __DSB()
+#endif
+
+#ifndef __ISB
+#define __ISB()
+#endif
+
+#ifndef __NOP
+#define __NOP()
+#endif
+
+void NVIC_SystemReset(void);
+void __disable_irq(void);
+void __enable_irq(void);
+uint32_t __get_PRIMASK(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_H */

babblesim/core/include/core_cm4.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _BSIM_CORE_CM4_H
+#define _BSIM_CORE_CM4_H
+
+#include <stdint.h>
+
+/* Include the original ext_NRF52_hw_models core_cm4.h */
+#include <../HW_models/core_cm4.h>
+
+/* Add missing function definitions */
+extern void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+extern void NVIC_EnableIRQ(IRQn_Type IRQn);
+extern void NVIC_DisableIRQ(IRQn_Type IRQn);
+
+void __WFI(void);
+
+#ifndef __REV
+#define __REV __builtin_bswap32
+#endif
+
+#endif

babblesim/core/include/time_machine.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2017 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _TIME_MACHINE_H
+#define _TIME_MACHINE_H
+
+#include "bs_types.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+extern bs_time_t now;
+bs_time_t tm_get_abs_time(void);
+bs_time_t tm_get_hw_time(void);
+bs_time_t tm_hw_time_to_abs_time(bs_time_t hwtime);
+bs_time_t tm_abs_time_to_hw_time(bs_time_t abstime);
+
+void tm_reset_hw_times(void);
+
+void tm_find_next_timer_to_trigger(void);
+bs_time_t tm_get_next_timer_abstime(void);
+
+void tm_update_last_phy_sync_time(bs_time_t abs_time);
+
+void tm_set_phy_max_resync_offset(bs_time_t offset_in_us);
+
+void tm_run_forever(void);
+
+void tm_sleep_until_hw_time(bs_time_t hw_time);
+
+void tm_sleep_until_abs_time(bs_time_t time);
+
+void tm_start(void);
+
+void tm_tick(void);
+
+void tm_tick_limited(bs_time_t max_time_diff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

porting/targets/dummy_bsp/pkg.yml → babblesim/core/pkg.yml

@@ -17,11 +17,16 @@
 # under the License.
 #
 
-pkg.name: porting/targets/dummy_bsp
-pkg.type: bsp
-pkg.description: A dummy BSP definition
+pkg.name: babblesim/core
+pkg.description: time machine, irq handeler, core
 pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
 pkg.homepage: "http://mynewt.apache.org/"
 pkg.keywords:
-pkg.cflags:
+
 pkg.deps:
+  - "babblesim/sdk"
+
+pkg.cflags: -std=gnu99
+
+pkg.init:
+  bsim_start: 9999

babblesim/core/src/argparse.c

@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2017 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <stdlib.h>
+#include <limits.h>
+#include "bs_tracing.h"
+#include "bs_oswrap.h"
+#include "bs_dump_files.h"
+#include "argparse.h"
+#include "NRF_hw_args.h"
+#include "bs_cmd_line.h"
+#include "bs_dynargs.h"
+#include "bs_cmd_line_typical.h"
+#include "NRF_HWLowL.h"
+#include "controller/ble_ll.h"
+
+static bs_args_struct_t *args_struct;
+static struct nrf52_bsim_args_t arg;
+const char *bogus_sim_id = "bogus";
+
+static void cmd_trace_lvl_found(char *argv, int offset)
+{
+	bs_trace_set_level(arg.verb);
+}
+
+static void cmd_gdev_nbr_found(char *argv, int offset)
+{
+	bs_trace_set_prefix_dev(arg.global_device_nbr);
+}
+
+static bool nosim;
+static void cmd_nosim_found(char *argv, int offset)
+{
+	hwll_set_nosim(true);
+}
+
+static void cmd_bdaddr_found(char *argv, int offset)
+{
+    union {
+        uint64_t u64;
+        uint8_t u8[8];
+    } bdaddr;
+    char *endptr;
+
+    if (sscanf(&argv[offset], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+               &bdaddr.u8[5], &bdaddr.u8[4], &bdaddr.u8[3], &bdaddr.u8[2],
+               &bdaddr.u8[1], &bdaddr.u8[0]) < 6) {
+        bdaddr.u64 = strtoull(&argv[offset], &endptr, 0);
+        if (*endptr) {
+            return;
+        }
+
+        bdaddr.u64 = htole64(bdaddr.u64);
+    }
+
+    ble_ll_set_public_addr(bdaddr.u8);
+}
+
+static void print_no_sim_warning(void)
+{
+	bs_trace_warning("Neither simulation id or the device number "
+			"have been set. I assume you want to run "
+			"without a BabbleSim phy (-nosim)\n");
+	bs_trace_warning("If this is not what you wanted, check with "
+			"--help how to set them\n");
+	bs_trace_raw(3, "setting sim_id to 'bogus', device number to 0 "
+			"and nosim\n");
+}
+
+void nrfbsim_register_args(void)
+{
+#define args (&arg)
+	/* This define is quite ugly, but allows reusing the definitions
+	 * provided by the utils library */
+	static bs_args_struct_t args_struct_toadd[] = {
+		ARG_TABLE_S_ID,
+		ARG_TABLE_P_ID_2G4,
+		ARG_TABLE_DEV_NBR,
+		ARG_TABLE_GDEV_NBR,
+		ARG_TABLE_VERB,
+		ARG_TABLE_SEED,
+		ARG_TABLE_COLOR,
+		ARG_TABLE_NOCOLOR,
+		ARG_TABLE_FORCECOLOR,
+		_NRF_HW_SUB_CMD_ARG_STRUCT,
+		/*
+		 * Fields:
+		 * manual, mandatory, switch,
+		 * option_name, var_name, type,
+		 * destination, callback,
+		 * description
+		 */
+		{ false, false , false,
+		  "A", "bdaddr", 's',
+		  NULL, cmd_bdaddr_found, "Device public address"},
+		{false, false, true,
+		"nosim", "", 'b',
+		(void *)&nosim, cmd_nosim_found,
+		"(debug feature) Do not connect to the phy"},
+		BS_DUMP_FILES_ARGS,
+		{true, false, false,
+		"argsmain", "arg", 'l',
+		NULL, NULL,
+		"The arguments that follow will be passed to main (default)"},
+		ARG_TABLE_ENDMARKER
+	};
+#undef args
+
+	bs_add_dynargs(&args_struct, args_struct_toadd);
+}
+
+/**
+ * Check the arguments provided in the command line: set args based on it or
+ * defaults, and check they are correct
+ */
+struct nrf52_bsim_args_t *nrfbsim_argsparse(int argc, char *argv[])
+{
+	bs_args_set_defaults(args_struct);
+	arg.verb = 2;
+	bs_trace_set_level(arg.verb);
+	nrf_hw_sub_cmline_set_defaults(&arg.nrf_hw);
+	static const char default_phy[] = "2G4";
+
+    for (int i = 1; i < argc; i++) {
+        if (bs_is_option(argv[i], "argsmain", 0)) {
+            continue;
+        }
+
+        if (!bs_args_parse_one_arg(argv[i], args_struct)) {
+            bs_args_print_switches_help(args_struct);
+            bs_trace_error_line("Incorrect option %s\n",
+                                argv[i]);
+        }
+    }
+
+	/**
+	 * If the user did not set the simulation id or device number
+	 * we assume he wanted to run with nosim (but warn him)
+	 */
+	if ((!nosim) && (arg.s_id == NULL) && (arg.device_nbr == UINT_MAX)) {
+		print_no_sim_warning();
+		nosim = true;
+		hwll_set_nosim(true);
+	}
+	if (nosim) {
+		if (arg.s_id == NULL) {
+			arg.s_id = (char *)bogus_sim_id;
+		}
+		if (arg.device_nbr == UINT_MAX) {
+			arg.device_nbr = 0;
+		}
+	}
+
+	if (arg.device_nbr == UINT_MAX) {
+		bs_args_print_switches_help(args_struct);
+		bs_trace_error_line("The command line option <device number> "
+				    "needs to be set\n");
+	}
+	if (arg.global_device_nbr == UINT_MAX) {
+		arg.global_device_nbr = arg.device_nbr;
+		bs_trace_set_prefix_dev(arg.global_device_nbr);
+	}
+	if (!arg.s_id) {
+		bs_args_print_switches_help(args_struct);
+		bs_trace_error_line("The command line option <simulation ID> "
+				    "needs to be set\n");
+	}
+	if (!arg.p_id) {
+		arg.p_id = (char *)default_phy;
+	}
+
+	if (arg.rseed == UINT_MAX) {
+		arg.rseed = 0x1000 + arg.device_nbr;
+	}
+	return &arg;
+}

babblesim/core/src/cmsis.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "irq_ctrl.h"
+
+#include "irq_sources.h"
+#include <nrfx.h>
+#include "cmsis.h"
+#include "os/sim.h"
+
+#include <stdbool.h>
+#include <stddef.h>
+
+extern void (* systemVectors[256])(void);
+
+/*
+ *  Replacement for ARMs NVIC functions()
+ */
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+	hw_irq_ctrl_raise_im_from_sw(IRQn);
+}
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+	hw_irq_ctrl_clear_irq(IRQn);
+}
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+	hw_irq_ctrl_disable_irq(IRQn);
+}
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+	hw_irq_ctrl_enable_irq(IRQn);
+}
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+	hw_irq_ctrl_prio_set(IRQn, priority);
+}
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+	return hw_irq_ctrl_get_prio(IRQn);
+}
+
+void NVIC_SystemReset(void)
+{
+	inner_main_clean_up(1);
+}
+
+/*
+ * Replacements for some other CMSIS functions
+ */
+void __enable_irq(void)
+{
+	hw_irq_ctrl_change_lock(false);
+}
+
+void __disable_irq(void)
+{
+	hw_irq_ctrl_change_lock(true);
+}
+
+uint32_t __get_PRIMASK(void)
+{
+	return hw_irq_ctrl_get_current_lock();
+}
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+	systemVectors[(int32_t)IRQn + 16] = (void(*)(void))vector;
+}

babblesim/core/src/irq_handler.c

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2017 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * SW side of the IRQ handling
+ */
+
+#include <stdint.h>
+#include "irq_ctrl.h"
+#include "irq_sources.h"
+#include "os/sim.h"
+
+static int currently_running_irq = -1;
+extern void (* const systemVectors[256])(void);
+
+/**
+ * When an interrupt is raised, this function is called to handle it and, if
+ * needed, swap to a re-enabled thread
+ *
+ * Note that even that this function is executing in a Zephyr thread,  it is
+ * effectively the model of the interrupt controller passing context to the IRQ
+ * handler and therefore its priority handling
+ */
+
+void posix_interrupt_raised(void)
+{
+    uint64_t irq_lock;
+    int irq_nbr;
+
+    irq_lock = hw_irq_ctrl_get_current_lock();
+
+    if (irq_lock) {
+        /* "spurious" wakes can happen with interrupts locked */
+        return;
+    }
+
+    while ((irq_nbr = hw_irq_ctrl_get_highest_prio_irq()) != -1) {
+        int last_current_running_prio = hw_irq_ctrl_get_cur_prio();
+        int last_running_irq = currently_running_irq;
+
+        hw_irq_ctrl_set_cur_prio(hw_irq_ctrl_get_prio(irq_nbr));
+        hw_irq_ctrl_clear_irq(irq_nbr);
+
+        currently_running_irq = irq_nbr;
+        systemVectors[irq_nbr + 16]();
+        currently_running_irq = last_running_irq;
+
+        hw_irq_ctrl_set_cur_prio(last_current_running_prio);
+    }
+}
+
+/**
+ * Thru this function the IRQ controller can raise an immediate  interrupt which
+ * will interrupt the SW itself
+ * (this function should only be called from the HW model code, from SW threads)
+ */
+void posix_irq_handler_im_from_sw(void)
+{
+	/*
+	 * if a higher priority interrupt than the possibly currently running is
+	 * pending we go immediately into irq_handler() to vector into its
+	 * handler
+	 */
+	if (hw_irq_ctrl_get_highest_prio_irq() != -1) {
+	    posix_interrupt_raised();
+	}
+}

babblesim/core/src/main_config.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2017-2018 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <unistd.h>
+#include "NRF_HW_model_top.h"
+#include "NRF_HWLowL.h"
+#include "bs_tracing.h"
+#include "bs_symbols.h"
+#include "bs_types.h"
+#include "bs_rand_main.h"
+#include "bs_pc_backchannel.h"
+#include "bs_dump_files.h"
+#include "argparse.h"
+#include "time_machine.h"
+#include "os/mynewt.h"
+#include <stdio.h>
+#include "os/sim.h"
+
+uint global_device_nbr;
+struct nrf52_bsim_args_t *args;
+
+void
+bst_tick(bs_time_t time)
+{
+    return;
+}
+
+uint8_t
+inner_main_clean_up(int exit_code)
+{
+    hwll_terminate_simulation();
+    nrf_hw_models_free_all();
+    bs_dump_files_close_all();
+
+    bs_clean_back_channels();
+    return 0;
+}
+
+uint8_t
+main_clean_up_trace_wrap(void)
+{
+    return inner_main_clean_up(0);
+}
+
+void
+bsim_init(int argc, char** argv, int (*main_fn)(int argc, char **arg))
+{
+        setvbuf(stdout, NULL, _IOLBF, 512);
+        setvbuf(stderr, NULL, _IOLBF, 512);
+
+        bs_trace_register_cleanup_function(main_clean_up_trace_wrap);
+        bs_trace_register_time_function(tm_get_abs_time);
+
+        nrf_hw_pre_init();
+        nrfbsim_register_args();
+
+        args = nrfbsim_argsparse(argc, argv);
+        global_device_nbr = args->global_device_nbr;
+
+        bs_read_function_names_from_Tsymbols(argv[0]);
+
+        nrf_hw_initialize(&args->nrf_hw);
+        os_init(main_fn);
+        os_start();
+
+        while (1) {
+            sleep(1);
+        }
+}
+
+void
+bsim_start(void)
+{
+    bs_trace_raw(9, "%s: Connecting to phy...\n", __func__);
+    hwll_connect_to_phy(args->device_nbr, args->s_id, args->p_id);
+    bs_trace_raw(9, "%s: Connected\n", __func__);
+
+    bs_random_init(args->rseed);
+    bs_dump_files_open(args->s_id, args->global_device_nbr);
+}

babblesim/core/src/time_machine.c

@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2017-2018 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "NRF_HW_model_top.h"
+#include "NRF_HWLowL.h"
+#include "bs_tracing.h"
+#include "bs_types.h"
+#include "bs_utils.h"
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <ctype.h>
+
+/* Note: All timers are relative to hw_time and NOT to 'now' */
+extern bs_time_t timer_nrf_main_timer;
+
+/* The events priorities are as in this list from top to bottom
+ * Priority being which timer executes first if several trigger at the same
+ * instant
+ */
+static enum {
+    NRF_HW_MAIN_TIMER = 0,
+    NUMBER_OF_TIMERS,
+    NONE
+} next_timer_index = NONE;
+
+static bs_time_t *Timer_list[NUMBER_OF_TIMERS] = {
+    &timer_nrf_main_timer,
+};
+static bs_time_t next_timer_time = TIME_NEVER;
+
+/*
+ * Current absolute time of this device, as the device knows it.
+ * It is never reset:
+ */
+bs_time_t now;
+/* Current time the HW of this device things it is */
+static bs_time_t hw_time;
+/*
+ * Offset between the current absolute time of the device and the HW time
+ * That is, the absolute time when the HW_time got reset
+ */
+static bs_time_t hw_time_delta;
+
+/* Last time we synchronized with the bsim PHY, in device abs time */
+static bs_time_t last_bsim_phy_sync_time;
+
+#define BSIM_DEFAULT_PHY_MAX_RESYNC_OFFSET 1000000
+/* At least every second we will inform the simulator about our timing */
+static bs_time_t max_resync_offset = BSIM_DEFAULT_PHY_MAX_RESYNC_OFFSET;
+
+/**
+ * Set the maximum amount of time the device will spend without talking
+ * (synching) with the phy.
+ * This does not change the functional behavior of the Zephyr code or of the
+ * radio emulation, and it is only relevant if special test code running in the
+ * device interacts behind the scenes with other devices test code.
+ * Setting for example a value of 5ms will ensure that this device time
+ * will never be more than 5ms away from the phy. Setting it in all devices
+ * to 5ms would then ensure no device time is farther apart than 5ms from any
+ * other.
+ *
+ * Note that setting low values has a performance penalty.
+ */
+void
+tm_set_phy_max_resync_offset(bs_time_t offset_in_us)
+{
+    max_resync_offset = offset_in_us;
+}
+
+/**
+ * Return the absolute current time (no HW model except the RADIO
+ * should look into this)
+ */
+bs_time_t
+tm_get_abs_time(void)
+{
+    return now;
+}
+
+/**
+ * Return the current HW time
+ */
+bs_time_t
+tm_get_hw_time(void)
+{
+    return hw_time;
+}
+
+bs_time_t
+posix_get_hw_cycle(void)
+{
+    return tm_get_hw_time();
+}
+
+/**
+ * Reset the HW time
+ */
+static void
+tm_reset_hw_time(void)
+{
+    hw_time = 0;
+    hw_time_delta = now;
+    if (now != 0) {
+        bs_trace_error_line("Reset not supposed to happen after "
+                            "initialization\n");
+    }
+}
+
+/**
+ * Update the current hw_time value given the absolute time
+ */
+INLINE void
+tm_update_HW_time(void)
+{
+    hw_time = now - hw_time_delta;
+}
+
+/*
+ * Reset the HW time
+ */
+void
+tm_reset_hw_times(void)
+{
+    tm_reset_hw_time();
+}
+
+/**
+ * Advance the internal time values of this device until time
+ */
+void
+tm_sleep_until_abs_time(bs_time_t time)
+{
+    if (time >= now) {
+        /*
+         * Ensure that at least we sync with the phy
+         * every max_resync_offset
+         */
+        if (time > last_bsim_phy_sync_time + max_resync_offset) {
+            hwll_sync_time_with_phy(time);
+            last_bsim_phy_sync_time = time;
+        }
+
+        now = time;
+    } else {
+        /* LCOV_EXCL_START */
+        bs_trace_warning_manual_time_line(now, "next_time_time "
+                                               "corrupted (%"PRItime"<= %"PRItime", timer idx=%i)\n",
+                                          time, now, next_timer_index);
+        /* LCOV_EXCL_STOP */
+    }
+    tm_update_HW_time();
+}
+
+/**
+ * Keep track of the last time we synchronized the time with the scheduler
+ */
+void
+tm_update_last_phy_sync_time(bs_time_t abs_time)
+{
+    last_bsim_phy_sync_time = abs_time;
+}
+
+/**
+ * Advance the internal time values of this device
+ * until the HW time reaches hw_time
+ */
+void
+tm_sleep_until_hw_time(bs_time_t hw_time)
+{
+    bs_time_t next_time = TIME_NEVER;
+
+    if (hw_time != TIME_NEVER) {
+        next_time = hw_time + hw_time_delta;
+    }
+
+    tm_sleep_until_abs_time(next_time);
+}
+
+/**
+ * Look into all timers and update next_timer accordingly
+ * To be called each time a "timed process" updates its timer
+ */
+void
+tm_find_next_timer_to_trigger(void)
+{
+    next_timer_time = *Timer_list[0];
+    next_timer_index = 0;
+
+    for (uint i = 1; i < NUMBER_OF_TIMERS; i++) {
+        if (next_timer_time > *Timer_list[i]) {
+            next_timer_time = *Timer_list[i];
+            next_timer_index = i;
+        }
+    }
+}
+
+bs_time_t
+tm_get_next_timer_abstime(void)
+{
+    return next_timer_time + hw_time_delta;
+}
+
+bs_time_t
+tm_hw_time_to_abs_time(bs_time_t hwtime)
+{
+    if (hwtime == TIME_NEVER) {
+        return TIME_NEVER;
+    }
+    return hwtime + hw_time_delta;
+}
+
+bs_time_t
+tm_abs_time_to_hw_time(bs_time_t abstime)
+{
+    if (abstime == TIME_NEVER) {
+        return TIME_NEVER;
+    }
+    return abstime - hw_time_delta;
+}
+
+void
+tm_tick_limited(bs_time_t max_time_diff)
+{
+    bs_time_t time_to_wait;
+
+    if (max_time_diff != TIME_NEVER && now + max_time_diff < next_timer_time) {
+        time_to_wait = now + max_time_diff;
+    } else {
+        time_to_wait = next_timer_time;
+    }
+
+    tm_sleep_until_hw_time(time_to_wait);
+    switch (next_timer_index) {
+        case NRF_HW_MAIN_TIMER:
+            nrf_hw_some_timer_reached();
+            break;
+        default:
+            bs_trace_error_time_line("next_timer_index "
+                                     "corrupted\n");
+            break;
+    }
+    tm_find_next_timer_to_trigger();
+}
+
+void
+tm_tick(void)
+{
+    tm_tick_limited(TIME_NEVER);
+}

babblesim/edtt/hci_test/pkg.yml

@@ -0,0 +1,32 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+pkg.name: babblesim/edtt/hci_test
+pkg.type: app
+pkg.description: nRF52 on BabbleSim - EDTT tester
+pkg.author: "Codecoup"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+
+pkg.deps:
+    - "@apache-mynewt-core/sys/console/stub"
+    - "@apache-mynewt-core/sys/log/stub"
+    - "@apache-mynewt-core/sys/stats/full"
+    - "@apache-mynewt-core/kernel/os"
+    - nimble/transport
+    - babblesim/edtt/hci_transport

babblesim/edtt/hci_test/src/main.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021 Codecoup
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/mynewt.h"
+#include "ble_hci_edtt.h"
+
+static int
+main_fn(int argc, char **argv)
+{
+    sysinit();
+
+    edtt_init();
+
+    while (1) {
+        os_eventq_run(os_eventq_dflt_get());
+    }
+    return 0;
+}
+
+int
+main(int argc, char **argv)
+{
+    extern void bsim_init(int argc, char** argv, void *main_fn);
+    bsim_init(argc, argv, main_fn);
+
+    return 0;
+}

babblesim/edtt/hci_test/syscfg.yml

@@ -0,0 +1,30 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+    BLE_TRANSPORT_LL: native
+    BLE_TRANSPORT_HS: custom
+
+    # EDTT requires 0x123456789ABC address for first device
+    # and 0x456789ABCDEF for second
+    BLE_LL_PUBLIC_DEV_ADDR: 0x123456789ABC
+#    BLE_LL_PUBLIC_DEV_ADDR: 0x456789ABCDEF
+
+    # For LL/CON/ADV/BV-09-C, LL/CON/ADV/BV-10-C
+    BLE_LL_CFG_FEAT_LE_CSA2: 1

nimble/transport/ram/include/transport/ram/ble_hci_ram.h → babblesim/edtt/hci_transport/include/ble_hci_edtt.h

@@ -1,4 +1,6 @@
 /*
+ * Copyright (c) 2021 Codecoup
+ *
  * Licensed to the Apache Software Foundation (ASF) under one
  * or more contributor license agreements.  See the NOTICE file
  * distributed with this work for additional information
@@ -17,16 +19,14 @@
  * under the License.
  */
 
-#ifndef H_BLE_HCI_RAM_
-#define H_BLE_HCI_RAM_
-
-#include "nimble/ble_hci_trans.h"
+#ifndef H_BLE_HCI_EDTT_
+#define H_BLE_HCI_EDTT_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void ble_hci_ram_init(void);
+int edtt_init(void);
 
 #ifdef __cplusplus
 }

babblesim/edtt/hci_transport/include/commands.h

@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2019 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef EDDT_APP_COMMANDS_H
+#define EDDT_APP_COMMANDS_H
+
+enum commands_t {
+	CMD_NOTHING = 0,
+	CMD_ECHO_REQ,
+	CMD_ECHO_RSP,
+	CMD_INQUIRE_REQ,
+	CMD_INQUIRE_RSP,
+	CMD_DISCONNECT_REQ,
+	CMD_DISCONNECT_RSP,
+	CMD_READ_REMOTE_VERSION_INFORMATION_REQ,
+	CMD_READ_REMOTE_VERSION_INFORMATION_RSP,
+	CMD_SET_EVENT_MASK_REQ,
+	CMD_SET_EVENT_MASK_RSP,
+	CMD_RESET_REQ,
+	CMD_RESET_RSP,
+	CMD_READ_TRANSMIT_POWER_LEVEL_REQ,
+	CMD_READ_TRANSMIT_POWER_LEVEL_RSP,
+	CMD_SET_CONTROLLER_TO_HOST_FLOW_CONTROL_REQ,
+	CMD_SET_CONTROLLER_TO_HOST_FLOW_CONTROL_RSP,
+	CMD_HOST_BUFFER_SIZE_REQ,
+	CMD_HOST_BUFFER_SIZE_RSP,
+	CMD_HOST_NUMBER_OF_COMPLETED_PACKETS_REQ,
+	CMD_HOST_NUMBER_OF_COMPLETED_PACKETS_RSP,
+	CMD_SET_EVENT_MASK_PAGE_2_REQ,
+	CMD_SET_EVENT_MASK_PAGE_2_RSP,
+	CMD_WRITE_LE_HOST_SUPPORT_REQ,
+	CMD_WRITE_LE_HOST_SUPPORT_RSP,
+	CMD_READ_AUTHENTICATED_PAYLOAD_TIMEOUT_REQ,
+	CMD_READ_AUTHENTICATED_PAYLOAD_TIMEOUT_RSP,
+	CMD_WRITE_AUTHENTICATED_PAYLOAD_TIMEOUT_REQ,
+	CMD_WRITE_AUTHENTICATED_PAYLOAD_TIMEOUT_RSP,
+	CMD_READ_LOCAL_VERSION_INFORMATION_REQ,
+	CMD_READ_LOCAL_VERSION_INFORMATION_RSP,
+	CMD_READ_LOCAL_SUPPORTED_COMMANDS_REQ,
+	CMD_READ_LOCAL_SUPPORTED_COMMANDS_RSP,
+	CMD_READ_LOCAL_SUPPORTED_FEATURES_REQ,
+	CMD_READ_LOCAL_SUPPORTED_FEATURES_RSP,
+	CMD_READ_BUFFER_SIZE_REQ,
+	CMD_READ_BUFFER_SIZE_RSP,
+	CMD_READ_BD_ADDR_REQ,
+	CMD_READ_BD_ADDR_RSP,
+	CMD_READ_RSSI_REQ,
+	CMD_READ_RSSI_RSP,
+	CMD_LE_SET_EVENT_MASK_REQ,
+	CMD_LE_SET_EVENT_MASK_RSP,
+	CMD_LE_READ_BUFFER_SIZE_REQ,
+	CMD_LE_READ_BUFFER_SIZE_RSP,
+	CMD_LE_READ_LOCAL_SUPPORTED_FEATURES_REQ,
+	CMD_LE_READ_LOCAL_SUPPORTED_FEATURES_RSP,
+	CMD_LE_SET_RANDOM_ADDRESS_REQ,
+	CMD_LE_SET_RANDOM_ADDRESS_RSP,
+	CMD_LE_SET_ADVERTISING_PARAMETERS_REQ,
+	CMD_LE_SET_ADVERTISING_PARAMETERS_RSP,
+	CMD_LE_READ_ADVERTISING_CHANNEL_TX_POWER_REQ,
+	CMD_LE_READ_ADVERTISING_CHANNEL_TX_POWER_RSP,
+	CMD_LE_SET_ADVERTISING_DATA_REQ,
+	CMD_LE_SET_ADVERTISING_DATA_RSP,
+	CMD_LE_SET_SCAN_RESPONSE_DATA_REQ,
+	CMD_LE_SET_SCAN_RESPONSE_DATA_RSP,
+	CMD_LE_SET_ADVERTISING_ENABLE_REQ,
+	CMD_LE_SET_ADVERTISING_ENABLE_RSP,
+	CMD_LE_SET_SCAN_PARAMETERS_REQ,
+	CMD_LE_SET_SCAN_PARAMETERS_RSP,
+	CMD_LE_SET_SCAN_ENABLE_REQ,
+	CMD_LE_SET_SCAN_ENABLE_RSP,
+	CMD_LE_CREATE_CONNECTION_REQ,
+	CMD_LE_CREATE_CONNECTION_RSP,
+	CMD_LE_CREATE_CONNECTION_CANCEL_REQ,
+	CMD_LE_CREATE_CONNECTION_CANCEL_RSP,
+	CMD_LE_READ_FILTER_ACCEPT_LIST_SIZE_REQ,
+	CMD_LE_READ_FILTER_ACCEPT_LIST_SIZE_RSP,
+	CMD_LE_CLEAR_FILTER_ACCEPT_LIST_REQ,
+	CMD_LE_CLEAR_FILTER_ACCEPT_LIST_RSP,
+	CMD_LE_ADD_DEVICE_TO_FILTER_ACCEPT_LIST_REQ,
+	CMD_LE_ADD_DEVICE_TO_FILTER_ACCEPT_LIST_RSP,
+	CMD_LE_REMOVE_DEVICE_FROM_FILTER_ACCEPT_LIST_REQ,
+	CMD_LE_REMOVE_DEVICE_FROM_FILTER_ACCEPT_LIST_RSP,
+	CMD_LE_CONNECTION_UPDATE_REQ,
+	CMD_LE_CONNECTION_UPDATE_RSP,
+	CMD_LE_SET_HOST_CHANNEL_CLASSIFICATION_REQ,
+	CMD_LE_SET_HOST_CHANNEL_CLASSIFICATION_RSP,
+	CMD_LE_READ_CHANNEL_MAP_REQ,
+	CMD_LE_READ_CHANNEL_MAP_RSP,
+	CMD_LE_READ_REMOTE_FEATURES_REQ,
+	CMD_LE_READ_REMOTE_FEATURES_RSP,
+	CMD_LE_ENCRYPT_REQ,
+	CMD_LE_ENCRYPT_RSP,
+	CMD_LE_RAND_REQ,
+	CMD_LE_RAND_RSP,
+	CMD_LE_START_ENCRYPTION_REQ,
+	CMD_LE_START_ENCRYPTION_RSP,
+	CMD_LE_LONG_TERM_KEY_REQUEST_REPLY_REQ,
+	CMD_LE_LONG_TERM_KEY_REQUEST_REPLY_RSP,
+	CMD_LE_LONG_TERM_KEY_REQUEST_NEGATIVE_REPLY_REQ,
+	CMD_LE_LONG_TERM_KEY_REQUEST_NEGATIVE_REPLY_RSP,
+	CMD_LE_READ_SUPPORTED_STATES_REQ,
+	CMD_LE_READ_SUPPORTED_STATES_RSP,
+	CMD_LE_RECEIVER_TEST_REQ,
+	CMD_LE_RECEIVER_TEST_RSP,
+	CMD_LE_TRANSMITTER_TEST_REQ,
+	CMD_LE_TRANSMITTER_TEST_RSP,
+	CMD_LE_TEST_END_REQ,
+	CMD_LE_TEST_END_RSP,
+	CMD_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_REPLY_REQ,
+	CMD_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_REPLY_RSP,
+	CMD_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_NEGATIVE_REPLY_REQ,
+	CMD_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_NEGATIVE_REPLY_RSP,
+	CMD_LE_SET_DATA_LENGTH_REQ,
+	CMD_LE_SET_DATA_LENGTH_RSP,
+	CMD_LE_READ_SUGGESTED_DEFAULT_DATA_LENGTH_REQ,
+	CMD_LE_READ_SUGGESTED_DEFAULT_DATA_LENGTH_RSP,
+	CMD_LE_WRITE_SUGGESTED_DEFAULT_DATA_LENGTH_REQ,
+	CMD_LE_WRITE_SUGGESTED_DEFAULT_DATA_LENGTH_RSP,
+	CMD_LE_READ_LOCAL_P_256_PUBLIC_KEY_COMMAND_REQ,
+	CMD_LE_READ_LOCAL_P_256_PUBLIC_KEY_COMMAND_RSP,
+	CMD_LE_GENERATE_DHKEY_COMMAND_REQ,
+	CMD_LE_GENERATE_DHKEY_COMMAND_RSP,
+	CMD_LE_ADD_DEVICE_TO_RESOLVING_LIST_REQ,
+	CMD_LE_ADD_DEVICE_TO_RESOLVING_LIST_RSP,
+	CMD_LE_REMOVE_DEVICE_FROM_RESOLVING_LIST_REQ,
+	CMD_LE_REMOVE_DEVICE_FROM_RESOLVING_LIST_RSP,
+	CMD_LE_CLEAR_RESOLVING_LIST_REQ,
+	CMD_LE_CLEAR_RESOLVING_LIST_RSP,
+	CMD_LE_READ_RESOLVING_LIST_SIZE_REQ,
+	CMD_LE_READ_RESOLVING_LIST_SIZE_RSP,
+	CMD_LE_READ_PEER_RESOLVABLE_ADDRESS_REQ,
+	CMD_LE_READ_PEER_RESOLVABLE_ADDRESS_RSP,
+	CMD_LE_READ_LOCAL_RESOLVABLE_ADDRESS_REQ,
+	CMD_LE_READ_LOCAL_RESOLVABLE_ADDRESS_RSP,
+	CMD_LE_SET_ADDRESS_RESOLUTION_ENABLE_REQ,
+	CMD_LE_SET_ADDRESS_RESOLUTION_ENABLE_RSP,
+	CMD_LE_SET_RESOLVABLE_PRIVATE_ADDRESS_TIMEOUT_REQ,
+	CMD_LE_SET_RESOLVABLE_PRIVATE_ADDRESS_TIMEOUT_RSP,
+	CMD_LE_READ_MAXIMUM_DATA_LENGTH_REQ,
+	CMD_LE_READ_MAXIMUM_DATA_LENGTH_RSP,
+	CMD_LE_READ_PHY_REQ,
+	CMD_LE_READ_PHY_RSP,
+	CMD_LE_SET_DEFAULT_PHY_REQ,
+	CMD_LE_SET_DEFAULT_PHY_RSP,
+	CMD_LE_SET_PHY_REQ,
+	CMD_LE_SET_PHY_RSP,
+	CMD_LE_ENHANCED_RECEIVER_TEST_REQ,
+	CMD_LE_ENHANCED_RECEIVER_TEST_RSP,
+	CMD_LE_ENHANCED_TRANSMITTER_TEST_REQ,
+	CMD_LE_ENHANCED_TRANSMITTER_TEST_RSP,
+	CMD_LE_SET_EXTENDED_ADVERTISING_PARAMETERS_REQ,
+	CMD_LE_SET_EXTENDED_ADVERTISING_PARAMETERS_RSP,
+	CMD_LE_SET_EXTENDED_ADVERTISING_DATA_REQ,
+	CMD_LE_SET_EXTENDED_ADVERTISING_DATA_RSP,
+	CMD_LE_SET_EXTENDED_SCAN_RESPONSE_DATA_REQ,
+	CMD_LE_SET_EXTENDED_SCAN_RESPONSE_DATA_RSP,
+	CMD_LE_SET_EXTENDED_ADVERTISING_ENABLE_REQ,
+	CMD_LE_SET_EXTENDED_ADVERTISING_ENABLE_RSP,
+	CMD_LE_READ_MAXIMUM_ADVERTISING_DATA_LENGTH_REQ,
+	CMD_LE_READ_MAXIMUM_ADVERTISING_DATA_LENGTH_RSP,
+	CMD_LE_READ_NUMBER_OF_SUPPORTED_ADVERTISING_SETS_REQ,
+	CMD_LE_READ_NUMBER_OF_SUPPORTED_ADVERTISING_SETS_RSP,
+	CMD_LE_REMOVE_ADVERTISING_SET_REQ,
+	CMD_LE_REMOVE_ADVERTISING_SET_RSP,
+	CMD_LE_CLEAR_ADVERTISING_SETS_REQ,
+	CMD_LE_CLEAR_ADVERTISING_SETS_RSP,
+	CMD_LE_SET_PERIODIC_ADVERTISING_PARAMETERS_REQ,
+	CMD_LE_SET_PERIODIC_ADVERTISING_PARAMETERS_RSP,
+	CMD_LE_SET_PERIODIC_ADVERTISING_DATA_REQ,
+	CMD_LE_SET_PERIODIC_ADVERTISING_DATA_RSP,
+	CMD_LE_SET_PERIODIC_ADVERTISING_ENABLE_REQ,
+	CMD_LE_SET_PERIODIC_ADVERTISING_ENABLE_RSP,
+	CMD_LE_SET_EXTENDED_SCAN_PARAMETERS_REQ,
+	CMD_LE_SET_EXTENDED_SCAN_PARAMETERS_RSP,
+	CMD_LE_SET_EXTENDED_SCAN_ENABLE_REQ,
+	CMD_LE_SET_EXTENDED_SCAN_ENABLE_RSP,
+	CMD_LE_EXTENDED_CREATE_CONNECTION_REQ,
+	CMD_LE_EXTENDED_CREATE_CONNECTION_RSP,
+	CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC_REQ,
+	CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC_RSP,
+	CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC_CANCEL_REQ,
+	CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC_CANCEL_RSP,
+	CMD_LE_PERIODIC_ADVERTISING_TERMINATE_SYNC_REQ,
+	CMD_LE_PERIODIC_ADVERTISING_TERMINATE_SYNC_RSP,
+	CMD_LE_ADD_DEVICE_TO_PERIODIC_ADVERTISER_LIST_REQ,
+	CMD_LE_ADD_DEVICE_TO_PERIODIC_ADVERTISER_LIST_RSP,
+	CMD_LE_REMOVE_DEVICE_FROM_PERIODIC_ADVERTISER_LIST_REQ,
+	CMD_LE_REMOVE_DEVICE_FROM_PERIODIC_ADVERTISER_LIST_RSP,
+	CMD_LE_CLEAR_PERIODIC_ADVERTISER_LIST_REQ,
+	CMD_LE_CLEAR_PERIODIC_ADVERTISER_LIST_RSP,
+	CMD_LE_READ_PERIODIC_ADVERTISER_LIST_SIZE_REQ,
+	CMD_LE_READ_PERIODIC_ADVERTISER_LIST_SIZE_RSP,
+	CMD_LE_READ_TRANSMIT_POWER_REQ,
+	CMD_LE_READ_TRANSMIT_POWER_RSP,
+	CMD_LE_READ_RF_PATH_COMPENSATION_REQ,
+	CMD_LE_READ_RF_PATH_COMPENSATION_RSP,
+	CMD_LE_WRITE_RF_PATH_COMPENSATION_REQ,
+	CMD_LE_WRITE_RF_PATH_COMPENSATION_RSP,
+	CMD_LE_SET_PRIVACY_MODE_REQ,
+	CMD_LE_SET_PRIVACY_MODE_RSP,
+	CMD_WRITE_BD_ADDR_REQ,
+	CMD_WRITE_BD_ADDR_RSP,
+	CMD_FLUSH_EVENTS_REQ,
+	CMD_FLUSH_EVENTS_RSP,
+	CMD_HAS_EVENT_REQ,
+	CMD_HAS_EVENT_RSP,
+	CMD_GET_EVENT_REQ,
+	CMD_GET_EVENT_RSP,
+	CMD_LE_FLUSH_DATA_REQ,
+	CMD_LE_FLUSH_DATA_RSP,
+	CMD_LE_DATA_READY_REQ,
+	CMD_LE_DATA_READY_RSP,
+	CMD_LE_DATA_WRITE_REQ,
+	CMD_LE_DATA_WRITE_RSP,
+	CMD_LE_DATA_READ_REQ,
+	CMD_LE_DATA_READ_RSP,
+	CMD_GATT_SERVICE_SET_REQ,
+	CMD_GATT_SERVICE_SET_RSP,
+	CMD_GATT_SERVICE_NOTIFY_REQ,
+	CMD_GATT_SERVICE_NOTIFY_RSP,
+	CMD_GATT_SERVICE_INDICATE_REQ,
+	CMD_GATT_SERVICE_INDICATE_RSP,
+	CMD_GAP_ADVERTISING_MODE_REQ,
+	CMD_GAP_ADVERTISING_MODE_RSP,
+	CMD_GAP_ADVERTISING_DATA_REQ,
+	CMD_GAP_ADVERTISING_DATA_RSP,
+	CMD_GAP_SCANNING_MODE_REQ,
+	CMD_GAP_SCANNING_MODE_RSP,
+	CMD_READ_STATIC_ADDRESSES_REQ,
+	CMD_READ_STATIC_ADDRESSES_RSP,
+	CMD_READ_KEY_HIERARCHY_ROOTS_REQ,
+	CMD_READ_KEY_HIERARCHY_ROOTS_RSP,
+	CMD_GAP_READ_IRK_REQ,
+	CMD_GAP_READ_IRK_RSP,
+	CMD_GAP_ROLE_REQ,
+	CMD_GAP_ROLE_RSP
+};
+
+#endif /* EDDT_APP_COMMANDS_H */

babblesim/edtt/hci_transport/include/edtt_driver.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef EDTT_DRIVER_H
+#define EDTT_DRIVER_H
+
+#include <stdlib.h>
+#include <stdbool.h>
+
+#define EDTTT_NONBLOCK 0
+#define EDTTT_BLOCK 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Generic EDTT interface
+ */
+bool edtt_start(void);
+bool edtt_stop(void);
+int edtt_read(uint8_t *ptr, size_t size, int flags);
+int edtt_write(uint8_t *ptr, size_t size, int flags);
+
+/**
+ * Exclusive functions for the BabbleSim driver
+ */
+void enable_edtt_mode(void);
+void set_edtt_autoshutdown(bool mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EDTT_DRIVER_H */

nimble/transport/da1469x/pkg.yml → babblesim/edtt/hci_transport/pkg.yml

@@ -6,7 +6,7 @@
 # to you under the Apache License, Version 2.0 (the
 # "License"); you may not use this file except in compliance
 # with the License.  You may obtain a copy of the License at
-# 
+#
 #  http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing,
@@ -17,22 +17,22 @@
 # under the License.
 #
 
-pkg.name: nimble/transport/da1469x
-pkg.description: HCI transport for DA1469x
+pkg.name: babblesim/edtt/hci_transport
+pkg.description: Provides communication with EDTT bridge over named pipes
 pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
 pkg.homepage: "http://mynewt.apache.org/"
-pkg.keywords:
-    - ble
-    - bluetooth
-
 pkg.deps:
-    - "@apache-mynewt-nimble/nimble"
-    - "@apache-mynewt-nimble/nimble/transport/da1469x/cmac_driver"
+    - "@apache-mynewt-core/sys/console/stub"
+    - "@apache-mynewt-core/sys/log/stub"
+    - "@apache-mynewt-core/sys/stats/full"
     - "@apache-mynewt-core/kernel/os"
+    - nimble/controller
+
+# allows to override settings from nimble/transport
+pkg.subpriority: 1
 
 pkg.apis:
     - ble_transport
 
 pkg.init:
-    da1469x_ble_hci_init: 100
-    da1469x_ble_hci_cmac_init: 201
+    ble_hci_edtt_init: 249

babblesim/edtt/hci_transport/src/ble_hci_edtt.c

@@ -0,0 +1,813 @@
+/*
+ * Copyright (c) 2019 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <assert.h>
+#include <string.h>
+#include <stdint.h>
+#include <bs_tracing.h>
+#include "sysinit/sysinit.h"
+#include "syscfg/syscfg.h"
+#include "os/os_eventq.h"
+#include "controller/ble_ll.h"
+
+/* BLE */
+#include "nimble/ble.h"
+#include "nimble/hci_common.h"
+
+#include "bs_symbols.h"
+#include "bs_types.h"
+#include "time_machine.h"
+#include "ble_hci_edtt.h"
+#include "edtt_driver.h"
+#include "commands.h"
+
+#define BLE_HCI_EDTT_NONE        0x00
+#define BLE_HCI_EDTT_CMD         0x01
+#define BLE_HCI_EDTT_ACL         0x02
+#define BLE_HCI_EDTT_EVT         0x04
+
+#define BT_HCI_OP_VS_WRITE_BD_ADDR 0xFC06
+
+/* A packet for queueing EDTT/HCI commands and events */
+struct ble_hci_edtt_pkt {
+    struct os_event ev;
+    STAILQ_ENTRY(ble_hci_edtt_pkt) next;
+    uint32_t timestamp;
+    uint8_t type;
+    void *data;
+};
+
+static struct os_eventq edtt_q_svc;
+static struct os_eventq edtt_q_data;
+static struct os_eventq edtt_q_event;
+static uint8_t edtt_q_event_count;
+
+static uint16_t waiting_opcode;
+static enum commands_t waiting_response;
+
+static struct os_task edtt_poller_task;
+static struct os_task edtt_service_task;
+
+#if EDTT_HCI_LOGS
+extern unsigned int global_device_nbr;
+static FILE *fptr;
+
+static void
+log_hex_array(uint8_t *buf, int len)
+{
+    int i;
+    for (i = 0; i < len; i++) {
+        fprintf(fptr, "%02X ", buf[i]);
+    }
+}
+
+static void
+log_hci_cmd(uint16_t opcode, uint8_t *buf, int len)
+{
+    if (fptr) {
+        fprintf(fptr, "> %llu %02d %02d ", now, BLE_HCI_OCF(opcode), (BLE_HCI_OGF(opcode)));
+        log_hex_array(buf, len);
+        fputs("\n\n", fptr);
+        fflush(fptr);
+    }
+}
+
+static void
+log_hci_evt(struct ble_hci_ev *hdr)
+{
+    if (fptr) {
+        fprintf(fptr, "< %llu %02d ", now, hdr->opcode);
+        log_hex_array(hdr->data, hdr->length);
+        fputs("\n\n", fptr);
+        fflush(fptr);
+    }
+}
+
+static void
+log_hci_init()
+{
+    int flen = (int) strlen(MYNEWT_VAL(EDTT_HCI_LOG_FILE)) + 7;
+    char *fpath = (char *) calloc(flen, sizeof(char));
+    sprintf(fpath, "%s_%02d.log", MYNEWT_VAL(EDTT_HCI_LOG_FILE), global_device_nbr);
+    fptr = fopen(fpath, "w");
+    free(fpath);
+}
+#endif
+
+static int
+ble_hci_edtt_acl_tx(struct os_mbuf *om)
+{
+    struct ble_hci_edtt_pkt *pkt;
+
+    /* If this packet is zero length, just free it */
+    if (OS_MBUF_PKTLEN(om) == 0) {
+        os_mbuf_free_chain(om);
+        return 0;
+    }
+
+    pkt = calloc(1, sizeof(*pkt));
+    pkt->type = BLE_HCI_EDTT_ACL;
+    pkt->data = om;
+
+    os_eventq_put(&edtt_q_svc, &pkt->ev);
+
+    return 0;
+}
+
+static int
+ble_hci_edtt_cmdevt_tx(uint8_t *hci_ev, uint8_t edtt_type)
+{
+    struct ble_hci_edtt_pkt *pkt;
+
+    pkt = calloc(1, sizeof(*pkt));
+    pkt->type = edtt_type;
+    pkt->data = hci_ev;
+
+    os_eventq_put(&edtt_q_svc, &pkt->ev);
+
+    return 0;
+}
+
+/**
+ * Sends an HCI event from the controller to the host.
+ *
+ * @param cmd                   The HCI event to send.  This buffer must be
+ *                                  allocated via ble_hci_trans_buf_alloc().
+ *
+ * @return                      0 on success;
+ *                              A BLE_ERR_[...] error code on failure.
+ */
+int
+ble_transport_to_hs_evt(void *buf)
+{
+    return ble_hci_edtt_cmdevt_tx(buf, BLE_HCI_EDTT_EVT);
+}
+
+/**
+ * Sends ACL data from controller to host.
+ *
+ * @param om                    The ACL data packet to send.
+ *
+ * @return                      0 on success;
+ *                              A BLE_ERR_[...] error code on failure.
+ */
+int
+ble_transport_to_hs_acl(struct os_mbuf *om)
+{
+    return ble_hci_edtt_acl_tx(om);
+}
+
+/**
+ * @brief Clean out excess bytes from the input buffer
+ */
+static void
+read_excess_bytes(uint16_t size)
+{
+    if (size > 0) {
+        uint8_t buffer[size];
+
+        edtt_read((uint8_t *) buffer, size, EDTTT_BLOCK);
+        bs_trace_raw_time(3, "command size wrong! (%u extra bytes removed)", size);
+    }
+}
+
+/**
+ * @brief Provide an error response when an HCI command send failed
+ */
+static void
+error_response(int error)
+{
+    uint16_t response = waiting_response;
+    int le_error = error;
+    uint16_t size = sizeof(le_error);
+
+    edtt_write((uint8_t *) &response, sizeof(response), EDTTT_BLOCK);
+    edtt_write((uint8_t *) &size, sizeof(size), EDTTT_BLOCK);
+    edtt_write((uint8_t *) &le_error, sizeof(le_error), EDTTT_BLOCK);
+    waiting_response = CMD_NOTHING;
+    waiting_opcode = 0;
+}
+
+/**
+ * @brief Allocate buffer for HCI command, fill in parameters and send the
+ * command
+ */
+static int
+send_hci_cmd_to_ctrl(uint16_t opcode, uint8_t param_len, uint16_t response) {
+    struct ble_hci_cmd *buf;
+    int err = 0;
+    waiting_response = response;
+    waiting_opcode = opcode;
+
+    buf = ble_transport_alloc_cmd();
+    if (buf != NULL) {
+        buf->opcode = opcode;
+        buf->length = param_len;
+
+        if (param_len) {
+            edtt_read((uint8_t *) buf->data, param_len, EDTTT_BLOCK);
+        }
+
+#if EDTT_HCI_LOGS
+        log_hci_cmd(opcode, buf->data, param_len);
+#endif
+
+        err = ble_transport_to_ll_cmd(buf);
+        if (err) {
+            ble_transport_free(buf);
+            bs_trace_raw_time(3, "Failed to send HCI command %d (err %d)", opcode, err);
+            error_response(err);
+        }
+    } else {
+        bs_trace_raw_time(3, "Failed to create buffer for HCI command 0x%04x", opcode);
+        error_response(-1);
+    }
+    return err;
+}
+
+/**
+ * @brief Echo function - echo input received
+ */
+static void
+echo(uint16_t size)
+{
+    uint16_t response = CMD_ECHO_RSP;
+
+    edtt_write((uint8_t *) &response, sizeof(response), EDTTT_BLOCK);
+    edtt_write((uint8_t *) &size, sizeof(size), EDTTT_BLOCK);
+
+    if (size > 0) {
+        uint8_t buff[size];
+
+        edtt_read(buff, size, EDTTT_BLOCK);
+        edtt_write(buff, size, EDTTT_BLOCK);
+    }
+}
+
+/**
+ * @brief Handle Command Complete HCI event
+ */
+static void
+command_complete(struct ble_hci_ev *evt)
+{
+    struct ble_hci_ev_command_complete *evt_cc = (void *) evt->data;
+    uint16_t response = waiting_response;
+    uint16_t size = evt->length - sizeof(evt_cc->num_packets) - sizeof(evt_cc->opcode);
+
+    if (evt_cc->opcode == 0) {
+        /* ignore nop */
+    } else if (evt_cc->opcode == waiting_opcode) {
+        bs_trace_raw_time(9, "Command complete for 0x%04x", waiting_opcode);
+
+        edtt_write((uint8_t *) &response, sizeof(response), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &size, sizeof(size), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &evt_cc->status, sizeof(evt_cc->status), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &evt_cc->return_params, size - sizeof(evt_cc->status), EDTTT_BLOCK);
+        waiting_opcode = 0;
+    } else {
+        bs_trace_raw_time(5, "Not waiting for 0x(%04x) command status,"
+                             " expected 0x(%04x)", evt_cc->opcode, waiting_opcode);
+    }
+}
+
+/**
+ * @brief Handle Command Status HCI event
+ */
+static void
+command_status(struct ble_hci_ev *evt)
+{
+    struct ble_hci_ev_command_status *evt_cs = (void *) evt->data;
+    uint16_t opcode = evt_cs->opcode;
+    uint16_t response = waiting_response;
+    uint16_t size;
+
+    size = evt->length - sizeof(evt_cs->num_packets) - sizeof(evt_cs->opcode);
+
+    if (opcode == waiting_opcode) {
+        bs_trace_raw_time(9, "Command status for 0x%04x", waiting_opcode);
+
+        edtt_write((uint8_t *) &response, sizeof(response), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &size, sizeof(size), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &evt_cs->status, sizeof(evt_cs->status), EDTTT_BLOCK);
+        edtt_write((uint8_t *) &evt_cs->num_packets, size - sizeof(evt_cs->status), EDTTT_BLOCK);
+        waiting_opcode = 0;
+    } else {
+        bs_trace_raw_time(5, "Not waiting for 0x(%04x) command status,"
+                             " expected 0x(%04x)", opcode, waiting_opcode);
+    }
+}
+
+static void
+free_data(struct ble_hci_edtt_pkt *pkt)
+{
+    assert(pkt);
+    os_mbuf_free_chain(pkt->data);
+    free(pkt);
+}
+
+static void
+free_event(struct ble_hci_edtt_pkt *pkt)
+{
+    assert(pkt);
+    ble_transport_free(pkt->data);
+    free(pkt);
+}
+
+/**
+ * @brief Allocate and store an event in the event queue
+ */
+static struct ble_hci_edtt_pkt *
+queue_event(struct ble_hci_ev *evt)
+{
+    struct ble_hci_edtt_pkt *pkt;
+
+    pkt = calloc(1, sizeof(*pkt));
+    assert(pkt);
+    pkt->timestamp = tm_get_hw_time();
+    pkt->type = BLE_HCI_EDTT_EVT;
+    pkt->data = evt;
+
+    os_eventq_put(&edtt_q_event, &pkt->ev);
+    edtt_q_event_count++;
+
+    return pkt;
+}
+
+static struct ble_hci_edtt_pkt *
+queue_data(struct os_mbuf *om)
+{
+    struct ble_hci_edtt_pkt *pkt;
+
+    pkt = calloc(1, sizeof(*pkt));
+    assert(pkt);
+    pkt->timestamp = tm_get_hw_time();
+    pkt->type = BLE_HCI_EDTT_ACL;
+    pkt->data = om;
+
+    os_eventq_put(&edtt_q_data, &pkt->ev);
+
+    return pkt;
+}
+
+
+static void *
+dup_complete_evt(void *evt)
+{
+    struct ble_hci_ev *evt_copy;
+
+    /* max evt size is always 257 */
+    evt_copy = ble_transport_alloc_evt(0);
+    memcpy(evt_copy, evt, 257);
+    ble_transport_free(evt);
+
+    return evt_copy;
+}
+
+/**
+ * @brief Thread to service events and ACL data packets from the HCI input queue
+ */
+static void
+service_events(void *arg)
+{
+    struct ble_hci_edtt_pkt *pkt;
+    struct ble_hci_ev *evt;
+    struct ble_hci_ev_num_comp_pkts *evt_ncp;
+
+    while (1) {
+        pkt = (void *)os_eventq_get(&edtt_q_svc);
+
+        if (pkt->type == BLE_HCI_EDTT_EVT) {
+            evt = (void *)pkt->data;
+
+#if EDTT_HCI_LOGS
+            log_hci_evt(hdr);
+#endif
+
+            /* Prepare and send EDTT events */
+            switch (evt->opcode) {
+            case BLE_HCI_EVCODE_COMMAND_COMPLETE:
+                evt = dup_complete_evt(evt);
+                queue_event(evt);
+                command_complete(evt);
+                break;
+            case BLE_HCI_EVCODE_COMMAND_STATUS:
+                evt = dup_complete_evt(evt);
+                queue_event(evt);
+                command_status(evt);
+                break;
+            case BLE_HCI_EVCODE_NUM_COMP_PKTS:
+                evt_ncp = (void *)evt->data;
+                /* This should always be true for NimBLE LL */
+                assert(evt_ncp->count == 1);
+                if (evt_ncp->completed[0].packets == 0) {
+                    /* Discard, because EDTT does not like it */
+                    ble_transport_free(evt);
+                } else {
+                    queue_event(evt);
+                }
+                break;
+            case BLE_HCI_OPCODE_NOP:
+                /* Ignore noop bytes from Link layer */
+                ble_transport_free(evt);
+                break;
+            default:
+                /* Queue HCI events. We will send them to EDTT
+                 * on CMD_GET_EVENT_REQ. */
+                queue_event(evt);
+            }
+        } else if (pkt->type == BLE_HCI_EDTT_ACL) {
+            queue_data(pkt->data);
+        }
+
+        free(pkt);
+    }
+}
+
+/**
+ * @brief Flush all HCI events from the input-copy queue
+ */
+static void
+flush_events(uint16_t size)
+{
+    uint16_t response = CMD_FLUSH_EVENTS_RSP;
+    struct ble_hci_edtt_pkt *pkt;
+
+    while ((pkt = (void *)os_eventq_get_no_wait(&edtt_q_event))) {
+        free_event(pkt);
+        edtt_q_event_count--;
+    }
+    read_excess_bytes(size);
+    size = 0;
+
+    edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
+    edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+}
+
+/**
+ * @brief Get next available HCI event from the input-copy queue
+ */
+static void
+get_event(uint16_t size)
+{
+    uint16_t response = CMD_GET_EVENT_RSP;
+    struct ble_hci_edtt_pkt *pkt;
+    struct ble_hci_ev *evt;
+
+    read_excess_bytes(size);
+    size = 0;
+
+    edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
+    pkt = (void*)os_eventq_get(&edtt_q_event);
+    if (pkt) {
+        evt = pkt->data;
+        size = sizeof(pkt->timestamp) + sizeof(*evt) + evt->length;
+
+        edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+        edtt_write((uint8_t *)&pkt->timestamp, sizeof(pkt->timestamp), EDTTT_BLOCK);
+        edtt_write((uint8_t *)evt, sizeof(*evt) + evt->length, EDTTT_BLOCK);
+
+        free_event(pkt);
+
+        edtt_q_event_count--;
+    } else {
+        edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+    }
+}
+
+/**
+ * @brief Get next available HCI events from the input-copy queue
+ */
+static void
+get_events(uint16_t size)
+{
+    uint16_t response = CMD_GET_EVENT_RSP;
+    struct ble_hci_edtt_pkt *pkt;
+    struct ble_hci_ev *evt;
+    uint8_t count = edtt_q_event_count;
+
+    read_excess_bytes(size);
+    size = 0;
+
+    edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
+    edtt_write((uint8_t *)&count, sizeof(count), EDTTT_BLOCK);
+
+    while (count--) {
+        pkt = (void *)os_eventq_get_no_wait(&edtt_q_event);
+        assert(pkt);
+        evt = pkt->data;
+        size = sizeof(pkt->timestamp) + sizeof(*evt) + evt->length;
+
+        edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+        edtt_write((uint8_t *)&pkt->timestamp, sizeof(pkt->timestamp), EDTTT_BLOCK);
+        edtt_write((uint8_t *)evt, sizeof(*evt) + evt->length, EDTTT_BLOCK);
+
+        free_event(pkt);
+
+        edtt_q_event_count--;
+    }
+}
+
+/**
+ * @brief Check whether an HCI event is available in the input-copy queue
+ */
+static void
+has_event(uint16_t size)
+{
+    struct has_event_resp {
+        uint16_t response;
+        uint16_t size;
+        uint8_t count;
+    } __attribute__((packed));
+    struct has_event_resp le_response = {
+        .response = CMD_HAS_EVENT_RSP,
+        .size = 1,
+        .count = edtt_q_event_count
+    };
+
+    if (size > 0) {
+        read_excess_bytes(size);
+    }
+    edtt_write((uint8_t *) &le_response, sizeof(le_response), EDTTT_BLOCK);
+}
+
+/**
+ * @brief Flush all ACL Data Packages from the input-copy queue
+ */
+static void
+le_flush_data(uint16_t size)
+{
+    uint16_t response = CMD_LE_FLUSH_DATA_RSP;
+    struct ble_hci_edtt_pkt *pkt;
+
+    while ((pkt = (void *)os_eventq_get_no_wait(&edtt_q_data))) {
+        free_data(pkt);
+    }
+
+    read_excess_bytes(size);
+    size = 0;
+
+    edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
+    edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+}
+
+/**
+ * @brief Check whether an ACL Data Package is available in the input-copy queue
+ */
+static void
+le_data_ready(uint16_t size)
+{
+    struct has_data_resp {
+        uint16_t response;
+        uint16_t size;
+        uint8_t empty;
+    } __attribute__((packed));
+    struct has_data_resp le_response = {
+        .response = CMD_LE_DATA_READY_RSP,
+        .size = 1,
+        .empty = 0
+    };
+
+    if (size > 0) {
+        read_excess_bytes(size);
+    }
+
+    /* There's no API to check if eventq is empty but a little hack will do... */
+    if (edtt_q_data.evq_list.stqh_first == NULL) {
+        le_response.empty = 1;
+    }
+
+    edtt_write((uint8_t *) &le_response, sizeof(le_response), EDTTT_BLOCK);
+}
+
+/**
+ * @brief Get next available HCI Data Package from the input-copy queue
+ */
+static void
+le_data_read(uint16_t size)
+{
+    uint16_t response = CMD_LE_DATA_READ_RSP;
+    struct ble_hci_edtt_pkt *pkt;
+    struct os_mbuf *om;
+
+    read_excess_bytes(size);
+    size = 0;
+
+    edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
+    pkt = (void *)os_eventq_get(&edtt_q_data);
+    if (pkt) {
+        om = pkt->data;
+
+        size = sizeof(pkt->timestamp) + OS_MBUF_PKTLEN(om);
+
+        edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+        edtt_write((uint8_t *)&pkt->timestamp, sizeof(pkt->timestamp), EDTTT_BLOCK);
+
+        while (om != NULL) {
+            edtt_write((uint8_t *)om->om_data, om->om_len, EDTTT_BLOCK);
+            om = SLIST_NEXT(om, om_next);
+        }
+
+        free_data(pkt);
+    } else {
+        edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
+    }
+}
+
+/**
+ * @brief Write ACL Data Package to the Controller
+ */
+static void
+le_data_write(uint16_t size)
+{
+    struct data_write_resp {
+        uint16_t code;
+        uint16_t size;
+        uint8_t status;
+    } __attribute__((packed));
+    struct data_write_resp response = {
+        .code = CMD_LE_DATA_WRITE_RSP,
+        .size = 1,
+        .status = 0
+    };
+    struct os_mbuf *om;
+    struct hci_data_hdr hdr;
+    int err;
+
+    if (size >= sizeof(hdr)) {
+        om = ble_transport_alloc_acl_from_hs();
+        if (om) {
+            edtt_read((void *)&hdr, sizeof(hdr), EDTTT_BLOCK);
+            size -= sizeof(hdr);
+
+            os_mbuf_append(om, &hdr, sizeof(hdr));
+
+            if (size >= hdr.hdh_len) {
+                /* Don't care, we have plenty of stack */
+                uint8_t tmp[hdr.hdh_len];
+
+                edtt_read(tmp, hdr.hdh_len, EDTTT_BLOCK);
+                size -= hdr.hdh_len;
+
+                os_mbuf_append(om, tmp, hdr.hdh_len);
+            }
+
+            err = ble_transport_to_ll_acl(om);
+            if (err) {
+                bs_trace_raw_time(3, "Failed to send ACL Data (err %d)", err);
+            }
+        } else {
+            err = -2; /* Failed to allocate data buffer */
+            bs_trace_raw_time(3, "Failed to create buffer for ACL Data.");
+        }
+    } else {
+        /* Size too small for header (handle and data length) */
+        err = -3;
+    }
+    read_excess_bytes(size);
+
+    response.status = err;
+    edtt_write((uint8_t *) &response, sizeof(response), EDTTT_BLOCK);
+}
+
+static void
+fake_write_bd_addr_cc()
+{
+    struct ble_hci_ev_command_complete *ev;
+    struct ble_hci_ev *hci_ev;
+    waiting_opcode = BT_HCI_OP_VS_WRITE_BD_ADDR;
+    waiting_response = CMD_WRITE_BD_ADDR_RSP;
+
+    hci_ev = ble_transport_alloc_evt(0);
+    if (hci_ev) {
+        hci_ev->opcode = BLE_HCI_EVCODE_COMMAND_COMPLETE;
+        hci_ev->length = sizeof(*ev);
+        ev = (void *) hci_ev->data;
+
+        ev->num_packets = 1;
+        ev->opcode = waiting_opcode;
+        ev->status = 0;
+        ble_hci_edtt_cmdevt_tx((uint8_t *) hci_ev, BLE_HCI_EDTT_EVT);
+    }
+}
+
+/* Reads and executes EDTT commands. */
+static void
+edtt_poller(void *arg) {
+    uint16_t command;
+    uint16_t size;
+    uint16_t opcode;
+    uint8_t bdaddr[6];
+
+    /* Initialize HCI command opcode and response variables */
+    waiting_opcode = 0;
+    waiting_response = CMD_NOTHING;
+    edtt_q_event_count = 0;
+
+    /* Initialize and start EDTT system */
+    enable_edtt_mode();
+    set_edtt_autoshutdown(true);
+    edtt_start();
+
+#if EDTT_HCI_LOGS
+    log_hci_init();
+#endif
+
+    while (1) {
+        edtt_read((uint8_t *) &command, sizeof(command), EDTTT_BLOCK);
+        edtt_read((uint8_t *) &size, sizeof(size), EDTTT_BLOCK);
+
+        bs_trace_raw_time(4, "command 0x%04X received (size %u) "
+                             "events=%u\n",
+                          command, size, edtt_q_event_count);
+
+        switch (command) {
+            case CMD_ECHO_REQ:
+                echo(size);
+                break;
+            case CMD_FLUSH_EVENTS_REQ:
+                flush_events(size);
+                break;
+            case CMD_HAS_EVENT_REQ:
+                has_event(size);
+                break;
+            case CMD_GET_EVENT_REQ: {
+                uint8_t multiple;
+
+                edtt_read((uint8_t *) &multiple, sizeof(multiple), EDTTT_BLOCK);
+                if (multiple)
+                    get_events(--size);
+                else
+                    get_event(--size);
+            }
+                break;
+            case CMD_LE_FLUSH_DATA_REQ:
+                le_flush_data(size);
+                break;
+            case CMD_LE_DATA_READY_REQ:
+                le_data_ready(size);
+                break;
+            case CMD_LE_DATA_WRITE_REQ:
+                le_data_write(size);
+                break;
+            case CMD_LE_DATA_READ_REQ:
+                le_data_read(size);
+                break;
+            case CMD_WRITE_BD_ADDR_REQ:
+                edtt_read((uint8_t *) &opcode, sizeof(opcode), EDTTT_BLOCK);
+
+                if (opcode == BT_HCI_OP_VS_WRITE_BD_ADDR) {
+                    edtt_read((uint8_t *) &bdaddr, sizeof(bdaddr), EDTTT_BLOCK);
+                    ble_ll_set_public_addr(bdaddr);
+                    fake_write_bd_addr_cc();
+                } else {
+                    assert(0);
+                }
+                break;
+            default:
+                if (size >= 2) {
+                    edtt_read((uint8_t *) &opcode, sizeof(opcode), EDTTT_BLOCK);
+                    send_hci_cmd_to_ctrl(opcode, size - 2, command + 1);
+                }
+        }
+    }
+}
+
+int
+edtt_init(void)
+{
+    os_stack_t dummy_stack;
+    int rc;
+
+    rc = os_task_init(&edtt_poller_task, "edttpoll", edtt_poller, NULL,
+                      MYNEWT_VAL(EDTT_POLLER_PRIO), OS_WAIT_FOREVER,
+                      &dummy_stack, 1);
+    assert(rc == 0);
+
+    rc = os_task_init(&edtt_service_task, "edttsvc", service_events, NULL,
+                      MYNEWT_VAL(EDTT_POLLER_PRIO) + 1, OS_WAIT_FOREVER,
+                      &dummy_stack, 1);
+    assert(rc == 0);
+
+    return 0;
+}
+
+/**
+ * Initializes the EDTT HCI transport module.
+ *
+ * @return                      0 on success;
+ *                              A BLE_ERR_[...] error code on failure.
+ */
+void
+ble_hci_edtt_init(void)
+{
+    /* Ensure this function only gets called by sysinit. */
+    SYSINIT_ASSERT_ACTIVE();
+
+    os_eventq_init(&edtt_q_svc);
+    os_eventq_init(&edtt_q_event);
+    os_eventq_init(&edtt_q_data);
+}

babblesim/edtt/hci_transport/src/edtt_driver_bsim.c

@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2019 Oticon A/S
+ * Copyright (c) 2021 Codecoup
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "bs_tracing.h"
+#include "bs_oswrap.h"
+#include "bs_pc_base_fifo_user.h"
+
+#include <time_machine.h>
+#include "edtt_driver.h"
+#include "os/os_sched.h"
+
+/* Recheck if something arrived from the EDTT every 5ms */
+#define EDTT_IF_RECHECK_DELTA 5 /* ms */
+
+/* We want the runs to be deterministic => we want to resync with the Phy
+ * before we retry any read so the bridge device may also run
+ */
+#define EDTT_SIMU_RESYNC_TIME_WITH_EDTT \
+	(EDTT_IF_RECHECK_DELTA * 1000 - 1)
+
+static int edtt_mode_enabled = 0;
+
+/* In this mode, when the EDTTool closes the FIFO we automatically terminate
+ * this simulated device. If false, we just continue running
+ */
+static int edtt_autoshutdown;
+
+#define TO_DEVICE  0
+#define TO_BRIDGE 1
+static int fifo[2] = { -1, -1 };
+static char *fifo_path[2] = {NULL, NULL};
+
+extern unsigned int global_device_nbr;
+
+static void edttd_clean_up(void);
+static void edptd_create_fifo_if(void);
+static int fifo_low_level_read(uint8_t *bufptr, int size);
+
+bool edtt_start(void)
+{
+	if (edtt_mode_enabled == false) {
+		/* otherwise we don't try to open the EDTT interface */
+		return true;
+	}
+
+	edptd_create_fifo_if();
+
+	extern void tm_set_phy_max_resync_offset(uint64_t offset_in_us);
+	tm_set_phy_max_resync_offset(EDTT_SIMU_RESYNC_TIME_WITH_EDTT);
+	return true;
+}
+
+bool edtt_stop(void)
+{
+	if (edtt_mode_enabled == false) {
+		/* otherwise we don't try to open the EDTT interface */
+		return true;
+	}
+
+	bs_trace_raw(9, "EDTTT: %s called\n", __func__);
+	edttd_clean_up();
+	edtt_mode_enabled = false;
+	return true;
+}
+
+static void
+print_hex_array(int lvl, uint8_t *buf, int len)
+{
+    char str[2*len];
+    char *p = str;
+    int i;
+    for (i = 0; i < len; i++) {
+        if (i > 0) *p++ = ' ';
+        sprintf(p++, "%02X", buf[i]);
+    }
+    *p = '\n';
+    bs_trace_raw(lvl, str);
+}
+
+/**
+ * Attempt to read size bytes thru the EDTT IF into the buffer <*ptr>
+ * <flags> can be set to EDTTT_BLOCK or EDTTT_NONBLOCK
+ *
+ * If set to EDTTT_BLOCK it will block the calling thread until <size>
+ * bytes have been read or the interface has been closed.
+ * If set to EDTTT_NONBLOCK it returns as soon as there is no more data to be
+ * read
+ *
+ * Returns the amount of read bytes, or -1 on error
+ */
+int edtt_read(uint8_t *ptr, size_t size, int flags)
+{
+    uint8_t *buf = ptr;
+
+	if (edtt_mode_enabled == false) {
+		return -1;
+	}
+
+	bs_trace_raw_time(8, "EDTT: Asked to read %i bytes\n", size);
+	int read = 0;
+
+	while (size > 0) {
+		int received_bytes;
+
+		received_bytes = fifo_low_level_read(ptr, size);
+		if (received_bytes < 0) {
+			return -1;
+		} else if (received_bytes > 0) {
+			size -= received_bytes;
+			ptr += received_bytes;
+			read += received_bytes;
+		} else {
+			if (flags & EDTTT_BLOCK) {
+				bs_trace_raw_time(9, "EDTT: No enough data yet,"
+						"sleeping for %i ms\n",
+						EDTT_IF_RECHECK_DELTA);
+                os_sched_sleep(os_sched_get_current_task(),
+                               os_time_ms_to_ticks32(EDTT_IF_RECHECK_DELTA));
+                os_sched(NULL);
+			} else {
+				bs_trace_raw_time(9, "EDTT: No enough data yet,"
+						"returning\n");
+				break;
+			}
+		}
+    }
+
+    if (read > 0) {
+        bs_trace_raw_time(8, "Read %i bytes:\n", read);
+        print_hex_array(8, buf, read);
+    }
+	return read;
+}
+
+/**
+ * Write <size> bytes from <ptr> toward the EDTTool
+ *
+ * <flags> is ignored in this driver, all writes to the tool are
+ * instantaneous
+ */
+int edtt_write(uint8_t *ptr, size_t size, int flags)
+{
+	if (edtt_mode_enabled == false) {
+		return -1;
+	}
+
+	bs_trace_raw_time(6, "EDTT: Asked to write %i bytes: ", size);
+    print_hex_array(6, ptr, size);
+
+	if (write(fifo[TO_BRIDGE], ptr, size) != size) {
+		if (errno == EPIPE) {
+			bs_trace_error_line("EDTT IF suddenly closed by other "
+					    "end\n");
+		}
+		if ((errno == EAGAIN) || (errno == EWOULDBLOCK)) {
+			bs_trace_error_line("EDTT IF to bridge filled up (FIFO "
+					    "size needs to be increased)\n");
+		}
+		bs_trace_error_line("EDTT IF: Unexpected error on write\n");
+	}
+	return size;
+}
+
+/*
+ * Applications may want to enable the EDTT interface only in some
+ * cases. By default it is not enabled in this driver. This function
+ * must be called once before starting it to do so
+ */
+void enable_edtt_mode(void)
+{
+	edtt_mode_enabled = true;
+}
+
+/**
+ * Automatically terminate this device execution once the EDTTool disconnects
+ */
+void set_edtt_autoshutdown(bool Mode)
+{
+	edtt_autoshutdown = Mode;
+}
+
+static void edptd_create_fifo_if(void)
+{
+	int flags;
+
+	bs_trace_raw_time(9, "Bringing EDTT IF up (waiting for other side)\n");
+
+	if (pb_com_path == NULL) {
+		bs_trace_error_line("Not connected to Phy."
+				    "EDTT IF cannot be brough up\n");
+	}
+
+	/* At this point we have connected to the Phy so the COM folder does
+	 * already exist
+	 * also SIGPIPE is already ignored
+	 */
+
+	fifo_path[TO_DEVICE] = (char *)bs_calloc(pb_com_path_length + 30,
+						 sizeof(char));
+	fifo_path[TO_BRIDGE] = (char *)bs_calloc(pb_com_path_length + 30,
+						 sizeof(char));
+	sprintf(fifo_path[TO_DEVICE], "%s/Device%i.PTTin",
+		pb_com_path, global_device_nbr);
+	sprintf(fifo_path[TO_BRIDGE], "%s/Device%i.PTTout",
+		pb_com_path, global_device_nbr);
+
+	if ((pb_create_fifo_if_not_there(fifo_path[TO_DEVICE]) != 0)
+		|| (pb_create_fifo_if_not_there(fifo_path[TO_BRIDGE]) != 0)) {
+		bs_trace_error_line("Couldnt create FIFOs for EDTT IF\n");
+	}
+
+	/* we block here until the bridge opens its end */
+	fifo[TO_BRIDGE] = open(fifo_path[TO_BRIDGE], O_WRONLY);
+	if (fifo[TO_BRIDGE] == -1) {
+		bs_trace_error_line("Couldn't create FIFOs for EDTT IF\n");
+	}
+
+	flags = fcntl(fifo[TO_BRIDGE], F_GETFL);
+	flags |= O_NONBLOCK;
+	fcntl(fifo[TO_BRIDGE], F_SETFL, flags);
+
+	/* we will block here until the bridge opens its end */
+	fifo[TO_DEVICE] = open(fifo_path[TO_DEVICE], O_RDONLY);
+	if (fifo[TO_DEVICE] == -1) {
+		bs_trace_error_line("Couldn't create FIFOs for EDTT IF\n");
+	}
+
+	flags = fcntl(fifo[TO_DEVICE], F_GETFL);
+	flags |= O_NONBLOCK;
+	fcntl(fifo[TO_DEVICE], F_SETFL, flags);
+}
+
+static void edttd_clean_up(void)
+{
+	for (int dir = TO_DEVICE ; dir <= TO_BRIDGE ; dir++) {
+		if (fifo_path[dir]) {
+			if (fifo[dir] != -1) {
+				close(fifo[dir]);
+				remove(fifo_path[dir]);
+				fifo[dir] = -1;
+			}
+			free(fifo_path[dir]);
+			fifo_path[dir] = NULL;
+		}
+	}
+	if (pb_com_path != NULL) {
+		rmdir(pb_com_path);
+	}
+}
+
+static int fifo_low_level_read(uint8_t *bufptr, int size)
+{
+	int received_bytes = read(fifo[TO_DEVICE], bufptr, size);
+
+	if ((received_bytes == -1) && (errno == EAGAIN)) {
+		return 0;
+	} else if (received_bytes == EOF || received_bytes == 0) {
+		/*The FIFO was closed by the bridge*/
+		if (edtt_autoshutdown) {
+			bs_trace_raw_time(3, "EDTT: FIFO closed "
+					"(ptt_autoshutdown==true) =>"
+					" Terminate\n");
+			edttd_clean_up();
+			bs_trace_exit_line("\n");
+		} else {
+			bs_trace_raw_time(3, "EDTT: FIFO closed "
+					"(ptt_autoshutdown==false) => We close "
+					"the FIFOs and move on\n");
+			edttd_clean_up();
+			edtt_mode_enabled = false;
+			return -1;
+		}
+	} else if (received_bytes == -1) {
+		bs_trace_error_line("EDTT: Unexpected error\n");
+	}
+
+	return received_bytes;
+}

babblesim/edtt/hci_transport/syscfg.yml

@@ -0,0 +1,40 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+    EDTT_HCI_LOG_FILE:
+        description: >
+            Path to the HCI log file. Skip file extension
+            because device id and .log will be appended.
+        value: "hci_logs"
+    EDTT_HCI_LOGS:
+        description: Turn on HCI commands logging.
+        value: 0
+    EDTT_POLLER_PRIO:
+        description: 'Priority of native EDTT poller task.'
+        type: task_priority
+        value: 2
+
+syscfg.vals:
+    BLE_TRANSPORT_ACL_COUNT: 32
+    BLE_TRANSPORT_EVT_COUNT: 64
+
+syscfg.restrictions:
+    - BLE_TRANSPORT_HS == "custom"
+    - BLE_TRANSPORT_LL == "native"

porting/targets/dummy_bsp/bsp.yml → babblesim/hw/bsp/nrf52_bsim/bsp.yml

@@ -17,11 +17,15 @@
 # under the License.
 #
 
-bsp.name: "dummy"
-bsp.url:
-bsp.maker:
-bsp.arch: dummy
+bsp.name: "nRF52 DK"
+bsp.url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK
+bsp.maker: "Nordic Semiconductor"
+bsp.arch: bsim_arch
 bsp.compiler: "@apache-mynewt-core/compiler/sim"
+bsp.downloadscript: "hw/bsp/nrf52_bsim/nordic_pca10040_download.sh"
+bsp.debugscript: "hw/bsp/nrf52_bsim/nordic_pca10040_debug.sh"
+bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nrf52_bsim/nordic_pca10040_download.cmd"
+bsp.debugscript.WINDOWS.OVERWRITE: "hw/bsp/nrf52_bsim/nordic_pca10040_debug.cmd"
 
 bsp.flash_map:
     areas:
@@ -29,28 +33,28 @@ bsp.flash_map:
         FLASH_AREA_BOOTLOADER:
             device: 0
             offset: 0x00000000
-            size: 32kB
+            size: 16kB
         FLASH_AREA_IMAGE_0:
             device: 0
-            offset: 0x0000c000
-            size: 472kB
+            offset: 0x00008000
+            size: 232kB
         FLASH_AREA_IMAGE_1:
             device: 0
-            offset: 0x00082000
-            size: 472kB
+            offset: 0x00042000
+            size: 232kB
         FLASH_AREA_IMAGE_SCRATCH:
             device: 0
-            offset: 0x000f8000
-            size: 16kB
+            offset: 0x0007c000
+            size: 4kB
 
         # User areas.
         FLASH_AREA_REBOOT_LOG:
             user_id: 0
             device: 0
-            offset: 0x00008000
+            offset: 0x00004000
             size: 16kB
         FLASH_AREA_NFFS:
             user_id: 1
             device: 0
-            offset: 0x000fc000
-            size: 16kB
+            offset: 0x0007d000
+            size: 12kB

babblesim/hw/bsp/nrf52_bsim/include/bsp/bsp.h

@@ -0,0 +1,91 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#include "os/mynewt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core   __attribute__((section(".data.core")))
+#define sec_bss_core    __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t         sec_bss_nz_core
+
+extern uint8_t _ram_start;
+#define RAM_SIZE        0x10000
+
+/* LED pins */
+#define LED_1           (17)
+#define LED_2           (18)
+#define LED_3           (19)
+#define LED_4           (20)
+#define LED_BLINK_PIN   (LED_1)
+
+/* Buttons */
+#define BUTTON_1 (13)
+#define BUTTON_2 (14)
+#define BUTTON_3 (15)
+#define BUTTON_4 (16)
+
+/* Arduino pins */
+#define ARDUINO_PIN_D0      11
+#define ARDUINO_PIN_D1      12
+#define ARDUINO_PIN_D2      13
+#define ARDUINO_PIN_D3      14
+#define ARDUINO_PIN_D4      15
+#define ARDUINO_PIN_D5      16
+#define ARDUINO_PIN_D6      17
+#define ARDUINO_PIN_D7      18
+#define ARDUINO_PIN_D8      19
+#define ARDUINO_PIN_D9      20
+#define ARDUINO_PIN_D10     22
+#define ARDUINO_PIN_D11     23
+#define ARDUINO_PIN_D12     24
+#define ARDUINO_PIN_D13     25
+#define ARDUINO_PIN_A0      3
+#define ARDUINO_PIN_A1      4
+#define ARDUINO_PIN_A2      28
+#define ARDUINO_PIN_A3      29
+#define ARDUINO_PIN_A4      30
+#define ARDUINO_PIN_A5      31
+
+#define ARDUINO_PIN_RX      ARDUINO_PIN_D0
+#define ARDUINO_PIN_TX      ARDUINO_PIN_D1
+
+#define ARDUINO_PIN_SCL     27
+#define ARDUINO_PIN_SDA     26
+
+#define ARDUINO_PIN_SCK     ARDUINO_PIN_D13
+#define ARDUINO_PIN_MOSI    ARDUINO_PIN_D11
+#define ARDUINO_PIN_MISO    ARDUINO_PIN_D12
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* H_BSP_H */

babblesim/hw/bsp/nrf52_bsim/include/os/os_arch.h

@@ -0,0 +1,64 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _OS_ARCH_ARM_H
+#define _OS_ARCH_ARM_H
+
+#include <stdint.h>
+#include "syscfg/syscfg.h"
+#include "mcu/cmsis_nvic.h"
+#include "mcu/cortex_m4.h"
+#include <irq_ctrl.h>
+#include "mcu/mcu_sim.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* CPU status register */
+typedef uint32_t os_sr_t;
+
+/* Stack element */
+typedef uint32_t os_stack_t;
+
+struct stack_frame;
+void os_arch_frame_init(struct stack_frame *sf);
+
+/* Stack sizes for common OS tasks */
+#define OS_SANITY_STACK_SIZE (2000)
+#if MYNEWT_VAL(OS_SYSVIEW)
+#define OS_IDLE_STACK_SIZE (80)
+#else
+#define OS_IDLE_STACK_SIZE (4000)
+#endif
+
+static inline int
+os_arch_in_isr(void)
+{
+	return hw_irq_ctrl_get_irq_status();
+}
+
+/* Include common arch definitions and APIs */
+#include "os/arch/common.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_ARCH_ARM_H */

babblesim/hw/bsp/nrf52_bsim/include/os/sim.h

@@ -0,0 +1,60 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_KERNEL_SIM_
+#define H_KERNEL_SIM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <setjmp.h>
+#include "os/mynewt.h"
+#include "mcu/mcu_sim.h"
+struct os_task;
+struct stack_frame;
+
+struct stack_frame {
+    int sf_mainsp;              /* stack on which main() is executing */
+    sigjmp_buf sf_jb;
+    struct os_task *sf_task;
+};
+
+void sim_task_start(struct stack_frame *sf, int rc);
+os_stack_t *sim_task_stack_init(struct os_task *t, os_stack_t *stack_top,
+                                int size);
+os_error_t sim_os_start(void);
+void sim_os_stop(void);
+os_error_t sim_os_init(void);
+void sim_ctx_sw(struct os_task *next_t);
+os_sr_t sim_save_sr(void);
+void sim_restore_sr(os_sr_t osr);
+int sim_in_critical(void);
+void sim_tick_idle(os_time_t ticks);
+int sig_block_irq_on();
+void sig_unblock_irq_off();
+
+uint8_t inner_main_clean_up(int exit_code);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

babblesim/hw/bsp/nrf52_bsim/nordic_pca10040_debug.cmd

@@ -0,0 +1,22 @@
+@rem
+@rem Licensed to the Apache Software Foundation (ASF) under one
+@rem or more contributor license agreements.  See the NOTICE file
+@rem distributed with this work for additional information
+@rem regarding copyright ownership.  The ASF licenses this file
+@rem to you under the Apache License, Version 2.0 (the
+@rem "License"); you may not use this file except in compliance
+@rem with the License.  You may obtain a copy of the License at
+@rem
+@rem  http://www.apache.org/licenses/LICENSE-2.0
+@rem
+@rem Unless required by applicable law or agreed to in writing,
+@rem software distributed under the License is distributed on an
+@rem "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+@rem KIND, either express or implied.  See the License for the
+@rem specific language governing permissions and limitations
+@rem under the License.
+@rem
+
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"

babblesim/hw/bsp/nrf52_bsim/nordic_pca10040_debug.sh

@@ -0,0 +1,45 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+#  - CORE_PATH is absolute path to @apache-mynewt-core
+#  - BSP_PATH is absolute path to hw/bsp/bsp_name
+#  - BIN_BASENAME is the path to prefix to target binary,
+#    .elf appended to name is the ELF file
+#  - FEATURES holds the target features string
+#  - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+#  - RESET set if target should be reset when attaching
+#  - NO_GDB set if we should not start gdb to debug
+#
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+if [ $# -gt 2 ]; then
+    SPLIT_ELF_NAME=$3.elf
+    # TODO -- this magic number 0x42000 is the location of the second image
+    # slot. we should either get this from a flash map file or somehow learn
+    # this from the image itself
+    EXTRA_GDB_CMDS="add-symbol-file $SPLIT_ELF_NAME 0x8000 -readnow"
+fi
+
+JLINK_DEV="nRF52"
+
+jlink_debug

babblesim/hw/bsp/nrf52_bsim/nordic_pca10040_download.cmd

@@ -0,0 +1,22 @@
+@rem
+@rem Licensed to the Apache Software Foundation (ASF) under one
+@rem or more contributor license agreements.  See the NOTICE file
+@rem distributed with this work for additional information
+@rem regarding copyright ownership.  The ASF licenses this file
+@rem to you under the Apache License, Version 2.0 (the
+@rem "License"); you may not use this file except in compliance
+@rem with the License.  You may obtain a copy of the License at
+@rem
+@rem  http://www.apache.org/licenses/LICENSE-2.0
+@rem
+@rem Unless required by applicable law or agreed to in writing,
+@rem software distributed under the License is distributed on an
+@rem "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+@rem KIND, either express or implied.  See the License for the
+@rem specific language governing permissions and limitations
+@rem under the License.
+@rem
+
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"

babblesim/hw/bsp/nrf52_bsim/nordic_pca10040_download.sh

@@ -0,0 +1,40 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# Called with following variables set:
+#  - CORE_PATH is absolute path to @apache-mynewt-core
+#  - BSP_PATH is absolute path to hw/bsp/bsp_name
+#  - BIN_BASENAME is the path to prefix to target binary,
+#    .elf appended to name is the ELF file
+#  - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+#  - FEATURES holds the target features string
+#  - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+#  - MFG_IMAGE is "1" if this is a manufacturing image
+#  - FLASH_OFFSET contains the flash offset to download to
+#  - BOOT_LOADER is set if downloading a bootloader
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+if [ "$MFG_IMAGE" ]; then
+    FLASH_OFFSET=0x0
+fi
+
+JLINK_DEV="nRF52"
+
+common_file_to_load
+jlink_load

babblesim/hw/bsp/nrf52_bsim/pkg.yml

@@ -0,0 +1,37 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/hw/bsp/nrf52_bsim
+pkg.type: bsp
+pkg.description: nRF52 on BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+
+pkg.cflags:
+    - '-DNRF52832_XXAA'
+    - '-DBABBLESIM'
+
+pkg.cflags.HARDFLOAT:
+    - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+    - "babblesim/core"
+    - "babblesim/hw/mcu/nordic/nrf52_bsim"
+    - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+    - "@apache-mynewt-nimble/nimble/controller"

babblesim/hw/bsp/nrf52_bsim/src/arch/bsim_arch/os_arch.c

@@ -0,0 +1,169 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#define _GNU_SOURCE
+#include <pthread.h>
+#include <syscfg/syscfg.h>
+#include <os/os_task.h>
+#include <hal/hal_os_tick.h>
+#include <irq_ctrl.h>
+
+static pthread_mutex_t bsim_ctx_sw_mutex = PTHREAD_MUTEX_INITIALIZER;
+static int bsim_pend_sv;
+
+struct task_info {
+    pthread_t tid;
+    pthread_cond_t cond;
+    void *arg;
+};
+
+static void *
+task_wrapper(void *arg)
+{
+    struct os_task *me = arg;
+    struct task_info *ti = me->t_arg;
+
+    pthread_mutex_lock(&bsim_ctx_sw_mutex);
+    if (g_current_task != me) {
+        pthread_cond_wait(&ti->cond, &bsim_ctx_sw_mutex);
+        assert(g_current_task == me);
+    }
+
+    me->t_func(ti->arg);
+
+    assert(0);
+}
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+    struct task_info *ti;
+    int err;
+
+    ti = calloc(1, sizeof(*ti));
+
+    pthread_cond_init(&ti->cond, NULL);
+    ti->arg = t->t_arg;
+    t->t_arg = ti;
+
+    err = pthread_create(&ti->tid, NULL, task_wrapper, t);
+    assert(err == 0);
+
+    pthread_setname_np(ti->tid, t->t_name);
+
+    return stack_top;
+}
+
+os_error_t
+os_arch_os_start(void)
+{
+    struct os_task *next_t;
+    struct task_info *ti;
+
+    os_tick_init(OS_TICKS_PER_SEC, 7);
+
+    next_t = os_sched_next_task();
+    assert(next_t);
+    os_sched_set_current_task(next_t);
+
+    g_os_started = 1;
+
+    ti = next_t->t_arg;
+    pthread_cond_signal(&ti->cond);
+
+    return 0;
+}
+
+os_error_t
+os_arch_os_init(void)
+{
+    STAILQ_INIT(&g_os_task_list);
+    TAILQ_INIT(&g_os_run_list);
+    TAILQ_INIT(&g_os_sleep_list);
+
+    os_init_idle_task();
+
+    return OS_OK;
+}
+
+void
+os_arch_ctx_sw(struct os_task *next_t)
+{
+    os_sched_ctx_sw_hook(next_t);
+    bsim_pend_sv = 1;
+}
+
+static void
+do_ctx_sw(void)
+{
+    struct os_task *next_t;
+    struct os_task *me;
+    struct task_info *ti, *next_ti;
+
+    next_t = os_sched_next_task();
+    assert(next_t);
+
+    bsim_pend_sv = 0;
+
+    assert(g_current_task);
+    me = g_current_task;
+    ti = me->t_arg;
+
+    if (me == next_t) {
+        return;
+    }
+
+    g_current_task = next_t;
+    next_ti = g_current_task->t_arg;
+
+    pthread_cond_signal(&next_ti->cond);
+    pthread_cond_wait(&ti->cond, &bsim_ctx_sw_mutex);
+    assert(g_current_task == me);
+}
+
+os_sr_t
+os_arch_save_sr(void)
+{
+    return hw_irq_ctrl_change_lock(1);
+}
+
+void
+os_arch_restore_sr(os_sr_t osr)
+{
+    hw_irq_ctrl_change_lock(osr);
+
+    if (!osr && bsim_pend_sv) {
+        do_ctx_sw();
+    }
+}
+
+int
+os_arch_in_critical(void)
+{
+    return hw_irq_ctrl_get_current_lock();
+}
+
+void
+__assert_func(const char *file, int line, const char *func, const char *e)
+{
+#if MYNEWT_VAL(OS_ASSERT_CB)
+    os_assert_cb();
+#endif
+    _Exit(1);
+}

babblesim/hw/bsp/nrf52_bsim/src/arch/bsim_arch/startup_nrf52_bsim.c

@@ -0,0 +1,231 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "nrf.h"
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Weak symbol reference. */
+#define WEAK        __attribute__ ((weak))
+
+/**************************************************************************************************
+  Functions
+**************************************************************************************************/
+
+extern void SystemInit(void);
+static void SystemDefaultHandler(void);
+
+/* Core vectors. */
+void WEAK Reset_Handler(void);
+void WEAK NMI_Handler(void);
+void WEAK HardFault_Handler(void);
+void WEAK MemoryManagement_Handler(void);
+void WEAK BusFault_Handler(void);
+void WEAK UsageFault_Handler(void);
+void WEAK SVC_Handler(void);
+void WEAK DebugMon_Handler(void);
+void WEAK PendSV_Handler(void);
+void WEAK SysTick_Handler(void);
+void WEAK POWER_CLOCK_IRQHandler(void);
+void WEAK RADIO_IRQHandler(void);
+void WEAK UARTE0_UART0_IRQHandler(void);
+void WEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler(void);
+void WEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void);
+void WEAK NFCT_IRQHandler(void);
+void WEAK GPIOTE_IRQHandler(void);
+void WEAK SAADC_IRQHandler(void);
+void WEAK TIMER0_IRQHandler(void);
+void WEAK TIMER1_IRQHandler(void);
+void WEAK TIMER2_IRQHandler(void);
+void WEAK RTC0_IRQHandler(void);
+void WEAK TEMP_IRQHandler(void);
+void WEAK RNG_IRQHandler(void);
+void WEAK ECB_IRQHandler(void);
+void WEAK CCM_AAR_IRQHandler(void);
+void WEAK WDT_IRQHandler(void);
+void WEAK RTC1_IRQHandler(void);
+void WEAK QDEC_IRQHandler(void);
+void WEAK COMP_LPCOMP_IRQHandler(void);
+void WEAK SWI0_EGU0_IRQHandler(void);
+void WEAK SWI1_EGU1_IRQHandler(void);
+void WEAK SWI2_EGU2_IRQHandler(void);
+void WEAK SWI3_EGU3_IRQHandler(void);
+void WEAK SWI4_EGU4_IRQHandler(void);
+void WEAK SWI5_EGU5_IRQHandler(void);
+void WEAK TIMER3_IRQHandler(void);
+void WEAK TIMER4_IRQHandler(void);
+void WEAK PWM0_IRQHandler(void);
+void WEAK PDM_IRQHandler(void);
+void WEAK MWU_IRQHandler(void);
+void WEAK PWM1_IRQHandler(void);
+void WEAK PWM2_IRQHandler(void);
+void WEAK SPIM2_SPIS2_SPI2_IRQHandler(void);
+void WEAK RTC2_IRQHandler(void);
+void WEAK I2S_IRQHandler(void);
+void WEAK FPU_IRQHandler(void);
+
+/* Assign default weak references. Override these values by defining a new function with the same name. */
+#pragma weak NMI_Handler                                    = SystemDefaultHandler
+#pragma weak HardFault_Handler                              = SystemDefaultHandler
+#pragma weak MemoryManagement_Handler                       = SystemDefaultHandler
+#pragma weak BusFault_Handler                               = SystemDefaultHandler
+#pragma weak UsageFault_Handler                             = SystemDefaultHandler
+#pragma weak SVC_Handler                                    = SystemDefaultHandler
+#pragma weak DebugMon_Handler                               = SystemDefaultHandler
+#pragma weak PendSV_Handler                                 = SystemDefaultHandler
+#pragma weak SysTick_Handler                                = SystemDefaultHandler
+#pragma weak POWER_CLOCK_IRQHandler                         = SystemDefaultHandler
+#pragma weak RADIO_IRQHandler                               = SystemDefaultHandler
+#pragma weak UARTE0_UART0_IRQHandler                        = SystemDefaultHandler
+#pragma weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler   = SystemDefaultHandler
+#pragma weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler   = SystemDefaultHandler
+#pragma weak NFCT_IRQHandler                                = SystemDefaultHandler
+#pragma weak GPIOTE_IRQHandler                              = SystemDefaultHandler
+#pragma weak SAADC_IRQHandler                               = SystemDefaultHandler
+#pragma weak TIMER0_IRQHandler                              = SystemDefaultHandler
+#pragma weak TIMER1_IRQHandler                              = SystemDefaultHandler
+#pragma weak TIMER2_IRQHandler                              = SystemDefaultHandler
+#pragma weak RTC0_IRQHandler                                = SystemDefaultHandler
+#pragma weak TEMP_IRQHandler                                = SystemDefaultHandler
+#pragma weak RNG_IRQHandler                                 = SystemDefaultHandler
+#pragma weak ECB_IRQHandler                                 = SystemDefaultHandler
+#pragma weak CCM_AAR_IRQHandler                             = SystemDefaultHandler
+#pragma weak WDT_IRQHandler                                 = SystemDefaultHandler
+#pragma weak RTC1_IRQHandler                                = SystemDefaultHandler
+#pragma weak QDEC_IRQHandler                                = SystemDefaultHandler
+#pragma weak COMP_LPCOMP_IRQHandler                         = SystemDefaultHandler
+#pragma weak SWI0_EGU0_IRQHandler                           = SystemDefaultHandler
+#pragma weak SWI1_EGU1_IRQHandler                           = SystemDefaultHandler
+#pragma weak SWI2_EGU2_IRQHandler                           = SystemDefaultHandler
+#pragma weak SWI3_EGU3_IRQHandler                           = SystemDefaultHandler
+#pragma weak SWI4_EGU4_IRQHandler                           = SystemDefaultHandler
+#pragma weak SWI5_EGU5_IRQHandler                           = SystemDefaultHandler
+#pragma weak TIMER3_IRQHandler                              = SystemDefaultHandler
+#pragma weak TIMER4_IRQHandler                              = SystemDefaultHandler
+#pragma weak PWM0_IRQHandler                                = SystemDefaultHandler
+#pragma weak PDM_IRQHandler                                 = SystemDefaultHandler
+#pragma weak MWU_IRQHandler                                 = SystemDefaultHandler
+#pragma weak PWM1_IRQHandler                                = SystemDefaultHandler
+#pragma weak PWM2_IRQHandler                                = SystemDefaultHandler
+#pragma weak SPIM2_SPIS2_SPI2_IRQHandler                    = SystemDefaultHandler
+#pragma weak RTC2_IRQHandler                                = SystemDefaultHandler
+#pragma weak I2S_IRQHandler                                 = SystemDefaultHandler
+#pragma weak FPU_IRQHandler                                 = SystemDefaultHandler
+
+/**************************************************************************************************
+  Global variables
+**************************************************************************************************/
+
+/*! Core vector table */
+void (* systemVectors[256])(void) =
+{
+  0,                                            /*  0: The initial stack pointer */
+  Reset_Handler,                                /*  1: The reset handler */
+  NMI_Handler,                                  /*  2: The NMI handler */
+  HardFault_Handler,                            /*  3: The hard fault handler */
+  MemoryManagement_Handler,                     /*  4: The MPU fault handler */
+  BusFault_Handler,                             /*  5: The bus fault handler */
+  UsageFault_Handler,                           /*  6: The usage fault handler */
+  0,                                            /*  7: Reserved */
+  0,                                            /*  8: Reserved */
+  0,                                            /*  9: Reserved */
+  0,                                            /* 10: Reserved */
+  SVC_Handler,                                  /* 11: SVCall handler */
+  DebugMon_Handler,                             /* 12: Debug monitor handler */
+  0,                                            /* 13: Reserved */
+  PendSV_Handler,                               /* 14: The PendSV handler */
+  SysTick_Handler,                              /* 15: The SysTick handler */
+
+  /* External interrupts */
+  POWER_CLOCK_IRQHandler,                       /* 16: POWER_CLOCK */
+  RADIO_IRQHandler,                             /* 17: RADIO */
+  UARTE0_UART0_IRQHandler,                      /* 18: UART0 */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, /* 19: SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, /* 20: SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+  NFCT_IRQHandler,                              /* 21: NFCT */
+  GPIOTE_IRQHandler,                            /* 22: GPIOTE */
+  SAADC_IRQHandler,                             /* 23: SAADC */
+  TIMER0_IRQHandler,                            /* 24: TIMER0 */
+  TIMER1_IRQHandler,                            /* 25: TIMER1 */
+  TIMER2_IRQHandler,                            /* 26: TIMER2 */
+  RTC0_IRQHandler,                              /* 27: RTC0 */
+  TEMP_IRQHandler,                              /* 28: TEMP */
+  RNG_IRQHandler,                               /* 29: RNG */
+  ECB_IRQHandler,                               /* 30: ECB */
+  CCM_AAR_IRQHandler,                           /* 31: CCM_AAR */
+  WDT_IRQHandler,                               /* 32: WDT */
+  RTC1_IRQHandler,                              /* 33: RTC1 */
+  QDEC_IRQHandler,                              /* 34: QDEC */
+  COMP_LPCOMP_IRQHandler,                       /* 35: COMP_LPCOMP */
+  SWI0_EGU0_IRQHandler,                         /* 36: SWI0_EGU0 */
+  SWI1_EGU1_IRQHandler,                         /* 37: SWI1_EGU1 */
+  SWI2_EGU2_IRQHandler,                         /* 38: SWI2_EGU2 */
+  SWI3_EGU3_IRQHandler,                         /* 39: SWI3_EGU3 */
+  SWI4_EGU4_IRQHandler,                         /* 40: SWI4_EGU4 */
+  SWI5_EGU5_IRQHandler,                         /* 41: SWI5_EGU5 */
+  TIMER3_IRQHandler,                            /* 42: TIMER3 */
+  TIMER4_IRQHandler,                            /* 43: TIMER4 */
+  PWM0_IRQHandler,                              /* 44: PWM0 */
+  PDM_IRQHandler,                               /* 45: PDM */
+  0,                                            /* 46: Reserved */
+  0,                                            /* 47: Reserved */
+  MWU_IRQHandler,                               /* 48: MWU */
+  PWM1_IRQHandler,                              /* 49: PWM1 */
+  PWM2_IRQHandler,                              /* 50: PWM2 */
+  SPIM2_SPIS2_SPI2_IRQHandler,                  /* 51: SPIM2_SPIS2_SPI2 */
+  RTC2_IRQHandler,                              /* 52: RTC2 */
+  I2S_IRQHandler,                               /* 53: I2S */
+  FPU_IRQHandler,                               /* 54: FPU */
+  0,                                            /* 55: Reserved */
+  0,                                            /* 56: Reserved */
+  0,                                            /* 57: Reserved */
+  0,                                            /* 58: Reserved */
+  0,                                            /* 59: Reserved */
+  0,                                            /* 60: Reserved */
+  0,                                            /* 61: Reserved */
+  0,                                            /* 62: Reserved */
+  0                                             /* 63: Reserved */
+                                                /* 64..127: Reserved */
+};
+
+/*************************************************************************************************/
+/*!
+ *  \brief      Reset handler.
+ */
+/*************************************************************************************************/
+void Reset_Handler(void)
+{
+  /* Core initialization. */
+  SystemInit();
+}
+
+/*************************************************************************************************/
+/*!
+ *  \brief      Default vector handler.
+ *
+ *  \param      None.
+ */
+/*************************************************************************************************/
+static void SystemDefaultHandler(void)
+{
+  volatile unsigned int forever = 1;
+  while (forever);
+}

babblesim/hw/bsp/nrf52_bsim/src/hal_bsp.c

@@ -0,0 +1,160 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include "os/mynewt.h"
+#include "nrfx.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_system.h"
+#include "mcu/nrf52_hal.h"
+#include "mcu/nrf52_periph.h"
+#include "mcu/native_bsp.h"
+#include "bsp/bsp.h"
+#include "defs/sections.h"
+#include "uart_hal/uart_hal.h"
+#include "uart/uart.h"
+
+/*
+ * What memory to include in coredump.
+ */
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+    [0] = {
+        .hbmd_start = &_ram_start,
+        .hbmd_size = RAM_SIZE
+    }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+    switch (id) {
+    case 0:
+        return &native_flash_dev;
+    default:
+        return NULL;
+    }
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+    *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+    return dump_cfg;
+}
+
+int
+hal_bsp_power_state(int state)
+{
+    return (0);
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+    uint32_t cfg_pri;
+
+    switch (irq_num) {
+    /* Radio gets highest priority */
+    case RADIO_IRQn:
+        cfg_pri = 0;
+        break;
+    default:
+        cfg_pri = pri;
+    }
+    return cfg_pri;
+}
+
+static void
+nrf52_periph_create_timers(void)
+{
+    int rc;
+
+    (void)rc;
+
+#if MYNEWT_VAL(TIMER_0)
+    rc = hal_timer_init(0, NULL);
+    assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+    rc = hal_timer_init(1, NULL);
+    assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+    rc = hal_timer_init(2, NULL);
+    assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+    rc = hal_timer_init(3, NULL);
+    assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+    rc = hal_timer_init(4, NULL);
+    assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_5)
+    rc = hal_timer_init(5, NULL);
+    assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(OS_CPUTIME_TIMER_NUM) >= 0
+    rc = os_cputime_init(MYNEWT_VAL(OS_CPUTIME_FREQ));
+    assert(rc == 0);
+#endif
+}
+
+static struct uart_dev os_bsp_uart0;
+static struct uart_dev os_bsp_uart1;
+
+void
+hal_bsp_init(void)
+{
+    /* Make sure system clocks have started */
+    hal_system_clock_start();
+
+    /* Create all available nRF52840 peripherals */
+//    nrf52_periph_create();
+    nrf52_periph_create_timers();
+
+    int rc;
+
+    rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+                       OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *) NULL);
+    assert(rc == 0);
+    rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
+                       OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *) NULL);
+    assert(rc == 0);
+}
+
+void
+hal_bsp_deinit(void)
+{
+}

babblesim/hw/bsp/nrf52_bsim/syscfg.yml

@@ -0,0 +1,74 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+    BSP_NRF52:
+        description: 'Set to indicate that BSP has NRF52'
+        value: 1
+    SOFT_PWM:
+        description: 'Enable soft PWM'
+        value: 0
+    ENC_FLASH_DEV:
+        description: 'Encrypting flash driver over interal flash for testing'
+        value: 0
+    UARTBB_0:
+        description: 'Enable bit-banger UART 0'
+        value: 0
+    RAM_RESIDENT:
+        description: 'Compile app to be loaded to RAM'
+        value: 0
+
+syscfg.vals:
+    HAL_SBRK: 0
+    OS_TICKS_PER_SEC: 1024
+    OS_MAIN_STACK_SIZE: 8000
+    MCU_TIMER_POLLER_PRIO: 0
+    BLE_LL_PRIO: 1
+    MCU_UART_POLLER_PRIO: 9
+
+    # Enable nRF52832 MCU
+    MCU_TARGET: nRF52832
+    # Set default pins for peripherals
+    UART_0_PIN_TX: 6
+    UART_0_PIN_RX: 8
+    UART_0_PIN_RTS: 5
+    UART_0_PIN_CTS: 7
+    SPI_0_MASTER_PIN_SCK: 23
+    SPI_0_MASTER_PIN_MOSI: 24
+    SPI_0_MASTER_PIN_MISO: 25
+    SPI_0_SLAVE_PIN_SCK: 23
+    SPI_0_SLAVE_PIN_MOSI: 24
+    SPI_0_SLAVE_PIN_MISO: 25
+    SPI_0_SLAVE_PIN_SS: 22
+    I2C_0_PIN_SCL: 27
+    I2C_0_PIN_SDA: 26
+
+    CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+    REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+    NFFS_FLASH_AREA: FLASH_AREA_NFFS
+    COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+    MCU_DCDC_ENABLED: 1
+    MCU_LFCLK_SOURCE: LFXO
+    BOOT_SERIAL_DETECT_PIN: 13  # Button 1
+
+syscfg.vals.BLE_CONTROLLER:
+    TIMER_0: 0
+    TIMER_5: 1
+    OS_CPUTIME_FREQ: 32768
+    OS_CPUTIME_TIMER_NUM: 5
+    BLE_LL_RFMGMT_ENABLE_TIME: 1500

babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/cmsis_nvic.h

@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+#include "nrf.h"
+
+#define NVIC_NUM_VECTORS      (16 + 38)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

nimble/transport/dialog_cmac/src/ble_hci_cmac_priv.h → babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/cortex_m4.h

@@ -17,13 +17,18 @@
  * under the License.
  */
 
-#ifndef _BLE_HCI_CMAC_PRIV_H_
-#define _BLE_HCI_CMAC_PRIV_H_
+#ifndef __MCU_CORTEX_M4_H__
+#define __MCU_CORTEX_M4_H__
 
-#include "os/os_mbuf.h"
+#include "nrf.h"
+#include <syscfg/syscfg.h>
 
-struct os_mbuf *ble_hci_cmac_alloc_acl_mbuf(void);
+#ifdef __cplusplus
+extern "C" {
+#endif
 
-void ble_hci_trans_notify_free(void);
+#ifdef __cplusplus
+}
+#endif
 
-#endif /* _BLE_HCI_CMAC_PRIV_H_ */
+#endif /* __MCU_CORTEX_M4_H__ */

babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/mcu.h

@@ -0,0 +1,69 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Defines for naming GPIOs. NOTE: the nordic chip docs use numeric labels for
+ * ports. Port A corresponds to Port 0, B to 1, etc. The nrf52832 has only one
+ * port and thus uses pins 0 - 31. The nrf52840 has two ports but Port 1 only
+ * has 16 pins.
+ */
+#define MCU_GPIO_PORTA(pin)	((0 * 16) + (pin))
+#define MCU_GPIO_PORTB(pin)	((1 * 16) + (pin))
+
+#if NRF52
+
+#define MCU_SYSVIEW_INTERRUPTS \
+    "I#1=Reset,I#2=MNI,I#3=HardFault,I#4=MemoryMgmt,I#5=BusFault,I#6=UsageFault," \
+    "I#11=SVCall,I#12=DebugMonitor,I#14=PendSV,I#15=SysTick," \
+    "I#16=POWER_CLOCK,I#17=RADIO,I#18=UARTE0_UART0,I#19=SPIx0_TWIx0," \
+    "I#20=SPIx1_TWIx1,I#21=NFCT,I#22=GPIOTE,I#23=SAADC," \
+    "I#24=TIMER0,I#25=TIMER1,I#26=TIMER2,I#27=RTC0,I#28=TEMP,I#29=RNG,I#30=ECB," \
+    "I#31=CCM_AAR,I#32=WDT,I#33=RTC1,I#34=QDEC,I#35=COMP_LPCOMP,I#36=SWI0_EGU0," \
+    "I#37=SWI1_EGU1,I#38=SWI2_EGU2,I#39=SWI3_EGU3,I#40=SWI4_EGU4,I#41=SWI5_EGU5," \
+    "I#42=TIMER3,I#43=TIMER4,I#44=PWM0,I#45=PDM,I#48=MWU,I#49=PWM1,I#50=PWM2," \
+    "I#51=SPIx2,I#52=RTC2,I#53=I2S,I#54=FPU"
+
+#elif NRF52840_XXAA
+
+#define MCU_SYSVIEW_INTERRUPTS \
+    "I#1=Reset,I#2=MNI,I#3=HardFault,I#4=MemoryMgmt,I#5=BusFault,I#6=UsageFault," \
+    "I#11=SVCall,I#12=DebugMonitor,I#14=PendSV,I#15=SysTick," \
+    "I#16=POWER_CLOCK,I#17=RADIO,I#18=UARTE0_UART0,I#19=SPIx0_TWIx0," \
+    "I#20=SPIx1_TWIx1,I#21=NFCT,I#22=GPIOTE,I#23=SAADC," \
+    "I#24=TIMER0,I#25=TIMER1,I#26=TIMER2,I#27=RTC0,I#28=TEMP,I#29=RNG,I#30=ECB," \
+    "I#31=CCM_AAR,I#32=WDT,I#33=RTC1,I#34=QDEC,I#35=COMP_LPCOMP,I#36=SWI0_EGU0," \
+    "I#37=SWI1_EGU1,I#38=SWI2_EGU2,I#39=SWI3_EGU3,I#40=SWI4_EGU4,I#41=SWI5_EGU5," \
+    "I#42=TIMER3,I#43=TIMER4,I#44=PWM0,I#45=PDM,I#48=MWU,I#49=PWM1,I#50=PWM2," \
+    "I#51=SPIx2,I#52=RTC2,I#53=I2S,I#54=FPU,I#55=USBD," \
+    "I#56=UARTE1,I#57=QSPI,I#58=CRYPTOCELL,I#61=PWM3,I#63=SPIM3"
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_MCU_H_ */

nimble/transport/da1469x/cmac_driver/include/cmac_driver/cmac_host.h → babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/mcu_sim.h

@@ -16,22 +16,23 @@
  * specific language governing permissions and limitations
  * under the License.
  */
-
-#ifndef __CMAC_HOST_H_
-#define __CMAC_HOST_H_
+#ifndef __MCU_SIM_H__
+#define __MCU_SIM_H__
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef int (* cmac_mbox_read_cb)(const uint8_t *, uint16_t len);
+extern char *native_flash_file;
+extern char *native_uart_log_file;
+extern const char *native_uart_dev_strs[];
+
+void mcu_sim_parse_args(int argc, char **argv);
 
-void cmac_host_init(void);
-void cmac_mbox_write(const uint8_t *buf, size_t len);
-void cmac_mbox_set_read_cb(cmac_mbox_read_cb cb);
+void static inline hal_debug_break(void) {}
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __CMAC_HOST_H_ */
+#endif /* __MCU_SIM_H__ */

babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/native_bsp.h

@@ -0,0 +1,34 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ * 
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_NATIVE_BSP_
+#define H_NATIVE_BSP_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const struct hal_flash native_flash_dev;
+
+int uart_set_dev(int port, const char *dev_str);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_NATIVE_BSP_ */

babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/nrf52_clock.h

@@ -0,0 +1,50 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_NRF52_CLOCK_
+#define H_NRF52_CLOCK_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ * Request HFXO clock be turned on. Note that each request must have a
+ * corresponding release.
+ *
+ * @return int 0: hfxo was already on. 1: hfxo was turned on.
+ */
+int nrf52_clock_hfxo_request(void);
+
+/**
+ * Release the HFXO; caller no longer needs the HFXO to be turned on. Each call
+ * to release should have been preceeded by a corresponding call to request the
+ * HFXO
+ *
+ *
+ * @return int 0: HFXO not stopped by this call (others using it) 1: HFXO
+ *         stopped.
+ */
+int nrf52_clock_hfxo_release(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* H_NRF52_CLOCK_ */

babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/nrf52_hal.h

@@ -0,0 +1,101 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_NRF52_HAL_
+#define H_NRF52_HAL_
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x)                     \
+    do {                                                \
+        x = __get_PRIMASK();                            \
+        __disable_irq();                                \
+    } while(0);
+
+#define __HAL_ENABLE_INTERRUPTS(x)                      \
+    do {                                                \
+        if (!x) {                                       \
+            __enable_irq();                             \
+        }                                               \
+    } while(0);
+
+struct nrf52_uart_cfg {
+    int8_t suc_pin_tx;                          /* pins for IO */
+    int8_t suc_pin_rx;
+    int8_t suc_pin_rts;
+    int8_t suc_pin_cts;
+};
+const struct nrf52_uart_cfg *bsp_uart_config(void);
+
+struct nrf52_hal_i2c_cfg {
+    int scl_pin;
+    int sda_pin;
+    uint32_t i2c_frequency;
+};
+struct hal_flash;
+extern const struct hal_flash nrf52k_flash_dev;
+extern const struct hal_flash nrf52k_qspi_dev;
+
+/* SPI configuration (used for both master and slave) */
+struct nrf52_hal_spi_cfg {
+    uint8_t sck_pin;
+    uint8_t mosi_pin;
+    uint8_t miso_pin;
+    uint8_t ss_pin;
+};
+
+/*
+ * GPIO pin mapping
+ *
+ * The logical GPIO pin numbers (0 to N) are mapped to ports in the following
+ * manner:
+ *  pins 0 - 31: Port 0
+ *  pins 32 - 48: Port 1.
+ *
+ *  The nrf52832 has only one port with 32 pins. The nrf52840 has 48 pins and
+ *  uses two ports.
+ *
+ *  NOTE: in order to save code space, there is no checking done to see if the
+ *  user specifies a pin that is not used by the processor. If an invalid pin
+ *  number is used unexpected and/or erroneous behavior will result.
+ */
+#if defined(NRF52832_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
+#define HAL_GPIO_INDEX(pin)     (pin)
+#define HAL_GPIO_PORT(pin)      (NRF_P0)
+#define HAL_GPIO_MASK(pin)      (1 << pin)
+#define HAL_GPIOTE_PIN_MASK     GPIOTE_CONFIG_PSEL_Msk
+#endif
+
+#ifdef NRF52840_XXAA
+#define HAL_GPIO_INDEX(pin)     ((pin) & 0x1F)
+#define HAL_GPIO_PORT(pin)      ((pin) > 31 ? NRF_P1 : NRF_P0)
+#define HAL_GPIO_MASK(pin)      (1 << HAL_GPIO_INDEX(pin))
+#define HAL_GPIOTE_PIN_MASK     (0x3FUL << GPIOTE_CONFIG_PSEL_Pos)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* H_NRF52_HAL_ */

porting/targets/dummy_bsp/include/bsp/bsp.h → babblesim/hw/mcu/nordic/nrf52_bsim/include/mcu/nrf52_periph.h

@@ -17,15 +17,17 @@
  * under the License.
  */
 
-#ifndef H_BSP_H
-#define H_BSP_H
+#ifndef H_NRF52_PERIPH_
+#define H_NRF52_PERIPH_
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
+void nrf52_periph_create(void);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* H_BSP_H */
+#endif  /* H_NRF52_PERIPH_ */

nimble/transport/ram/pkg.yml → babblesim/hw/mcu/nordic/nrf52_bsim/pkg.yml

@@ -17,20 +17,16 @@
 # under the License.
 #
 
-pkg.name: nimble/transport/ram
-pkg.description: XXX
+pkg.name: babblesim/hw/mcu/nordic/nrf52_bsim
+pkg.description: nRF52 on BabbleSim
 pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
 pkg.homepage: "http://mynewt.apache.org/"
-pkg.keywords:
-    - ble
-    - bluetooth
 
-pkg.deps:
-    - "@apache-mynewt-core/kernel/os"
-    - nimble
+pkg.lflags:
+    - -lpthread
 
-pkg.apis:
-    - ble_transport
+pkg.deps:
+    - "babblesim/core"
 
-pkg.init:
-    ble_hci_ram_init: 'MYNEWT_VAL(BLE_TRANS_RAM_SYSINIT_STAGE)'
+pkg.deps.BLE_CONTROLLER:
+    - "@apache-mynewt-nimble/nimble/drivers/nrf52"

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_flash.c

@@ -0,0 +1,289 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <string.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#include "os/mynewt.h"
+
+#include "hal/hal_flash_int.h"
+#include "mcu/mcu_sim.h"
+
+char *native_flash_file;
+static int file = -1;
+static void *file_loc;
+
+static int native_flash_init(const struct hal_flash *dev);
+static int native_flash_read(const struct hal_flash *dev, uint32_t address,
+        void *dst, uint32_t length);
+static int native_flash_write(const struct hal_flash *dev, uint32_t address,
+        const void *src, uint32_t length);
+static int native_flash_erase_sector(const struct hal_flash *dev,
+        uint32_t sector_address);
+static int native_flash_sector_info(const struct hal_flash *dev, int idx,
+        uint32_t *address, uint32_t *size);
+
+static const struct hal_flash_funcs native_flash_funcs = {
+    .hff_read = native_flash_read,
+    .hff_write = native_flash_write,
+    .hff_erase_sector = native_flash_erase_sector,
+    .hff_sector_info = native_flash_sector_info,
+    .hff_init = native_flash_init
+};
+
+#if MYNEWT_VAL(MCU_FLASH_STYLE_ST)
+static const uint32_t native_flash_sectors[] = {
+    0x00000000, /* 16 * 1024 */
+    0x00004000, /* 16 * 1024 */
+    0x00008000, /* 16 * 1024 */
+    0x0000c000, /* 16 * 1024 */
+    0x00010000, /* 64 * 1024 */
+    0x00020000, /* 128 * 1024 */
+    0x00040000, /* 128 * 1024 */
+    0x00060000, /* 128 * 1024 */
+    0x00080000, /* 128 * 1024 */
+    0x000a0000, /* 128 * 1024 */
+    0x000c0000, /* 128 * 1024 */
+    0x000e0000, /* 128 * 1024 */
+};
+#elif MYNEWT_VAL(MCU_FLASH_STYLE_NORDIC)
+static uint32_t native_flash_sectors[1024 * 1024 / 2048];
+#else
+#error "Need to specify either MCU_FLASH_STYLE_NORDIC or MCU_FLASH_STYLE_ST"
+#endif
+
+#define FLASH_NUM_AREAS   (int)(sizeof native_flash_sectors /           \
+                                sizeof native_flash_sectors[0])
+
+const struct hal_flash native_flash_dev = {
+    .hf_itf = &native_flash_funcs,
+    .hf_base_addr = 0,
+    .hf_size = 1024 * 1024,
+    .hf_sector_cnt = FLASH_NUM_AREAS,
+    .hf_align = MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE),
+    .hf_erased_val = 0xff,
+};
+
+static void
+flash_native_erase(uint32_t addr, uint32_t len)
+{
+    memset(file_loc + addr, 0xff, len);
+}
+
+static void
+flash_native_file_open(char *name)
+{
+    int created = 0;
+    char tmpl[] = "/tmp/native_flash.XXXXXX";
+
+    extern int ftruncate(int fd, off_t length);
+
+    if (file != -1) {
+        close(file);
+        file = -1;
+    }
+
+    if (name) {
+        file = open(name, O_RDWR);
+        if (file < 0) {
+            file = open(name, O_RDWR | O_CREAT, 0660);
+            assert(file > 0);
+            created = 1;
+        }
+    } else {
+        file = mkstemp(tmpl);
+        assert(file > 0);
+        created = 1;
+    }
+
+    if (created) {
+        if (ftruncate(file, native_flash_dev.hf_size) < 0) {
+            assert(0);
+        }
+    }
+
+    if (file_loc != NULL) {
+        munmap(file_loc, native_flash_dev.hf_size);
+    }
+
+    file_loc = mmap(0, native_flash_dev.hf_size,
+          PROT_READ | PROT_WRITE, MAP_SHARED, file, 0);
+    assert(file_loc != MAP_FAILED);
+    if (created) {
+        flash_native_erase(0, native_flash_dev.hf_size);
+    }
+
+    /* If using a temporary file, unlink it immediately. */
+    if (name == NULL) {
+        remove(tmpl);
+    }
+}
+
+static void
+flash_native_ensure_file_open(void)
+{
+    if (file == 0) {
+        flash_native_file_open(NULL);
+    }
+}
+
+static int
+flash_native_write_internal(uint32_t address, const void *src, uint32_t length,
+                            int allow_overwrite)
+{
+    static uint8_t buf[256];
+    uint32_t cur;
+    uint32_t end;
+    int chunk_sz;
+    int rc;
+    int i;
+
+    if (length == 0) {
+        return 0;
+    }
+
+    end = address + length;
+
+    flash_native_ensure_file_open();
+
+    cur = address;
+    while (cur < end) {
+        if (end - cur < sizeof buf) {
+            chunk_sz = end - cur;
+        } else {
+            chunk_sz = sizeof buf;
+        }
+
+        /* Ensure data is not being overwritten. */
+        if (!allow_overwrite) {
+            rc = native_flash_read(NULL, cur, buf, chunk_sz);
+            assert(rc == 0);
+            for (i = 0; i < chunk_sz; i++) {
+                assert(buf[i] == 0xff);
+            }
+        }
+
+        cur += chunk_sz;
+    }
+
+    memcpy((char *)file_loc + address, src, length);
+
+    return 0;
+}
+
+static int
+native_flash_write(const struct hal_flash *dev, uint32_t address,
+        const void *src, uint32_t length)
+{
+    assert(address % native_flash_dev.hf_align == 0);
+    return flash_native_write_internal(address, src, length, 0);
+}
+
+int
+flash_native_memset(uint32_t offset, uint8_t c, uint32_t len)
+{
+    memset(file_loc + offset, c, len);
+    return 0;
+}
+
+static int
+native_flash_read(const struct hal_flash *dev, uint32_t address, void *dst,
+        uint32_t length)
+{
+    flash_native_ensure_file_open();
+    memcpy(dst, (char *)file_loc + address, length);
+
+    return 0;
+}
+
+static int
+find_area(uint32_t address)
+{
+    int i;
+
+    for (i = 0; i < FLASH_NUM_AREAS; i++) {
+        if (native_flash_sectors[i] == address) {
+            return i;
+        }
+    }
+
+    return -1;
+}
+
+static int
+flash_sector_len(int sector)
+{
+    uint32_t end;
+
+    if (sector == FLASH_NUM_AREAS - 1) {
+        end = native_flash_dev.hf_size + native_flash_sectors[0];
+    } else {
+        end = native_flash_sectors[sector + 1];
+    }
+    return end - native_flash_sectors[sector];
+}
+
+static int
+native_flash_erase_sector(const struct hal_flash *dev, uint32_t sector_address)
+{
+    int area_id;
+    uint32_t len;
+
+    flash_native_ensure_file_open();
+
+    area_id = find_area(sector_address);
+    if (area_id == -1) {
+        return -1;
+    }
+    len = flash_sector_len(area_id);
+    flash_native_erase(sector_address, len);
+    return 0;
+}
+
+static int
+native_flash_sector_info(const struct hal_flash *dev, int idx,
+        uint32_t *address, uint32_t *size)
+{
+    assert(idx < FLASH_NUM_AREAS);
+
+    *address = native_flash_sectors[idx];
+    *size = flash_sector_len(idx);
+    return 0;
+}
+
+static int
+native_flash_init(const struct hal_flash *dev)
+{
+    //if (native_flash_file) {
+        flash_native_file_open(native_flash_file);
+    //}
+#if MYNEWT_VAL(MCU_FLASH_STYLE_NORDIC)
+    int i;
+
+    for (i = 0; i < FLASH_NUM_AREAS; i++) {
+        native_flash_sectors[i] = i * 2048;
+    }
+#endif
+    return 0;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_hw_id.c

@@ -0,0 +1,73 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <inttypes.h>
+#include <string.h>
+
+#include "hal/hal_bsp.h"
+
+#include "hal_native_priv.h"
+
+#ifndef min
+#define min(a, b) ((a)<(b)?(a):(b))
+#endif
+
+static uint8_t hal_hw_id[HAL_BSP_MAX_ID_LEN];
+static uint8_t hal_hw_id_len;
+
+int
+hal_bsp_hw_id_len(void)
+{
+    if (hal_hw_id_len != 0) {
+        return hal_hw_id_len;
+    } else {
+        return HAL_BSP_MAX_ID_LEN;
+    }
+}
+
+/*
+ * This can be used as the unique hardware identifier for the platform, as
+ * it's supposed to be unique for this particular MCU.
+ */
+int
+hal_bsp_hw_id(uint8_t *id, int max_len)
+{
+    if (hal_hw_id_len) {
+        if (max_len > hal_hw_id_len) {
+            max_len = hal_hw_id_len;
+        }
+        memcpy(id, hal_hw_id, max_len);
+        return max_len;
+    }
+    if (max_len > HAL_BSP_MAX_ID_LEN) {
+        max_len = HAL_BSP_MAX_ID_LEN;
+    }
+    memset(id, 0x42, max_len);
+    return max_len;
+}
+
+void
+hal_bsp_set_hw_id(const uint8_t *id, int len)
+{
+    if (len > HAL_BSP_MAX_ID_LEN) {
+        len = HAL_BSP_MAX_ID_LEN;
+    }
+    hal_hw_id_len = len;
+    memcpy(hal_hw_id, id, len);
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_native_priv.h

@@ -0,0 +1,27 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __HAL_NATIVE_PRIV_H__
+#define __HAL_NATIVE_PRIV_H__
+
+#include <stdint.h>
+
+void hal_bsp_set_hw_id(const uint8_t *id, int len);
+
+#endif /*  __HAL_NATIVE_PRIV_H__ */

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_os_tick.c

@@ -0,0 +1,226 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include "os/mynewt.h"
+#include "hal/hal_os_tick.h"
+#include "nrf.h"
+#include "mcu/cmsis_nvic.h"
+#include "mcu/mcu_sim.h"
+#include <time_machine.h>
+#include <NRF_HWLowL.h>
+#include <NRF_HW_model_top.h>
+#include <NRF_RTC.h>
+#include <hal/nrf_rtc.h>
+
+/* The OS scheduler requires a low-frequency timer. */
+#if MYNEWT_VAL(OS_SCHEDULING) && !MYNEWT_VAL(MCU_LFCLK_SOURCE)
+    #error The OS scheduler requires a low-frequency timer; configure MCU_LFCLK_SOURCE
+#endif
+
+#define RTC_FREQ            32768       /* in Hz */
+#define OS_TICK_TIMER       NRF_RTC1
+#define OS_TICK_IRQ         RTC1_IRQn
+#define OS_TICK_CMPREG      3   /* generate timer interrupt */
+#define RTC_COMPARE_INT_MASK(ccreg) (1UL << ((ccreg) + 16))
+
+struct hal_os_tick
+{
+    int ticks_per_ostick;
+    os_time_t max_idle_ticks;
+    uint32_t lastocmp;
+};
+
+struct hal_os_tick g_hal_os_tick;
+
+/*
+ * Implement (x - y) where the range of both 'x' and 'y' is limited to 24-bits.
+ *
+ * For example:
+ *
+ * sub24(0, 0xffffff) = 1
+ * sub24(0xffffff, 0xfffffe) = 1
+ * sub24(0xffffff, 0) = -1
+ * sub24(0x7fffff, 0) = 8388607
+ * sub24(0x800000, 0) = -8388608
+ */
+static inline int
+sub24(uint32_t x, uint32_t y)
+{
+    int result;
+
+    assert(x <= 0xffffff);
+    assert(y <= 0xffffff);
+
+    result = x - y;
+    if (result & 0x800000) {
+        return (result | 0xff800000);
+    } else {
+        return (result & 0x007fffff);
+    }
+}
+
+static inline uint32_t
+nrf52_os_tick_counter(void)
+{
+    return nrf_rtc_counter_get(OS_TICK_TIMER);
+}
+
+static inline void
+nrf52_os_tick_set_ocmp(uint32_t ocmp)
+{
+    int delta;
+    uint32_t counter;
+
+    OS_ASSERT_CRITICAL();
+    while (1) {
+        ocmp &= 0xffffff;
+        nrf_rtc_cc_set(OS_TICK_TIMER, OS_TICK_CMPREG, ocmp);
+        counter = nrf52_os_tick_counter();
+        /*
+         * From nRF52 Product specification
+         *
+         * - If Counter is 'N' writing (N) or (N + 1) to CC register
+         *   may not trigger a compare event.
+         *
+         * - If Counter is 'N' writing (N + 2) to CC register is guaranteed
+         *   to trigger a compare event at 'N + 2'.
+         */
+        delta = sub24(ocmp, counter);
+        if (delta > 2) {
+            break;
+        }
+        ocmp += g_hal_os_tick.ticks_per_ostick;
+    }
+}
+
+static void
+nrf52_timer_handler(void)
+{
+    int delta;
+    int ticks;
+    os_sr_t sr;
+    uint32_t counter;
+
+    os_trace_isr_enter();
+    OS_ENTER_CRITICAL(sr);
+
+    /* Calculate elapsed ticks and advance OS time. */
+
+    counter = nrf52_os_tick_counter();
+    delta = sub24(counter, g_hal_os_tick.lastocmp);
+    ticks = delta / g_hal_os_tick.ticks_per_ostick;
+    os_time_advance(ticks);
+
+    /* Clear timer interrupt */
+    OS_TICK_TIMER->EVENTS_COMPARE[OS_TICK_CMPREG] = 0;
+
+    /* Update the time associated with the most recent tick */
+    g_hal_os_tick.lastocmp = (g_hal_os_tick.lastocmp +
+        (ticks * g_hal_os_tick.ticks_per_ostick)) & 0xffffff;
+
+    /* Update the output compare to interrupt at the next tick */
+    nrf52_os_tick_set_ocmp(g_hal_os_tick.lastocmp + g_hal_os_tick.ticks_per_ostick);
+
+    OS_EXIT_CRITICAL(sr);
+    os_trace_isr_exit();
+}
+
+/* Wait For Interrupt */
+void
+__WFI(void)
+{
+    while (hw_irq_ctrl_get_irq_status() == 0) {
+        tm_tick();
+    }
+}
+
+void
+os_tick_idle(os_time_t ticks)
+{
+    uint32_t ocmp;
+
+    OS_ASSERT_CRITICAL();
+
+    if (ticks > 0) {
+        /*
+         * Enter tickless regime during long idle durations.
+         */
+        if (ticks > g_hal_os_tick.max_idle_ticks) {
+            ticks = g_hal_os_tick.max_idle_ticks;
+        }
+        ocmp = g_hal_os_tick.lastocmp + (ticks*g_hal_os_tick.ticks_per_ostick);
+        nrf52_os_tick_set_ocmp(ocmp);
+    }
+
+    __WFI();
+
+    if (ticks > 0) {
+        /*
+         * Update OS time before anything else when coming out of
+         * the tickless regime.
+         */
+        nrf52_timer_handler();
+    }
+}
+
+extern void nrf_rtc_regw_sideeffects(int i);
+
+void
+os_tick_init(uint32_t os_ticks_per_sec, int prio)
+{
+    uint32_t sr;
+
+    assert(RTC_FREQ % os_ticks_per_sec == 0);
+
+    g_hal_os_tick.lastocmp = 0;
+    g_hal_os_tick.ticks_per_ostick = RTC_FREQ / os_ticks_per_sec;
+
+    /*
+     * The maximum number of OS ticks allowed to elapse during idle is
+     * limited to 1/4th the number of timer ticks before the 24-bit counter
+     * rolls over.
+     */
+    g_hal_os_tick.max_idle_ticks = (1UL << 22) / g_hal_os_tick.ticks_per_ostick;
+
+    /* disable interrupts */
+    OS_ENTER_CRITICAL(sr);
+
+    /* Set isr in vector table and enable interrupt */
+    NVIC_SetPriority(OS_TICK_IRQ, prio);
+    NVIC_SetVector(OS_TICK_IRQ, (uint32_t)nrf52_timer_handler);
+    NVIC_EnableIRQ(OS_TICK_IRQ);
+
+    /*
+     * Program the OS_TICK_TIMER to operate at 32KHz and trigger an output
+     * compare interrupt at a rate of 'os_ticks_per_sec'.
+     */
+    nrf_rtc_task_trigger(OS_TICK_TIMER, NRF_RTC_TASK_STOP);
+    nrf_rtc_task_trigger(OS_TICK_TIMER, NRF_RTC_TASK_CLEAR);
+    nrf_rtc_event_disable(OS_TICK_TIMER, 0xffffffff);
+    nrf_rtc_int_disable(OS_TICK_TIMER, 0xffffffff);
+    nrf_rtc_int_enable(OS_TICK_TIMER, RTC_COMPARE_INT_MASK(OS_TICK_CMPREG));
+
+    OS_TICK_TIMER->EVENTS_COMPARE[OS_TICK_CMPREG] = 0;
+    nrf_rtc_cc_set(OS_TICK_TIMER, OS_TICK_CMPREG, g_hal_os_tick.ticks_per_ostick);
+
+    nrf_rtc_task_trigger(OS_TICK_TIMER, NRF_RTC_TASK_START);
+
+    OS_EXIT_CRITICAL(sr);
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_reset_cause.c

@@ -0,0 +1,47 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <nrf.h>
+#include "hal/hal_system.h"
+
+enum hal_reset_reason
+hal_reset_cause(void)
+{
+    static enum hal_reset_reason reason;
+    uint32_t reg;
+
+    if (reason) {
+        return reason;
+    }
+    reg = NRF_POWER->RESETREAS;
+
+    if (reg & (POWER_RESETREAS_DOG_Msk | POWER_RESETREAS_LOCKUP_Msk)) {
+        reason = HAL_RESET_WATCHDOG;
+    } else if (reg & POWER_RESETREAS_SREQ_Msk) {
+        reason = HAL_RESET_SOFT;
+    } else if (reg & POWER_RESETREAS_RESETPIN_Msk) {
+        reason = HAL_RESET_PIN;
+    } else if (reg & POWER_RESETREAS_OFF_Msk) {
+        reason = HAL_RESET_SYS_OFF_INT;
+    } else {
+        reason = HAL_RESET_POR; /* could also be brownout */
+    }
+    NRF_POWER->RESETREAS = reg;
+    return reason;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_system.c

@@ -0,0 +1,128 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "syscfg/syscfg.h"
+#include "hal/hal_system.h"
+#include "hal/hal_debug.h"
+#include "nrf.h"
+#include "cmsis.h"
+#include "mcu/mcu_sim.h"
+#include "hal/nrf_clock.h"
+
+/**
+ * Function called at startup. Called after BSS and .data initialized but
+ * prior to the _start function.
+ *
+ * NOTE: this function is called by both the bootloader and the application.
+ * If you add code here that you do not want executed in either case you need
+ * to conditionally compile it using the config variable BOOT_LOADER (will
+ * be set to 1 in case of bootloader build)
+ *
+ */
+void
+hal_system_init(void)
+{
+#if MYNEWT_VAL(MCU_DCDC_ENABLED)
+    NRF_POWER->DCDCEN = 1;
+#endif
+}
+
+void
+hal_system_reset(void)
+{
+
+#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB)
+    hal_system_reset_cb();
+#endif
+
+    while (1) {
+        HAL_DEBUG_BREAK();
+        NVIC_SystemReset();
+    }
+}
+
+int
+hal_debugger_connected(void)
+{
+    return 0;
+}
+
+/**
+ * hal system clock start
+ *
+ * Makes sure the LFCLK and/or HFCLK is started.
+ */
+void
+hal_system_clock_start(void)
+{
+#if MYNEWT_VAL(MCU_LFCLK_SOURCE)
+    uint32_t regmsk;
+    uint32_t regval;
+    uint32_t clksrc;
+
+    regmsk = CLOCK_LFCLKSTAT_STATE_Msk | CLOCK_LFCLKSTAT_SRC_Msk;
+    regval = CLOCK_LFCLKSTAT_STATE_Running << CLOCK_LFCLKSTAT_STATE_Pos;
+
+#if MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFXO)
+    regval |= CLOCK_LFCLKSTAT_SRC_Xtal << CLOCK_LFCLKSTAT_SRC_Pos;
+    clksrc = CLOCK_LFCLKSRC_SRC_Xtal;
+#elif MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFSYNTH)
+    regval |= CLOCK_LFCLKSTAT_SRC_Synth << CLOCK_LFCLKSTAT_SRC_Pos;
+    clksrc = CLOCK_LFCLKSRC_SRC_Synth;
+#elif MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFRC)
+    regval |= CLOCK_LFCLKSTAT_SRC_RC << CLOCK_LFCLKSTAT_SRC_Pos;
+    clksrc = CLOCK_LFCLKSRC_SRC_RC;
+#else
+    #error Unknown LFCLK source selected
+#endif
+
+#if MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFSYNTH)
+    /* Must turn on HFLCK for synthesized 32768 crystal */
+    nrf52_clock_hfxo_request();
+#else
+    /* Make sure HFCLK is stopped */
+    nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
+#endif
+
+    /* Check if this clock source is already running */
+    if ((NRF_CLOCK_regs.LFCLKSTAT & regmsk) != regval) {
+
+        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTOP);
+        NRF_CLOCK_regs.EVENTS_LFCLKSTARTED = 0;
+        NRF_CLOCK_regs.LFCLKSRC = clksrc;
+        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART);
+
+        /* Wait here till started! */
+//        while (1) {
+//            if (NRF_CLOCK_regs.EVENTS_LFCLKSTARTED) {
+//                if ((NRF_CLOCK_regs.LFCLKSTAT & regmsk) == regval) {
+//                    break;
+//                }
+//            }
+//        }
+    }
+#endif
+}
+
+
+void*
+NRF_RADIO_BASE_FUN(void)
+{
+    return NULL;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_timer.c

@@ -0,0 +1,949 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <assert.h>
+#include <errno.h>
+#include <hal/nrf_rtc.h>
+#include "os/mynewt.h"
+#include "mcu/cmsis_nvic.h"
+#include "hal/hal_timer.h"
+#include "nrf.h"
+#include "mcu/nrf52_hal.h"
+#include "mcu/nrf52_clock.h"
+#include "hal/nrf_timer.h"
+
+/* IRQ prototype */
+typedef void (*hal_timer_irq_handler_t)(void);
+
+/* User CC 2 for reading counter, CC 3 for timer isr */
+#define NRF_TIMER_CC_READ       (NRF_TIMER_CC_CHANNEL2)
+#define NRF_TIMER_CC_INT        (3)
+
+/* Output compare 2 used for RTC timers */
+#define NRF_RTC_TIMER_CC_INT    (2)
+
+/* Maximum number of hal timers used */
+#define NRF52_HAL_TIMER_MAX     (6)
+
+/* Maximum timer frequency */
+#define NRF52_MAX_TIMER_FREQ    (16000000)
+
+struct nrf52_hal_timer {
+    uint8_t tmr_enabled;
+    uint8_t tmr_irq_num;
+    uint8_t tmr_rtc;
+    uint8_t tmr_pad;
+    uint32_t tmr_cntr;
+    uint32_t timer_isrs;
+    uint32_t tmr_freq;
+    void *tmr_reg;
+    TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_q;
+};
+
+#if MYNEWT_VAL(TIMER_0)
+struct nrf52_hal_timer nrf52_hal_timer0;
+#endif
+#if MYNEWT_VAL(TIMER_1)
+struct nrf52_hal_timer nrf52_hal_timer1;
+#endif
+#if MYNEWT_VAL(TIMER_2)
+struct nrf52_hal_timer nrf52_hal_timer2;
+#endif
+#if MYNEWT_VAL(TIMER_3)
+struct nrf52_hal_timer nrf52_hal_timer3;
+#endif
+#if MYNEWT_VAL(TIMER_4)
+struct nrf52_hal_timer nrf52_hal_timer4;
+#endif
+#if MYNEWT_VAL(TIMER_5)
+struct nrf52_hal_timer nrf52_hal_timer5;
+#endif
+
+static const struct nrf52_hal_timer *nrf52_hal_timers[NRF52_HAL_TIMER_MAX] = {
+#if MYNEWT_VAL(TIMER_0)
+    &nrf52_hal_timer0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(TIMER_1)
+    &nrf52_hal_timer1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(TIMER_2)
+    &nrf52_hal_timer2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(TIMER_3)
+    &nrf52_hal_timer3,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(TIMER_4)
+    &nrf52_hal_timer4,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(TIMER_5)
+    &nrf52_hal_timer5
+#else
+    NULL
+#endif
+};
+
+/* Resolve timer number into timer structure */
+#define NRF52_HAL_TIMER_RESOLVE(__n, __v)       \
+    if ((__n) >= NRF52_HAL_TIMER_MAX) {         \
+        rc = EINVAL;                            \
+        goto err;                               \
+    }                                           \
+    (__v) = (struct nrf52_hal_timer *) nrf52_hal_timers[(__n)];            \
+    if ((__v) == NULL) {                        \
+        rc = EINVAL;                            \
+        goto err;                               \
+    }
+
+/* Interrupt mask for interrupt enable/clear */
+#define NRF_TIMER_INT_MASK(x)    ((1 << (uint32_t)(x)) << 16)
+
+static uint32_t
+nrf_read_timer_cntr(NRF_TIMER_Type *hwtimer)
+{
+    uint32_t tcntr;
+
+    /* Force a capture of the timer into 'cntr' capture channel; read it */
+    nrf_timer_task_trigger(hwtimer, NRF_TIMER_TASK_CAPTURE2);
+    tcntr = hwtimer->CC[NRF_TIMER_CC_READ];
+
+    return tcntr;
+}
+
+/**
+ * nrf timer set ocmp
+ *
+ * Set the OCMP used by the timer to the desired expiration tick
+ *
+ * NOTE: Must be called with interrupts disabled.
+ *
+ * @param timer Pointer to timer.
+ */
+static void
+nrf_timer_set_ocmp(struct nrf52_hal_timer *bsptimer, uint32_t expiry)
+{
+    int32_t delta_t;
+    uint32_t temp;
+    uint32_t cntr;
+    NRF_TIMER_Type *hwtimer;
+    NRF_RTC_Type *rtctimer;
+
+    if (bsptimer->tmr_rtc) {
+        rtctimer = (NRF_RTC_Type *)bsptimer->tmr_reg;
+        nrf_rtc_int_disable(rtctimer, NRF_TIMER_INT_MASK(NRF_RTC_TIMER_CC_INT));
+        temp = bsptimer->tmr_cntr;
+        cntr = nrf_rtc_counter_get(rtctimer);
+        if (rtctimer->EVENTS_OVRFLW) {
+            temp += (1UL << 24);
+            cntr = nrf_rtc_counter_get(rtctimer);
+        }
+        temp |= cntr;
+        delta_t = (int32_t)(expiry - temp);
+
+        /*
+         * The nRF52xxx documentation states that COMPARE event is guaranteed
+         * only if value written to CC register is at least 2 greater than the
+         * current counter value. We also need to account for possible extra
+         * tick during calculations so effectively any delta less than 3 needs
+         * to be handled differently. TICK event is used to have interrupt on
+         * each subsequent tick so we won't miss any and in case we detected
+         * mentioned extra tick during calculations, interrupt is triggered
+         * immediately. Delta 0 or less means we should always fire immediately.
+         */
+        if (delta_t < 1) {
+            nrf_rtc_int_disable(rtctimer, RTC_INTENCLR_TICK_Msk);
+            NVIC_SetPendingIRQ(bsptimer->tmr_irq_num);
+        } else if (delta_t < 3 && 0) {
+            nrf_rtc_int_enable(rtctimer, RTC_INTENSET_TICK_Msk);
+	    if (nrf_rtc_counter_get(rtctimer) != cntr) {
+                NVIC_SetPendingIRQ(bsptimer->tmr_irq_num);
+            }
+        } else {
+            nrf_rtc_int_disable(rtctimer, RTC_INTENCLR_TICK_Msk);
+
+            if (delta_t < (1UL << 24)) {
+                nrf_rtc_cc_set(rtctimer, NRF_RTC_TIMER_CC_INT, expiry & 0x00ffffff);
+            } else {
+                /* CC too far ahead. Just make sure we set compare far ahead */
+                nrf_rtc_cc_set(rtctimer, NRF_RTC_TIMER_CC_INT, cntr + (1UL << 23));
+            }
+            nrf_rtc_int_enable(rtctimer, NRF_TIMER_INT_MASK(NRF_RTC_TIMER_CC_INT));
+        }
+    } else {
+        hwtimer = bsptimer->tmr_reg;
+
+        /* Disable ocmp interrupt and set new value */
+        nrf_timer_int_disable(hwtimer, NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT));
+
+        /* Set output compare register to timer expiration */
+        nrf_timer_cc_set(hwtimer, NRF_TIMER_CC_INT, expiry);
+
+        /* Clear interrupt flag */
+        hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT] = 0;
+
+        /* Enable the output compare interrupt */
+        nrf_timer_int_enable(hwtimer, NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT));
+
+        /* Force interrupt to occur as we may have missed it */
+        if ((int32_t)(nrf_read_timer_cntr(hwtimer) - expiry) >= 0) {
+            NVIC_SetPendingIRQ(bsptimer->tmr_irq_num);
+        }
+    }
+}
+
+/* Disable output compare used for timer */
+static void
+nrf_timer_disable_ocmp(NRF_TIMER_Type *hwtimer)
+{
+    nrf_timer_int_disable(hwtimer, NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT));
+}
+
+static void
+nrf_rtc_disable_ocmp(NRF_RTC_Type *rtctimer)
+{
+    nrf_rtc_int_disable(rtctimer, NRF_TIMER_INT_MASK(NRF_RTC_TIMER_CC_INT));
+    nrf_rtc_int_disable(rtctimer, RTC_INTENCLR_TICK_Msk);
+}
+
+static uint32_t
+hal_timer_read_bsptimer(struct nrf52_hal_timer *bsptimer)
+{
+    uint32_t low32;
+    uint32_t ctx;
+    uint32_t tcntr;
+    NRF_RTC_Type *rtctimer;
+
+    rtctimer = (NRF_RTC_Type *)bsptimer->tmr_reg;
+    __HAL_DISABLE_INTERRUPTS(ctx);
+    tcntr = bsptimer->tmr_cntr;
+    low32 = nrf_rtc_counter_get(rtctimer);
+    if (rtctimer->EVENTS_OVRFLW) {
+        tcntr += (1UL << 24);
+        bsptimer->tmr_cntr = tcntr;
+        low32 = nrf_rtc_counter_get(rtctimer);
+        rtctimer->EVENTS_OVRFLW = 0;
+        NVIC_SetPendingIRQ(bsptimer->tmr_irq_num);
+    }
+    tcntr |= low32;
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return tcntr;
+}
+
+#if (MYNEWT_VAL(TIMER_0) || MYNEWT_VAL(TIMER_1) || MYNEWT_VAL(TIMER_2) || \
+     MYNEWT_VAL(TIMER_3) || MYNEWT_VAL(TIMER_4) || MYNEWT_VAL(TIMER_5))
+/**
+ * hal timer chk queue
+ *
+ *
+ * @param bsptimer
+ */
+static void
+hal_timer_chk_queue(struct nrf52_hal_timer *bsptimer)
+{
+    uint32_t tcntr;
+    uint32_t ctx;
+    struct hal_timer *timer;
+
+    /* disable interrupts */
+    __HAL_DISABLE_INTERRUPTS(ctx);
+    while ((timer = TAILQ_FIRST(&bsptimer->hal_timer_q)) != NULL) {
+        if (bsptimer->tmr_rtc) {
+            tcntr = hal_timer_read_bsptimer(bsptimer);
+        } else {
+            tcntr = nrf_read_timer_cntr(bsptimer->tmr_reg);
+        }
+        if ((int32_t)(tcntr - timer->expiry) >= 0) {
+            TAILQ_REMOVE(&bsptimer->hal_timer_q, timer, link);
+            timer->link.tqe_prev = NULL;
+            timer->cb_func(timer->cb_arg);
+        } else {
+            break;
+        }
+    }
+
+    /* Any timers left on queue? If so, we need to set OCMP */
+    timer = TAILQ_FIRST(&bsptimer->hal_timer_q);
+    if (timer) {
+        nrf_timer_set_ocmp(bsptimer, timer->expiry);
+    } else {
+        if (bsptimer->tmr_rtc) {
+            nrf_rtc_disable_ocmp((NRF_RTC_Type *)bsptimer->tmr_reg);
+        } else {
+            nrf_timer_disable_ocmp(bsptimer->tmr_reg);
+        }
+    }
+    __HAL_ENABLE_INTERRUPTS(ctx);
+}
+#endif
+
+/**
+ * hal timer irq handler
+ *
+ * Generic HAL timer irq handler.
+ *
+ * @param tmr
+ */
+/**
+ * hal timer irq handler
+ *
+ * This is the global timer interrupt routine.
+ *
+ */
+#if (MYNEWT_VAL(TIMER_0) || MYNEWT_VAL(TIMER_1) || MYNEWT_VAL(TIMER_2) || \
+     MYNEWT_VAL(TIMER_3) || MYNEWT_VAL(TIMER_4))
+
+static void
+hal_timer_irq_handler(struct nrf52_hal_timer *bsptimer)
+{
+    uint32_t compare;
+    NRF_TIMER_Type *hwtimer;
+
+    os_trace_isr_enter();
+
+    /* Check interrupt source. If set, clear them */
+    hwtimer = bsptimer->tmr_reg;
+    compare = hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT];
+    if (compare) {
+        hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT] = 0;
+    }
+
+    /* XXX: make these stats? */
+    /* Count # of timer isrs */
+    ++bsptimer->timer_isrs;
+
+    /*
+     * NOTE: we dont check the 'compare' variable here due to how the timer
+     * is implemented on this chip. There is no way to force an output
+     * compare, so if we are late setting the output compare (i.e. the timer
+     * counter is already passed the output compare value), we use the NVIC
+     * to set a pending interrupt. This means that there will be no compare
+     * flag set, so all we do is check to see if the compare interrupt is
+     * enabled.
+     */
+    if (hwtimer->INTENCLR & NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT)) {
+        hal_timer_chk_queue(bsptimer);
+        /* XXX: Recommended by nordic to make sure interrupts are cleared */
+        compare = hwtimer->EVENTS_COMPARE[NRF_TIMER_CC_INT];
+    }
+
+    os_trace_isr_exit();
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_5)
+static void
+hal_rtc_timer_irq_handler(struct nrf52_hal_timer *bsptimer)
+{
+    uint32_t overflow;
+    uint32_t compare;
+    uint32_t tick;
+    NRF_RTC_Type *rtctimer;
+
+    os_trace_isr_enter();
+
+    /* Check interrupt source. If set, clear them */
+    rtctimer = (NRF_RTC_Type *)bsptimer->tmr_reg;
+    compare = rtctimer->EVENTS_COMPARE[NRF_RTC_TIMER_CC_INT];
+    if (compare) {
+       rtctimer->EVENTS_COMPARE[NRF_RTC_TIMER_CC_INT] = 0;
+    }
+
+    tick = rtctimer->EVENTS_TICK;
+    if (tick) {
+        rtctimer->EVENTS_TICK = 0;
+    }
+
+    overflow = rtctimer->EVENTS_OVRFLW;
+    if (overflow) {
+        rtctimer->EVENTS_OVRFLW = 0;
+        bsptimer->tmr_cntr += (1UL << 24);
+    }
+
+    /* Count # of timer isrs */
+    ++bsptimer->timer_isrs;
+
+    /*
+     * NOTE: we dont check the 'compare' variable here due to how the timer
+     * is implemented on this chip. There is no way to force an output
+     * compare, so if we are late setting the output compare (i.e. the timer
+     * counter is already passed the output compare value), we use the NVIC
+     * to set a pending interrupt. This means that there will be no compare
+     * flag set, so all we do is check to see if the compare interrupt is
+     * enabled.
+     */
+    hal_timer_chk_queue(bsptimer);
+
+    /* Recommended by nordic to make sure interrupts are cleared */
+    compare = rtctimer->EVENTS_COMPARE[NRF_RTC_TIMER_CC_INT];
+
+    os_trace_isr_exit();
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+void
+nrf52_timer0_irq_handler(void)
+{
+    hal_timer_irq_handler(&nrf52_hal_timer0);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_1)
+void
+nrf52_timer1_irq_handler(void)
+{
+    hal_timer_irq_handler(&nrf52_hal_timer1);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_2)
+void
+nrf52_timer2_irq_handler(void)
+{
+    hal_timer_irq_handler(&nrf52_hal_timer2);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_3)
+void
+nrf52_timer3_irq_handler(void)
+{
+    hal_timer_irq_handler(&nrf52_hal_timer3);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_4)
+void
+nrf52_timer4_irq_handler(void)
+{
+    hal_timer_irq_handler(&nrf52_hal_timer4);
+}
+#endif
+
+#if MYNEWT_VAL(TIMER_5)
+void
+nrf52_timer5_irq_handler(void)
+{
+    hal_rtc_timer_irq_handler(&nrf52_hal_timer5);
+}
+#endif
+
+/**
+ * hal timer init
+ *
+ * Initialize platform specific timer items
+ *
+ * @param timer_num     Timer number to initialize
+ * @param cfg           Pointer to platform specific configuration
+ *
+ * @return int          0: success; error code otherwise
+ */
+int
+hal_timer_init(int timer_num, void *cfg)
+{
+    int rc;
+    uint8_t irq_num;
+    struct nrf52_hal_timer *bsptimer;
+    void *hwtimer;
+    hal_timer_irq_handler_t irq_isr;
+
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+
+    /* If timer is enabled do not allow init */
+    if (bsptimer->tmr_enabled) {
+        rc = EINVAL;
+        goto err;
+    }
+
+    switch (timer_num) {
+#if MYNEWT_VAL(TIMER_0)
+    case 0:
+        irq_num = TIMER0_IRQn;
+        hwtimer = NRF_TIMER0;
+        irq_isr = nrf52_timer0_irq_handler;
+        break;
+#endif
+#if MYNEWT_VAL(TIMER_1)
+    case 1:
+        irq_num = TIMER1_IRQn;
+        hwtimer = NRF_TIMER1;
+        irq_isr = nrf52_timer1_irq_handler;
+        break;
+#endif
+#if MYNEWT_VAL(TIMER_2)
+    case 2:
+        irq_num = TIMER2_IRQn;
+        hwtimer = NRF_TIMER2;
+        irq_isr = nrf52_timer2_irq_handler;
+        break;
+#endif
+#if MYNEWT_VAL(TIMER_3)
+    case 3:
+        irq_num = TIMER3_IRQn;
+        hwtimer = NRF_TIMER3;
+        irq_isr = nrf52_timer3_irq_handler;
+        break;
+#endif
+#if MYNEWT_VAL(TIMER_4)
+    case 4:
+        irq_num = TIMER4_IRQn;
+        hwtimer = NRF_TIMER4;
+        irq_isr = nrf52_timer4_irq_handler;
+        break;
+#endif
+#if MYNEWT_VAL(TIMER_5)
+    case 5:
+        irq_num = RTC0_IRQn;
+        hwtimer = NRF_RTC0;
+        irq_isr = nrf52_timer5_irq_handler;
+        bsptimer->tmr_rtc = 1;
+        break;
+#endif
+    default:
+        hwtimer = NULL;
+        break;
+    }
+
+    if (hwtimer == NULL) {
+        rc = EINVAL;
+        goto err;
+    }
+
+    bsptimer->tmr_reg = hwtimer;
+    bsptimer->tmr_irq_num = irq_num;
+
+    /* Disable IRQ, set priority and set vector in table */
+    NVIC_DisableIRQ(irq_num);
+    NVIC_SetPriority(irq_num, (1 << __NVIC_PRIO_BITS) - 1);
+    NVIC_SetVector(irq_num, (uint32_t)irq_isr);
+
+    return 0;
+
+err:
+    return rc;
+}
+
+/**
+ * hal timer config
+ *
+ * Configure a timer to run at the desired frequency. This starts the timer.
+ *
+ * @param timer_num
+ * @param freq_hz
+ *
+ * @return int
+ */
+int
+hal_timer_config(int timer_num, uint32_t freq_hz)
+{
+    int rc;
+    uint8_t prescaler;
+    uint32_t ctx;
+    uint32_t div;
+    uint32_t min_delta;
+    uint32_t max_delta;
+    struct nrf52_hal_timer *bsptimer;
+    NRF_TIMER_Type *hwtimer;
+#if MYNEWT_VAL(TIMER_5)
+    NRF_RTC_Type *rtctimer;
+#endif
+
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+
+#if MYNEWT_VAL(TIMER_5)
+    if (timer_num == 5) {
+        /* NOTE: we only allow the RTC frequency to be set at 32768 */
+        if (bsptimer->tmr_enabled || (freq_hz != 32768) ||
+            (bsptimer->tmr_reg == NULL)) {
+            rc = EINVAL;
+            goto err;
+        }
+
+        bsptimer->tmr_freq = freq_hz;
+        bsptimer->tmr_enabled = 1;
+
+        __HAL_DISABLE_INTERRUPTS(ctx);
+
+        rtctimer = (NRF_RTC_Type *)bsptimer->tmr_reg;
+
+        /* Stop the timer first */
+        nrf_rtc_task_trigger(rtctimer, NRF_RTC_TASK_STOP);
+        nrf_rtc_task_trigger(rtctimer, NRF_RTC_TASK_CLEAR);
+
+        /* Always no prescaler */
+        rtctimer->PRESCALER = 0;
+
+        /* Clear overflow events and set overflow interrupt */
+        rtctimer->EVENTS_OVRFLW = 0;
+        nrf_rtc_int_enable(rtctimer, RTC_INTENSET_OVRFLW_Msk);
+
+        /* Start the timer */
+        nrf_rtc_task_trigger(rtctimer, NRF_RTC_TASK_START);
+        /* Set isr in vector table and enable interrupt */
+        NVIC_EnableIRQ(bsptimer->tmr_irq_num);
+
+        __HAL_ENABLE_INTERRUPTS(ctx);
+        return 0;
+    }
+#endif
+
+    /* Set timer to desired frequency */
+    div = NRF52_MAX_TIMER_FREQ / freq_hz;
+
+    /*
+     * Largest prescaler is 2^9 and must make sure frequency not too high.
+     * If hwtimer is NULL it means that the timer was not initialized prior
+     * to call.
+     */
+    if (bsptimer->tmr_enabled || (div == 0) || (div > 512) ||
+        (bsptimer->tmr_reg == NULL)) {
+        rc = EINVAL;
+        goto err;
+    }
+
+    if (div == 1) {
+        prescaler = 0;
+    } else {
+        /* Find closest prescaler */
+        for (prescaler = 1; prescaler < 10; ++prescaler) {
+            if (div <= (1 << prescaler)) {
+                min_delta = div - (1 << (prescaler - 1));
+                max_delta = (1 << prescaler) - div;
+                if (min_delta < max_delta) {
+                    prescaler -= 1;
+                }
+                break;
+            }
+        }
+    }
+
+    /* Now set the actual frequency */
+    bsptimer->tmr_freq = NRF52_MAX_TIMER_FREQ / (1 << prescaler);
+    bsptimer->tmr_enabled = 1;
+
+    /* disable interrupts */
+    __HAL_DISABLE_INTERRUPTS(ctx);
+
+#if MYNEWT_VAL_CHOICE(MCU_HFCLK_SOURCE, HFXO)
+    /* Make sure HFXO is started */
+    nrf52_clock_hfxo_request();
+#endif
+    hwtimer = bsptimer->tmr_reg;
+
+    /* Stop the timer first */
+    nrf_timer_task_trigger(hwtimer, NRF_TIMER_TASK_STOP);
+    nrf_timer_task_trigger(hwtimer, NRF_TIMER_TASK_CLEAR);
+
+    /* Put the timer in timer mode using 32 bits. */
+    nrf_timer_mode_set(hwtimer, NRF_TIMER_MODE_TIMER);
+    hwtimer->BITMODE = TIMER_BITMODE_BITMODE_32Bit;
+
+    /* Set the pre-scalar */
+    hwtimer->PRESCALER = prescaler;
+
+    /* Start the timer */
+    nrf_timer_task_trigger(hwtimer, NRF_TIMER_TASK_START);
+
+    NVIC_EnableIRQ(bsptimer->tmr_irq_num);
+
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return 0;
+
+err:
+    return rc;
+}
+
+/**
+ * hal timer deinit
+ *
+ * De-initialize a HW timer.
+ *
+ * @param timer_num
+ *
+ * @return int
+ */
+int
+hal_timer_deinit(int timer_num)
+{
+    int rc;
+    uint32_t ctx;
+    struct nrf52_hal_timer *bsptimer;
+    NRF_TIMER_Type *hwtimer;
+    NRF_RTC_Type *rtctimer;
+
+    rc = 0;
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+
+    __HAL_DISABLE_INTERRUPTS(ctx);
+    if (bsptimer->tmr_rtc) {
+        rtctimer = (NRF_RTC_Type *)bsptimer->tmr_reg;
+        nrf_rtc_int_disable(rtctimer, NRF_TIMER_INT_MASK(NRF_RTC_TIMER_CC_INT));
+	nrf_rtc_task_trigger(rtctimer, NRF_RTC_TASK_STOP);
+    } else {
+        hwtimer = (NRF_TIMER_Type *)bsptimer->tmr_reg;
+        nrf_timer_int_disable(hwtimer, NRF_TIMER_INT_MASK(NRF_TIMER_CC_INT));
+        hwtimer->TASKS_SHUTDOWN = 1;
+    }
+    bsptimer->tmr_enabled = 0;
+    bsptimer->tmr_reg = NULL;
+
+#if MYNEWT_VAL_CHOICE(MCU_HFCLK_SOURCE, HFXO)
+    if (timer_num != 5) {
+        nrf52_clock_hfxo_release();
+    }
+#endif
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+err:
+    return rc;
+}
+
+/**
+ * hal timer get resolution
+ *
+ * Get the resolution of the timer. This is the timer period, in nanoseconds
+ *
+ * @param timer_num
+ *
+ * @return uint32_t The
+ */
+uint32_t
+hal_timer_get_resolution(int timer_num)
+{
+    int rc;
+    uint32_t resolution;
+    struct nrf52_hal_timer *bsptimer;
+
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+
+    resolution = 1000000000 / bsptimer->tmr_freq;
+    return resolution;
+
+err:
+    rc = 0;
+    return rc;
+}
+
+/**
+ * hal timer read
+ *
+ * Returns the timer counter. NOTE: if the timer is a 16-bit timer, only
+ * the lower 16 bits are valid. If the timer is a 64-bit timer, only the
+ * low 32-bits are returned.
+ *
+ * @return uint32_t The timer counter register.
+ */
+uint32_t
+hal_timer_read(int timer_num)
+{
+    int rc;
+    uint32_t tcntr;
+    struct nrf52_hal_timer *bsptimer;
+
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+    if (bsptimer->tmr_rtc) {
+        tcntr = hal_timer_read_bsptimer(bsptimer);
+    } else {
+        tcntr = nrf_read_timer_cntr(bsptimer->tmr_reg);
+    }
+
+    return tcntr;
+
+    /* Assert here since there is no invalid return code */
+err:
+    assert(0);
+    rc = 0;
+    return rc;
+}
+
+/**
+ * hal timer delay
+ *
+ * Blocking delay for n ticks
+ *
+ * @param timer_num
+ * @param ticks
+ *
+ * @return int 0 on success; error code otherwise.
+ */
+int
+hal_timer_delay(int timer_num, uint32_t ticks)
+{
+    uint32_t until;
+
+    until = hal_timer_read(timer_num) + ticks;
+    while ((int32_t)(hal_timer_read(timer_num) - until) <= 0) {
+        /* Loop here till finished */
+    }
+
+    return 0;
+}
+
+/**
+ *
+ * Initialize the HAL timer structure with the callback and the callback
+ * argument. Also initializes the HW specific timer pointer.
+ *
+ * @param cb_func
+ *
+ * @return int
+ */
+int
+hal_timer_set_cb(int timer_num, struct hal_timer *timer, hal_timer_cb cb_func,
+                 void *arg)
+{
+    int rc;
+    struct nrf52_hal_timer *bsptimer;
+
+    NRF52_HAL_TIMER_RESOLVE(timer_num, bsptimer);
+
+    timer->cb_func = cb_func;
+    timer->cb_arg = arg;
+    timer->link.tqe_prev = NULL;
+    timer->bsp_timer = bsptimer;
+
+    rc = 0;
+
+err:
+    return rc;
+}
+
+int
+hal_timer_start(struct hal_timer *timer, uint32_t ticks)
+{
+    int rc;
+    uint32_t tick;
+    struct nrf52_hal_timer *bsptimer;
+
+    /* Set the tick value at which the timer should expire */
+    bsptimer = (struct nrf52_hal_timer *)timer->bsp_timer;
+    if (bsptimer->tmr_rtc) {
+        tick = hal_timer_read_bsptimer(bsptimer) + ticks;
+    } else {
+        tick = nrf_read_timer_cntr(bsptimer->tmr_reg) + ticks;
+    }
+    rc = hal_timer_start_at(timer, tick);
+    return rc;
+}
+
+int
+hal_timer_start_at(struct hal_timer *timer, uint32_t tick)
+{
+    uint32_t ctx;
+    struct hal_timer *entry;
+    struct nrf52_hal_timer *bsptimer;
+
+    if ((timer == NULL) || (timer->link.tqe_prev != NULL) ||
+        (timer->cb_func == NULL)) {
+        return EINVAL;
+    }
+    bsptimer = (struct nrf52_hal_timer *)timer->bsp_timer;
+    timer->expiry = tick;
+
+    __HAL_DISABLE_INTERRUPTS(ctx);
+
+    if (TAILQ_EMPTY(&bsptimer->hal_timer_q)) {
+        TAILQ_INSERT_HEAD(&bsptimer->hal_timer_q, timer, link);
+    } else {
+        TAILQ_FOREACH(entry, &bsptimer->hal_timer_q, link) {
+            if ((int32_t)(timer->expiry - entry->expiry) < 0) {
+                TAILQ_INSERT_BEFORE(entry, timer, link);
+                break;
+            }
+        }
+        if (!entry) {
+            TAILQ_INSERT_TAIL(&bsptimer->hal_timer_q, timer, link);
+        }
+    }
+
+    /* If this is the head, we need to set new OCMP */
+    if (timer == TAILQ_FIRST(&bsptimer->hal_timer_q)) {
+        nrf_timer_set_ocmp(bsptimer, timer->expiry);
+    }
+
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return 0;
+}
+
+/**
+ * hal timer stop
+ *
+ * Stop a timer.
+ *
+ * @param timer
+ *
+ * @return int
+ */
+int
+hal_timer_stop(struct hal_timer *timer)
+{
+    uint32_t ctx;
+    int reset_ocmp;
+    struct hal_timer *entry;
+    struct nrf52_hal_timer *bsptimer;
+
+    if (timer == NULL) {
+        return EINVAL;
+    }
+
+   bsptimer = (struct nrf52_hal_timer *)timer->bsp_timer;
+
+    __HAL_DISABLE_INTERRUPTS(ctx);
+
+    if (timer->link.tqe_prev != NULL) {
+        reset_ocmp = 0;
+        if (timer == TAILQ_FIRST(&bsptimer->hal_timer_q)) {
+            /* If first on queue, we will need to reset OCMP */
+            entry = TAILQ_NEXT(timer, link);
+            reset_ocmp = 1;
+        }
+        TAILQ_REMOVE(&bsptimer->hal_timer_q, timer, link);
+        timer->link.tqe_prev = NULL;
+        if (reset_ocmp) {
+            if (entry) {
+                nrf_timer_set_ocmp((struct nrf52_hal_timer *)entry->bsp_timer,
+                                   entry->expiry);
+            } else {
+                if (bsptimer->tmr_rtc) {
+                    nrf_rtc_disable_ocmp((NRF_RTC_Type *)bsptimer->tmr_reg);
+                } else {
+                    nrf_timer_disable_ocmp(bsptimer->tmr_reg);
+                }
+            }
+        }
+    }
+
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return 0;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_uart.c

@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "bsp/bsp.h"
+
+#ifdef MN_LINUX
+#include <pty.h>
+#endif
+#ifdef MN_OSX
+#include <util.h>
+#endif
+#ifdef MN_FreeBSD
+#include <libutil.h>
+#endif
+#include <ctype.h>
+#include <stdio.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+#include <termios.h>
+#include <errno.h>
+
+#include "mcu/mcu_sim.h"
+#include "native_uart_cfg_priv.h"
+#include "syscfg/syscfg.h"
+
+#define UART_CNT                2
+
+#if MYNEWT_VAL(CONSOLE_UART_TX_BUF_SIZE)
+#define UART_MAX_BYTES_PER_POLL	MYNEWT_VAL(CONSOLE_UART_TX_BUF_SIZE) - 2
+#else
+#define UART_MAX_BYTES_PER_POLL	64
+#endif
+#define UART_POLLER_STACK_SZ	OS_STACK_ALIGN(1024)
+
+struct uart {
+    int u_open;
+    int u_fd;
+    int u_tx_run;
+    int u_rx_char;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+};
+
+const char *native_uart_dev_strs[UART_CNT];
+
+/*
+ * XXXX should try to use O_ASYNC/SIGIO for byte arrival notification,
+ * so we wouldn't need an OS for pseudo ttys.
+ */
+char *native_uart_log_file = NULL;
+static int uart_log_fd = -1;
+
+static struct uart uarts[UART_CNT];
+static int uart_poller_running;
+static struct os_task uart_poller_task;
+static os_stack_t uart_poller_stack[UART_POLLER_STACK_SZ];
+
+static void
+uart_open_log(void)
+{
+    if (native_uart_log_file && uart_log_fd < 0) {
+        uart_log_fd = open(native_uart_log_file, O_WRONLY | O_CREAT | O_TRUNC,
+                0666);
+        assert(uart_log_fd >= 0);
+    }
+}
+
+static void
+uart_log_data(struct uart *u, int istx, uint8_t data)
+{
+    static struct {
+        struct uart *uart;
+        int istx;
+        uint32_t time;
+        int chars_in_line;
+    } state = {
+            .uart = NULL,
+            .istx = 0
+    };
+    uint32_t now;
+    char tmpbuf[32];
+    int len;
+
+    if (uart_log_fd < 0) {
+        return;
+    }
+    now = os_time_get();
+    if (state.uart) {
+        if (u != state.uart || now != state.time || istx != state.istx) {
+            /*
+             * End current printout.
+             */
+            if (write(uart_log_fd, "\n", 1) != 1) {
+                assert(0);
+            }
+            state.uart = NULL;
+        } else {
+            if (state.chars_in_line == 8) {
+                if (write(uart_log_fd, "\n\t", 2) != 2) {
+                    assert(0);
+                }
+                state.chars_in_line = 0;
+            }
+            len = snprintf(tmpbuf, sizeof(tmpbuf), "%c (%02x) ",
+                    isalnum(data) ? data : '?', data);
+            if (write(uart_log_fd, tmpbuf, len) != len) {
+                assert(0);
+            }
+            state.chars_in_line++;
+        }
+    }
+    if (u && state.uart == NULL) {
+        len = snprintf(tmpbuf, sizeof(tmpbuf), "%u:uart%d %s\n\t%c (%02x) ",
+                now, u - uarts, istx ? "tx" : "rx", isalnum(data) ? data : '?', data);
+        if (write(uart_log_fd, tmpbuf, len) != len) {
+            assert(0);
+        }
+        state.chars_in_line = 1;
+        state.uart = u;
+        state.istx = istx;
+        state.time = now;
+    }
+}
+
+static int
+uart_transmit_char(struct uart *uart)
+{
+    int sr;
+    int rc;
+    char ch;
+
+    OS_ENTER_CRITICAL(sr);
+    rc = uart->u_tx_func(uart->u_func_arg);
+    if (rc < 0) {
+        /*
+         * No more data to send.
+         */
+        uart->u_tx_run = 0;
+        if (uart->u_tx_done) {
+            uart->u_tx_done(uart->u_func_arg);
+        }
+        OS_EXIT_CRITICAL(sr);
+        return 0;
+    }
+    ch = rc;
+    uart_log_data(uart, 1, ch);
+    OS_EXIT_CRITICAL(sr);
+    rc = write(uart->u_fd, &ch, 1);
+    if (rc <= 0) {
+        /* XXX EOF/error, what now? */
+        return -1;
+    }
+    return 0;
+}
+
+static void
+uart_poller(void *arg)
+{
+    int i;
+    int rc;
+    int bytes;
+    int sr;
+    int didwork;
+    unsigned char ch;
+    struct uart *uart;
+
+    while (1) {
+        for (i = 0; i < UART_CNT; i++) {
+            if (!uarts[i].u_open) {
+                continue;
+            }
+            uart = &uarts[i];
+
+            for (bytes = 0; bytes < UART_MAX_BYTES_PER_POLL; bytes++) {
+                didwork = 0;
+                if (uart->u_tx_run) {
+                    uart_transmit_char(uart);
+                    didwork = 1;
+                }
+                if (uart->u_rx_char < 0) {
+                    rc = read(uart->u_fd, &ch, 1);
+                    if (rc == 0) {
+                        /* XXX EOF, what now? */
+                        assert(0);
+                    } else if (rc > 0) {
+                        uart->u_rx_char = ch;
+                    }
+                }
+                if (uart->u_rx_char >= 0) {
+                    OS_ENTER_CRITICAL(sr);
+                    uart_log_data(uart, 0, uart->u_rx_char);
+                    rc = uart->u_rx_func(uart->u_func_arg, uart->u_rx_char);
+                    /* Delivered */
+                    if (rc >= 0) {
+                        uart->u_rx_char = -1;
+                        didwork = 1;
+                    }
+                    OS_EXIT_CRITICAL(sr);
+                }
+                if (!didwork) {
+                    break;
+                }
+            }
+        }
+        uart_log_data(NULL, 0, 0);
+        os_time_delay(OS_TICKS_PER_SEC / 100);
+    }
+}
+
+static void
+set_nonblock(int fd)
+{
+    int flags;
+
+    flags = fcntl(fd, F_GETFL);
+    if (flags == -1) {
+        const char msg[] = "fcntl(F_GETFL) fail";
+        write(1, msg, sizeof(msg));
+        return;
+    }
+    if (fcntl(fd, F_SETFL, flags | O_NONBLOCK) < 0) {
+        const char msg[] = "fcntl(F_SETFL) fail";
+        write(1, msg, sizeof(msg));
+        return;
+    }
+}
+
+static int
+uart_pty_set_attr(int fd)
+{
+    struct termios tios;
+
+    if (tcgetattr(fd, &tios)) {
+        const char msg[] = "tcgetattr() failed";
+        write(1, msg, sizeof(msg));
+        return -1;
+    }
+
+    tios.c_cflag &= ~(CSIZE | CSTOPB | PARENB);
+    tios.c_cflag |= CS8 | CREAD;
+    tios.c_iflag = IGNPAR;
+    tios.c_oflag = 0;
+    tios.c_lflag = 0;
+    if (tcsetattr(fd, TCSAFLUSH, &tios) < 0) {
+        const char msg[] = "tcsetattr() failed";
+        write(1, msg, sizeof(msg));
+        return -1;
+    }
+    return 0;
+}
+
+static int
+uart_pty(int port)
+{
+    int fd;
+    int loop_slave;
+    char pty_name[32];
+    char msg[64];
+
+    if (openpty(&fd, &loop_slave, pty_name, NULL, NULL) < 0) {
+        const char msg[] = "openpty() failed";
+        write(1, msg, sizeof(msg));
+        return -1;
+    }
+
+    if (uart_pty_set_attr(loop_slave)) {
+        goto err;
+    }
+
+    snprintf(msg, sizeof(msg), "uart%d at %s\n", port, pty_name);
+    write(1, msg, strlen(msg));
+    return fd;
+    err:
+    close(fd);
+    close(loop_slave);
+    return -1;
+}
+
+/**
+ * Opens an external device terminal (/dev/cu.<...>).
+ */
+static int
+uart_open_dev(int port, int32_t baudrate, uint8_t databits,
+              uint8_t stopbits, enum hal_uart_parity parity,
+              enum hal_uart_flow_ctl flow_ctl)
+{
+    const char *filename;
+    int fd;
+    int rc;
+
+    filename = native_uart_dev_strs[port];
+    assert(filename != NULL);
+
+    fd = open(filename, O_RDWR);
+    if (fd < 0) {
+        return -1;
+    }
+
+    rc = uart_dev_set_attr(fd, baudrate, databits,
+            stopbits, parity, flow_ctl);
+    if (rc != 0) {
+        close(fd);
+        return rc;
+    }
+
+    dprintf(1, "uart%d at %s\n", port, filename);
+
+    return fd;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    int sr;
+
+    if (port >= UART_CNT || uarts[port].u_open == 0) {
+        return;
+    }
+    OS_ENTER_CRITICAL(sr);
+    uarts[port].u_tx_run = 1;
+    if (!os_started()) {
+        /*
+         * XXX this is a hack.
+         */
+        uart_transmit_char(&uarts[port]);
+    }
+    OS_EXIT_CRITICAL(sr);
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    /* nothing to do here */
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+    if (port >= UART_CNT || uarts[port].u_open == 0) {
+        return;
+    }
+
+    /* XXX: Count statistics and add error checking here. */
+    (void) write(uarts[port].u_fd, &data, sizeof(data));
+}
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func, void *arg)
+{
+    struct uart *uart;
+    int rc;
+
+    if (port >= UART_CNT) {
+        return -1;
+    }
+
+    uart = &uarts[port];
+    if (uart->u_open) {
+        return -1;
+    }
+    uart->u_tx_func = tx_func;
+    uart->u_tx_done = tx_done;
+    uart->u_rx_func = rx_func;
+    uart->u_func_arg = arg;
+    uart->u_rx_char = -1;
+
+    if (!uart_poller_running) {
+        uart_poller_running = 1;
+        rc = os_task_init(&uart_poller_task, "uartpoll", uart_poller, NULL,
+                MYNEWT_VAL(MCU_UART_POLLER_PRIO), OS_WAIT_FOREVER, uart_poller_stack,
+                UART_POLLER_STACK_SZ);
+        assert(rc == 0);
+    }
+    return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+                enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+    struct uart *uart;
+
+    if (port >= UART_CNT) {
+        return -1;
+    }
+
+    uart = &uarts[port];
+    if (uart->u_open) {
+        return -1;
+    }
+
+    if (native_uart_dev_strs[port] == NULL) {
+        uart->u_fd = uart_pty(port);
+    } else {
+        uart->u_fd = uart_open_dev(port, baudrate, databits, stopbits,
+                parity, flow_ctl);
+    }
+
+    if (uart->u_fd < 0) {
+        return -1;
+    }
+    set_nonblock(uart->u_fd);
+
+
+    uart_open_log();
+    uart->u_open = 1;
+    return 0;
+}
+
+int
+hal_uart_close(int port)
+{
+    struct uart *uart;
+    int rc;
+
+    if (port >= UART_CNT) {
+        rc = -1;
+        goto err;
+    }
+
+    uart = &uarts[port];
+    if (!uart->u_open) {
+        rc = -1;
+        goto err;
+    }
+
+    close(uart->u_fd);
+
+    uart->u_open = 0;
+    return (0);
+    err:
+    return (rc);
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+    return (0);
+}
+
+int
+uart_set_dev(int port, const char *dev_str)
+{
+    if (port < 0 || port >= UART_CNT) {
+        return SYS_EINVAL;
+    }
+
+    if (uarts[port].u_open) {
+        return SYS_EBUSY;
+    }
+
+    native_uart_dev_strs[port] = dev_str;
+
+    return 0;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/hal_watchdog.c

@@ -0,0 +1,36 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_watchdog.h"
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+    return (0);
+}
+
+void
+hal_watchdog_enable(void)
+{
+}
+
+void
+hal_watchdog_tickle(void)
+{
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/native_uart_cfg.c

@@ -0,0 +1,248 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <termios.h>
+
+/* B0 defined in bits/termios.h collides with nrfx/mdk/nrf52.h */
+#undef B0
+
+#include "os/mynewt.h"
+#include "native_uart_cfg_priv.h"
+
+/* uint64 is used here to accommodate speed_t, whatever that is. */
+static const uint64_t uart_baud_table[][2] = {
+#ifdef B50
+    { 50, B50 },
+#endif
+#ifdef B75
+    { 75, B75 },
+#endif
+#ifdef B110
+    { 110, B110 },
+#endif
+#ifdef B134
+    { 134, B134 },
+#endif
+#ifdef B150
+    { 150, B150 },
+#endif
+#ifdef B200
+    { 200, B200 },
+#endif
+#ifdef B300
+    { 300, B300 },
+#endif
+#ifdef B600
+    { 600, B600 },
+#endif
+#ifdef B1200
+    { 1200, B1200 },
+#endif
+#ifdef B1800
+    { 1800, B1800 },
+#endif
+#ifdef B2400
+    { 2400, B2400 },
+#endif
+#ifdef B4800
+    { 4800, B4800 },
+#endif
+#ifdef B9600
+    { 9600, B9600 },
+#endif
+#ifdef B19200
+    { 19200, B19200 },
+#endif
+#ifdef B38400
+    { 38400, B38400 },
+#endif
+#ifdef B57600
+    { 57600, B57600 },
+#endif
+#ifdef B115200
+    { 115200, B115200 },
+#endif
+#ifdef B230400
+    { 230400, B230400 },
+#endif
+#ifdef B460800
+    { 460800, B460800 },
+#endif
+#ifdef B500000
+    { 500000, B500000 },
+#endif
+#ifdef B576000
+    { 576000, B576000 },
+#endif
+#ifdef B921600
+    { 921600, B921600 },
+#endif
+#ifdef B1000000
+    { 1000000, B1000000 },
+#endif
+#ifdef B1152000
+    { 1152000, B1152000 },
+#endif
+#ifdef B1500000
+    { 1500000, B1500000 },
+#endif
+#ifdef B2000000
+    { 2000000, B2000000 },
+#endif
+#ifdef B2500000
+    { 2500000, B2500000 },
+#endif
+#ifdef B3000000
+    { 3000000, B3000000 },
+#endif
+#ifdef B3500000
+    { 3500000, B3500000 },
+#endif
+#ifdef B3710000
+    { 3710000, B3710000 },
+#endif
+#ifdef B4000000
+    { 4000000, B4000000 },
+#endif
+};
+#define UART_BAUD_TABLE_SZ (sizeof uart_baud_table / sizeof uart_baud_table[0])
+
+/**
+ * Returns 0 on failure.
+ */
+speed_t
+uart_baud_to_speed(int_least32_t baud)
+{
+    int i;
+
+    for (i = 0; i < UART_BAUD_TABLE_SZ; i++) {
+        if (uart_baud_table[i][0] == baud) {
+            return uart_baud_table[i][1];
+        }
+    }
+
+    return 0;
+}
+
+/**
+ * Configures an external device terminal (/dev/cu.<...>).
+ */
+int
+uart_dev_set_attr(int fd, int32_t baudrate, uint8_t databits,
+                  uint8_t stopbits, enum hal_uart_parity parity,
+                  enum hal_uart_flow_ctl flow_ctl)
+{
+    struct termios tty;
+    speed_t speed;
+    int rc;
+
+    assert(fd >= 0);
+
+    memset(&tty, 0, sizeof(tty));
+    cfmakeraw(&tty);
+
+    speed = uart_baud_to_speed(baudrate);
+    if (speed == 0) {
+        fprintf(stderr, "invalid baud rate: %d\n", (int)baudrate);
+        assert(0);
+    }
+
+    tty.c_cflag |= (speed | CLOCAL | CREAD);
+
+    /* Set flow control. */
+    switch (flow_ctl) {
+    case HAL_UART_FLOW_CTL_NONE:
+        tty.c_cflag &= ~CRTSCTS;
+        break;
+
+    case HAL_UART_FLOW_CTL_RTS_CTS:
+        tty.c_cflag |= CRTSCTS;
+        break;
+
+    default:
+        fprintf(stderr, "invalid flow control setting: %d\n", flow_ctl);
+        return -1;
+    }
+
+    errno = 0;
+    rc = cfsetospeed(&tty, speed);
+    if (rc != 0) {
+        fprintf(stderr, "cfsetospeed failed; %d (%s) baudrate=%d\n",
+                errno, strerror(errno), (int)baudrate);
+        return -1;
+    }
+
+    errno = 0;
+    rc = cfsetispeed(&tty, speed);
+    if (rc != 0) {
+        fprintf(stderr, "cfsetispeed failed; %d (%s) baudrate=%d\n",
+                errno, strerror(errno), (int)baudrate);
+        return -1;
+    }
+
+    switch (databits) {
+    case 7:
+        tty.c_cflag |= CS7;
+
+        switch (parity) {
+        case HAL_UART_PARITY_ODD:
+            tty.c_cflag |= PARENB;
+            tty.c_cflag |= PARODD;
+            tty.c_cflag &= ~CSTOPB;
+            tty.c_cflag &= ~CSIZE;
+            break;
+
+        case HAL_UART_PARITY_EVEN:
+            tty.c_cflag |= PARENB;
+            tty.c_cflag &= ~PARODD;
+            tty.c_cflag &= ~CSTOPB;
+            tty.c_cflag &= ~CSIZE;
+            break;
+
+        default:
+            return SYS_EINVAL;
+        }
+
+    case 8:
+        if (parity != HAL_UART_PARITY_NONE) {
+            return SYS_EINVAL;
+        }
+        tty.c_cflag |= CS8;
+        tty.c_cflag &= ~PARENB;
+        tty.c_cflag &= ~CSTOPB;
+        tty.c_cflag &= ~CSIZE;
+        break;
+
+    default:
+        return SYS_EINVAL;
+    }
+
+    rc = tcsetattr(fd, TCSANOW, &tty);
+    if (rc != 0) {
+        fprintf(stderr, "tcsetattr failed; %d (%s)\n", errno, strerror(errno));
+        return -1;
+    }
+
+    return 0;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/native_uart_cfg_priv.h

@@ -0,0 +1,31 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_NATIVE_UART_CFG_PRIV_
+#define H_NATIVE_UART_CFG_PRIV_
+
+#include <termios.h>
+#include "hal/hal_uart.h"
+
+speed_t uart_baud_to_speed(int_least32_t baud);
+int uart_dev_set_attr(int fd, int32_t baudrate, uint8_t databits,
+                      uint8_t stopbits, enum hal_uart_parity parity,
+                      enum hal_uart_flow_ctl flow_ctl);
+
+#endif

babblesim/hw/mcu/nordic/nrf52_bsim/src/nrf52_clock.c

@@ -0,0 +1,103 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+#include <stdint.h>
+#include <hal/nrf_clock.h>
+#include <time_machine.h>
+#include "mcu/nrf52_hal.h"
+#include "nrfx.h"
+#include "syscfg/syscfg.h"
+#include "os/os.h"
+
+static uint8_t nrf52_clock_hfxo_refcnt;
+
+/**
+ * Request HFXO clock be turned on. Note that each request must have a
+ * corresponding release.
+ *
+ * @return int 0: hfxo was already on. 1: hfxo was turned on.
+ */
+int
+nrf52_clock_hfxo_request(void)
+{
+    int started;
+    uint32_t ctx;
+
+#if MYNEWT_VAL_CHOICE(MCU_HFCLK_SOURCE, HFINT)
+    /* Cannot enable/disable hfxo if it is not present */
+    assert(0);
+#endif
+
+    started = 0;
+    __HAL_DISABLE_INTERRUPTS(ctx);
+    assert(nrf52_clock_hfxo_refcnt < 0xff);
+    if (nrf52_clock_hfxo_refcnt == 0) {
+        /* Check the current STATE and SRC of HFCLK */
+        if ((NRF_CLOCK->HFCLKSTAT &
+             (CLOCK_HFCLKSTAT_SRC_Msk | CLOCK_HFCLKSTAT_STATE_Msk)) !=
+            (CLOCK_HFCLKSTAT_SRC_Xtal << CLOCK_HFCLKSTAT_SRC_Pos |
+             CLOCK_HFCLKSTAT_STATE_Running << CLOCK_HFCLKSTAT_STATE_Pos)) {
+            NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+            nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
+            while (!NRF_CLOCK->EVENTS_HFCLKSTARTED) {
+#if BABBLESIM
+                tm_tick();
+#endif
+            }
+        }
+        started = 1;
+    }
+    ++nrf52_clock_hfxo_refcnt;
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return started;
+}
+
+/**
+ * Release the HFXO. This means that the caller no longer needs the HFXO to be
+ * turned on. Each call to release should have been preceeded by a corresponding
+ * call to request the HFXO
+ *
+ *
+ * @return int 0: HFXO not stopped by this call (others using it) 1: HFXO
+ *         stopped.
+ */
+int
+nrf52_clock_hfxo_release(void)
+{
+    int stopped;
+    uint32_t ctx;
+
+#if MYNEWT_VAL_CHOICE(MCU_HFCLK_SOURCE, HFINT)
+    /* Cannot enable/disable hfxo if it is not present */
+    assert(0);
+#endif
+
+    stopped = 0;
+    __HAL_DISABLE_INTERRUPTS(ctx);
+    assert(nrf52_clock_hfxo_refcnt != 0);
+    --nrf52_clock_hfxo_refcnt;
+    if (nrf52_clock_hfxo_refcnt == 0) {
+        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
+        stopped = 1;
+    }
+    __HAL_ENABLE_INTERRUPTS(ctx);
+
+    return stopped;
+}

babblesim/hw/mcu/nordic/nrf52_bsim/src/system_nrf52.c

@@ -0,0 +1,37 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "mcu/cmsis_nvic.h"
+#include "nrf.h"
+
+
+void SystemInit(void)
+{
+}

babblesim/hw/mcu/nordic/nrf52_bsim/syscfg.yml

@@ -0,0 +1,526 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+    MCU_TARGET:
+        description: >
+            Specifies target MCU, shall be set by BSP.
+        value:
+        restrictions:
+            - $notnull
+        choices:
+            - nRF52810
+            - nRF52811
+            - nRF52832
+            - nRF52840
+
+    MCU_FLASH_MIN_WRITE_SIZE:
+        description: >
+            Specifies the required alignment for internal flash writes.
+            Used internally by the newt tool.
+        value: 1
+
+    MCU_DCDC_ENABLED:
+        description: >
+            Specifies whether or not to enable DC/DC regulator. This requires
+            external circuitry so is defined to be zero by default and
+            expected to be overridden by the BSP.
+        value: 0
+
+    MCU_HFCLK_SOURCE:
+        description: >
+            Selected source for high frequency clock (HFCLK).
+            Selecting HFXO will still mostly use the HFINT but will switch to HFXO when requested (BLE, certain timers, etc...)
+            Selecting HFINT should only be used in the case where an external 32MHz crystal oscillator is not present.
+        value: HFXO
+        choices:
+            - HFXO
+            - HFINT
+        restrictions:
+            - '(MCU_HFCLK_SOURCE == "HFXO") || (MCU_LFCLK_SOURCE != "LFSYNTH")'
+
+    MCU_LFCLK_SOURCE:
+        description: >
+            Selected source for low frequency clock (LFCLK).
+        value:
+        choices:
+            - LFRC      # 32.768 kHz RC oscillator
+            - LFXO      # 32.768 kHz crystal oscillator
+            - LFSYNTH   # 32.768 kHz synthesized from HFCLK
+
+    MCU_I2C_RECOVERY_DELAY_USEC:
+        description: >
+            Time to wait for activity on SCL line after triggering start task
+            before restarting TWI controller. This is to recover from state
+            where controller is unresponsive due to glitch on I2C bus.
+            Note: Default value seems to work fine, but may need to be tuned.
+        value: 100
+
+    MCU_BUS_DRIVER_I2C_USE_TWIM:
+        description: >
+            Enables usage of i2c_nrf52_twim bus driver for I2C.
+            If disabled, standard i2c_hal driver is used.
+        value: 0
+
+    MCU_GPIO_USE_PORT_EVENT:
+        description: >
+            When enabled, hal_gpio will use GPIOTE PORT event instead of PIN
+            events for interrupts. This mode may be less accurate (i.e. pulse
+            length needs to be longer in order to be detected) but it reduces
+            power consumption since it does not require HFCLK to be running.
+            Refer to nRF52xxx Product Specification document for more details.
+        value: 0
+
+    MCU_DEBUG_IGNORE_BKPT:
+       description: >
+            When enabled, asm(bkpt) will be ignored. If not set, it will hit
+            the breakpoint wherever it gets called, For example, reset and crash
+       value: 0
+
+
+# MCU peripherals definitions
+    I2C_0:
+        description: 'Enable nRF52xxx I2C (TWI) 0'
+        value: 0
+        restrictions:
+            - '!(SPI_0_MASTER && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+            - '!(SPI_0_SLAVE  && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+            - '!(SPI_1_MASTER && (MCU_TARGET == "nrf52811"))'
+            - '!(SPI_1_SLAVE  && (MCU_TARGET == "nrf52811"))'
+    I2C_0_PIN_SCL:
+        description: 'SCL pin for I2C_0'
+        value: ''
+    I2C_0_PIN_SDA:
+        description: 'SDA pin for I2C_0'
+        value: ''
+    I2C_0_FREQ_KHZ:
+        description: 'Frequency [kHz] for I2C_0'
+        value: 100
+
+    I2C_1:
+        description: 'Enable nRF52xxx I2C (TWI) 1'
+        value: 0
+        restrictions:
+            - "!SPI_1_MASTER"
+            - "!SPI_1_SLAVE"
+    I2C_1_PIN_SCL:
+        description: 'SCL pin for I2C_1'
+        value: ''
+    I2C_1_PIN_SDA:
+        description: 'SDA pin for I2C_1'
+        value: ''
+    I2C_1_FREQ_KHZ:
+        description: 'Frequency [kHz] for I2C_1'
+        value: 100
+
+    SPI_0_MASTER:
+        description: 'Enable nRF52xxx SPI Master 0'
+        value: 0
+        restrictions:
+            - "!SPI_0_SLAVE"
+            - '!(I2C_0 && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+    SPI_0_MASTER_PIN_SCK:
+        description: 'SCK pin for SPI_0_MASTER'
+        value: ''
+    SPI_0_MASTER_PIN_MOSI:
+        description: 'MOSI pin for SPI_0_MASTER'
+        value: ''
+    SPI_0_MASTER_PIN_MISO:
+        description: 'MISO pin for SPI_0_MASTER'
+        value: ''
+
+    SPI_0_SLAVE:
+        description: 'Enable nRF52xxx SPI Slave 0'
+        value: 0
+        restrictions:
+            - "!SPI_0_MASTER"
+            - '!(I2C_0 && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+    SPI_0_SLAVE_PIN_SCK:
+        description: 'SCK pin for SPI_0_SLAVE'
+        value: ''
+    SPI_0_SLAVE_PIN_MOSI:
+        description: 'MOSI pin for SPI_0_SLAVE'
+        value: ''
+    SPI_0_SLAVE_PIN_MISO:
+        description: 'MISO pin for SPI_0_SLAVE'
+        value: ''
+    SPI_0_SLAVE_PIN_SS:
+        description: 'SS pin for SPI_0_SLAVE'
+        value: ''
+
+    SPI_1_MASTER:
+        description: 'Enable nRF52xxx SPI Master 1'
+        value: 0
+        restrictions:
+            - "!SPI_1_SLAVE"
+            - '!(I2C_1 && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+            - '!(I2C_0 && ((MCU_TARGET == "nrf52811")))'
+    SPI_1_MASTER_PIN_SCK:
+        description: 'SCK pin for SPI_1_MASTER'
+        value: ''
+    SPI_1_MASTER_PIN_MOSI:
+        description: 'MOSI pin for SPI_1_MASTER'
+        value: ''
+    SPI_1_MASTER_PIN_MISO:
+        description: 'MISO pin for SPI_1_MASTER'
+        value: ''
+
+    SPI_1_SLAVE:
+        description: 'Enable nRF52xxx SPI Slave 1'
+        value: 0
+        restrictions:
+            - "!SPI_1_MASTER"
+            - '!(I2C_1 && ((MCU_TARGET == "nrf52832") || (MCU_TARGET == "nrf52840")))'
+            - '!(I2C_0 && ((MCU_TARGET == "nrf52811")))'
+    SPI_1_SLAVE_PIN_SCK:
+        description: 'SCK pin for SPI_1_SLAVE'
+        value: ''
+    SPI_1_SLAVE_PIN_MOSI:
+        description: 'MOSI pin for SPI_1_SLAVE'
+        value: ''
+    SPI_1_SLAVE_PIN_MISO:
+        description: 'MISO pin for SPI_1_SLAVE'
+        value: ''
+    SPI_1_SLAVE_PIN_SS:
+        description: 'SS pin for SPI_1_SLAVE'
+        value: ''
+
+    SPI_2_MASTER:
+        description: 'Enable nRF52xxx SPI Master 2'
+        value: 0
+        restrictions:
+            - "!SPI_2_SLAVE"
+    SPI_2_MASTER_PIN_SCK:
+        description: 'SCK pin for SPI_2_MASTER'
+        value: ''
+    SPI_2_MASTER_PIN_MOSI:
+        description: 'MOSI pin for SPI_2_MASTER'
+        value: ''
+    SPI_2_MASTER_PIN_MISO:
+        description: 'MISO pin for SPI_2_MASTER'
+        value: ''
+
+    SPI_2_SLAVE:
+        description: 'Enable nRF52xxx SPI Slave 2'
+        value: 0
+        restrictions:
+            - "!SPI_2_MASTER"
+    SPI_2_SLAVE_PIN_SCK:
+        description: 'SCK pin for SPI_2_SLAVE'
+        value: ''
+    SPI_2_SLAVE_PIN_MOSI:
+        description: 'MOSI pin for SPI_2_SLAVE'
+        value: ''
+    SPI_2_SLAVE_PIN_MISO:
+        description: 'MISO pin for SPI_2_SLAVE'
+        value: ''
+    SPI_2_SLAVE_PIN_SS:
+        description: 'SS pin for SPI_2_SLAVE'
+        value: ''
+
+    SPI_3_MASTER:
+        description: 'Enable nRF52xxx SPI Master 3'
+        value: 0
+        restrictions:
+            - 'MCU_TARGET == "nRF52840" || !SPI_3_MASTER'
+    SPI_3_MASTER_PIN_SCK:
+        description: 'SCK pin for SPI_3_MASTER'
+        value: ''
+    SPI_3_MASTER_PIN_MOSI:
+        description: 'MOSI pin for SPI_3_MASTER'
+        value: ''
+    SPI_3_MASTER_PIN_MISO:
+        description: 'MISO pin for SPI_3_MASTER'
+        value: ''
+
+    ADC_0:
+        description: 'Enable nRF52xxx ADC 0'
+        value:  0
+
+    ADC_0_REFMV_0:
+        description: 'reference mV in AREF0 if used'
+        value: 0
+
+    PWM_0:
+        description: 'Enable nRF52xxx PWM 0'
+        value: 0
+    PWM_1:
+        description: 'Enable nRF52xxx PWM 1'
+        value: 0
+    PWM_2:
+        description: 'Enable nRF52xxx PWM 2'
+        value: 0
+    PWM_3:
+        description: 'Enable nRF52xxx PWM 3'
+        value: 0
+        restrictions:
+            - 'MCU_TARGET == "nRF52840" || !PWM_3'
+
+    TRNG:
+        description: 'Enable nRF52xxx TRNG'
+        value: 0
+
+    CRYPTO:
+        description: 'Enable nRF52xxx CRYPTO'
+        value: 0
+
+    UART_0:
+        description: 'Enable nRF52xxx UART0'
+        value: 1
+    UART_0_PIN_TX:
+        description: 'TX pin for UART0'
+        value: ''
+    UART_0_PIN_RX:
+        description: 'RX pin for UART0'
+        value: ''
+    UART_0_PIN_RTS:
+        description: 'RTS pin for UART0'
+        value: -1
+    UART_0_PIN_CTS:
+        description: 'CTS pin for UART0'
+        value: -1
+
+    UART_1:
+        description: 'Enable nRF52xxx UART1'
+        value: 0
+        restrictions:
+            - 'MCU_TARGET == "nRF52840" || !UART_1'
+    UART_1_PIN_TX:
+        description: 'TX pin for UART1'
+        value: ''
+    UART_1_PIN_RX:
+        description: 'RX pin for UART1'
+        value: ''
+    UART_1_PIN_RTS:
+        description: 'RTS pin for UART1'
+        value: -1
+    UART_1_PIN_CTS:
+        description: 'CTS pin for UART1'
+        value: -1
+
+    TEMP:
+        description: 'Enable nRF52xxx internal temperature mesurement'
+        value:  0
+
+    TIMER_0:
+        description: 'Enable nRF52xxx Timer 0'
+        value:  1
+    TIMER_1:
+        description: 'Enable nRF52xxx Timer 1'
+        value:  0
+    TIMER_2:
+        description: 'Enable nRF52xxx Timer 2'
+        value:  0
+    TIMER_3:
+        description: 'Enable nRF52xxx Timer 3'
+        value:  0
+    TIMER_4:
+        description: 'Enable nRF52xxx Timer 4'
+        value:  0
+    TIMER_5:
+        description: 'Enable nRF52xxx RTC 0'
+        value:  0
+
+    QSPI_ENABLE:
+        description: 'NRF52 QSPI'
+        value: 0
+
+    QSPI_READOC:
+        description: >
+            QSPI Command to use
+            0 - 0x09 Fast Read
+            1 - 0x3B Fast Read Dual Output
+            2 - 0xBB Fast Read Dual I/O
+            3 - 0x6B Fast Read Quad Output
+            4 - 0xEB Fast Read Quad I/O
+        value: 0
+    QSPI_WRITEOC:
+        description: >
+            QSPI Command to use
+            0 - 0x02 Page program
+            1 - 0xA2 Page program Dual Data
+            2 - 0x32 Page program Quad Data
+            3 - 0x38 Page program Quad I/O
+        value: 0
+    QSPI_ADDRMODE:
+        description: 'Address lentgh 0=24 bits, 1=32 bits'
+        value: 0
+    QSPI_DPMCONFIG:
+        description: 'Deep power mode enable'
+        value: 0
+    QSPI_SCK_DELAY:
+        description: >
+            Minimum amount of time that the CSN pin must stay high
+            before it can go low again. Value is specified in number of 16
+            MHz periods (62.5 ns).
+        value: 0
+    QSPI_SCK_FREQ:
+        description: '32MHz clock divider (0-31). Clock = 32MHz / (1+divider)'
+        value: 0
+    QSPI_SPI_MODE:
+        description: 'SPI 0=Mode0 or 1=Mode3'
+        value: 0
+
+    QSPI_FLASH_SECTOR_SIZE:
+        description: 'QSPI sector size. In most cases it should be 4096.'
+        value: 0
+    QSPI_FLASH_PAGE_SIZE:
+        description: >
+            QSPI page size. Writes can only be performed to one page at a time.
+            In most cases it should be 256.
+        value: 0
+
+    QSPI_FLASH_SECTOR_COUNT:
+        description: 'QSPI sector count'
+        value: -1
+    QSPI_PIN_CS:
+        description: 'CS pin for QSPI'
+        value: -1
+    QSPI_PIN_SCK:
+        description: 'SCK pin for QSPI'
+        value: -1
+    QSPI_PIN_DIO0:
+        description: 'DIO0 pin for QSPI'
+        value: -1
+    QSPI_PIN_DIO1:
+        description: 'DIO1 pin for QSPI'
+        value: -1
+    QSPI_PIN_DIO2:
+        description: 'DIO2 pin for QSPI'
+        value: -1
+    QSPI_PIN_DIO3:
+        description: 'DIO3 pin for QSPI'
+        value: -1
+
+    NFC_PINS_AS_GPIO:
+        description: 'Use NFC pins as GPIOs instead of NFC functionality'
+        value: 1
+
+    GPIO_AS_PIN_RESET:
+        description: 'Enable pin reset'
+        value: 0
+
+# Deprecated settings
+
+    MCU_NRF52832:
+        description: Use MCU_TARGET instead
+        value: 0
+        restrictions:
+            - "!MCU_NRF52840"
+        deprecated: 1
+    MCU_NRF52840:
+        description: Use MCU_TARGET instead
+        value: 0
+        restrictions:
+            - "!MCU_NRF52832"
+        deprecated: 1
+
+    XTAL_32768:
+        description: Use MCU_LFCLK_SOURCE instead
+        value: 0
+        restrictions:
+            - "!XTAL_RC"
+            - "!XTAL_32768_SYNTH"
+        deprecated: 1
+    XTAL_RC:
+        description: Use MCU_LFCLK_SOURCE instead
+        value: 0
+        restrictions:
+            - "!XTAL_32768"
+            - "!XTAL_32768_SYNTH"
+        deprecated: 1
+    XTAL_32768_SYNTH:
+        description: Use MCU_LFCLK_SOURCE instead
+        value: 0
+        restrictions:
+            - "!XTAL_32768"
+            - "!XTAL_RC"
+        deprecated: 1
+
+    MCU_NATIVE_USE_SIGNALS:
+        description: >
+            Whether to use POSIX signals to implement context switches.  Valid
+            values are as follows:
+                1: More correctness; less stability.  The OS tick timer will
+                   cause a high-priority task to preempt a low-priority task.
+                   This causes stability issues because a task can be preempted
+                   while it is in the middle of a system call, potentially
+                   causing deadlock or memory corruption.
+
+                0: Less correctness; more stability.  The OS tick timer only
+                   runs while the idle task is active.  Therefore, a sleeping
+                   high-priority task will not preempt a low-priority task due
+                   to a timing event (e.g., delay or callout expired).
+                   However, this version of sim does not suffer from the
+                   stability issues that affect the "signals" implementation.
+
+            Unit tests should use 1.  Long-running sim processes should use 0.
+
+        value: 1
+    MCU_NATIVE:
+        description: >
+            Set to indicate that we are using native mcu.
+        value: 1
+    MCU_FLASH_STYLE_ST:
+        description: Emulated flash layout is similar to one in STM32.
+        value: 0
+        restrictions:
+            - "!MCU_FLASH_STYLE_NORDIC"
+    MCU_FLASH_STYLE_NORDIC:
+        description: >
+            Emulated flash layout is similar to one in NRF51/2 and SAMD21.
+        value: 1
+        restrictions:
+            - "!MCU_FLASH_STYLE_ST"
+    MCU_UART_POLLER_PRIO:
+        description: 'Priority of native UART poller task.'
+        type: task_priority
+        value: 1
+    MCU_TIMER_POLLER_PRIO:
+        description: 'Priority of native HAL timer task.'
+        type: task_priority
+        value: 0
+
+syscfg.vals:
+    OS_TICKS_PER_SEC: 128
+
+syscfg.vals.MCU_NRF52832:
+    MCU_TARGET: nRF52832
+syscfg.vals.MCU_NRF52840:
+    MCU_TARGET: nRF52840
+
+syscfg.vals.XTAL_32768:
+    MCU_LFCLK_SOURCE: LFXO
+syscfg.vals.XTAL_RC:
+    MCU_LFCLK_SOURCE: LFRC
+syscfg.vals.XTAL_32768_SYNTH:
+    MCU_LFCLK_SOURCE: LFSYNTH
+
+syscfg.restrictions:
+    - "!I2C_0 || (I2C_0_PIN_SCL && I2C_0_PIN_SDA)"
+    - "!I2C_1 || (I2C_1_PIN_SCL && I2C_1_PIN_SDA)"
+    - "!SPI_0_MASTER || (SPI_0_MASTER_PIN_SCK && SPI_0_MASTER_PIN_MOSI && SPI_0_MASTER_PIN_MISO)"
+    - "!SPI_1_MASTER || (SPI_1_MASTER_PIN_SCK && SPI_1_MASTER_PIN_MOSI && SPI_1_MASTER_PIN_MISO)"
+    - "!SPI_2_MASTER || (SPI_2_MASTER_PIN_SCK && SPI_2_MASTER_PIN_MOSI && SPI_2_MASTER_PIN_MISO)"
+    - "!SPI_3_MASTER || (SPI_3_MASTER_PIN_SCK && SPI_3_MASTER_PIN_MOSI && SPI_3_MASTER_PIN_MISO)"
+    - "!SPI_0_SLAVE || (SPI_0_SLAVE_PIN_SCK && SPI_0_SLAVE_PIN_MOSI && SPI_0_SLAVE_PIN_MISO && SPI_0_SLAVE_PIN_SS)"
+    - "!SPI_1_SLAVE || (SPI_1_SLAVE_PIN_SCK && SPI_1_SLAVE_PIN_MOSI && SPI_1_SLAVE_PIN_MISO && SPI_1_SLAVE_PIN_SS)"
+    - "!SPI_2_SLAVE || (SPI_2_SLAVE_PIN_SCK && SPI_2_SLAVE_PIN_MOSI && SPI_2_SLAVE_PIN_MISO && SPI_2_SLAVE_PIN_SS)"
+    - "!UART_0 || (UART_0_PIN_TX && UART_0_PIN_RX)"
+    - "!UART_1 || (UART_1_PIN_TX && UART_1_PIN_RX)"
+    - "(OS_TICKS_PER_SEC == 128 || OS_TICKS_PER_SEC == 256 || OS_TICKS_PER_SEC == 512 || OS_TICKS_PER_SEC == 1024)"

babblesim/sdk/.gitignore

@@ -0,0 +1,3 @@
+components
+nrfx
+src

babblesim/sdk/pkg.yml

@@ -0,0 +1,47 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/sdk
+pkg.type: sdk
+pkg.description: External files required to build BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "https://mynewt.apache.org/"
+
+pkg.cflags: -std=gnu99
+
+pkg.include_dirs:
+  - components/ext_NRF52_hw_models/src/nrfx_config
+  - components/ext_NRF52_hw_models/src/nrfx/nrfx_replacements
+  - components/ext_NRF52_hw_models/src/nrfx/mdk_replacements
+  - components/ext_NRF52_hw_models/src/HW_models
+  - components/libUtilv1/src
+  - components/libPhyComv1/src
+  - components/libRandv2/src
+  - components/ext_libCryptov1/src
+  - nrfx
+  - nrfx/drivers
+  - nrfx/hal
+  - nrfx/mdk
+
+pkg.pre_build_cmds:
+  scripts/link_babblesim.sh: 1
+  scripts/link_nrfx.sh: 2
+
+pkg.lflags:
+  - -ldl

babblesim/sdk/scripts/link_babblesim.sh

@@ -0,0 +1,47 @@
+#!/bin/bash
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+if [ -z ${BSIM_COMPONENTS_PATH+x} ]; then
+  echo "This board requires the BabbleSim simulator. Please set" \
+        "the environment variable BSIM_COMPONENTS_PATH to point to its components" \
+        "folder. More information can be found in" \
+        "https://babblesim.github.io/folder_structure_and_env.html"
+  exit 1
+fi
+
+if [ -z ${BSIM_OUT_PATH+x} ]; then
+  echo "This board requires the BabbleSim simulator. Please set" \
+        "the environment variable BSIM_OUT_PATH to point to the folder where the" \
+        "simulator is compiled to. More information can be found in" \
+        "https://babblesim.github.io/folder_structure_and_env.html"
+  exit 1
+fi
+
+ln -sfn "${BSIM_COMPONENTS_PATH}" ./components
+
+mkdir -p ./src/
+cp "${BSIM_OUT_PATH}"/lib/*.32.a ./src/
+
+# XXX: Workaround for bad linking by newt. Sometimes newt will link
+# nrf weak functions from nrf_hal_originals.o instead of their BabbleSim
+# replacements inside libNRF52_hw_models.32.a. But as long as the other
+# weak functions, that do not have their replacements, are not used,
+# we can just remove the file from the .a library here.
+ar d ./src/libNRF52_hw_models.32.a nrf_hal_originals.o

babblesim/sdk/scripts/link_nrfx.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+ln -sfn ${NRFX_BASE} ./nrfx

babblesim/targets/blecent/pkg.yml

@@ -0,0 +1,23 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/targets/blecent
+pkg.type: target
+pkg.descrption: Sample target for running blecent on BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "https://mynewt.apache.org/"

nimble/transport/da1469x/cmac_driver/syscfg.yml → babblesim/targets/blecent/syscfg.yml

@@ -16,8 +16,5 @@
 # under the License.
 #
 
-syscfg.defs:
-    CMAC_IMAGE_FILE_NAME:
-        description: >
-            Path to library with CMAC firmware. See README for details.
-        value: "libble_stack_da1469x.a"
+syscfg.vals:
+  BLE_LL_PUBLIC_DEV_ADDR: 0xbabb1e000002

babblesim/targets/blecent/target.yml

@@ -0,0 +1,21 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+target.app: "@apache-mynewt-nimble/apps/blecent"
+target.bsp: "@apache-mynewt-nimble/babblesim/hw/bsp/nrf52_bsim"
+target.build_profile: debug

babblesim/targets/blehci/pkg.yml

@@ -0,0 +1,23 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/targets/blehci
+pkg.type: target
+pkg.descrption: Sample target for running blehci on BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "https://mynewt.apache.org/"

babblesim/targets/blehci/syscfg.yml

@@ -0,0 +1,21 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+  BLE_LL_PUBLIC_DEV_ADDR: 0xbabb1e000001
+  BLE_HCI_TRANSPORT: uart

babblesim/targets/blehci/target.yml

@@ -0,0 +1,21 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+target.app: "@apache-mynewt-nimble/apps/blehci"
+target.bsp: "@apache-mynewt-nimble/babblesim/hw/bsp/nrf52_bsim"
+target.build_profile: debug

babblesim/targets/bleprph/pkg.yml

@@ -0,0 +1,23 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/targets/bleprph
+pkg.type: target
+pkg.descrption: Sample target for running bleprph on BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "https://mynewt.apache.org/"

babblesim/targets/bleprph/syscfg.yml

@@ -0,0 +1,20 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+  BLE_LL_PUBLIC_DEV_ADDR: 0xbabb1e000003

babblesim/targets/bleprph/target.yml

@@ -0,0 +1,21 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+target.app: "@apache-mynewt-nimble/apps/bleprph"
+target.bsp: "@apache-mynewt-nimble/babblesim/hw/bsp/nrf52_bsim"
+target.build_profile: debug

babblesim/targets/btshell/pkg.yml

@@ -0,0 +1,23 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: babblesim/targets/btshell
+pkg.type: target
+pkg.descrption: Sample target for running btshell on BabbleSim
+pkg.author: "Apache Mynewt <dev@mynewt.apache.org>"
+pkg.homepage: "https://mynewt.apache.org/"

babblesim/targets/btshell/syscfg.yml

@@ -0,0 +1,20 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+  BLE_LL_PUBLIC_DEV_ADDR: 0xbabb1e000004

babblesim/targets/btshell/target.yml

@@ -0,0 +1,21 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+target.app: "@apache-mynewt-nimble/apps/btshell"
+target.bsp: "@apache-mynewt-nimble/babblesim/hw/bsp/nrf52_bsim"
+target.build_profile: debug

nimble/transport/da1469x/cmac_driver/pkg.yml → babblesim/targets/edtthci/pkg.yml

@@ -17,11 +17,8 @@
 # under the License.
 #
 
-pkg.name: nimble/transport/da1469x/cmac_driver
-pkg.description: Driver for Dialog's BLE controller
+pkg.name: babblesim/targets/edtthci
+pkg.type: target
+pkg.description:
 pkg.author:
 pkg.homepage:
-pkg.keywords:
-
-pkg.pre_link_cmds.BLE_HOST:
-    scripts/build_libcmac.sh: 100

babblesim/targets/edtthci/syscfg.yml

@@ -0,0 +1,55 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+  # EDTT requires 0x123456789ABC address for the first device
+  # and 0x456789ABCDEF for the second one
+  BLE_LL_PUBLIC_DEV_ADDR: 0x123456789ABC  # d=1
+  # BLE_LL_PUBLIC_DEV_ADDR: 0x456789ABCDEF # d=2
+
+  EDTT_HCI_LOG_FILE: ("hci_logs")
+  EDTT_HCI_LOGS: 1
+
+  BLE_LL_CFG_FEAT_LE_ENCRYPTION: 1
+  BLE_LL_CFG_FEAT_CONN_PARAM_REQ: 1
+  BLE_LL_CFG_FEAT_SLAVE_INIT_FEAT_XCHG: 1
+  BLE_LL_CFG_FEAT_LE_PING: 1
+  BLE_LL_CFG_FEAT_DATA_LEN_EXT: 1
+  BLE_LL_CFG_FEAT_LL_PRIVACY: 1
+  BLE_LL_CFG_FEAT_LE_CSA2: 1
+  BLE_LL_CFG_FEAT_LE_2M_PHY: 1
+#  BLE_LL_CFG_FEAT_LE_CODED_PHY: 1  # not modeled in bsim
+  BLE_LL_CFG_FEAT_LL_EXT_ADV: 1
+  BLE_LL_CFG_FEAT_LL_PERIODIC_ADV: 1
+  BLE_LL_CFG_FEAT_LL_PERIODIC_ADV_SYNC_TRANSFER: 1
+  BLE_LL_CFG_FEAT_CTRL_TO_HOST_FLOW_CONTROL: 1
+  BLE_LL_CFG_FEAT_LL_SCA_UPDATE: 1
+
+  BLE_ROLE_CENTRAL: 1
+  BLE_ROLE_PERIPHERAL: 1
+  BLE_ROLE_BROADCASTER: 1
+  BLE_ROLE_OBSERVER: 1
+
+  BLE_VERSION: 52
+  BLE_CONTROLLER: 1
+  BLE_LL_ROLE_CENTRAL: 1
+  BLE_LL_ROLE_PERIPHERAL: 1
+  BLE_LL_ROLE_BROADCASTER: 1
+  BLE_LL_ROLE_OBSERVER: 1
+  BLE_HW_WHITELIST_ENABLE: 1

babblesim/targets/edtthci/target.yml

@@ -0,0 +1,22 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+target.app: "@apache-mynewt-nimble/babblesim/edtt/hci_test"
+target.bsp: "@apache-mynewt-nimble/babblesim/hw/bsp/nrf52_bsim"
+target.build_profile: debug

docs/btshell/btshell_api.rst

@@ -48,11 +48,11 @@ For example:
     set addr_type=public addr=01:02:03:04:05:06
     set addr_type=random addr=c1:aa:bb:cc:dd:ee
 
-The address configuration can be viewed with the ``gatt-show-addr`` command, as follows:
+The address configuration can be viewed with the ``show-addr`` command, as follows:
 
 ::
 
-    gatt-show-addr
+    show-addr
     public_id_addr=01:02:03:04:05:06 random_id_addr=c1:aa:bb:cc:dd:ee
 
 Initiate a direct connection to a device

docs/firmwares/README.md

@@ -0,0 +1,87 @@
+# 蓝牙控制器固件
+
+目前在 qume 下运行此协议栈需要搭配蓝牙 Controller 芯片，以下固件都是在 Zephyr 环境下编译 hci 相关例程生成的，经实际使用测试，工作稳定。
+
+参考：[hci-uart](https://docs.zephyrproject.org/latest/samples/bluetooth/hci_uart/README.html) 和 [hci-usb](https://docs.zephyrproject.org/latest/samples/bluetooth/hci_usb/README.html)
+
+
+### hci_uart_nrf52840dk.hex
+
+<img src="./images/nrf52840dk.png" alt="nrf52840dk" style="zoom:67%;" />
+
+该固件使用的是 [nrf52840dk](https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dk) 开发板，HCI 传输层为 H4 协议，波特率 115200，使用硬件控制流 CTS/RTS。
+
+**Windows** 平台下载该固件比较简单，将 nrf52840dk 插入电脑，电脑会自动识别一个 `JLINK` U 盘，用鼠标将固件拖入该 U 盘即可。
+
+![JLINK U 盘](./images/JLINK_U.png)
+
+**Linux** 平台下载该固件较为麻烦，需要使用工具 [J-Link Software and documentation pack](https://www.segger.com/downloads/jlink/) 和 [nRF Command Line Tools](https://www.nordicsemi.com/Products/Development-tools/nrf-command-line-tools)
+
+下载固件流程：
+
+1. 擦除芯片内程序
+
+```shell
+nrfjprog --eraseall -f nrf52
+```
+
+2. 写入固件
+
+```shell
+nrfjprog --program hci_uart_nrf52840dk.hex -f nrf52
+```
+
+3. 复位并启动
+
+```shell
+nrfjprog --reset -f nrf52
+```
+
+可参考：[nordic-segger](https://docs.zephyrproject.org/latest/develop/flash_debug/nordic_segger.html#nordic-segger)
+
+
+
+**qemu 环境下使用提示**
+
+使用 nrf52840dk 开发板 JLink 虚拟串口进行交互，当识别到 JLink 时，虚拟串口也可以被识别。
+
+```
+# 参考以下命令替换原有命令， /dev/ttyACM0 按照被识别的实际串口修改
+qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin -serial mon:stdio -serial /dev/ttyACM0
+```
+
+
+
+### hci_usb_nrf52840dongle.hex
+
+<img src="./images/nrf52840dongle.png" alt="nrf52840dongle" style="zoom: 67%;" />
+
+该固件使用的是 [nrf52840dongle](https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle) 开发板，HCI 传输层为 USB 协议。
+
+下载该固件需要使用 [nRF Util](https://www.nordicsemi.com/Products/Development-tools/nRF-Util)，输入 `pip3 install nrfutil` 即可安装。
+
+下载固件：
+
+1. 按下 RESET 按钮进入 bootloader
+2. 利用 nrfutil 打包固件
+
+```shell
+nrfutil pkg generate --hw-version 52 --sd-req=0x00 \
+        --application hci_usb_nrf52840dongle.hex \
+        --application-version 1 hci_usb_nrf52840dongle.zip
+```
+
+3. 写入固件，注意 Linux 环境下使用 `/dev/ttyXXX` 设备，Windows 使用 `COMx`，macOS 也类似。
+
+```shell
+nrfutil dfu usb-serial -pkg hci_usb_nrf52840dongle.zip -p /dev/ttyACM0
+```
+
+可参考：[Zephyr-nrf52840dongle](https://docs.zephyrproject.org/latest/boards/arm/nrf52840dongle_nrf52840/doc/index.html)
+
+
+
+**qemu 环境下使用提示**
+
+此固件会被识别成 hci 设备， 具体使用可参考 [QEMU 运行 BLE](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/setup/qemu/qemu-ble/qemu_ble?id=qemu-运行-ble)
+

docs/firmwares/hci_uart_nrf52840dk.hex

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docs/同步上游代码说明.md

@@ -0,0 +1,70 @@
+# 同步上游代码说明
+
+这里简要说明一下，同步上游代码时主要修改了哪些地方。[上游官方仓库](https://github.com/apache/mynewt-nimble)
+
+## NimBLE 目录结构
+
+```
+NimBLE
+   ├───apps                   /* Bluetooth 示例应用程序 */
+   ├───docs                   /* 文档及 API 说明 */
+   ├───ext
+   │   └───tinycrypt          /* Tinycrypt 加密库 */
+   ├───nimble
+   │   ├───controller         /* Controller 实现 */
+   │   ├───doc                /* 当前包含 transport 层说明文档 */   
+   │   ├───drivers            /* Nordic 系列 Phy 驱动 */
+   │   ├───host               /* Host Stack(主机控制器)实现 */
+   │   ├───include
+   │   └───transport          /* HCI 传输抽象层 */
+   └───porting                /* OS 抽象层及系统配置 */
+```
+
+## apps 
+
+此目录下都为 Bluetooth 示例应用程序，大部分程序做了 RT-Thread 的适配，已有的例程建议不要直接覆盖；官方对此部分改动应该不会很大，要对照实际内容修改，也可在 debug 过程中修改代码。
+
+官方写的新例程可以尝试添加一下，并按照其他例程形式修改一下在 RT-Thread 上跑起来。
+
+## docs
+
+此目录下都为文档资料，包含官方文档，也有后续 rt-thread 社区小伙伴 PR 的文档。官方文档可以更新一下，基本内容都比较少。
+
+## ext
+
+目录下包含扩展库，目前包含了一个 Tinycrypt 加密库，提供了一个最小的标准密码原语集，可以跟着官方更新一下。
+
+## nimble
+
+nimble 目录下的文件基本上都是协议栈的主干部分，包括 controller 、host 和 transport HCI 传输抽象层的东西。 此部分代码与 RT-Thread 基本没有耦合，属于协议栈本身代码；如果要同步到上游，这一部分文件基本都要同步。
+
+不过要注意 transport 下 RT-Thread UART 对接 HCI 的代码，如果 HCI 层框架改变了，则需要进行相应调整。
+
+## porting
+
+porting 目录如下
+
+```
+porting                /* OS 抽象层及系统配置 */
+    ├───nimble
+    │   ├───include
+    │   └───src
+    └───npl
+        └───rtthread       /* RT-Thread OS 接口实现 */
+            ├───include
+            │   ├───config /* NimBLE 协议栈配置选项 */
+            │   ├───console
+            │   └───nimble
+            └───src
+```
+
+基本是 OS 抽象层与 rtthread 的对接代码，包括系统配置等等。
+
+-   porting/nimble 目录下代码主要是定义 OS 抽象层框架 和 系统配置，可以同步到上游。
+-   npl/rtthread 则是 OS 抽象层对接 RT-Thread 的移植代码，一般保留不动，如遇到 bug 可能需要适当调整。
+
+## SConscript 文件
+
+SConscript 文件在 NimBLE 软件包根目录下，是 Scons 构建工具的构建描述文件。
+
+在同步上游代码后，需要针对实际编译情况对此文件进行相应修改，如移除某些文件，添加某些头文件路径，添加某些源文件加入编译等。