Release v1.2.0

Inc/Legacy/stm32_hal_legacy.h

@@ -472,7 +472,9 @@ extern "C" {
 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) 
 #define PAGESIZE                      FLASH_PAGE_SIZE
+#endif /* STM32F2 && STM32F4 && STM32F7 &&  STM32H7 && STM32H5 */
 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
@@ -536,6 +538,10 @@ extern "C" {
 #define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
 #define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
 #endif /* STM32H7 */
+#if defined(STM32H7RS)
+#define FLASH_OPTKEY1                 FLASH_OPT_KEY1
+#define FLASH_OPTKEY2                 FLASH_OPT_KEY2
+#endif /* STM32H7RS */
 #if defined(STM32U5)
 #define OB_USER_nRST_STOP             OB_USER_NRST_STOP
 #define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
@@ -601,6 +607,15 @@ extern "C" {
 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
 #endif /* STM32G4 */
 
+#if defined(STM32U5)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster                 HAL_SYSCFG_EnableIOAnalogBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster                HAL_SYSCFG_DisableIOAnalogBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection        HAL_SYSCFG_EnableIOAnalogVoltageSelection
+#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection       HAL_SYSCFG_DisableIOAnalogVoltageSelection
+
+#endif /* STM32U5 */
+
 #if defined(STM32H5)
 #define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC
 #define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC
@@ -875,6 +890,10 @@ extern "C" {
 #define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
 #define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
 
+#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
+#define HRTIMInterruptResquests  HRTIMInterruptRequests
+#endif /* STM32F3 || STM32G4 || STM32H7 */
+
 #if defined(STM32G4)
 #define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
 #define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
@@ -1012,8 +1031,8 @@ extern "C" {
 #define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
 #define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
 #define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
 #endif /* STM32F3 */
+
 /**
   * @}
   */
@@ -1264,10 +1283,10 @@ extern "C" {
 #define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
 
-#if defined(STM32H5) || defined(STM32H7RS)
+#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
 #define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
 #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
-#endif /* STM32H5 || STM32H7RS */
+#endif /* STM32H5 || STM32H7RS || STM32N6 */
 
 #if defined(STM32WBA)
 #define TAMP_SECRETDEVICE_ERASE_NONE            TAMP_DEVICESECRETS_ERASE_NONE
@@ -1279,27 +1298,27 @@ extern "C" {
 #define TAMP_SECRETDEVICE_ERASE_ALL             TAMP_DEVICESECRETS_ERASE_ALL
 #endif /* STM32WBA */
 
-#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
 #define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
 #define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
-#endif /* STM32H5 || STM32WBA || STM32H7RS */
+#endif /* STM32H5 || STM32WBA || STM32H7RS ||  STM32N6 */
 
-#if defined(STM32F7)
+#if defined(STM32F7) || defined(STM32WB)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
-#endif /* STM32F7 */
+#endif /* STM32F7 || STM32WB */
 
 #if defined(STM32H7)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
 #endif /* STM32H7 */
 
-#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
 #define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
 #define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
 #define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
 #define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 || STM32L0 */
+#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
 
 /**
   * @}
@@ -1466,7 +1485,7 @@ extern "C" {
 #define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
 #endif
 
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32MP2)
 #define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
 #define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
 #endif
@@ -2014,12 +2033,12 @@ extern "C" {
 /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
   * @{
   */
-#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
 #define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
 #define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
 #define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
 #define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
-#endif /* STM32H5 || STM32WBA || STM32H7RS */
+#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
 
 /**
   * @}
@@ -3680,8 +3699,8 @@ extern "C" {
 #endif
 
 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
-    defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || \
-    defined(STM32U0)
+      defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
+      defined(STM32U0)
 #define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
 #else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3932,7 +3951,8 @@ extern "C" {
   */
 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
     defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
-    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) ||  defined (STM32U0)
+    defined (STM32WBA) || defined (STM32H5) || \
+    defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif
@@ -4226,6 +4246,33 @@ extern "C" {
 
 #define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
 #define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+#if defined(STM32U5)
+#define USB_OTG_GOTGCTL_BSESVLD                            USB_OTG_GOTGCTL_BSVLD
+#define USB_OTG_GAHBCFG_GINT                               USB_OTG_GAHBCFG_GINTMSK
+#define USB_OTG_GUSBCFG_PHYLPCS                            USB_OTG_GUSBCFG_PHYLPC
+#define USB_OTG_GRSTCTL_HSRST                              USB_OTG_GRSTCTL_PSRST
+#define USB_OTG_GINTSTS_BOUTNAKEFF                         USB_OTG_GINTSTS_GONAKEFF
+#define USB_OTG_GINTSTS_WKUINT                             USB_OTG_GINTSTS_WKUPINT
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM                    USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
+#define USB_OTG_GRXSTSP_EPNUM                              USB_OTG_GRXSTSP_EPNUM_CHNUM
+#define USB_OTG_GLPMCFG_L1ResumeOK                         USB_OTG_GLPMCFG_L1RSMOK
+#define USB_OTG_HPTXFSIZ_PTXFD                             USB_OTG_HPTXFSIZ_PTXFSIZ
+#define USB_OTG_HCCHAR_MC                                  USB_OTG_HCCHAR_MCNT
+#define USB_OTG_HCCHAR_MC_0                                USB_OTG_HCCHAR_MCNT_0
+#define USB_OTG_HCCHAR_MC_1                                USB_OTG_HCCHAR_MCNT_1
+#define USB_OTG_HCINTMSK_AHBERR                            USB_OTG_HCINTMSK_AHBERRM
+#define USB_OTG_HCTSIZ_DOPING                              USB_OTG_HCTSIZ_DOPNG
+#define USB_OTG_DOEPMSK_OPEM                               USB_OTG_DOEPMSK_OUTPKTERRM
+#define USB_OTG_DIEPCTL_SODDFRM                            USB_OTG_DIEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DIEPTSIZ_MULCNT                            USB_OTG_DIEPTSIZ_MCNT
+#define USB_OTG_DOEPCTL_SODDFRM                            USB_OTG_DOEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DOEPCTL_DPID                               USB_OTG_DOEPCTL_DPID_EONUM
+#define USB_OTG_DOEPTSIZ_STUPCNT                           USB_OTG_DOEPTSIZ_RXDPID
+#define USB_OTG_DOEPTSIZ_STUPCNT_0                         USB_OTG_DOEPTSIZ_RXDPID_0
+#define USB_OTG_DOEPTSIZ_STUPCNT_1                         USB_OTG_DOEPTSIZ_RXDPID_1
+#define USB_OTG_PCGCCTL_STOPCLK                            USB_OTG_PCGCCTL_STPPCLK
+#define USB_OTG_PCGCCTL_GATECLK                            USB_OTG_PCGCCTL_GATEHCLK
+#endif
 /**
   * @}
   */

Inc/stm32h7rsxx_hal.h

@@ -60,6 +60,7 @@ typedef enum
   * @{
   */
 #define REV_ID_A 0x1003U  /*!< STM32H7Rx/Sx rev.A */
+#define REV_ID_B 0x2000U  /*!< STM32H7Rx/Sx rev.B */
 /**
   * @}
   */
@@ -71,7 +72,7 @@ typedef enum
   * @brief STM32H7RSxx HAL Driver version number
   */
 #define STM32H7RSXX_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define STM32H7RSXX_HAL_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */
+#define STM32H7RSXX_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
 #define STM32H7RSXX_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define STM32H7RSXX_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define STM32H7RSXX_HAL_VERSION        ((STM32H7RSXX_HAL_VERSION_MAIN  << 24U)\

Inc/stm32h7rsxx_hal_conf_template.h

@@ -79,6 +79,7 @@ extern "C" {
 #define HAL_RTC_MODULE_ENABLED
 #define HAL_SAI_MODULE_ENABLED
 #define HAL_SD_MODULE_ENABLED
+#define HAL_SDIO_MODULE_ENABLED
 #define HAL_SDRAM_MODULE_ENABLED
 #define HAL_SMARTCARD_MODULE_ENABLED
 #define HAL_SMBUS_MODULE_ENABLED
@@ -216,6 +217,7 @@ extern "C" {
 #define USE_HAL_RTC_REGISTER_CALLBACKS        0U
 #define USE_HAL_SAI_REGISTER_CALLBACKS        0U
 #define USE_HAL_SD_REGISTER_CALLBACKS         0U
+#define USE_HAL_SDIO_REGISTER_CALLBACKS       0U
 #define USE_HAL_SDRAM_REGISTER_CALLBACKS      0U
 #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
 #define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
@@ -258,6 +260,9 @@ extern "C" {
 
 #define USE_SD_TRANSCEIVER            0U
 
+/* ################## SDIO peripheral configuration ########################## */
+#define USE_SDIO_TRANSCEIVER          0U
+#define SDIO_MAX_IO_NUMBER            7U
 /* Includes ------------------------------------------------------------------*/
 /**
   * @brief Include module's header file
@@ -439,6 +444,10 @@ extern "C" {
 #include "stm32h7rsxx_hal_sd.h"
 #endif /* HAL_SD_MODULE_ENABLED */
 
+#ifdef HAL_SDIO_MODULE_ENABLED
+#include "stm32h7rsxx_hal_sdio.h"
+#endif /* HAL_SDIO_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
 #include "stm32h7rsxx_hal_sdram.h"
 #endif /* HAL_SDRAM_MODULE_ENABLED */

Inc/stm32h7rsxx_hal_cryp.h

@@ -726,7 +726,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, const CRYP_ConfigTypeDef *pConf);
 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,

Inc/stm32h7rsxx_hal_dcmipp.h

@@ -906,13 +906,11 @@ uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp);
 #define IS_DCMIPP_LINE_SELECT_START(LINE__START)(((LINE__START) == DCMIPP_OELS_ODD) ||\
                                                  ((LINE__START) == DCMIPP_OELS_EVEN))
 
-
 #define IS_DCMIPP_MEMORY_ADDRESS(MEMORY_ADDRESS) (((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_0) ||\
                                                   ((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_1))
 
 #define IS_DCMIPP_DATA_LIMIT(DATA_LIMIT) (((DATA_LIMIT) >=1U ) && ((DATA_LIMIT) <= 0xFFFFFFU))
 
-
 #define IS_DCMIPP_PIPE_MULTILINE(MULTILINE) (((MULTILINE) == DCMIPP_MULTILINE_1_LINE )   ||\
                                              ((MULTILINE) == DCMIPP_MULTILINE_2_LINES)  ||\
                                              ((MULTILINE) == DCMIPP_MULTILINE_4_LINES)  ||\

Inc/stm32h7rsxx_hal_eth.h

@@ -105,7 +105,7 @@ typedef struct
 
   uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
 
-  uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
+  uint32_t *CurrentPacketAddress;           /*<! Current transmit packet addresses */
 
   uint32_t BuffersInUse;                   /*<! Buffers in Use */
 
@@ -1798,6 +1798,7 @@ uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
 uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
 uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
 uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
 /**
   * @}
   */

Inc/stm32h7rsxx_hal_flash.h

@@ -448,8 +448,8 @@ typedef struct
 #define FLASH_KEY2                   0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
                                                       to unlock the FLASH registers access */
 
-#define FLASH_OPTKEY1                0x08192A3BU /*!< Flash option byte key1 */
-#define FLASH_OPTKEY2                0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
+#define FLASH_OPT_KEY1                0x08192A3BU /*!< Flash option byte key1 */
+#define FLASH_OPT_KEY2                0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPT_KEY1
                                                       to allow option bytes operations */
 /**
   * @}

Inc/stm32h7rsxx_hal_hash.h

@@ -296,11 +296,13 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash);  /*!< pointer
   *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
   *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
   *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) > 8U)  ?                    \
-                                                    (((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
-                                                    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
+#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) > 8U)  ?                           \
+                                                    ((((__HANDLE__)->Instance->CR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) :                     \
+                                                    ((((__HANDLE__)->Instance->SR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) )
 
 /** @brief  Clear the specified HASH flag.
   * @param  __HANDLE__ specifies the HASH handle.
@@ -394,7 +396,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
 HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
-HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

Inc/stm32h7rsxx_hal_i2s.h

@@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
 
+/* IO Swap feature */
+HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s);
+uint32_t          HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s);
+
 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);

Inc/stm32h7rsxx_hal_mmc.h

@@ -717,9 +717,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti
   * @{
   */
 HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
 HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
 /**
   * @}

Inc/stm32h7rsxx_hal_mmc_ex.h

@@ -69,9 +69,11 @@ extern "C" {
 /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
   * @{
   */
-HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc,
+                                                     const MMC_DMALinkedListTypeDef *pLinkedList,
                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc,
+                                                      const MMC_DMALinkedListTypeDef *pLinkedList,
                                                       uint32_t BlockAdd, uint32_t NumberOfBlocks);
 
 HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,

Inc/stm32h7rsxx_hal_pcd_ex.h

@@ -45,7 +45,6 @@ extern "C" {
 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
   * @{
   */
-
 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);

Inc/stm32h7rsxx_hal_pka.h

@@ -107,6 +107,9 @@ typedef struct
   PKA_TypeDef                   *Instance;              /*!< Register base address */
   __IO HAL_PKA_StateTypeDef     State;                  /*!< PKA state */
   __IO uint32_t                 ErrorCode;              /*!< PKA Error code */
+  __IO uint32_t                 primeordersize;         /*!< Elliptic curve prime order length */
+  __IO uint32_t                 opsize;                 /*!< Modular exponentiation operand length */
+  __IO uint32_t                 modulussize;            /*!< Elliptic curve modulus length */
 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
   void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
   void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka);         /*!< PKA Error callback            */

Inc/stm32h7rsxx_hal_rng.h

@@ -178,6 +178,7 @@ typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
 #define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
 #define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
 #define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
+#define  HAL_RNG_ERROR_RECOVERSEED      0x00000020U    /*!< Recover Seed error */
 /**
   * @}
   */

Inc/stm32h7rsxx_hal_sd.h

@@ -687,10 +687,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
   * @{
   */
 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
 HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
 HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
 /**
   * @}
   */

Inc/stm32h7rsxx_hal_sd_ex.h

@@ -69,9 +69,9 @@ extern "C" {
 /** @defgroup SDEx_Exported_Functions_Group1 Linked List functions
   * @{
   */
-HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList,
                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList,
                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks);
 
 HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf);

Inc/stm32h7rsxx_hal_sdio.h

@@ -0,0 +1,601 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32h7rsxx_hal_sdio.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDIO HAL module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32H7RSxx_HAL_SDIO_H
+#define STM32H7RSxx_HAL_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32h7rsxx_ll_sdmmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+
+/** @defgroup SDIO SDIO
+  * @brief SDIO HAL module driver
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Types SDIO Exported Types
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure
+  * @{
+
+  */
+typedef enum
+{
+  HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */
+  HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us    */
+  HAL_SDIO_STATE_BUSY  = 0x02U, /*!< SDIO process ongoing                 */
+} HAL_SDIO_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition
+  * @{
+  */
+/**
+  * @brief  SDIO Card Common Control Register Structure definition
+  */
+typedef struct
+{
+  uint8_t sdio_revision;     /*!< SDIO revision                */
+  uint8_t cccr_revision;     /*!< CCCR version                 */
+  uint8_t sd_spec_revision;  /*!< SD revision                  */
+  uint8_t bus_width_8Bit;    /*!< SDIO bus width 8 bit support */
+  uint32_t card_capability;  /*!< SDIO card capability         */
+  uint32_t commonCISPointer; /*!< point to common CIS          */
+} HAL_SDIO_CCCR_TypeDef;
+
+/**
+  * @brief sdio card FBR register(Function Basic Register)
+  */
+typedef struct
+{
+  uint8_t flags;             /*!< SDIO current IO flags                  */
+  uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */
+  uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */
+  uint32_t ioPointerToCIS;   /*!< SDIO current IO pointer to CIS         */
+  uint32_t ioPointerToCSA;   /*!< SDIO current IO pointer to CSA         */
+} HAL_SDIO_FBR_t;
+
+/**
+  * @brief  SDIO CMD52 Structure definition
+  */
+typedef struct
+{
+  uint32_t Reg_Addr;       /*!< This is the address of the byte of data inside of the selected function to read or write */
+  uint8_t  ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only.                     */
+  uint8_t  IOFunctionNbr;  /*!< The number of the function within the IO card you wish to read or write                  */
+} HAL_SDIO_DirectCmd_TypeDef;
+
+/**
+  * @brief  SDIO CMD53 Structure definition
+  */
+typedef struct
+{
+  uint32_t Reg_Addr;      /*!< This is the address of the byte of data inside of the selected function to read or write */
+  uint32_t OpCode;        /*!< Read/Write operation mode                                                                */
+  uint32_t Block_Mode;    /*!< Bytes or Blocks mode                                                                     */
+  uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write                  */
+} HAL_SDIO_ExtendedCmd_TypeDef;
+
+#define SDIO_InitTypeDef      SDMMC_InitTypeDef
+#define SDIO_TypeDef          SDMMC_TypeDef
+
+/**
+  * @brief  SDIO handle Structure definition
+  */
+typedef struct __SDIO_HandleTypeDef
+{
+  SDIO_TypeDef                   *Instance;        /*!< SDIO registers base address                             */
+
+  SDIO_InitTypeDef               Init;              /*!< SDIO required parameters                               */
+
+  HAL_LockTypeDef                Lock;              /*!< SDIO locking object                                    */
+
+  uint8_t                        *pTxBuffPtr;       /*!< Pointer to SDIO Tx transfer Buffer                     */
+
+  uint32_t                       TxXferSize;        /*!< SDIO Tx Transfer size                                  */
+
+  uint8_t                        *pRxBuffPtr;       /*!< Pointer to SDIO Rx transfer Buffer                     */
+
+  uint32_t                       RxXferSize;        /*!< SDIO Rx Transfer size                                  */
+
+  uint32_t                       remaining_data;    /*!< Remaining data to transfer                             */
+
+  uint32_t                       next_data_addr;    /*!< SDIO Next data address                                 */
+
+  __IO uint32_t                  next_reg_addr;     /*!< SDIO Next register address                             */
+
+  uint16_t                       block_size;        /*!< SDIO Block size                                        */
+
+  __IO uint32_t                  Context;           /*!< SDIO transfer context                                  */
+
+  __IO HAL_SDIO_StateTypeDef     State;             /*!< SDIO card State                                        */
+
+  __IO uint32_t                  ErrorCode;         /*!< SDIO Card Error codes                                  */
+
+  uint8_t                        IOFunctionMask;    /*!< SDIO used to record current enabled io interrupt       */
+
+  volatile uint8_t               IOInterruptNbr;    /*!< SDIO used to record total enabled io interrupt numbers */
+
+  void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func);
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+  void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+  HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio);
+
+} SDIO_HandleTypeDef;
+
+/**
+  * @}
+  */
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_SDIO_TX_CPLT_CB_ID    = 0x00U,  /*!< SDIO Tx Complete Callback ID */
+  HAL_SDIO_RX_CPLT_CB_ID    = 0x01U,  /*!< SDIO Rx Complete Callback ID */
+  HAL_SDIO_ERROR_CB_ID      = 0x02U,  /*!< SDIO Error Callback ID       */
+  HAL_SDIO_MSP_INIT_CB_ID   = 0x10U,  /*!< SDIO MspInit Callback ID     */
+  HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U   /*!< SDIO MspDeInit Callback ID   */
+} HAL_SDIO_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition
+  * @{
+  */
+typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio);
+typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func);
+/**
+  * @}
+  */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Constants SDIO Exported Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition
+  * @{
+  */
+#define HAL_SDIO_ERROR_NONE             SDMMC_ERROR_NONE              /*!< No error                                    */
+#define HAL_SDIO_ERROR_DATA_CRC_FAIL    SDMMC_ERROR_DATA_CRC_FAIL     /*!< Data block sent/received (CRC check failed) */
+#define HAL_SDIO_ERROR_DATA_TIMEOUT     SDMMC_ERROR_DATA_TIMEOUT      /*!< Data timeout                                */
+#define HAL_SDIO_ERROR_TX_UNDERRUN      SDMMC_ERROR_TX_UNDERRUN       /*!< Transmit FIFO underrun                      */
+#define HAL_SDIO_ERROR_RX_OVERRUN       SDMMC_ERROR_RX_OVERRUN        /*!< Receive FIFO overrun                        */
+#define HAL_SDIO_ERROR_TIMEOUT          SDMMC_ERROR_TIMEOUT           /*!< Timeout error                               */
+#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error                      */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration
+  * @{
+  */
+#define SDIO_CONTEXT_NONE                 0x00U /*!< None                             */
+#define SDIO_CONTEXT_READ_SINGLE_BLOCK    0x01U /*!< Read single block operation      */
+#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK  0x02U /*!< Read multiple blocks operation   */
+#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK   0x10U /*!< Write single block operation     */
+#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation  */
+#define SDIO_CONTEXT_IT                   0x08U /*!< Process in Interrupt mode        */
+#define SDIO_CONTEXT_DMA                  0x80U /*!< Process in DMA mode              */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration
+  * @{
+  */
+#define HAL_SDIO_MODE_BYTE   SDMMC_SDIO_MODE_BYTE
+#define HAL_SDIO_MODE_BLOCK  SDMMC_SDIO_MODE_BLOCK
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration
+  * @{
+  */
+#define HAL_SDIO_OP_CODE_NO_INC    SDMMC_SDIO_NO_INC
+#define HAL_SDIO_OP_CODE_AUTO_INC  SDMMC_SDIO_AUTO_INC
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration
+  * @{
+  */
+#define HAL_SDIO_WRITE_ONLY       SDMMC_SDIO_WO  /*!< SDIO Write only       */
+#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration
+  * @{
+  */
+#define HAL_SDIO_1_WIRE_MODE   0U /*!< SDIO wire support 1 wire  */
+#define HAL_SDIO_4_WIRES_MODE  1U /*!< SDIO wire support 4 wires */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration
+  * @{
+  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE     1U    /*!< SDIO data block size 1 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE     2U    /*!< SDIO data block size 2 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE     4U    /*!< SDIO data block size 4 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE     8U    /*!< SDIO data block size 8 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE    16U   /*!< SDIO data block size 16 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE    32U   /*!< SDIO data block size 32 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE    64U   /*!< SDIO data block size 64 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE   128U  /*!< SDIO data block size 128 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE   256U  /*!< SDIO data block size 256 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE   512U  /*!< SDIO data block size 512 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE  1024U /*!< SDIO data block size 1024 byte */
+#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE  2048U /*!< SDIO data block size 2048 byte */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration
+  * @{
+  */
+#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */
+#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED     1U /*!< SDIO bus width 8 bit is supported     */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions
+  * @{
+  */
+#define HAL_SDIOS_DATA_RATE_SDR12  0U /*!< SDIO Data rate SDR12 */
+#define HAL_SDIOS_DATA_RATE_SDR25  1U /*!< SDIO Data rate SDR25 */
+#define HAL_SDIOS_DATA_RATE_SDR50  2U /*!< SDIO Data rate SDR50 */
+#define HAL_SDIOS_DATA_RATE_DDR50  3U /*!< SDIO Data rate DDR50 */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions
+  * @{
+  */
+#define HAL_SDIO_FUNCTION_0  0U /*!< SDIO function 0 */
+#define HAL_SDIO_FUNCTION_1  1U /*!< SDIO function 1 */
+#define HAL_SDIO_FUNCTION_2  2U /*!< SDIO function 2 */
+#define HAL_SDIO_FUNCTION_3  3U /*!< SDIO function 3 */
+#define HAL_SDIO_FUNCTION_4  4U /*!< SDIO function 4 */
+#define HAL_SDIO_FUNCTION_5  5U /*!< SDIO function 5 */
+#define HAL_SDIO_FUNCTION_6  6U /*!< SDIO function 6 */
+#define HAL_SDIO_FUNCTION_7  7U /*!< SDIO function 7 */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions
+  * @{
+  */
+#define HAL_SDIO_FBR_SUPPORT_CSA             1U /*!< SDIO function support CSA             */
+#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_macros SDIO Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+/**
+  * @brief  Enable the SDIO device interrupt.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources.
+  * @retval None
+  */
+#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDIO device interrupt.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources.
+  * @retval None
+  */
+#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SDIO flag is set or not.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of @ref SDMMC_LL_Flags.
+  * @retval The new state of SDIO FLAG (SET or RESET).
+  */
+#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SDIO's pending flags.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of @ref SDMMC_LL_Flags.
+  * @retval None
+  */
+#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SDIO interrupt has occurred or not.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of @ref SDMMC_LL_Interrupt_sources.
+  * @retval The new state of SDIO IT (SET or RESET).
+  */
+#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt is enabled or not.
+  * @param  __HANDLE__    : SDIO handle.
+  * @param  __INTERRUPT__ : specifies the SDMMC interrupt source to check.
+  * @retval The state of SDIO IT (SET or RESET).
+  */
+#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
+  * @{
+  */
+/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio);
+
+void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide);
+HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed);
+
+HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize);
+HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate);
+
+HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr);
+HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group3 Process functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData);
+HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data);
+
+HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                        uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);
+
+HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                         uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);
+
+HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                            uint8_t *pData, uint32_t Size_byte);
+
+HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                             uint8_t *pData, uint32_t Size_byte);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions
+  * @{
+  */
+void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio);
+
+void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func);
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/* Callback to switch in 1.8V mode */
+void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID,
+                                            pSDIO_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio,
+                                                       pSDIO_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction,
+                                                      HAL_SDIO_IOFunction_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio,
+                                                        pSDIO_IdentifyCardCallbackTypeDef pCallback);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio);
+uint32_t              HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio);
+
+/**
+  * @}
+  */
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Types SDIO Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines ---------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Defines SDIO Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Variables SDIO Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Constants SDIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Macros SDIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes --------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions SDIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7RSxx_HAL_SDIO_H */
+

Inc/stm32h7rsxx_hal_spi.h

@@ -1083,6 +1083,9 @@ uint32_t             HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
                                                     ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
                                                     ((LENGTH) == SPI_CRC_LENGTH_4BIT))
 
+
+#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE)         (((SIZE) < 0x3FFU) && ((SIZE) != 0U))
+
 /**
   * @brief  CRC Length for limited instance
   */
@@ -1092,6 +1095,8 @@ uint32_t             HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
 
 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)          ((POLYNOMIAL) > 0x0UL)
 
+#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL)
+
 
 
 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)            (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
@@ -1105,6 +1110,8 @@ uint32_t             HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
 
 #define IS_SPI_MASTER_RX_AUTOSUSP(MODE)            (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \
                                                     ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE))
+
+#define IS_SPI_TRANSFER_SIZE(SIZE)                 (((SIZE) < 0xFFFFU) && ((SIZE) != 0U))
 /**
   * @}
   */

Inc/stm32h7rsxx_hal_xspi.h

@@ -373,38 +373,38 @@ typedef struct
 /** @defgroup XSPI_MemorySize XSPI Memory Size
   * @{
   */
-#define HAL_XSPI_SIZE_16B                    (0x00000000U)  /*!<  16 bits  (  2  Byte = 2^( 0+1)) */
-#define HAL_XSPI_SIZE_32B                    (0x00000001U)  /*!<  32 bits  (  4  Byte = 2^( 1+1)) */
-#define HAL_XSPI_SIZE_64B                    (0x00000002U)  /*!<  64 bits  (  8  Byte = 2^( 2+1)) */
-#define HAL_XSPI_SIZE_128B                   (0x00000003U)  /*!< 128 bits  ( 16  Byte = 2^( 3+1)) */
-#define HAL_XSPI_SIZE_256B                   (0x00000004U)  /*!< 256 bits  ( 32  Byte = 2^( 4+1)) */
-#define HAL_XSPI_SIZE_512B                   (0x00000005U)  /*!< 512 bits  ( 64  Byte = 2^( 5+1)) */
-#define HAL_XSPI_SIZE_1KB                    (0x00000006U)  /*!<   1 Kbits (128  Byte = 2^( 6+1)) */
-#define HAL_XSPI_SIZE_2KB                    (0x00000007U)  /*!<   2 Kbits (256  Byte = 2^( 7+1)) */
-#define HAL_XSPI_SIZE_4KB                    (0x00000008U)  /*!<   4 Kbits (512  Byte = 2^( 8+1)) */
-#define HAL_XSPI_SIZE_8KB                    (0x00000009U)  /*!<   8 Kbits (  1 KByte = 2^( 9+1)) */
-#define HAL_XSPI_SIZE_16KB                   (0x0000000AU)  /*!<  16 Kbits (  2 KByte = 2^(10+1)) */
-#define HAL_XSPI_SIZE_32KB                   (0x0000000BU)  /*!<  32 Kbits (  4 KByte = 2^(11+1)) */
-#define HAL_XSPI_SIZE_64KB                   (0x0000000CU)  /*!<  64 Kbits (  8 KByte = 2^(12+1)) */
-#define HAL_XSPI_SIZE_128KB                  (0x0000000DU)  /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */
-#define HAL_XSPI_SIZE_256KB                  (0x0000000EU)  /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */
-#define HAL_XSPI_SIZE_512KB                  (0x0000000FU)  /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */
-#define HAL_XSPI_SIZE_1MB                    (0x00000010U)  /*!<   1 Mbits (128 KByte = 2^(16+1)) */
-#define HAL_XSPI_SIZE_2MB                    (0x00000011U)  /*!<   2 Mbits (256 KByte = 2^(17+1)) */
-#define HAL_XSPI_SIZE_4MB                    (0x00000012U)  /*!<   4 Mbits (512 KByte = 2^(18+1)) */
-#define HAL_XSPI_SIZE_8MB                    (0x00000013U)  /*!<   8 Mbits (  1 MByte = 2^(19+1)) */
-#define HAL_XSPI_SIZE_16MB                   (0x00000014U)  /*!<  16 Mbits (  2 MByte = 2^(20+1)) */
-#define HAL_XSPI_SIZE_32MB                   (0x00000015U)  /*!<  32 Mbits (  4 MByte = 2^(21+1)) */
-#define HAL_XSPI_SIZE_64MB                   (0x00000016U)  /*!<  64 Mbits (  8 MByte = 2^(22+1)) */
-#define HAL_XSPI_SIZE_128MB                  (0x00000017U)  /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */
-#define HAL_XSPI_SIZE_256MB                  (0x00000018U)  /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */
-#define HAL_XSPI_SIZE_512MB                  (0x00000019U)  /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */
-#define HAL_XSPI_SIZE_1GB                    (0x0000001AU)  /*!<   1 Gbits (128 MByte = 2^(26+1)) */
-#define HAL_XSPI_SIZE_2GB                    (0x0000001BU)  /*!<   2 Gbits (256 MByte = 2^(27+1)) */
-#define HAL_XSPI_SIZE_4GB                    (0x0000001CU)  /*!<   4 Gbits (256 MByte = 2^(28+1)) */
-#define HAL_XSPI_SIZE_8GB                    (0x0000001DU)  /*!<   8 Gbits (256 MByte = 2^(29+1)) */
-#define HAL_XSPI_SIZE_16GB                   (0x0000001EU)  /*!<  16 Gbits (256 MByte = 2^(30+1)) */
-#define HAL_XSPI_SIZE_32GB                   (0x0000001FU)  /*!<  32 Gbits (256 MByte = 2^(31+1)) */
+#define HAL_XSPI_SIZE_16B                    (0x00000000U)  /*!<  16 bits  (  2  Bytes = 2^( 0+1)) */
+#define HAL_XSPI_SIZE_32B                    (0x00000001U)  /*!<  32 bits  (  4  Bytes = 2^( 1+1)) */
+#define HAL_XSPI_SIZE_64B                    (0x00000002U)  /*!<  64 bits  (  8  Bytes = 2^( 2+1)) */
+#define HAL_XSPI_SIZE_128B                   (0x00000003U)  /*!< 128 bits  ( 16  Bytes = 2^( 3+1)) */
+#define HAL_XSPI_SIZE_256B                   (0x00000004U)  /*!< 256 bits  ( 32  Bytes = 2^( 4+1)) */
+#define HAL_XSPI_SIZE_512B                   (0x00000005U)  /*!< 512 bits  ( 64  Bytes = 2^( 5+1)) */
+#define HAL_XSPI_SIZE_1KB                    (0x00000006U)  /*!<   1 Kbits (128  Bytes = 2^( 6+1)) */
+#define HAL_XSPI_SIZE_2KB                    (0x00000007U)  /*!<   2 Kbits (256  Bytes = 2^( 7+1)) */
+#define HAL_XSPI_SIZE_4KB                    (0x00000008U)  /*!<   4 Kbits (512  Bytes = 2^( 8+1)) */
+#define HAL_XSPI_SIZE_8KB                    (0x00000009U)  /*!<   8 Kbits (  1 KBytes = 2^( 9+1)) */
+#define HAL_XSPI_SIZE_16KB                   (0x0000000AU)  /*!<  16 Kbits (  2 KBytes = 2^(10+1)) */
+#define HAL_XSPI_SIZE_32KB                   (0x0000000BU)  /*!<  32 Kbits (  4 KBytes = 2^(11+1)) */
+#define HAL_XSPI_SIZE_64KB                   (0x0000000CU)  /*!<  64 Kbits (  8 KBytes = 2^(12+1)) */
+#define HAL_XSPI_SIZE_128KB                  (0x0000000DU)  /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */
+#define HAL_XSPI_SIZE_256KB                  (0x0000000EU)  /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */
+#define HAL_XSPI_SIZE_512KB                  (0x0000000FU)  /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */
+#define HAL_XSPI_SIZE_1MB                    (0x00000010U)  /*!<   1 Mbits (128 KBytes = 2^(16+1)) */
+#define HAL_XSPI_SIZE_2MB                    (0x00000011U)  /*!<   2 Mbits (256 KBytes = 2^(17+1)) */
+#define HAL_XSPI_SIZE_4MB                    (0x00000012U)  /*!<   4 Mbits (512 KBytes = 2^(18+1)) */
+#define HAL_XSPI_SIZE_8MB                    (0x00000013U)  /*!<   8 Mbits (  1 MBytes = 2^(19+1)) */
+#define HAL_XSPI_SIZE_16MB                   (0x00000014U)  /*!<  16 Mbits (  2 MBytes = 2^(20+1)) */
+#define HAL_XSPI_SIZE_32MB                   (0x00000015U)  /*!<  32 Mbits (  4 MBytes = 2^(21+1)) */
+#define HAL_XSPI_SIZE_64MB                   (0x00000016U)  /*!<  64 Mbits (  8 MBytes = 2^(22+1)) */
+#define HAL_XSPI_SIZE_128MB                  (0x00000017U)  /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */
+#define HAL_XSPI_SIZE_256MB                  (0x00000018U)  /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */
+#define HAL_XSPI_SIZE_512MB                  (0x00000019U)  /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */
+#define HAL_XSPI_SIZE_1GB                    (0x0000001AU)  /*!<   1 Gbits (128 MBytes = 2^(26+1)) */
+#define HAL_XSPI_SIZE_2GB                    (0x0000001BU)  /*!<   2 Gbits (256 MBytes = 2^(27+1)) */
+#define HAL_XSPI_SIZE_4GB                    (0x0000001CU)  /*!<   4 Gbits (512 MBytes = 2^(28+1)) */
+#define HAL_XSPI_SIZE_8GB                    (0x0000001DU)  /*!<   8 Gbits (  1 GBytes = 2^(29+1)) */
+#define HAL_XSPI_SIZE_16GB                   (0x0000001EU)  /*!<  16 Gbits (  2 GBytes = 2^(30+1)) */
+#define HAL_XSPI_SIZE_32GB                   (0x0000001FU)  /*!<  32 Gbits (  4 GBytes = 2^(31+1)) */
 /**
   * @}
   */
@@ -460,38 +460,38 @@ typedef struct
 /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary
   * @{
   */
-#define HAL_XSPI_BONDARYOF_NONE              (0x00000000U)  /*!     CS boundary disabled        */
-#define HAL_XSPI_BONDARYOF_16B               (0x00000001U)  /*!<  16 bits  (  2  Byte = 2^(1))  */
-#define HAL_XSPI_BONDARYOF_32B               (0x00000002U)  /*!<  32 bits  (  4  Byte = 2^(2))  */
-#define HAL_XSPI_BONDARYOF_64B               (0x00000003U)  /*!<  64 bits  (  8  Byte = 2^(3))  */
-#define HAL_XSPI_BONDARYOF_128B              (0x00000004U)  /*!< 128 bits  ( 16  Byte = 2^(4))  */
-#define HAL_XSPI_BONDARYOF_256B              (0x00000005U)  /*!< 256 bits  ( 32  Byte = 2^(5))  */
-#define HAL_XSPI_BONDARYOF_512B              (0x00000006U)  /*!< 512 bits  ( 64  Byte = 2^(6))  */
-#define HAL_XSPI_BONDARYOF_1KB               (0x00000007U)  /*!<   1 Kbits (128  Byte = 2^(7))  */
-#define HAL_XSPI_BONDARYOF_2KB               (0x00000008U)  /*!<   2 Kbits (256  Byte = 2^(8))  */
-#define HAL_XSPI_BONDARYOF_4KB               (0x00000009U)  /*!<   4 Kbits (512  Byte = 2^(9))  */
-#define HAL_XSPI_BONDARYOF_8KB               (0x0000000AU)  /*!<   8 Kbits (  1 KByte = 2^(10)) */
-#define HAL_XSPI_BONDARYOF_16KB              (0x0000000BU)  /*!<  16 Kbits (  2 KByte = 2^(11)) */
-#define HAL_XSPI_BONDARYOF_32KB              (0x0000000CU)  /*!<  32 Kbits (  4 KByte = 2^(12)) */
-#define HAL_XSPI_BONDARYOF_64KB              (0x0000000DU)  /*!< 64 Kbits  (  8 KByte = 2^(13)) */
-#define HAL_XSPI_BONDARYOF_128KB             (0x0000000EU)  /*!< 128 Kbits ( 16 KByte = 2^(14)) */
-#define HAL_XSPI_BONDARYOF_256KB             (0x0000000FU)  /*!< 256 Kbits ( 32 KByte = 2^(15)) */
-#define HAL_XSPI_BONDARYOF_512KB             (0x00000010U)  /*!< 512 Kbits ( 64 KByte = 2^(16)) */
-#define HAL_XSPI_BONDARYOF_1MB               (0x00000011U)  /*!<   1 Mbits (128 KByte = 2^(17)) */
-#define HAL_XSPI_BONDARYOF_2MB               (0x00000012U)  /*!<   2 Mbits (256 KByte = 2^(18)) */
-#define HAL_XSPI_BONDARYOF_4MB               (0x00000013U)  /*!<   4 Mbits (512 KByte = 2^(19)) */
-#define HAL_XSPI_BONDARYOF_8MB               (0x00000014U)  /*!<   8 Mbits (  1 MByte = 2^(20)) */
-#define HAL_XSPI_BONDARYOF_16MB              (0x00000015U)  /*!<  16 Mbits (  2 MByte = 2^(21)) */
-#define HAL_XSPI_BONDARYOF_32MB              (0x00000016U)  /*!<  32 Mbits (  4 MByte = 2^(22)) */
-#define HAL_XSPI_BONDARYOF_64MB              (0x00000017U)  /*!<  64 Mbits (  8 MByte = 2^(23)) */
-#define HAL_XSPI_BONDARYOF_128MB             (0x00000018U)  /*!< 128 Mbits ( 16 MByte = 2^(24)) */
-#define HAL_XSPI_BONDARYOF_256MB             (0x00000019U)  /*!< 256 Mbits ( 32 MByte = 2^(25)) */
-#define HAL_XSPI_BONDARYOF_512MB             (0x0000001AU)  /*!< 512 Mbits ( 64 MByte = 2^(26)) */
-#define HAL_XSPI_BONDARYOF_1GB               (0x0000001BU)  /*!<   1 Gbits (128 MByte = 2^(27)) */
-#define HAL_XSPI_BONDARYOF_2GB               (0x0000001CU)  /*!<   2 Gbits (256 MByte = 2^(28)) */
-#define HAL_XSPI_BONDARYOF_4GB               (0x0000001DU)  /*!<   4 Gbits (512 MByte = 2^(29)) */
-#define HAL_XSPI_BONDARYOF_8GB               (0x0000001EU)  /*!<   8 Gbits (  1 GByte = 2^(30)) */
-#define HAL_XSPI_BONDARYOF_16GB              (0x0000001FU)  /*!<  16 Gbits (  2 GByte = 2^(31)) */
+#define HAL_XSPI_BONDARYOF_NONE              (0x00000000U)  /*!     CS boundary disabled         */
+#define HAL_XSPI_BONDARYOF_16B               (0x00000001U)  /*!<  16 bits  (  2  Bytes = 2^(1))  */
+#define HAL_XSPI_BONDARYOF_32B               (0x00000002U)  /*!<  32 bits  (  4  Bytes = 2^(2))  */
+#define HAL_XSPI_BONDARYOF_64B               (0x00000003U)  /*!<  64 bits  (  8  Bytes = 2^(3))  */
+#define HAL_XSPI_BONDARYOF_128B              (0x00000004U)  /*!< 128 bits  ( 16  Bytes = 2^(4))  */
+#define HAL_XSPI_BONDARYOF_256B              (0x00000005U)  /*!< 256 bits  ( 32  Bytes = 2^(5))  */
+#define HAL_XSPI_BONDARYOF_512B              (0x00000006U)  /*!< 512 bits  ( 64  Bytes = 2^(6))  */
+#define HAL_XSPI_BONDARYOF_1KB               (0x00000007U)  /*!<   1 Kbits (128  Bytes = 2^(7))  */
+#define HAL_XSPI_BONDARYOF_2KB               (0x00000008U)  /*!<   2 Kbits (256  Bytes = 2^(8))  */
+#define HAL_XSPI_BONDARYOF_4KB               (0x00000009U)  /*!<   4 Kbits (512  Bytes = 2^(9))  */
+#define HAL_XSPI_BONDARYOF_8KB               (0x0000000AU)  /*!<   8 Kbits (  1 KBytes = 2^(10)) */
+#define HAL_XSPI_BONDARYOF_16KB              (0x0000000BU)  /*!<  16 Kbits (  2 KBytes = 2^(11)) */
+#define HAL_XSPI_BONDARYOF_32KB              (0x0000000CU)  /*!<  32 Kbits (  4 KBytes = 2^(12)) */
+#define HAL_XSPI_BONDARYOF_64KB              (0x0000000DU)  /*!<  64 Kbits (  8 KBytes = 2^(13)) */
+#define HAL_XSPI_BONDARYOF_128KB             (0x0000000EU)  /*!< 128 Kbits ( 16 KBytes = 2^(14)) */
+#define HAL_XSPI_BONDARYOF_256KB             (0x0000000FU)  /*!< 256 Kbits ( 32 KBytes = 2^(15)) */
+#define HAL_XSPI_BONDARYOF_512KB             (0x00000010U)  /*!< 512 Kbits ( 64 KBytes = 2^(16)) */
+#define HAL_XSPI_BONDARYOF_1MB               (0x00000011U)  /*!<   1 Mbits (128 KBytes = 2^(17)) */
+#define HAL_XSPI_BONDARYOF_2MB               (0x00000012U)  /*!<   2 Mbits (256 KBytes = 2^(18)) */
+#define HAL_XSPI_BONDARYOF_4MB               (0x00000013U)  /*!<   4 Mbits (512 KBytes = 2^(19)) */
+#define HAL_XSPI_BONDARYOF_8MB               (0x00000014U)  /*!<   8 Mbits (  1 MBytes = 2^(20)) */
+#define HAL_XSPI_BONDARYOF_16MB              (0x00000015U)  /*!<  16 Mbits (  2 MBytes = 2^(21)) */
+#define HAL_XSPI_BONDARYOF_32MB              (0x00000016U)  /*!<  32 Mbits (  4 MBytes = 2^(22)) */
+#define HAL_XSPI_BONDARYOF_64MB              (0x00000017U)  /*!<  64 Mbits (  8 MBytes = 2^(23)) */
+#define HAL_XSPI_BONDARYOF_128MB             (0x00000018U)  /*!< 128 Mbits ( 16 MBytes = 2^(24)) */
+#define HAL_XSPI_BONDARYOF_256MB             (0x00000019U)  /*!< 256 Mbits ( 32 MBytes = 2^(25)) */
+#define HAL_XSPI_BONDARYOF_512MB             (0x0000001AU)  /*!< 512 Mbits ( 64 MBytes = 2^(26)) */
+#define HAL_XSPI_BONDARYOF_1GB               (0x0000001BU)  /*!<   1 Gbits (128 MBytes = 2^(27)) */
+#define HAL_XSPI_BONDARYOF_2GB               (0x0000001CU)  /*!<   2 Gbits (256 MBytes = 2^(28)) */
+#define HAL_XSPI_BONDARYOF_4GB               (0x0000001DU)  /*!<   4 Gbits (512 MBytes = 2^(29)) */
+#define HAL_XSPI_BONDARYOF_8GB               (0x0000001EU)  /*!<   8 Gbits (  1 GBytes = 2^(30)) */
+#define HAL_XSPI_BONDARYOF_16GB              (0x0000001FU)  /*!<  16 Gbits (  2 GBytes = 2^(31)) */
 /**
   * @}
   */

Inc/stm32h7rsxx_ll_cortex.h

@@ -171,7 +171,6 @@ extern "C" {
 #define LL_MPU_TEX_LEVEL0                  (0U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
 #define LL_MPU_TEX_LEVEL1                  (1U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
 #define LL_MPU_TEX_LEVEL2                  (2U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  (4U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 /**
   * @}
   */
@@ -640,7 +639,7 @@ __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
   *           or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE

Inc/stm32h7rsxx_ll_lpuart.h

@@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] =
   (uint16_t)32,
   (uint16_t)64,
   (uint16_t)128,
+  (uint16_t)256,
+  (uint16_t)256,
+  (uint16_t)256,
+  (uint16_t)256,
   (uint16_t)256
 };
 /**

Inc/stm32h7rsxx_ll_sdmmc.h

@@ -61,10 +61,10 @@ typedef struct
   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
                                       This parameter can be a value between Min_Data = 0 and Max_Data = 1023   */
 
-#if (USE_SD_TRANSCEIVER != 0U)
+#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U)
   uint32_t TranceiverPresent;    /*!< Specifies if there is a 1V8 Transceiver/Switcher.
                                       This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT       */
-#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */
 } SDMMC_InitTypeDef;
 
 
@@ -182,84 +182,128 @@ typedef struct
 #define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */
 #define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */
 
+/**
+  * @brief  Masks for R5 Response
+  */
+/** this is the reserved for future use in spec RFU */
+#define SDMMC_SDIO_R5_ERROR                          ((uint32_t)0x00000400U)
+/** Out of range error */
+#define SDMMC_SDIO_R5_OUT_OF_RANGE                   ((uint32_t)0x00000100U)
+/** Invalid function number */
+#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER        ((uint32_t)0x00000200U)
+/** General or an unknown error */
+#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR          ((uint32_t)0x00000800U)
+/** SDIO Card current state
+  * 00=DIS (card not selected)
+  * 01=CMD (data line free)
+  * 10=TRN (transfer on data lines) */
+#define SDMMC_SDIO_R5_IO_CURRENT_STATE               ((uint32_t)0x00003000U)
+/** Illegal command error */
+#define SDMMC_SDIO_R5_ILLEGAL_CMD                    ((uint32_t)0x00004000U)
+/** CRC check of previous cmd failed */
+#define SDMMC_SDIO_R5_COM_CRC_FAILED                 ((uint32_t)0x00008000U)
+
+#define SDMMC_SDIO_R5_ERRORBITS                      (SDMMC_SDIO_R5_COM_CRC_FAILED          | \
+                                                      SDMMC_SDIO_R5_ILLEGAL_CMD             | \
+                                                      SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR   | \
+                                                      SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \
+                                                      SDMMC_SDIO_R5_OUT_OF_RANGE)
+/**
+  * @brief SDIO_CMD53_MODE
+  */
+#define SDMMC_SDIO_MODE_BYTE                         0x00U  /*!< Byte Mode  */
+#define SDMMC_SDIO_MODE_BLOCK                        0x01U  /*!< Block Mode */
+
+/**
+  * @brief SDIO_CMD53_OP_CODE
+  */
+#define SDMMC_SDIO_NO_INC                            0x00U  /*!< No auto indentation */
+#define SDMMC_SDIO_AUTO_INC                          0x01U  /*!< Auto indentation    */
+
+/**
+  * @brief SDIO_CMD53_RAW
+  */
+#define SDMMC_SDIO_WO                                0x00U  /*!< Write only Flag       */
+#define SDMMC_SDIO_RAW                               0x01U  /*!< Read after write Flag */
+
 /**
   * @brief SDMMC Commands Index
   */
-#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
-#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
-#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information  and asks the card whether card supports voltage.                      */
-#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SDMMC_CMD_VOLTAGE_SWITCH                      ((uint8_t)11U)  /*!< SD card Voltage switch to 1.8V mode.                                                     */
-#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
-#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
-#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */
-#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective        */
+#define SDMMC_CMD_GO_IDLE_STATE                       0U   /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                        1U   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                        2U   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                        3U   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                             4U   /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   5U   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
+#define SDMMC_CMD_HS_SWITCH                           6U   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                      7U   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     8U   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information  and asks the card whether card supports voltage.                      */
+#define SDMMC_CMD_SEND_CSD                            9U   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                            10U  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_VOLTAGE_SWITCH                      11U  /*!< SD card Voltage switch to 1.8V mode.                                                     */
+#define SDMMC_CMD_STOP_TRANSMISSION                   12U  /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                         13U  /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                     14U  /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                   15U  /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                        16U  /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective        */
 /*!< for SDHS and SDXC.                                                                       */
-#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                    */
-#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by  STOP_TRANSMISSION command.                                                            */
-#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
-#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                   */
-#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
-#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).                                  */
-#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).           */
-#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
-#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.                                                */
-#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather than a standard command.                                                   */
-#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.                         */
-#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   17U  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                    */
+#define SDMMC_CMD_READ_MULT_BLOCK                     18U  /*!< Continuously transfers data blocks from card to host until interrupted by  STOP_TRANSMISSION command.                                                            */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                    19U  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                20U  /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                     23U  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  24U  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                   */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                    25U  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                            26U  /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                            27U  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                      28U  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                      29U  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                     30U  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                  32U  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                    33U  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                     35U  /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).                                  */
+#define SDMMC_CMD_ERASE_GRP_END                       36U  /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).           */
+#define SDMMC_CMD_ERASE                               38U  /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                             39U  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                        40U  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                         42U  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.                                                */
+#define SDMMC_CMD_APP_CMD                             55U  /*!< Indicates to the card that the next command is an application specific command rather than a standard command.                                                   */
+#define SDMMC_CMD_GEN_CMD                             56U  /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.                         */
+#define SDMMC_CMD_NO_CMD                              64U  /*!< No command                                                                               */
 
 /**
   * @brief Following commands are SD Card Specific commands.
   *        SDMMC_APP_CMD should be sent before sending these commands.
   */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.                                                   */
-#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.                                                               */
-#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
-#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */
-#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 6U   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.                                                   */
+#define SDMMC_CMD_SD_APP_STATUS                       13U  /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        22U  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.                                                               */
+#define SDMMC_CMD_SD_APP_OP_COND                      41U  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          42U  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                     51U  /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                     52U  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   53U  /*!< For SD I/O card only, reserved for security specification.                               */
 
 /**
   * @brief Following commands are MMC Specific commands.
   */
-#define SDMMC_CMD_MMC_SLEEP_AWAKE                     ((uint8_t)5U)   /*!< Toggle the device between Sleep state and Standby state.                                 */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE                     5U   /*!< Toggle the device between Sleep state and Standby state.                                 */
 
 /**
   * @brief Following commands are SD Card Specific security commands.
   *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
   */
-#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)
-#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_GET_MKB                      43U
+#define SDMMC_CMD_SD_APP_GET_MID                      44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             48U
 
 /**
   * @brief  Masks for errors Card Status R1 (OCR Register)
@@ -313,12 +357,12 @@ typedef struct
 #define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
 #define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
 
-#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
+#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */
 #define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
 #endif /* SDMMC_DATATIMEOUT */
 
 #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
-#define SDMMC_SWDATATIMEOUT                SDMMC_DATATIMEOUT
+#define SDMMC_SWDATATIMEOUT                ((uint32_t)0xFFFFFFFFU)
 #endif /* SDMMC_SWDATATIMEOUT */
 
 #define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
@@ -688,6 +732,82 @@ typedef struct
   * @}
   */
 
+/** @defgroup SDMMC_SDIO_CCCR_Registers
+  * @{
+  */
+/*-------------------------------- CCCR0 ----------------------------------*/
+#define SDMMC_SDIO_CCCR0                     0x000U  /*!< SDIOS Card Common Control Register 0        */
+#define SDMMC_SDIO_CCCR0_SD_BYTE0            0x000U  /*!< SDIOS Card Common Control Register 0 Byte 0 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE1            0x001U  /*!< SDIOS Card Common Control Register 0 Byte 1 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE2            0x002U  /*!< SDIOS Card Common Control Register 0 Byte 2 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE3            0x003U  /*!< SDIOS Card Common Control Register 0 Byte 3 */
+
+/*-------------------------------- CCCR4 ----------------------------------*/
+#define SDMMC_SDIO_CCCR4                     0x004U  /*!< SDIOS Card Common Control Register 4        */
+#define SDMMC_SDIO_CCCR4_SD_BYTE0            0x004U  /*!< SDIOS Card Common Control Register 4 Byte 0 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE1            0x005U  /*!< SDIOS Card Common Control Register 4 Byte 1 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE2            0x006U  /*!< SDIOS Card Common Control Register 4 Byte 2 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE3            0x007U  /*!< SDIOS Card Common Control Register 4 Byte 3 */
+
+/*-------------------------------- CCCR8 ----------------------------------*/
+#define SDMMC_SDIO_CCCR8                     0x008U  /*!< SDIOS Card Common Control Register 8        */
+#define SDMMC_SDIO_CCCR8_SD_BYTE0            0x008U  /*!< SDIOS Card Common Control Register 8 Byte 0 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE1            0x009U  /*!< SDIOS Card Common Control Register 8 Byte 1 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE2            0x00AU  /*!< SDIOS Card Common Control Register 8 Byte 2 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE3            0x00BU  /*!< SDIOS Card Common Control Register 8 Byte 3 */
+
+/*-------------------------------- CCCR12 ---------------------------------*/
+#define SDMMC_SDIO_CCCR12                    0x00CU  /*!< SDIOS Card Common Control Register 12        */
+#define SDMMC_SDIO_CCCR12_SD_BYTE0           0x00CU  /*!< SDIOS Card Common Control Register 12 Byte 0 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE1           0x00DU  /*!< SDIOS Card Common Control Register 12 Byte 1 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE2           0x00EU  /*!< SDIOS Card Common Control Register 12 Byte 2 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE3           0x00FU  /*!< SDIOS Card Common Control Register 12 Byte 3 */
+
+/*-------------------------------- CCCR16 ---------------------------------*/
+#define SDMMC_SDIO_CCCR16                    0x010U  /*!< SDIOS Card Common Control Register 16        */
+#define SDMMC_SDIO_CCCR16_SD_BYTE0           0x010U  /*!< SDIOS Card Common Control Register 16 Byte 0 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE1           0x011U  /*!< SDIOS Card Common Control Register 16 Byte 1 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE2           0x012U  /*!< SDIOS Card Common Control Register 16 Byte 2 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE3           0x013U  /*!< SDIOS Card Common Control Register 16 Byte 3 */
+
+/*-------------------------------- CCCR20 ---------------------------------*/
+#define SDMMC_SDIO_CCCR20                    0x014U  /*!< SDIOS Card Common Control Register 20        */
+#define SDMMC_SDIO_CCCR20_SD_BYTE0           0x014U  /*!< SDIOS Card Common Control Register 20 Byte 0 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE1           0x015U  /*!< SDIOS Card Common Control Register 20 Byte 1 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE2           0x016U  /*!< SDIOS Card Common Control Register 20 Byte 2 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE3           0x017U  /*!< SDIOS Card Common Control Register 20 Byte 3 */
+
+/*-------------------------------- F1BR0 ----------------------------------*/
+#define SDMMC_SDIO_F1BR0                     0x100U  /*!< SDIOS Function 1 Basic Register 0        */
+#define SDMMC_SDIO_F1BR0_SD_BYTE0            0x100U  /*!< SDIOS Function 1 Basic Register 0 Byte 0 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE1            0x101U  /*!< SDIOS Function 1 Basic Register 0 Byte 1 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE2            0x102U  /*!< SDIOS Function 1 Basic Register 0 Byte 2 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE3            0x103U  /*!< SDIOS Function 1 Basic Register 0 Byte 3 */
+
+/*-------------------------------- F1BR8 ----------------------------------*/
+#define SDMMC_SDIO_F1BR8                     0x108U  /*!< SDIOS Function 1 Basic Register 8        */
+#define SDMMC_SDIO_F1BR8_SD_BYTE0            0x108U  /*!< SDIOS Function 1 Basic Register 8 Byte 0 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE1            0x109U  /*!< SDIOS Function 1 Basic Register 8 Byte 1 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE2            0x10AU  /*!< SDIOS Function 1 Basic Register 8 Byte 2 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE3            0x10BU  /*!< SDIOS Function 1 Basic Register 8 Byte 3 */
+
+/*-------------------------------- F1BR12 ---------------------------------*/
+#define SDMMC_SDIO_F1BR12                    0x10CU  /*!< SDIOS Function 1 Basic Register 12        */
+#define SDMMC_SDIO_F1BR12_SD_BYTE0           0x10CU  /*!< SDIOS Function 1 Basic Register 12 Byte 0 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE1           0x10DU  /*!< SDIOS Function 1 Basic Register 12 Byte 1 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE2           0x10EU  /*!< SDIOS Function 1 Basic Register 12 Byte 2 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE3           0x10FU  /*!< SDIOS Function 1 Basic Register 12 Byte 3 */
+
+/*-------------------------------- F1BR16 ---------------------------------*/
+#define SDMMC_SDIO_F1BR16                    0x110U  /*!< SDIOS Function 1 Basic Register 16        */
+#define SDMMC_SDIO_F1BR16_SD_BYTE0           0x110U  /*!< SDIOS Function 1 Basic Register 16 Byte 0 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE1           0x111U  /*!< SDIOS Function 1 Basic Register 16 Byte 1 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE2           0x112U  /*!< SDIOS Function 1 Basic Register 16 Byte 2 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE3           0x113U  /*!< SDIOS Function 1 Basic Register 16 Byte 3 */
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -902,6 +1022,38 @@ typedef struct
   */
 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
 
+/**
+  * @brief  Checks the source of specified interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__)))
+
 /**
   * @brief  Clears the SDMMC's interrupt pending bits.
   * @param  __INSTANCE__ Pointer to SDMMC register base
@@ -1056,12 +1208,12 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
 uint32_t          SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx);
 
 /* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command);
 uint8_t           SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx);
 uint32_t          SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response);
 
 /* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data);
 uint32_t          SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx);
 uint32_t          SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx);
 
@@ -1105,6 +1257,9 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount);
+uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse);
+uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp);
 /**
   * @}
   */
@@ -1116,6 +1271,8 @@ uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount);
 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp);
+uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData);
 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
 /**
@@ -1126,7 +1283,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
 /** @addtogroup HAL_SDMMC_LL_Group6
   * @{
   */
-uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf);
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf);
 uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
                                         SDMMC_DMALinkNodeTypeDef *pNode);
 uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode);

Inc/stm32h7rsxx_ll_spi.h

@@ -836,7 +836,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
   */
 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
 {
-  MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
+  MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
 }
 
 /**
@@ -3632,7 +3632,7 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
   */
 
 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
 

Inc/stm32h7rsxx_ll_ucpd.h

@@ -869,7 +869,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
 }
 
 /**
-  * @brief  Enable Rx hard resrt interrupt
+  * @brief  Enable Rx hard reset interrupt
   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_EnableIT_RxHRST
   * @param  UCPDx UCPD Instance
   * @retval None
@@ -1034,7 +1034,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
 }
 
 /**
-  * @brief  Disable Rx hard resrt interrupt
+  * @brief  Disable Rx hard reset interrupt
   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_DisableIT_RxHRST
   * @param  UCPDx UCPD Instance
   * @retval None
@@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD
 }
 
 /**
-  * @brief  Check if Rx hard resrt interrupt enabled
+  * @brief  Check if Rx hard reset interrupt enabled
   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_IsEnableIT_RxHRST
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
 }
 
 /**
-  * @brief  Clear Rx hard resrt interrupt
+  * @brief  Clear Rx hard reset interrupt
   * @rmtoll ICR          RXHRSTDETIE         LL_UCPD_ClearFlag_RxHRST
   * @param  UCPDx UCPD Instance
   * @retval None
@@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
   */
 
 /**
-  * @brief  Check if FRS interrupt
+  * @brief  Check if FRS Event Flag is active
   * @rmtoll SR          FRSEVT         LL_UCPD_IsActiveFlag_FRS
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
 {
@@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD
   * @brief  Check if type c event on CC2
   * @rmtoll SR          TYPECEVT2        LL_UCPD_IsActiveFlag_TypeCEventCC2
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
 {
@@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *
   * @brief  Check if type c event on CC1
   * @rmtoll SR          TYPECEVT1        LL_UCPD_IsActiveFlag_TypeCEventCC1
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
 {
@@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *
 }
 
 /**
-  * @brief  Check if Rx message end interrupt
+  * @brief  Check if Rx error flag is active
+  * @rmtoll SR          RXERR         LL_UCPD_IsActiveFlag_RxErr
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx message end flag is active
   * @rmtoll SR          RXMSGEND         LL_UCPD_IsActiveFlag_RxMsgEnd
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
 {
@@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const
 }
 
 /**
-  * @brief  Check if Rx overrun interrupt
+  * @brief  Check if Rx overrun flag is active
   * @rmtoll SR          RXOVR         LL_UCPD_IsActiveFlag_RxOvr
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
 {
@@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC
 }
 
 /**
-  * @brief  Check if Rx hard resrt interrupt
+  * @brief  Check if Rx hard reset flag is active
   * @rmtoll SR          RXHRSTDET         LL_UCPD_IsActiveFlag_RxHRST
   * @param  UCPDx UCPD Instance
-  * @retval None
+  * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
 {
@@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U
 }
 
 /**
-  * @brief  Check if Rx orderset interrupt
+  * @brief  Check if Rx orderset flag is active
   * @rmtoll SR          RXORDDET         LL_UCPD_IsActiveFlag_RxOrderSet
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con
 }
 
 /**
-  * @brief  Check if Rx non empty interrupt
+  * @brief  Check if Rx non empty flag is active
   * @rmtoll SR          RXNE         LL_UCPD_IsActiveFlag_RxNE
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP
 }
 
 /**
-  * @brief  Check if TX underrun interrupt
+  * @brief  Check if TX underrun flag is active
   * @rmtoll SR          TXUND         LL_UCPD_IsActiveFlag_TxUND
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC
 }
 
 /**
-  * @brief  Check if hard reset sent interrupt
+  * @brief  Check if hard reset sent flag is active
   * @rmtoll SR          HRSTSENT         LL_UCPD_IsActiveFlag_TxHRSTSENT
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con
 }
 
 /**
-  * @brief  Check if hard reset discard interrupt
+  * @brief  Check if hard reset discard flag is active
   * @rmtoll SR          HRSTDISC         LL_UCPD_IsActiveFlag_TxHRSTDISC
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con
 }
 
 /**
-  * @brief  Check if Tx message abort interrupt
+  * @brief  Check if Tx message abort flag is active
   * @rmtoll SR          TXMSGABT         LL_UCPD_IsActiveFlag_TxMSGABT
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const
 }
 
 /**
-  * @brief  Check if Tx message sent interrupt
+  * @brief  Check if Tx message sent flag is active
   * @rmtoll SR          TXMSGSENT         LL_UCPD_IsActiveFlag_TxMSGSENT
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons
 }
 
 /**
-  * @brief  Check if Tx message discarded interrupt
+  * @brief  Check if Tx message discarded flag is active
   * @rmtoll SR         TXMSGDISC         LL_UCPD_IsActiveFlag_TxMSGDISC
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).
@@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons
 }
 
 /**
-  * @brief  Check if Tx data receive interrupt
+  * @brief  Check if Tx data interrupt flag is active
   * @rmtoll SR          TXIS         LL_UCPD_IsActiveFlag_TxIS
   * @param  UCPDx UCPD Instance
   * @retval State of bit (1 or 0).

Inc/stm32h7rsxx_ll_usart.h

@@ -57,6 +57,10 @@ static const uint32_t USART_PRESCALER_TAB[] =
   32UL,
   64UL,
   128UL,
+  256UL,
+  256UL,
+  256UL,
+  256UL,
   256UL
 };
 /**

Inc/stm32h7rsxx_ll_utils.h

@@ -66,11 +66,6 @@ extern "C" {
   */
 #define UID_BASE_ADDRESS              UID_BASE
 
-/**
-  * @brief Flash size data register base address
-  */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
 /**
   * @brief Package data register base address
   */
@@ -272,21 +267,6 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
   return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U))));
 }
 
-/**
-  * @brief  Get Flash memory size
-  * @note   This bitfield indicates the size of the device Flash memory expressed in
-  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
-  * @note   The read address belongs to an area which may contain virgin data generating
-  *         double ECC error (as never programmed). Thus, in case of cache activation
-  *         the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
-  *         through the MPU.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint32_t)((READ_REG(*((__IO uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF0000UL) >> 16UL);
-}
-
 /**
   * @brief  Get Package type
   * @note   The read address belongs to an area which may contain virgin data generating
@@ -312,7 +292,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
   */
 __STATIC_INLINE uint32_t LL_GetPackageType(void)
 {
-  return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL);
+  return (uint32_t)((READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x000F0000UL) >> 16UL);
 }
 
 /**

Release_Notes.html

@@ -40,14 +40,206 @@
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
+<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 05-February-2025</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <h3 id="maintenance-release-of-stm32cubeh7rs-halll-drivers-supporting-stm32h7rxsx-devices">Maintenance Release of <strong>STM32CubeH7RS</strong> HAL/LL Drivers supporting <strong>STM32H7Rx/Sx</strong> devices</h3>
 <h2 id="contents">Contents</h2>
 <h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
 <ul>
+<li>Remove unnecessary parentheses that causes compilation warning.</li>
+<li>Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers.</li>
+<li><strong>HAL ADC</strong>
+<ul>
+<li>Fix definition of VREFINT_CAL_ADDR, TEMPSENSOR_CAL1_ADDR, TEMPSENSOR_CAL2_ADDR macros.</li>
+<li>Fix description of parameter Length in HAL_ADCEx_MultiModeStart_DMA() API.</li>
+</ul></li>
+<li><strong>LL Cortex</strong>
+<ul>
+<li>Remove all references to LL_MPU_TEX_LEVEL4 macro in LL cortex driver.</li>
+</ul></li>
+<li><strong>HAL CRYP</strong>
+<ul>
+<li>Update related to reliability issue when running AES GCM in interrupt mode.</li>
+<li>Add SAES RESET using IPRST bit.</li>
+</ul></li>
+<li><strong>HAL Flash</strong>
+<ul>
+<li>Update the naming of defined Flash option byte keys to FLASH_OPT_KEY1 and FLASH_OPT_KEY2.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Add Pull-down capability in analog mode.</li>
+</ul></li>
+<li><strong>HAL HASH</strong>
+<ul>
+<li>Optimize HASH_WaitOnFlagUntilTimeout() API.</li>
+</ul></li>
+<li><strong>LL RCC</strong>
+<ul>
+<li>Update Timer clocks Prescaler definition.</li>
+</ul></li>
+<li><strong>HAL RNG</strong>
+<ul>
+<li>Update to distinguish error coming from RecoverSeedError or SeedError.</li>
+</ul></li>
+<li><strong>HAL/LL DMA</strong>
+<ul>
+<li>Remove duplicated assert checking.</li>
+<li>Add missing assert checking in some LL linked-list case.</li>
+<li>Fix in linked list node initialization.</li>
+</ul></li>
+<li><strong>HAL DMA2D</strong>
+<ul>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+<li><strong>HAL JPEG</strong>
+<ul>
+<li>Fix HAL_JPEG_IRQHandler() API calling blocking DMA abort:
+<ul>
+<li>Replaced blocking HAL_DMA_Abort() with HAL_DMA_Abort_IT() in HAL_JPEG_IRQHandler() API.</li>
+<li>Added a note to the JPEG_DMA_StartProcess() function to ensure that the DMA interrupt has a higher priority than the JPEG interrupt. This prevents the JPEG interrupt from preempting the DMA interrupt before the DMA state is updated to ready.</li>
+</ul></li>
+<li>Remove multiple volatile reads in interrupt handler.</li>
+<li>Remove non referenced local variable in JPEG_DMA_ContinueProcess static function.</li>
+<li>Remove non referenced local variable in JPEG_Process static function.</li>
+</ul></li>
+<li><strong>HAL FMC nand</strong>
+<ul>
+<li>Add a fix to avoid compiler optimizations and ensure correct data reads in HAL_NAND_Read_Page_8b() and HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Page_16b() and HAL_NAND_Read_SpareArea_16b() APIs.</li>
+</ul></li>
+<li><strong>HAL PKA</strong>
+<ul>
+<li>Remove static global variables and add them to PKA handle to be compliant with HAL coding rules.</li>
+<li>Add check for MontgomeryParam not equal to null in HAL_PKA_PointCheck() and HAL_PKA_PointCheck_IT() APIs.</li>
+</ul></li>
+<li><strong>HAL SDIO</strong>
+<ul>
+<li>Add new HAL SDIO driver.</li>
+</ul></li>
+<li><strong>HAL SDMMC</strong>
+<ul>
+<li>Fix Misra issue for unused parameter in ll_sdmmc source file.</li>
+<li>Update MMC High Speed clock.</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Add protection against wrong transfer size during transmission.</li>
+<li>Check coherence between data size and DMA TX configuration.</li>
+<li>Clear auto suspend flag in HAL_SPI_Receive() API.</li>
+<li>Ensure DMA RX aborts after DMA TX in HAL_SPI_Abort_IT() API.</li>
+<li>Fix CRC computation to feat with standard CRC16-CCITT (XMODEM).</li>
+<li>Fix a bug reception when FIFO threshold is set.</li>
+</ul></li>
+<li><strong>HAL XSPI</strong>
+<ul>
+<li>Check BUSY flag instead of TC flag in indirect mode to be sure that command is well completed (FIFO flush).</li>
+<li>Correct comments for XSPI_MemorySize and XSPI_ChipSelectBoundary related definitions.</li>
+</ul></li>
+<li><strong>HAL ETH</strong>
+<ul>
+<li>Correct the disabling PTP transmission issue by clearing the TTSE bit in DESC2.</li>
+<li>Fix identical definitions of the ETH state code.</li>
+<li>Fix the calculation of the tail pointer so that it points to the last updated descriptor.</li>
+<li>Update the HAL_ETH_PTP_SetConfig() API to comply with the steps described in the reference manual guidelines.</li>
+<li>Fix issue with filter Configuration in HAL_ETH_SetMACFilterConfig() API.</li>
+<li>Add new API HAL_ETH_GetTxBuffersNumber() to get Buffers in use number.</li>
+<li>Update HAL_ETH_ReadData() API to properly handle the Context descriptor when timestamping is enabled.</li>
+</ul></li>
+<li><strong>HAL FDCAN</strong>
+<ul>
+<li>Fix assert issue when Standard or Extended filter numbers are zero.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Move variable tmp declaration at the beginning in I2C_TransferCofig() function.</li>
+<li>Update HAL_I2C_IsDeviceReady() API to take into account the number of trials.</li>
+</ul></li>
+<li><strong>HAL I2S</strong>
+<ul>
+<li>Add IOSwap APIs:
+<ul>
+<li>HAL_I2S_EnableIOSwap() API.</li>
+<li>HAL_I2S_DisableIOSwap() API.</li>
+<li>HAL_I2S_IsEnabledIOSwap() API.</li>
+</ul></li>
+<li>Remove HAL_LOCK() APIs inside register callback functions.</li>
+</ul></li>
+<li><strong>HAL MDIOS</strong>
+<ul>
+<li>Remove multiple volatile reads or writes in interrupt handler (for better performance).</li>
+</ul></li>
+<li><strong>LL LPUART</strong>
+<ul>
+<li>Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array.</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.</li>
+<li>Correct references to HAL_UARTEx_WakeupCallback() and to HAL_UART_WAKEUP_CB_ID() APIs define, according to series capabilities.</li>
+<li>Provide accurate position in RxEventCallback when ReceptionToIdle mode is used with DMA, when UART and DMA interrupts process is delayed.</li>
+</ul></li>
+<li><strong>LL USART</strong>
+<ul>
+<li>Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array.</li>
+</ul></li>
+<li><strong>LL UCPD</strong>
+<ul>
+<li>Add LL UCPD API LL_UCPD_IsActiveFlag_RxErr() API.</li>
+<li>Correct wording in some LL API LL_UCPD_IsActiveFlag_xxx() API descriptions.</li>
+</ul></li>
+<li><strong>LL UTILS</strong>
+<ul>
+<li>Remove F_SIZE bit field and change PKG_CODE position to align vs latest RM.</li>
+<li>Update LL_SetFlashLatency() and add missing VOS scale frequency.</li>
+</ul></li>
+<li><strong>HAL IWDG</strong>
+<ul>
+<li>Calculate the maximum IWDG Timeout period HAL_IWDG_DEFAULT_TIMEOUT, based on a Prescaler=128 at LSI frequency=32kHz (refer to the datasheet).</li>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+<li><strong>HAL/LL USB</strong>
+<ul>
+<li>Add multi packet support for iso transfer.</li>
+<li>hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.</li>
+<li>Fix the condition on EONUM flag of DOEPCTLx register in HAL_PCD_IRQHandler() API to correctly check on the frame number parity.</li>
+<li>Fix Misra-C 2012 Rule-10.7 issue.</li>
+</ul></li>
+<li><strong>HAL WWDG</strong>
+<ul>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32H7S7xx, STM32H7S3xx, STM32H7R7xx, STM32H7R3xx devices</li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>Not applicable</li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="dependencies">Dependencies</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="notes">Notes</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-of-stm32cubeh7rs-halll-drivers-supporting-stm32h7rxsx-devices-1">Maintenance Release of <strong>STM32CubeH7RS</strong> HAL/LL Drivers supporting <strong>STM32H7Rx/Sx</strong> devices</h3>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
 <li><strong>HAL CORDIC</strong> driver
 <ul>
 <li>Remove empty lines for quality code indentation</li>
@@ -138,57 +330,58 @@
 <li>Remove number of WS according to RM</li>
 </ul></li>
 </ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
 <ul>
 <li>STM32H7S7xx, STM32H7S3xx, STM32H7R7xx, STM32H7R3xx devices</li>
 </ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
 </div>
 </div>
+<div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-February-2024</strong></label>
 <div>
 <h2 id="first-release">First Release</h2>
 <ul>
 <li>First official Release of <strong>STM32CubeH7RS</strong> HAL/LL Drivers supporting <strong>STM32H7Rx/Sx</strong> devices</li>
 </ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <ul>
 <li><strong>HAL</strong>: ADC, CEC, CORDIC, CORTEX, CRC, CRS, CRYP, DBGMCU, DCMIPP, DLB, DMA (HPDMA and GPDMA), DMA2D, DTS, ETH, EXTI, FDCAN, FLASH, FMC, GPIO, GFXMMU, GFXTIM, GPU2D, HASH, I2C, I3C, I2S, ICACHE, IRDA, IWDG, JPEG, LPTIM, LTDC, MCE, MDF, MDIOS, MMC/NAND/NOR/SD/SDRAM/SRAM, PKA, PSSI, PWR, RAMECC, RCC, RNG, RTC, SAI, SBS, SPDIFRX, SMARTCARD, SMBUS, SPI, TIM, UART, USART, USB (HCD and PCD), WWDG, XSPI</li>
 <li><strong>LL</strong>: ADC, CORDIC, CORTEX, CRC, CRS, DMA, EXTI, FMC, GPIO, I2C, I3C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SDMMC, SPI, SYSTEM, TIM, USART, USB, UTILS, UCPD<br />
 </li>
 </ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
 <ul>
 <li>STM32H7S7xx, STM32H7S3xx, STM32H7R7xx, STM32H7R3xx devices</li>
 </ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
 <ul>
 <li>None</li>
 </ul>

Src/stm32h7rsxx_hal_adc_ex.c

@@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
   *         conversions.
   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
   * @param pData Destination Buffer address.
-  * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+  * @param Length Length of data to be transferred from ADC peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)

Src/stm32h7rsxx_hal_cryp.c

@@ -343,8 +343,17 @@
                                                                                }while(0)
 #endif /* USE_HAL_SAES_ONLY */
 
-#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |=  CRYP_CR_FFLUSH)
-
+#define CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |=  CRYP_CR_FFLUSH)
+
+#define SAES_IP_RESET(__HANDLE__)   do { \
+                                         __IO uint32_t tmpreg; \
+                                         SET_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
+                                         /* Delay after an SAES peripheral IPRST */ \
+                                         tmpreg = READ_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
+                                         SAES_CR_IPRST); \
+                                         CLEAR_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
+                                         UNUSED(tmpreg); \
+                                          } while(0)
 
 /**
   * @}
@@ -532,6 +541,9 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
   if (IS_SAES_INSTANCE(hcryp->Instance))
   {
+    /* Reset of SAES */
+    SAES_IP_RESET(hcryp);
+
     /* Wait for BUSY flag to go to 0 */
     if (CRYP_WaitOnBUSYFlag(hcryp, CRYP_GENERAL_TIMEOUT) != HAL_OK)
     {
@@ -644,7 +656,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
   *         the configuration information for CRYP module
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, const CRYP_ConfigTypeDef *pConf)
 {
   /* Check the CRYP handle allocation */
   if ((hcryp == NULL) || (pConf == NULL))
@@ -4687,9 +4699,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
     {
       SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
 
-      /* Enable computation complete flag and error interrupts */
-      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
-
       /* Enable the CRYP peripheral */
       __HAL_CRYP_ENABLE(hcryp);
 
@@ -4735,6 +4744,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
             HAL_CRYP_InCpltCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
           }
+
+          /* Enable computation complete flag and error interrupts */
+          __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
         }
         else /* Size < 16Bytes  : first block is the last block*/
         {
@@ -4782,6 +4794,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
           /*Call legacy Input complete callback*/
           HAL_CRYP_InCpltCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+          /* Enable computation complete flag and error interrupts */
+          __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
         }
       }
       /* Enter header data */
@@ -5929,14 +5944,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
         }
         else if (hcryp->Size >= 16U)
         {
-          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
           hcryp->CrypInCount++;
-          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
           hcryp->CrypInCount++;
-          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
           hcryp->CrypInCount++;
-          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
           hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
 
           if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
           {
@@ -6042,14 +6057,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
       {
         /* Write the first input header block in the Input FIFO,
            the following header data will be fed after interrupt occurrence */
-        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
         hcryp->CrypHeaderCount++;
-        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
         hcryp->CrypHeaderCount++;
-        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
         hcryp->CrypHeaderCount++;
-        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
         hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
       } /* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is  skipped*/
     } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
 #endif /* USE_HAL_SAES_ONLY */
@@ -6070,14 +6085,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
     }
     else if (hcryp->Size >= 16U)
     {
-      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
       hcryp->CrypInCount++;
-      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
       hcryp->CrypInCount++;
-      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
       hcryp->CrypInCount++;
-      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
       hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
 
       if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
       {
@@ -7595,7 +7610,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
       }
     }
-    else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
+    else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
     {
       /* Can enter full 4 header words */
 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)

Src/stm32h7rsxx_hal_dcmipp.c

@@ -32,26 +32,43 @@
      camera module, which should be made before to configure and enable
      the DCMIPP to capture images.
 
-     (#) Program the required configuration through the following parameters:
-         the Format, the VSPolarity,the HSPolarity, the PCKPolarity, the ExtendedDataMode
-         the SynchroMode, the SynchroCodes of the frame delimite, the SwapBits and the SwapCycles
-         using HAL_DCMIPP_Init() and HAL_DCMIPP_SetParallelConfig
-     (#) Program the required configuration through the following parameters:
-         the FrameRate using HAL_DCMIPP_PIPE_Config function.
+
+
+Initialize the DCMIPP through HAL_DCMIPP_Init() function.
+
+  *** Mandatory Configuration ***
+  ===================================
+The configuration of the camera sensor interface in Parallel mode
+involves programming specific parameters to ensure proper functionality.
+Below is the structured process for configuring each interface type:
+
+     (#)Parallel Mode configuration
+        To configure the camera sensor in Parallel mode, program the following parameters:
+        the Format, the VSPolarity,the HSPolarity, the PCKPolarity, the ExtendedDataMode the SynchroMode,
+        the SynchroCodes of the frame delimiter, the SwapBits and the SwapCycles
+        using HAL_DCMIPP_PARALLEL_SetConfig() function.
+
+     (#)Pipe configuration
+         + To configure the Pipe , program the following parameters:
+           the FrameRate using HAL_DCMIPP_PIPE_SetConfig() function.
 
   *** Interrupt mode IO operation ***
   ===================================
-     (#) Configure Pipe parameter, destination (one or two) and Capture Mode (Snapshot or Continuous) and enable
-         the capture request using the following functions:
+
+     (#) Configure Pipe parameters, destination (one or two) and Capture Mode (Snapshot or Continuous) and enable
+         the capture request using one from the following functions:
          HAL_DCMIPP_PIPE_Start() or HAL_DCMIPP_PIPE_DoubleBufferStart().
 
+
+
      (#) Use HAL_DCMIPP_IRQHandler() called under DCMIPP_IRQHandler() interrupt subroutine.
      (#) At the end of frame capture request HAL_DCMIPP_IRQHandler() function is executed and user can
          add his own function by customization of function pointer PipeFrameEventCallback (member
          of DCMIPP handle structure).
-     (#) In case of common error, the HAL_DCMIPP_IRQHandler() function calls the callback
-         ErrorCallback otherwise in case of Pipe error
-         the HAL_DCMIPP_IRQHandler() function calls the callbackPipeErrorCallback.
+
+
+    (#) In case of common error, the HAL_DCMIPP_IRQHandler() function calls the callback
+         ErrorCallback, in case of Pipe error the HAL_DCMIPP_IRQHandler() function calls the callback PIPE_ErrorCallback
 
     (#) The Pipe capture can be suspended and resumed using the following functions
         HAL_DCMIPP_PIPE_Suspend() and HAL_DCMIPP_PIPE_Resume().
@@ -86,9 +103,7 @@
     (#) To read and reset the Frame counter of the pipe, use the following functions:
         HAL_DCMIPP_PIPE_ReadFrameCounter() and HAL_DCMIPP_PIPE_ResetFrameCounter().
 
-    (#) The Pipe capture can be Stopped using HAL_DCMIPP_PIPE_Stop() function.
-
-
+    (#) The Pipe capture in parallel mode can be Stopped using HAL_DCMIPP_PIPE_Stop() function.
     (#) To control the DCMIPP state, use the following function: HAL_DCMIPP_GetState().
 
     (#) To control the DCMIPP Pipe state, use the following function: HAL_DCMIPP_PIPE_GetState().
@@ -121,11 +136,11 @@
           This function takes as parameters the HAL peripheral handle, the Callback ID
           and a pointer to the user callback function.
      (#) Function @ref HAL_DCMIPP_PIPE_RegisterCallback() allows to register following callbacks:
-         (+) PipeFrameEventCallback : callback for Pipe Frame Event.
-         (+) PipeVsyncEventCallback : callback for Pipe Vsync Event.
-         (+) PipeLineEventCallback  : callback for Pipe Line Event.
-         (+) PipeLimitEventCallback : callback for Pipe Limit Event.
-         (+) PipeErrorCallback      : callback for Pipe Error
+         (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
+         (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
+         (+) PIPE_LineEventCallback  : callback for Pipe Line Event.
+         (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
+         (+) PIPE_ErrorCallback      : callback for Pipe Error
           This function takes as parameters the HAL peripheral handle, the Callback ID
           and a pointer to the user callback function.
 
@@ -142,11 +157,11 @@
          @ref HAL_DCMIPP_PIPE_UnRegisterCallback() takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
-         (+) PipeFrameEventCallback : callback for Pipe Frame Event.
-         (+) PipeVsyncEventCallback : callback for Pipe Vsync Event.
-         (+) PipeLineEventCallback  : callback for Pipe Line Event.
-         (+) PipeLimitEventCallback : callback for Pipe Limit Event.
-         (+) PipeErrorCallback      : callback for Pipe Error
+         (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
+         (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
+         (+) PIPE_LineEventCallback  : callback for Pipe Line Event.
+         (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
+         (+) PIPE_ErrorCallback      : callback for Pipe Error
 
      (#) By default, after the @ref HAL_DCMIPP_Init and if the state is HAL_DCMIPP_STATE_RESET
          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
@@ -210,148 +225,6 @@ static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, ui
                                 uint32_t DstAddress1, uint32_t CaptureMode);
 static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
 static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
-/**
-  * @}
-  */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
-  * @{
-  */
-/**
-  * @brief  Configure the selected Pipe
-  * @param  hdcmipp     Pointer to DCMIPP handle
-  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
-  * @param  pPipeConfig pointer to the DCMIPP_PipeConfTypeDef structure that contains
-  *                     the configuration information for the pipe.
-  * @retval None
-  */
-static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig)
-{
-  if (Pipe == DCMIPP_PIPE0)
-  {
-    /* Configure Pipe0 */
-    /* Configure Frame Rate */
-    MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, pPipeConfig->FrameRate);
-  }
-}
-/**
-  * @brief  Configure the destination address and capture mode for the selected pipe
-  * @param  hdcmipp     Pointer to DCMIPP handle
-  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
-  * @param  DstAddress  Specifies the destination memory address for the captured data.
-  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
-  * @retval None
-  */
-static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode)
-{
-  if (Pipe == DCMIPP_PIPE0)
-  {
-    /* Update the DCMIPP pipe State */
-    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
-
-    /* Set the capture mode */
-    hdcmipp->Instance->P0FCTCR |= CaptureMode;
-
-    /* Set the destination address */
-    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
-
-    /* Enable all required interrupts lines for the PIPE0 */
-    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR |
-                           DCMIPP_IT_AXI_TRANSFER_ERROR);
-  }
-}
-/**
-  * @brief  Configure the destination addresses and capture mode for the selected pipe for Double Buffering Mode
-  * @param  hdcmipp     Pointer to DCMIPP handle
-  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
-  * @param  DstAddress0 Specifies the first destination memory address for the captured data.
-  * @param  DstAddress1 Specifies the second destination memory address for the captured data.
-  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
-  * @retval None
-  */
-static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
-                                uint32_t DstAddress1, uint32_t CaptureMode)
-{
-  if (Pipe == DCMIPP_PIPE0)
-  {
-    /* Update the DCMIPP pipe State */
-    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
-
-    /* Set the capture mode */
-    hdcmipp->Instance->P0FCTCR |= CaptureMode;
-
-    /* Set the destination address */
-    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress0);
-
-    /* Set the second destination address */
-    WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress1);
-
-    /* Enable Double buffering Mode */
-    SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
-
-    /* Enable all required interrupts lines for the Pipe0 */
-    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
-  }
-}
-/**
-  * @brief  Enable the capture for the specified DCMIPP pipe.
-  * @param  hdcmipp     Pointer to DCMIPP handle
-  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
-  * @retval None
-  */
-static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
-{
-  if (Pipe == DCMIPP_PIPE0)
-  {
-    /* Activate the Pipe */
-    SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
-
-    /* Start the capture */
-    SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
-  }
-}
-/**
-  * @brief  Stop the capture for the specified DCMIPP pipe.
-  * @param  hdcmipp     Pointer to DCMIPP handle
-  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
-{
-  uint32_t tickstart;
-
-  if (Pipe == DCMIPP_PIPE0)
-  {
-    /* Stop the capture */
-    CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
-
-    /* Poll CPTACT status till No capture currently active */
-    tickstart = HAL_GetTick();
-    do
-    {
-      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
-      {
-        return HAL_ERROR;
-      }
-    } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
-
-    /* Disable DBM when enabled */
-    if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
-    {
-      CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
-    }
-
-    /* Disable the pipe */
-    CLEAR_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
-
-    /* Disable all interrupts for this pipe */
-    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_LINE | \
-                            DCMIPP_IT_PIPE0_LIMIT | DCMIPP_IT_PIPE0_OVR);
-
-  }
-
-  return HAL_OK;
-}
 /**
   * @}
   */
@@ -1522,6 +1395,17 @@ HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmi
 /**
   * @}
   */
+/**
+  * The DCMIPP pipe peripheral can be configured using a set of functions that allow
+  *
+  */
+
+/**
+  * Crop Feature : Allows setting and managing the crop coordinates to capture a specific area of the image.
+  *    - HAL_DCMIPP_PIPE_SetCropConfig() : Configure the DCMI crop coordinates.
+  *    - HAL_DCMIPP_PIPE_EnableCrop()    : Enable the cropping feature.
+  *    - HAL_DCMIPP_PIPE_DisableCrop()   : Disable the cropping feature.
+  */
 /** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions
   * @{
   */
@@ -1675,6 +1559,13 @@ HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uin
 /** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions
   * @{
   */
+/**
+  * Decimation Feature
+  *     - Horizontal resolution :
+  *       - HAL_DCMIPP_PIPE_SetBytesDecimationConfig() : Set the bytes decimation.
+  *     - Vertical resolution :
+  *       - HAL_DCMIPP_PIPE_SetLinesDecimationConfig() : Set the lines decimation.
+  */
 /**
   * @brief  Configure the Bytes decimation for the selected Pipe.
   * @param  hdcmipp     Pointer to DCMIPP handle
@@ -2063,6 +1954,11 @@ HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmip
 /** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions
   * @{
   */
+/**
+  * Lines Event Feature:
+  *     - HAL_DCMIPP_PIPE_EnableLineEvent()    : Enable the Line event for the selected Line.
+  *     - HAL_DCMIPP_PIPE_DisableLineEvent()   : Disable the Line event for the selected Line.
+  */
 /**
   * @brief  Configures the position of the line interrupt.
   * @param  hdcmipp  Pointer to DCMIPP handle
@@ -2278,6 +2174,145 @@ HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
+  * @{
+  */
+/**
+  * @brief  Configure the selected Pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pPipeConfig pointer to the DCMIPP_PipeConfTypeDef structure that contains
+  *                     the configuration information for the pipe.
+  * @retval None
+  */
+static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Configure Pipe0 */
+    /* Configure Frame Rate */
+    MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, pPipeConfig->FrameRate);
+  }
+}
+/**
+  * @brief  Configure the destination address and capture mode for the selected pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress  Specifies the destination memory address for the captured data.
+  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
+  * @retval None
+  */
+static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P0FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
+
+    /* Enable all required interrupts lines for the PIPE0 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR |
+                           DCMIPP_IT_AXI_TRANSFER_ERROR);
+  }
+}
+/**
+  * @brief  Configure the destination addresses and capture mode for the selected pipe for Double Buffering Mode
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress0 Specifies the first destination memory address for the captured data.
+  * @param  DstAddress1 Specifies the second destination memory address for the captured data.
+  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
+  * @retval None
+  */
+static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
+                                uint32_t DstAddress1, uint32_t CaptureMode)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P0FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress0);
+
+    /* Set the second destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress1);
+
+    /* Enable Double buffering Mode */
+    SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
+
+    /* Enable all required interrupts lines for the Pipe0 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
+  }
+}
+/**
+  * @brief  Enable the capture for the specified DCMIPP pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Activate the Pipe */
+    SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
+
+    /* Start the capture */
+    SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+  }
+}
+/**
+  * @brief  Stop the capture for the specified DCMIPP pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  uint32_t tickstart;
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Stop the capture */
+    CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+
+    /* Poll CPTACT status till No capture currently active */
+    tickstart = HAL_GetTick();
+    do
+    {
+      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+    } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
+
+    /* Disable DBM when enabled */
+    if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
+    }
+
+    /* Disable the pipe */
+    CLEAR_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
+
+    /* Disable all interrupts for this pipe */
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_LINE | \
+                            DCMIPP_IT_PIPE0_LIMIT | DCMIPP_IT_PIPE0_OVR);
+
+  }
+
+  return HAL_OK;
+}
 /**
   * @}
   */

Src/stm32h7rsxx_hal_dma.c

@@ -412,6 +412,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
   /* Allocate lock resource */
   __HAL_UNLOCK(hdma);
 
+  /* Initialize the callbacks */
+  if (hdma->State == HAL_DMA_STATE_RESET)
+  {
+    /* Clean all callbacks */
+    hdma->XferCpltCallback     = NULL;
+    hdma->XferHalfCpltCallback = NULL;
+    hdma->XferErrorCallback    = NULL;
+    hdma->XferAbortCallback    = NULL;
+    hdma->XferSuspendCallback  = NULL;
+  }
+
   /* Update the DMA channel state */
   hdma->State = HAL_DMA_STATE_BUSY;
 
@@ -1019,7 +1030,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Data Transfer Error Interrupt management *************************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
@@ -1033,7 +1044,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Update Linked-list Error Interrupt management ********************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
@@ -1047,7 +1058,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* User Setting Error Interrupt management **************************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
@@ -1061,7 +1072,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Trigger Overrun Interrupt management *****************************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
@@ -1075,7 +1086,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Half Transfer Complete Interrupt management **********************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
@@ -1093,7 +1104,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Suspend Transfer Interrupt management ****************************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
@@ -1151,7 +1162,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
   }
 
   /* Transfer Complete Interrupt management ***************************************************************************/
-  if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U))
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)
   {
     /* Check if interrupt source is enabled */
     if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
@@ -1549,7 +1560,6 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co
 }
 
 
-
 /**
   * @brief  Lock the DMA channel privilege attribute.
   * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the

Src/stm32h7rsxx_hal_dma2d.c

@@ -118,7 +118,7 @@
           and a pointer to the user callback function.
 
       (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
-          weak (surcharged) function.
+          weak (overridden) function.
           @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
           and the Callback ID.
           This function allows to reset following callbacks:
@@ -130,16 +130,16 @@
             (+) MspDeInitCallback  : DMA2D MspDeInit.
 
       (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
-          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+          all callbacks are reset to the corresponding legacy weak (overridden) functions:
           examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
           Exception done for MspInit and MspDeInit callbacks that are respectively
-          reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+          reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
           and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
           If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
           Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
-          as weak (surcharged) functions. They must be defined by the user to be resorted to.
+          as weak (overridden) functions. They must be defined by the user to be resorted to.
 
           Callbacks can be registered/unregistered in READY state only.
           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
@@ -151,7 +151,7 @@
 
           When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
           not defined, the callback registering feature is not available
-          and weak (surcharged) callbacks are used.
+          and weak (overridden) callbacks are used.
 
      [..]
       (@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -431,7 +431,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User DMA2D Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used instead of the weak (overridden) predefined callback
   * @param hdma2d DMA2D handle
   * @param CallbackID ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -530,7 +530,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM
 
 /**
   * @brief  Unregister a DMA2D Callback
-  *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
+  *         DMA2D Callback is redirected to the weak (overridden) predefined callback
   * @param hdma2d DMA2D handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -571,11 +571,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
         break;
 
       case HAL_DMA2D_MSPINIT_CB_ID :
-        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
         break;
 
       case HAL_DMA2D_MSPDEINIT_CB_ID :
-        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
         break;
 
       default :
@@ -591,11 +591,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
     switch (CallbackID)
     {
       case HAL_DMA2D_MSPINIT_CB_ID :
-        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (overridden) Msp Init */
         break;
 
       case HAL_DMA2D_MSPDEINIT_CB_ID :
-        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (overridden) Msp DeInit */
         break;
 
       default :

Src/stm32h7rsxx_hal_eth.c

@@ -1040,6 +1040,8 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi
 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
 {
   uint32_t descidx;
+  uint32_t descidx_next;
+  ETH_DMADescTypeDef *dmarxdesc_next;
   ETH_DMADescTypeDef *dmarxdesc;
   uint32_t desccnt = 0U;
   uint32_t desccntmax;
@@ -1065,14 +1067,8 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
   while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
          && (rxdataready == 0U))
   {
-    if (READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
-    {
-      /* Get timestamp high */
-      heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
-      /* Get timestamp low */
-      heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc->DESC0;
-    }
-    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
+    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) ||
+        (heth->RxDescList.pRxStart != NULL))
     {
       /* Check if first descriptor */
       if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
@@ -1081,7 +1077,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
         heth->RxDescList.RxDataLength = 0;
       }
 
-      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+      /* Get the Frame Length of the received packet */
       bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
 
       /* Check if last descriptor */
@@ -1092,6 +1088,22 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
 
         /* Packet ready */
         rxdataready = 1;
+
+        if (READ_BIT(dmarxdesc->DESC1, ETH_DMARXNDESCWBF_TSA) != (uint32_t)RESET)
+        {
+          descidx_next = descidx;
+          INCR_RX_DESC_INDEX(descidx_next, 1U);
+
+          dmarxdesc_next = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx_next];
+
+          if (READ_BIT(dmarxdesc_next->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
+          {
+            /* Get timestamp high */
+            heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc_next->DESC1;
+            /* Get timestamp low */
+            heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc_next->DESC0;
+          }
+        }
       }
 
       /* Link data */
@@ -1209,7 +1221,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
   if (heth->RxDescList.RxBuildDescCnt != desccount)
   {
     /* Set the tail pointer index */
-    tailidx = (descidx + 1U) % ETH_RX_DESC_CNT;
+    tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
 
     /* DMB instruction to avoid race condition */
     __DMB();
@@ -1429,7 +1441,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
 #ifdef HAL_ETH_USE_PTP
 
         /* Disable Ptp transmission */
-        CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U));
+        CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE);
 
         if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
             && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
@@ -1506,6 +1518,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
     return HAL_ERROR;
   }
 
+  /* Mask the Timestamp Trigger interrupt */
+  CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE);
+
   tmpTSCR = ptpconfig->Timestamp |
             ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) |
             ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) |
@@ -1539,8 +1554,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
     }
   }
 
-  /* Ptp Init */
-  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
+  /* Enable Update mode */
+  if (ptpconfig->TimestampUpdateMode == ENABLE)
+  {
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
+  }
 
   /* Set PTP Configuration done */
   heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
@@ -1552,6 +1570,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
 
   HAL_ETH_PTP_SetTime(heth, &time);
 
+  /* Ptp Init */
+  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
+
   /* Return function status */
   return HAL_OK;
 }
@@ -2453,7 +2474,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_
                   ((uint32_t)pFilterConfig->HashMulticast << 2)  |
                   ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
                   ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
-                  ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
+                  ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) |
                   ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
                   ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
                   ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
@@ -2486,7 +2507,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_
   pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
                                                        ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
+  pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
   pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
                                                       ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
@@ -2734,6 +2755,16 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
   return heth->MACWakeUpEvent;
 }
 
+/**
+  * @brief  Returns the ETH Tx Buffers in use number
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH Tx Buffers in use number
+  */
+uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth)
+{
+  return heth->TxDescList.BuffersInUse;
+}
 /**
   * @}
   */
@@ -3018,7 +3049,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @param  pTxConfig: Tx packet configuration
-  * @param  ItMode: Enable or disable Tx EOT interrept
+  * @param  ItMode: Enable or disable Tx EOT interrupt
   * @retval Status
   */
 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,

Src/stm32h7rsxx_hal_flash.c

@@ -542,8 +542,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
   if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
   {
     /* Authorizes the Option Byte register programming */
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
 
     /* Verify that the Option Bytes are unlocked */
     if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)

Src/stm32h7rsxx_hal_gpio.c

@@ -200,7 +200,8 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
         GPIOx->OTYPER = temp;
       }
 
-      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
+          (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
       {
         /* Check the Pull parameter */
         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

Src/stm32h7rsxx_hal_hash.c

@@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
   *         the configuration information for HASH module
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf)
 {
   uint32_t cr_value;
 
@@ -2954,7 +2954,7 @@ static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash)
       }
     }
   }
-  else if ((hhash->State == HAL_HASH_STATE_SUSPENDED))
+  else if (hhash->State == HAL_HASH_STATE_SUSPENDED)
   {
     return HAL_OK;
   }
@@ -3110,43 +3110,20 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash,
 {
   uint32_t tickstart = HAL_GetTick();
 
-  /* Wait until flag is set */
-  if (Status == RESET)
+  while (__HAL_HASH_GET_FLAG(hhash, Flag) == Status)
   {
-    while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET)
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  else
-  {
-    while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
+        /* Set State to Ready to be able to restart later on */
+        hhash->State  = HAL_HASH_STATE_READY;
+        hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
 
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
     }
   }

Src/stm32h7rsxx_hal_hcd.c

@@ -1708,6 +1708,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
       else
       {
         hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* Re-activate the channel  */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
       }
     }
     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);

Src/stm32h7rsxx_hal_i2c.c

@@ -3424,6 +3424,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 
   __IO uint32_t I2C_Trials = 0UL;
 
+  HAL_StatusTypeDef status = HAL_OK;
+
   FlagStatus tmp1;
   FlagStatus tmp2;
 
@@ -3481,37 +3483,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         /* Wait until STOPF flag is reset */
         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
-          return HAL_ERROR;
+          /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
+          if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+          {
+            /* Clear STOP Flag */
+            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+            /* Reset the error code for next trial */
+            hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+          }
+          else
+          {
+            status = HAL_ERROR;
+          }
         }
+        else
+        {
+          /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
 
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+          /* Clear STOP Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
-        /* Device is ready */
-        hi2c->State = HAL_I2C_STATE_READY;
+          /* Device is ready */
+          hi2c->State = HAL_I2C_STATE_READY;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
 
-        return HAL_OK;
+          return HAL_OK;
+        }
       }
       else
       {
-        /* Wait until STOPF flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
+        /* A non acknowledge is detected, this mean that device not respond to its address,
+           a new trial must be performed */
 
         /* Clear NACK Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Clear STOP Flag, auto generated with autoend*/
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+        }
       }
 
       /* Increment Trials */
       I2C_Trials++;
+
+      if ((I2C_Trials < Trials) && (status == HAL_ERROR))
+      {
+        status = HAL_OK;
+      }
+
     } while (I2C_Trials < Trials);
 
     /* Update I2C state */
@@ -6602,7 +6631,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
     /* Increment Buffer pointer */
     hi2c->pBuffPtr++;
 
-    if ((hi2c->XferSize > 0U))
+    if (hi2c->XferSize > 0U)
     {
       hi2c->XferSize--;
       hi2c->XferCount--;
@@ -6758,7 +6787,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
     /* Increment Buffer pointer */
     hi2c->pBuffPtr++;
 
-    if ((hi2c->XferSize > 0U))
+    if (hi2c->XferSize > 0U)
     {
       hi2c->XferSize--;
       hi2c->XferCount--;
@@ -7266,7 +7295,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
-        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
+        if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
         {
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           hi2c->State = HAL_I2C_STATE_READY;
@@ -7306,7 +7335,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
-        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
         {
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           hi2c->State = HAL_I2C_STATE_READY;
@@ -7345,7 +7374,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     /* Check for the Timeout */
     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
     {
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->State = HAL_I2C_STATE_READY;
@@ -7423,7 +7452,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     /* Check for the Timeout */
     if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
     {
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->State = HAL_I2C_STATE_READY;
@@ -7590,15 +7619,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T
 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
                                uint32_t Request)
 {
+  uint32_t tmp;
+
   /* Check the parameters */
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_TRANSFER_MODE(Mode));
   assert_param(IS_TRANSFER_REQUEST(Request));
 
   /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
-                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
-                             (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+  tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                    (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                    (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
 
   /* update CR2 register */
   MODIFY_REG(hi2c->Instance->CR2, \

Src/stm32h7rsxx_hal_i2s.c

@@ -170,7 +170,7 @@
 
        When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
        not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
+       and weak callbacks are used.
 
 
   @endverbatim
@@ -540,6 +540,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
   *                the configuration information for the specified I2S.
   * @param  CallbackID ID of the callback to be registered
   * @param  pCallback pointer to the Callback function
+  * @note   The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
@@ -554,8 +556,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hi2s);
 
   if (HAL_I2S_STATE_READY == hi2s->State)
   {
@@ -637,8 +637,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
   return status;
 }
 
@@ -648,15 +646,14 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
   *                the configuration information for the specified I2S.
   * @param  CallbackID ID of the callback to be unregistered
+  * @note   The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
   if (HAL_I2S_STATE_READY == hi2s->State)
   {
     switch (CallbackID)
@@ -736,8 +733,6 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
   return status;
 }
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
@@ -2009,6 +2004,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
   return errorcode;
 }
 
+/**
+  * @brief  Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx.
+  *         Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable
+  *         on half-duplex mode in case of single data line).
+  * @param  hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module.
+  * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state.
+  * @retval HAL_OK IO Swap feature enabled successfully.
+  */
+HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if (hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the global state */
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check for IOLock */
+  if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK))
+  {
+    return  HAL_ERROR;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
+  {
+    /* Disable I2S peripheral */
+    __HAL_I2S_DISABLE(hi2s);
+  }
+
+  /* Enable IO Swap feature */
+  SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx.
+  *         Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable
+  *         on half-duplex mode in case of single data line).
+  * @param  hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module.
+  * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state.
+  * @retval HAL_OK IO Swap feature disabled successfully.
+  */
+HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if (hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the global state */
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check for IOLock */
+  if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
+  {
+    /* Disable I2S peripheral */
+    __HAL_I2S_DISABLE(hi2s);
+  }
+
+  /* Disable the IO Swap feature */
+  CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx.
+  * @param  hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module.
+  * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null.
+  */
+uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if (hi2s == NULL)
+  {
+    return 0;
+  }
+
+  return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
+}
+
 /**
   * @brief  This function handles I2S interrupt request.
   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains

Src/stm32h7rsxx_hal_i3c.c

@@ -127,7 +127,7 @@
         The I3C_XferTypeDef structure contains different parameters about Control, Status buffer,
         and Transmit and Receive buffer.
         Use HAL_I3C_AddDescToFrame() function each time application add a descriptor in the frame before call
-        an IO operation interface
+        a Controller IO operation interface
         One element of the frame descriptor correspond to one frame to manage through IO operation.
 
     (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready()
@@ -1661,8 +1661,8 @@ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rul
              All different characteristics must be fill through structure I3C_DeviceConfTypeDef.
              This function is called only when mode is Controller.
 
-         (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a transfer descriptor
-             which contained different buffer pointers and their associated size through I3C_XferTypeDef.
+         (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a Controller transfer
+             descriptor which contained different buffer pointers and their associated size through I3C_XferTypeDef.
              This function must be called before initiate any communication transfer.
          (+) Call the function HAL_I3C_Ctrl_SetConfigResetPattern() to configure the insertion of the reset pattern
              at the end of a Frame.
@@ -2141,10 +2141,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef           *hi3
 }
 
 /**
-  * @brief  Add Private or CCC descriptor in the user data transfer descriptor.
-  * @note   This function must be called before initiate any communication transfer. This function help the preparation
-  *         of the full transfer usecase in a transfer descriptor which contained different buffer pointers
-  *         and their associated size through I3C_XferTypeDef.
+  * @brief  Add Private or CCC descriptor in the user data transfer controller descriptor.
+  * @note   This function must be called before initiate initiate any controller communication transfer. This function
+  *         help the preparation of the full transfer usecase in a transfer descriptor which contained different buffer
+  *         pointers and their associated size through I3C_XferTypeDef.
   * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
   *         multiple transmission frames.
   * @param  hi3c          : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
@@ -5495,7 +5495,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
   *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
   *                            to transmit in bytes (TxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @param  timeout    : [IN]  Timeout duration in millisecond.
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
@@ -5639,7 +5638,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
   *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
   *                            to transmit in bytes (TxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
@@ -5738,7 +5736,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
   *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
   *                            to transmit in bytes (TxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
@@ -5899,7 +5896,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
   *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
   *                            to be received in bytes (RxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @param  timeout    : [IN]  Timeout duration in millisecond.
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
@@ -6042,7 +6038,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
   *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
   *                            to be received in bytes (RxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
@@ -6137,7 +6132,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe
   * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
   *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
   *                            to be received in bytes (RxBuf.Size)).
-  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
   * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
   */
 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
@@ -6686,7 +6680,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPa
     else
     {
       /* Verify if IBI request feature is enabled*/
-      if ((LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U))
+      if (LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U)
       {
         hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
         status = HAL_ERROR;

Src/stm32h7rsxx_hal_iwdg.c

@@ -137,7 +137,8 @@
    The timeout value is multiplied by 1000 to be converted in milliseconds.
    LSI startup time is also considered here by adding LSI_STARTUP_TIME
    converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT        (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define HAL_IWDG_DEFAULT_TIMEOUT        (((1UL * 1024UL * 1000UL) / (LSI_VALUE / 128U)) + \
+                                         ((LSI_STARTUP_TIME / 1000UL) + 1UL))
 #define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
 /**
   * @}
@@ -313,7 +314,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
 #if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User IWDG Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used instead of the weak (overridden) predefined callback
   * @param  hiwdg IWDG handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -354,7 +355,7 @@ HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_
 
 /**
   * @brief  Unregister a IWDG Callback
-  *         IWDG Callback is redirected to the weak (surcharged) predefined callback
+  *         IWDG Callback is redirected to the weak (overridden) predefined callback
   * @param  hiwdg IWDG handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:

Src/stm32h7rsxx_hal_jpeg.c

@@ -3369,7 +3369,6 @@ static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
 static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
 {
   uint32_t tmpContext;
-  uint32_t itsource = hjpeg->Instance->CR;
   uint32_t itflag = hjpeg->Instance->SR;
 
   /*End of header processing flag */
@@ -3828,7 +3827,6 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
   */
 static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
 {
-  uint32_t itsource = hjpeg->Instance->CR;
   uint32_t itflag = hjpeg->Instance->SR;
 
   /*End of header processing flag rises*/

Src/stm32h7rsxx_hal_mdios.c

@@ -712,8 +712,12 @@ HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
   */
 void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
 {
+  uint32_t itsource = READ_REG(hmdios->Instance->CR);
+  uint32_t itflag = READ_REG(hmdios->Instance->SR);
+  uint32_t exti_flag = READ_REG(EXTI->PR2);
+
   /* Write Register Interrupt enabled ? */
-  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET)
+  if ((itsource & MDIOS_IT_WRITE) != 0U)
   {
     /* Write register flag */
     if (HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET)
@@ -732,7 +736,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
   }
 
   /* Read Register Interrupt enabled ? */
-  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET)
+  if ((itsource & MDIOS_IT_READ) != 0U)
   {
     /* Read register flag */
     if (HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET)
@@ -751,10 +755,10 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
   }
 
   /* Error Interrupt enabled ? */
-  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET)
+  if ((itsource & MDIOS_IT_ERROR) != 0U)
   {
     /* All Errors Flag */
-    if (__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET)
+    if ((itflag & MDIOS_ALL_ERRORS_FLAG) != 0U)
     {
       hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA;
 
@@ -772,7 +776,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
     hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
   }
   /* check MDIOS WAKEUP exti flag */
-  if (__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+  if ((exti_flag & MDIOS_WAKEUP_EXTI_LINE) != 0U)
   {
     /* Clear MDIOS WAKEUP Exti pending bit */
     __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);

Src/stm32h7rsxx_hal_mmc.c

@@ -402,7 +402,7 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3
 /**
   * @brief  Initializes the MMC according to the specified parameters in the
             MMC_HandleTypeDef and create the associated handle.
-  * @param  hmmc Pointer to the MMC handle
+  * @param  hmmc: Pointer to the MMC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
@@ -478,7 +478,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Initializes the MMC Card.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @note   This function initializes the MMC card. It could be used when a card
             re-initialization is needed.
   * @retval HAL status
@@ -561,7 +561,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  De-Initializes the MMC card.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
@@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Initializes the MMC MSP.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval None
   */
 __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
@@ -616,7 +616,7 @@ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  De-Initialize MMC MSP.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval None
   */
 __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
@@ -653,11 +653,11 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
   *         is managed by polling mode.
   * @note   This API should be followed by a check on the card state through
   *         HAL_MMC_GetCardState().
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData pointer to the buffer that will contain the received data
-  * @param  BlockAdd Block Address from where data is to be read
-  * @param  NumberOfBlocks Number of MMC blocks to read
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of MMC blocks to read
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
@@ -850,11 +850,11 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
   *         transfer is managed by polling mode.
   * @note   This API should be followed by a check on the card state through
   *         HAL_MMC_GetCardState().
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd Block Address where data will be written
-  * @param  NumberOfBlocks Number of MMC blocks to write
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of MMC blocks to write
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
@@ -1047,10 +1047,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD
   *         HAL_MMC_GetCardState().
   * @note   You could also check the IT transfer process through the MMC Rx
   *         interrupt event.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData Pointer to the buffer that will contain the received data
-  * @param  BlockAdd Block Address from where data is to be read
-  * @param  NumberOfBlocks Number of blocks to read.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
@@ -1160,10 +1160,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
   *         HAL_MMC_GetCardState().
   * @note   You could also check the IT transfer process through the MMC Tx
   *         interrupt event.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd Block Address where data will be written
-  * @param  NumberOfBlocks Number of blocks to write
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
@@ -1274,10 +1274,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t
   *         HAL_MMC_GetCardState().
   * @note   You could also check the DMA transfer process through the MMC Rx
   *         interrupt event.
-  * @param  hmmc Pointer MMC handle
-  * @param  pData Pointer to the buffer that will contain the received data
-  * @param  BlockAdd Block Address from where data is to be read
-  * @param  NumberOfBlocks Number of blocks to read.
+  * @param  hmmc: Pointer MMC handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
@@ -1389,10 +1389,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
   *         HAL_MMC_GetCardState().
   * @note   You could also check the DMA transfer process through the MMC Tx
   *         interrupt event.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd Block Address where data will be written
-  * @param  NumberOfBlocks Number of blocks to write
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
@@ -1502,7 +1502,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t
   * @brief  Erases the specified memory area of the given MMC card.
   * @note   This API should be followed by a check on the card state through
   *         HAL_MMC_GetCardState().
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  BlockStartAdd: Start Block address
   * @param  BlockEndAdd: End Block address
   * @retval HAL status
@@ -1613,7 +1613,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
 
 /**
   * @brief  This function handles MMC card interrupt request.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval None
   */
 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
@@ -1827,7 +1827,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief return the MMC state
-  * @param hmmc Pointer to mmc handle
+  * @param hmmc: Pointer to mmc handle
   * @retval HAL state
   */
 HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc)
@@ -1848,7 +1848,7 @@ uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief Tx Transfer completed callbacks
-  * @param hmmc Pointer to MMC handle
+  * @param hmmc: Pointer to MMC handle
   * @retval None
   */
 __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1863,7 +1863,7 @@ __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief Rx Transfer completed callbacks
-  * @param hmmc Pointer MMC handle
+  * @param hmmc: Pointer MMC handle
   * @retval None
   */
 __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1878,7 +1878,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief MMC error callbacks
-  * @param hmmc Pointer MMC handle
+  * @param hmmc: Pointer MMC handle
   * @retval None
   */
 __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
@@ -1893,7 +1893,7 @@ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief MMC Abort callbacks
-  * @param hmmc Pointer MMC handle
+  * @param hmmc: Pointer MMC handle
   * @retval None
   */
 __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
@@ -2115,12 +2115,12 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
 /**
   * @brief  Returns information the information of the card which are stored on
   *         the CID register.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  pCID: Pointer to a HAL_MMC_CIDTypedef structure that
   *         contains all CID register parameters
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
+HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
 {
   pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
 
@@ -2148,7 +2148,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp
 /**
   * @brief  Returns information the information of the card which are stored on
   *         the CSD register.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
   *         contains all CSD register parameters
   * @retval HAL status
@@ -2266,12 +2266,12 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp
 
 /**
   * @brief  Gets the MMC card info.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
   *         will contain the MMC card status information
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
 {
   pCardInfo->CardType     = (uint32_t)(hmmc->MmcCard.CardType);
   pCardInfo->Class        = (uint32_t)(hmmc->MmcCard.Class);
@@ -2407,7 +2407,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC
 /**
   * @brief  Enables wide bus operation for the requested card if supported by
   *         card.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  WideMode: Specifies the MMC card wide bus mode
   *          This parameter can be one of the following values:
   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
@@ -2526,7 +2526,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
 
 /**
   * @brief  Configure the speed bus mode
-  * @param  hmmc Pointer to the MMC handle
+  * @param  hmmc: Pointer to the MMC handle
   * @param  SpeedMode: Specifies the MMC card speed bus mode
   *          This parameter can be one of the following values:
   *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
@@ -2689,7 +2689,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3
 
 /**
   * @brief  Gets the current mmc card data state.
-  * @param  hmmc pointer to MMC handle
+  * @param  hmmc: pointer to MMC handle
   * @retval Card state
   */
 HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
@@ -2711,7 +2711,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Abort the current transfer and disable the MMC.
-  * @param  hmmc pointer to a MMC_HandleTypeDef structure that contains
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
   *                the configuration information for MMC module.
   * @retval HAL status
   */
@@ -2806,7 +2806,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
 }
 /**
   * @brief  Abort the current transfer and disable the MMC (IT mode).
-  * @param  hmmc pointer to a MMC_HandleTypeDef structure that contains
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
   *                the configuration information for MMC module.
   * @retval HAL status
   */
@@ -3588,7 +3588,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Initializes the mmc card.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval MMC Card error state
   */
 static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
@@ -3695,7 +3695,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
   * @brief  Enquires cards about their operating voltage and configures clock
   *         controls and stores MMC information that will be needed in future
   *         in the MMC handle.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval error state
   */
 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
@@ -3748,7 +3748,7 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Turns the SDMMC output signals off.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @retval None
   */
 static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
@@ -3759,7 +3759,7 @@ static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Returns the current card's status.
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  pCardStatus: pointer to the buffer that will contain the MMC card
   *         status (Card Status register)
   * @retval error state
@@ -3788,10 +3788,10 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
 
 /**
   * @brief  Reads extended CSD register to get the sectors number of the device
-  * @param  hmmc Pointer to MMC handle
+  * @param  hmmc: Pointer to MMC handle
   * @param  pFieldData: Pointer to the read buffer
   * @param  FieldIndex: Index of the field to be read
-  * @param  Timeout Specify timeout value
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
@@ -3906,7 +3906,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
 
 /**
   * @brief  Wrap up reading in non-blocking mode.
-  * @param  hmmc pointer to a MMC_HandleTypeDef structure that contains
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
   *              the configuration information.
   * @retval None
   */
@@ -3941,7 +3941,7 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Wrap up writing in non-blocking mode.
-  * @param  hmmc pointer to a MMC_HandleTypeDef structure that contains
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
   *              the configuration information.
   * @retval None
   */
@@ -3976,7 +3976,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
 
 /**
   * @brief  Switches the MMC card to high speed mode.
-  * @param  hmmc MMC handle
+  * @param  hmmc: MMC handle
   * @param  state: State of high speed mode
   * @retval MMC Card error state
   */
@@ -4089,7 +4089,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
 
 /**
   * @brief  Switches the MMC card to Double Data Rate (DDR) mode.
-  * @param  hmmc MMC handle
+  * @param  hmmc: MMC handle
   * @param  state: State of DDR mode
   * @retval MMC Card error state
   */
@@ -4300,8 +4300,8 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3
 
 /**
   * @brief  Used to select the partition.
-  * @param  hmmc Pointer to MMC handle
-  * @param  Partition Partition type
+  * @param  hmmc: Pointer to MMC handle
+  * @param  Partition: Partition type
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition)
@@ -4403,9 +4403,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti
 
 /**
   * @brief  Allows to program the authentication key within the RPMB partition
-  * @param  hmmc Pointer to MMC handle
-  * @param  pKey pointer to the authentication key (32 bytes)
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pKey: pointer to the authentication key (32 bytes)
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout)
@@ -4681,9 +4681,9 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc,
 
 /**
   * @brief  Allows to get the value of write counter within the RPMB partition.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pNonce pointer to the value of nonce (16 bytes)
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pNonce: pointer to the value of nonce (16 bytes)
+  * @param  Timeout: Specify timeout value
   * @retval write counter value.
   */
 uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout)
@@ -4972,12 +4972,12 @@ uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce,
 /**
   * @brief  Allows to write block(s) to a specified address in the RPMB partition. The Data
   *         transfer is managed by polling mode.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd Block Address where data will be written
-  * @param  NumberOfBlocks Number of blocks to write
-  * @param  pMAC Pointer to the authentication MAC buffer
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @param  pMAC: Pointer to the authentication MAC buffer
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
@@ -5535,13 +5535,13 @@ HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_
 /**
   * @brief  Allows to read block(s) to a specified address in the RPMB partition. The Data
   *         transfer is managed by polling mode.
-  * @param  hmmc Pointer to MMC handle
-  * @param  pData Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd Block Address where data will be written
-  * @param  NumberOfBlocks Number of blocks to write
-  * @param  pNonce Pointer to the buffer that will contain the nonce to transmit
-  * @param  pMAC Pointer to the authentication MAC buffer
-  * @param  Timeout Specify timeout value
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @param  pNonce: Pointer to the buffer that will contain the nonce to transmit
+  * @param  pMAC: Pointer to the authentication MAC buffer
+  * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
@@ -5847,7 +5847,7 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pDat
 
 /**
   * @brief Read DMA Linked list node Transfer completed callbacks
-  * @param hmmc MMC handle
+  * @param hmmc: MMC handle
   * @retval None
   */
 __weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -5861,7 +5861,7 @@ __weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
 }
 /**
   * @brief Read DMA Linked list node Transfer completed callbacks
-  * @param hmmc MMC handle
+  * @param hmmc: MMC handle
   * @retval None
   */
 __weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)

Src/stm32h7rsxx_hal_mmc_ex.c

@@ -60,7 +60,6 @@
   */
 
 
-
 /** @addtogroup MMCEx_Exported_Functions_Group1
   *  @brief   Linked List management functions
   *
@@ -218,7 +217,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListT
   * @param  NumberOfBlocks: Total number of blocks to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc,
+                                                     const MMC_DMALinkedListTypeDef *pLinkedList,
                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -327,7 +327,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MM
   * @param  NumberOfBlocks: Total number of blocks to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc,
+                                                      const MMC_DMALinkedListTypeDef *pLinkedList,
                                                       uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -427,7 +428,6 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, M
 }
 
 
-
 /**
   * @}
   */

Src/stm32h7rsxx_hal_nand.c

@@ -637,7 +637,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad
       /* Get Data into Buffer */
       for (index = 0U; index < hnand->Config.PageSize; index++)
       {
-        *buff = *(uint8_t *)deviceaddress;
+        *buff = *(__IO uint8_t *)deviceaddress;
         buff++;
       }
 
@@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A
       /* Get Data into Buffer */
       for (index = 0U; index < hnand->Config.PageSize; index++)
       {
-        *buff = *(uint16_t *)deviceaddress;
+        *buff = *(__IO uint16_t *)deviceaddress;
         buff++;
       }
 
@@ -1287,7 +1287,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA
       /* Get Data into Buffer */
       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
       {
-        *buff = *(uint8_t *)deviceaddress;
+        *buff = *(__IO uint8_t *)deviceaddress;
         buff++;
       }
 
@@ -1452,7 +1452,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N
       /* Get Data into Buffer */
       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
       {
-        *buff = *(uint16_t *)deviceaddress;
+        *buff = *(__IO uint16_t *)deviceaddress;
         buff++;
       }
 

Src/stm32h7rsxx_hal_pcd.c

@@ -1468,7 +1468,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 
         if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
             ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
-            ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
+            (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
         {
           hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
 
@@ -1781,7 +1781,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
                                   uint16_t ep_mps, uint8_t ep_type)
 {
-  HAL_StatusTypeDef  ret = HAL_OK;
+  HAL_StatusTypeDef ret = HAL_OK;
   PCD_EPTypeDef *ep;
 
   if ((ep_addr & 0x80U) == 0x80U)
@@ -1796,7 +1796,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
   }
 
   ep->num = ep_addr & EP_ADDR_MSK;
-  ep->maxpacket = ep_mps;
+  ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
   ep->type = ep_type;
 
   if (ep->is_in != 0U)
@@ -2346,13 +2346,11 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
 }
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
-
 /**
   * @}
   */
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 #endif /* HAL_PCD_MODULE_ENABLED */
-
 /**
   * @}
   */

Src/stm32h7rsxx_hal_pka.c

@@ -288,9 +288,6 @@
   */
 
 /* Private variables ---------------------------------------------------------*/
-static uint32_t   primeordersize;
-static uint32_t   opsize;
-static uint32_t   modulussize;
 /* Private function prototypes -----------------------------------------------*/
 /** @defgroup PKA_Private_Functions PKA Private Functions
   * @{
@@ -864,7 +861,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExp_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   /* Start the operation */
   return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
 }
@@ -879,7 +876,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExp_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   /* Start the operation */
   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
 }
@@ -895,7 +892,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExpFastMode_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   /* Start the operation */
   return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
 }
@@ -910,7 +907,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExpFastMode_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   /* Start the operation */
   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
 }
@@ -928,7 +925,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExpProtectMode_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
 }
 
@@ -943,7 +940,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE
 {
   /* Set input parameter in PKA RAM */
   PKA_ModExpProtectMode_Set(hpka, in);
-  opsize = in->OpSize;
+  hpka->opsize = in->OpSize;
   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
 }
 
@@ -959,7 +956,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
   uint32_t size;
 
   /* Get output result size */
-  size = opsize;
+  size = hpka->opsize;
 
   /* Move the result to appropriate location (indicated in out parameter) */
   PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size);
@@ -976,7 +973,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType
 {
   /* Set input parameter in PKA RAM */
   PKA_ECDSASign_Set(hpka, in);
-  primeordersize = in->primeOrderSize;
+  hpka->primeordersize = in->primeOrderSize;
   /* Start the operation */
   return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
 }
@@ -991,7 +988,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT
 {
   /* Set input parameter in PKA RAM */
   PKA_ECDSASign_Set(hpka, in);
-  primeordersize = in->primeOrderSize;
+  hpka->primeordersize = in->primeOrderSize;
   /* Start the operation */
   return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
 }
@@ -1008,7 +1005,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe
   uint32_t size;
 
   /* Get output result size */
-  size = primeordersize;
+  size = hpka->primeordersize;
 
 
   if (out != NULL)
@@ -1124,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
   */
 HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
 {
-  /* Set input parameter in PKA RAM */
-  PKA_PointCheck_Set(hpka, in);
+  if ((in->pMontgomeryParam) != NULL)
+  {
+    /* Set input parameter in PKA RAM */
+    PKA_PointCheck_Set(hpka, in);
 
-  /* Start the operation */
-  return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
+    /* Start the operation */
+    return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
 }
 
 /**
@@ -1139,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy
   */
 HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
 {
-  /* Set input parameter in PKA RAM */
-  PKA_PointCheck_Set(hpka, in);
+  if ((in->pMontgomeryParam) != NULL)
+  {
+    /* Set input parameter in PKA RAM */
+    PKA_PointCheck_Set(hpka, in);
 
-  /* Start the operation */
-  return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
+    /* Start the operation */
+    return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
 }
 
 /**
@@ -1169,7 +1180,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i
 {
   /* Set input parameter in PKA RAM */
   PKA_ECCMul_Set(hpka, in);
-  modulussize = in->modulusSize;
+  hpka->modulussize = in->modulusSize;
   /* Start the operation */
   return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
 }
@@ -1184,7 +1195,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef
 {
   /* Set input parameter in PKA RAM */
   PKA_ECCMul_Set(hpka, in);
-  modulussize = in->modulusSize;
+  hpka->modulussize = in->modulusSize;
   /* Start the operation */
   return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
 }
@@ -1199,7 +1210,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDe
 {
   /* Set input parameter in PKA RAM */
   PKA_ECCMulEx_Set(hpka, in);
-  modulussize = in->modulusSize;
+  hpka->modulussize = in->modulusSize;
   /* Start the operation */
   return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
 }
@@ -1214,7 +1225,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTyp
 {
   /* Set input parameter in PKA RAM */
   PKA_ECCMulEx_Set(hpka, in);
-  modulussize = in->modulusSize;
+  hpka->modulussize = in->modulusSize;
   /* Start the operation */
   return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
 }
@@ -1229,7 +1240,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out
   uint32_t size;
 
   /* Get output result size */
-  size = modulussize;
+  size = hpka->modulussize;
 
   /* If a destination buffer is provided */
   if (out != NULL)

Src/stm32h7rsxx_hal_rng.c

@@ -641,6 +641,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
       status = RNG_RecoverSeedError(hrng);
       if (status == HAL_ERROR)
       {
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED;
         return status;
       }
     }

Src/stm32h7rsxx_hal_rng_ex.c

@@ -306,6 +306,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
 
     /* sequence to fully recover from a seed error */
     status = RNG_RecoverSeedError(hrng);
+    if (status == HAL_ERROR)
+    {
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED;
+    }
   }
   else
   {

Src/stm32h7rsxx_hal_sd.c

@@ -2111,7 +2111,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
   *         contains all CID register parameters
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
 {
   pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
 
@@ -2327,7 +2327,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
   *         will contain the SD card status information
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
 {
   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);

Src/stm32h7rsxx_hal_sd_ex.c

@@ -196,7 +196,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTyp
   * @param  NumberOfBlocks: Total number of blocks to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd,
+                                                    const SDMMC_DMALinkedListTypeDef *pLinkedList,
                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -290,7 +291,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC
   * @param  NumberOfBlocks: Total number of blocks to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList,
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd,
+                                                     const SDMMC_DMALinkedListTypeDef *pLinkedList,
                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks)
 
 {

Src/stm32h7rsxx_hal_sdio.c

@@ -0,0 +1,2877 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7rsxx_hal_sdio.c
+  * @author  MCD Application Team
+  * @brief   SDIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital Input Output (SDIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this SDIO card. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_SDIO_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with SDIO cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implementing the HAL_SDIO_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for SDIO card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) NVIC configuration if you need to use interrupt process (HAL_SDIO_ReadExtended_DMA()
+             and HAL_SDIO_WriteExtended_DMA() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SDIO_ENABLE_IT()
+                  and __HAL_SDIO_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SDIO_GET_IT().
+        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+    (#) At this stage, you can perform SDIO read/write/erase operations after SDIO card initialization.
+
+  *** SDIO Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SDIO Card, use the HAL_SDIO_Init() function. It Initializes
+    SDMMC Peripheral(STM32 side) and the SDIO Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SDIO Card initialization process at 400KHz. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SDIO Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+        In initialization mode and according to the SDIO Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the SDIO card. The API used is HAL_SDIO_Init().
+        This phase allows the card initialization and identification.
+
+    (#) Configure the SDIO Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field by the API HAL_SDIO_ConfigFrequency().
+
+    (#) Configure the SDIO Card in wide bus mode: 4-bits data by the API HAL_SDIO_SetDataBusWidth().
+
+    (#) Configure the SDIO Card data block size by the API : HAL_SDIO_SetBlockSize().
+
+    (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode().
+
+    (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback
+        function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function.
+
+  *** SDIO Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SDIO card in polling mode by using function HAL_SDIO_ReadExtended().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+
+    (+) You can read from SDIO card in DMA mode by using function HAL_SDIO_ReadExtended_DMA().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+        After this, you have to ensure that the transfer is done correctly.
+        You could also check the DMA transfer process through the SDIO Rx interrupt event.
+
+  *** SDIO Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SDIO card in polling mode by using function HAL_SDIO_WriteExtended().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+
+    (+) You can write to SDIO card in DMA mode by using function HAL_SDIO_WriteExtended_DMA().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+        You could also check the DMA transfer process through the SDIO Tx interrupt event.
+
+
+  *** SDIO card common control register (CCCR) ***
+  ======================
+  [..]
+    (+) The SDIO CCCR allow for quick host checking and control of an IO card's enable and interrupts on a per card and
+        per function basis.
+        To get the Card common control registers field, you can use the API HAL_SDIO_GetCardCommonControlRegister().
+
+  *** SDIO card Function basic register (FBR) ***
+  ===========================
+  [..]
+    (+) The SDIO card function basic register are used to allow the host to quickly determine the abilities and
+        requirements of each function.
+    (+) To get the SDIO function basic register information, you can use the API HAL_SDIO_GetCardFBRRegister().
+
+  *** SDIO HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SDIO HAL driver.
+
+    (+) __HAL_SDIO_ENABLE_IT: Enable the SDIO device interrupt
+    (+) __HAL_SDIO_DISABLE_IT: Disable the SDIO device interrupt
+    (+) __HAL_SDIO_GET_FLAG: Check whether the specified SDIO flag is set or not
+    (+) __HAL_SDIO_CLEAR_FLAG: Clear the SDIO's pending flags
+    (+) __HAL_SDIO_GET_IT: Check whether the specified SDIO interrupt has occurred or not
+    (+) __HAL_SDIO_GET_IT_SOURCE: Checks whether the specified SDIO interrupt is enabled or not
+
+    (@) You can refer to the SDIO HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SDIO_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) MspInitCallback    : SDIO MspInit.
+      (+) MspDeInitCallback  : SDIO MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+    For specific callbacks TransceiverCallback use dedicated register callbacks:
+    respectively HAL_SDIO_RegisterTransceiverCallback().
+
+    Use function HAL_SDIO_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) MspInitCallback    : SDIO MspInit.
+      (+) MspDeInitCallback  : SDIO MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+    For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+    respectively HAL_SDIO_UnRegisterTransceiverCallback().
+
+    By default, after the HAL_SDIO_Init and if the state is HAL_SDIO_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_SDIO_Init
+    and HAL_SDIO_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SDIO_Init and HAL_SDIO_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SDIO_RegisterCallback before calling HAL_SDIO_DeInit
+    or HAL_SDIO_Init function.
+
+    When The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  *** SDIO peripheral IO interrupt ***
+  =============================================
+  [..]
+  (+) Below the list of most used SDIO function to check and control the IO card's enable and interrupts on a per
+      functions basis.
+
+    (+) HAL_SDIO_EnableIOFunctionInterrupt: Enable SDIO IO interrupt.
+    (+) HAL_SDIO_DisableIOFunctionInterrupt: Disable SDIO IO interrupt.
+    (+) HAL_SDIO_EnableIOFunction: Enable Function number(0-7)
+    (+) HAL_SDIO_DisableIOFunction: Disable Function number(0-7)
+    (+) HAL_SDIO_SelectIOFunction: Select a function number(0-7)
+    (+) HAL_SDIO_AbortIOFunction: Abort an IO read or write operation and free the SDIO bus.
+    (+) HAL_SDIO_EnableIOAsynInterrupt: Enable Bit of asynchronous interrupt
+    (+) HAL_SDIO_DisableIOAsynInterrupt: Disable Bit of asynchronous interrupt
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32h7rsxx_hal.h"
+
+/** @addtogroup STM32H7RSxx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_SDIO_MODULE_ENABLED
+
+/* Private define ----------------------------------------------------------------------------------------------------*/
+/** @addtogroup SDIO_Private_Defines
+  * @{
+  */
+#define SDIO_INIT_FREQ         400000U /*!< Initialization phase : 400 kHz max */
+#define SDIO_TIMEOUT           1000U   /*!< SDIO timeout millisecond           */
+
+#define SDIO_FUNCTION_0        0x00U   /*!< SDIO_Functions 0                   */
+#define SDIO_FUNCTION_1        0x01U   /*!< SDIO_Functions 1                   */
+
+#define SDIO_READ              0x0U    /*!< Read flag for cmd52 and cmd53      */
+#define SDIO_WRITE             0x1U    /*!< Write flag for cmd52 and cmd53     */
+
+#define SDIO_BUS_SPEED_SDR12   0x00U   /*!< SDIO bus speed mode SDR12          */
+#define SDIO_BUS_SPEED_SDR25   0x02U   /*!< SDIO bus speed mode SDR25          */
+#define SDIO_BUS_SPEED_SDR50   0x04U   /*!< SDIO bus speed mode SDR50          */
+#define SDIO_BUS_SPEED_DDR50   0x08U   /*!< SDIO bus speed mode DDR50          */
+
+#define SDIO_CCCR_REG_NUMBER   0x16U   /*!< SDIO card cccr register number     */
+
+#define SDIO_OCR_VDD_32_33     (1U << 20U)
+#define SDIO_OCR_SDIO_S18R     (1U << 24U)
+/**
+  * @}
+  */
+
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+#define IS_SDIO_RAW_FLAG(ReadAfterWrite)   (((ReadAfterWrite) == HAL_SDIO_WRITE_ONLY) || \
+                                            ((ReadAfterWrite) == HAL_SDIO_READ_AFTER_WRITE))
+
+#define IS_SDIO_FUNCTION(FN)        (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7))
+
+#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE))
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions SDIO Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio);
+static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr,
+                                         uint8_t *pData);
+static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr,
+                                          uint8_t *pData);
+static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg,
+                                            uint8_t *pData, uint16_t Size_byte);
+static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size);
+static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDIO_Exported_Functions
+  * @{
+  */
+/** @addtogroup SDIO_Exported_Functions_Group1
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SDIO
+    device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the SDIO according to the specified parameters in the
+            SDIO_HandleTypeDef and create the associated handle.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio)
+{
+  SDIO_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+  uint8_t data;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsdio->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsdio->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsdio->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsdio->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsdio->Init.ClockDiv));
+
+  /* Check the SDIO handle allocation */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SDIO_STATE_RESET only */
+    hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback;
+    hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback;
+    hsdio->ErrorCallback  = HAL_SDIO_ErrorCallback;
+#if (USE_SDIO_TRANSCEIVER != 0U)
+    if (hsdio->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback;
+    }
+#endif /* USE_SDIO_TRANSCEIVER */
+
+    if (hsdio->MspInitCallback == NULL)
+    {
+      hsdio->MspInitCallback = HAL_SDIO_MspInit;
+    }
+    /* Init the low level hardware */
+    hsdio->MspInitCallback(hsdio);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SDIO_MspInit(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+  }
+
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+  sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12);
+  if (sdmmc_clk == 0U)
+  {
+    hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+    return HAL_ERROR;
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * SDIO_INIT_FREQ);
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hsdio->Instance, Init);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsdio->Instance);
+
+  /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */
+  sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+
+  if (hsdio->SDIO_IdentifyCard == NULL)
+  {
+    hsdio->SDIO_IdentifyCard = SDIO_InitCard;
+  }
+  /* SDIO enumeration sequence */
+  if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK)
+  {
+    hsdio->State = HAL_SDIO_STATE_RESET;
+    return HAL_ERROR;
+  }
+
+  /* Configure the SDMMC user parameters */
+  Init.ClockEdge           = hsdio->Init.ClockEdge;
+  Init.ClockPowerSave      = hsdio->Init.ClockPowerSave;
+  Init.BusWide             = hsdio->Init.BusWide;
+  Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl;
+  Init.ClockDiv            = hsdio->Init.ClockDiv;
+  (void)SDMMC_Init(hsdio->Instance, Init);
+
+  data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U;
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->Context = SDIO_CONTEXT_NONE;
+  hsdio->State = HAL_SDIO_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SDIO device.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance));
+
+  /* Check the SDIO handle allocation */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hsdio->Instance);
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+  if (hsdio->MspDeInitCallback == NULL)
+  {
+    hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsdio->MspDeInitCallback(hsdio);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SDIO_MspDeInit(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+  hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+  hsdio->State = HAL_SDIO_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SDIO MSP.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SDIO MSP.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_MspDeInit could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group2
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to re-configure the SDIO peripheral.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by card.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  BusWide: Specifies the SDIO card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide)
+{
+  uint8_t data;
+  HAL_StatusTypeDef error_state = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    data = (BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U;
+    MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_WIDBUS,
+               (BusWide == HAL_SDIO_4_WIRES_MODE) ? SDMMC_BUS_WIDE_4B : SDMMC_BUS_WIDE_1B);
+
+    if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK)
+    {
+      error_state =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    error_state =  HAL_ERROR;
+  }
+
+  return error_state;
+}
+
+/**
+  * @brief  Update the SDIO Clock.
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  ClockSpeed: SDIO Clock speed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed)
+{
+  uint32_t ClockDiv;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12)) / (2U * ClockSpeed);
+    MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the SDIO block size.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  function_nbr: Specifies the SDIO function number.
+  * @param  BlockSize: Specifies the SDIO Block size to set.
+  *         This parameter can be one of the following values @ref SDIO_Exported_Constansts_Group7.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize)
+{
+  HAL_SDIO_ExtendedCmd_TypeDef cmd53;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(function_nbr));
+  assert_param(IS_SDIO_SUPPORTED_BLOCK_SIZE(BlockSize));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set SDIO F1 block size */
+  cmd53.IOFunctionNbr = SDIO_FUNCTION_0;
+  cmd53.OpCode = HAL_SDIO_OP_CODE_AUTO_INC;
+  cmd53.Block_Mode = HAL_SDIO_MODE_BYTE;
+  cmd53.Reg_Addr = (function_nbr * 0x100UL) + 0x10UL;
+  if (SDIO_WriteExtended(hsdio, &cmd53, (uint8_t *)(&BlockSize), 2U) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->block_size = BlockSize;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the data rate.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  DataRate: Specifies the SDIO data rate to set.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate)
+{
+  HAL_StatusTypeDef errorstate = HAL_OK;
+  uint8_t data;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (DataRate)
+  {
+    case HAL_SDIOS_DATA_RATE_SDR25:
+      data = SDIO_BUS_SPEED_SDR25;
+      errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      break;
+
+    case HAL_SDIOS_DATA_RATE_SDR50:
+      data = SDIO_BUS_SPEED_SDR50;
+      errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U)
+                                            | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED);
+      break;
+
+    case HAL_SDIOS_DATA_RATE_DDR50:
+      data = SDIO_BUS_SPEED_DDR50;
+      errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) |
+                                            SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED,
+                 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED);
+      break;
+    default: /* SDR12 */
+      break;
+  }
+
+  return (errorstate != HAL_OK) ? HAL_ERROR : HAL_OK;
+}
+
+/**
+  * @brief  Reset SDIO Card
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t data = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /**  To reset the SDIO module by CMD52 with writing to RES in CCCR or send CMD0 the card shall change the speed mode
+    *  default speed mode.
+    *  The reset cmd (cmd0) is only used for memory. In order to reset an I/O card or the I/O portion of a combo card,
+    *  Use CMD52 to write 1 to the RES bit in the CCC(bit3 of register 6).
+    */
+  if (SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) |
+                               SDMMC_SDIO_CCCR4_SD_BYTE2),
+                       HAL_SDIO_WRITE_ONLY,
+                       0U,
+                       &data) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->State = HAL_SDIO_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Card Common Control register (CCCR).
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  pCccr: Pointer to Cccr register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr)
+{
+  uint8_t tempBuffer[256] = {0U};
+  uint32_t count;
+
+  assert_param(hsdio != NULL);
+  assert_param(pCccr != NULL);
+
+  if ((hsdio == NULL) || (pCccr == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++)
+  {
+    if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0 + count, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) !=
+        HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  pCccr->cccr_revision = tempBuffer[0] & 0x0FU;
+  pCccr->sdio_revision = (tempBuffer[0] & 0xF0U) >> 4U;
+  pCccr->sd_spec_revision = tempBuffer[0x01U] & 0x0FU;
+  pCccr->bus_width_8Bit = ((tempBuffer[0x07U] & 0x04U) != 0U) ? HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED
+                          : HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED;
+  pCccr->card_capability = (tempBuffer[0x08U] & 0xDFUL);
+  /* common CIS pointer */
+  pCccr->commonCISPointer = tempBuffer[0x09U] | ((uint32_t)tempBuffer[(uint32_t)0x09U + 1U] << 8U) |
+                            ((uint32_t)tempBuffer[(uint32_t)0x09U + 2U] << 16U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Card Function Basic register(FBR).
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  pFbr: Pointer to Fbr register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr)
+{
+  uint8_t tempBuffer[256] = {0U};
+  uint32_t count;
+  uint8_t func_idx;
+
+  assert_param(hsdio != NULL);
+  assert_param(pFbr != NULL);
+
+  if ((hsdio == NULL) || (pFbr == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  for (func_idx = 2U; func_idx <= SDIO_MAX_IO_NUMBER; func_idx++)
+  {
+    for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++)
+    {
+      if (SDIO_ReadDirect(hsdio, (((uint32_t)SDMMC_SDIO_F1BR0 * (uint32_t)func_idx) + count),
+                          HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    pFbr[(uint32_t)func_idx - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU;
+    pFbr[(uint32_t)func_idx - 1U].ioExtFunctionCode = tempBuffer[1U];
+    pFbr[(uint32_t)func_idx - 1U].ioPointerToCIS = tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) |
+                                                   ((uint32_t)tempBuffer[11U] << 16U);
+    pFbr[(uint32_t)func_idx - 1U].ioPointerToCSA = tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) |
+                                                   ((uint32_t)tempBuffer[14U] << 16U);
+    if ((tempBuffer[2U] & 0x01U) != 0U)
+    {
+      pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_POWER_SELECTION;
+    }
+    if ((tempBuffer[0U] & 0x40U) != 0U)
+    {
+      pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_CSA;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group3
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Data management functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data transfer from/to SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Read data from a specified address using the direct mode through cmd52.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Specifies the SDIO Argument.
+  * @param  pData: pointer to the buffer that will contain the received data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData)
+{
+  uint32_t cmd;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+  assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite));
+
+  if ((hsdio == NULL) || (Argument == NULL) || (NULL == pData))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    cmd = SDIO_READ << 31U;
+    cmd |= (((uint32_t)Argument->IOFunctionNbr) << 28U);
+    cmd |= (((uint32_t)Argument->ReadAfterWrite) << 27U);
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= 0U;
+    errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData);
+
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Read data from a specified address using the direct mode through cmd52.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Specifies the SDIO Argument.
+  * @param  Data: pointer to the buffer that will contain the received data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data)
+{
+  uint32_t cmd;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite));
+
+  if ((hsdio == NULL) || (Argument == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    cmd = SDIO_WRITE << 31U;
+    cmd |= ((uint32_t)Argument->IOFunctionNbr) << 28U;
+    cmd |= ((uint32_t)Argument->ReadAfterWrite) << 27U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= Data;
+    errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &Data);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from a specified address using extended mode through cmd53.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:   size to read.
+  * @param  Timeout_Ms:  Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                        uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t *tempbuff = pData;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                          SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM         = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Correspond to the write or read bit of the CMD argument */
+    /* Read */
+    hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK :
+                     SDIO_CONTEXT_READ_SINGLE_BLOCK;
+    cmd = SDIO_READ << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= (Size_byte & 0x1FFU);
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+
+    while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL |
+                                SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (regCount = 0U; regCount < 8U; regCount++)
+        {
+          data = SDMMC_ReadFIFO(hsdio->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+        }
+        dataremaining -= 32U;
+      }
+      else if (dataremaining < 32U)
+      {
+        while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE)))
+        {
+          data = SDMMC_ReadFIFO(hsdio->Instance);
+          for (byteCount = 0U; byteCount < 4U; byteCount++)
+          {
+            if (dataremaining > 0U)
+            {
+              *tempbuff = (uint8_t)((data >> (byteCount * 8U)) & 0xFFU);
+              tempbuff++;
+              dataremaining--;
+            }
+          }
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+      if ((HAL_GetTick() - tickstart) >=  Timeout_Ms)
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+    /* Get error state */
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_RX_OVERRUN;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write data from a specified address using extended mode through cmd53.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @param  Timeout_Ms:  Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                         uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t *u32tempbuff = pData;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                           SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Correspond to the write or read bit of the CMD argument */
+    hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                     SDIO_CONTEXT_WRITE_SINGLE_BLOCK;
+    cmd = SDIO_WRITE << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= (Size_byte & 0x1FFU);
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                                SDMMC_FLAG_DATAEND))
+    {
+
+      if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (regCount = 0U; regCount < 8U; regCount++)
+        {
+          hsdio->Instance->FIFO = *u32tempbuff;
+          u32tempbuff++;
+        }
+        dataremaining -= 32U;
+      }
+      else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)))
+      {
+        uint8_t *u8buff = (uint8_t *)u32tempbuff;
+        while (dataremaining > 0U)
+        {
+          data = 0U;
+          for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++)
+          {
+            data |= ((uint32_t)(*u8buff) << (byteCount << 3U));
+            u8buff++;
+            dataremaining--;
+          }
+          hsdio->Instance->FIFO = data;
+        }
+      }
+      if (((HAL_GetTick() - tickstart) >=  Timeout_Ms))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+    /* Get error state */
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from a specified address using extended mode through cmd53 in DMA mode.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                            uint8_t *pData, uint32_t Size_byte)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint8_t *p_dma_buffer;
+  uint32_t cmd;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    p_dma_buffer = (uint8_t *)pData;
+    hsdio->pRxBuffPtr = (uint8_t *)pData;
+    hsdio->RxXferSize = Size_byte;
+    hsdio->next_data_addr = (uint32_t)pData;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    if (nbr_of_block != 0U)
+    {
+      hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block));
+      hsdio->next_reg_addr = (Argument->Reg_Addr) | ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U)
+                             | ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U);
+      hsdio->next_data_addr += (nbr_of_block * hsdio->block_size);
+    }
+    else
+    {
+      hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte :
+                               HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      if (hsdio->remaining_data != 0U)
+      {
+        hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                                (Size_byte - hsdio->remaining_data);
+        hsdio->next_reg_addr += (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \
+                                (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE + 1U) : (Size_byte + 1U);
+      }
+    }
+
+    /* DMA configuration (use single buffer) */
+    hsdio->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+    hsdio->Instance->IDMABASER = (uint32_t)p_dma_buffer;
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC ;
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                           SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Read */
+    hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK :
+                                SDIO_CONTEXT_READ_SINGLE_BLOCK) | SDIO_CONTEXT_DMA;
+
+    cmd = SDIO_READ << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= ((nbr_of_block == 0U) ? Size_byte :  nbr_of_block) & 0x1FFU;
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Enable interrupt */
+    __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write data from a specified address using extended mode through cmd53 in DMA mode.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                             uint8_t *pData, uint32_t Size_byte)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint8_t *p_dma_buffer;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    p_dma_buffer = (uint8_t *)pData;
+    hsdio->pTxBuffPtr = (uint8_t *)pData;
+    hsdio->TxXferSize = Size_byte;
+    hsdio->next_data_addr = (uint32_t)pData;
+
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    if (nbr_of_block != 0U)
+    {
+      hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block));
+      if (hsdio->block_size <= 128U)
+      {
+        hsdio->next_reg_addr = (Argument->Reg_Addr) |
+                               ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) |
+                               ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U);
+      }
+      else
+      {
+        hsdio->next_reg_addr = (nbr_of_block * hsdio->block_size) >> 1U;
+      }
+      hsdio->next_data_addr += (nbr_of_block * hsdio->block_size);
+    }
+    else
+    {
+      hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                              (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                              (Size_byte - hsdio->remaining_data);
+      if (hsdio->remaining_data != 0U)
+      {
+        hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                                (Size_byte - hsdio->remaining_data);
+        hsdio->next_reg_addr += ((Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \
+                                 (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE >> 1U) : (Size_byte >> 1U)) |
+                                (((hsdio->remaining_data > 0U) ? 0U : 1U));
+      }
+      hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte :
+                               HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+    }
+
+    /* DMA configuration (use single buffer) */
+    hsdio->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+    hsdio->Instance->IDMABASER = (uint32_t)p_dma_buffer;
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength = (Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK
+                           : SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Write */
+    hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ?
+                                SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                                SDIO_CONTEXT_WRITE_SINGLE_BLOCK) | SDIO_CONTEXT_DMA;
+    cmd = SDIO_WRITE << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= ((nbr_of_block == 0U) ? ((Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                    HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte) : nbr_of_block) & 0x1FFU;
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Enable interrupt */
+    __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group4
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set callback functions allowing to manage the data transfer from/to SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles SDIO device interrupt request.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio)
+{
+  HAL_SDIO_ExtendedCmd_TypeDef CMD53_desc;
+  HAL_StatusTypeDef errorstate;
+  uint32_t ctx = hsdio->Context;
+  uint32_t flags;
+
+  flags   = READ_REG(((SDMMC_TypeDef *)((uint32_t)(hsdio)->Instance))->STA);
+
+  if (READ_BIT(flags, SDMMC_FLAG_SDIOIT) != 0U)
+  {
+    (void)SDIO_IOFunction_IRQHandler(hsdio);
+  }
+
+  if (READ_BIT(flags, SDMMC_FLAG_DATAEND) != 0U)
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_FLAG_DATAEND);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR |
+                          SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF);
+
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_IDMABTC);
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    if ((ctx & SDIO_CONTEXT_DMA) != 0U)
+    {
+      hsdio->Instance->DLEN = 0;
+      hsdio->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+      if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+      {
+        hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+      }
+      else
+      {
+        hsdio->Instance->DCTRL = 0U;
+      }
+
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      hsdio->State = HAL_SDIO_STATE_READY;
+    }
+
+    if (hsdio->remaining_data != 0U)
+    {
+      CMD53_desc.Block_Mode = HAL_SDIO_MODE_BYTE;
+      CMD53_desc.Reg_Addr = hsdio->next_reg_addr;
+      CMD53_desc.IOFunctionNbr = 1;
+      CMD53_desc.OpCode = 1;
+      if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+        hsdio->pRxBuffPtr = (uint8_t *)hsdio->next_data_addr;
+        errorstate =  HAL_SDIO_ReadExtended_DMA(hsdio, &CMD53_desc, hsdio->pRxBuffPtr, hsdio->remaining_data);
+      }
+      else
+      {
+        hsdio->pTxBuffPtr = (uint8_t *)hsdio->next_data_addr;
+        errorstate =  HAL_SDIO_WriteExtended_DMA(hsdio, &CMD53_desc, hsdio->pTxBuffPtr, hsdio->remaining_data);
+      }
+      if (errorstate != HAL_OK)
+      {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1)
+        hsdio->ErrorCallback(hsdio);
+#else
+        HAL_SDIO_ErrorCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+      }
+    }
+    else if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+      hsdio->RxCpltCallback(hsdio);
+#else
+      HAL_SDIO_RxCpltCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+    }
+    else
+    {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+      hsdio->TxCpltCallback(hsdio);
+#else
+      HAL_SDIO_TxCpltCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+    }
+  }
+
+  if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR))
+  {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1)
+    hsdio->ErrorCallback(hsdio);
+#else
+    HAL_SDIO_ErrorCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsdio: Pointer SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SDIO error callbacks
+  * @param hsdio: Pointer SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SDIO IO Function complete callback
+  * @param hsdio: Pointer SDIO handle
+  * @param func: SDIO IO Function
+  * @retval None
+  */
+__weak void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+  UNUSED(func);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_ErrorCallback can be implemented in the user file
+   */
+}
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/**
+  * @brief  Enable/Disable the SDIO Transceiver 1.8V Mode Callback.
+  * @param  hsdio: Pointer SDIO handle
+  * @param  status: Voltage Switch State
+  * @retval None
+  */
+__weak  void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+  UNUSED(status);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_EnableTransceiver could be implemented in the user file
+   */
+}
+#endif /* USE_SDIO_TRANSCEIVER  */
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SDIO Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDIO_TX_CPLT_CB_ID                 SDIO Tx Complete Callback ID
+  *          @arg @ref HAL_SDIO_RX_CPLT_CB_ID                 SDIO Rx Complete Callback ID
+  *          @arg @ref HAL_SDIO_ERROR_CB_ID                   SDIO Error Callback ID
+  *          @arg @ref HAL_SDIO_MSP_INIT_CB_ID                SDIO MspInit Callback ID
+  *          @arg @ref HAL_SDIO_MSP_DEINIT_CB_ID              SDIO MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID,
+                                            pSDIO_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(pCallback != NULL);
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_TX_CPLT_CB_ID :
+        hsdio->TxCpltCallback = pCallback;
+        break;
+      case HAL_SDIO_RX_CPLT_CB_ID :
+        hsdio->RxCpltCallback = pCallback;
+        break;
+      case HAL_SDIO_ERROR_CB_ID :
+        hsdio->ErrorCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDIO Callback
+  *         SDIO Callback is redirected to the weak (overridden) predefined callback.
+  * @note   The HAL_SDIO_UnRegisterCallback() may be called before HAL_SDIO_Init() in
+  *         HAL_SDIO_STATE_RESET to register callbacks for HAL_SDIO_MSP_INIT_CB_ID
+  *         and HAL_SDIO_MSP_DEINIT_CB_ID.
+  * @param hsdio : SDIO handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values @ref SDIO_Exported_Types_Group3.
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_TX_CPLT_CB_ID :
+        hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback;
+        break;
+      case HAL_SDIO_RX_CPLT_CB_ID :
+        hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback;
+        break;
+      case HAL_SDIO_ERROR_CB_ID :
+        hsdio->ErrorCallback = HAL_SDIO_ErrorCallback;
+        break;
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = HAL_SDIO_MspInit;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+        break;
+      default :
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = HAL_SDIO_MspInit;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+        break;
+      default :
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/**
+  * @brief  Register a User SDIO Transceiver Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio,
+                                                       pSDIO_TransceiverCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->DriveTransceiver_1_8V_Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDIO Transceiver Callback
+  *         SDIO Callback is redirected to the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_SDIO_TRANSCEIVER */
+
+/**
+  * @brief Register a User SDIO Identification Callback
+  * @param hsdio: Pointer to SDIO handle
+  * @param pCallback: pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio,
+                                                        pSDIO_IdentifyCardCallbackTypeDef pCallback)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(pCallback != NULL);
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  hsdio->SDIO_IdentifyCard = pCallback;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group5
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SDIO card operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief return the SDIO state
+  * @param hsdio: Pointer to SDIO handle
+  * @retval HAL state
+  */
+HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio)
+{
+  return hsdio->State;
+}
+
+/**
+  * @brief  Return the SDIO error code
+  * @param  hsdio : Pointer to a SDIO_HandleTypeDef structure that contains the configuration information.
+  * @retval SDIO Error Code
+  */
+uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio)
+{
+  return hsdio->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group6
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Peripheral IO interrupt #####
+  ==============================================================================
+  [..]
+    This subsection provides a set functions allowing to enable/disable IO functions interrupt features
+    on the SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enable SDIO IO interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t intEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if ((((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U))
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    intEn |= (1U << (uint32_t)IOFunction) | 0x01U;
+    hsdio->IOInterruptNbr++;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0,
+                       &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  __HAL_SDIO_ENABLE_IT(hsdio, SDMMC_IT_SDIOIT);
+
+  /* Enable host SDIO interrupt operations */
+  __SDMMC_OPERATION_ENABLE(hsdio->Instance);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable SDIO IO interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t intEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already disable , do not need enable again */
+  if (((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    /* disable the interrupt, don't disable the interrupt master here */
+    intEn &= ~(1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->IOInterruptNbr > 1U)
+  {
+    hsdio->IOInterruptNbr--;
+  }
+  else
+  {
+    hsdio->IOInterruptNbr = 0U;
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_SDIOIT);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t ioEn  = 0U;
+  uint8_t ioReady = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need to enable again */
+  if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    ioEn |= (1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioReady) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* check if IO ready */
+  if ((ioReady & (1U << (uint32_t)IOFunction)) != 0U)
+  {
+    return HAL_OK;
+  }
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t ioEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    ioEn &= ~(1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR12_SD_BYTE1, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       (uint8_t *)&IOFunction) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort IO transfer.
+  * @param  hsdio:  Pointer to SDIO handle
+  * @param IOFunction IO number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       (uint8_t *)&IOFunction) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable Assynchrone interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t enable_asyn_it  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it)
+      != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if ((enable_asyn_it & 0x02U) == 0x02U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    enable_asyn_it |= 0x02U;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &enable_asyn_it) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable Assynchrone interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t enable_asyn_it  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it)
+      != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already disable , do not need disable again */
+  if ((enable_asyn_it & 0x02U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    enable_asyn_it &= (uint8_t) ~(0x02U);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &enable_asyn_it) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief sdio set io IRQ handler.
+  * @param hsdio  Pointer to SDIO handle
+  * @param IOFunction IO function io number.
+  * @param Callback io IRQ handler.
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction,
+                                                      HAL_SDIO_IOFunction_CallbackTypeDef pCallback)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback;
+  hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction);
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function --------------------------------------------------------------------------------------------------*/
+/** @addtogroup SDIO_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Initializes the SDIO device.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio)
+{
+  uint32_t errorstate;
+  uint32_t timeout = 0U;
+  uint16_t sdio_rca = 1U;
+  uint32_t Resp4;
+  uint32_t nbr_of_func;
+
+  /* Identify card operating voltage */
+  errorstate = SDMMC_CmdGoIdleState(hsdio->Instance);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hsdio->Instance) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Send CMD5 */
+  errorstate = SDMMC_CmdSendOperationcondition(hsdio->Instance, 0U, &Resp4);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  nbr_of_func = ((Resp4 & 0x70000000U) >> 28U);
+  /* Check if Nbr of function > 0 and OCR valid */
+  if (nbr_of_func > 0U)
+  {
+    /* Send CMD5 with arg= S18R, WV*/
+    if (SDMMC_CmdSendOperationcondition(hsdio->Instance, (SDIO_OCR_VDD_32_33 | SDIO_OCR_SDIO_S18R), &Resp4)
+        != HAL_SDIO_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    /* Check if IORDY = 1 and S18A = 1 */
+    if ((((Resp4 & 0x80000000U) >> 31U) != 0U) && (((Resp4 & 0x1000000U) >> 24U) != 0U))
+    {
+      /* Send CMD11 to switch 1.8V mode */
+      errorstate = SDMMC_CmdVoltageSwitch(hsdio->Instance);
+      if (errorstate != HAL_SDIO_ERROR_NONE)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* S18A is not supported */
+    }
+  }
+
+  /** Cmd3 is sent while response is SDMMC_ERROR_ILLEGAL_CMD, due to the partial init test done before
+    * (sending cmd0 after the sequence cmd0/cmd3 is sent is considered illegal).
+    */
+  do
+  {
+    errorstate = SDMMC_CmdSetRelAdd(hsdio->Instance, &sdio_rca);
+    timeout++;
+    HAL_Delay(1);
+  } while ((errorstate == SDMMC_ERROR_ILLEGAL_CMD) && (timeout != SDIO_TIMEOUT));
+
+  if ((timeout == SDIO_TIMEOUT) || (errorstate != HAL_SDIO_ERROR_NONE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Select the Card ( Sending CMD7)*/
+  errorstate = SDMMC_CmdSelDesel(hsdio->Instance, (uint32_t)(((uint32_t)sdio_rca) << 16U));
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read 1 byte data.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted CMD52 structure
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw,
+                                         uint32_t function_nbr, uint8_t *pData)
+{
+  uint32_t errorstate;
+  uint32_t cmd;
+
+  cmd = SDIO_READ << 31U;
+  cmd |= function_nbr << 28U;
+  cmd |= raw << 27U;
+  cmd |= (addr & 0x1FFFFU) << 9U;
+  errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    hsdio->ErrorCode |= errorstate;
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+  /* Clear all the static flags */
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write 1 byte data.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted CMD52 structure
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw,
+                                          uint32_t function_nbr, uint8_t *pData)
+{
+  uint32_t errorstate;
+  uint32_t cmd;
+  uint8_t response;
+
+  cmd = SDIO_WRITE << 31U;
+  cmd |= function_nbr << 28U;
+  cmd |= raw << 27U;
+  cmd |= (addr & 0x1FFFFU) << 9U;
+  cmd |= ((uint32_t) * pData & 0x000000FFU);
+  errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &response);
+
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    hsdio->ErrorCode |= errorstate;
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+  /* Clear all the static flags */
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write multiple data with a single command.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted cmd53 structure
+  * @param  Size_byte: block size if CMD53 defined in HAL_SDIO_MODE_BLOCK
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg,
+                                            uint8_t *pData, uint16_t Size_byte)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData;
+  SDMMC_TypeDef *SDMMCx;
+  uint32_t cmd;
+  uint32_t nbr_of_block;
+
+  hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+
+  /* Compute how many blocks are to be send for pData of length data_size to be send */
+  nbr_of_block = (((uint32_t)Size_byte & ~((uint32_t)hsdio->block_size & 1U))) >> __CLZ(__RBIT(hsdio->block_size));
+
+  /* Initialize data control register */
+  if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+  {
+    hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+  }
+  else
+  {
+    hsdio->Instance->DCTRL = 0U;
+  }
+
+  /* Configure the SDIO DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  if (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK)
+  {
+    config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+    config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+  }
+  else
+  {
+    config.DataLength    = Size_byte;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+  }
+
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+  config.TransferMode  = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                         SDMMC_TRANSFER_MODE_SDIO;
+  config.DPSM          = SDMMC_DPSM_DISABLE;
+  (void)SDMMC_ConfigData(hsdio->Instance, &config);
+  __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+  hsdio->Context = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                   SDIO_CONTEXT_WRITE_SINGLE_BLOCK;
+  cmd = SDIO_WRITE << 31U;
+  cmd |= cmd_arg->IOFunctionNbr << 28U;
+  cmd |= cmd_arg->Block_Mode << 27U;
+  cmd |= cmd_arg->OpCode << 26U;
+  cmd |= (cmd_arg->Reg_Addr & 0x1FFFFU) << 9U;
+  cmd |= (((uint32_t)Size_byte) & 0x1FFU);
+  errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+    hsdio->ErrorCode |= errorstate;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+
+  SDMMCx = hsdio->Instance;
+  dataremaining = config.DataLength;
+  while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                              SDMMC_FLAG_DATAEND))
+  {
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+    {
+      for (regCount = 8U; regCount > 0U; regCount--)
+      {
+        SDMMCx->FIFO = *u32tempbuff;
+        u32tempbuff++;
+      }
+      dataremaining -= 32U;
+    }
+    else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)))
+    {
+      uint8_t *u8buff = (uint8_t *)u32tempbuff;
+      while (dataremaining > 0U)
+      {
+        data = 0U;
+        for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++)
+        {
+          data |= ((uint32_t)(*u8buff) << (byteCount << 3U));
+          u8buff++;
+          dataremaining--;
+        }
+        SDMMCx->FIFO = data;
+      }
+    }
+    if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+  if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Allows to convert a block size in the according SDMMC value for configuring the SDMMC when doing a CMD53
+  * @param  hsdio: Pointer to the SDIO handle.
+  * @param  block_size: block size in bytes
+  * @retval block size as DBLOCKSIZE[3:0] bits format
+  */
+static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size)
+{
+  UNUSED(hsdio);
+
+  uint8_t most_bit = (uint8_t)__CLZ(__RBIT(block_size));
+  /*(1 << most_bit) - 1) is the mask used for blocksize*/
+  if (((uint8_t)block_size & ((1U << most_bit) - 1U)) != 0U)
+  {
+    return (uint8_t)SDMMC_DATABLOCK_SIZE_4B;
+  }
+  return most_bit << SDMMC_DCTRL_DBLOCKSIZE_Pos;
+}
+
+/*!
+ * @brief SDIO card io pending interrupt handle function.
+ * @note  This function is used to handle the pending io interrupt.
+ *        To register a IO IRQ handler, Use HAL_SDIO_EnableIOInterrupt and HAL_SDIO_SetIOIRQHandler
+ * @param  hsdio: Pointer to SDIO handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t count;
+  uint8_t pendingInt;
+
+  if (hsdio->IOInterruptNbr == 1U)
+  {
+    if ((hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U]) != NULL)
+    {
+      (hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U])(hsdio, hsdio->IOFunctionMask - 1U);
+    }
+  }
+  else if ((hsdio->IOInterruptNbr > 1U) && (hsdio->IOFunctionMask != 0U))
+  {
+    /* Get pending int firstly */
+    if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE1, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &pendingInt) !=
+        HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    if ((pendingInt != 0U) && (hsdio->IOFunctionMask != 0U))
+    {
+      for (count = 1; count <= SDIO_MAX_IO_NUMBER; count++)
+      {
+        if (((pendingInt & (1U << count)) != 0U) && (((1U << count)  & hsdio->IOFunctionMask) != 0U))
+        {
+          if ((hsdio->SDIO_IOFunction_Callback[count - 1U]) != NULL)
+          {
+            (hsdio->SDIO_IOFunction_Callback[count - 1U])(hsdio, count);
+          }
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+#endif /* HAL_SDIO_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Src/stm32h7rsxx_hal_smbus.c

@@ -1925,7 +1925,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
         /* Increment Buffer pointer */
         hsmbus->pBuffPtr++;
 
-        if ((hsmbus->XferSize > 0U))
+        if (hsmbus->XferSize > 0U)
         {
           hsmbus->XferSize--;
           hsmbus->XferCount--;
@@ -2353,7 +2353,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
         /* Increment Buffer pointer */
         hsmbus->pBuffPtr++;
 
-        if ((hsmbus->XferSize > 0U))
+        if (hsmbus->XferSize > 0U)
         {
           hsmbus->XferSize--;
           hsmbus->XferCount--;

Src/stm32h7rsxx_hal_spi_ex.c

@@ -57,7 +57,6 @@
     data transfers.
 
     (#) SPIEx function:
-        (++) HAL_SPIEx_FlushRxFifo()
         (++) HAL_SPIEx_FlushRxFifo()
         (++) HAL_SPIEx_EnableLockConfiguration()
         (++) HAL_SPIEx_ConfigureUnderrun()

Src/stm32h7rsxx_hal_tim.c

@@ -8101,17 +8101,17 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   *            @arg TIM_TS_ITR0: Internal Trigger 0
   *            @arg TIM_TS_ITR1: Internal Trigger 1
   *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_CLOCKSOURCE_ITR3: Internal Trigger 3
-  *            @arg TIM_CLOCKSOURCE_ITR4: Internal Trigger 4
-  *            @arg TIM_CLOCKSOURCE_ITR5: Internal Trigger 5
-  *            @arg TIM_CLOCKSOURCE_ITR6: Internal Trigger 6
-  *            @arg TIM_CLOCKSOURCE_ITR7: Internal Trigger 7
-  *            @arg TIM_CLOCKSOURCE_ITR8: Internal Trigger 8
-  *            @arg TIM_CLOCKSOURCE_ITR9: Internal Trigger 9
-  *            @arg TIM_CLOCKSOURCE_ITR10: Internal Trigger 10
-  *            @arg TIM_CLOCKSOURCE_ITR11: Internal Trigger 11
-  *            @arg TIM_CLOCKSOURCE_ITR13: Internal Trigger 13
-  *            @arg TIM_CLOCKSOURCE_ITR14: Internal Trigger 14
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_ITR4: Internal Trigger 4
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8
+  *            @arg TIM_TS_ITR9: Internal Trigger 9
+  *            @arg TIM_TS_ITR10: Internal Trigger 10
+  *            @arg TIM_TS_ITR11: Internal Trigger 11
+  *            @arg TIM_TS_ITR13: Internal Trigger 13
+  *            @arg TIM_TS_ITR14: Internal Trigger 14
   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2

Src/stm32h7rsxx_hal_uart.c

@@ -1080,6 +1080,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
         reception services:
         (+) HAL_UARTEx_RxEventCallback()
 
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
         Errors are handled as follows :
        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
@@ -3903,12 +3906,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
      If Reception till IDLE event has been selected : use Rx Event callback */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
+    huart->RxXferCount = 0;
+
+    /* Check current nb of data still to be received on DMA side.
+       DMA Normal mode, remaining nb of data will be 0
+       DMA Circular mode, remaining nb of data is reset to RxXferSize */
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+    if (nb_remaining_rx_data < huart->RxXferSize)
+    {
+      /* Update nb of remaining data */
+      huart->RxXferCount = nb_remaining_rx_data;
+    }
+
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
     /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize);
+    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 #else
     /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
   }
   else
@@ -3941,12 +3956,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
      If Reception till IDLE event has been selected : use Rx Event callback */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
+    huart->RxXferCount = huart->RxXferSize / 2U;
+
+    /* Check current nb of data still to be received on DMA side. */
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+    if (nb_remaining_rx_data <= huart->RxXferSize)
+    {
+      /* Update nb of remaining data */
+      huart->RxXferCount = nb_remaining_rx_data;
+    }
+
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
     /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 #else
     /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
   }
   else

Src/stm32h7rsxx_hal_wwdg.c

@@ -95,7 +95,7 @@
     and a pointer to the user callback function.
 
     (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
-    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+    the default weak function. HAL_WWDG_UnRegisterCallback()
     takes as parameters the HAL peripheral handle and the Callback ID.
     This function allows to reset following callbacks:
         (++) EwiCallback : callback for  Early WakeUp Interrupt.
@@ -103,14 +103,14 @@
 
     [..]
     When calling HAL_WWDG_Init function, callbacks are reset to the
-    corresponding legacy weak (surcharged) functions:
+    corresponding legacy weak functions:
     HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
     not been registered before.
 
     [..]
     When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registering feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak (overridden) callbacks are used.
 
     *** WWDG HAL driver macros list ***
     ===================================
@@ -240,7 +240,7 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User WWDG Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used instead of the weak (overridden) predefined callback
   * @param  hwwdg WWDG handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_
 
 /**
   * @brief  Unregister a WWDG Callback
-  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
+  *         WWDG Callback is redirected to the weak (overridden) predefined callback
   * @param  hwwdg WWDG handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:

Src/stm32h7rsxx_hal_xspi.c

@@ -886,9 +886,10 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp
         if (pCmd->DataMode == HAL_XSPI_DATA_NONE)
         {
           /* When there is no data phase, the transfer start as soon as the configuration is done
-             so wait until TC flag is set to go back in idle state */
-          status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout);
+             so wait until BUSY flag is reset to go back in idle state. */
+          status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout);
 
+          /* Clear TC flag */
           HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
         }
         else
@@ -2832,7 +2833,7 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTyp
 
   for (index = 0U; index < (XSPI_NB_INSTANCE - 1U); index++)
   {
-    if ((IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort))
+    if (IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort)
     {
       /*Mux*/
       SET_BIT(XSPIM->CR, XSPIM_CR_MUXEN);
@@ -3238,7 +3239,7 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC
       /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */
       CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT);
     }
-    else if(hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)
+    else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)
     {
       /* Configure sample shifting */
       SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT);

Src/stm32h7rsxx_ll_dma.c

@@ -897,7 +897,6 @@ uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct,
     assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
   }
 
-  /* Check non 2D addressing settings */
   {
     assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
     assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));

Src/stm32h7rsxx_ll_i3c.c

@@ -18,8 +18,8 @@
 #if defined(USE_FULL_LL_DRIVER)
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32h7rsxx_ll_i3c.h"
 #include "stm32h7rsxx_ll_bus.h"
+#include "stm32h7rsxx_ll_i3c.h"
 #ifdef  USE_FULL_ASSERT
 #include "stm32_assert.h"
 #else

Src/stm32h7rsxx_ll_sdmmc.c

@@ -163,7 +163,7 @@
   */
 
 #if defined (SDMMC1) || defined (SDMMC2)
-#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)
+#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) || defined (HAL_SDIO_MODULE_ENABLED)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -349,7 +349,7 @@ uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx)
   *         the configuration information for the SDMMC command
   * @retval HAL status
   */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command)
 {
   uint32_t tmpreg = 0;
 
@@ -417,7 +417,7 @@ uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response)
   *         that contains the configuration information for the SDMMC data.
   * @retval HAL status
   */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data)
 {
   uint32_t tmpreg = 0;
 
@@ -1256,6 +1256,78 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
   return errorstate;
 }
 
+/**
+  * @brief  Execute a cmd52 to write single byte data and read single byte data if needed
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument:  SDMMC command argument which is sent to a card as part of a command message
+  * @param  pData: pointer to read response if needed
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_RW_DIRECT;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Execute a cmd53 to write or read multiple data with a single command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: SDMMC command argument which is sent to a card as part of a command message
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_RW_EXTENDED;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Execute a cmd5 to write or read multiple data with a single command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: SDMMC command argument which is sent to a card as part of a command message
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp)
+{
+  SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+  uint32_t             errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_SEN_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp);
+
+  return errorstate;
+}
 /**
   * @}
   */
@@ -1491,6 +1563,138 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
   return SDMMC_ERROR_NONE;
 }
 
+/**
+  * @brief  Checks for error conditions for R4 response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pResp: pointer to response
+  * @retval error state
+  */
+uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp)
+{
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R5 (cmd52/cmd53) response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  SDIO_CMD: The sent command index
+  * @param  pData: pointer to the read/write buffer needed for cmd52
+  * @retval SDIO Card error state
+  */
+uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData)
+{
+  uint32_t response_r5;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */
+    if (pData != NULL)
+    {
+      *pData = (uint8_t)(response_r5 & 0xFFU);
+    }
+
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
 /**
   * @brief  Checks for error conditions for R6 (RCA) response.
   * @param  hsd: SD handle
@@ -1645,7 +1849,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
   * @param  pNodeConf: Pointer to configuration parameters for new node to add.
   * @retval Error status
   */
-uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf)
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf)
 {
 
   if ((pNode == NULL) || (pNodeConf == NULL))

Src/stm32h7rsxx_ll_spi.c

@@ -566,17 +566,20 @@ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
   *          - SUCCESS: SPI registers are Initialized
   *          - ERROR: SPI registers are not Initialized
   */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct)
 {
   uint32_t i2sdiv = 0UL;
   uint32_t i2sodd = 0UL;
   uint32_t packetlength = 1UL;
   uint32_t ispcm = 0UL;
   uint32_t tmp;
-  uint32_t sourceclock;
+  uint32_t sourceclock = 0UL;
 
   ErrorStatus status = ERROR;
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(sourceclock);
+
   /* Check the I2S parameters */
   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));

Src/stm32h7rsxx_ll_usb.c

@@ -315,29 +315,29 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
     USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
     /* B-peripheral session valid override enable */
-    if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
+    if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U)
     {
-      USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-      USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+      USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+      USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
     }
     else
     {
-      USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-      USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+      USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+      USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
     }
   }
   else
   {
     /* B-peripheral session valid override disable */
-    if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
+    if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U)
     {
-      USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN;
-      USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
+      USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN;
+      USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
     }
     else
     {
-      USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN;
-      USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
+      USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN;
+      USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
     }
 
     /* Enable HW VBUS sensing */
@@ -795,17 +795,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
       }
       else
       {
-        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
-                                       (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+        pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
+
+        if (ep->type == EP_TYPE_ISOC)
+        {
+          USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+          USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
+        }
       }
 
       USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
-      if (ep->type == EP_TYPE_ISOC)
-      {
-        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
-        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
-      }
     }
 
     if (dma == 1U)

Src/stm32h7rsxx_ll_utils.c

@@ -69,14 +69,16 @@
 #define UTILS_SCALE0_LATENCY2_FREQ     120000000U   /*!< HCLK frequency to set FLASH latency 2 in power scale 0  */
 #define UTILS_SCALE0_LATENCY3_FREQ     160000000U   /*!< HCLK frequency to set FLASH latency 3 in power scale 0  */
 #define UTILS_SCALE0_LATENCY4_FREQ     200000000U   /*!< HCLK frequency to set FLASH latency 4 in power scale 0  */
-#define UTILS_SCALE0_LATENCY5_FREQ     234000000U   /*!< HCLK frequency to set FLASH latency 5 in power scale 0  */
+#define UTILS_SCALE0_LATENCY5_FREQ     240000000U   /*!< HCLK frequency to set FLASH latency 5 in power scale 0  */
+#define UTILS_SCALE0_LATENCY6_FREQ     280000000U   /*!< HCLK frequency to set FLASH latency 6 in power scale 0  */
+#define UTILS_SCALE0_LATENCY7_FREQ     320000000U   /*!< HCLK frequency to set FLASH latency 7 in power scale 0  */
 
 #define UTILS_SCALE1_LATENCY0_FREQ      36000000U   /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
 #define UTILS_SCALE1_LATENCY1_FREQ      72000000U   /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
 #define UTILS_SCALE1_LATENCY2_FREQ     108000000U   /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
 #define UTILS_SCALE1_LATENCY3_FREQ     144000000U   /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
 #define UTILS_SCALE1_LATENCY4_FREQ     180000000U   /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
-#define UTILS_SCALE1_LATENCY5_FREQ     183000000U   /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+#define UTILS_SCALE1_LATENCY5_FREQ     216000000U   /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
 /**
   * @}
   */
@@ -255,8 +257,8 @@ void LL_mDelay(uint32_t Delay)
     [..]
          System, AXI, AHB and APB buses clocks configuration
 
-         (+) The maximum frequency of the SYSCLK is 464 MHz and HCLK is 232 MHz.
-         (+) The maximum frequency of the PCLK1, PCLK2, PCLK4 and PCLK5 is 116 MHz.
+         (+) The maximum frequency of the SYSCLK is 600 MHz and HCLK is 300 MHz.
+         (+) The maximum frequency of the PCLK1, PCLK2, PCLK4 and PCLK5 is 150 MHz.
   @endverbatim
   @internal
              Depending on the device voltage range, the maximum frequency should be
@@ -264,8 +266,8 @@ void LL_mDelay(uint32_t Delay)
              (++) +---------------------------------------------------------------------------+
              (++) |  Wait states        |  AXI interface clock frequency (MHz) vs Vcore range |
              (++) |                     |-----------------------------------------------------|
-             (++) |  (Latency)          |      voltage scale 1     |      voltage scale 0     |
-             (++) |                     |       1.15V - 1.26V      |       1.26V - 1.40V      |
+             (++) |  (Latency)          | voltage scale 1 (low)    | voltage scale 0 (high)   |
+             (++) |                     |       1.15V - 1.26V      |       1.30V - 1.40V      |
              (++) |---------------------|--------------------------|--------------------------|
              (++) | 0WS (1 CPU cycle)   |     0 < HCLK <= 36       |     0 < HCLK <= 40       |
              (++) |---------------------|--------------------------|--------------------------|
@@ -279,7 +281,9 @@ void LL_mDelay(uint32_t Delay)
              (++) |---------------------|--------------------------|--------------------------|
              (++) | 5WS (6 CPU cycles)  |   180 < HCLK <= 216      |   200 < HCLK <= 240      |
              (++) |---------------------|--------------------------|--------------------------|
-             (++) | 6WS (7 CPU cycles)  |   216 < HCLK <= 252      |                          |
+             (++) | 6WS (7 CPU cycles)  |           NA             |   240 < HCLK <= 280      |
+             (++) |---------------------|--------------------------|--------------------------|
+             (++) | 7WS (8 CPU cycles)  |           NA             |   280 < HCLK <= 320      |
              (++) |---------------------|--------------------------|--------------------------|
 
   @endinternal
@@ -612,7 +616,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
   ErrorStatus status = SUCCESS;
   uint32_t timeout;
   uint32_t getlatency;
-  uint32_t latency;
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
 
   /* Frequency cannot be equal to 0 */
   if (HCLK_Frequency == 0U)
@@ -623,76 +627,95 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
   {
     if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) /* Scale 0 */
     {
-      if ((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
+      if (HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
+      {
+        /* 0 < HCLK <= 40 => 0WS (1 CPU cycle) : Do nothing, keep latency to default  LL_FLASH_LATENCY_0 */
+      }         
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ)
+      {
+        latency = LL_FLASH_LATENCY_1; /* 40 < HCLK <= 80  => 1WS (2 CPU cycles) */
+      }
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ)
       {
-        latency = LL_FLASH_LATENCY_5; /* 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2; /* 80 < HCLK <= 120  => 2WS (3 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)
       {
-        latency = LL_FLASH_LATENCY_4; /* 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3; /* 120 < HCLK <= 160  => 3WS (4 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ)
       {
-        latency = LL_FLASH_LATENCY_3; /* 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4; /* 160 < HCLK <= 200  => 4WS (5 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ)
       {
-        latency = LL_FLASH_LATENCY_2; /* 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5; /* 200 < HCLK <= 240  => 5WS (6 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ)
       {
-        latency = LL_FLASH_LATENCY_1; /* 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_6; /* 240 < HCLK <= 280  => 6WS (7 CPU cycles) */
       }
+      else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY7_FREQ)
+      {
+        latency = LL_FLASH_LATENCY_7; /* 280 < HCLK <= 320  => 6WS (7 CPU cycles) */
+      }      
       else
       {
-        latency = LL_FLASH_LATENCY_0; /* 0WS (1 CPU cycles) */
+        status = ERROR;
       }
     }
     else /* Scale 1 */
     {
-      if ((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
+      if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
       {
-        latency = LL_FLASH_LATENCY_5; /* 5WS (6 CPU cycles) */
+         /* 0 < HCLK <= 36 => 0WS (1 CPU cycles) : Do nothing, keep latency to default  LL_FLASH_LATENCY_0 */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)
       {
-        latency = LL_FLASH_LATENCY_4; /* 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1; /* 36 < HCLK <= 72 => 1WS (2 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)
       {
-        latency = LL_FLASH_LATENCY_3; /* 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2; /* 72 < HCLK <= 108 => 2WS (3 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)
       {
-        latency = LL_FLASH_LATENCY_2; /* 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3; /* 108 < HCLK <= 144 => 3WS (2 CPU cycles) */
       }
-      else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
+      else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)
       {
-        latency = LL_FLASH_LATENCY_1; /* 1WS (2 CPU cycles) */
-      }
+        latency = LL_FLASH_LATENCY_4; /* 144 < HCLK <= 180 => 4WS (5 CPU cycles) */
+      }               
+      else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ)
+      {
+        latency = LL_FLASH_LATENCY_5; /* 180 < HCLK <= 216 => 5WS (6 CPU cycles) */
+      }    
       else
       {
-        latency = LL_FLASH_LATENCY_0; /* 0WS (1 CPU cycles) */
+        status = ERROR;
       }
     }
+  }  
 
-    LL_FLASH_SetLatency(latency);
+    if (status == SUCCESS)
+    {    
+      LL_FLASH_SetLatency(latency);
 
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    timeout = 2;
-    do
-    {
-      /* Wait for Flash latency to be updated */
-      getlatency = LL_FLASH_GetLatency();
-      timeout--;
-    } while ((getlatency != latency) && (timeout > 0U));
+      /* Check that the new number of wait states is taken into account to access the Flash
+      memory by reading the FLASH_ACR register */
+      timeout = 2;
+      do
+      {
+        /* Wait for Flash latency to be updated */
+        getlatency = LL_FLASH_GetLatency();
+        timeout--;
+      } while ((getlatency != latency) && (timeout > 0U));
 
-    if (getlatency != latency)
-    {
-      status = ERROR;
+      if (getlatency != latency)
+      {
+        status = ERROR;
+      }
     }
-  }
 
   return status;
 }