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+/*
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+ * The MIT License (MIT)
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+ *
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+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * in the Software without restriction, including without limitation the rights
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+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+ * copies of the Software, and to permit persons to whom the Software is
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+ * furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * THE SOFTWARE.
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+ *
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+ * This file is part of the TinyUSB stack.
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+ */
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+
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+#include "tusb_option.h"
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+
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+#if TUSB_OPT_DEVICE_ENABLED && \
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+ (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
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+
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+//--------------------------------------------------------------------+
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+// INCLUDE
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+//--------------------------------------------------------------------+
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+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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+ #include "fsl_device_registers.h"
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+ #define INCLUDE_FSL_DEVICE_REGISTERS
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+#else
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+ // LPCOpen for 18xx & 43xx
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+ #include "chip.h"
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+#endif
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+
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+#include "common/tusb_common.h"
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+#include "device/dcd.h"
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+#include "ci_hs_type.h"
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+
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+#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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+ #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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+#else
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+ #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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+#endif
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+
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+//--------------------------------------------------------------------+
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+// MACRO CONSTANT TYPEDEF
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+//--------------------------------------------------------------------+
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+
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+// ENDPTCTRL
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+enum {
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+ ENDPTCTRL_STALL = TU_BIT(0),
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+ ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only
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+ ENDPTCTRL_TOGGLE_RESET = TU_BIT(6),
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+ ENDPTCTRL_ENABLE = TU_BIT(7)
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+};
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+
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+enum {
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+ ENDPTCTRL_TYPE_POS = 2, // Endpoint type is 2-bit field
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+};
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+
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+// USBSTS, USBINTR
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+enum {
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+ INTR_USB = TU_BIT(0),
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+ INTR_ERROR = TU_BIT(1),
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+ INTR_PORT_CHANGE = TU_BIT(2),
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+ INTR_RESET = TU_BIT(6),
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+ INTR_SOF = TU_BIT(7),
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+ INTR_SUSPEND = TU_BIT(8),
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+ INTR_NAK = TU_BIT(16)
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+};
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+
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+// Queue Transfer Descriptor
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+typedef struct
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+{
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+ // Word 0: Next QTD Pointer
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+ uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
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+
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+ // Word 1: qTQ Token
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+ uint32_t : 3 ;
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+ volatile uint32_t xact_err : 1 ;
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+ uint32_t : 1 ;
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+ volatile uint32_t buffer_err : 1 ;
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+ volatile uint32_t halted : 1 ;
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+ volatile uint32_t active : 1 ;
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+ uint32_t : 2 ;
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+ uint32_t iso_mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
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+ uint32_t : 3 ;
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+ uint32_t int_on_complete : 1 ;
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+ volatile uint32_t total_bytes : 15 ;
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+ uint32_t : 1 ;
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+
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+ // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
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+ uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
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+
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+ //--------------------------------------------------------------------+
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+ // TD is 32 bytes aligned but occupies only 28 bytes
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+ // Therefore there are 4 bytes padding that we can use.
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+ //--------------------------------------------------------------------+
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+ uint16_t expected_bytes;
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+ uint8_t reserved[2];
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+} dcd_qtd_t;
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+
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+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
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+
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+// Queue Head
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+typedef struct
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+{
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+ // Word 0: Capabilities and Characteristics
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+ uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
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+ uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
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+ uint32_t max_packet_size : 11 ; ///< Endpoint's wMaxPacketSize
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+ uint32_t : 2 ;
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+ uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
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+ uint32_t iso_mult : 2 ; ///<
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+
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+ // Word 1: Current qTD Pointer
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+ volatile uint32_t qtd_addr;
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+
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+ // Word 2-9: Transfer Overlay
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+ volatile dcd_qtd_t qtd_overlay;
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+
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+ // Word 10-11: Setup request (control OUT only)
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+ volatile tusb_control_request_t setup_request;
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+
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+ //--------------------------------------------------------------------+
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+ // QHD is 64 bytes aligned but occupies only 48 bytes
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+ // Therefore there are 16 bytes padding that we can use.
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+ //--------------------------------------------------------------------+
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+ tu_fifo_t * ff;
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+ uint8_t reserved[12];
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+} dcd_qhd_t;
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+
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+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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+
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+//--------------------------------------------------------------------+
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+// Variables
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+//--------------------------------------------------------------------+
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+
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+typedef struct
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+{
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+ dcd_registers_t* regs; // registers
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+ const IRQn_Type irqnum; // IRQ number
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+ const uint8_t ep_count; // Max bi-directional Endpoints
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+}dcd_controller_t;
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+
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+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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+ static const dcd_controller_t _dcd_controller[] =
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+ {
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+ // RT1010 and RT1020 only has 1 USB controller
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+ #if FSL_FEATURE_SOC_USBHS_COUNT == 1
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+ { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
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+ #else
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+ { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
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+ { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
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+ #endif
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+ };
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+
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+#else
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+ static const dcd_controller_t _dcd_controller[] =
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+ {
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+ { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
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+ { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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+ };
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+#endif
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+
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+#define QTD_NEXT_INVALID 0x01
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+
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+typedef struct {
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+ // Must be at 2K alignment
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+ // Each endpoint with direction (IN/OUT) occupies a queue head
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+ // for portability, TinyUSB only queue 1 TD for each Qhd
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+ dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
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+ dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
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+}dcd_data_t;
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+
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+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
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+static dcd_data_t _dcd_data;
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+
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+//--------------------------------------------------------------------+
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+// Controller API
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+//--------------------------------------------------------------------+
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+
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+/// follows LPC43xx User Manual 23.10.3
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+static void bus_reset(uint8_t rhport)
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+{
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+
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+ // The reset value for all endpoint types is the control endpoint. If one endpoint
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+ // direction is enabled and the paired endpoint of opposite direction is disabled, then the
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+ // endpoint type of the unused direction must be changed from the control type to any other
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+ // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
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+ // for the data PID tracking on the active endpoint.
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+ for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
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+ {
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+ dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
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+ }
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+
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+ //------------- Clear All Registers -------------//
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+ dcd_reg->ENDPTNAK = dcd_reg->ENDPTNAK;
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+ dcd_reg->ENDPTNAKEN = 0;
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+ dcd_reg->USBSTS = dcd_reg->USBSTS;
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+ dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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+ dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE;
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+
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+ while (dcd_reg->ENDPTPRIME) {}
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+ dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
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+ while (dcd_reg->ENDPTFLUSH) {}
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+
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+ // read reset bit in portsc
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+
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+ //------------- Queue Head & Queue TD -------------//
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+ tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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+
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+ //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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+ _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
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+ _dcd_data.qhd[0][0].max_packet_size = _dcd_data.qhd[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
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+ _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
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+
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+ _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
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+}
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+
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+void dcd_init(uint8_t rhport)
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+{
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+ tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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+
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+
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+ // Reset controller
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+ dcd_reg->USBCMD |= USBCMD_RESET;
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+ while( dcd_reg->USBCMD & USBCMD_RESET ) {}
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+
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+ // Set mode to device, must be set immediately after reset
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+ dcd_reg->USBMODE = USBMODE_CM_DEVICE;
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+ dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
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+
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+#if !TUD_OPT_HIGH_SPEED
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+ dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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+#endif
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+
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+ CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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+
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+ dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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+ dcd_reg->USBSTS = dcd_reg->USBSTS;
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+ dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
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+
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+ dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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+ dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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+}
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+
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+void dcd_int_enable(uint8_t rhport)
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+{
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+ NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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+}
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+
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+void dcd_int_disable(uint8_t rhport)
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+{
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+ NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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+}
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+
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+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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+{
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+ // Response with status first before changing device address
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+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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+
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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+}
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+
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+void dcd_remote_wakeup(uint8_t rhport)
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+{
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
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+}
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+
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+void dcd_connect(uint8_t rhport)
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+{
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->USBCMD |= USBCMD_RUN_STOP;
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+}
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+
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+void dcd_disconnect(uint8_t rhport)
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+{
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
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+}
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+
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+//--------------------------------------------------------------------+
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+// HELPER
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+//--------------------------------------------------------------------+
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+
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+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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+{
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+ // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
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+ // address to 32-byte boundaries. Buffer must be word aligned
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+ CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
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+
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+ tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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+
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+ p_qtd->next = QTD_NEXT_INVALID;
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+ p_qtd->active = 1;
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+ p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
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+ p_qtd->int_on_complete = true;
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+
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+ if (data_ptr != NULL)
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+ {
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+ p_qtd->buffer[0] = (uint32_t) data_ptr;
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+
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+ uint32_t const bufend = p_qtd->buffer[0] + total_bytes;
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+ for(uint8_t i=1; i<5; i++)
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+ {
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+ uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096;
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+ if ( bufend <= next_page ) break;
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+
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+ p_qtd->buffer[i] = next_page;
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+
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+ // TODO page[1] FRAME_N for ISO transfer
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+ }
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+ }
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+}
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+
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+//--------------------------------------------------------------------+
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+// DCD Endpoint Port
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+//--------------------------------------------------------------------+
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+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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+
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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+
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+ // flush to abort any primed buffer
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+ dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
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+}
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+
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+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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+
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+ // data toggle also need to be reset
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+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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+ dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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+ dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
|
|
|
+}
|
|
|
+
|
|
|
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
|
|
|
+{
|
|
|
+ uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
|
|
|
+ uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
|
|
|
+
|
|
|
+ // Must not exceed max endpoint number
|
|
|
+ TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
|
|
|
+
|
|
|
+ //------------- Prepare Queue Head -------------//
|
|
|
+ dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
|
|
|
+ tu_memclr(p_qhd, sizeof(dcd_qhd_t));
|
|
|
+
|
|
|
+ p_qhd->zero_length_termination = 1;
|
|
|
+ p_qhd->max_packet_size = tu_edpt_packet_size(p_endpoint_desc);
|
|
|
+ if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
|
|
|
+ {
|
|
|
+ p_qhd->iso_mult = 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
|
|
|
+
|
|
|
+ CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
|
|
+
|
|
|
+ // Enable EP Control
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+
|
|
|
+ uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
|
|
|
+
|
|
|
+ if ( dir == TUSB_DIR_OUT )
|
|
|
+ {
|
|
|
+ dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl;
|
|
|
+ }else
|
|
|
+ {
|
|
|
+ dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16);
|
|
|
+ }
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+void dcd_edpt_close_all (uint8_t rhport)
|
|
|
+{
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+
|
|
|
+ // Disable all non-control endpoints
|
|
|
+ for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
|
|
|
+ {
|
|
|
+ _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
|
|
|
+ _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
|
|
|
+
|
|
|
+ dcd_reg->ENDPTFLUSH = TU_BIT(epnum) | TU_BIT(epnum+16);
|
|
|
+ dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
|
|
+{
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
+
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+
|
|
|
+ _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
|
|
|
+
|
|
|
+ // Flush EP
|
|
|
+ uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0));
|
|
|
+ dcd_reg->ENDPTFLUSH = flush_mask;
|
|
|
+ while(dcd_reg->ENDPTFLUSH & flush_mask);
|
|
|
+
|
|
|
+ // Clear EP enable
|
|
|
+ dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
|
|
|
+}
|
|
|
+
|
|
|
+static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
|
|
|
+{
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+ dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
|
|
|
+ dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
|
|
|
+
|
|
|
+ p_qhd->qtd_overlay.halted = false; // clear any previous error
|
|
|
+ p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
|
|
|
+
|
|
|
+ // flush cache
|
|
|
+ CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
|
|
+
|
|
|
+ if ( epnum == 0 )
|
|
|
+ {
|
|
|
+ // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
|
|
|
+ // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
|
|
|
+ while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
|
|
|
+ }
|
|
|
+
|
|
|
+ // start transfer
|
|
|
+ dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
|
|
|
+}
|
|
|
+
|
|
|
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
|
|
+{
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
+
|
|
|
+ dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
|
|
|
+ dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
|
|
|
+
|
|
|
+ // Prepare qtd
|
|
|
+ qtd_init(p_qtd, buffer, total_bytes);
|
|
|
+
|
|
|
+ // Start qhd transfer
|
|
|
+ p_qhd->ff = NULL;
|
|
|
+ qhd_start_xfer(rhport, epnum, dir);
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+// fifo has to be aligned to 4k boundary
|
|
|
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
|
|
|
+{
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
+
|
|
|
+ dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
|
|
|
+ dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
|
|
|
+
|
|
|
+ tu_fifo_buffer_info_t fifo_info;
|
|
|
+
|
|
|
+ if (dir)
|
|
|
+ {
|
|
|
+ tu_fifo_get_read_info(ff, &fifo_info);
|
|
|
+ } else
|
|
|
+ {
|
|
|
+ tu_fifo_get_write_info(ff, &fifo_info);
|
|
|
+ }
|
|
|
+
|
|
|
+ if ( fifo_info.len_lin >= total_bytes )
|
|
|
+ {
|
|
|
+ // Linear length is enough for this transfer
|
|
|
+ qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // linear part is not enough
|
|
|
+
|
|
|
+ // prepare TD up to linear length
|
|
|
+ qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin);
|
|
|
+
|
|
|
+ if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) )
|
|
|
+ {
|
|
|
+ // If buffer is aligned to 4K & buffer size is multiple of 4K
|
|
|
+ // We can make use of buffer page array to also combine the linear + wrapped length
|
|
|
+ p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
|
|
|
+
|
|
|
+ for(uint8_t i = 1, page = 0; i < 5; i++)
|
|
|
+ {
|
|
|
+ // pick up buffer array where linear ends
|
|
|
+ if (p_qtd->buffer[i] == 0)
|
|
|
+ {
|
|
|
+ p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page;
|
|
|
+ page++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // TODO we may need to carry the wrapped length after the linear part complete
|
|
|
+ // for now only transfer up to linear part
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // Start qhd transfer
|
|
|
+ p_qhd->ff = ff;
|
|
|
+ qhd_start_xfer(rhport, epnum, dir);
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+//--------------------------------------------------------------------+
|
|
|
+// ISR
|
|
|
+//--------------------------------------------------------------------+
|
|
|
+
|
|
|
+static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir)
|
|
|
+{
|
|
|
+ dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
|
|
|
+ dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
|
|
|
+
|
|
|
+ uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
|
|
|
+ ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
|
|
|
+
|
|
|
+ if ( result != XFER_RESULT_SUCCESS )
|
|
|
+ {
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+ // flush to abort error buffer
|
|
|
+ dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
|
|
|
+ }
|
|
|
+
|
|
|
+ uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
|
|
|
+
|
|
|
+ if (p_qhd->ff)
|
|
|
+ {
|
|
|
+ if (dir == TUSB_DIR_IN)
|
|
|
+ {
|
|
|
+ tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
|
|
|
+ } else
|
|
|
+ {
|
|
|
+ tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // only number of bytes in the IOC qtd
|
|
|
+ dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
|
|
|
+}
|
|
|
+
|
|
|
+void dcd_int_handler(uint8_t rhport)
|
|
|
+{
|
|
|
+ dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
|
|
+
|
|
|
+ uint32_t const int_enable = dcd_reg->USBINTR;
|
|
|
+ uint32_t const int_status = dcd_reg->USBSTS & int_enable;
|
|
|
+ dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
|
|
|
+
|
|
|
+ // disabled interrupt sources
|
|
|
+ if (int_status == 0) return;
|
|
|
+
|
|
|
+ // Set if the port controller enters the full or high-speed operational state.
|
|
|
+ // either from Bus Reset or Suspended state
|
|
|
+ if (int_status & INTR_PORT_CHANGE)
|
|
|
+ {
|
|
|
+ // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
|
|
|
+
|
|
|
+ // Reset interrupt is not enabled, we manually check if Port Change is due
|
|
|
+ // to connection / disconnection
|
|
|
+ if ( dcd_reg->USBSTS & INTR_RESET )
|
|
|
+ {
|
|
|
+ dcd_reg->USBSTS = INTR_RESET;
|
|
|
+
|
|
|
+ if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
|
|
|
+ {
|
|
|
+ uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
|
|
|
+ bus_reset(rhport);
|
|
|
+ dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
|
|
|
+ }else
|
|
|
+ {
|
|
|
+ dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // Triggered by resuming from suspended state
|
|
|
+ if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
|
|
|
+ {
|
|
|
+ dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (int_status & INTR_SUSPEND)
|
|
|
+ {
|
|
|
+ // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
|
|
|
+
|
|
|
+ if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
|
|
|
+ {
|
|
|
+ // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
|
|
+ // Skip suspend event if we are not addressed
|
|
|
+ if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
|
|
|
+ {
|
|
|
+ dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (int_status & INTR_USB)
|
|
|
+ {
|
|
|
+ // Make sure we read the latest version of _dcd_data.
|
|
|
+ CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
|
|
+
|
|
|
+ uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
|
|
|
+ dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
|
|
|
+
|
|
|
+ if (dcd_reg->ENDPTSETUPSTAT)
|
|
|
+ {
|
|
|
+ //------------- Set up Received -------------//
|
|
|
+ // 23.10.10.2 Operational model for setup transfers
|
|
|
+ dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
|
|
|
+
|
|
|
+ dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
|
|
|
+ }
|
|
|
+
|
|
|
+ // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
|
|
|
+ // nothing to do, we will submit xfer as error to usbd
|
|
|
+ // if (int_status & INTR_ERROR) { }
|
|
|
+
|
|
|
+ if ( edpt_complete )
|
|
|
+ {
|
|
|
+ for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++)
|
|
|
+ {
|
|
|
+ if ( tu_bit_test(edpt_complete, epnum) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
|
|
|
+ if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (int_status & INTR_SOF)
|
|
|
+ {
|
|
|
+ dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|
hathach