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+/*
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+ * Licensed to the Apache Software Foundation (ASF) under one
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+ * or more contributor license agreements. See the NOTICE file
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+ * distributed with this work for additional information
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+ * regarding copyright ownership. The ASF licenses this file
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+ * to you under the Apache License, Version 2.0 (the
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+ * "License"); you may not use this file except in compliance
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+ * with the License. You may obtain a copy of the License at
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+ *
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+ * http://www.apache.org/licenses/LICENSE-2.0
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+ *
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+ * Unless required by applicable law or agreed to in writing,
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+ * software distributed under the License is distributed on an
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+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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+ * KIND, either express or implied. See the License for the
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+ * specific language governing permissions and limitations
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+ * under the License.
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+ */
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+
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+ #include "syscfg/syscfg.h"
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+
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+ .syntax unified
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+ .arch armv7-m
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+
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+ .section .stack
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+ .align 3
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+#ifdef __STACK_SIZE
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+ .equ Stack_Size, __STACK_SIZE
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+#else
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+ .equ Stack_Size, 0xC00
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+#endif
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+ .equ SYS_CTRL_REG, 0x50000024
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+ .equ CACHE_FLASH_REG, 0x100C0040
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+ .equ RESET_STAT_REG, 0x500000BC
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+
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+ .globl __StackTop
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+ .globl __StackLimit
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+__StackLimit:
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+ .space Stack_Size
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+ .size __StackLimit, . - __StackLimit
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+__StackTop:
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+ .size __StackTop, . - __StackTop
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+
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+ .section .heap
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+ .align 3
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+#ifdef __HEAP_SIZE
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+ .equ Heap_Size, __HEAP_SIZE
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+#else
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+ .equ Heap_Size, 0
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+#endif
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+ .globl __HeapBase
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+ .globl __HeapLimit
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+__HeapBase:
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+ .if Heap_Size
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+ .space Heap_Size
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+ .endif
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+ .size __HeapBase, . - __HeapBase
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+__HeapLimit:
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+ .size __HeapLimit, . - __HeapLimit
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+
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+ .section .isr_vector
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+ .align 2
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+ .globl __isr_vector
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+__isr_vector:
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+ .long __StackTop
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+ .long Reset_Handler
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+ /* Cortex-M33 interrupts */
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+ .long NMI_Handler
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+ .long HardFault_Handler
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+ .long MemoryManagement_Handler
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+ .long BusFault_Handler
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+ .long UsageFault_Handler
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+ .long SecureFault_Handler
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long SVC_Handler
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+ .long DebugMonitor_Handler
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+ .long 0 /* Reserved */
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+ .long PendSV_Handler
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+ .long SysTick_Handler
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+ /* DA1469x interrupts */
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+ .long SENSOR_NODE_IRQHandler
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+ .long DMA_IRQHandler
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+ .long CHARGER_STATE_IRQHandler
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+ .long CHARGER_ERROR_IRQHandler
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+ .long CMAC2SYS_IRQHandler
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+ .long UART_IRQHandler
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+ .long UART2_IRQHandler
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+ .long UART3_IRQHandler
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+ .long I2C_IRQHandler
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+ .long I2C2_IRQHandler
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+ .long SPI_IRQHandler
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+ .long SPI2_IRQHandler
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+ .long PCM_IRQHandler
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+ .long SRC_IN_IRQHandler
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+ .long SRC_OUT_IRQHandler
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+ .long USB_IRQHandler
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+ .long TIMER_IRQHandler
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+ .long TIMER2_IRQHandler
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+ .long RTC_IRQHandler
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+ .long KEY_WKUP_GPIO_IRQHandler
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+ .long PDC_IRQHandler
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+ .long VBUS_IRQHandler
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+ .long MRM_IRQHandler
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+ .long MOTOR_CONTROLLER_IRQHandler
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+ .long TRNG_IRQHandler
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+ .long DCDC_IRQHandler
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+ .long XTAL32M_RDY_IRQHandler
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+ .long ADC_IRQHandler
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+ .long ADC2_IRQHandler
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+ .long CRYPTO_IRQHandler
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+ .long CAPTIMER1_IRQHandler
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+ .long RFDIAG_IRQHandler
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+ .long LCD_CONTROLLER_IRQHandler
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+ .long PLL_LOCK_IRQHandler
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+ .long TIMER3_IRQHandler
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+ .long TIMER4_IRQHandler
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+ .long LRA_IRQHandler
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+ .long RTC_EVENT_IRQHandler
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+ .long GPIO_P0_IRQHandler
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+ .long GPIO_P1_IRQHandler
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .long 0 /* Reserved */
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+ .size __isr_vector, . - __isr_vector
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+
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+ .text
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+ .thumb
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+ .thumb_func
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+ .align 2
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+ .globl Reset_Handler
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+ .type Reset_Handler, %function
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+Reset_Handler:
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+ /* Make sure interrupt vector is remapped at 0x0 */
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+ ldr r1, =SYS_CTRL_REG
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+ ldrh r2, [r1, #0]
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+ orrs r2, r2, #8
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+ strh r2, [r1, #0]
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+
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+#if !MYNEWT_VAL(RAM_RESIDENT)
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+/*
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+ * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
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+ * 0x16000000 but to start of an image on flash. This is calculated from product
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+ * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
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+ * retrieve proper offset value for calculations later.
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+ */
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+ ldr r1, =CACHE_FLASH_REG
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+ ldr r4, [r1, #0]
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+ mov r2, r4
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+ mov r3, #0xFFFF
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+ bic r4, r4, r3 /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
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+ mov r3, #0xFFF0
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+ and r2, r2, r3 /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
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+ lsr r2, r2, #2
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+ orr r4, r4, r2
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+
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+/* Copy ISR vector from flash to RAM */
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+ ldr r1, =__isr_vector_start /* src ptr */
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+ ldr r2, =__isr_vector_end /* src end */
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+ ldr r3, =__intvect_start__ /* dst ptr */
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+/* Make sure we copy from QSPIC address range, not from remapped range */
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+ cmp r1, r4
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+ itt lt
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+ addlt r1, r1, r4
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+ addlt r2, r2, r4
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+.loop_isr_copy:
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+ cmp r1, r2
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+ ittt lt
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+ ldrlt r0, [r1], #4
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+ strlt r0, [r3], #4
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+ blt .loop_isr_copy
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+
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+/* Copy QSPI code from flash to RAM */
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+ ldr r1, =__text_ram_addr /* src ptr */
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+ ldr r2, =__text_ram_start__ /* ptr */
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+ ldr r3, =__text_ram_end__ /* dst end */
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+.loop_code_text_ram_copy:
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+ cmp r2, r3
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+ ittt lt
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+ ldrlt r0, [r1], #4
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+ strlt r0, [r2], #4
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+ blt .loop_code_text_ram_copy
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+
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+/* Copy data from flash to RAM */
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+ ldr r1, =__etext /* src ptr */
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+ ldr r2, =__data_start__ /* dst ptr */
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+ ldr r3, =__data_end__ /* dst end */
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+.loop_data_copy:
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+ cmp r2, r3
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+ ittt lt
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+ ldrlt r0, [r1], #4
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+ strlt r0, [r2], #4
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+ blt .loop_data_copy
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+#endif
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+
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+/* Clear BSS */
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+ movs r0, 0
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+ ldr r1, =__bss_start__
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+ ldr r2, =__bss_end__
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+.loop_bss_clear:
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+ cmp r1, r2
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+ itt lt
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+ strlt r0, [r1], #4
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+ blt .loop_bss_clear
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+
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+ ldr r0, =__HeapBase
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+ ldr r1, =__HeapLimit
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+/* Call static constructors */
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+ bl __libc_init_array
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+
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+ bl SystemInit
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+ bl main
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+
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+ .pool
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+ .size Reset_Handler, . - Reset_Handler
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+
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+/* Default interrupt handler */
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+ .type Default_Handler, %function
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+Default_Handler:
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+ ldr r1, =SYS_CTRL_REG
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+ ldrh r2, [r1, #0]
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+ orrs r2, r2, #0x80 /* DEBUGGER_ENABLE */
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+ strh r2, [r1, #0]
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+ b .
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+
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+ .size Default_Handler, . - Default_Handler
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+
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+/* Default handlers for all interrupts */
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+ .macro IRQ handler
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+ .weak \handler
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+ .set \handler, Default_Handler
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+ .endm
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+
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+ /* Cortex-M33 interrupts */
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+ IRQ NMI_Handler
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+ IRQ HardFault_Handler
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+ IRQ MemoryManagement_Handler
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+ IRQ BusFault_Handler
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+ IRQ UsageFault_Handler
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+ IRQ SecureFault_Handler
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+ IRQ SVC_Handler
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+ IRQ DebugMonitor_Handler
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+ IRQ PendSV_Handler
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+ IRQ SysTick_Handler
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+ /* DA1469x interrupts */
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+ IRQ SENSOR_NODE_IRQHandler
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+ IRQ DMA_IRQHandler
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+ IRQ CHARGER_STATE_IRQHandler
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+ IRQ CHARGER_ERROR_IRQHandler
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+ IRQ CMAC2SYS_IRQHandler
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+ IRQ UART_IRQHandler
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+ IRQ UART2_IRQHandler
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+ IRQ UART3_IRQHandler
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+ IRQ I2C_IRQHandler
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+ IRQ I2C2_IRQHandler
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+ IRQ SPI_IRQHandler
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+ IRQ SPI2_IRQHandler
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+ IRQ PCM_IRQHandler
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+ IRQ SRC_IN_IRQHandler
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+ IRQ SRC_OUT_IRQHandler
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+ IRQ USB_IRQHandler
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+ IRQ TIMER_IRQHandler
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+ IRQ TIMER2_IRQHandler
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+ IRQ RTC_IRQHandler
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+ IRQ KEY_WKUP_GPIO_IRQHandler
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+ IRQ PDC_IRQHandler
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+ IRQ VBUS_IRQHandler
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+ IRQ MRM_IRQHandler
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+ IRQ MOTOR_CONTROLLER_IRQHandler
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+ IRQ TRNG_IRQHandler
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+ IRQ DCDC_IRQHandler
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+ IRQ XTAL32M_RDY_IRQHandler
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+ IRQ ADC_IRQHandler
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+ IRQ ADC2_IRQHandler
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+ IRQ CRYPTO_IRQHandler
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+ IRQ CAPTIMER1_IRQHandler
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+ IRQ RFDIAG_IRQHandler
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+ IRQ LCD_CONTROLLER_IRQHandler
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+ IRQ PLL_LOCK_IRQHandler
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+ IRQ TIMER3_IRQHandler
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+ IRQ TIMER4_IRQHandler
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+ IRQ LRA_IRQHandler
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+ IRQ RTC_EVENT_IRQHandler
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+ IRQ GPIO_P0_IRQHandler
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+ IRQ GPIO_P1_IRQHandler
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+ IRQ RESERVED40_IRQHandler
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+ IRQ RESERVED41_IRQHandler
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+ IRQ RESERVED42_IRQHandler
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+ IRQ RESERVED43_IRQHandler
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+ IRQ RESERVED44_IRQHandler
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+ IRQ RESERVED45_IRQHandler
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+ IRQ RESERVED46_IRQHandler
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+ IRQ RESERVED47_IRQHandler
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+
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+.end
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