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@@ -147,12 +147,13 @@ typedef struct {
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typedef volatile uint32_t * usb_fifo_t;
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#if TUD_OPT_RHPORT == 1
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-# define EP_MAX EP_MAX_HS
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-# define EP_FIFO_SIZE EP_FIFO_SIZE_HS
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+ #define EP_MAX EP_MAX_HS
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+ #define EP_FIFO_SIZE EP_FIFO_SIZE_HS
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#else
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-# define EP_MAX EP_MAX_FS
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-# define EP_FIFO_SIZE EP_FIFO_SIZE_FS
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+ #define EP_MAX EP_MAX_FS
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+ #define EP_FIFO_SIZE EP_FIFO_SIZE_FS
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#endif
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+
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xfer_ctl_t xfer_status[EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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@@ -325,63 +326,44 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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}
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-# if defined(USB_HS_PHYC) && TUD_OPT_HIGH_SPEED
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+#if defined(USB_HS_PHYC) && TUD_OPT_HIGH_SPEED
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static bool USB_HS_PHYCInit(void)
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{
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- USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef *)USB_HS_PHYC_CONTROLLER_BASE;
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- // Enable LDO
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- usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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- int32_t count = 2000000;
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- while(1) {
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- if (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS)
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- break;
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- TU_ASSERT(count > 0);
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- }
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- uint32_t phyc_pll = 0;
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- switch (HSE_VALUE) {
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- case 12000000:
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ;
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- break;
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- case 12500000:
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ;
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- break;
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- case 16000000:
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ;
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- break;
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- case 24000000:
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ;
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- break;
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- case 25000000:
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ;
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- break;
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- case 32000000:
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- // Value not defined in header
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- phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk;
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- break;
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+ USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
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+
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+ // Enable LDO
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+ usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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+
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+ // Wait until LDO ready
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+ while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
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+
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+ uint32_t phyc_pll = 0;
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+ switch ( HSE_VALUE )
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+ {
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+ case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break;
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+ case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
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+ case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break;
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+ case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break;
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+ case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break;
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+ case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header
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default:
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- TU_ASSERT(0);
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- }
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- usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
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-
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- // Use magic value as in stm32f7xx_ll_usb.
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-# if !defined (USB_HS_PHYC_TUNE_VALUE)
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-# define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
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-# endif /* USB_HS_PHYC_TUNE_VALUE */
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- // Control the tuning interface of the High Speed PHY */
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- usb_hs_phyc->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
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-
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- // Enable PLL internal PHY
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- usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll | USB_HS_PHYC_PLL_PLLEN;
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-
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- /* Original ST code has 2 ms delay for PLL stabilization.
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- * Primitive test shows that more than 10 USB un/replug cycle
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- * showed no error with enumeration
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- * //#include "../../../../hw/bsp//board.h"
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- * //board_delay(2);
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- */
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- return true;
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+ TU_ASSERT(0);
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+ }
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+ usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
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+
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+ // Control the tuning interface of the High Speed PHY
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+ // Use magic value from ST driver
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+ usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
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+
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+ // Enable PLL internal PHY
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+ usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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+
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+ // Original ST code has 2 ms delay for PLL stabilization.
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+ // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
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+
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+ return true;
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}
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-# endif
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+#endif
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/*------------------------------------------------------------------*/
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/* Controller API
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@@ -417,9 +399,6 @@ void dcd_init (uint8_t rhport)
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// Enables control of a High Speed USB PHY
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USB_HS_PHYCInit();
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-
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- // Disable external VBUS detection
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- usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPIEVBUSD;
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#endif
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} else
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#endif
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