fix ci

hw/bsp/same70_xplained/board.mk

@@ -41,8 +41,9 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samg
+#SRC_C += src/portable/template/dcd_template.c
+VENDOR = .
+CHIP_FAMILY = template
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7

src/portable/template/dcd_template.c

@@ -45,20 +45,6 @@ void dcd_init (uint8_t rhport)
   (void) rhport;
 }
 
-#if HAS_INTERNAL_PULLUP
-// Enable internal D+/D- pullup
-void dcd_connect(uint8_t rhport) TU_ATTR_WEAK
-{
-  (void) rhport;
-}
-
-// Disable internal D+/D- pullup
-void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK
-{
-  (void) rhport;
-}
-#endif
-
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport)
 {

tools/build_all.py

@@ -76,6 +76,10 @@ def skip_example(example, board):
         if 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents:
             return 1
 
+        # Skip all OPT_MCU_NONE these are WIP port
+        if '-DCFG_TUSB_MCU=OPT_MCU_NONE' in mk_contents:
+            return 1
+
         # Skip if CFG_TUSB_MCU in board.mk to match skip file
         for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'):
             mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2]