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@@ -1,653 +0,0 @@
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-/*
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- * The MIT License (MIT)
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- *
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- * Copyright (c) 2019 William D. Jones for Adafruit Industries
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- *
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- * Permission is hereby granted, free of charge, to any person obtaining a copy
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- * of this software and associated documentation files (the "Software"), to deal
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- * in the Software without restriction, including without limitation the rights
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- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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- * copies of the Software, and to permit persons to whom the Software is
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- * furnished to do so, subject to the following conditions:
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- *
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- * The above copyright notice and this permission notice shall be included in
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- * all copies or substantial portions of the Software.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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- * THE SOFTWARE.
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- *
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- * This file is part of the TinyUSB stack.
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- */
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-
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-#include "tusb_option.h"
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-
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-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_STM32H7
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-
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-#include "device/dcd.h"
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-#include "stm32h7xx.h"
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-
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-/*------------------------------------------------------------------*/
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-/* MACRO TYPEDEF CONSTANT ENUM
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- *------------------------------------------------------------------*/
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-#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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-#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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-#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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-#define FIFO_BASE(_x) (volatile uint32_t *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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-
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-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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-static uint8_t _setup_offs; // We store up to 3 setup packets.
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-
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-typedef struct {
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- uint8_t * buffer;
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- uint16_t total_len;
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- uint16_t queued_len;
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- uint16_t max_size;
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- bool short_packet;
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-} xfer_ctl_t;
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-
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-typedef volatile uint32_t * usb_fifo_t;
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-
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-xfer_ctl_t xfer_status[4][2];
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-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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-
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-
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-// Setup the control endpoint 0.
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-static void bus_reset(void)
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-{
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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-
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- for(int n = 0; n < 4; n++)
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- {
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- out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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- }
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-
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- dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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- dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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- dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
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-
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- // Peripheral FIFO architecture (Rev6 RM 56.11.1)
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- //
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- // --------------- 1024 ( 4096 bytes )
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- // | IN FIFO 7 |
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- // ---------------
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- // | ... |
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- // --------------- y + x + 16 + GRXFSIZ
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- // | IN FIFO 2 |
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- // --------------- x + 16 + GRXFSIZ
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- // | IN FIFO 1 |
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- // --------------- 16 + GRXFSIZ
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- // | IN FIFO 0 |
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- // --------------- GRXFSIZ
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- // | OUT FIFO |
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- // | ( Shared ) |
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- // --------------- 0
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- //
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- // FIFO sizes are set up by the following rules (each word 32-bits):
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- // All EP OUT shared a unique OUT FIFO which uses (based on page 2747 of Rev 6 of reference manual):
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- // * 10 locations in hardware for setup packets + setup control words
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- // (up to 3 setup packets).
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- // * 2 locations for OUT endpoint control words.
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- // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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- // * 1 location for global NAK (not required/used here).
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- //
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- // It is recommended to allocate 2 times the largest packet size, therefore
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- // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
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- USB2_OTG_FS->GRXFSIZ = 50;
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-
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- // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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- USB2_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB2_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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-
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- out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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-
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- USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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-}
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-
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-static void end_of_reset(void)
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-{
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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- // On current silicon on the Full Speed core, speed is fixed to Full Speed.
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- // However, keep for debugging and in case Low Speed is ever supported.
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- uint32_t enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
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-
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- // Maximum packet size for EP 0 is set for both directions by writing
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- // DIEPCTL.
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- if(enum_spd == 0x03) {
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- // 64 bytes
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- in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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- xfer_status[0][TUSB_DIR_OUT].max_size = 64;
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- xfer_status[0][TUSB_DIR_IN].max_size = 64;
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- } else {
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- // 8 bytes
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- in_ep[0].DIEPCTL |= (0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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- xfer_status[0][TUSB_DIR_OUT].max_size = 8;
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- xfer_status[0][TUSB_DIR_IN].max_size = 8;
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- }
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-}
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-
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-
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-/*------------------------------------------------------------------*/
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-/* Controller API
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- *------------------------------------------------------------------*/
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-void dcd_init (uint8_t rhport)
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-{
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- (void) rhport;
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-
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- // Programming model begins on page 2634 of Rev 6 of reference manual.
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- USB2_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_TXFELVL | USB_OTG_GAHBCFG_GINT;
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-
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- // No HNP/SRP (no OTG support), program timeout later, turnaround
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- // programmed for 32+ MHz.
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- USB2_OTG_FS->GUSBCFG |= (0x06 << USB_OTG_GUSBCFG_TRDT_Pos) | USB_OTG_GUSBCFG_PHYSEL;
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-
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- // Clear all used interrupts
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- USB2_OTG_FS->GINTSTS |= USB_OTG_GINTSTS_OTGINT | USB_OTG_GINTSTS_MMIS | \
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- USB_OTG_GINTSTS_USBRST | USB_OTG_GINTSTS_ENUMDNE | \
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- USB_OTG_GINTSTS_ESUSP | USB_OTG_GINTSTS_USBSUSP | USB_OTG_GINTSTS_SOF;
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-
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- // Required as part of core initialization. Disable OTGINT as we don't use
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- // it right now. TODO: How should mode mismatch be handled? It will cause
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- // the core to stop working/require reset.
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- USB2_OTG_FS->GINTMSK |= /* USB_OTG_GINTMSK_OTGINT | */ USB_OTG_GINTMSK_MMISM;
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-
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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-
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- // If USB host misbehaves during status portion of control xfer
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- // (non zero-length packet), send STALL back and discard. Full speed.
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- dev->DCFG |= USB_OTG_DCFG_NZLSOHSK | (3 << USB_OTG_DCFG_DSPD_Pos);
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-
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- USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | \
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- USB_OTG_GINTMSK_SOFM | USB_OTG_GINTMSK_RXFLVLM /* SB_OTG_GINTMSK_ESUSPM | \
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- USB_OTG_GINTMSK_USBSUSPM */;
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-
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- // Enable pullup, enable peripheral.
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-#ifdef USB_OTG_GCCFG_VBDEN
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- USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
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-#else
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- USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
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-#endif
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-
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- // This step does not appear to be specified in the programmer's model.
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- dev->DCTL &= ~USB_OTG_DCTL_SDIS;
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-}
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-
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-void dcd_int_enable (uint8_t rhport)
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-{
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- (void) rhport;
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- NVIC_EnableIRQ(OTG_FS_IRQn);
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-}
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-
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-void dcd_int_disable (uint8_t rhport)
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-{
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- (void) rhport;
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- NVIC_DisableIRQ(OTG_FS_IRQn);
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-}
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-
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-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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-{
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- (void) rhport;
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-
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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-
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- dev->DCFG |= (dev_addr << USB_OTG_DCFG_DAD_Pos) & USB_OTG_DCFG_DAD_Msk;
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-
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- // Response with status after changing device address
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- dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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-}
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-
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-void dcd_set_config (uint8_t rhport, uint8_t config_num)
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-{
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- (void) rhport;
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- (void) config_num;
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- // Nothing to do
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-}
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-
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-void dcd_remote_wakeup(uint8_t rhport)
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-{
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- (void) rhport;
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-}
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-
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-/*------------------------------------------------------------------*/
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-/* DCD Endpoint port
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- *------------------------------------------------------------------*/
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-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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-{
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- (void) rhport;
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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-
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- uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
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- uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
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-
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- // Unsupported endpoint numbers/size.
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- if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7)) {
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- return false;
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- }
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-
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- xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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- xfer->max_size = desc_edpt->wMaxPacketSize.size;
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-
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- if(dir == TUSB_DIR_OUT) {
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- out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | \
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- desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos | \
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- desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos;
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- dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
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- } else {
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- // Peripheral FIFO architecture (Rev6 RM 56.11.1)
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- //
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- // --------------- 1024 ( 4096 bytes )
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- // | IN FIFO 7 |
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- // ---------------
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- // | ... |
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- // --------------- y + x + 16 + GRXFSIZ
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- // | IN FIFO 2 |
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- // --------------- x + 16 + GRXFSIZ
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- // | IN FIFO 1 |
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- // --------------- 16 + GRXFSIZ
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- // | IN FIFO 0 |
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- // --------------- GRXFSIZ
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- // | OUT FIFO |
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- // | ( Shared ) |
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- // --------------- 0
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- //
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- // Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (1024-50-16) / 7 = 136 ~ 130
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-
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- in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | \
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- (epnum - 1) << USB_OTG_DIEPCTL_TXFNUM_Pos | \
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- desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos | \
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- (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | \
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- desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos;
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- dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
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-
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- // Both TXFD and TXSA are in unit of 32-bit words
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- uint16_t const fifo_size = 130;
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- uint32_t const fifo_offset = (USB2_OTG_FS->GRXFSIZ & 0x0000ffff) + 16 + fifo_size*(epnum-1);
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- USB2_OTG_FS->DIEPTXF[epnum - 1] = (130 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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- }
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-
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- return true;
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-}
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-
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-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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-{
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- (void) rhport;
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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-
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- uint8_t const epnum = tu_edpt_number(ep_addr);
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- uint8_t const dir = tu_edpt_dir(ep_addr);
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-
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- xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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- xfer->buffer = buffer;
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- xfer->total_len = total_bytes;
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- xfer->queued_len = 0;
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- xfer->short_packet = false;
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-
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- uint16_t num_packets = (total_bytes / xfer->max_size);
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- uint8_t short_packet_size = total_bytes % xfer->max_size;
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-
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- // Zero-size packet is special case.
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- if(short_packet_size > 0 || (total_bytes == 0)) {
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- num_packets++;
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- }
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-
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- // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
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- // here.
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- if(dir == TUSB_DIR_IN) {
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- // A full IN transfer (multiple packets, possibly) triggers XFRC.
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- in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | \
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- ((total_bytes & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) << USB_OTG_DIEPTSIZ_XFRSIZ_Pos);
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- in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
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- dev->DIEPEMPMSK |= (1 << epnum);
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- } else {
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- // Each complete packet for OUT xfers triggers XFRC.
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- out_ep[epnum].DOEPTSIZ |= (1 << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | \
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- ((xfer->max_size & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) << USB_OTG_DOEPTSIZ_XFRSIZ_Pos);
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- out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
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- }
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-
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- return true;
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-}
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-
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-// TODO: The logic for STALLing and disabling an endpoint is very similar
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-// (send STALL versus NAK handshakes back). Refactor into resuable function.
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-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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-{
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- (void) rhport;
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- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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-
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- uint8_t const epnum = tu_edpt_number(ep_addr);
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- uint8_t const dir = tu_edpt_dir(ep_addr);
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-
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- if(dir == TUSB_DIR_IN) {
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- // Only disable currently enabled non-control endpoint
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- if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
|
|
|
- in_ep[epnum].DIEPCTL |= (USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_STALL);
|
|
|
- } else {
|
|
|
- // Stop transmitting packets and NAK IN xfers.
|
|
|
- in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
|
- while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
|
|
|
-
|
|
|
- // Disable the endpoint.
|
|
|
- in_ep[epnum].DIEPCTL |= (USB_OTG_DIEPCTL_STALL | USB_OTG_DIEPCTL_EPDIS);
|
|
|
- while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
|
|
|
- in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
|
|
|
- }
|
|
|
-
|
|
|
- // Flush the FIFO, and wait until we have confirmed it cleared.
|
|
|
- USB2_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
|
|
|
- USB2_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
|
|
|
- while((USB2_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
|
|
|
- } else {
|
|
|
- // Only disable currently enabled non-control endpoint
|
|
|
- if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
|
|
|
- out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
|
- } else {
|
|
|
- // Asserting GONAK is required to STALL an OUT endpoint.
|
|
|
- // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
|
|
|
- // anyway, and it can't be cleared by user code. If this while loop never
|
|
|
- // finishes, we have bigger problems than just the stack.
|
|
|
- dev->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
|
- while((USB2_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
|
|
|
-
|
|
|
- // Ditto here- disable the endpoint.
|
|
|
- out_ep[epnum].DOEPCTL |= (USB_OTG_DOEPCTL_STALL | USB_OTG_DOEPCTL_EPDIS);
|
|
|
- while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
|
|
|
- out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
|
|
|
-
|
|
|
- // Allow other OUT endpoints to keep receiving.
|
|
|
- dev->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
-{
|
|
|
- (void) rhport;
|
|
|
- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
|
|
|
- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
|
|
|
-
|
|
|
- uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
- uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
-
|
|
|
- if(dir == TUSB_DIR_IN) {
|
|
|
- in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
|
-
|
|
|
- uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> \
|
|
|
- USB_OTG_DIEPCTL_EPTYP_Pos;
|
|
|
- // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
|
|
|
- // and bulk endpoints.
|
|
|
- if(eptype == 2 || eptype == 3) {
|
|
|
- in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
|
- }
|
|
|
- } else {
|
|
|
- out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
|
-
|
|
|
- uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> \
|
|
|
- USB_OTG_DOEPCTL_EPTYP_Pos;
|
|
|
- // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
|
|
|
- // and bulk endpoints.
|
|
|
- if(eptype == 2 || eptype == 3) {
|
|
|
- out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-/*------------------------------------------------------------------*/
|
|
|
-
|
|
|
-// TODO: Split into "receive on endpoint 0" and "receive generic"; endpoint 0's
|
|
|
-// DOEPTSIZ register is smaller than the others, and so is insufficient for
|
|
|
-// determining how much of an OUT transfer is actually remaining.
|
|
|
-static void receive_packet(xfer_ctl_t * xfer, /* USB_OTG_OUTEndpointTypeDef * out_ep, */ uint16_t xfer_size) {
|
|
|
- usb_fifo_t rx_fifo = FIFO_BASE(0);
|
|
|
-
|
|
|
- // See above TODO
|
|
|
- // uint16_t remaining = (out_ep->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
|
|
|
- // xfer->queued_len = xfer->total_len - remaining;
|
|
|
-
|
|
|
- uint16_t remaining = xfer->total_len - xfer->queued_len;
|
|
|
- uint16_t to_recv_size;
|
|
|
-
|
|
|
- if(remaining <= xfer->max_size) {
|
|
|
- // Avoid buffer overflow.
|
|
|
- to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
|
|
|
- } else {
|
|
|
- // Room for full packet, choose recv_size based on what the microcontroller
|
|
|
- // claims.
|
|
|
- to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
|
|
|
- }
|
|
|
-
|
|
|
- uint8_t to_recv_rem = to_recv_size % 4;
|
|
|
- uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
|
|
|
-
|
|
|
- // Do not assume xfer buffer is aligned.
|
|
|
- uint8_t * base = (xfer->buffer + xfer->queued_len);
|
|
|
-
|
|
|
- // This for loop always runs at least once- skip if less than 4 bytes
|
|
|
- // to collect.
|
|
|
- if(to_recv_size >= 4) {
|
|
|
- for(uint16_t i = 0; i < to_recv_size_aligned; i += 4) {
|
|
|
- uint32_t tmp = (* rx_fifo);
|
|
|
- base[i] = tmp & 0x000000FF;
|
|
|
- base[i + 1] = (tmp & 0x0000FF00) >> 8;
|
|
|
- base[i + 2] = (tmp & 0x00FF0000) >> 16;
|
|
|
- base[i + 3] = (tmp & 0xFF000000) >> 24;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- // Do not read invalid bytes from RX FIFO.
|
|
|
- if(to_recv_rem != 0) {
|
|
|
- uint32_t tmp = (* rx_fifo);
|
|
|
- uint8_t * last_32b_bound = base + to_recv_size_aligned;
|
|
|
-
|
|
|
- last_32b_bound[0] = tmp & 0x000000FF;
|
|
|
- if(to_recv_rem > 1) {
|
|
|
- last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
|
|
|
- }
|
|
|
- if(to_recv_rem > 2) {
|
|
|
- last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- xfer->queued_len += xfer_size;
|
|
|
-
|
|
|
- // Per USB spec, a short OUT packet (including length 0) is always
|
|
|
- // indicative of the end of a transfer (at least for ctl, bulk, int).
|
|
|
- xfer->short_packet = (xfer_size < xfer->max_size);
|
|
|
-}
|
|
|
-
|
|
|
-static void transmit_packet(xfer_ctl_t * xfer, USB_OTG_INEndpointTypeDef * in_ep, uint8_t fifo_num) {
|
|
|
- usb_fifo_t tx_fifo = FIFO_BASE(fifo_num);
|
|
|
-
|
|
|
- uint16_t remaining = (in_ep->DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
|
|
|
- xfer->queued_len = xfer->total_len - remaining;
|
|
|
-
|
|
|
- uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
|
|
|
- uint8_t to_xfer_rem = to_xfer_size % 4;
|
|
|
- uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
|
|
|
-
|
|
|
- // Buffer might not be aligned to 32b, so we need to force alignment
|
|
|
- // by copying to a temp var.
|
|
|
- uint8_t * base = (xfer->buffer + xfer->queued_len);
|
|
|
-
|
|
|
- // This for loop always runs at least once- skip if less than 4 bytes
|
|
|
- // to send off.
|
|
|
- if(to_xfer_size >= 4) {
|
|
|
- for(uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
|
|
|
- uint32_t tmp = base[i] | (base[i + 1] << 8) | \
|
|
|
- (base[i + 2] << 16) | (base[i + 3] << 24);
|
|
|
- (* tx_fifo) = tmp;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- // Do not read beyond end of buffer if not divisible by 4.
|
|
|
- if(to_xfer_rem != 0) {
|
|
|
- uint32_t tmp = 0;
|
|
|
- uint8_t * last_32b_bound = base + to_xfer_size_aligned;
|
|
|
-
|
|
|
- tmp |= last_32b_bound[0];
|
|
|
- if(to_xfer_rem > 1) {
|
|
|
- tmp |= (last_32b_bound[1] << 8);
|
|
|
- }
|
|
|
- if(to_xfer_rem > 2) {
|
|
|
- tmp |= (last_32b_bound[2] << 16);
|
|
|
- }
|
|
|
-
|
|
|
- (* tx_fifo) = tmp;
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
|
|
|
- usb_fifo_t rx_fifo = FIFO_BASE(0);
|
|
|
-
|
|
|
- // Pop control word off FIFO (completed xfers will have 2 control words,
|
|
|
- // we only pop one ctl word each interrupt).
|
|
|
- uint32_t ctl_word = USB2_OTG_FS->GRXSTSP;
|
|
|
- uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
|
|
|
- uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos;
|
|
|
- uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
|
|
|
-
|
|
|
- switch(pktsts) {
|
|
|
- case 0x01: // Global OUT NAK (Interrupt)
|
|
|
- break;
|
|
|
- case 0x02: // Out packet recvd
|
|
|
- {
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
|
|
|
- receive_packet(xfer, bcnt);
|
|
|
- }
|
|
|
- break;
|
|
|
- case 0x03: // Out packet done (Interrupt)
|
|
|
- break;
|
|
|
- case 0x04: // Setup packet done (Interrupt)
|
|
|
- _setup_offs = 2 - ((out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_STUPCNT_Msk) >> USB_OTG_DOEPTSIZ_STUPCNT_Pos);
|
|
|
- out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
|
|
|
- break;
|
|
|
- case 0x06: // Setup packet recvd
|
|
|
- {
|
|
|
- uint8_t setup_left = ((out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_STUPCNT_Msk) >> USB_OTG_DOEPTSIZ_STUPCNT_Pos);
|
|
|
-
|
|
|
- // We can receive up to three setup packets in succession, but
|
|
|
- // only the last one is valid.
|
|
|
- _setup_packet[4 - 2*setup_left] = (* rx_fifo);
|
|
|
- _setup_packet[5 - 2*setup_left] = (* rx_fifo);
|
|
|
- }
|
|
|
- break;
|
|
|
- default: // Invalid
|
|
|
- TU_BREAKPOINT();
|
|
|
- break;
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
|
|
|
- // DAINT for a given EP clears when DOEPINTx is cleared.
|
|
|
- // OEPINT will be cleared when DAINT's out bits are cleared.
|
|
|
- for(int n = 0; n < 8; n++) {
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
|
|
|
-
|
|
|
- if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
|
|
|
- // SETUP packet Setup Phase done.
|
|
|
- if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
|
|
|
- out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP;
|
|
|
- dcd_event_setup_received(0, (uint8_t*) &_setup_packet[2*_setup_offs], true);
|
|
|
- _setup_offs = 0;
|
|
|
- }
|
|
|
-
|
|
|
- // OUT XFER complete (single packet).
|
|
|
- if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
|
|
|
- out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
|
|
|
-
|
|
|
- // TODO: Because of endpoint 0's constrained size, we handle XFRC
|
|
|
- // on a packet-basis. The core can internally handle multiple OUT
|
|
|
- // packets; it would be more efficient to only trigger XFRC on a
|
|
|
- // completed transfer for non-0 endpoints.
|
|
|
-
|
|
|
- // Transfer complete if short packet or total len is transferred
|
|
|
- if(xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
|
|
|
- xfer->short_packet = false;
|
|
|
- dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
|
|
- } else {
|
|
|
- // Schedule another packet to be received.
|
|
|
- out_ep[n].DOEPTSIZ |= (1 << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | \
|
|
|
- ((xfer->max_size & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) << USB_OTG_DOEPTSIZ_XFRSIZ_Pos);
|
|
|
- out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
|
|
|
- // DAINT for a given EP clears when DIEPINTx is cleared.
|
|
|
- // IEPINT will be cleared when DAINT's out bits are cleared.
|
|
|
- for(uint8_t n = 0; n < 8; n++) {
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
|
|
|
-
|
|
|
- if(dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n))) {
|
|
|
- // IN XFER complete (entire xfer).
|
|
|
- if(in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC) {
|
|
|
- in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
|
|
|
- dev->DIEPEMPMSK &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
|
|
|
- dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
|
|
|
- }
|
|
|
-
|
|
|
- // XFER FIFO empty
|
|
|
- if(in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) {
|
|
|
- in_ep[n].DIEPINT = USB_OTG_DIEPINT_TXFE;
|
|
|
- transmit_packet(xfer, &in_ep[n], n);
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-void OTG_FS_IRQHandler (void)
|
|
|
-{
|
|
|
- USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
|
|
|
- USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
|
|
|
- USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
|
|
|
-
|
|
|
- uint32_t int_status = USB2_OTG_FS->GINTSTS;
|
|
|
-
|
|
|
- if(int_status & USB_OTG_GINTMSK_USBRST)
|
|
|
- {
|
|
|
- USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
|
|
|
- bus_reset();
|
|
|
- }
|
|
|
-
|
|
|
- if(int_status & USB_OTG_GINTMSK_ENUMDNEM)
|
|
|
- {
|
|
|
- USB2_OTG_FS->GINTSTS = USB_OTG_GINTMSK_ENUMDNEM;
|
|
|
- end_of_reset();
|
|
|
- dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
|
|
- }
|
|
|
-
|
|
|
- if(int_status & USB_OTG_GINTSTS_SOF) {
|
|
|
- USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
|
|
|
- dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
|
|
|
- }
|
|
|
-
|
|
|
- if(int_status & USB_OTG_GINTSTS_RXFLVL) {
|
|
|
- read_rx_fifo(out_ep);
|
|
|
- }
|
|
|
-
|
|
|
- // OUT endpoint interrupt handling.
|
|
|
- if(int_status & USB_OTG_GINTSTS_OEPINT) {
|
|
|
- handle_epout_ints(dev, out_ep);
|
|
|
- }
|
|
|
-
|
|
|
- // IN endpoint interrupt handling.
|
|
|
- if(int_status & USB_OTG_GINTSTS_IEPINT) {
|
|
|
- handle_epin_ints(dev, in_ep);
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-#endif
|
hathach