Merge pull request #808 from hathach/lpc55-port1-hs

Lpc55 port1 hs

docs/boards.md

@@ -102,10 +102,14 @@ This code base already had supported for a handful of following boards (sorted a
 - [LPCXpresso18S37 Development Board](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc4000-cortex-m4/lpcxpresso18s37-development-board:OM13076)
 - [LPCXpresso 51U68](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005)
 - [LPCXpresso 54114](https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso54114-board:OM13089)
-- [LPCXpresso 55s28 EVK](https://www.nxp.com/design/software/development-software/lpcxpresso55s28-development-board:LPC55S28-EVK)
-- [LPCXpresso 55s69 EVK](https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK)
 - [NGX LPC4330-Xplorer](https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027)
+
+## NXP LPC55
+
 - [Double M33 Express](https://www.crowdsupply.com/steiert-solutions/double-m33-express)
+- [LPCXpresso 55s28 EVK](https://www.nxp.com/design/software/development-software/lpcxpresso55s28-development-board:LPC55S28-EVK)
+- [LPCXpresso 55s69 EVK](https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK)
+- [MCU-Link](https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK)
 
 ### Renesas RX
 

hw/bsp/lpc55/boards/double_m33_express/board.h

@@ -53,6 +53,9 @@
 #define UART_RX_PINMUX        0U, 29U, IOCON_PIO_DIG_FUNC1_EN
 #define UART_TX_PINMUX        0U, 30U, IOCON_PIO_DIG_FUNC1_EN
 
+// XTAL
+//#define XTAL0_CLK_HZ          16000000U
+
 #ifdef __cplusplus
  }
 #endif

hw/bsp/lpc55/boards/lpcxpresso55s28/board.h

@@ -42,9 +42,12 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-//#define UART_DEV              USART0
-//#define UART_RX_PINMUX        0U, 29U, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0U, 30U, IOCON_PIO_DIG_FUNC1_EN
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          16000000U
 
 #ifdef __cplusplus
  }

hw/bsp/lpc55/boards/lpcxpresso55s69/board.h

@@ -42,9 +42,12 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-//#define UART_DEV              USART0
-//#define UART_RX_PINMUX        0U, 29U, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0U, 30U, IOCON_PIO_DIG_FUNC1_EN
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          16000000U
 
 #ifdef __cplusplus
  }

hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk

@@ -2,6 +2,7 @@ MCU_VARIANT = LPC55S69
 MCU_CORE = LPC55S69_cm33_core0
 
 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
+PORT ?= 1
 
 JLINK_DEVICE = LPC55S69
 PYOCD_TARGET = LPC55S69

hw/bsp/lpc55/boards/mcu_link/board.h

@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              0
+#define LED_PIN               5
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_PORT           0
+#define BUTTON_PIN            30
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif

hw/bsp/lpc55/boards/mcu_link/board.mk

@@ -0,0 +1,13 @@
+PORT ?= 1
+SPEED ?= high
+
+MCU_VARIANT = LPC55S69
+MCU_CORE = LPC55S69_cm33_core0
+
+CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0
+
+JLINK_DEVICE = LPC55S69
+PYOCD_TARGET = LPC55S69
+
+# flash using pyocd
+flash: flash-pyocd

hw/bsp/lpc55/family.c

@@ -34,19 +34,6 @@
 #include "fsl_sctimer.h"
 #include "sct_neopixel.h"
 
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB1_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -67,6 +54,19 @@ void USB1_IRQHandler(void)
 #define IOCON_PIO_DIG_FUNC4_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) /*!<@brief Digital pin function 2 enabled */
 #define IOCON_PIO_DIG_FUNC7_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) /*!<@brief Digital pin function 2 enabled */
 
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USB1_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
 /****************************************************************
 name: BOARD_BootClockFROHF96M
 outputs:
@@ -109,10 +109,10 @@ void board_init(void)
   // Init 96 MHz clock
   BootClockFROHF96M();
 
-#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
@@ -145,7 +145,7 @@ void board_init(void)
   gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
   GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
 
-#if defined(UART_DEV)
+#ifdef UART_DEV
   // UART
   IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
   IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
@@ -164,43 +164,71 @@ void board_init(void)
   /* PORT0 PIN22 configured as USB0_VBUS */
   IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
 
-  // USB Controller
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB0 Phy */
-  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*< Turn on USB1 Phy */
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  // Port0 is Full Speed
+
+  /* Turn on USB0 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
 
   /* reset the IP to make sure it's in reset state. */
   RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
-
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-  CLOCK_EnableClock(kCLOCK_Usbh1);
-  /* Put PHY powerdown under software control */
-  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
-  /* According to reference mannual, device mode setting has to be set by access usb host register */
-  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
-  /* enable usb1 host clock */
-  CLOCK_DisableClock(kCLOCK_Usbh1);
-#endif
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
   // Enable USB Clock Adjustments to trim the FRO for the full speed controller
   ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
   CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
   CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-  /* enable usb0 host clock */
-  CLOCK_EnableClock(kCLOCK_Usbhsl0);
+
   /*According to reference mannual, device mode setting has to be set by access usb host register */
+  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
   USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-  /* disable usb0 host clock */
-  CLOCK_DisableClock(kCLOCK_Usbhsl0);
-  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB Device clock */
+  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+
+  /* enable USB Device clock */
+  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
 #endif
 
+#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+  // Port1 is High Speed
+
+  /* Turn on USB1 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
+
+  /* reset the IP to make sure it's in reset state. */
+  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
+
+  /* According to reference mannual, device mode setting has to be set by access usb host register */
+  CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+
+  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
+  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+
+  CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+
+  /* enable USB Device clock */
+  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
+  CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
+  CLOCK_EnableClock(kCLOCK_UsbRam1);
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  USBPHY->PWD = 0;
+
+  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
+  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
+
+  // TX Timing
+//  uint32_t phytx = USBPHY->TX;
+//  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+//  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+//  USBPHY->TX = phytx;
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -237,8 +265,8 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  (void) buf; (void) len;
-  return 0;
+  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
+  return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE

hw/bsp/lpc55/family.mk

@@ -14,13 +14,15 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv5-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
   -DBOARD_DEVICE_RHPORT_NUM=$(PORT)
 
 ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
   $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+
+  # LPC55 Highspeed Port1 can only write to USB_SRAM region
+  CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
 else
   $(info "PORT0 Full Speed")
 endif

src/class/msc/msc_device.c

@@ -77,28 +77,19 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
 
 static inline uint32_t rdwr10_get_lba(uint8_t const command[])
 {
-  // read10 & write10 has the same format
-  scsi_write10_t* p_rdwr10 = (scsi_write10_t*) command;
+  // use offsetof to avoid pointer to the odd/unaligned address
+  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
 
-  // copy first to prevent mis-aligned access
-  uint32_t lba;
-  // use offsetof to avoid pointer to the odd/misaligned address
-  memcpy(&lba, (uint8_t*) p_rdwr10 + offsetof(scsi_write10_t, lba), 4);
-
-  // lba is in Big Endian format
+  // lba is in Big Endian
   return tu_ntohl(lba);
 }
 
 static inline uint16_t rdwr10_get_blockcount(uint8_t const command[])
 {
-  // read10 & write10 has the same format
-  scsi_write10_t* p_rdwr10 = (scsi_write10_t*) command;
-
-  // copy first to prevent mis-aligned access
-  uint16_t block_count;
   // use offsetof to avoid pointer to the odd/misaligned address
-  memcpy(&block_count, (uint8_t*) p_rdwr10 + offsetof(scsi_write10_t, block_count), 2);
+  uint16_t const block_count = tu_unaligned_read16(command + offsetof(scsi_write10_t, block_count));
 
+  // block count is in Big Endian
   return tu_ntohs(block_count);
 }
 

src/common/tusb_common.h

@@ -47,13 +47,13 @@
 #define U16_TO_U8S_BE(u16)    TU_U16_HIGH(u16), TU_U16_LOW(u16)
 #define U16_TO_U8S_LE(u16)    TU_U16_LOW(u16), TU_U16_HIGH(u16)
 
-#define U32_B1_U8(u32)        ((uint8_t) ((((uint32_t) u32) >> 24) & 0x000000ff)) // MSB
-#define U32_B2_U8(u32)        ((uint8_t) ((((uint32_t) u32) >> 16) & 0x000000ff))
-#define U32_B3_U8(u32)        ((uint8_t) ((((uint32_t) u32) >>  8) & 0x000000ff))
-#define U32_B4_U8(u32)        ((uint8_t) (((uint32_t)  u32)        & 0x000000ff)) // LSB
+#define TU_U32_BYTE3(u32)     ((uint8_t) ((((uint32_t) u32) >> 24) & 0x000000ff)) // MSB
+#define TU_U32_BYTE2(u32)     ((uint8_t) ((((uint32_t) u32) >> 16) & 0x000000ff))
+#define TU_U32_BYTE1(u32)     ((uint8_t) ((((uint32_t) u32) >>  8) & 0x000000ff))
+#define TU_U32_BYTE0(u32)     ((uint8_t) (((uint32_t)  u32)        & 0x000000ff)) // LSB
 
-#define U32_TO_U8S_BE(u32)    U32_B1_U8(u32), U32_B2_U8(u32), U32_B3_U8(u32), U32_B4_U8(u32)
-#define U32_TO_U8S_LE(u32)    U32_B4_U8(u32), U32_B3_U8(u32), U32_B2_U8(u32), U32_B1_U8(u32)
+#define U32_TO_U8S_BE(u32)    TU_U32_BYTE3(u32), TU_U32_BYTE2(u32), TU_U32_BYTE1(u32), TU_U32_BYTE0(u32)
+#define U32_TO_U8S_LE(u32)    TU_U32_BYTE0(u32), TU_U32_BYTE1(u32), TU_U32_BYTE2(u32), TU_U32_BYTE3(u32)
 
 #define TU_BIT(n)             (1U << (n))
 
@@ -81,9 +81,9 @@
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
 
 //------------- Bytes -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
 {
-  return ( ((uint32_t) b1) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b3) << 8) | b4;
+  return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
@@ -91,8 +91,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
   return (uint16_t) ((((uint16_t) high) << 8) | low);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return (uint8_t) (((uint16_t) (u16 >> 8)) & 0x00ff); }
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return (uint8_t) (u16 & 0x00ff); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t u32) { return TU_U32_BYTE3(u32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t u32) { return TU_U32_BYTE2(u32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t u32) { return TU_U32_BYTE1(u32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t u32) { return TU_U32_BYTE0(u32); }
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return TU_U16_HIGH(u16); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return TU_U16_LOW(u16); }
 
 //------------- Bits -------------//
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set  (uint32_t value, uint8_t pos) { return value | TU_BIT(pos);                  }
@@ -115,8 +120,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t a
   return value & ((uint32_t) ~(alignment-1));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
 
@@ -141,6 +146,8 @@ static inline uint8_t tu_log2(uint32_t value)
 //------------- Unaligned Access -------------//
 #if TUP_ARCH_STRICT_ALIGN
 
+// Rely on compiler to generate correct code for unaligned access
+
 typedef struct { uint16_t val; } TU_ATTR_PACKED tu_unaligned_uint16_t;
 typedef struct { uint32_t val; } TU_ATTR_PACKED tu_unaligned_uint32_t;
 
@@ -168,8 +175,44 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
   ua16->val = value;
 }
 
+#elif TUP_MCU_STRICT_ALIGN
+
+// MCU such as LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM although it is ARM M4.
+// We have to manually pick up bytes since tu_unaligned_uint32_t will still generate unaligned code
+// NOTE: volatile cast to memory to prevent compiler to optimize and generate unaligned code
+// TODO Big Endian may need minor changes
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void* mem)
+{
+  volatile uint8_t const* buf8 = (uint8_t const*) mem;
+  return tu_u32(buf8[3], buf8[2], buf8[1], buf8[0]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void* mem, uint32_t value)
+{
+  volatile uint8_t* buf8 = (uint8_t*) mem;
+  buf8[0] = tu_u32_byte0(value);
+  buf8[1] = tu_u32_byte1(value);
+  buf8[2] = tu_u32_byte2(value);
+  buf8[3] = tu_u32_byte3(value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void* mem)
+{
+  volatile uint8_t const* buf8 = (uint8_t const*) mem;
+  return tu_u16(buf8[1], buf8[0]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_t value)
+{
+  volatile uint8_t* buf8 = (uint8_t*) mem;
+  buf8[0] = tu_u16_low(value);
+  buf8[1] = tu_u16_high(value);
+}
+
+
 #else
 
+// MCU that could access unaligned memory natively
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem           ) { return *((uint32_t*) mem);  }
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem           ) { return *((uint16_t*) mem);  }
 

src/device/usbd.c

@@ -302,6 +302,8 @@ static char const* const _tusb_std_request_str[] =
   "Synch Frame"
 };
 
+static char const* const _tusb_speed_str[] = { "Full", "Low", "High" };
+
 // for usbd_control to print the name of control complete driver
 void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
 {
@@ -464,7 +466,7 @@ void tud_task (void)
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG2("\r\n");
+        TU_LOG2(": %s Speed\r\n", _tusb_speed_str[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;

src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c

@@ -33,11 +33,7 @@
  * - LPC51U68
  * - LPC54114
  * - LPC55s69
- *
- * For similar controller of other families, this file may require some minimal changes to work with.
- * Previous MCUs such as LPC17xx, LPC40xx, LPC18xx, LPC43xx have their own driver implementation.
  */
-
 #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC13XX  || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC15XX  || \
@@ -45,45 +41,45 @@
                                  CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC55XX)
 
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+
 #if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
-  // LPC 11Uxx, 13xx, 15xx use lpcopen
+  // LPCOpen
   #include "chip.h"
-  #define DCD_REGS        LPC_USB
-
-#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-      CFG_TUSB_MCU == OPT_MCU_LPC55XX // TODO 55xx has dual usb controllers
+#else
+  // SDK
   #include "fsl_device_registers.h"
-  #define DCD_REGS        USB0
-
+  #define INCLUDE_FSL_DEVICE_REGISTERS
 #endif
 
 #include "device/dcd.h"
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
+// IP3511 Registers
 //--------------------------------------------------------------------+
 
-// Number of endpoints
-// - 11 13 15 51 54 has 5x2 endpoints
-// - 18/43 usb0 & 55s usb1 (HS) has 6x2 endpoints
-// - 18/43 usb1 & 55s usb0 (FS) has 4x2 endpoints
-#define EP_COUNT 10
-
-// only SRAM1 & USB RAM can be used for transfer.
-// Used to set DATABUFSTART which is 22-bit aligned
-// 2000 0000 to 203F FFFF
-#define SRAM_REGION   0x20000000
-
-/* Although device controller are the same. Somehow only LPC134x can execute
- * DMA with 1023 bytes for Bulk/Control. Others (11u, 51u, 54xxx) can only work
- * with max 64 bytes
- */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;    // Device Command/Status register, offset: 0x0
+  __I  uint32_t INFO;          // Info register, offset: 0x4
+  __IO uint32_t EPLISTSTART;   // EP Command/Status List start address, offset: 0x8
+  __IO uint32_t DATABUFSTART;  // Data buffer start address, offset: 0xC
+  __IO uint32_t LPM;           // Link Power Management register, offset: 0x10
+  __IO uint32_t EPSKIP;        // Endpoint skip, offset: 0x14
+  __IO uint32_t EPINUSE;       // Endpoint Buffer in use, offset: 0x18
+  __IO uint32_t EPBUFCFG;      // Endpoint Buffer Configuration register, offset: 0x1C
+  __IO uint32_t INTSTAT;       // interrupt status register, offset: 0x20
+  __IO uint32_t INTEN;         // interrupt enable register, offset: 0x24
+  __IO uint32_t INTSETSTAT;    // set interrupt status register, offset: 0x28
+       uint8_t RESERVED_0[8];
+  __I  uint32_t EPTOGGLE;      // Endpoint toggle register, offset: 0x34
+} dcd_registers_t;
+
+// Max nbytes for each control/bulk/interrupt transfer
 enum {
-  #if CFG_TUSB_MCU == OPT_MCU_LPC13XX
-    DMA_NBYTES_MAX = 1023
-  #else
-    DMA_NBYTES_MAX = 64
-  #endif
+  NBYTES_CBI_FULLSPEED_MAX = 64,
+  NBYTES_CBI_HIGHSPEED_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
 
 enum {
@@ -95,57 +91,124 @@ enum {
   CMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
   CMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
   CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), ///< reflect the soft-connect only, does not reflect the actual attached state
+  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
   CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
+                                            // 23-22 is link speed (only available for HighSpeed port)
   CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
   CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
   CMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
   CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
 };
 
-typedef struct TU_ATTR_PACKED
+enum {
+  CMDSTAT_SPEED_SHIFT = 22
+};
+
+//--------------------------------------------------------------------+
+// Endpoint Command/Status List
+//--------------------------------------------------------------------+
+
+// Endpoint Command/Status
+typedef union TU_ATTR_PACKED
 {
-  // Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
-  volatile uint16_t buffer_offset;
-
-  volatile uint16_t nbytes : 10 ;
-  uint16_t is_iso          : 1  ;
-  uint16_t toggle_mode     : 1  ;
-  uint16_t toggle_reset    : 1  ;
-  uint16_t stall           : 1  ;
-  uint16_t disable         : 1  ;
-  volatile uint16_t active : 1  ;
+  // Full and High speed has different bit layout for buffer_offset and nbytes
+
+  // Buffer (aligned 64) = DATABUFSTART [31:22]  | buffer_offset [21:6]
+  volatile struct {
+    uint32_t offset      : 16;
+    uint32_t nbytes      : 10;
+    uint32_t TU_RESERVED : 6;
+  } buffer_fs;
+
+  // Buffer (aligned 64) = USB_RAM [31:17] | buffer_offset [16:6]
+  volatile struct {
+    uint32_t offset      : 11 ;
+    uint32_t nbytes      : 15 ;
+    uint32_t TU_RESERVED : 6  ;
+  } buffer_hs;
+
+  volatile struct {
+    uint32_t TU_RESERVED  : 26;
+    uint32_t is_iso       : 1 ;
+    uint32_t toggle_mode  : 1 ;
+    uint32_t toggle_reset : 1 ;
+    uint32_t stall        : 1 ;
+    uint32_t disable      : 1 ;
+    uint32_t active       : 1 ;
+  };
 }ep_cmd_sts_t;
 
 TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
 
+// Software transfer management
 typedef struct
 {
   uint16_t total_bytes;
   uint16_t xferred_bytes;
 
   uint16_t nbytes;
+
+  // prevent unaligned access on Highspeed port on USB_SRAM
+  uint16_t TU_RESERVED;
 }xfer_dma_t;
 
+// Absolute max of endpoints pairs for all port
+// - 11 13 15 51 54 has 5x2 endpoints
+// - 55 usb0 (FS) has 5x2 endpoints, usb1 (HS) has 6x2 endpoints
+#define MAX_EP_PAIRS  6
+
 // NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
 // current_td is used to keep track of number of remaining & xferred bytes of the current request.
 typedef struct
 {
   // 256 byte aligned, 2 for double buffer (not used)
   // Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
-  ep_cmd_sts_t ep[EP_COUNT][2];
-
-  xfer_dma_t dma[EP_COUNT];
+  ep_cmd_sts_t ep[2*MAX_EP_PAIRS][2];
+  xfer_dma_t dma[2*MAX_EP_PAIRS];
 
   TU_ATTR_ALIGNED(64) uint8_t setup_packet[8];
 }dcd_data_t;
 
+// EP list must be 256-byte aligned
+//    Some MCU controller may require this variable to be placed in specific SRAM region.
+//    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
+//    Use CFG_TUSB_MEM_SECTION to place it accordingly.
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
+
 //--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
+// Multiple Controllers
 //--------------------------------------------------------------------+
 
-// EP list must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
+typedef struct
+{
+  dcd_registers_t* regs;        // registers
+  const tusb_speed_t max_speed; // max link speed
+  const IRQn_Type irqnum;       // IRQ number
+  const uint8_t ep_pairs;       // Max bi-directional Endpoints
+}dcd_controller_t;
+
+#ifdef INCLUDE_FSL_DEVICE_REGISTERS
+
+static const dcd_controller_t _dcd_controller[] =
+{
+    { .regs = (dcd_registers_t*) USB0_BASE  , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
+  #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
+    { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
+  #endif
+};
+
+#else
+
+static const dcd_controller_t _dcd_controller[] =
+{
+  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
+};
+
+#endif
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
 
 static inline uint16_t get_buf_offset(void const * buffer)
 {
@@ -154,9 +217,9 @@ static inline uint16_t get_buf_offset(void const * buffer)
   return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
-static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
+static inline uint8_t ep_addr2id(uint8_t ep_addr)
 {
-  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+  return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
 }
 
 //--------------------------------------------------------------------+
@@ -164,38 +227,37 @@ static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
 //--------------------------------------------------------------------+
 void dcd_init(uint8_t rhport)
 {
-  (void) rhport;
-
-  DCD_REGS->EPLISTSTART  = (uint32_t) _dcd.ep;
-  DCD_REGS->DATABUFSTART = SRAM_REGION; // 22-bit alignment
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
-  DCD_REGS->INTSTAT      = DCD_REGS->INTSTAT; // clear all pending interrupt
-  DCD_REGS->INTEN        = INT_DEVICE_STATUS_MASK;
-  DCD_REGS->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
+  dcd_reg->EPLISTSTART  = (uint32_t) _dcd.ep;
+  dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment
+  dcd_reg->INTSTAT     |= dcd_reg->INTSTAT; // clear all pending interrupt
+  dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK;
+  dcd_reg->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
                            CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
 
-  NVIC_ClearPendingIRQ(USB0_IRQn);
+  NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
 }
 
 void dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(USB0_IRQn);
+  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  DCD_REGS->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
-  DCD_REGS->DEVCMDSTAT |= dev_addr;
+  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  dcd_reg->DEVCMDSTAT |= dev_addr;
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
@@ -205,14 +267,14 @@ void dcd_remote_wakeup(uint8_t rhport)
 
 void dcd_connect(uint8_t rhport)
 {
-  (void) rhport;
-  DCD_REGS->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
-  (void) rhport;
-  DCD_REGS->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 //--------------------------------------------------------------------+
@@ -255,20 +317,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
 
   // Enable EP interrupt
-  DCD_REGS->INTEN |= TU_BIT(ep_id);
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->INTEN |= TU_BIT(ep_id);
 
   return true;
 }
 
-static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
+static void prepare_setup_packet(uint8_t rhport)
 {
-  uint16_t const nbytes = tu_min16(total_bytes, DMA_NBYTES_MAX);
+  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
+  {
+    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);;
+  }else
+  {
+    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);;
+  }
+}
+
+static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
+{
+  uint16_t nbytes;
+
+  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
+  {
+    // TODO ISO FullSpeed can have up to 1023 bytes
+    nbytes = tu_min16(total_bytes, NBYTES_CBI_FULLSPEED_MAX);
+    _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
+    _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
+  }else
+  {
+    nbytes = tu_min16(total_bytes, NBYTES_CBI_HIGHSPEED_MAX);
+    _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
+    _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
+  }
 
   _dcd.dma[ep_id].nbytes = nbytes;
 
-  _dcd.ep[ep_id][0].buffer_offset = buf_offset;
-  _dcd.ep[ep_id][0].nbytes        = nbytes;
-  _dcd.ep[ep_id][0].active        = 1;
+  _dcd.ep[ep_id][0].active = 1;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
@@ -277,10 +362,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
-  tu_varclr(&_dcd.dma[ep_id]);
+  tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
+  prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;
 }
@@ -288,52 +373,76 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 //--------------------------------------------------------------------+
 // IRQ
 //--------------------------------------------------------------------+
-static void bus_reset(void)
+static void bus_reset(uint8_t rhport)
 {
   tu_memclr(&_dcd, sizeof(dcd_data_t));
 
   // disable all non-control endpoints on bus reset
-  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
+  for(uint8_t ep_id = 2; ep_id < 2*MAX_EP_PAIRS; ep_id++)
   {
     _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
   }
 
-  _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
+  prepare_setup_packet(rhport);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
-  DCD_REGS->EPINUSE      = 0;
-  DCD_REGS->EPBUFCFG     = 0;
-  DCD_REGS->EPSKIP       = 0xFFFFFFFF;
+  dcd_reg->EPINUSE      = 0;
+  dcd_reg->EPBUFCFG     = 0;
+  dcd_reg->EPSKIP       = 0xFFFFFFFF;
 
-  DCD_REGS->INTSTAT      = DCD_REGS->INTSTAT; // clear all pending interrupt
-  DCD_REGS->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
-  DCD_REGS->INTEN        = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
+  dcd_reg->INTSTAT      = dcd_reg->INTSTAT;                               // clear all pending interrupt
+  dcd_reg->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
+  dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
 }
 
-static void process_xfer_isr(uint32_t int_status)
+static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
 {
-  for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
+  uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
+
+  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
   {
     if ( tu_bit_test(int_status, ep_id) )
     {
       ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
       xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
 
-      xfer_dma->xferred_bytes += xfer_dma->nbytes - ep_cs->nbytes;
+      if ( ep_id == 0 || ep_id == 1)
+      {
+        // For control endpoint, we need to manually clear Active bit
+        ep_cs->active = 0;
+      }
+
+      uint16_t buf_offset;
+      uint16_t buf_nbytes;
 
-      if ( (ep_cs->nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
+      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL)
+      {
+        buf_offset = ep_cs->buffer_fs.offset;
+        buf_nbytes = ep_cs->buffer_fs.nbytes;
+      }else
+      {
+        buf_offset = ep_cs->buffer_hs.offset;
+        buf_nbytes = ep_cs->buffer_hs.nbytes;
+      }
+
+      xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes;
+
+      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
       {
         // There is more data to transfer
         // buff_offset has been already increased by hw to correct value for next transfer
-        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
+        prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
       }
       else
       {
+        // for detecting ZLP
         xfer_dma->total_bytes = xfer_dma->xferred_bytes;
 
-        uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
+        uint8_t const ep_addr = tu_edpt_addr(ep_id / 2, ep_id & 0x01);
 
         // TODO no way determine if the transfer is failed or not
-        dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(rhport, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
       }
     }
   }
@@ -341,23 +450,36 @@ static void process_xfer_isr(uint32_t int_status)
 
 void dcd_int_handler(uint8_t rhport)
 {
-  (void) rhport; // TODO support multiple USB on supported mcu such as LPC55s69
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
-  uint32_t const cmd_stat = DCD_REGS->DEVCMDSTAT;
+  uint32_t const cmd_stat = dcd_reg->DEVCMDSTAT;
 
-  uint32_t int_status = DCD_REGS->INTSTAT & DCD_REGS->INTEN;
-  DCD_REGS->INTSTAT = int_status; // Acknowledge handled interrupt
+  uint32_t int_status = dcd_reg->INTSTAT & dcd_reg->INTEN;
+  dcd_reg->INTSTAT = int_status; // Acknowledge handled interrupt
 
   if (int_status == 0) return;
 
   //------------- Device Status -------------//
   if ( int_status & INT_DEVICE_STATUS_MASK )
   {
-    DCD_REGS->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+
     if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
     {
-      bus_reset();
-      dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
+      bus_reset(rhport);
+
+      tusb_speed_t speed = TUSB_SPEED_FULL;
+
+      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
+      {
+        // 0 : reserved, 1 : full, 2 : high, 3: super
+        if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
+        {
+          speed= TUSB_SPEED_HIGH;
+        }
+      }
+
+      dcd_event_bus_reset(rhport, speed, true);
     }
 
     if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
@@ -366,7 +488,7 @@ void dcd_int_handler(uint8_t rhport)
       if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
       {
         // debouncing as this can be set when device is powering
-        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+        dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
       }
     }
 
@@ -378,13 +500,13 @@ void dcd_int_handler(uint8_t rhport)
         // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
         if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
         {
-          dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+          dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
         }
       }
     }
 //        else
 //      { // resume signal
-//    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+//    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 //      }
 //    }
   }
@@ -396,19 +518,19 @@ void dcd_int_handler(uint8_t rhport)
     _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
     _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
 
-    DCD_REGS->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
 
-    dcd_event_setup_received(0, _dcd.setup_packet, true);
+    dcd_event_setup_received(rhport, _dcd.setup_packet, true);
 
     // keep waiting for next setup
-    _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
+    prepare_setup_packet(rhport);
 
     // clear bit0
     int_status = tu_bit_clear(int_status, 0);
   }
 
   // Endpoint transfer complete interrupt
-  process_xfer_isr(int_status);
+  process_xfer_isr(rhport, int_status);
 }
 
 #endif

src/portable/nxp/transdimension/dcd_transdimension.c

@@ -34,6 +34,7 @@
 //--------------------------------------------------------------------+
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #include "fsl_device_registers.h"
+  #define INCLUDE_FSL_DEVICE_REGISTERS
 #else
   // LPCOpen for 18xx & 43xx
   #include "chip.h"

src/tusb_option.h

@@ -283,6 +283,7 @@
 
 // TUP_ARCH_STRICT_ALIGN if arch cannot access unaligned memory
 
+
 // ARMv7+ (M3-M7, M23-M33) can access unaligned memory
 #if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
   #define TUP_ARCH_STRICT_ALIGN   0
@@ -290,6 +291,16 @@
   #define TUP_ARCH_STRICT_ALIGN   1
 #endif
 
+// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
+// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
+// to generate unaligned access code.
+// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
+#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+  #define TUP_MCU_STRICT_ALIGN   1
+#else
+  #define TUP_MCU_STRICT_ALIGN   0
+#endif
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------