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+/*
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+ * The MIT License (MIT)
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+ *
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+ * Copyright (c) 2019-2020 William D. Jones
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+ * Copyright (c) 2019-2020 Ha Thach (tinyusb.org)
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * in the Software without restriction, including without limitation the rights
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+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+ * copies of the Software, and to permit persons to whom the Software is
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+ * furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * THE SOFTWARE.
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+ *
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+ * This file is part of the TinyUSB stack.
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+ */
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+
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+#include "tusb_option.h"
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+
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+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MSP430x5xx )
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+
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+#include "msp430.h"
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+#include "device/dcd.h"
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+
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+/*------------------------------------------------------------------*/
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+/* MACRO TYPEDEF CONSTANT ENUM
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+ *------------------------------------------------------------------*/
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+// usbpllir_mirror and usbmaintl_mirror can be added later if needed.
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+static volatile uint16_t usbiepie_mirror = 0;
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+static volatile uint16_t usboepie_mirror = 0;
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+static volatile uint8_t usbie_mirror = 0;
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+static volatile uint16_t usbpwrctl_mirror = 0;
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+static bool in_isr = false;
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+
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+uint8_t _setup_packet[8];
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+
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+// Xfer control
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+typedef struct
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+{
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+ uint8_t * buffer;
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+ uint16_t total_len;
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+ uint16_t queued_len;
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+ uint16_t max_size;
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+ bool short_packet;
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+} xfer_ctl_t;
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+
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+xfer_ctl_t xfer_status[8][2];
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+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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+
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+// Accessing endpoint regs
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+typedef volatile uint8_t * ep_regs_t;
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+
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+typedef enum
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+{
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+ CNF = 0,
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+ BBAX = 1,
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+ BCTX = 2,
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+ BBAY = 5,
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+ BCTY = 6,
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+ SIZXY = 7
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+} ep_regs_index_t;
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+
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+#define EP_REGS(epnum, dir) &USBOEPCNF_1 + 64*dir + 8*(epnum - 1)
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+
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+
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+static void bus_reset(void)
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+{
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+ // Hardcoded into the USB core.
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+ xfer_status[0][TUSB_DIR_OUT].max_size = 8;
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+ xfer_status[0][TUSB_DIR_IN].max_size = 8;
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+
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+ USBKEYPID = USBKEY;
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+
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+ // Enable the control EP 0. Also enable Indication Enable- a guard flag
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+ // separate from the Interrupt Enable mask.
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+ USBOEPCNF_0 |= (UBME | USBIIE);
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+ USBIEPCNF_0 |= (UBME | USBIIE);
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+
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+ // Enable interrupts for this endpoint.
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+ USBOEPIE |= BIT0;
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+ USBIEPIE |= BIT0;
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+
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+ // Clear NAK until a setup packet is received.
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+ USBOEPCNT_0 &= ~NAK;
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+ USBIEPCNT_0 &= ~NAK;
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+
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+ USBCTL |= FEN; // Enable responding to packets.
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+
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+ // Dedicated buffers in hardware for SETUP and EP0, no setup needed.
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+ // Now safe to respond to SETUP packets.
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+ USBIE |= SETUPIE;
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+
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+ USBKEYPID = 0;
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+}
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+
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+
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+/*------------------------------------------------------------------*/
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+/* Controller API
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+ *------------------------------------------------------------------*/
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+void dcd_init (uint8_t rhport)
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+{
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+ (void) rhport;
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+
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+ USBKEYPID = USBKEY;
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+
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+ // Enable the module (required to write config regs)!
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+ USBCNF |= USB_EN;
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+
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+ // Reset used interrupts
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+ USBOEPIE = 0;
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+ USBIEPIE = 0;
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+ USBIE = 0;
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+ USBOEPIFG = 0;
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+ USBIEPIFG = 0;
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+ USBIFG = 0;
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+ USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE | VUOVLIFG | VBONIFG | VBOFFIFG);
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+ usboepie_mirror = 0;
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+ usbiepie_mirror = 0;
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+ usbie_mirror = 0;
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+ usbpwrctl_mirror = 0;
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+
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+ USBVECINT = 0;
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+
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+ // Enable reset and wait for it before continuing.
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+ USBIE |= RSTRIE;
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+
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+ // Enable pullup.
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+ USBCNF |= PUR_EN;
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+
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+ USBKEYPID = 0;
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+}
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+
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+// There is no "USB peripheral interrupt disable" bit on MSP430, so we have
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+// to save the relevant registers individually.
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+// WARNING: Unlike the ARM/NVIC routines, these functions are _not_ idempotent
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+// if you modified the registers saved in between calls so they don't match
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+// the mirrors; mirrors will be updated to reflect most recent register
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+// contents.
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+void dcd_int_enable (uint8_t rhport)
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+{
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+ (void) rhport;
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+
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+ __bic_SR_register(GIE); // Unlikely to be called in ISR, but let's be safe.
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+ // Also, this cleanly disables all USB interrupts
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+ // atomically from application's POV.
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+
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+ // This guard is required because tinyusb can enable interrupts without
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+ // having disabled them first.
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+ if(in_isr)
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+ {
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+ USBOEPIE = usboepie_mirror;
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+ USBIEPIE = usbiepie_mirror;
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+ USBIE = usbie_mirror;
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+ USBPWRCTL |= usbpwrctl_mirror;
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+ }
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+
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+ in_isr = false;
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+ __bis_SR_register(GIE);
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+}
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+
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+void dcd_int_disable (uint8_t rhport)
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+{
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+ (void) rhport;
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+
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+ __bic_SR_register(GIE);
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+ usboepie_mirror = USBOEPIE;
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+ usbiepie_mirror = USBIEPIE;
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+ usbie_mirror = USBIE;
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+ usbpwrctl_mirror = (USBPWRCTL & (VUOVLIE | VBONIE | VBOFFIE));
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+ USBOEPIE = 0;
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+ USBIEPIE = 0;
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+ USBIE = 0;
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+ USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE);
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+ in_isr = true;
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+ __bis_SR_register(GIE);
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+}
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+
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+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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+{
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+ (void) rhport;
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+
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+ USBFUNADR = dev_addr;
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+
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+ // Response with status after changing device address
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+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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+}
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+
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+void dcd_set_config (uint8_t rhport, uint8_t config_num)
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+{
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+ (void) rhport;
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+ (void) config_num;
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+ // Nothing to do
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+}
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+
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+void dcd_remote_wakeup(uint8_t rhport)
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+{
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+ (void) rhport;
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+}
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+
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+/*------------------------------------------------------------------*/
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+/* DCD Endpoint port
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+ *------------------------------------------------------------------*/
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+
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+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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+{
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+ (void) rhport;
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+
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+ uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
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+ uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
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+
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+ // Unsupported endpoint numbers/size or type (Iso not supported. Control
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+ // not supported on nonzero endpoints).
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+ if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7) || \
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+ (desc_edpt->bmAttributes.xfer == 0) || \
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+ (desc_edpt->bmAttributes.xfer == 1)) {
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+ return false;
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+ }
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+
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+ xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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+ xfer->max_size = desc_edpt->wMaxPacketSize.size;
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+
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+ // Buffer allocation scheme:
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+ // For simplicity, only single buffer for now, since tinyusb currently waits
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+ // for an xfer to complete before scheduling another one. This means only
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+ // the X buffer is used.
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+ //
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+ // 1904 bytes are available, the max endpoint size supported on msp430 is
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+ // 64 bytes. This is enough RAM for all 14 endpoints enabled _with_ double
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+ // bufferring (64*14*2 = 1792 bytes). Extra RAM exists for triple and higher
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+ // order bufferring, which must be maintained in software.
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+ //
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+ // For simplicity, each endpoint gets a hardcoded 64 byte chunk (regardless
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+ // of actual wMaxPacketSize) whose start address is the following:
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+ // addr = 128 * (epnum - 1) + 64 * dir.
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+ //
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+ // Double buffering equation:
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+ // x_addr = 256 * (epnum - 1) + 128 * dir
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+ // y_addr = x_addr + 64
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+ // Address is right-shifted by 3 to fit into 8 bits.
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+
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+ uint8_t buf_base = (128 * (epnum - 1) + 64 * dir) >> 3;
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+
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+ // IN and OUT EP registers have the same structure.
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+ ep_regs_t ep_regs = EP_REGS(epnum, dir);
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+
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+ // FIXME: I was able to get into a situation where OUT EP 3 would stall
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+ // while debugging, despite stall code never being called. It appears
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+ // these registers don't get cleared on reset, being part of RAM.
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+ // Investigate and see if I can duplicate.
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+ // Also, DBUF got set on OUT EP 2 while debugging. Only OUT EPs seem to be
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+ // affected at this time. USB RAM directly precedes main RAM; perhaps I'm
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+ // overwriting registers via buffer overflow w/ my debugging code?
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+ ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size;
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+ ep_regs[BCTX] |= NAK;
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+ ep_regs[BBAX] = buf_base;
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+ ep_regs[CNF] &= ~(TOGGLE | STALL | DBUF); // ISO xfers not supported on
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+ // MSP430, so no need to gate DATA0/1 and frame
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+ // behavior. Clear stall and double buffer bit as
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+ // well- see above comment.
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+ ep_regs[CNF] |= (UBME | USBIIE);
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+
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+ USBKEYPID = USBKEY;
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+ if(dir == TUSB_DIR_OUT)
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+ {
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+ USBOEPIE |= (1 << epnum);
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+ }
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+ else
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+ {
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+ USBIEPIE |= (1 << epnum);
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+ }
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+ USBKEYPID = 0;
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+
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+ return true;
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+}
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+
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+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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+{
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+ (void) rhport;
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+
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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+
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+ xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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+ xfer->buffer = buffer;
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+ xfer->total_len = total_bytes;
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+ xfer->queued_len = 0;
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+ xfer->short_packet = false;
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+
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+ if(epnum == 0)
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+ {
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+ if(dir == TUSB_DIR_OUT)
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+ {
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+ // Interrupt will notify us when data was received.
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+ USBCTL &= ~DIR;
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+ USBOEPCNT_0 &= ~NAK;
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+ }
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+ else
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+ {
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+ // Kickstart the IN packet handler by queuing initial data and calling
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+ // the ISR to transmit the first packet.
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+ // Interrupt only fires on completed xfer.
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+ USBCTL |= DIR;
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+ USBIEPIFG |= BIT0;
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+ }
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+ }
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+ else
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+ {
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+ ep_regs_t ep_regs = EP_REGS(epnum, dir);
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+
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+ if(dir == TUSB_DIR_OUT)
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+ {
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+ ep_regs[BCTX] &= ~NAK;
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+ }
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+ else
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+ {
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+ USBIEPIFG |= (1 << epnum);
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+ }
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+ }
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+
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+ return true;
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+}
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+
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+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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+{
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+ (void) rhport;
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+
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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+
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+ if(epnum == 0)
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+ {
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+ if(dir == TUSB_DIR_OUT)
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+ {
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+ USBOEPCNT_0 |= NAK;
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+ USBOEPCNF_0 |= STALL;
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+ }
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+ else
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+ {
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+ USBIEPCNT_0 |= NAK;
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+ USBIEPCNF_0 |= STALL;
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+ }
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+ }
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+ else
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+ {
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+ ep_regs_t ep_regs = EP_REGS(epnum, dir);
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+ ep_regs[CNF] |= STALL;
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+ }
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+}
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+
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+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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+{
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+ (void) rhport;
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+
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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+
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+ if(epnum == 0)
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+ {
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+ if(dir == TUSB_DIR_OUT)
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+ {
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+ USBOEPCNF_0 &= ~STALL;
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+ }
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+ else
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+ {
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+ USBIEPCNF_0 &= ~STALL;
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+ }
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+ }
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+ else
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+ {
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+ ep_regs_t ep_regs = EP_REGS(epnum, dir);
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+ // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
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+ // and bulk endpoints.
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+ ep_regs[CNF] &= ~(STALL + TOGGLE);
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+ }
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+}
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+
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+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
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+{
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+ (void) rhport;
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+ (void) request;
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+
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+ // FIXME: Per manual, we should be clearing the NAK bits of EP0 after the
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+ // Status Phase of a control xfer is done, in preparation of another possible
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+ // SETUP packet. However, from my own testing, SETUP packets _are_ correctly
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+ // handled by the USB core without clearing the NAKs.
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+ //
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+ // Right now, clearing NAKs in this callbacks causes a direction mismatch
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+ // between host and device on EP0. Figure out why and come back to this.
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+ // USBOEPCNT_0 &= ~NAK;
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+ // USBIEPCNT_0 &= ~NAK;
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+}
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+
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+/*------------------------------------------------------------------*/
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+
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+static void receive_packet(uint8_t ep_num)
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+{
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+ xfer_ctl_t * xfer = XFER_CTL_BASE(ep_num, TUSB_DIR_OUT);
|
|
|
+ ep_regs_t ep_regs = EP_REGS(ep_num, TUSB_DIR_OUT);
|
|
|
+ uint8_t xfer_size;
|
|
|
+
|
|
|
+ if(ep_num == 0)
|
|
|
+ {
|
|
|
+ xfer_size = USBOEPCNT_0 & 0x0F;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ xfer_size = ep_regs[BCTX] & 0x7F;
|
|
|
+ }
|
|
|
+
|
|
|
+ uint16_t remaining = xfer->total_len - xfer->queued_len;
|
|
|
+ uint16_t to_recv_size;
|
|
|
+
|
|
|
+ if(remaining <= xfer->max_size) {
|
|
|
+ // Avoid buffer overflow.
|
|
|
+ to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
|
|
|
+ } else {
|
|
|
+ // Room for full packet, choose recv_size based on what the microcontroller
|
|
|
+ // claims.
|
|
|
+ to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
|
|
|
+ }
|
|
|
+
|
|
|
+ uint8_t * base = (xfer->buffer + xfer->queued_len);
|
|
|
+
|
|
|
+ if(ep_num == 0)
|
|
|
+ {
|
|
|
+ volatile uint8_t * ep0out_buf = &USBOEP0BUF;
|
|
|
+ for(uint16_t i = 0; i < to_recv_size; i++)
|
|
|
+ {
|
|
|
+ base[i] = ep0out_buf[i];
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ volatile uint8_t * ep_buf = &USBSTABUFF + (ep_regs[BBAX] << 3);
|
|
|
+ for(uint16_t i = 0; i < to_recv_size ; i++)
|
|
|
+ {
|
|
|
+ base[i] = ep_buf[i];
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ xfer->queued_len += xfer_size;
|
|
|
+
|
|
|
+ xfer->short_packet = (xfer_size < xfer->max_size);
|
|
|
+ if((xfer->total_len == xfer->queued_len) || xfer->short_packet)
|
|
|
+ {
|
|
|
+ dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // Schedule to receive another packet.
|
|
|
+ if(ep_num == 0)
|
|
|
+ {
|
|
|
+ USBOEPCNT_0 &= ~NAK;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ ep_regs[BCTX] &= ~NAK;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void transmit_packet(uint8_t ep_num)
|
|
|
+{
|
|
|
+ xfer_ctl_t * xfer = XFER_CTL_BASE(ep_num, TUSB_DIR_IN);
|
|
|
+
|
|
|
+ // First, determine whether we should even send a packet or finish
|
|
|
+ // up the xfer.
|
|
|
+ bool zlp = (xfer->total_len == 0); // By necessity, xfer->total_len will
|
|
|
+ // equal xfer->queued_len for ZLPs.
|
|
|
+ // Of course a ZLP is a short packet.
|
|
|
+ if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->short_packet)
|
|
|
+ {
|
|
|
+ dcd_event_xfer_complete(0, ep_num | TUSB_DIR_IN_MASK, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ // Then actually commit to transmit a packet.
|
|
|
+ uint8_t * base = (xfer->buffer + xfer->queued_len);
|
|
|
+ uint16_t remaining = xfer->total_len - xfer->queued_len;
|
|
|
+ uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining;
|
|
|
+
|
|
|
+ xfer->queued_len += xfer_size;
|
|
|
+ if(xfer_size < xfer->max_size)
|
|
|
+ {
|
|
|
+ // Next "xfer complete interrupt", the transfer will end.
|
|
|
+ xfer->short_packet = true;
|
|
|
+ }
|
|
|
+
|
|
|
+ if(ep_num == 0)
|
|
|
+ {
|
|
|
+ volatile uint8_t * ep0in_buf = &USBIEP0BUF;
|
|
|
+ for(uint16_t i = 0; i < xfer_size; i++)
|
|
|
+ {
|
|
|
+ ep0in_buf[i] = base[i];
|
|
|
+ }
|
|
|
+
|
|
|
+ USBIEPCNT_0 = (USBIEPCNT_0 & 0xF0) + xfer_size;
|
|
|
+ USBIEPCNT_0 &= ~NAK;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ ep_regs_t ep_regs = EP_REGS(ep_num, TUSB_DIR_IN);
|
|
|
+ volatile uint8_t * ep_buf = &USBSTABUFF + (ep_regs[BBAX] << 3);
|
|
|
+
|
|
|
+ for(int i = 0; i < xfer_size; i++)
|
|
|
+ {
|
|
|
+ ep_buf[i] = base[i];
|
|
|
+ }
|
|
|
+
|
|
|
+ ep_regs[BCTX] = (ep_regs[BCTX] & 0x80) + (xfer_size & 0x7F);
|
|
|
+ ep_regs[BCTX] &= ~NAK;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void handle_setup_packet(void)
|
|
|
+{
|
|
|
+ volatile uint8_t * setup_buf = &USBSUBLK;
|
|
|
+
|
|
|
+ for(int i = 0; i < 8; i++)
|
|
|
+ {
|
|
|
+ _setup_packet[i] = setup_buf[i];
|
|
|
+ }
|
|
|
+
|
|
|
+ // Clearing SETUPIFG by reading USBVECINT does not set NAK, so now that we
|
|
|
+ // have a SETUP packet, force NAKs until tinyusb can handle the SETUP
|
|
|
+ // packet and prepare for a new xfer.
|
|
|
+ USBIEPCNT_0 |= NAK;
|
|
|
+ USBOEPCNT_0 |= NAK;
|
|
|
+ dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
|
|
|
+}
|
|
|
+
|
|
|
+void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void)
|
|
|
+{
|
|
|
+ // Setup is special- reading USBVECINT to handle setup packets is done to
|
|
|
+ // stop hardware-generated NAKs on EP0.
|
|
|
+ uint8_t setup_status = USBIFG & SETUPIFG;
|
|
|
+
|
|
|
+ if(setup_status)
|
|
|
+ {
|
|
|
+ handle_setup_packet();
|
|
|
+ }
|
|
|
+
|
|
|
+ uint16_t curr_vector = USBVECINT;
|
|
|
+
|
|
|
+ switch(curr_vector)
|
|
|
+ {
|
|
|
+ case USBVECINT_RSTR:
|
|
|
+ bus_reset();
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
|
|
+ break;
|
|
|
+
|
|
|
+ // Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet
|
|
|
+ // is received. At this point, even though the hardware is no longer
|
|
|
+ // forcing NAKs, the EP0 NAK bits should still be set to avoid
|
|
|
+ // sending/receiving data before tinyusb is ready.
|
|
|
+ //
|
|
|
+ // Furthermore, it's possible for the hardware to STALL in the middle of
|
|
|
+ // a control xfer if the EP0 NAK bits aren't set properly.
|
|
|
+ // See: https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/845259
|
|
|
+ // From my testing, if all of the following hold:
|
|
|
+ // * OUT EP0 NAK is cleared.
|
|
|
+ // * IN EP0 NAK is set.
|
|
|
+ // * DIR bit in USBCTL is clear.
|
|
|
+ // and an IN packet is received on EP0, the USB core will STALL. Setting
|
|
|
+ // both EP0 NAKs manually when a SETUP packet is received, as is done
|
|
|
+ // in handle_setup_packet(), avoids meeting STALL conditions.
|
|
|
+ //
|
|
|
+ // TODO: Figure out/explain why the STALL condition can be reached in the
|
|
|
+ // first place. When I first noticed the STALL, the only two places I
|
|
|
+ // touched the NAK bits were in dcd_edpt_xfer() and to _set_ (sic) them in
|
|
|
+ // bus_reset(). SETUP packet handling should've been unaffected.
|
|
|
+ case USBVECINT_SETUP_PACKET_RECEIVED:
|
|
|
+ break;
|
|
|
+
|
|
|
+ case USBVECINT_INPUT_ENDPOINT0:
|
|
|
+ transmit_packet(0);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT0:
|
|
|
+ receive_packet(0);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case USBVECINT_INPUT_ENDPOINT1:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT2:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT3:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT4:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT5:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT6:
|
|
|
+ case USBVECINT_INPUT_ENDPOINT7:
|
|
|
+ {
|
|
|
+ uint8_t ep = ((curr_vector - USBVECINT_INPUT_ENDPOINT1) >> 1) + 1;
|
|
|
+ transmit_packet(ep);
|
|
|
+ }
|
|
|
+ break;
|
|
|
+
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT1:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT2:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT3:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT4:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT5:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT6:
|
|
|
+ case USBVECINT_OUTPUT_ENDPOINT7:
|
|
|
+ {
|
|
|
+ uint8_t ep = ((curr_vector - USBVECINT_OUTPUT_ENDPOINT1) >> 1) + 1;
|
|
|
+ receive_packet(ep);
|
|
|
+ }
|
|
|
+ break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ while(true);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|
Ha Thach