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@@ -262,7 +262,7 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
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if (!ep->configured)
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{
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// Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
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- ep->interrupt_num = i - 1;
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+ ep->interrupt_num = (uint8_t) (i - 1);
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return ep;
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}
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}
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@@ -297,7 +297,7 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
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return ep;
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}
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-static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
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+static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
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{
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// Already has data buffer, endpoint control, and buffer control allocated at this point
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assert(ep->endpoint_control);
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@@ -329,7 +329,10 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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| EP_CTRL_INTERRUPT_PER_BUFFER
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| (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
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| dpram_offset;
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- ep_reg |= bmInterval ? (bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB : 0;
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+ if (bmInterval)
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+ {
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+ ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
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+ }
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*ep->endpoint_control = ep_reg;
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pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
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ep->configured = true;
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@@ -341,7 +344,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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// device address
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// endpoint number / direction
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// preamble
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- uint32_t reg = dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB);
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+ uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
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if (dir == TUSB_DIR_OUT)
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{
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@@ -367,39 +370,41 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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//--------------------------------------------------------------------+
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bool hcd_init(uint8_t rhport)
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{
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- pico_trace("hcd_init %d\n", rhport);
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- assert(rhport == 0);
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+ (void) rhport;
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+ pico_trace("hcd_init %d\n", rhport);
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+ assert(rhport == 0);
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- // Reset any previous state
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- rp2040_usb_init();
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+ // Reset any previous state
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+ rp2040_usb_init();
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- // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
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- usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
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+ // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
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+ usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
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- irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
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+ irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
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- // clear epx and interrupt eps
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- memset(&ep_pool, 0, sizeof(ep_pool));
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+ // clear epx and interrupt eps
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+ memset(&ep_pool, 0, sizeof(ep_pool));
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- // Enable in host mode with SOF / Keep alive on
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- usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
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- usb_hw->sie_ctrl = SIE_CTRL_BASE;
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- usb_hw->inte = USB_INTE_BUFF_STATUS_BITS |
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- USB_INTE_HOST_CONN_DIS_BITS |
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- USB_INTE_HOST_RESUME_BITS |
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- USB_INTE_STALL_BITS |
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- USB_INTE_TRANS_COMPLETE_BITS |
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- USB_INTE_ERROR_RX_TIMEOUT_BITS |
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- USB_INTE_ERROR_DATA_SEQ_BITS ;
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+ // Enable in host mode with SOF / Keep alive on
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+ usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
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+ usb_hw->sie_ctrl = SIE_CTRL_BASE;
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+ usb_hw->inte = USB_INTE_BUFF_STATUS_BITS |
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+ USB_INTE_HOST_CONN_DIS_BITS |
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+ USB_INTE_HOST_RESUME_BITS |
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+ USB_INTE_STALL_BITS |
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+ USB_INTE_TRANS_COMPLETE_BITS |
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+ USB_INTE_ERROR_RX_TIMEOUT_BITS |
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+ USB_INTE_ERROR_DATA_SEQ_BITS ;
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- return true;
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+ return true;
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}
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void hcd_port_reset(uint8_t rhport)
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{
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- pico_trace("hcd_port_reset\n");
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- assert(rhport == 0);
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- // TODO: Nothing to do here yet. Perhaps need to reset some state?
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+ (void) rhport;
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+ pico_trace("hcd_port_reset\n");
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+ assert(rhport == 0);
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+ // TODO: Nothing to do here yet. Perhaps need to reset some state?
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}
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void hcd_port_reset_end(uint8_t rhport)
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@@ -409,25 +414,27 @@ void hcd_port_reset_end(uint8_t rhport)
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bool hcd_port_connect_status(uint8_t rhport)
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{
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- pico_trace("hcd_port_connect_status\n");
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- assert(rhport == 0);
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- return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
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+ (void) rhport;
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+ pico_trace("hcd_port_connect_status\n");
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+ assert(rhport == 0);
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+ return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
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}
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tusb_speed_t hcd_port_speed_get(uint8_t rhport)
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{
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- assert(rhport == 0);
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- // TODO: Should enumval this register
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- switch (dev_speed())
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- {
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- case 1:
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- return TUSB_SPEED_LOW;
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- case 2:
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- return TUSB_SPEED_FULL;
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- default:
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- panic("Invalid speed\n");
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- return TUSB_SPEED_INVALID;
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- }
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+ (void) rhport;
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+ assert(rhport == 0);
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+ // TODO: Should enumval this register
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+ switch (dev_speed())
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+ {
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+ case 1:
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+ return TUSB_SPEED_LOW;
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+ case 2:
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+ return TUSB_SPEED_FULL;
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+ default:
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+ panic("Invalid speed\n");
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+ return TUSB_SPEED_INVALID;
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+ }
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}
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// Close all opened endpoint belong to this device
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@@ -465,15 +472,17 @@ uint32_t hcd_frame_number(uint8_t rhport)
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void hcd_int_enable(uint8_t rhport)
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{
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- assert(rhport == 0);
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- irq_set_enabled(USBCTRL_IRQ, true);
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+ (void) rhport;
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+ assert(rhport == 0);
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+ irq_set_enabled(USBCTRL_IRQ, true);
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}
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void hcd_int_disable(uint8_t rhport)
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{
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- // todo we should check this is disabling from the correct core; note currently this is never called
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- assert(rhport == 0);
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- irq_set_enabled(USBCTRL_IRQ, false);
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+ (void) rhport;
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+ // todo we should check this is disabling from the correct core; note currently this is never called
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+ assert(rhport == 0);
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+ irq_set_enabled(USBCTRL_IRQ, false);
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}
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//--------------------------------------------------------------------+
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@@ -488,6 +497,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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// Allocated differently based on if it's an interrupt endpoint or not
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struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
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+ TU_ASSERT(ep);
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_hw_endpoint_init(ep,
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dev_addr,
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@@ -510,7 +520,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// Get appropriate ep. Either EPX or interrupt endpoint
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struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
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- assert(ep);
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+ TU_ASSERT(ep);
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// EP should be inactive
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assert(!ep->active);
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@@ -532,7 +542,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// That has set up buffer control, endpoint control etc
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// for host we have to initiate the transfer
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- usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
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+ usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
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uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
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(ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
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@@ -556,11 +566,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Warray-bounds"
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#pragma GCC diagnostic ignored "-Wstringop-overflow"
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- memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
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+ memcpy((void*) (uintptr_t) &usbh_dpram->setup_packet[0], setup_packet, 8);
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#pragma GCC diagnostic pop
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// Configure EP0 struct with setup info for the trans complete
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struct hw_endpoint *ep = _hw_endpoint_allocate(0);
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+ TU_ASSERT(ep);
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// EPX should be inactive
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assert(!ep->active);
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