Merge pull request #220 from hathach/develop

Port NXP iMX RT10XX

examples/device/cdc_msc/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/cdc_msc_hid_freertos/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/dfu_rt/src/tusb_config.h

@@ -21,7 +21,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/hid_composite/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/hid_generic_inout/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/midi_test/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/msc_dual_lun/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/usbtmc/src/tusb_config.h

@@ -21,7 +21,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/device/webusb_serial/src/tusb_config.h

@@ -39,7 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE

examples/host/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject

@@ -29,7 +29,7 @@
       linker_memory_map_file="LPC1769_MemoryMap.xml"
       linker_section_placement_file="flash_placement.xml"
       linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_175x_6x"
+      macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x"
       project_directory=""
       project_type="Executable"
       target_reset_script="Reset();"
@@ -46,40 +46,40 @@
         <file file_name="../../../../../hw/bsp/ansi_escape.h" />
         <file file_name="../../../../../hw/bsp/board.h" />
         <folder Name="lpcxpresso1769">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" />
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" />
+          <file file_name="../../../../../hw/bsp/lpcxpresso1769/lpcxpresso1769.c" />
         </folder>
+        <file file_name="../../../../../hw/bsp/board.c" />
       </folder>
       <folder Name="mcu">
         <folder Name="nxp">
           <folder Name="lpc_chip_175x_6x">
             <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sys_config.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cm3.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/lpc_types.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/sys_config.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" />
             </folder>
             <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
             </folder>
           </folder>
         </folder>

examples/host/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject

@@ -24,7 +24,7 @@
       gcc_entry_point="Reset_Handler"
       linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
       linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_18xx"
+      macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx"
       package_dependencies="LPC1800"
       project_directory=""
       project_type="Executable"
@@ -51,52 +51,51 @@
         <file file_name="../../../../../hw/bsp/ansi_escape.h" />
         <file file_name="../../../../../hw/bsp/board.h" />
         <folder Name="mcb1800">
-          <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.c" />
-          <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.h" />
+          <file file_name="../../../../../hw/bsp/mcb1800/mcb1800.c" />
         </folder>
       </folder>
       <folder Name="mcu">
         <folder Name="nxp">
           <folder Name="lpc_chip_18xx">
             <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_common_tables.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_math.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_clocks.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/clock_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0plus.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc000.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc300.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/creg_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/gpio_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/uart_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/arm_common_tables.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/arm_math.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_clocks.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_lpc18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_lpc43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/clock_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm0.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm0plus.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm3.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_sc000.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_sc300.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/creg_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/gpio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/lpc_types.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/uart_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" />
               <folder Name="config_18xx">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/sys_config.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/config_18xx/sys_config.h" />
               </folder>
             </folder>
             <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/chip_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/clock_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/gpio_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/sysinit_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/uart_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/chip_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/clock_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/gpio_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/sysinit_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/uart_18xx_43xx.c" />
             </folder>
           </folder>
         </folder>

examples/host/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject

@@ -26,7 +26,7 @@
       gcc_entry_point="Reset_Handler"
       linker_memory_map_file="$(ProjectDir)/LPC4088FBD208_MemoryMap.xml"
       linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_40xx"
+      macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx"
       package_dependencies="LPC4000"
       project_directory=""
       project_type="Executable"
@@ -53,40 +53,39 @@
         <file file_name="../../../../../hw/bsp/ansi_escape.h" />
         <file file_name="../../../../../hw/bsp/board.h" />
         <folder Name="ea4088qs">
-          <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.c" />
-          <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.h" />
+          <file file_name="../../../../../hw/bsp/ea4088qs/ea4088qs.c" />
         </folder>
       </folder>
       <folder Name="mcu">
         <folder Name="nxp">
           <folder Name="lpc_chip_40xx">
             <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc175x_6x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc177x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc407x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/clock_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/cmsis_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/gpio_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/sys_config.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/uart_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/usb_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/iocon_17xx_40xx.h" />
             </folder>
             <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/chip_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/clock_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/gpio_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/iocon_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/sysctl_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/sysinit_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/uart_17xx_40xx.c" />
             </folder>
           </folder>
         </folder>

examples/host/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject

@@ -29,7 +29,7 @@
       linker_memory_map_file="LPC4357 Cortex-M4_MemoryMap.xml"
       linker_section_placement_file="flash_placement.xml"
       linker_section_placements_segments="FLASH RX 0x1a000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_43xx"
+      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx"
       project_directory=""
       project_type="Executable"
       target_reset_script="Reset();"
@@ -46,8 +46,7 @@
         <file file_name="../../../../../hw/bsp/ansi_escape.h" />
         <file file_name="../../../../../hw/bsp/board.h" />
         <folder Name="ea4357">
-          <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.c" />
-          <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.h" />
+          <file file_name="../../../../../hw/bsp/ea4357/ea4357.c" />
           <file file_name="../../../../../hw/bsp/ea4357/pca9532.c" />
           <file file_name="../../../../../hw/bsp/ea4357/pca9532.h" />
         </folder>
@@ -56,52 +55,52 @@
         <folder Name="nxp">
           <folder Name="lpc_chip_43xx">
             <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_common_tables.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_math.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_clocks.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/clock_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0plus.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc000.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc300.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/creg_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/fpu_init.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gpio_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/packing.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/uart_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/arm_common_tables.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/arm_math.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_clocks.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_lpc18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_lpc43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/clock_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm0.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm0plus.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm3.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_sc000.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_sc300.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/creg_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/fpu_init.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/gpio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2c_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/lpc_types.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/packing.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/uart_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" />
               <folder Name="config_43xx">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/sys_config.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/config_43xx/sys_config.h" />
               </folder>
             </folder>
             <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/chip_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/clock_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/fpu_init.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/gpio_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2c_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2cm_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sysinit_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/uart_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/chip_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/clock_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/fpu_init.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/gpio_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/i2c_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/i2cm_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/sysinit_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/uart_18xx_43xx.c" />
             </folder>
           </folder>
         </folder>

examples/host/cdc_msc_hid/src/tusb_config.h

@@ -40,7 +40,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST

examples/make.mk

@@ -85,11 +85,7 @@ CFLAGS += \
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og -ggdb
 else
-  ifneq ($(BOARD),spresense)
-    CFLAGS += -flto -Os
-  else
-    CFLAGS += -Os
-  endif
+	CFLAGS += -Os
 endif
 
 # TUSB Logging option

hw/bsp/circuitplayground_bluefruit/board.mk

@@ -1,11 +1,12 @@
 CFLAGS += \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
-	-DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-	-DNRF52840_XXAA \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
+  -DNRF52840_XXAA \
   -DCONFIG_GPIO_AS_PINRESET
 
 # nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
@@ -23,17 +24,17 @@ LD_FILE = hw/bsp/circuitplayground_bluefruit/nrf52840_s140_v6.ld
 LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
 
 SRC_C += \
-	hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
-	hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \
+  hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
+  hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \
 
 INC += \
-	$(TOP)/hw/mcu/nordic/cmsis/Include \
-	$(TOP)/hw/mcu/nordic \
-	$(TOP)/hw/mcu/nordic/nrfx \
-	$(TOP)/hw/mcu/nordic/nrfx/mdk \
-	$(TOP)/hw/mcu/nordic/nrfx/hal \
-	$(TOP)/hw/mcu/nordic/nrfx/drivers/include \
-	$(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+  $(TOP)/hw/mcu/nordic/cmsis/Include \
+  $(TOP)/hw/mcu/nordic \
+  $(TOP)/hw/mcu/nordic/nrfx \
+  $(TOP)/hw/mcu/nordic/nrfx/mdk \
+  $(TOP)/hw/mcu/nordic/nrfx/hal \
+  $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
+  $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
 
 SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_nrf52840.S
 

hw/bsp/circuitplayground_express/board.mk

@@ -11,23 +11,23 @@ CFLAGS += \
 LD_FILE = hw/bsp/circuitplayground_express/samd21g18a_flash.ld
 
 SRC_C += \
-	hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
-	hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
-	hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
+  hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
+  hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
+  hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
+  hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
+  hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
+  hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
 
 INC += \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/pm/ \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
-	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/pm/ \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
+  $(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
 
 # For TinyUSB port source 
 VENDOR = microchip

hw/bsp/ea4088qs/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
@@ -16,9 +17,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/ea4088qs/lpc4088.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \

hw/bsp/ea4088qs/ea4088qs.c

@@ -113,6 +113,21 @@ void board_init(void)
   LPC_USB->StCtrl = 0x3;
 }
 
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/ea4357/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
@@ -15,9 +16,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/ea4357/lpc4357.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
@@ -34,7 +32,7 @@ INC += \
 
 # For TinyUSB port source
 VENDOR = nxp
-CHIP_FAMILY = lpc18_43
+CHIP_FAMILY = transdimension
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4

hw/bsp/ea4357/ea4357.c

@@ -166,19 +166,19 @@ void board_init(void)
 #if CFG_TUSB_RHPORT0_MODE
   Chip_USB0_Init();
 
-  // Reset controller
-  LPC_USB0->USBCMD_D |= 0x02;
-  while( LPC_USB0->USBCMD_D & 0x02 ) {}
-
-  // Set mode
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-
-    LPC_USB0->PORTSC1_D |= (1<<24); // FIXME force full speed for debugging
-  #else // TODO OTG
-    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
-    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-  #endif
+//  // Reset controller
+//  LPC_USB0->USBCMD_D |= 0x02;
+//  while( LPC_USB0->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+//    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//
+//    LPC_USB0->PORTSC1_D |= (1<<24); // FIXME force full speed for debugging
+//  #else // TODO OTG
+//    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
+//    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+//  #endif
 #endif
 
   /* USB1
@@ -202,19 +202,19 @@ void board_init(void)
 #if CFG_TUSB_RHPORT1_MODE
   Chip_USB1_Init();
 
-  // Reset controller
-  LPC_USB1->USBCMD_D |= 0x02;
-  while( LPC_USB1->USBCMD_D & 0x02 ) {}
-
-  // Set mode
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
-  #endif
-
-  // USB1 as fullspeed
-  LPC_USB1->PORTSC1_D |= (1<<24);
+//  // Reset controller
+//  LPC_USB1->USBCMD_D |= 0x02;
+//  while( LPC_USB1->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+//    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//  #else // TODO OTG
+//    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+//  #endif
+//
+//  // USB1 as fullspeed
+//  LPC_USB1->PORTSC1_D |= (1<<24);
 #endif
 
   // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
@@ -230,6 +230,31 @@ void board_init(void)
   // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
 }
 
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
+void USB1_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    tuh_isr(1);
+  #endif
+
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+    tud_isr(1);
+  #endif
+}
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/feather_m0_express/board.mk

@@ -1,10 +1,11 @@
 CFLAGS += \
-  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
-  -D__SAMD21G18A__ \
+  -flto \
   -mthumb \
   -mabi=aapcs-linux \
   -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
+  -D__SAMD21G18A__ \
+  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 # All source paths should be relative to the top level.

hw/bsp/feather_m4_express/board.mk

@@ -1,11 +1,12 @@
 CFLAGS += \
-  -D__SAMD51J19A__ \
+  -flto \
   -mthumb \
   -mabi=aapcs-linux \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -D__SAMD51J19A__ \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
 CFLAGS += -Wno-error=undef

hw/bsp/feather_nrf52840_express/board.mk

@@ -1,11 +1,12 @@
 CFLAGS += \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
-	-DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-	-DNRF52840_XXAA \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
+  -DNRF52840_XXAA \
   -DCONFIG_GPIO_AS_PINRESET
 
 # nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
@@ -23,17 +24,17 @@ LD_FILE = hw/bsp/feather_nrf52840_express/nrf52840_s140_v6.ld
 LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
 
 SRC_C += \
-	hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
-	hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \
+  hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
+  hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \
 
 INC += \
-	$(TOP)/hw/mcu/nordic/cmsis/Include \
-	$(TOP)/hw/mcu/nordic \
-	$(TOP)/hw/mcu/nordic/nrfx \
-	$(TOP)/hw/mcu/nordic/nrfx/mdk \
-	$(TOP)/hw/mcu/nordic/nrfx/hal \
-	$(TOP)/hw/mcu/nordic/nrfx/drivers/include \
-	$(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+  $(TOP)/hw/mcu/nordic/cmsis/Include \
+  $(TOP)/hw/mcu/nordic \
+  $(TOP)/hw/mcu/nordic/nrfx \
+  $(TOP)/hw/mcu/nordic/nrfx/mdk \
+  $(TOP)/hw/mcu/nordic/nrfx/hal \
+  $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
+  $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
 
 SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_nrf52840.S
 

hw/bsp/feather_stm32f405/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=12000000 \
-  -DSTM32F405xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F405xx \
+  -DHSE_VALUE=12000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver

hw/bsp/fomu/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -march=rv32i \
   -mabi=ilp32 \
   -nostdlib \

hw/bsp/lpcxpresso11u37/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0 \

hw/bsp/lpcxpresso11u68/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \

hw/bsp/lpcxpresso1347/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \

hw/bsp/lpcxpresso1549/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \

hw/bsp/lpcxpresso1769/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \
@@ -16,9 +17,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/lpcxpresso1769/lpc1769.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \

hw/bsp/lpcxpresso1769/lpcxpresso1769.c

@@ -143,6 +143,20 @@ void board_init(void)
 #endif
 }
 
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/lpcxpresso51u68/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \

hw/bsp/lpcxpresso54114/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \

hw/bsp/lpcxpresso55s69/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m33 \

hw/bsp/mbed1768/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \
@@ -16,9 +17,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/mbed1768/lpc1768.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
@@ -43,5 +41,7 @@ FREERTOS_PORT = ARM_CM3
 JLINK_DEVICE = LPC1768
 JLINK_IF = swd
 
-# flash using jlink
-flash: flash-jlink
+# flash using pyocd 
+flash: $(BUILD)/$(BOARD)-firmware.hex
+	pyocd flash -t lpc1768 $<
+

hw/bsp/mbed1768/mbed1768.c

@@ -135,6 +135,20 @@ void board_init(void)
 #endif
 }
 
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/mcb1800/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \
@@ -15,9 +16,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/mcb1800/lpc1857.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
@@ -32,7 +30,7 @@ INC += \
 
 # For TinyUSB port source
 VENDOR = nxp
-CHIP_FAMILY = lpc18_43
+CHIP_FAMILY = transdimension
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3

hw/bsp/mcb1800/mcb1800.c

@@ -139,39 +139,63 @@ void board_init(void)
 #if CFG_TUSB_RHPORT0_MODE
   Chip_USB0_Init();
 
-  // Reset controller
-  LPC_USB0->USBCMD_D |= 0x02;
-  while( LPC_USB0->USBCMD_D & 0x02 ) {}
-
-  // Set mode
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
-    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-  #endif
+//  // Reset controller
+//  LPC_USB0->USBCMD_D |= 0x02;
+//  while( LPC_USB0->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+//    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//  #else // TODO OTG
+//    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
+//    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+//  #endif
 #endif
 
   // USB1
 #if CFG_TUSB_RHPORT1_MODE
   Chip_USB1_Init();
 
-  // Reset controller
-  LPC_USB1->USBCMD_D |= 0x02;
-  while( LPC_USB1->USBCMD_D & 0x02 ) {}
+//  // Reset controller
+//  LPC_USB1->USBCMD_D |= 0x02;
+//  while( LPC_USB1->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+//    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//  #else // TODO OTG
+//    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+//  #endif
+//
+//  // USB1 as fullspeed
+//  LPC_USB1->PORTSC1_D |= (1<<24);
+#endif
+}
 
-  // Set mode
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
   #endif
 
-  // USB1 as fullspeed
-  LPC_USB1->PORTSC1_D |= (1<<24);
-#endif
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
 }
 
+void USB1_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    tuh_isr(1);
+  #endif
+
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+    tud_isr(1);
+  #endif
+}
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/metro_m0_express/board.mk

@@ -1,10 +1,11 @@
 CFLAGS += \
-  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
-  -D__SAMD21G18A__ \
+  -flto \
   -mthumb \
   -mabi=aapcs-linux \
   -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
+  -D__SAMD21G18A__ \
+  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 # All source paths should be relative to the top level.

hw/bsp/metro_m4_express/board.mk

@@ -1,11 +1,12 @@
 CFLAGS += \
-  -D__SAMD51J19A__ \
+  -flto \
   -mthumb \
   -mabi=aapcs-linux \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -D__SAMD51J19A__ \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
 CFLAGS += -Wno-error=undef

src/portable/nxp/lpc18_43/hal_lpc18_43.c → hw/bsp/mimxrt1064_evk/board.h

@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,39 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "tusb.h"
 
-#if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
+#ifndef BOARD_H_
+#define BOARD_H_
 
-#include "chip.h"
+// required since iMX RT10xx SDK include this file for board size
+#define BOARD_FLASH_SIZE (0x400000U)
 
-extern void hal_dcd_isr(uint8_t rhport);
-extern void hal_hcd_isr(uint8_t hostid);
-
-#if CFG_TUSB_RHPORT0_MODE
-void USB0_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-#endif
-
-#if CFG_TUSB_RHPORT1_MODE
-void USB1_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(1);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(1);
-  #endif
-}
-#endif
-
-#endif
+#endif /* BOARD_H_ */

hw/bsp/mimxrt1064_evk/board.mk

@@ -0,0 +1,58 @@
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-d16 \
+  -D__ARMVFP__=0 -D__ARMFPV5__=0\
+  -DCPU_MIMXRT1064DVL6A \
+  -DXIP_EXTERNAL_FLASH=1 \
+  -DXIP_BOOT_HEADER_ENABLE=1 \
+  -DCFG_TUSB_MCU=OPT_MCU_RT10XX \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs
+CFLAGS += -Wno-error=unused-parameter
+
+MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1064
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/MIMXRT1064xxxxx_flexspi_nor.ld
+
+SRC_C += \
+	$(MCU_DIR)/system_MIMXRT1064.c \
+	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
+	$(MCU_DIR)/project_template/clock_config.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(MCU_DIR)/drivers/fsl_gpio.c \
+	$(MCU_DIR)/drivers/fsl_common.c \
+	$(MCU_DIR)/drivers/fsl_lpuart.c
+
+INC += \
+	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(MCU_DIR)/project_template \
+
+SRC_S += $(MCU_DIR)/gcc/startup_MIMXRT1064.S
+
+# For TinyUSB port source
+VENDOR = nxp
+CHIP_FAMILY = transdimension
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM7
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1064xxx6A
+JLINK_IF = swd
+
+# flash using pyocd
+#flash: $(BUILD)/$(BOARD)-firmware.hex
+#	pyocd flash -t mimxrt1050_quadspi $<
+
+flash: $(BUILD)/$(BOARD)-firmware.bin
+	cp $< /media/$(USER)/RT1064-EVK/

hw/bsp/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1064_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+            .sflashPadType = kSerialFlash_4Pads,
+            .serialClkFreq = kFlexSpiSerialClk_100MHz,
+            .sflashA1Size  = 8u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 256u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */

hw/bsp/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h

@@ -0,0 +1,268 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_120MHz = 7,
+    kFlexSpiSerialClk_133MHz = 8,
+    kFlexSpiSerialClk_166MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */

hw/bsp/mimxrt1064_evk/mimxrt1064_evk.c

@@ -0,0 +1,184 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_iomuxc.h"
+#include "fsl_clock.h"
+#include "fsl_lpuart.h"
+
+#include "clock_config.h"
+
+#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              GPIO1
+#define LED_PIN               9
+#define LED_STATE_ON          0
+
+// SW8 button
+#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           GPIO5
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART1
+#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
+#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
+
+const uint8_t dcd_data[] = { 0x00 };
+
+void board_init(void)
+{
+  // Init clock
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+
+  // Enable IOCON clock
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+//  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // LED
+  IOMUXC_SetPinMux( LED_PINMUX, 0U);
+  IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
+
+  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
+  GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
+  board_led_write(true);
+
+  // Button
+  IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
+  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
+
+  // UART
+  IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
+  IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
+  IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
+  IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+  LPUART_Init(UART_PORT, &uart_config, (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U));
+
+  //------------- USB0 -------------//
+  // Clock
+  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+  CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
+
+  USBPHY_Type* usb_phy = USBPHY1;
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  usb_phy->PWD = 0;
+
+  // TX Timing
+  uint32_t phytx = usb_phy->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  usb_phy->TX = phytx;
+
+  // USB1
+//  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+//  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
+}
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB_OTG1_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
+void USB_OTG2_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    tuh_isr(1);
+  #endif
+
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+    tud_isr(1);
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  // active low
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  LPUART_ReadBlocking(UART_PORT, buf, len);
+  return len;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif

hw/bsp/ngx4330/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
@@ -15,9 +16,6 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
 
-# TODO remove later
-SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
-
 SRC_C += \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
@@ -32,7 +30,7 @@ INC += \
 
 # For TinyUSB port source
 VENDOR = nxp
-CHIP_FAMILY = lpc18_43
+CHIP_FAMILY = transdimension
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4

hw/bsp/ngx4330/ngx4330.c

@@ -164,19 +164,19 @@ void board_init(void)
 #if CFG_TUSB_RHPORT0_MODE
   Chip_USB0_Init();
 
-  // Reset controller
-  LPC_USB0->USBCMD_D |= 0x02;
-  while( LPC_USB0->USBCMD_D & 0x02 ) {}
-
-  // Set mode
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-
-    LPC_USB0->PORTSC1_D |= (1<<24); // FIXME force full speed for debugging
-  #else // TODO OTG
-    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
-    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-  #endif
+//  // Reset controller
+//  LPC_USB0->USBCMD_D |= 0x02;
+//  while( LPC_USB0->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+//    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//
+//    LPC_USB0->PORTSC1_D |= (1<<24); // FIXME force full speed for debugging
+//  #else // TODO OTG
+//    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
+//    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+//  #endif
 #endif
 
   /* USB1
@@ -200,25 +200,50 @@ void board_init(void)
 #if CFG_TUSB_RHPORT1_MODE
   Chip_USB1_Init();
 
-  // Reset controller
-  LPC_USB1->USBCMD_D |= 0x02;
-  while( LPC_USB1->USBCMD_D & 0x02 ) {}
-
-  // Set mode
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
-  #endif
-
-  // USB1 as fullspeed
-  LPC_USB1->PORTSC1_D |= (1<<24);
+//  // Reset controller
+//  LPC_USB1->USBCMD_D |= 0x02;
+//  while( LPC_USB1->USBCMD_D & 0x02 ) {}
+//
+//  // Set mode
+//  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+//    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+//  #else // TODO OTG
+//    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+//  #endif
+//
+//  // USB1 as fullspeed
+//  LPC_USB1->PORTSC1_D |= (1<<24);
 
 //	Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 6);							/* GPIO5[6] = USB1_PWR_EN */
 //	Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 6, true);							/* GPIO5[6] output high */
 #endif
 }
 
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    tuh_isr(0);
+  #endif
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+    tud_isr(0);
+  #endif
+}
+
+void USB1_IRQHandler(void)
+{
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    tuh_isr(1);
+  #endif
+
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+    tud_isr(1);
+  #endif
+}
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

hw/bsp/nrf52840_mdk_dongle/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \

hw/bsp/pca10056/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \

hw/bsp/pca10059/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \

hw/bsp/pca10100/board.mk

@@ -1,4 +1,5 @@
 CFLAGS += \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \

hw/bsp/pyboardv11/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=12000000 \
-  -DSTM32F405xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F405xx \
+  -DHSE_VALUE=12000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver

hw/bsp/spresense/board.mk

@@ -1,12 +1,3 @@
-SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
-
-INC += \
-	$(SPRESENSE_SDK)/nuttx/include \
-	$(SPRESENSE_SDK)/nuttx/arch \
-	$(SPRESENSE_SDK)/nuttx/arch/chip \
-	$(SPRESENSE_SDK)/sdk/bsp/include \
-	$(SPRESENSE_SDK)/sdk/bsp/include/sdk \
-
 CFLAGS += \
 	-DCONFIG_WCHAR_BUILTIN \
 	-DCONFIG_HAVE_DOUBLE \
@@ -23,6 +14,15 @@ CFLAGS += \
 	-fomit-frame-pointer \
 	-DCFG_TUSB_MCU=OPT_MCU_CXD56 \
 
+SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
+
+INC += \
+	$(SPRESENSE_SDK)/nuttx/include \
+	$(SPRESENSE_SDK)/nuttx/arch \
+	$(SPRESENSE_SDK)/nuttx/arch/chip \
+	$(SPRESENSE_SDK)/sdk/bsp/include \
+	$(SPRESENSE_SDK)/sdk/bsp/include/sdk \
+
 LIBS += \
 	$(SPRESENSE_SDK)/sdk/libs/libapps.a \
 	$(SPRESENSE_SDK)/sdk/libs/libsdk.a \

hw/bsp/stm32f070rbnucleo/board.mk

@@ -1,13 +1,14 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32F070xB \
-	-mthumb \
-	-mabi=aapcs-linux \
-	-mcpu=cortex-m0 \
-	-mfloat-abi=soft \
-	-nostdlib -nostartfiles \
-	-DCFG_EXAMPLE_MSC_READONLY \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32F0
+  -flto \
+  -mthumb \
+  -mabi=aapcs-linux \
+  -mcpu=cortex-m0 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DHSE_VALUE=8000000 \
+  -DSTM32F070xB \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
@@ -19,21 +20,21 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F0xx
 LD_FILE = hw/bsp/$(BOARD)/stm32F070rbtx_flash.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32f0xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_uart.c
+  $(ST_CMSIS)/Source/Templates/system_stm32f0xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_gpio.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_uart.c
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32f072disco/board.mk

@@ -1,13 +1,14 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32F072xB \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m0 \
-	-mfloat-abi=soft \
-	-nostdlib -nostartfiles \
-	-DCFG_EXAMPLE_MSC_READONLY \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32F0
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DSTM32F072xB \
+  -DHSE_VALUE=8000000 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
@@ -19,22 +20,22 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F0xx
 LD_FILE = hw/bsp/$(BOARD)/STM32F072RBTx_FLASH.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32f0xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_uart.c
+  $(ST_CMSIS)/Source/Templates/system_stm32f0xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_gpio.c \
+  $(ST_HAL_DRIVER)/Src/stm32f0xx_hal_uart.c
 
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32f103bluepill/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32F103xB \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m3 \
-	-mfloat-abi=soft \
-	-nostdlib -nostartfiles \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32F1
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m3 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DSTM32F103xB \
+  -DHSE_VALUE=8000000 \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F1
 
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=unused-parameter
@@ -18,21 +19,21 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F1xx
 LD_FILE = hw/bsp/$(BOARD)/STM32F103XB_FLASH.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32f1xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32f1xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32f1xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f1xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32f1xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f1xx_hal_gpio.c
+  $(ST_CMSIS)/Source/Templates/system_stm32f1xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32f1xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32f1xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f1xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32f1xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f1xx_hal_gpio.c
 
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32f207nucleo/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32F207xx \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m3 \
-	-mfloat-abi=soft \
-	-nostdlib -nostartfiles \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32F2
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m3 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DSTM32F207xx \
+  -DHSE_VALUE=8000000 \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=sign-compare
@@ -18,21 +19,21 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F2xx
 LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32f2xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32f2xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32f2xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f2xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32f2xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f2xx_hal_gpio.c
+  $(ST_CMSIS)/Source/Templates/system_stm32f2xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32f2xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32f2xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f2xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32f2xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f2xx_hal_gpio.c
 
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32f303disco/board.mk

@@ -1,13 +1,14 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32F303xC \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
-	-nostdlib -nostartfiles \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32F3
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DSTM32F303xC \
+  -DHSE_VALUE=8000000 \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F3
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
@@ -19,21 +20,21 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F3xx
 LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32f3xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32f3xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32f3xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f3xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32f3xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32f3xx_hal_gpio.c
+  $(ST_CMSIS)/Source/Templates/system_stm32f3xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32f3xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32f3xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f3xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32f3xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32f3xx_hal_gpio.c
 
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32f407disco/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32F407xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F407xx \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver

hw/bsp/stm32f411disco/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32F411xE \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F411xE \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver

hw/bsp/stm32f412disco/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32F412Zx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F412Zx \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 # mcu driver cause following warnings

hw/bsp/stm32f767nucleo/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32F767xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m7 \
   -mfloat-abi=hard \
   -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32F767xx \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F7
 
 # mcu driver cause following warnings

hw/bsp/stm32h743nucleo/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32H743xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m7 \
   -mfloat-abi=hard \
   -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32H743xx \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32H7
 
 # mcu driver cause following warnings

hw/bsp/stm32l0538disco/board.mk

@@ -1,13 +1,14 @@
 CFLAGS += \
-	-DHSE_VALUE=8000000 \
-	-DSTM32L053xx \
-	-mthumb \
-	-mabi=aapcs \
-	-mcpu=cortex-m0plus \
-	-mfloat-abi=soft \
-	-nostdlib -nostartfiles \
-	-DCFG_EXAMPLE_MSC_READONLY \
-	-DCFG_TUSB_MCU=OPT_MCU_STM32L0
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DSTM32L053xx \
+  -DHSE_VALUE=8000000 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
@@ -19,21 +20,21 @@ ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32L0xx
 LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
 
 SRC_C += \
-	$(ST_CMSIS)/Source/Templates/system_stm32l0xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32l0xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32l0xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32l0xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32l0xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32l0xx_hal_gpio.c
+  $(ST_CMSIS)/Source/Templates/system_stm32l0xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32l0xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32l0xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32l0xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32l0xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32l0xx_hal_gpio.c
 
 SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
 
 INC += \
-	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
 
 # For TinyUSB port source
 VENDOR = st

hw/bsp/stm32l476disco/board.mk

@@ -1,12 +1,13 @@
 CFLAGS += \
-  -DHSE_VALUE=8000000 \
-  -DSTM32L476xx \
+  -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
+  -DSTM32L476xx \
+  -DHSE_VALUE=8000000 \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L4
 
 ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32L4xx_HAL_Driver

src/device/dcd.h

@@ -88,6 +88,9 @@ typedef struct TU_ATTR_ALIGNED(4)
 // Initialize controller to device mode
 void dcd_init       (uint8_t rhport);
 
+// Interrupt Handler
+void dcd_isr        (uint8_t rhport);
+
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport);
 

src/device/usbd.h

@@ -47,6 +47,9 @@ bool tud_init (void);
 // Task function should be called in main/rtos loop
 void tud_task (void);
 
+// Interrupt handler, name alias to DCD
+#define tud_isr   dcd_isr
+
 // Check if device is connected and configured
 bool tud_mounted(void);
 

src/host/ehci/ehci.c

@@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr );
 
   // Remove from all interval period list
-  for(uint8_t i = 0; i < TU_ARRAY_SZIE(ehci_data.period_head_arr); i++)
+  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++)
   {
     list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr);
   }
@@ -623,7 +623,7 @@ static void xfer_error_isr(uint8_t hostid)
 }
 
 //------------- Host Controller Driver's Interrupt Handler -------------//
-void hal_hcd_isr(uint8_t rhport)
+void hcd_isr(uint8_t rhport)
 {
   ehci_registers_t* regs = ehci_data.regs;
 

src/host/hcd.h

@@ -87,6 +87,7 @@ enum {
 // HCD API
 //--------------------------------------------------------------------+
 bool hcd_init(void);
+void hcd_isr(uint8_t hostid);
 void hcd_int_enable (uint8_t rhport);
 void hcd_int_disable(uint8_t rhport);
 

src/host/ohci/ohci.c

@@ -599,7 +599,7 @@ static void done_queue_isr(uint8_t hostid)
   }
 }
 
-void hal_hcd_isr(uint8_t hostid)
+void hcd_isr(uint8_t hostid)
 {
   uint32_t const int_en     = OHCI_REG->interrupt_enable;
   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;

src/host/usbh.c

@@ -95,7 +95,7 @@ static host_class_driver_t const usbh_class_drivers[] =
   #endif
 };
 
-enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SZIE(usbh_class_drivers) };
+enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION

src/host/usbh.h

@@ -68,6 +68,9 @@ typedef struct {
 //--------------------------------------------------------------------+
 void tuh_task(void);
 
+// Interrupt handler, name alias to HCD
+#define tuh_isr   hcd_isr
+
 tusb_device_state_t tuh_device_get_state (uint8_t dev_addr);
 static inline bool tuh_device_is_configured(uint8_t dev_addr)
 {

src/portable/nxp/lpc17_40/dcd_lpc17_40.c

@@ -495,7 +495,7 @@ static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
 }
 
 // main USB IRQ handler
-void hal_dcd_isr(uint8_t rhport)
+void dcd_isr(uint8_t rhport)
 {
   uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
   LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt

src/portable/nxp/lpc17_40/hal_lpc17_40.c → src/portable/nxp/lpc17_40/hcd_lpc17_40.c

@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,27 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
+#include "tusb_option.h"
 
 #if (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
 
-extern void hal_hcd_isr(uint8_t hostid);
-extern void hal_dcd_isr(uint8_t rhport);
-
-void USB_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-
-//FIXME move later
 void hcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
@@ -57,5 +42,5 @@ void hcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_IRQn);
 }
 
-
 #endif
+

src/portable/nxp/lpc18_43/dcd_lpc18_43.c

@@ -1,356 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "device/dcd.h"
-#include "dcd_lpc18_43.h"
-
-#include "chip.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-#define QHD_MAX          12
-#define QTD_NEXT_INVALID 0x01
-
-typedef struct {
-  // Must be at 2K alignment
-  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
-}dcd_data_t;
-
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
-#endif
-
-static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
-
-static dcd_data_t* const dcd_data_ptr[2] =
-{
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  &dcd_data0,
-#else
-  NULL,
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  &dcd_data1
-#else
-  NULL
-#endif
-};
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must bechanged from the control type to any other
-  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-
-  // USB0 has 5 but USB1 only has 3 non-control endpoints
-  for( int i=1; i < (rhport ? 6 : 4); i++)
-  {
-    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
-  }
-
-  //------------- Clear All Registers -------------//
-  lpc_usb->ENDPTNAK       = lpc_usb->ENDPTNAK;
-  lpc_usb->ENDPTNAKEN     = 0;
-  lpc_usb->USBSTS_D       = lpc_usb->USBSTS_D;
-  lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
-  lpc_usb->ENDPTCOMPLETE  = lpc_usb->ENDPTCOMPLETE;
-
-  while (lpc_usb->ENDPTPRIME);
-  lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
-  while (lpc_usb->ENDPTFLUSH);
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-	p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
-	p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
-	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-	p_dcd->qhd[0].int_on_setup = 1; // OUT only
-}
-
-void dcd_init(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
-  lpc_usb->USBSTS_D  = lpc_usb->USBSTS_D;
-  lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
-
-  lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
-  lpc_usb->USBCMD_D |= TU_BIT(0); // connect
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-  (void) rhport;
-  (void) config_num;
-  // nothing to do
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-// index to bit position in register
-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
-{
-  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
-}
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0]   = (uint32_t) data_ptr;
-    for(uint8_t i=1; i<5; i++)
-    {
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
-  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  // TODO not support ISO yet
-  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
-  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  // USB0 has 5, USB1 has 3 non-control endpoints
-  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  // Enable EP Control
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
-
-  return true;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-  //------------- Prepare qtd -------------//
-  qtd_init(p_qtd, buffer, total_bytes);
-  p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
-
-  // start transfer
-  LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void hal_dcd_isr(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-
-  uint32_t const int_enable = lpc_usb->USBINTR_D;
-  uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
-  lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;// disabled interrupt sources
-
-
-  if (int_status & INT_MASK_RESET)
-  {
-    bus_reset(rhport);
-    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
-  }
-
-  if (int_status & INT_MASK_SUSPEND)
-  {
-    if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-      }
-    }
-  }
-
-  // TODO disconnection does not generate interrupt !!!!!!
-//	if (int_status & INT_MASK_PORT_CHANGE)
-//	{
-//	  if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
-//	  {
-//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
-//      dcd_event_handler(&event, true);
-//	  }
-//	}
-
-  if (int_status & INT_MASK_USB)
-  {
-    uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
-    lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
-
-    if (lpc_usb->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
-
-      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
-    }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
-      {
-        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
-        {
-          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-          dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
-              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
-        }
-      }
-    }
-  }
-
-  if (int_status & INT_MASK_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  if (int_status & INT_MASK_NAK) {}
-  if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
-}
-
-#endif

src/portable/nxp/lpc18_43/dcd_lpc18_43.h

@@ -1,144 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc143xx LPC43xx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC43XX_H_
-#define _TUSB_DCD_LPC43XX_H_
-
-#include "common/tusb_common.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-/*---------- ENDPTCTRL ----------*/
-enum {
-  ENDPTCTRL_MASK_STALL          = TU_BIT(0),
-  ENDPTCTRL_MASK_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
-  ENDPTCTRL_MASK_TOGGLE_RESET   = TU_BIT(6),
-  ENDPTCTRL_MASK_ENABLE         = TU_BIT(7)
-};
-
-/*---------- USBCMD ----------*/
-enum {
-  USBCMD_MASK_RUN_STOP         = TU_BIT(0),
-  USBCMD_MASK_RESET            = TU_BIT(1),
-  USBCMD_MASK_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_MASK_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-};
-// Interrupt Threshold bit 23:16
-
-/*---------- USBSTS, USBINTR ----------*/
-enum {
-  INT_MASK_USB         = TU_BIT(0),
-  INT_MASK_ERROR       = TU_BIT(1),
-  INT_MASK_PORT_CHANGE = TU_BIT(2),
-  INT_MASK_RESET       = TU_BIT(6),
-  INT_MASK_SOF         = TU_BIT(7),
-  INT_MASK_SUSPEND     = TU_BIT(8),
-  INT_MASK_NAK         = TU_BIT(16)
-};
-
-//------------- PORTSC -------------//
-enum {
-  PORTSC_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
-  PORTSC_FORCE_PORT_RESUME_MASK      = TU_BIT(6),
-  PORTSC_SUSPEND_MASK                = TU_BIT(7)
-};
-
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 0  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //------------- DCD Area -------------//
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-  uint32_t                         : 0  ;
-
-  // Word 1: Current qTD Pointer
-	volatile uint32_t qtd_addr;
-
-	// Word 2-9: Transfer Overlay
-	volatile dcd_qtd_t qtd_overlay;
-
-	// Word 10-11: Setup request (control OUT only)
-	volatile tusb_control_request_t setup_request;
-
-	//--------------------------------------------------------------------+
-  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
-	/// thus there are 16 bytes padding free that we can make use of.
-  //--------------------------------------------------------------------+
-	uint8_t reserved[16];
-}  dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC43XX_H_ */
-
-/** @} */

src/portable/nxp/transdimension/dcd_transdimension.c

@@ -0,0 +1,530 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
+                                CFG_TUSB_MCU == OPT_MCU_LPC43XX || \
+                                CFG_TUSB_MCU == OPT_MCU_RT10XX)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "device/dcd.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_RT10XX
+  #include "fsl_device_registers.h"
+  #define   DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
+  IRQn_Type DCD_IRQn[] =  { USB_OTG1_IRQn, USB_OTG2_IRQn };
+
+#else
+  #include "chip.h"
+  #define   DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
+  IRQn_Type DCD_IRQn[] =  { USB0_IRQn, USB1_IRQn };
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// ENDPTCTRL
+enum {
+  ENDPTCTRL_STALL          = TU_BIT(0),
+  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
+  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
+  ENDPTCTRL_ENABLE         = TU_BIT(7)
+};
+
+// USBCMD
+enum {
+  USBCMD_RUN_STOP         = TU_BIT(0),
+  USBCMD_RESET            = TU_BIT(1),
+  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
+};
+// Interrupt Threshold bit 23:16
+
+// USBSTS, USBINTR
+enum {
+  INTR_USB         = TU_BIT(0),
+  INTR_ERROR       = TU_BIT(1),
+  INTR_PORT_CHANGE = TU_BIT(2),
+  INTR_RESET       = TU_BIT(6),
+  INTR_SOF         = TU_BIT(7),
+  INTR_SUSPEND     = TU_BIT(8),
+  INTR_NAK         = TU_BIT(16)
+};
+
+// PORTSC1
+enum {
+  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
+  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
+  PORTSC1_SUSPEND                = TU_BIT(7),
+  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
+};
+
+// OTGSC
+enum {
+  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
+  OTGSC_VBUS_CHARGE             = TU_BIT(1),
+//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
+  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
+  OTGSC_DATA_PULSING            = TU_BIT(4),
+  OTGSC_ID_PULLUP               = TU_BIT(5),
+//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
+//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
+  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
+  OTGSC_A_VBUS_VALID            = TU_BIT(9),
+  OTGSC_A_SESSION_VALID         = TU_BIT(10),
+  OTGSC_B_SESSION_VALID         = TU_BIT(11),
+  OTGSC_B_SESSION_END           = TU_BIT(12),
+  OTGSC_1MS_TOGGLE              = TU_BIT(13),
+  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
+};
+
+// USBMode
+enum {
+  USBMODE_CM_DEVICE = 2,
+  USBMODE_CM_HOST   = 3,
+
+  USBMODE_SLOM = TU_BIT(3),
+  USBMODE_SDIS = TU_BIT(4),
+
+  USBMODE_VBUS_POWER_SELCT = TU_BIT(5), // Enable for LPC18XX/43XX in host most only
+};
+
+// Device Registers
+typedef struct
+{
+  //------------- ID + HW Parameter Registers-------------//
+  __I  uint32_t TU_RESERVED[64];    ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
+
+  //------------- Capability Registers-------------//
+  __I  uint8_t  CAPLENGTH;          ///< Capability Registers Length
+  __I  uint8_t  TU_RESERVED[1];
+  __I  uint16_t HCIVERSION;         ///< Host Controller Interface Version
+
+  __I  uint32_t HCSPARAMS;          ///< Host Controller Structural Parameters
+  __I  uint32_t HCCPARAMS;          ///< Host Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[5];
+
+  __I  uint16_t DCIVERSION;         ///< Device Controller Interface Version
+  __I  uint8_t  TU_RESERVED[2];
+
+  __I  uint32_t DCCPARAMS;          ///< Device Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[6];
+
+  //------------- Operational Registers -------------//
+  __IO uint32_t USBCMD;             ///< USB Command Register
+  __IO uint32_t USBSTS;             ///< USB Status Register
+  __IO uint32_t USBINTR;            ///< Interrupt Enable Register
+  __IO uint32_t FRINDEX;            ///< USB Frame Index
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t DEVICEADDR;         ///< Device Address
+  __IO uint32_t ENDPTLISTADDR;      ///< Endpoint List Address
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t BURSTSIZE;          ///< Programmable Burst Size
+  __IO uint32_t TXFILLTUNING;       ///< TX FIFO Fill Tuning
+       uint32_t TU_RESERVED[4];
+  __IO uint32_t ENDPTNAK;           ///< Endpoint NAK
+  __IO uint32_t ENDPTNAKEN;         ///< Endpoint NAK Enable
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t PORTSC1;            ///< Port Status & Control
+  __I  uint32_t TU_RESERVED[7];
+  __IO uint32_t OTGSC;              ///< On-The-Go Status & control
+  __IO uint32_t USBMODE;            ///< USB Device Mode
+  __IO uint32_t ENDPTSETUPSTAT;     ///< Endpoint Setup Status
+  __IO uint32_t ENDPTPRIME;         ///< Endpoint Prime
+  __IO uint32_t ENDPTFLUSH;         ///< Endpoint Flush
+  __I  uint32_t ENDPTSTAT;          ///< Endpoint Status
+  __IO uint32_t ENDPTCOMPLETE;      ///< Endpoint Complete
+  __IO uint32_t ENDPTCTRL[8];       ///< Endpoint Control 0 - 7
+} dcd_registers_t;
+
+
+// Queue Transfer Descriptor
+typedef struct
+{
+  // Word 0: Next QTD Pointer
+  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
+
+  // Word 1: qTQ Token
+  uint32_t                      : 3  ;
+  volatile uint32_t xact_err    : 1  ;
+  uint32_t                      : 1  ;
+  volatile uint32_t buffer_err  : 1  ;
+  volatile uint32_t halted      : 1  ;
+  volatile uint32_t active      : 1  ;
+  uint32_t                      : 2  ;
+  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
+  uint32_t                      : 3  ;
+  uint32_t int_on_complete      : 1  ;
+  volatile uint32_t total_bytes : 15 ;
+  uint32_t                      : 0  ;
+
+  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
+
+  //------------- DCD Area -------------//
+  uint16_t expected_bytes;
+  uint8_t reserved[2];
+} dcd_qtd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
+
+// Queue Head
+typedef struct
+{
+  // Word 0: Capabilities and Characteristics
+  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
+  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
+  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
+  uint32_t                         : 2  ;
+  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
+  uint32_t iso_mult                : 2  ; ///<
+  uint32_t                         : 0  ;
+
+  // Word 1: Current qTD Pointer
+	volatile uint32_t qtd_addr;
+
+	// Word 2-9: Transfer Overlay
+	volatile dcd_qtd_t qtd_overlay;
+
+	// Word 10-11: Setup request (control OUT only)
+	volatile tusb_control_request_t setup_request;
+
+	//--------------------------------------------------------------------+
+  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
+	/// thus there are 16 bytes padding free that we can make use of.
+  //--------------------------------------------------------------------+
+	uint8_t reserved[16];
+}  dcd_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Variables
+//--------------------------------------------------------------------+
+
+#define QHD_MAX          12
+#define QTD_NEXT_INVALID 0x01
+
+typedef struct {
+  // Must be at 2K alignment
+  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
+}dcd_data_t;
+
+static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
+static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+
+/// follows LPC43xx User Manual 23.10.3
+static void bus_reset(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = DCD_REGS[rhport];
+
+  // The reset value for all endpoint types is the control endpoint. If one endpoint
+  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
+  // endpoint type of the unused direction must bechanged from the control type to any other
+  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
+  // for the data PID tracking on the active endpoint.
+
+  // USB0 has 5 but USB1 only has 3 non-control endpoints
+  for( int i=1; i < (rhport ? 6 : 4); i++)
+  {
+    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+  }
+
+  //------------- Clear All Registers -------------//
+  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
+  dcd_reg->ENDPTNAKEN     = 0;
+  dcd_reg->USBSTS         = dcd_reg->USBSTS;
+  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
+
+  while (dcd_reg->ENDPTPRIME);
+  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
+  while (dcd_reg->ENDPTFLUSH);
+
+  // read reset bit in portsc
+
+  //------------- Queue Head & Queue TD -------------//
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
+	_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
+	_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
+	_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
+
+	_dcd_data.qhd[0].int_on_setup = 1; // OUT only
+}
+
+void dcd_init(uint8_t rhport)
+{
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
+
+  // Reset controller
+  dcd_reg->USBCMD |= USBCMD_RESET;
+  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
+
+  // Set mode to device, must be set immediately after reset
+  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
+
+  // TODO Force fullspeed on non-highspeed port
+  // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+
+  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
+  dcd_reg->USBSTS  = dcd_reg->USBSTS;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
+
+  dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
+  dcd_reg->USBCMD |= TU_BIT(0); // connect
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(DCD_IRQn[rhport]);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(DCD_IRQn[rhport]);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  // Response with status first before changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+  // nothing to do
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// HELPER
+//--------------------------------------------------------------------+
+// index to bit position in register
+static inline uint8_t ep_idx2bit(uint8_t ep_idx)
+{
+  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
+}
+
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
+{
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next        = QTD_NEXT_INVALID;
+  p_qtd->active      = 1;
+  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+  if (data_ptr != NULL)
+  {
+    p_qtd->buffer[0]   = (uint32_t) data_ptr;
+    for(uint8_t i=1; i<5; i++)
+    {
+      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  // data toggle also need to be reset
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  // TODO not support ISO yet
+  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+
+  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  // USB0 has 5, USB1 has 3 non-control endpoints
+  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
+
+  //------------- Prepare Queue Head -------------//
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
+
+  p_qhd->zero_length_termination = 1;
+  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
+
+  // Enable EP Control
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
+  }
+
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+  //------------- Prepare qtd -------------//
+  qtd_init(p_qtd, buffer, total_bytes);
+  p_qtd->int_on_complete = true;
+  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+
+  // start transfer
+  DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_isr(uint8_t rhport)
+{
+  dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
+
+  uint32_t const int_enable = dcd_reg->USBINTR;
+  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
+  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
+
+  // disabled interrupt sources
+  if (int_status == 0) return;
+
+  if (int_status & INTR_RESET)
+  {
+    bus_reset(rhport);
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (int_status & INTR_SUSPEND)
+  {
+    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
+      {
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+      }
+    }
+  }
+
+  // TODO disconnection does not generate interrupt !!!!!!
+//	if (int_status & INTR_PORT_CHANGE)
+//	{
+//	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
+//	  {
+//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
+//      dcd_event_handler(&event, true);
+//	  }
+//	}
+
+  if (int_status & INTR_USB)
+  {
+    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
+    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
+
+    if (dcd_reg->ENDPTSETUPSTAT)
+    {
+      //------------- Set up Received -------------//
+      // 23.10.10.2 Operational model for setup transfers
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge
+
+      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true);
+    }
+
+    if ( edpt_complete )
+    {
+      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
+      {
+        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
+        {
+          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+          dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
+              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
+          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
+        }
+      }
+    }
+  }
+
+  if (int_status & INTR_SOF)
+  {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (int_status & INTR_NAK) {}
+  if (int_status & INTR_ERROR) TU_ASSERT(false, );
+}
+
+#endif

src/tusb_option.h

@@ -37,40 +37,42 @@
  *  @{ */
 
 // LPC
-#define OPT_MCU_LPC11UXX        1 ///< NXP LPC11Uxx
-#define OPT_MCU_LPC13XX         2 ///< NXP LPC13xx
-#define OPT_MCU_LPC15XX         3 ///< NXP LPC15xx
-#define OPT_MCU_LPC175X_6X      4 ///< NXP LPC175x, LPC176x
-#define OPT_MCU_LPC177X_8X      5 ///< NXP LPC177x, LPC178x
-#define OPT_MCU_LPC18XX         6 ///< NXP LPC18xx
-#define OPT_MCU_LPC40XX         7 ///< NXP LPC40xx
-#define OPT_MCU_LPC43XX         8 ///< NXP LPC43xx
-#define OPT_MCU_LPC51UXX        9 ///< NXP LPC51U6x
-#define OPT_MCU_LPC54XXX       10 ///< NXP LPC54xxx
-#define OPT_MCU_LPC55XX        11 ///< NXP LPC55xx
+#define OPT_MCU_LPC11UXX            1 ///< NXP LPC11Uxx
+#define OPT_MCU_LPC13XX             2 ///< NXP LPC13xx
+#define OPT_MCU_LPC15XX             3 ///< NXP LPC15xx
+#define OPT_MCU_LPC175X_6X          4 ///< NXP LPC175x, LPC176x
+#define OPT_MCU_LPC177X_8X          5 ///< NXP LPC177x, LPC178x
+#define OPT_MCU_LPC18XX             6 ///< NXP LPC18xx
+#define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx
+#define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx
+#define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x
+#define OPT_MCU_LPC54XXX           10 ///< NXP LPC54xxx
+#define OPT_MCU_LPC55XX            11 ///< NXP LPC55xx
 
 // NRF
-#define OPT_MCU_NRF5X         100 ///< Nordic nRF5x series
+#define OPT_MCU_NRF5X             100 ///< Nordic nRF5x series
 
 // SAM
-#define OPT_MCU_SAMD21        200 ///< MicroChip SAMD21
-#define OPT_MCU_SAMD51        201 ///< MicroChip SAMD51
+#define OPT_MCU_SAMD21            200 ///< MicroChip SAMD21
+#define OPT_MCU_SAMD51            201 ///< MicroChip SAMD51
 
 // STM32
-#define OPT_MCU_STM32F0       300 ///< ST STM32F0
-#define OPT_MCU_STM32F1       301 ///< ST STM32F1
-#define OPT_MCU_STM32F2       302 ///< ST STM32F2
-#define OPT_MCU_STM32F3       303 ///< ST STM32F3
-#define OPT_MCU_STM32F4       304 ///< ST STM32F4
-#define OPT_MCU_STM32F7       305 ///< ST STM32F7
-#define OPT_MCU_STM32H7       306 ///< ST STM32H7
-#define OPT_MCU_STM32L0       307 ///< ST STM32L0
-#define OPT_MCU_STM32L1       308 ///< ST STM32L1
-#define OPT_MCU_STM32L4       309 ///< ST STM32L4
-
-#define OPT_MCU_CXD56         400 ///< SONY CXD56
-
-#define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config
+#define OPT_MCU_STM32F0           300 ///< ST STM32F0
+#define OPT_MCU_STM32F1           301 ///< ST STM32F1
+#define OPT_MCU_STM32F2           302 ///< ST STM32F2
+#define OPT_MCU_STM32F3           303 ///< ST STM32F3
+#define OPT_MCU_STM32F4           304 ///< ST STM32F4
+#define OPT_MCU_STM32F7           305 ///< ST STM32F7
+#define OPT_MCU_STM32H7           306 ///< ST STM32H7
+#define OPT_MCU_STM32L0           307 ///< ST STM32L0
+#define OPT_MCU_STM32L1           308 ///< ST STM32L1
+#define OPT_MCU_STM32L4           309 ///< ST STM32L4
+
+#define OPT_MCU_CXD56             400 ///< SONY CXD56
+
+#define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config
+
+#define OPT_MCU_RT10XX            700 ///< NXP iMX RT10xx
 
 /** @} */
 

test/test/device/usbd/test_usbd.c

@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 hathach for Adafruit Industries
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal

test/test/support/tusb_config.h

@@ -43,7 +43,7 @@
   #define CFG_TUSB_MCU  OPT_MCU_NRF5X
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_RT10XX
 #define CFG_TUSB_RHPORT0_MODE    (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
 #else
 #define CFG_TUSB_RHPORT0_MODE    OPT_MODE_DEVICE

tools/build_all.py

@@ -15,12 +15,17 @@ exit_status = 0
 total_time = time.monotonic()
 
 all_examples = []
-for entry in os.scandir("examples/device"):
-    if entry.is_dir():
-        all_examples.append(entry.name)
 
-# TODO update freeRTOS example to work with all boards (only nrf52840 now)
-all_examples.remove("cdc_msc_hid_freertos")
+# build all example if input not existed
+if len(sys.argv) > 1:
+    all_examples.append(sys.argv[1])
+else:
+    for entry in os.scandir("examples/device"):
+        if entry.is_dir():
+            all_examples.append(entry.name)
+
+    # TODO update freeRTOS example to work with all boards (only nrf52840 now)
+    all_examples.remove("cdc_msc_hid_freertos")
 
 all_boards = []
 for entry in os.scandir("hw/bsp"):
@@ -31,7 +36,7 @@ for entry in os.scandir("hw/bsp"):
 def build_example(example, board):
     subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True,
                    stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-    return subprocess.run("make -j 4 -C examples/device/{} BOARD={} all".format(example, board), shell=True,
+    return subprocess.run("make -j 8 -C examples/device/{} BOARD={} all".format(example, board), shell=True,
                           stdout=subprocess.PIPE, stderr=subprocess.STDOUT)