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@@ -51,6 +51,11 @@ enum
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USBD_INTENCLR_ENDISOIN_Msk | USBD_INTEN_ENDISOOUT_Msk
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};
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+enum
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+{
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+ EP_COUNT = 8
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+};
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+
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// Transfer descriptor
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typedef struct
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{
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@@ -69,36 +74,73 @@ typedef struct
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static struct
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{
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// All 8 endpoints including control IN & OUT (offset 1)
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- xfer_td_t xfer[8][2];
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+ xfer_td_t xfer[EP_COUNT][2];
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- // Only one DMA can run at a time
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- volatile bool dma_running;
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+ // Number of pending DMA that is started but not handled yet by dcd_int_handler().
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+ // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
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+ // However, in critical section with interrupt disabled, the DMA can be finished and added up
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+ // until handled by dcd_init_handler() when exiting critical section.
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+ volatile uint8_t dma_pending;
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}_dcd;
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/*------------------------------------------------------------------*/
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/* Control / Bulk / Interrupt (CBI) Transfer
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*------------------------------------------------------------------*/
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+// NVIC_GetEnableIRQ is only available in CMSIS v5
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+#ifndef NVIC_GetEnableIRQ
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+static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
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+{
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+ if ((int32_t)(IRQn) >= 0)
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+ {
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+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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+ }
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+ else
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+ {
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+ return(0U);
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+ }
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+}
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+#endif
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+
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// helper to start DMA
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static void edpt_dma_start(volatile uint32_t* reg_startep)
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{
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// Only one dma can be active
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- if ( _dcd.dma_running )
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+ if ( _dcd.dma_pending )
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{
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if (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk)
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{
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- // If called within ISR, use usbd task to defer later
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+ // Called within ISR, use usbd task to defer later
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usbd_defer_func( (osal_task_func_t) edpt_dma_start, (void*) reg_startep, true );
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return;
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}
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else
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{
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- // Otherwise simply block wait
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- while ( _dcd.dma_running ) { }
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+ if ( __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
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+ {
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+ // Called in critical section with interrupt disabled. We have to manually check
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+ // for the DMA complete by comparing current pending DMA with number of ENDED Events
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+ uint32_t ended = 0;
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+
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+ while ( _dcd.dma_pending < ((uint8_t) ended) )
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+ {
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+ ended = NRF_USBD->EVENTS_ENDISOIN + NRF_USBD->EVENTS_ENDISOOUT;
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+
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+ for (uint8_t i=0; i<EP_COUNT; i++)
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+ {
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+ ended += NRF_USBD->EVENTS_ENDEPIN[i] + NRF_USBD->EVENTS_ENDEPOUT[i];
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+ }
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+ }
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+ }else
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+ {
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+ // Called in non-critical thread-mode, should be 99% of the time.
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+ // Should be safe to blocking wait until previous DMA transfer complete
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+ while ( _dcd.dma_pending ) { }
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+ }
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}
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}
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- _dcd.dma_running = true;
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+ _dcd.dma_pending++;
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(*reg_startep) = 1;
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__ISB(); __DSB();
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@@ -107,8 +149,8 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
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// DMA is complete
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static void edpt_dma_end(void)
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{
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- TU_ASSERT(_dcd.dma_running, );
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- _dcd.dma_running = false;
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+ TU_ASSERT(_dcd.dma_pending, );
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+ _dcd.dma_pending = 0;
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}
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// helper getting td
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@@ -282,9 +324,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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if ( control_status )
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{
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- // Status Phase also require Easy DMA has to be free as well !!!!
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+ // Status Phase also requires Easy DMA has to be available as well !!!!
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+ // However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently
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+ // Therefore dma_running state will be corrected right away
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edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
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- edpt_dma_end();
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+ if (_dcd.dma_pending) _dcd.dma_pending--; // correct the dma_running++ in dma start
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// The nRF doesn't interrupt on status transmit so we queue up a success response.
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dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, false);
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Ha Thach