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@@ -0,0 +1,564 @@
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+/*
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+* The MIT License (MIT)
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+*
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+* Copyright (c) 2018, hathach (tinyusb.org)
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+* Copyright (c) 2020, HiFiPhile
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+*
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+* Permission is hereby granted, free of charge, to any person obtaining a copy
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+* of this software and associated documentation files (the "Software"), to deal
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+* in the Software without restriction, including without limitation the rights
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+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+* copies of the Software, and to permit persons to whom the Software is
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+* furnished to do so, subject to the following conditions:
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+*
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+* The above copyright notice and this permission notice shall be included in
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+* all copies or substantial portions of the Software.
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+*
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+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+* THE SOFTWARE.
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+*
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+* This file is part of the TinyUSB stack.
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+*/
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+
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+
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+
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+#include "tusb_option.h"
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+
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+#if CFG_TUSB_MCU == OPT_MCU_SAME70
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+
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+#include "device/dcd.h"
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+
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+#include "sam.h"
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+
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+#include "SEGGER_RTT.h"
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+//--------------------------------------------------------------------+
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+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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+//--------------------------------------------------------------------+
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+
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+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
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+// We disable SOF for now until needed later on
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+#ifndef USE_SOF
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+# define USE_SOF 0
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+#endif
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+
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+#ifndef USBHS_RAM_ADDR
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+# define USBHS_RAM_ADDR 0xA0100000u
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+#endif
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+
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+#define get_ep_fifo_ptr(ep, scale) (((volatile TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
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+
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+#define EP_MAX 10
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+
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+typedef struct {
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+ uint8_t * buffer;
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+ uint16_t total_len;
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+ uint16_t queued_len;
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+ uint16_t max_packet_size;
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+ uint8_t interval;
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+} xfer_ctl_t;
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+
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+xfer_ctl_t xfer_status[EP_MAX+1];
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+
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+static const tusb_desc_endpoint_t ep0_desc =
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+{
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+ .bLength = sizeof(tusb_desc_endpoint_t),
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+ .bDescriptorType = TUSB_DESC_ENDPOINT,
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+
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+ .bEndpointAddress = 0x00,
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+ .bmAttributes = { .xfer = TUSB_XFER_CONTROL },
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+ .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE },
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+ .bInterval = 0
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+};
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+
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+static tusb_speed_t get_speed(void);
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+static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
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+//------------------------------------------------------------------
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+// Device API
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+//------------------------------------------------------------------
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+
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+// Initialize controller to device mode
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+void dcd_init (uint8_t rhport)
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+{
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+ // Enable USBPLL
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+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
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+ // Wait until USB UTMI stabilize
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+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));
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+ // Enable USB FS clk
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+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
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+ PMC->PMC_SCER = PMC_SCER_USBCLK;
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+ dcd_connect(rhport);
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+}
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+
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+// Enable device interrupt
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+void dcd_int_enable (uint8_t rhport)
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+{
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+ (void) rhport;
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+ NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
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+}
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+
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+// Disable device interrupt
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+void dcd_int_disable (uint8_t rhport)
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+{
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+ (void) rhport;
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+ NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
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+}
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+
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+// Receive Set Address request, mcu port must also include status IN response
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+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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+{
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+ (void) rhport;
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+ // Set the address but keep it disabled for now. It should be enabled
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+ // only after the ack to the host completes.
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+ USBHS->USBHS_DEVCTRL &= ~(USBHS_DEVCTRL_UADD_Msk | USBHS_DEVCTRL_ADDEN);
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+ USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(dev_addr);
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+
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+ // Respond with status
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+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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+}
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+
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+// Wake up host
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+void dcd_remote_wakeup (uint8_t rhport)
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+{
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+ (void) rhport;
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+ USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
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+}
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+
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+// Connect by enabling internal pull-up resistor on D+/D-
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+void dcd_connect(uint8_t rhport)
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+{
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+ uint32_t irq_state = __get_PRIMASK();
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+ __disable_irq();
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+ // Enable USB clock
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+ PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
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+ // Enable the USB controller in device mode
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+ USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
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+ // Wait to unfreeze clock
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+ while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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+ // Attach the device
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+ USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
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+ // Enable the End Of Reset, Suspend & Wakeup interrupts
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+ USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
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+#if USE_SOF
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+ USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES;
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+#endif
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+ // Clear the End Of Reset, SOF & Wakeup interrupts
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+ USBHS->USBHS_DEVICR = (USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_WAKEUPC);
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+ // Manually set the Suspend Interrupt
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+ USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
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+ // Ack the Wakeup Interrupt
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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+ // Freeze USB clock
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+ USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
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+ __set_PRIMASK(irq_state);
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+}
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+
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+// Disconnect by disabling internal pull-up resistor on D+/D-
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+void dcd_disconnect(uint8_t rhport)
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+{
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+ (void) rhport;
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+ uint32_t irq_state = __get_PRIMASK();
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+ __disable_irq();
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+ // Disable all endpoints
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+ USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
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+ // Unfreeze USB clock
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+ USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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+ // Wait to unfreeze clock
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+ while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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+ // Clear all the pending interrupts
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
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+ // Disable all interrupts
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+ USBHS->USBHS_DEVIDR = USBHS_DEVCTRL_UADD_Msk;
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+ // Detach the device
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+ USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
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+ // Disable the device address
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+ USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
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+ __set_PRIMASK(irq_state);
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+}
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+
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+static tusb_speed_t get_speed(void)
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+{
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+ switch((USBHS->USBHS_SR & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos)
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+ {
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+ case USBHS_SR_SPEED_FULL_SPEED_Val:
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+ default:
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+ return TUSB_SPEED_FULL;
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+ case USBHS_SR_SPEED_HIGH_SPEED_Val:
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+ return TUSB_SPEED_HIGH;
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+ case USBHS_SR_SPEED_LOW_SPEED_Val:
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+ return TUSB_SPEED_LOW;
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+ }
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+}
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+
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+static void dcd_ep_handler(uint8_t ep_ix)
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+{
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+ uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix] & USBHS->USBHS_DEVEPTIMR[ep_ix];
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+ uint32_t dev_ctrl = USBHS->USBHS_DEVCTRL;
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+ uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
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+ USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
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+ SEGGER_RTT_printf(0, "ep: %u %u %u \r\n", ep_ix, count, int_status);
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+ if(ep_ix == 0U)
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+ {
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+ if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI) {
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+
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+ // Get 8-bit access to endpoint 0 FIFO from USB RAM address
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+ volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
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+ SCB_InvalidateDCache_by_Addr((uint32_t *) ptr, 8);
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+ dcd_event_setup_received(0, (uint8_t*)ptr, true);
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+
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+ // Acknowledge the interrupt
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+ USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
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+ }
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+ if (int_status & USBHS_DEVEPTISR_RXOUTI) {
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+ // Disable the interrupt
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+ //USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
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+
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+ xfer_ctl_t *xfer = &xfer_status[0];
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+
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+ if(count)
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+ {
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+ volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
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+ for (int i = 0; i < count; i++) {
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+ xfer->buffer[xfer->queued_len + i] = ptr[i];
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+ }
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+ xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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+ }
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+
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+ USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
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+
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+ if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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+ {
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+ // RX COMPLETE
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+ dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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+ xfer->queued_len = 0;
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+ SEGGER_RTT_printf(0, "rx: %u \r\n", xfer->queued_len);
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+ // Though the host could still send, we don't know.
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+ }
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+
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+
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+ }
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+ if (int_status & USBHS_DEVEPTISR_TXINI) {
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+ // Disable the interrupt
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+ USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
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+ if (!(dev_ctrl & USBHS_DEVCTRL_ADDEN) &&
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+ (dev_ctrl & USBHS_DEVCTRL_UADD_Msk) != 0U) {
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+ // Commit the pending address update. This
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+ // must be done after the ack to the host
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+ // completes else the ack will get dropped.
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+ USBHS->USBHS_DEVCTRL = dev_ctrl | USBHS_DEVCTRL_ADDEN;
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+ }
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+ xfer_ctl_t * xfer = &xfer_status[EP_MAX];
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+ if((xfer->total_len != xfer->queued_len)) // TX not complete
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+ {
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+ dcd_transmit_packet(xfer, 0);
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+ }
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+ else // TX Complete
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+ {
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+ dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
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+ }
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+ }
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+ }
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+ else
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+ {
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+ if (int_status & USBHS_DEVEPTISR_RXOUTI) {
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+ // Acknowledge the interrupt
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+ USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
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+
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+ xfer_ctl_t *xfer = &xfer_status[ep_ix];
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+
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+ if(count)
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+ {
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+ volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
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+ for (int i = 0; i < count; i++) {
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+ xfer->buffer[xfer->queued_len + i] = ptr[i];
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+ }
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+ xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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+ }
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+ // Clear the FIFO control flag to receive more data.
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+ USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
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+ if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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+ {
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+ // RX COMPLETE
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+ dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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+ xfer->queued_len = 0;
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+ // Though the host could still send, we don't know.
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+ }
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+ }
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+ if (int_status & USBHS_DEVEPTISR_TXINI) {
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+ // Acknowledge the interrupt
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+ USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
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+ xfer_ctl_t * xfer = &xfer_status[ep_ix];;
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+ if((xfer->total_len != xfer->queued_len)) // TX not complete
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+ {
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+ dcd_transmit_packet(xfer, ep_ix);
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+ }
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+ else // TX Complete
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+ {
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+ dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
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+ }
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+ }
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+ }
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+}
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+
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+void dcd_int_handler(uint8_t rhport)
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+{
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+ (void) rhport;
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+ uint32_t int_status = USBHS->USBHS_DEVISR;
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+ // End of reset interrupt
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+ if (int_status & USBHS_DEVISR_EORST) {
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+ // Unfreeze USB clock
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+ USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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+ while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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+ // Reset all endpoints
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+ for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
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+ {
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+ // Disable endpoint interrupt
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+ USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + ep_ix);
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+ // Disable endpoint and SETUP, IN or OUT interrupts
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+ USBHS->USBHS_DEVEPT &= ~ (1 << (USBHS_DEVEPT_EPEN0_Pos + ep_ix));
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+ // Free all endpoint memory
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+ USBHS->USBHS_DEVEPTCFG[ep_ix] &= ~USBHS_DEVEPTCFG_ALLOC;
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+ }
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+ dcd_edpt_open (0, &ep0_desc);
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+ // Acknowledge the End of Reset interrupt
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
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+ // Acknowledge the Wakeup interrupt
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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+ // Acknowledge the suspend interrupt
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
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+ // Enable Suspend Interrupt
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+ USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
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+
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+ dcd_event_bus_reset(rhport, get_speed(), true);
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+ }
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+ // End of Wakeup interrupt
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+ if (int_status & USBHS_DEVISR_WAKEUP) {
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+ // Unfreeze USB clock
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+ USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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+ // Wait to unfreeze clock
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+ while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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+ // Acknowledge the Wakeup interrupt
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+ USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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+ // Disable Wakeup Interrupt
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+ USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
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+ // Enable Suspend Interrupt
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+ USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
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+
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+ dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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+ }
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+ // Suspend interrupt
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+ if (int_status & USBHS_DEVISR_SUSP) {
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+ // Unfreeze USB clock
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+ USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
|
|
|
+ // Wait to unfreeze clock
|
|
|
+ while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
|
|
|
+ // Acknowledge the suspend interrupt
|
|
|
+ USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
|
|
|
+ // Disable Suspend Interrupt
|
|
|
+ USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
|
|
|
+ // Enable Wakeup Interrupt
|
|
|
+ USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
|
|
|
+ // Freeze USB clock
|
|
|
+ USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
|
|
|
+
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
|
|
|
+ }
|
|
|
+#if USE_SOF
|
|
|
+ if(int_status & USBHS_DEVISR_SOF) {
|
|
|
+ USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
|
|
|
+
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ // Endpoints interrupt
|
|
|
+ for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
|
|
|
+ if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
|
|
|
+ dcd_ep_handler(ep_ix);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+//--------------------------------------------------------------------+
|
|
|
+// Endpoint API
|
|
|
+//--------------------------------------------------------------------+
|
|
|
+
|
|
|
+// Configure endpoint's registers according to descriptor
|
|
|
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
|
|
+{
|
|
|
+ (void) rhport;
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
|
|
|
+ uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
|
|
|
+ uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
|
|
|
+ tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
|
|
|
+ uint8_t fifoSize = 0; // FIFO size
|
|
|
+ uint16_t defaultEndpointSize = 8; // Default size of Endpoint
|
|
|
+ // Find upper 2 power number of epMaxPktSize
|
|
|
+ if(epMaxPktSize)
|
|
|
+ {
|
|
|
+ while (defaultEndpointSize < epMaxPktSize)
|
|
|
+ {
|
|
|
+ fifoSize++;
|
|
|
+ defaultEndpointSize <<= 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ xfer_status[epnum].max_packet_size = epMaxPktSize;
|
|
|
+
|
|
|
+ if(epnum == 0)
|
|
|
+ {
|
|
|
+ xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
|
|
|
+ // Enable the control endpoint - Endpoint 0
|
|
|
+ USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
|
|
|
+ // Configure the Endpoint 0 configuration register
|
|
|
+ USBHS->USBHS_DEVEPTCFG[0] =
|
|
|
+ (
|
|
|
+ USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
|
|
|
+ USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
|
|
|
+ USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
|
|
|
+ USBHS_DEVEPTCFG_ALLOC
|
|
|
+ );
|
|
|
+ USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
|
|
|
+ USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
|
|
|
+ if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
|
|
|
+ {
|
|
|
+ // Endpoint configuration is successful
|
|
|
+ USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES | USBHS_DEVEPTIER_RXOUTES;
|
|
|
+ // Enable Endpoint 0 Interrupts
|
|
|
+ USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
|
|
|
+ return true;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // Endpoint configuration is not successful
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // Enable the endpoint
|
|
|
+ USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
|
|
|
+ // Set up the maxpacket size, fifo start address fifosize
|
|
|
+ // and enable the interrupt. CLear the data toggle.
|
|
|
+ USBHS->USBHS_DEVEPTCFG[epnum] =
|
|
|
+ (
|
|
|
+ USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
|
|
|
+ USBHS_DEVEPTCFG_EPTYPE(eptype) |
|
|
|
+ USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
|
|
|
+ USBHS_DEVEPTCFG_ALLOC |
|
|
|
+ ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
|
|
|
+ );
|
|
|
+
|
|
|
+ if (eptype == TUSB_XFER_ISOCHRONOUS)
|
|
|
+ {
|
|
|
+ USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
|
|
|
+ }
|
|
|
+ USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
|
|
|
+ USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
|
|
|
+ if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
|
|
|
+ {
|
|
|
+ // Endpoint configuration is successful. Enable Endpoint Interrupts
|
|
|
+ if(dir == TUSB_DIR_OUT)
|
|
|
+ {
|
|
|
+ USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
|
|
|
+ USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
|
|
|
+ }
|
|
|
+ USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
|
|
|
+ return true;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // Endpoint configuration is not successful
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
|
|
|
+{
|
|
|
+ uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
|
|
|
+
|
|
|
+ if(len > xfer->max_packet_size) // max packet size for FS transfer
|
|
|
+ {
|
|
|
+ len = xfer->max_packet_size;
|
|
|
+ }
|
|
|
+
|
|
|
+ volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
|
|
|
+ for (int i = 0; i < len; i++) {
|
|
|
+ ptr[i] = xfer->buffer[xfer->queued_len + i];
|
|
|
+ }
|
|
|
+
|
|
|
+ xfer->queued_len = (uint16_t)(xfer->queued_len + len);
|
|
|
+
|
|
|
+ if (ep_ix == 0U) {
|
|
|
+
|
|
|
+ // Control endpoint: clear the interrupt flag to send the data,
|
|
|
+ // and re-enable the interrupts to trigger an interrupt at the
|
|
|
+ // end of the transfer.
|
|
|
+ USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
|
|
|
+ USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
|
|
|
+ } else {
|
|
|
+
|
|
|
+ // Other endpoint types: clear the FIFO control flag to send the data.
|
|
|
+ USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
|
|
|
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
|
|
+{
|
|
|
+ (void) rhport;
|
|
|
+
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
+
|
|
|
+ xfer_ctl_t * xfer = &xfer_status[epnum];
|
|
|
+ if(ep_addr == 0x80)
|
|
|
+ xfer = &xfer_status[EP_MAX];
|
|
|
+
|
|
|
+ xfer->buffer = buffer;
|
|
|
+ xfer->total_len = total_bytes;
|
|
|
+ xfer->queued_len = 0;
|
|
|
+
|
|
|
+ SEGGER_RTT_printf(0, "xfer: %u %u %u \r\n", epnum, dir, total_bytes);
|
|
|
+
|
|
|
+ if ( dir == TUSB_DIR_OUT )
|
|
|
+ {
|
|
|
+ // Endpoint configuration is successful
|
|
|
+ // Acknowledge the interrupt
|
|
|
+ //USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_RXOUTIC;
|
|
|
+
|
|
|
+ //USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
|
|
|
+ }
|
|
|
+ else // IN
|
|
|
+ {
|
|
|
+ dcd_transmit_packet(xfer,epnum);
|
|
|
+ }
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+// Stall endpoint
|
|
|
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
+{
|
|
|
+ (void) rhport;
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_STALLRQS;
|
|
|
+}
|
|
|
+
|
|
|
+// clear stall, data toggle is also reset to DATA0
|
|
|
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
+{
|
|
|
+ (void) rhport;
|
|
|
+ uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
+ USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
|
|
|
+ USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|
HiFiPhile