ehci_controller_fake.c 7.1 KB

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  1. /**************************************************************************/
  2. /*!
  3. @file ehci_controller_fake.c
  4. @author hathach (tinyusb.org)
  5. @section LICENSE
  6. Software License Agreement (BSD License)
  7. Copyright (c) 2013, hathach (tinyusb.org)
  8. All rights reserved.
  9. Redistribution and use in source and binary forms, with or without
  10. modification, are permitted provided that the following conditions are met:
  11. 1. Redistributions of source code must retain the above copyright
  12. notice, this list of conditions and the following disclaimer.
  13. 2. Redistributions in binary form must reproduce the above copyright
  14. notice, this list of conditions and the following disclaimer in the
  15. documentation and/or other materials provided with the distribution.
  16. 3. Neither the name of the copyright holders nor the
  17. names of its contributors may be used to endorse or promote products
  18. derived from this software without specific prior written permission.
  19. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
  20. EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22. DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
  23. DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24. INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25. LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
  26. ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
  28. SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. This file is part of the tinyusb stack.
  30. */
  31. /**************************************************************************/
  32. //--------------------------------------------------------------------+
  33. // INCLUDE
  34. //--------------------------------------------------------------------+
  35. #include "unity.h"
  36. #include "common/common.h"
  37. #include "hal.h"
  38. #include "usbh_hcd.h"
  39. #include "ehci.h"
  40. #include "ehci_controller_fake.h"
  41. //--------------------------------------------------------------------+
  42. // MACRO CONSTANT TYPEDEF
  43. //--------------------------------------------------------------------+
  44. LPC_USB0_Type lpc_usb0;
  45. LPC_USB1_Type lpc_usb1;
  46. extern usbh_device_info_t usbh_devices[TUSB_CFG_HOST_DEVICE_MAX+1];
  47. //--------------------------------------------------------------------+
  48. // IMPLEMENTATION
  49. //--------------------------------------------------------------------+
  50. void ehci_controller_init(void)
  51. {
  52. memclr_(&lpc_usb0, sizeof(LPC_USB0_Type));
  53. memclr_(&lpc_usb1, sizeof(LPC_USB1_Type));
  54. }
  55. void ehci_controller_control_xfer_proceed(uint8_t dev_addr, uint8_t p_data[])
  56. {
  57. ehci_registers_t* const regs = get_operational_register( usbh_devices[dev_addr].core_id );
  58. ehci_qhd_t * p_qhd = get_control_qhd(dev_addr);
  59. ehci_qtd_t * p_qtd_setup = get_control_qtds(dev_addr);
  60. ehci_qtd_t * p_qtd_data = p_qtd_setup + 1;
  61. ehci_qtd_t * p_qtd_status = p_qtd_setup + 2;
  62. tusb_control_request_t const *p_request = (tusb_control_request_t *) p_qtd_setup->buffer[0];
  63. if (p_request->wLength > 0 && p_request->bmRequestType_bit.direction == TUSB_DIR_DEV_TO_HOST)
  64. {
  65. memcpy(p_qtd_data, p_data, p_request->wLength);
  66. }
  67. //------------- retire all QTDs -------------//
  68. p_qtd_setup->active = p_qtd_data->active = p_qtd_status->active = 0;
  69. p_qhd->qtd_overlay = *p_qtd_status;
  70. regs->usb_sts = EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC;
  71. hcd_isr( usbh_devices[dev_addr].core_id );
  72. }
  73. void complete_qtd_in_qhd(ehci_qhd_t *p_qhd)
  74. {
  75. if ( !p_qhd->qtd_overlay.halted )
  76. {
  77. while(!p_qhd->qtd_overlay.next.terminate)
  78. {
  79. ehci_qtd_t* p_qtd = (ehci_qtd_t*) align32(p_qhd->qtd_overlay.next.address);
  80. p_qtd->active = 0;
  81. p_qtd->total_bytes = 0;
  82. p_qhd->qtd_overlay = *p_qtd;
  83. }
  84. }
  85. }
  86. bool complete_all_qtd_in_async(ehci_qhd_t *head)
  87. {
  88. ehci_qhd_t *p_qhd = head;
  89. do
  90. {
  91. complete_qtd_in_qhd(p_qhd);
  92. p_qhd = (ehci_qhd_t*) align32(p_qhd->next.address);
  93. }while(p_qhd != head); // stop if loop around
  94. return true;
  95. }
  96. bool complete_all_qtd_in_period(ehci_link_t *head)
  97. {
  98. while(!head->terminate)
  99. {
  100. uint32_t queue_type = head->type;
  101. head = (ehci_link_t*) align32(head->address);
  102. if ( queue_type == EHCI_QUEUE_ELEMENT_QHD)
  103. {
  104. complete_qtd_in_qhd( (ehci_qhd_t*) head );
  105. }
  106. }
  107. return true;
  108. }
  109. void ehci_controller_run(uint8_t hostid)
  110. {
  111. //------------- Async List -------------//
  112. ehci_registers_t* const regs = get_operational_register(hostid);
  113. complete_all_qtd_in_async((ehci_qhd_t*) regs->async_list_base);
  114. //------------- Period List -------------//
  115. for(uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
  116. {
  117. complete_all_qtd_in_period( get_period_head(hostid, i) );
  118. }
  119. regs->usb_sts = EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC;
  120. hcd_isr(hostid);
  121. }
  122. void complete_1st_qtd_with_error(ehci_qhd_t* p_qhd, bool halted, bool xact_err)
  123. {
  124. if ( !p_qhd->qtd_overlay.halted )
  125. {
  126. if(!p_qhd->qtd_overlay.next.terminate) // TODO add active check
  127. {
  128. ehci_qtd_t* p_qtd = (ehci_qtd_t*) align32(p_qhd->qtd_overlay.next.address);
  129. p_qtd->active = 0;
  130. p_qtd->halted = halted ? 1 : 0;
  131. p_qtd->xact_err = xact_err ? 1 : 0;
  132. p_qhd->qtd_overlay = *p_qtd;
  133. }
  134. }
  135. }
  136. void complete_list_with_error(uint8_t hostid, bool halted, bool xact_err)
  137. {
  138. //------------- Async List -------------//
  139. ehci_registers_t* const regs = get_operational_register(hostid);
  140. ehci_qhd_t *p_qhd = (ehci_qhd_t*) regs->async_list_base;
  141. do
  142. {
  143. complete_1st_qtd_with_error(p_qhd, halted, xact_err);
  144. p_qhd = (ehci_qhd_t*) align32(p_qhd->next.address);
  145. }while(p_qhd != get_async_head(hostid)); // stop if loop around
  146. //------------- Period List -------------//
  147. for(uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
  148. {
  149. ehci_link_t *head = get_period_head(hostid, i);
  150. while(!head->terminate)
  151. {
  152. uint32_t queue_type = head->type;
  153. head = (ehci_link_t*) align32(head->address);
  154. if ( queue_type == EHCI_QUEUE_ELEMENT_QHD)
  155. {
  156. complete_1st_qtd_with_error((ehci_qhd_t*) head, halted, xact_err);
  157. }
  158. }
  159. }
  160. regs->usb_sts = EHCI_INT_MASK_ERROR;
  161. hcd_isr(hostid);
  162. }
  163. void ehci_controller_run_stall(uint8_t hostid)
  164. {
  165. complete_list_with_error(hostid, true, false);
  166. }
  167. void ehci_controller_run_error(uint8_t hostid)
  168. {
  169. complete_list_with_error(hostid, true, true);
  170. }
  171. void ehci_controller_device_plug(uint8_t hostid, tusb_speed_t speed)
  172. {
  173. ehci_registers_t* const regs = get_operational_register(hostid);
  174. regs->usb_sts_bit.port_change_detect = 1;
  175. regs->portsc_bit.connect_status_change = 1;
  176. regs->portsc_bit.current_connect_status = 1;
  177. regs->portsc_bit.nxp_port_speed = speed;
  178. hcd_isr(hostid);
  179. }
  180. void ehci_controller_device_unplug(uint8_t hostid)
  181. {
  182. ehci_registers_t* const regs = get_operational_register(hostid);
  183. regs->usb_sts_bit.port_change_detect = 1;
  184. regs->portsc_bit.connect_status_change = 1;
  185. regs->portsc_bit.current_connect_status = 0;
  186. hcd_isr(hostid);
  187. }