Merge pull request #4684 from OpenNuvoton/nuvoton

[nuvoton] Support NK-N9H30 NUemWin platform.

bsp/nuvoton/README.md

@@ -1,10 +1,11 @@
-ï»? Nuvoton BSP descriptions
+# Nuvoton BSP Description
 Current supported BSP shown in below table:
 
-| **BSP folder** | **Board name** |
-|:------------------------- |:-------------------------- |
+| **BSP Folder** | **Board Name** |
+| ------------------------- | -------------------------- |
 | [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
 | [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
 | [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
 | [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
-| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
+| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
+| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |

bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_compiler.h

@@ -31,21 +31,21 @@
  * ARM Compiler 4/5
  */
 #if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
+#include "cmsis_armcc.h"
 
 
 /*
  * ARM Compiler 6 (armclang)
  */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armclang.h"
+#include "cmsis_armclang.h"
 
 
 /*
  * GNU Compiler
  */
 #elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
+#include "cmsis_gcc.h"
 
 
 /*
@@ -54,298 +54,313 @@
 #elif defined ( __ICCARM__ )
 
 
-  #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
+#endif
 
-  #include <cmsis_iar.h>
+#include <cmsis_iar.h>
 
-  /* CMSIS compiler control architecture macros */
-  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+/* CMSIS compiler control architecture macros */
+#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
     #ifndef __ARM_ARCH_6M__
-      #define __ARM_ARCH_6M__                      1
+        #define __ARM_ARCH_6M__                      1
     #endif
-  #elif (__CORE__ == __ARM7M__)
+#elif (__CORE__ == __ARM7M__)
     #ifndef __ARM_ARCH_7M__
-      #define __ARM_ARCH_7M__                      1
+        #define __ARM_ARCH_7M__                      1
     #endif
-  #elif (__CORE__ == __ARM7EM__)
+#elif (__CORE__ == __ARM7EM__)
     #ifndef __ARM_ARCH_7EM__
-      #define __ARM_ARCH_7EM__                     1
+        #define __ARM_ARCH_7EM__                     1
     #endif
-  #endif
+#endif
 
-  #ifndef   __NO_RETURN
+#ifndef   __NO_RETURN
     #define __NO_RETURN                            __noreturn
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #define __USED                                 __root
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               __packed
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        __packed struct
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         __packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    __packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+__packed struct T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     //#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
     #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     //#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
-
-  // Workaround for missing __CLZ intrinsic in
-  // various versions of the IAR compilers.
-  // __IAR_FEATURE_CLZ__ should be defined by
-  // the compiler that supports __CLZ internally.
-  #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
-    __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+#endif
+
+// Workaround for missing __CLZ intrinsic in
+// various versions of the IAR compilers.
+// __IAR_FEATURE_CLZ__ should be defined by
+// the compiler that supports __CLZ internally.
+#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+__STATIC_INLINE uint32_t __CLZ(uint32_t data)
+{
+    if (data == 0u)
+    {
+        return 32u;
+    }
+
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0)
     {
-      if (data == 0u) { return 32u; }
-      
-      uint32_t count = 0;
-      uint32_t mask = 0x80000000;
-      
-      while ((data & mask) == 0)
-      {
         count += 1u;
         mask = mask >> 1u;
-      }
-      
-      return (count);
     }
-  #endif
+
+    return (count);
+}
+#endif
 
 
 /*
  * TI ARM Compiler
  */
 #elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
+#include <cmsis_ccs.h>
 
-  #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __attribute__((packed)) T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
+#endif
 
 
 /*
  * TASKING Compiler
  */
 #elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
 
-  #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __packed__ T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
+#endif
 
 
 /*
  * COSMIC Compiler
  */
 #elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
+#include <cmsis_csm.h>
 
- #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     // NO RETURN is automatically detected hence no warning here
     #define __NO_RETURN
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #warning No compiler specific solution for __USED. __USED is ignored.
     #define __USED
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+@packed struct T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
     #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
+#endif
 
 
 #else
-  #error Unknown compiler.
+#error Unknown compiler.
 #endif
 
 

bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0.h

@@ -23,9 +23,9 @@
  */
 
 #if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
+    #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
+    #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM0_H_GENERIC
@@ -34,7 +34,7 @@
 #include <stdint.h>
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /**
@@ -61,7 +61,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
@@ -76,39 +76,39 @@
 #define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #endif
 
@@ -127,25 +127,25 @@
 #define __CORE_CM0_H_DEPENDANT
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
+#ifndef __CM0_REV
+#define __CM0_REV               0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
 #endif
 
 /* IO definitions (access restrictions to peripheral registers) */
@@ -157,9 +157,9 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
@@ -198,15 +198,15 @@
  */
 typedef union
 {
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
@@ -228,12 +228,12 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
@@ -246,18 +246,18 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
@@ -285,13 +285,13 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
@@ -313,16 +313,16 @@ typedef union
  */
 typedef struct
 {
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
@@ -340,15 +340,15 @@ typedef struct
  */
 typedef struct
 {
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    uint32_t RESERVED0;
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
@@ -447,10 +447,10 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
@@ -567,33 +567,33 @@ typedef struct
  */
 
 #ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
 /*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
 /*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
 #endif /* CMSIS_NVIC_VIRTUAL */
 
 #ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 #else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 
 #define NVIC_USER_IRQ_OFFSET          16
@@ -614,10 +614,10 @@ typedef struct
  */
 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -631,14 +631,14 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else
+    {
+        return (0U);
+    }
 }
 
 
@@ -650,12 +650,12 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
 }
 
 
@@ -669,14 +669,14 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else
+    {
+        return (0U);
+    }
 }
 
 
@@ -688,10 +688,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -703,10 +703,10 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -721,16 +721,16 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else
+    {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
 }
 
 
@@ -746,14 +746,14 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else
+    {
+        return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
 }
 
 
@@ -768,8 +768,8 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
-  uint32_t *vectors = (uint32_t *)0x0U;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+    uint32_t *vectors = (uint32_t *)0x0U;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 
 
@@ -783,8 +783,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
  */
 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
-  uint32_t *vectors = (uint32_t *)0x0U;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+    uint32_t *vectors = (uint32_t *)0x0U;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 }
 
 
@@ -794,16 +794,16 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SystemReset(void)
 {
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for (;;)                                                          /* wait until reset */
+    {
+        __NOP();
+    }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
@@ -858,18 +858,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+    {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);  /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
 }
 
 #endif

bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0plus.h

@@ -23,9 +23,9 @@
  */
 
 #if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
+    #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
+    #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM0PLUS_H_GENERIC
@@ -34,7 +34,7 @@
 #include <stdint.h>
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /**
@@ -61,7 +61,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0+ definitions */
 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
@@ -76,39 +76,39 @@
 #define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
 #endif
 
@@ -127,35 +127,35 @@
 #define __CORE_CM0PLUS_H_DEPENDANT
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV             0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
 #endif
 
 /* IO definitions (access restrictions to peripheral registers) */
@@ -167,9 +167,9 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
@@ -209,15 +209,15 @@
  */
 typedef union
 {
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
@@ -239,12 +239,12 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
@@ -257,18 +257,18 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
@@ -296,13 +296,13 @@ typedef union
  */
 typedef union
 {
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    struct
+    {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
@@ -327,16 +327,16 @@ typedef union
  */
 typedef struct
 {
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
@@ -354,19 +354,19 @@ typedef struct
  */
 typedef struct
 {
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 #else
-        uint32_t RESERVED0;
+    uint32_t RESERVED0;
 #endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
@@ -471,10 +471,10 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
@@ -523,11 +523,11 @@ typedef struct
  */
 typedef struct
 {
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
 } MPU_Type;
 
 /* MPU Type Register Definitions */
@@ -653,8 +653,8 @@ typedef struct
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 
 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 /*@} */
@@ -683,33 +683,33 @@ typedef struct
  */
 
 #ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
 /*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
 /*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
 #endif /* CMSIS_NVIC_VIRTUAL */
 
 #ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 #else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 
 #define NVIC_USER_IRQ_OFFSET          16
@@ -730,10 +730,10 @@ typedef struct
  */
 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -747,14 +747,14 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else
+    {
+        return (0U);
+    }
 }
 
 
@@ -766,12 +766,12 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
 }
 
 
@@ -785,14 +785,14 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else
+    {
+        return (0U);
+    }
 }
 
 
@@ -804,10 +804,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -819,10 +819,10 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
 }
 
 
@@ -837,16 +837,16 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else
+    {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
 }
 
 
@@ -862,14 +862,14 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
+    if ((int32_t)(IRQn) >= 0)
+    {
+        return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else
+    {
+        return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
 }
 
 
@@ -886,11 +886,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
 #else
     uint32_t *vectors = (uint32_t *)0x0U;
 #endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 
 
@@ -905,11 +905,11 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
 #else
-  uint32_t *vectors = (uint32_t *)0x0U;
+    uint32_t *vectors = (uint32_t *)0x0U;
 #endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 
 }
 
@@ -920,16 +920,16 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
  */
 __STATIC_INLINE void __NVIC_SystemReset(void)
 {
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for (;;)                                                          /* wait until reset */
+    {
+        __NOP();
+    }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
@@ -991,18 +991,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+    {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);  /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
 }
 
 #endif

bsp/nuvoton/libraries/m2354/CMSIS/Include/mpu_armv7.h

@@ -21,7 +21,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #ifndef ARM_MPU_ARMV7_H
 #define ARM_MPU_ARMV7_H
 
@@ -54,7 +54,7 @@
 #define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
 #define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
 
-#define ARM_MPU_AP_NONE 0u 
+#define ARM_MPU_AP_NONE 0u
 #define ARM_MPU_AP_PRIV 1u
 #define ARM_MPU_AP_URO  2u
 #define ARM_MPU_AP_FULL 3u
@@ -70,7 +70,7 @@
 
 /**
 * MPU Region Attribut and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -79,7 +79,7 @@
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
+*/
 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
   ((DisableExec      << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
   ((AccessPermission << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
@@ -95,21 +95,22 @@
 /**
 * Struct for a single MPU Region
 */
-typedef struct _ARM_MPU_Region_t {
-  uint32_t RBAR; //!< The region base address register value (RBAR)
-  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+typedef struct _ARM_MPU_Region_t
+{
+    uint32_t RBAR; //!< The region base address register value (RBAR)
+    uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+    __DSB();
+    __ISB();
+    MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
 }
 
@@ -117,12 +118,12 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 */
 __STATIC_INLINE void ARM_MPU_Disable()
 {
-  __DSB();
-  __ISB();
+    __DSB();
+    __ISB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+    SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+    MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
 }
 
 /** Clear and disable the given MPU region.
@@ -130,30 +131,30 @@ __STATIC_INLINE void ARM_MPU_Disable()
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 {
-  MPU->RNR = rnr;
-  MPU->RASR = 0u;
+    MPU->RNR = rnr;
+    MPU->RASR = 0u;
 }
 
 /** Configure an MPU region.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 {
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
+    MPU->RBAR = rbar;
+    MPU->RASR = rasr;
 }
 
 /** Configure the given MPU region.
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
 {
-  MPU->RNR = rnr;
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
+    MPU->RNR = rnr;
+    MPU->RBAR = rbar;
+    MPU->RASR = rasr;
 }
 
 /** Memcopy with strictly ordered memory access, e.g. for register targets.
@@ -161,22 +162,22 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
 {
-  uint32_t i;
-  for (i = 0u; i < len; ++i) 
-  {
-    dst[i] = src[i];
-  }
+    uint32_t i;
+    for (i = 0u; i < len; ++i)
+    {
+        dst[i] = src[i];
+    }
 }
 
 /** Load the given number of MPU regions from a table.
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
 {
-  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * sizeof(ARM_MPU_Region_t) / 4u);
 }
 
 #endif

bsp/nuvoton/libraries/m2354/CMSIS/Include/tz_context.h

@@ -26,44 +26,44 @@
  * Version 1.0
  *    Initial Release
  *---------------------------------------------------------------------------*/
-  
+
 #ifndef TZ_CONTEXT_H
 #define TZ_CONTEXT_H
- 
+
 #include <stdint.h>
- 
+
 #ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
+    #define TZ_MODULEID_T
+    /// \details Data type that identifies secure software modules called by a process.
+    typedef uint32_t TZ_ModuleId_t;
 #endif
- 
+
 /// \details TZ Memory ID identifies an allocated memory slot.
 typedef uint32_t TZ_MemoryId_t;
-  
+
 /// Initialize secure context memory system
 /// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
- 
+uint32_t TZ_InitContextSystem_S(void);
+
 /// Allocate context memory for calling secure software modules in TrustZone
 /// \param[in]  module   identifies software modules called from non-secure mode
 /// \return value != 0 id TrustZone memory slot identifier
 /// \return value 0    no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
- 
+TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
+
 /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
- 
+uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
+
 /// Load secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
- 
+uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
+
 /// Store secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
- 
+uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
+
 #endif  // TZ_CONTEXT_H

bsp/nuvoton/libraries/m2354/USBHostLib/inc/config.h

@@ -17,7 +17,7 @@
 /*----------------------------------------------------------------------------------------*/
 /*   Hardware settings                                                                    */
 /*----------------------------------------------------------------------------------------*/
-#define HCLK_MHZ               192          /* used for loop-delay. must be larger than 
+#define HCLK_MHZ               192          /* used for loop-delay. must be larger than
                                                true HCLK clock MHz                        */
 
 #define ENABLE_OHCI_IRQ()      NVIC_EnableIRQ(USBH_IRQn)
@@ -25,12 +25,12 @@
 
 #define ENABLE_OHCI                         /* Enable OHCI host controller                */
 
-#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling 
+#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling
                                                OHCI isochronous transfer                  */
 
-#define MAX_DESC_BUFF_SIZE     512          /* To hold the configuration descriptor, USB 
+#define MAX_DESC_BUFF_SIZE     512          /* To hold the configuration descriptor, USB
                                                core will allocate a buffer with this size
-                                               for each connected device. USB core does 
+                                               for each connected device. USB core does
                                                not release it until device disconnected.  */
 
 /*----------------------------------------------------------------------------------------*/
@@ -57,7 +57,7 @@
 /*   Re-defined staff for various compiler                                                */
 /*----------------------------------------------------------------------------------------*/
 #ifdef __ICCARM__
-#define   __inline    inline
+    #define   __inline    inline
 #endif
 
 
@@ -70,21 +70,21 @@
 //#define DUMP_DESCRIPTOR                     /* dump descriptors                           */
 
 #ifdef ENABLE_ERROR_MSG
-#define USB_error            rt_kprintf
+    #define USB_error            rt_kprintf
 #else
-#define USB_error(...)
+    #define USB_error(...)
 #endif
 
 #ifdef ENABLE_DEBUG_MSG
-#define USB_debug            rt_kprintf
-#ifdef ENABLE_VERBOSE_DEBUG
-#define USB_vdebug          rt_kprintf
+    #define USB_debug            rt_kprintf
+    #ifdef ENABLE_VERBOSE_DEBUG
+        #define USB_vdebug          rt_kprintf
+    #else
+        #define USB_vdebug(...)
+    #endif
 #else
-#define USB_vdebug(...)
-#endif
-#else
-#define USB_debug(...)
-#define USB_vdebug(...)
+    #define USB_debug(...)
+    #define USB_vdebug(...)
 #endif
 
 

bsp/nuvoton/libraries/m2354/USBHostLib/inc/usbh_lib.h

@@ -51,7 +51,7 @@ extern "C"
 #define USBH_ERR_DISCONNECTED       -259   /*!< USB device was disconnected                     */
 
 #define USBH_ERR_TRANSACTION        -271   /*!< USB transaction timeout, CRC, Bad PID, etc.     */
-#define USBH_ERR_BABBLE_DETECTED    -272   /*!< A ¡§babble¡¨ is detected during the transaction   */
+#define USBH_ERR_BABBLE_DETECTED    -272   /*!< A 'babble' is detected during the transaction   */
 #define USBH_ERR_DATA_BUFF          -274   /*!< Data buffer overrun or underrun                 */
 
 #define USBH_ERR_CC_NO_ERR          -280   /*!< OHCI CC code - no error                         */
@@ -145,7 +145,7 @@ extern int  usbh_polling_root_hubs(void);
 extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
 extern void usbh_suspend(void);
 extern void usbh_resume(void);
-extern struct udev_t * usbh_find_device(char *hub_id, int port);
+extern struct udev_t *usbh_find_device(char *hub_id, int port);
 /**
  * @brief  A function return current tick count.
  * @return Current tick.
@@ -161,7 +161,7 @@ extern uint32_t usbh_tick_from_millisecond(uint32_t msec);   /* This function mu
 /*                                                                  */
 /*------------------------------------------------------------------*/
 extern void     usbh_cdc_init(void);
-extern struct cdc_dev_t * usbh_cdc_get_device_list(void);
+extern struct cdc_dev_t *usbh_cdc_get_device_list(void);
 /// @cond HIDDEN_SYMBOLS
 extern int32_t  usbh_cdc_get_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
 extern int32_t  usbh_cdc_set_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
@@ -178,7 +178,7 @@ extern int32_t  usbh_cdc_send_data(struct cdc_dev_t *cdev, uint8_t *buff, int bu
 /*                                                                  */
 /*------------------------------------------------------------------*/
 extern void     usbh_hid_init(void);
-extern struct usbhid_dev * usbh_hid_get_device_list(void);
+extern struct usbhid_dev *usbh_hid_get_device_list(void);
 extern int32_t  usbh_hid_get_report_descriptor(struct usbhid_dev *hdev, uint8_t *desc_buf, int buf_max_len);
 extern int32_t  usbh_hid_get_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
 extern int32_t  usbh_hid_set_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
@@ -211,7 +211,7 @@ extern int  usbh_umas_reset_disk(int drv_no);
 /*------------------------------------------------------------------*/
 extern void usbh_uac_init(void);
 extern int usbh_uac_open(struct uac_dev_t *audev);
-extern struct uac_dev_t * usbh_uac_get_device_list(void);
+extern struct uac_dev_t *usbh_uac_get_device_list(void);
 extern int usbh_uac_get_channel_number(struct uac_dev_t *audev, uint8_t target);
 extern int usbh_uac_get_bit_resolution(struct uac_dev_t *audev, uint8_t target, uint8_t *byte_cnt);
 extern int usbh_uac_get_sampling_rate(struct uac_dev_t *audev, uint8_t target, uint32_t *srate_list, int max_cnt, uint8_t *type);

bsp/nuvoton/libraries/m2354/USBHostLib/src/usb_core.c

@@ -22,7 +22,7 @@
 
 USBH_T     *_ohci;
 
-static UDEV_DRV_T *  _drivers[MAX_UDEV_DRIVER];
+static UDEV_DRV_T   *_drivers[MAX_UDEV_DRIVER];
 static CONN_FUNC  *g_conn_func, *g_disconn_func;
 
 /// @endcond HIDDEN_SYMBOLS
@@ -34,7 +34,7 @@ static CONN_FUNC  *g_conn_func, *g_disconn_func;
   */
 void  usbh_core_init()
 {
-    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    if ((__PC() & NS_OFFSET) == NS_OFFSET)
     {
         _ohci = USBH_NS;
     }
@@ -50,7 +50,7 @@ void  usbh_core_init()
     g_conn_func = NULL;
     g_disconn_func = NULL;
 
- //   usbh_hub_init();
+//   usbh_hub_init();
 
     usbh_memory_init();
 
@@ -111,7 +111,7 @@ int usbh_connect_device(UDEV_T *udev)
 
     if (g_conn_func)
         g_conn_func(udev, 0);
-    
+
     return 0;
 }
 
@@ -123,8 +123,8 @@ void usbh_disconnect_device(UDEV_T *udev)
     if (g_disconn_func)
         g_disconn_func(udev, 0);
 
-    
-#if 1    //CHECK: Maybe create a new API to quit_xfer and free udev for application    
+
+#if 1    //CHECK: Maybe create a new API to quit_xfer and free udev for application
     usbh_quit_xfer(udev, &(udev->ep0));    /* Quit control transfer if hw_pipe is not NULL.  */
 
     /* remove device from global device list */
@@ -153,7 +153,7 @@ int usbh_reset_port(UDEV_T *udev)
     if (udev->parent == NULL)
     {
         if (udev->hc_driver)
-            return udev->hc_driver->rthub_port_reset(udev->port_num-1);
+            return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
         else
             return USBH_ERR_NOT_FOUND;
     }
@@ -171,7 +171,7 @@ int usbh_reset_port(UDEV_T *udev)
   */
 int usbh_quit_utr(UTR_T *utr)
 {
-    if(!utr || !utr->udev)
+    if (!utr || !utr->udev)
         return USBH_ERR_NOT_FOUND;
 
     return utr->udev->hc_driver->quit_xfer(utr, NULL);

bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c

@@ -94,7 +94,7 @@ rt_err_t nu_crc_init(void)
 {
     SYS_ResetModule(CRC_RST);
 
-    rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
     return RT_EOK;
 }
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c

@@ -82,11 +82,11 @@ static rt_err_t nu_crypto_init(void)
     SHA_ENABLE_INT(CRPT);
 
     //init cipher mutex
-    rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
-    rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
+    rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
 #if !defined(BSP_USING_TRNG)
     PRNG_ENABLE_INT(CRPT);
-    rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
 #endif
 
     return RT_EOK;

bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.c

@@ -314,7 +314,7 @@ static int nu_fmc_init(void)
     FMC_ENABLE_ISP();
     SYS_LockReg();
 
-    g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
+    g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_PRIO);
 
     /* PKG_USING_FAL */
 #if defined(PKG_USING_FAL)

bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c

@@ -210,7 +210,7 @@ static void nu_pdma_init(void)
     if (nu_pdma_inited)
         return;
 
-    g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
+    g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_PRIO);
     RT_ASSERT(g_mutex_sg != RT_NULL);
 
     nu_pdma_chn_mask = ~(NU_PDMA_CH_Msk);
@@ -534,7 +534,7 @@ rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u3
         goto exit_nu_pdma_desc_setup;
     else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8)))
         goto exit_nu_pdma_desc_setup;
-    else if ( i32TransferCnt > NU_PDMA_MAX_TXCNT )
+    else if (i32TransferCnt > NU_PDMA_MAX_TXCNT)
         goto exit_nu_pdma_desc_setup;
 
     PDMA = NU_PDMA_GET_BASE(i32ChannID);
@@ -890,7 +890,7 @@ static void nu_pdma_memfun_actor_init(void)
         nu_pdma_memfun_actor_maxnum = i;
         nu_pdma_memfun_actor_mask = ~(((1 << i) - 1));
         nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
-        nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
+        nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO);
     }
 }
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_qspi.c

@@ -161,10 +161,10 @@ exit_nu_qspi_bus_configure:
     return -(ret);
 }
 
-#if defined(RT_SFUD_USING_QSPI)
 static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
 {
     QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
+#if defined(RT_SFUD_USING_QSPI)
     if (qspi_lines > 1)
     {
         if (tx)
@@ -199,13 +199,13 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8
         }
     }
     else
+#endif
     {
         QSPI_DISABLE_DUAL_MODE(qspi_base);
         QSPI_DISABLE_QUAD_MODE(qspi_base);
     }
     return qspi_lines;
 }
-#endif
 
 static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
@@ -298,9 +298,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
                         qspi_message->dummy_cycles / (8 / u8last),
                         1);
     }
-
     /* Data stage */
     nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
+#else
+    /* Data stage */
+    nu_qspi_mode_config(qspi_bus, RT_NULL, RT_NULL, 1);
 #endif //#if defined(RT_SFUD_USING_QSPI)
 
     if (message->length != 0)
@@ -350,8 +352,7 @@ static int rt_hw_qspi_init(void)
 #if defined(BSP_USING_SPI_PDMA)
         nu_qspi_arr[i].pdma_chanid_tx = -1;
         nu_qspi_arr[i].pdma_chanid_rx = -1;
-#endif
-#if defined(BSP_USING_QSPI_PDMA)
+
         if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
         {
             if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)

bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c

@@ -222,7 +222,7 @@ static int rt_hw_slcd_init(void)
     {
         ret = rt_hw_slcd_register(&nu_slcd_arr[i].dev, nu_slcd_arr[i].name, RT_DEVICE_FLAG_RDWR, NULL);
         RT_ASSERT(ret == RT_EOK);
-        nu_slcd_arr[i].lock = rt_mutex_create(nu_slcd_arr[i].name, RT_IPC_FLAG_FIFO);
+        nu_slcd_arr[i].lock = rt_mutex_create(nu_slcd_arr[i].name, RT_IPC_FLAG_PRIO);
         RT_ASSERT(nu_slcd_arr[i].lock != RT_NULL);
     }
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c

@@ -212,6 +212,6 @@ int rt_soft_i2c_init(void)
 
     return 0;
 }
-INIT_BOARD_EXPORT(rt_soft_i2c_init);
+INIT_DEVICE_EXPORT(rt_soft_i2c_init);
 
 #endif //#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN))

bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c

@@ -50,7 +50,7 @@ rt_err_t nu_trng_init(void)
 {
     rt_err_t result;
 
-    result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
     s_i32TRNGEnable = 1;

bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h

@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. October 2015
-* $Revision: 	V.1.4.5 a
+* $Revision:    V.1.4.5 a
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
 *
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
 *
 * Target Processor: Cortex-M4/Cortex-M3
 *

bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h

@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. March 2015
-* $Revision: 	V.1.4.5
+* $Revision:    V.1.4.5
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
 *
-* Description:	This file has constant structs that are initialized for
+* Description:  This file has constant structs that are initialized for
 *              user convenience.  For example, some can be given as
 *              arguments to the arm_cfft_f32() function.
 *
@@ -46,34 +46,34 @@
 #include "arm_math.h"
 #include "arm_common_tables.h"
 
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
 
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
 
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
 
 #endif

bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h

@@ -10,7 +10,7 @@
 #define __SYS_REG_H__
 
 #if defined ( __CC_ARM   )
-#pragma anon_unions
+    #pragma anon_unions
 #endif
 
 /**
@@ -3339,7 +3339,7 @@ typedef struct
 #define SYS_HIRCTCTL_CESTOPEN_Msk        (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos)              /*!< SYS_T::HIRCTCTL: CESTOPEN Mask         */
 
 #define SYS_HIRCTCTL_BOUNDEN_Pos         (9)                                               /*!< SYS_T::HIRCTCTL: BOUNDEN Position      */
-#define SYS_HIRCTCTL_BOUNDEN_Msk         (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos)               /*!< SYS_T::HIRCTCTL: BOUNDEN Mask          */  
+#define SYS_HIRCTCTL_BOUNDEN_Msk         (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos)               /*!< SYS_T::HIRCTCTL: BOUNDEN Mask          */
 
 #define SYS_HIRCTCTL_REFCKSEL_Pos        (10)                                              /*!< SYS_T::HIRCTCTL: REFCKSEL Position     */
 #define SYS_HIRCTCTL_REFCKSEL_Msk        (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos)              /*!< SYS_T::HIRCTCTL: REFCKSEL Mask         */
@@ -3656,7 +3656,7 @@ typedef struct
 /**@}*/ /* end of REGISTER group */
 
 #if defined ( __CC_ARM   )
-#pragma no_anon_unions
+    #pragma no_anon_unions
 #endif
 
 #endif /* __SYS_REG_H__ */

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h

@@ -298,7 +298,7 @@ extern "C"
 #define CLK_PCLKDIV_PCLK1DIV4            (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
 #define CLK_PCLKDIV_PCLK1DIV8            (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
 #define CLK_PCLKDIV_PCLK1DIV16           (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
-// 
+//
 #define CLK_PCLKDIV_APB0DIV_DIV1         (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
 #define CLK_PCLKDIV_APB0DIV_DIV2         (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
 #define CLK_PCLKDIV_APB0DIV_DIV4         (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
@@ -617,7 +617,7 @@ __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
 
     /* Waiting for down-count to zero */
-    while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
+    while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
     {
     }
 
@@ -642,7 +642,7 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
 
     do
     {
-        if(us > delay)
+        if (us > delay)
         {
             us -= delay;
         }
@@ -657,13 +657,13 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
         SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
 
         /* Waiting for down-count to zero */
-        while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
+        while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
 
         /* Disable SysTick counter */
         SysTick->CTRL = 0UL;
 
     }
-    while(us > 0UL);
+    while (us > 0UL);
 
 }
 

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_trng.h

@@ -32,8 +32,8 @@ extern "C"
 /*----------------------------------------------------------------------------------------------*/
 
 /**
-  * @brief  Let TRNG engine know the currrent PCLK frequency. The CLKPSC is the peripheral 
-  *         clock frequency range for the selected value , the CLKPSC setting must be higher 
+  * @brief  Let TRNG engine know the currrent PCLK frequency. The CLKPSC is the peripheral
+  *         clock frequency range for the selected value , the CLKPSC setting must be higher
   *         than or equal to the actual peripheral clock frequency (for correct random generation).
   * @param  clkpsc   0: PCLK is 80~100 MHz
   *                  1: PCLK is 60~80 MHz

bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c

@@ -16,9 +16,9 @@
 #define ENABLE_DEBUG    0
 
 #if ENABLE_DEBUG
-#define CRPT_DBGMSG   printf
+    #define CRPT_DBGMSG   printf
 #else
-#define CRPT_DBGMSG(...)   do { } while (0)       /* disable debug */
+    #define CRPT_DBGMSG(...)   do { } while (0)       /* disable debug */
 #endif
 
 /** @endcond HIDDEN_SYMBOLS */
@@ -75,8 +75,8 @@ void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32
         crpt->PRNG_SEED = u32Seed;
     }
 
-    crpt->PRNG_CTL =  (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
-                      (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
+    crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                     (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
 }
 
 /**
@@ -178,7 +178,7 @@ void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t
     uint32_t  i, wcnt, key_reg_addr;
 
     key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL);
-    wcnt = 4UL + u32KeySize*2UL;
+    wcnt = 4UL + u32KeySize * 2UL;
 
     for (i = 0U; i < wcnt; i++)
     {
@@ -379,9 +379,9 @@ void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t h
         crpt->HMAC_KEYCNT = hmac_key_len;
 
         if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)
-            crpt->HMAC_CTL |= (1<<4);   /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
+            crpt->HMAC_CTL |= (1 << 4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
         else
-            crpt->HMAC_CTL |= (1<<11);  /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
+            crpt->HMAC_CTL |= (1 << 11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
     }
 }
 
@@ -447,7 +447,7 @@ void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])
         wcnt = 16UL;
     }
 
-    reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]);
+    reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]);
     for (i = 0UL; i < wcnt; i++)
     {
         u32Digest[i] = inpw(reg_addr);
@@ -887,7 +887,7 @@ const ECC_CURVE _Curve[] =
 static ECC_CURVE  *pCurve;
 static ECC_CURVE  Curve_Copy;
 
-static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
+static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve);
 static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);
 static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
 
@@ -990,7 +990,7 @@ static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
   */
 static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
 {
-    return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ];
+    return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ];
 }
 
 
@@ -1012,7 +1012,7 @@ static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
     }
 }
 
-static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
+static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve)
 {
     uint32_t   i;
     ECC_CURVE  *ret = NULL;
@@ -1108,7 +1108,7 @@ static int ecc_strcmp(char *s1, char *s2)
     while (*s1 == '0') s1++;
     while (*s2 == '0') s2++;
 
-    for ( ; *s1 || *s2; s1++, s2++)
+    for (; *s1 || *s2; s1++, s2++)
     {
         if ((*s1 >= 'A') && (*s1 <= 'Z'))
             c1 = *s1 + 32;
@@ -1502,7 +1502,7 @@ int32_t  ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *messag
         Reg2Hex(pCurve->Echar, temp_result1, R);
 
         /*
-         *   4. Compute s = k ? 1 ¡Ñ (e + d ¡Ñ r)(mod n). If s = 0, go to step 2
+         *   4. Compute s = k ? 1 � (e + d � r)(mod n). If s = 0, go to step 2
          *      (1) Write the curve order to N registers according
          *      (2) Write 0x1 to Y1 registers
          *      (3) Write the random integer k to X1 registers according
@@ -1732,7 +1732,7 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
 #endif
 
         /*
-         *   4. Compute u1 = e ¡Ñ w (mod n) and u2 = r ¡Ñ w (mod n)
+         *   4. Compute u1 = e � w (mod n) and u2 = r � w (mod n)
          *      (1) Write the curve order and curve length to N ,M registers
          *      (2) Write e, w to X1, Y1 registers
          *      (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
@@ -1814,7 +1814,7 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
 #endif
 
         /*
-         *   5. Compute X¡¦ (x1¡¦, y1¡¦) = u1 * G + u2 * Q
+         *   5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
          *      (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
          *      (2) Write the point G(x, y) to X1, Y1 registers
          *      (3) Write u1 to K registers
@@ -1833,17 +1833,17 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
          *      (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
          *      (17) Set START(CRPT_ECC_CTL[0]) to 1
          *      (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
-         *      (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦)
+         *      (19) Read X1, Y1 registers to get X・(x1・, y1・)
          *      (20) Write the curve order and curve length to N ,M registers
-         *      (21) Write x1¡¦ to X1 registers
+         *      (21) Write x1・ to X1 registers
          *      (22) Write 0x0 to Y1 registers
          *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
          *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
          *      (25) Set START(CRPT_ECC_CTL[0]) to 1
          *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
-         *      (27) Read X1 registers to get x1¡¦ (mod n)
+         *      (27) Read X1 registers to get x1・ (mod n)
          *
-         *   6. The signature is valid if x1¡¦ = r, otherwise it is invalid
+         *   6. The signature is valid if x1・ = r, otherwise it is invalid
          */
 
         /*
@@ -1927,7 +1927,7 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
 
         run_ecc_codec(crpt, ECCOP_POINT_ADD);
 
-        /* (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) */
+        /* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
         for (i = 0; i < 18; i++)
         {
             temp_x[i] = crpt->ECC_X1[i];
@@ -1949,7 +1949,7 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
         Hex2Reg(pCurve->Eorder, crpt->ECC_N);
 
         /*
-         *  (21) Write x1¡¦ to X1 registers
+         *  (21) Write x1・ to X1 registers
          *  (22) Write 0x0 to Y1 registers
          */
         for (i = 0; i < 18; i++)
@@ -1967,11 +1967,11 @@ int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
 
         run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
 
-        /*  (27) Read X1 registers to get x1¡¦ (mod n) */
+        /*  (27) Read X1 registers to get x1・ (mod n) */
         Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
         CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
 
-        /* 6. The signature is valid if x1¡¦ = r, otherwise it is invalid */
+        /* 6. The signature is valid if x1・ = r, otherwise it is invalid */
 
         /* Compare with test pattern to check if r is correct or not */
         if (ecc_strcmp(temp_hex_str, R) != 0)

bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c

@@ -209,7 +209,7 @@ void EMAC_PhyInit(void)
 
     while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
     {
-        if (i++ > 80000UL)      /* Cable not connected */
+        if (i++ > 10000UL)      /* Cable not connected */
         {
             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
@@ -217,7 +217,7 @@ void EMAC_PhyInit(void)
         }
     }
 
-    if (i <= 80000UL)
+    if (i <= 10000UL)
     {
         /* Configure auto negotiation capability */
         EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
@@ -747,7 +747,8 @@ uint32_t EMAC_SendPktDone(void)
             desc->u32Next = desc->u32Backup2;
             /* go to next descriptor in link */
             desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
-        } while (last_tx_desc != (uint32_t)desc);    /* If we reach last sent Tx descriptor, leave the loop */
+        }
+        while (last_tx_desc != (uint32_t)desc);      /* If we reach last sent Tx descriptor, leave the loop */
 
         /* Save last processed Tx descriptor */
         u32CurrentTxDesc = (uint32_t)desc;
@@ -1115,7 +1116,7 @@ uint8_t *EMAC_ClaimFreeTXBuf(void)
   * @return An data length of avaiable RX buffer.
   * @note   This API should be called before EMAC_RecvPktDone_WoTrigger calling. Caller will do data-copy.
   */
-uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf)
+uint32_t EMAC_GetAvailRXBufSize(uint8_t **ppuDataBuf)
 {
     EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
 
@@ -1126,7 +1127,7 @@ uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf)
         /* It is good and no CRC error. */
         if ((status & EMAC_RXFD_RXGD) && !(status & EMAC_RXFD_CRCE))
         {
-            *ppuDataBuf = (uint8_t*)desc->u32Backup1;
+            *ppuDataBuf = (uint8_t *)desc->u32Backup1;
             return desc->u32Status1 & 0xFFFFUL;
         }
         else

bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c

@@ -46,9 +46,9 @@ uint32_t QSPI_Open(QSPI_T *qspi,
                    uint32_t u32DataWidth,
                    uint32_t u32BusClock)
 {
-    uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
+    uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U;
 
-    if(u32DataWidth == 32U)
+    if (u32DataWidth == 32U)
     {
         u32DataWidth = 0U;
     }
@@ -56,7 +56,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
     /* Get system clock frequency */
     u32HCLKFreq = CLK_GetHCLKFreq();
 
-    if(u32MasterSlave == QSPI_MASTER)
+    if (u32MasterSlave == QSPI_MASTER)
     {
         /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
         qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
@@ -64,7 +64,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
         /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
         qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
 
-        if(u32BusClock >= u32HCLKFreq)
+        if (u32BusClock >= u32HCLKFreq)
         {
             /* Select PCLK as the clock source of QSPI */
             if (qspi == QSPI0)
@@ -76,15 +76,15 @@ uint32_t QSPI_Open(QSPI_T *qspi,
         /* Check clock source of QSPI */
         if (qspi == QSPI0)
         {
-            if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+            if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
             {
                 u32ClkSrc = __HXT; /* Clock source is HXT */
             }
-            else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
             {
                 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
             }
-            else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
             {
                 /* Clock source is PCLK0 */
                 u32ClkSrc = CLK_GetPCLK0Freq();
@@ -96,15 +96,15 @@ uint32_t QSPI_Open(QSPI_T *qspi,
         }
         else if (qspi == QSPI1)
         {
-            if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+            if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
             {
                 u32ClkSrc = __HXT; /* Clock source is HXT */
             }
-            else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+            else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
             {
                 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
             }
-            else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+            else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
             {
                 /* Clock source is PCLK1 */
                 u32ClkSrc = CLK_GetPCLK1Freq();
@@ -115,21 +115,21 @@ uint32_t QSPI_Open(QSPI_T *qspi,
             }
         }
 
-        if(u32BusClock >= u32HCLKFreq)
+        if (u32BusClock >= u32HCLKFreq)
         {
             /* Set DIVIDER = 0 */
             qspi->CLKDIV = 0U;
             /* Return master peripheral clock rate */
             u32RetValue = u32ClkSrc;
         }
-        else if(u32BusClock >= u32ClkSrc)
+        else if (u32BusClock >= u32ClkSrc)
         {
             /* Set DIVIDER = 0 */
             qspi->CLKDIV = 0U;
             /* Return master peripheral clock rate */
             u32RetValue = u32ClkSrc;
         }
-        else if(u32BusClock == 0U)
+        else if (u32BusClock == 0U)
         {
             /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
             qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@@ -139,7 +139,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
         else
         {
             u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
-            if(u32Div > 0xFFU)
+            if (u32Div > 0xFFU)
             {
                 u32Div = 0xFFU;
                 qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@@ -272,7 +272,7 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
     /* Get system clock frequency */
     u32HCLKFreq = CLK_GetHCLKFreq();
 
-    if(u32BusClock >= u32HCLKFreq)
+    if (u32BusClock >= u32HCLKFreq)
     {
         /* Select PCLK as the clock source of QSPI */
         if (qspi == QSPI0)
@@ -284,15 +284,15 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
     /* Check clock source of QSPI */
     if (qspi == QSPI0)
     {
-        if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+        if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
         {
             u32ClkSrc = __HXT; /* Clock source is HXT */
         }
-        else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+        else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
         {
             u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
         }
-        else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+        else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
         {
             /* Clock source is PCLK0 */
             u32ClkSrc = CLK_GetPCLK0Freq();
@@ -304,15 +304,15 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
     }
     else if (qspi == QSPI1)
     {
-        if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+        if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
         {
             u32ClkSrc = __HXT; /* Clock source is HXT */
         }
-        else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+        else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
         {
             u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
         }
-        else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+        else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
         {
             /* Clock source is PCLK1 */
             u32ClkSrc = CLK_GetPCLK1Freq();
@@ -323,21 +323,21 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
         }
     }
 
-    if(u32BusClock >= u32HCLKFreq)
+    if (u32BusClock >= u32HCLKFreq)
     {
         /* Set DIVIDER = 0 */
         qspi->CLKDIV = 0U;
         /* Return master peripheral clock rate */
         u32RetValue = u32ClkSrc;
     }
-    else if(u32BusClock >= u32ClkSrc)
+    else if (u32BusClock >= u32ClkSrc)
     {
         /* Set DIVIDER = 0 */
         qspi->CLKDIV = 0U;
         /* Return master peripheral clock rate */
         u32RetValue = u32ClkSrc;
     }
-    else if(u32BusClock == 0U)
+    else if (u32BusClock == 0U)
     {
         /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
         qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@@ -347,7 +347,7 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
     else
     {
         u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
-        if(u32Div > 0x1FFU)
+        if (u32Div > 0x1FFU)
         {
             u32Div = 0x1FFU;
             qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@@ -389,7 +389,7 @@ void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold
 uint32_t QSPI_GetBusClock(QSPI_T *qspi)
 {
     uint32_t u32Div;
-    uint32_t u32ClkSrc;
+    uint32_t u32ClkSrc = 0;
 
     /* Get DIVIDER setting */
     u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
@@ -397,15 +397,15 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
     /* Check clock source of QSPI */
     if (qspi == QSPI0)
     {
-        if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
+        if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
         {
             u32ClkSrc = __HXT; /* Clock source is HXT */
         }
-        else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
+        else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
         {
             u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
         }
-        else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+        else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
         {
             /* Clock source is PCLK0 */
             u32ClkSrc = CLK_GetPCLK0Freq();
@@ -417,15 +417,15 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
     }
     else if (qspi == QSPI1)
     {
-        if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
+        if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
         {
             u32ClkSrc = __HXT; /* Clock source is HXT */
         }
-        else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
+        else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
         {
             u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
         }
-        else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
+        else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
         {
             /* Clock source is PCLK1 */
             u32ClkSrc = CLK_GetPCLK1Freq();
@@ -463,61 +463,61 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
 {
     /* Enable unit transfer interrupt flag */
-    if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+    if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
     {
         qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
     }
 
     /* Enable slave selection signal active interrupt flag */
-    if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+    if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
     {
         qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
     }
 
     /* Enable slave selection signal inactive interrupt flag */
-    if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+    if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
     {
         qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
     }
 
     /* Enable slave TX under run interrupt flag */
-    if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+    if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
     {
         qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
     }
 
     /* Enable slave bit count error interrupt flag */
-    if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+    if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
     {
         qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
     }
 
     /* Enable slave TX underflow interrupt flag */
-    if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+    if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
     {
         qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
     }
 
     /* Enable TX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
     {
         qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
     }
 
     /* Enable RX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
     {
         qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
     }
 
     /* Enable RX overrun interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
     {
         qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
     }
 
     /* Enable RX time-out interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
     {
         qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
     }
@@ -546,61 +546,61 @@ void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
 void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
 {
     /* Disable unit transfer interrupt flag */
-    if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+    if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
     {
         qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
     }
 
     /* Disable slave selection signal active interrupt flag */
-    if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+    if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
     {
         qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
     }
 
     /* Disable slave selection signal inactive interrupt flag */
-    if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+    if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
     {
         qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
     }
 
     /* Disable slave TX under run interrupt flag */
-    if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+    if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
     {
         qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
     }
 
     /* Disable slave bit count error interrupt flag */
-    if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+    if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
     {
         qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
     }
 
     /* Disable slave TX underflow interrupt flag */
-    if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+    if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
     {
         qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
     }
 
     /* Disable TX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
     {
         qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
     }
 
     /* Disable RX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
     {
         qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
     }
 
     /* Disable RX overrun interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
     {
         qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
     }
 
     /* Disable RX time-out interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+    if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
     {
         qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
     }
@@ -632,70 +632,70 @@ uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
     /* Check unit transfer interrupt flag */
-    if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_UNIT_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
     /* Check slave selection signal active interrupt flag */
-    if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_SSACT_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
     /* Check slave selection signal inactive interrupt flag */
-    if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_SSINACT_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
     /* Check slave TX under run interrupt flag */
-    if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_SLVUR_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
     /* Check slave bit count error interrupt flag */
-    if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_SLVBE_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
     /* Check slave TX underflow interrupt flag */
-    if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_TXUF_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
     /* Check TX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
     /* Check RX threshold interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
     /* Check RX overrun interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
     }
 
     u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
     /* Check RX time-out interrupt flag */
-    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
+    if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
     {
         u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
     }
@@ -723,42 +723,42 @@ uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
   */
 void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
 {
-    if(u32Mask & QSPI_UNIT_INT_MASK)
+    if (u32Mask & QSPI_UNIT_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
     }
 
-    if(u32Mask & QSPI_SSACT_INT_MASK)
+    if (u32Mask & QSPI_SSACT_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
     }
 
-    if(u32Mask & QSPI_SSINACT_INT_MASK)
+    if (u32Mask & QSPI_SSINACT_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
     }
 
-    if(u32Mask & QSPI_SLVUR_INT_MASK)
+    if (u32Mask & QSPI_SLVUR_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
     }
 
-    if(u32Mask & QSPI_SLVBE_INT_MASK)
+    if (u32Mask & QSPI_SLVBE_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
     }
 
-    if(u32Mask & QSPI_TXUF_INT_MASK)
+    if (u32Mask & QSPI_TXUF_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
     }
 
-    if(u32Mask & QSPI_FIFO_RXOV_INT_MASK)
+    if (u32Mask & QSPI_FIFO_RXOV_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
     }
 
-    if(u32Mask & QSPI_FIFO_RXTO_INT_MASK)
+    if (u32Mask & QSPI_FIFO_RXTO_INT_MASK)
     {
         qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
     }
@@ -788,56 +788,56 @@ uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
     /* Check busy status */
-    if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_BUSY_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
     /* Check RX empty flag */
-    if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_RX_EMPTY_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
     /* Check RX full flag */
-    if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_RX_FULL_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
     /* Check TX empty flag */
-    if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_TX_EMPTY_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
     /* Check TX full flag */
-    if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_TX_FULL_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
     /* Check TX/RX reset flag */
-    if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_TXRX_RESET_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk;
     /* Check QSPIEN flag */
-    if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_QSPIEN_STS_MASK;
     }
 
     u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
     /* Check QSPIx_SS line status */
-    if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
+    if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
     {
         u32Flag |= QSPI_SSLINE_STS_MASK;
     }

bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h

@@ -18,7 +18,7 @@
 /*----------------------------------------------------------------------------------------*/
 /*   Hardware settings                                                                    */
 /*----------------------------------------------------------------------------------------*/
-#define HCLK_MHZ               192          /* used for loop-delay. must be larger than 
+#define HCLK_MHZ               192          /* used for loop-delay. must be larger than
                                                true HCLK clock MHz                        */
 
 #define ENABLE_OHCI_IRQ()      NVIC_EnableIRQ(USBH_IRQn)
@@ -29,26 +29,26 @@
 #define ENABLE_OHCI                         /* Enable OHCI host controller                */
 
 #if defined(BSP_USING_HSUSBH)
-#define ENABLE_EHCI                         /* Enable EHCI host controller                */
+    #define ENABLE_EHCI                         /* Enable EHCI host controller                */
 #endif
 
 #define EHCI_PORT_CNT          1            /* Number of EHCI roothub ports               */
 #define OHCI_PORT_CNT          2            /* Number of OHCI roothub ports               */
 #define OHCI_PER_PORT_POWER                 /* OHCI root hub per port powered             */
 
-#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling 
+#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling
                                                OHCI isochronous transfer                  */
 
-#define EHCI_ISO_DELAY         2            /* preserved number of frames while 
+#define EHCI_ISO_DELAY         2            /* preserved number of frames while
                                                scheduling EHCI isochronous transfer       */
 
-#define EHCI_ISO_RCLM_RANGE    32           /* When inspecting activated iTD/siTD, 
+#define EHCI_ISO_RCLM_RANGE    32           /* When inspecting activated iTD/siTD,
                                                unconditionally reclaim iTD/isTD scheduled
                                                in just elapsed EHCI_ISO_RCLM_RANGE ms.    */
 
-#define MAX_DESC_BUFF_SIZE     512          /* To hold the configuration descriptor, USB 
+#define MAX_DESC_BUFF_SIZE     512          /* To hold the configuration descriptor, USB
                                                core will allocate a buffer with this size
-                                               for each connected device. USB core does 
+                                               for each connected device. USB core does
                                                not release it until device disconnected.  */
 
 /*----------------------------------------------------------------------------------------*/
@@ -75,7 +75,7 @@
 /*   Re-defined staff for various compiler                                                */
 /*----------------------------------------------------------------------------------------*/
 #ifdef __ICCARM__
-#define   __inline    inline
+    #define   __inline    inline
 #endif
 
 
@@ -88,21 +88,21 @@
 //#define DUMP_DESCRIPTOR                     /* dump descriptors                           */
 
 #ifdef ENABLE_ERROR_MSG
-#define USB_error            rt_kprintf
+    #define USB_error            rt_kprintf
 #else
-#define USB_error(...)
+    #define USB_error(...)
 #endif
 
 #ifdef ENABLE_DEBUG_MSG
-#define USB_debug            rt_kprintf
-#ifdef ENABLE_VERBOSE_DEBUG
-#define USB_vdebug          rt_kprintf
+    #define USB_debug            rt_kprintf
+    #ifdef ENABLE_VERBOSE_DEBUG
+        #define USB_vdebug          rt_kprintf
+    #else
+        #define USB_vdebug(...)
+    #endif
 #else
-#define USB_vdebug(...)
-#endif
-#else
-#define USB_debug(...)
-#define USB_vdebug(...)
+    #define USB_debug(...)
+    #define USB_vdebug(...)
 #endif
 
 

bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h

@@ -51,7 +51,7 @@ extern "C"
 #define USBH_ERR_DISCONNECTED       -259   /*!< USB device was disconnected                     */
 
 #define USBH_ERR_TRANSACTION        -271   /*!< USB transaction timeout, CRC, Bad PID, etc.     */
-#define USBH_ERR_BABBLE_DETECTED    -272   /*!< A ¡§babble¡¨ is detected during the transaction   */
+#define USBH_ERR_BABBLE_DETECTED    -272   /*!< A 'babble' is detected during the transaction   */
 #define USBH_ERR_DATA_BUFF          -274   /*!< Data buffer overrun or underrun                 */
 
 #define USBH_ERR_CC_NO_ERR          -280   /*!< OHCI CC code - no error                         */
@@ -145,7 +145,7 @@ extern int  usbh_polling_root_hubs(void);
 extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
 extern void usbh_suspend(void);
 extern void usbh_resume(void);
-extern struct udev_t * usbh_find_device(char *hub_id, int port);
+extern struct udev_t *usbh_find_device(char *hub_id, int port);
 
 /**
  * @brief  A function return current tick count.

bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c

@@ -29,13 +29,13 @@ extern int ehci_iso_xfer(UTR_T *utr);       /* EHCI isochronous transfer functio
 extern int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
 
 #ifdef __ICCARM__
-#pragma data_alignment=4096
-uint32_t  _PFList[FL_SIZE];                 /* Periodic frame list (IAR)                  */
+    #pragma data_alignment=4096
+    uint32_t  _PFList[FL_SIZE];                 /* Periodic frame list (IAR)                  */
 #else
-uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096)));  /* Periodic frame list         */
+    uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096)));  /* Periodic frame list         */
 #endif
 
-QH_T  * _Iqh[NUM_IQH];
+QH_T   *_Iqh[NUM_IQH];
 
 
 #ifdef ENABLE_ERROR_MSG
@@ -65,7 +65,7 @@ void dump_ehci_qtd(qTD_T *qtd)
     USB_debug("    [qTD] - 0x%08x\n", (int)qtd);
     USB_debug("        0x%08x (Next qtd Pointer)\n", qtd->Next_qTD);
     USB_debug("        0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD);
-    USB_debug("        0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token>>8)&0x3)==0) ? "OUT" : ((((qtd->Token>>8)&0x3)==1) ? "IN" : "SETUP"), (qtd->Token>>16)&0x7FFF, (qtd->Token>>15)&0x1);
+    USB_debug("        0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token >> 8) & 0x3) == 0) ? "OUT" : ((((qtd->Token >> 8) & 0x3) == 1) ? "IN" : "SETUP"), (qtd->Token >> 16) & 0x7FFF, (qtd->Token >> 15) & 0x1);
     USB_debug("        0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]);
     //USB_debug("        0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]);
     //USB_debug("        0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]);
@@ -84,7 +84,7 @@ void dump_ehci_asynclist(void)
     {
         USB_debug("[QH] - 0x%08x\n", (int)qh);
         USB_debug("    0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink);
-        USB_debug("    0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst&0x7F, (qh->Chrst>>8)&0xF, (qh->Chrst>>16)&0x7FF, ((qh->Chrst>>12)&0x3 == 0) ? "Full" : (((qh->Chrst>>12)&0x3 == 1) ? "Low" : "High"));
+        USB_debug("    0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst & 0x7F, (qh->Chrst >> 8) & 0xF, (qh->Chrst >> 16) & 0x7FF, ((qh->Chrst >> 12) & 0x3 == 0) ? "Full" : (((qh->Chrst >> 12) & 0x3 == 1) ? "Low" : "High"));
         USB_debug("    0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap);
         USB_debug("    0x%08x (Current qtd Pointer)\n", qh->Curr_qTD);
         USB_debug("    --- Overlay Area ---\n");
@@ -122,7 +122,7 @@ void dump_ehci_asynclist_simple(void)
 
 void dump_ehci_period_frame_list_simple(void)
 {
-    QH_T     *qh = _Iqh[NUM_IQH-1];
+    QH_T     *qh = _Iqh[NUM_IQH - 1];
 
     USB_debug(">>> EHCI period frame list simple <<<\n");
     USB_debug("[FList] => ");
@@ -165,7 +165,7 @@ static void init_periodic_frame_list()
 
     iso_ep_list = NULL;
 
-    for (i = NUM_IQH-1; i >= 0; i--)        /* interval = i^2                             */
+    for (i = NUM_IQH - 1; i >= 0; i--)      /* interval = i^2                             */
     {
         _Iqh[i] = alloc_ehci_QH();
 
@@ -204,19 +204,19 @@ static void init_periodic_frame_list()
     }
 }
 
-static QH_T * get_int_tree_head_node(int interval)
+static QH_T *get_int_tree_head_node(int interval)
 {
     int    i;
 
     interval /= 8;                          /* each frame list entry for 8 micro-frame    */
 
-    for (i = 0; i < NUM_IQH-1; i++)
+    for (i = 0; i < NUM_IQH - 1; i++)
     {
         interval >>= 1;
         if (interval == 0)
             return _Iqh[i];
     }
-    return _Iqh[NUM_IQH-1];
+    return _Iqh[NUM_IQH - 1];
 }
 
 static int  make_int_s_mask(int bInterval)
@@ -245,7 +245,7 @@ static int  make_int_s_mask(int bInterval)
 
 static int  ehci_init(void)
 {
-    int      timeout = 250*1000;            /* EHCI reset time-out 250 ms                */
+    int      timeout = 250 * 1000;          /* EHCI reset time-out 250 ms                */
 
     /*------------------------------------------------------------------------------------*/
     /*  Reset EHCI host controller                                                        */
@@ -283,11 +283,11 @@ static int  ehci_init(void)
     /*  Initialize periodic list                                                          */
     /*------------------------------------------------------------------------------------*/
     if (FL_SIZE == 256)
-        _ehci->UCMDR |= (0x2<<HSUSBH_UCMDR_FLSZ_Pos);
+        _ehci->UCMDR |= (0x2 << HSUSBH_UCMDR_FLSZ_Pos);
     else if (FL_SIZE == 512)
-        _ehci->UCMDR |= (0x1<<HSUSBH_UCMDR_FLSZ_Pos);
+        _ehci->UCMDR |= (0x1 << HSUSBH_UCMDR_FLSZ_Pos);
     else if (FL_SIZE == 1024)
-        _ehci->UCMDR |= (0x0<<HSUSBH_UCMDR_FLSZ_Pos);
+        _ehci->UCMDR |= (0x0 << HSUSBH_UCMDR_FLSZ_Pos);
     else
         return USBH_ERR_EHCI_INIT;               /* Invalid FL_SIZE setting!              */
 
@@ -371,7 +371,7 @@ static void move_qh_to_remove_list(QH_T *qh)
     /*------------------------------------------------------------------------------------*/
     /*  Search periodic frame list and remove qh if found in list.                        */
     /*------------------------------------------------------------------------------------*/
-    q =  _Iqh[NUM_IQH-1];
+    q =  _Iqh[NUM_IQH - 1];
     while (q->HLink != QH_HLNK_END)
     {
         if (QH_PTR(q->HLink) == qh)
@@ -508,7 +508,7 @@ static int ehci_ctrl_xfer(UTR_T *utr)
 
     if (utr->data_len > 0)
     {
-        if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF)+0x5000))
+        if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF) + 0x5000))
             return USBH_ERR_BUFF_OVERRUN;
     }
 
@@ -918,7 +918,7 @@ static int visit_qtd(qTD_T *qtd)
 static void scan_asynchronous_list()
 {
     QH_T    *qh, *qh_tmp;
-    qTD_T   *q_pre=NULL, *qtd, *qtd_tmp;
+    qTD_T   *q_pre = NULL, *qtd, *qtd_tmp;
     UTR_T   *utr;
 
     qh =  QH_PTR(_H_qh->HLink);
@@ -982,7 +982,7 @@ static void scan_periodic_frame_list()
     /*------------------------------------------------------------------------------------*/
     /* Scan interrupt frame list                                                          */
     /*------------------------------------------------------------------------------------*/
-    qh =  _Iqh[NUM_IQH-1];
+    qh =  _Iqh[NUM_IQH - 1];
     while (qh != NULL)
     {
         qtd = qh->qtd_list;
@@ -1095,7 +1095,7 @@ void iaad_remove_qh()
     /*------------------------------------------------------------------------------------*/
     /* Free all qTD in done_list of each QH of periodic frame list                        */
     /*------------------------------------------------------------------------------------*/
-    qh =  _Iqh[NUM_IQH-1];
+    qh =  _Iqh[NUM_IQH - 1];
     while (qh != NULL)
     {
         while (qh->done_list)               /* we can free the qTDs now                   */
@@ -1138,7 +1138,7 @@ void EHCI_IRQHandler(void)
     }
 }
 
-static UDEV_T * ehci_find_device_by_port(int port)
+static UDEV_T *ehci_find_device_by_port(int port)
 {
     UDEV_T  *udev;
 
@@ -1165,12 +1165,12 @@ static int ehci_rh_port_reset(int port)
         _ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
 
         t0 = usbh_get_ticks();
-        while (usbh_get_ticks() - t0 <  (reset_time)+1) ;     /* wait at least 50 ms        */
+        while (usbh_get_ticks() - t0 < (reset_time) + 1) ;    /* wait at least 50 ms        */
 
         _ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
 
         t0 = usbh_get_ticks();
-        while (usbh_get_ticks() - t0 < (reset_time)+1)
+        while (usbh_get_ticks() - t0 < (reset_time) + 1)
         {
             if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
                     ((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
@@ -1179,7 +1179,7 @@ static int ehci_rh_port_reset(int port)
         reset_time += PORT_RESET_RETRY_INC_MS;
     }
 
-    USB_debug("EHCI port %d - port reset failed!\n", port+1);
+    USB_debug("EHCI port %d - port reset failed!\n", port + 1);
     return USBH_ERR_PORT_RESET;
 
 port_reset_done:
@@ -1222,7 +1222,7 @@ static int ehci_rh_polling(void)
     /*  Port de-bounce                                                                */
     /*--------------------------------------------------------------------------------*/
     t0 = usbh_get_ticks();
-	debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
+    debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
     connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk;
     while (usbh_get_ticks() - t0 < debounce_tick)
     {

bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c

@@ -22,7 +22,7 @@
 USBH_T     *_ohci;
 HSUSBH_T   *_ehci;
 
-static UDEV_DRV_T *  _drivers[MAX_UDEV_DRIVER];
+static UDEV_DRV_T   *_drivers[MAX_UDEV_DRIVER];
 static CONN_FUNC  *g_conn_func, *g_disconn_func;
 
 /**
@@ -130,7 +130,7 @@ int usbh_connect_device(UDEV_T *udev)
 
     if (g_conn_func)
         g_conn_func(udev, 0);
-    
+
     return 0;
 }
 
@@ -142,8 +142,8 @@ void usbh_disconnect_device(UDEV_T *udev)
     if (g_disconn_func)
         g_disconn_func(udev, 0);
 
-    
-#if 1    //CHECK: Maybe create a new API to quit_xfer and free udev for application    
+
+#if 1    //CHECK: Maybe create a new API to quit_xfer and free udev for application
     usbh_quit_xfer(udev, &(udev->ep0));    /* Quit control transfer if hw_pipe is not NULL.  */
 
     /* remove device from global device list */
@@ -172,7 +172,7 @@ int usbh_reset_port(UDEV_T *udev)
     if (udev->parent == NULL)
     {
         if (udev->hc_driver)
-            return udev->hc_driver->rthub_port_reset(udev->port_num-1);
+            return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
         else
             return USBH_ERR_NOT_FOUND;
     }

bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c

@@ -100,7 +100,7 @@ rt_err_t nu_crc_init(void)
 
     SYS_ResetModule(CRC_RST);
 
-    result = rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
     return RT_EOK;

bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c

@@ -91,18 +91,18 @@ static rt_err_t nu_crypto_init(void)
     SHA_ENABLE_INT(CRPT);
 
     //init cipher mutex
-    result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
-    result = rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
-    result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
 #if !defined(BSP_USING_TRNG)
     PRNG_ENABLE_INT(CRPT);
-    result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 #endif
 

bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c

@@ -484,7 +484,7 @@ int nu_epwm_capture_device_init(void)
 
         }
     }
-#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0) 
+#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
 #if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
     for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
     {

bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c

@@ -331,7 +331,7 @@ static int nu_fmc_init(void)
     FMC_ENABLE_ISP();
     SYS_LockReg();
 
-    g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
+    g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_PRIO);
     RT_ASSERT(g_mutex_fmc != RT_NULL);
 
     /* PKG_USING_FAL */

bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c

@@ -208,10 +208,10 @@ static void nu_pdma_init(void)
     if (nu_pdma_inited)
         return;
 
-    g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_FIFO);
+    g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_PRIO);
     RT_ASSERT(g_mutex_res != RT_NULL);
 
-    g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
+    g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_PRIO);
     RT_ASSERT(g_mutex_sg != RT_NULL);
 
     nu_pdma_chn_mask = ~NU_PDMA_CH_Msk;
@@ -894,7 +894,7 @@ static void nu_pdma_memfun_actor_init(void)
         nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
         RT_ASSERT(nu_pdma_memfun_actor_pool_sem != RT_NULL);
 
-        nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
+        nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO);
         RT_ASSERT(nu_pdma_memfun_actor_pool_lock != RT_NULL);
     }
 }

bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c

@@ -180,10 +180,10 @@ exit_nu_qspi_bus_configure:
     return -(ret);
 }
 
-#if defined(RT_SFUD_USING_QSPI)
 static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
 {
     QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
+#if defined(RT_SFUD_USING_QSPI)
     if (qspi_lines > 1)
     {
         if (tx)
@@ -218,13 +218,13 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8
         }
     }
     else
+#endif
     {
         QSPI_DISABLE_DUAL_MODE(qspi_base);
         QSPI_DISABLE_QUAD_MODE(qspi_base);
     }
     return qspi_lines;
 }
-#endif
 
 static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
@@ -317,9 +317,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
                         qspi_message->dummy_cycles / (8 / u8last),
                         1);
     }
-
     /* Data stage */
     nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
+#else
+    /* Data stage */
+    nu_qspi_mode_config(qspi_bus, RT_NULL, RT_NULL, 1);
 #endif //#if defined(RT_SFUD_USING_QSPI)
 
     if (message->length != 0)
@@ -369,8 +371,7 @@ static int rt_hw_qspi_init(void)
 #if defined(BSP_USING_SPI_PDMA)
         nu_qspi_arr[i].pdma_chanid_tx = -1;
         nu_qspi_arr[i].pdma_chanid_rx = -1;
-#endif
-#if defined(BSP_USING_QSPI_PDMA)
+
         if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
         {
             if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)

bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c

@@ -212,6 +212,6 @@ int rt_soft_i2c_init(void)
 
     return 0;
 }
-INIT_BOARD_EXPORT(rt_soft_i2c_init);
+INIT_DEVICE_EXPORT(rt_soft_i2c_init);
 
 #endif //#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN))

bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c

@@ -50,7 +50,7 @@ rt_err_t nu_trng_init(void)
 {
     rt_err_t result;
 
-    result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO);
+    result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_PRIO);
     RT_ASSERT(result == RT_EOK);
 
     if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)

bsp/nuvoton/libraries/n9h30/Driver/Include/N9H30.h

@@ -0,0 +1,2097 @@
+/**************************************************************************//**
+ * @file     N9H30.h
+ * @version  V1.00
+ * @brief    N9H30 peripheral access layer header file.
+ *           This file contains all the peripheral register's definitions
+ *           and memory mapping for NuMicro N9H30 MCU.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+/**
+   \mainpage NuMicro N9H30 Family Driver Reference Guide
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the usage of N9H30 family device driver
+   *
+   * <b>Disclaimer</b>
+   *
+   * The Software is furnished "AS IS", without warranty as to performance or results, and
+   * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+   * warranties, express, implied or otherwise, with regard to the Software, its use, or
+   * operation, including without limitation any and all warranties of merchantability, fitness
+   * for a particular purpose, and non-infringement of intellectual property rights.
+   *
+   * <b>Important Notice</b>
+   *
+   * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+   * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+   * property damage. Such applications are deemed, "Insecure Usage".
+   *
+   * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+   * atomic energy control instruments, airplane or spaceship instruments, the control or
+   * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+   * instruments, all types of safety devices, and other applications intended to support or
+   * sustain life.
+   *
+   * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+   * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+   * the damages and liabilities thus incurred by Nuvoton.
+   *
+   * Please note that all data and specifications are subject to change without notice. All the
+   * trademarks of products and companies mentioned in this document belong to their respective
+   * owners.
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+   */
+
+#ifndef __N9H30_H__
+    #define __N9H30_H__
+
+    #include <stdint.h>
+
+    /** @addtogroup N9H30_PERIPHERAL_MEM_MAP N9H30 Peripheral Memory Base
+    Memory Mapped Structure for N9H30 Peripheral
+    @{
+    */
+
+    /*!< AHB peripherals */
+    #define    SYS_BA    0xB0000000  /*!< System Global Control */
+    #define    CLK_BA    0xB0000200  /*!< Clock Control */
+    #define    EBI_BA    0xB0001000  /*!< EBI Control */
+    #define    SDIC_BA   0xB0001800  /*!< SDRAM (SDR/DDR/DDR2) Control */
+    #define    EMC0_BA   0xB0002000  /*!< Ethernet MAC 0 Control */
+    #define    EMC1_BA   0xB0003000  /*!< Ethernet MAC 1 Control */
+    #define    GDMA_BA   0xB0004000  /*!< GDMA control */
+    #define    USBH_BA   0xB0005000  /*!< USB Host EHCI Control */
+    #define    USBD_BA   0xB0006000  /*!< USB Device Control */
+    #define    USBO_BA   0xB0007000  /*!< OHCI USB Host Control */
+    #define    LCM_BA    0xB0008000  /*!< Display, LCM Interface */
+    #define    ACTL_BA   0xB0009000  /*!< Audio Control */
+    #define    JPEG_BA   0xB000A000  /*!< JPEG Engine Control */
+    #define    GE_BA     0xB000B000  /*!< 2-D Graphic Engine */
+    #define    SDH_BA    0xB000C000  /*!< SD/SDIO Host Controller */
+    #define    FMI_BA    0xB000D000  /*!< Flash Memory Card Interface */
+    #define    CAP_BA    0xB000E000  /*!< Sensor (Capture) Interface Control */
+    #define    CRPT_BA   0xB000F000  /*!< Crypto Engine Control */
+
+    /*!< APB peripherals */
+    #define    UART0_BA  0xB8000000  /*!< UART0 Control */
+    #define    UART1_BA  0xB8000100  /*!< UART1 Control (High-Speed UART) */
+    #define    UART2_BA  0xB8000200  /*!< UART2 Control (High-Speed UART) */
+    #define    UART3_BA  0xB8000300  /*!< UART3 Control  */
+    #define    UART4_BA  0xB8000400  /*!< UART4 Control (High-Speed UART) */
+    #define    UART5_BA  0xB8000500  /*!< UART5 Control */
+    #define    UART6_BA  0xB8000600  /*!< UART6 Control (High-Speed UART) */
+    #define    UART7_BA  0xB8000700  /*!< UART7 Control */
+    #define    UART8_BA  0xB8000800  /*!< UART8 Control (High-Speed UART) */
+    #define    UART9_BA  0xB8000900  /*!< UART9 Control */
+    #define    UARTA_BA  0xB8000A00  /*!< UARTA Control (High-Speed UART) */
+    #define    TMR0_BA   0xB8001000  /*!< Timer 0 */
+    #define    TMR1_BA   0xB8001010  /*!< Timer 1 */
+    #define    TMR2_BA   0xB8001020  /*!< Timer 2 */
+    #define    TMR3_BA   0xB8001030  /*!< Timer 3 */
+    #define    TMR4_BA   0xB8001040  /*!< Timer 4 */
+    #define    ETMR0_BA  0xB8001400  /*!< Enhanced Timer 0 */
+    #define    ETMR1_BA  0xB8001500  /*!< Enhanced Timer 1 */
+    #define    ETMR2_BA  0xB8001600  /*!< Enhanced Timer 2 */
+    #define    ETMR3_BA  0xB8001700  /*!< Enhanced Timer 3 */
+    #define    WDT_BA    0xB8001800  /*!< Watch Dog Timer */
+    #define    WWDT_BA   0xB8001900  /*!< Window Watch Dog Timer */
+    #define    AIC_BA    0xB8002000  /*!< Interrupt Controller */
+    #define    GPIO_BA   0xB8003000  /*!< GPIO Control */
+    #define    RTC_BA    0xB8004000  /*!< Real Time Clock Control */
+    #define    SC0_BA    0xB8005000  /*!< Smart Card 0 Control */
+    #define    SC1_BA    0xB8005400  /*!< Smart Card 1 Control */
+    #define    I2C0_BA   0xB8006000  /*!< I2C 0 Control */
+    #define    I2C1_BA   0xB8006100  /*!< I2C 1 Control */
+    #define    SPI0_BA   0xB8006200  /*!< Serial Peripheral Interface 0 */
+    #define    SPI1_BA   0xB8006300  /*!< Serial Peripheral Interface 1 */
+    #define    PWM_BA    0xB8007000  /*!< Pulse Width Modulation (PWM) Control */
+    #define    ADC_BA    0xB800A000  /*!< ADC Control */
+    #define    CAN0_BA   0xB800B000  /*!< CAN 0 Control */
+    #define    CAN1_BA   0xB800B400  /*!< CAN 1 Control */
+    #define    MTP_BA    0xB800C000  /*!< MTP Control */
+
+    /*@}*/ /* end of group N9H30_PERIPHERAL_MEM_MAP */
+
+    /******************************************************************************/
+    /*                Device Specific Peripheral registers structures             */
+    /******************************************************************************/
+    /** @addtogroup N9H30_Peripherals N9H30 Control Register
+    N9H30 Device Specific Peripheral registers structures
+    @{
+    */
+
+    /*---------------------- System Manger Controller -------------------------*/
+    /**
+    @addtogroup SYS System Manger Controller(SYS)
+    Memory Mapped Structure for SYS Controller
+    @{ */
+
+    #define    REG_SYS_PDID         (SYS_BA+0x000)  /*!< Product Identifier Register */
+    #define    REG_SYS_PWRON        (SYS_BA+0x004)  /*!< Power-On Setting Register */
+    #define    REG_SYS_ARBCON       (SYS_BA+0x008)  /*!< Arbitration Control Register */
+    #define    REG_SYS_LVRDCR       (SYS_BA+0x020)  /*!< Low Voltage Reset & Detect Control Register */
+    #define    REG_SYS_MISCFCR      (SYS_BA+0x030)  /*!< Miscellaneous Function Control Register */
+    #define    REG_SYS_MISCIER      (SYS_BA+0x040)  /*!< Miscellaneous Interrupt Enable Register */
+    #define    REG_SYS_MISCISR      (SYS_BA+0x044)  /*!< Miscellaneous Interrupt Status Register */
+    #define    REG_SYS_WKUPSER      (SYS_BA+0x058)  /*!< System Wakeup Source Enable Register */
+    #define    REG_SYS_WKUPSSR      (SYS_BA+0x05C)  /*!< System Wakeup Source Status Register */
+    #define    REG_SYS_AHBIPRST     (SYS_BA+0x060)  /*!< AHB IP Reset Control Register */
+    #define    REG_SYS_APBIPRST0    (SYS_BA+0x064)  /*!< APB IP Reset Control Register 0 */
+    #define    REG_SYS_APBIPRST1    (SYS_BA+0x068)  /*!< APB IP Reset Control Register 1 */
+    #define    REG_SYS_RSTSTS       (SYS_BA+0x06C)  /*!< Reset Source Active Status Register */
+    #define    REG_SYS_GPA_MFPL     (SYS_BA+0x070)  /*!< GPIOA Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPA_MFPH     (SYS_BA+0x074)  /*!< GPIOA High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPB_MFPL     (SYS_BA+0x078)  /*!< GPIOB Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPB_MFPH     (SYS_BA+0x07C)  /*!< GPIOB High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPC_MFPL     (SYS_BA+0x080)  /*!< GPIOC Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPC_MFPH     (SYS_BA+0x084)  /*!< GPIOC High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPD_MFPL     (SYS_BA+0x088)  /*!< GPIOD Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPD_MFPH     (SYS_BA+0x08C)  /*!< GPIOD High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPE_MFPL     (SYS_BA+0x090)  /*!< GPIOE Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPE_MFPH     (SYS_BA+0x094)  /*!< GPIOE High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPF_MFPL     (SYS_BA+0x098)  /*!< GPIOF Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPF_MFPH     (SYS_BA+0x09C)  /*!< GPIOF High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPG_MFPL     (SYS_BA+0x0A0)  /*!< GPIOG Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPG_MFPH     (SYS_BA+0x0A4)  /*!< GPIOG High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPH_MFPL     (SYS_BA+0x0A8)  /*!< GPIOH Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPH_MFPH     (SYS_BA+0x0AC)  /*!< GPIOH High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPI_MFPL     (SYS_BA+0x0B0)  /*!< GPIOI Low Byte Multiple Function Control Register */
+    #define    REG_SYS_GPI_MFPH     (SYS_BA+0x0B4)  /*!< GPIOI High Byte Multiple Function Control Register */
+    #define    REG_SYS_GPJ_MFPL     (SYS_BA+0x0B8)  /*!< GPIOJ Low Byte Multiple Function Control Register */
+    #define    REG_SYS_DDR_DSCTL    (SYS_BA+0x0F0)  /*!< DDR I/O Driving Strength Control Register */
+    #define    REG_SYS_PORDISCR     (SYS_BA+0x100)  /*!< Power-On-Reset Disable Control Register */
+    #define    REG_SYS_ICEDBGCR     (SYS_BA+0x104)  /*!< ICE Debug Interface Control Register */
+    #define    REG_SYS_ERRADDCR     (SYS_BA+0x108)  /*!< Error Response Address Control Regsiter */
+    #define    REG_SYS_REGWPCTL     (SYS_BA+0x1FC)  /*!< Register Write-Protection Control Register */
+
+    /**@}*/ /* end of SYS register group */
+
+    /*---------------------- System Clock Controller -------------------------*/
+    /**
+    @addtogroup CLK System Clock Controller(CLK)
+    Memory Mapped Structure for CLK Controller
+    @{ */
+
+    #define    REG_CLK_PMCON        (CLK_BA+0x00) /*!< Power Management Control Register */
+    #define    REG_CLK_HCLKEN       (CLK_BA+0x10) /*!< AHB IP Clock Enable Control Register */
+    #define    REG_CLK_PCLKEN0      (CLK_BA+0x18) /*!< APB IP Clock Enable Control Register 0 */
+    #define    REG_CLK_PCLKEN1      (CLK_BA+0x1C) /*!< APB IP Clock Enable Control Register 1 */
+    #define    REG_CLK_DIVCTL0      (CLK_BA+0x20) /*!< Clock Divider Control Register 0 */
+    #define    REG_CLK_DIVCTL1      (CLK_BA+0x24) /*!< Clock Divider Control Register 1 */
+    #define    REG_CLK_DIVCTL2      (CLK_BA+0x28) /*!< Clock Divider Control Register 2 */
+    #define    REG_CLK_DIVCTL3      (CLK_BA+0x2C) /*!< Clock Divider Control Register 3 */
+    #define    REG_CLK_DIVCTL4      (CLK_BA+0x30) /*!< Clock Divider Control Register 4 */
+    #define    REG_CLK_DIVCTL5      (CLK_BA+0x34) /*!< Clock Divider Control Register 5 */
+    #define    REG_CLK_DIVCTL6      (CLK_BA+0x38) /*!< Clock Divider Control Register 6 */
+    #define    REG_CLK_DIVCTL7      (CLK_BA+0x3C) /*!< Clock Divider Control Register 7 */
+    #define    REG_CLK_DIVCTL8      (CLK_BA+0x40) /*!< Clock Divider Control Register 8 */
+    #define    REG_CLK_DIVCTL9      (CLK_BA+0x44) /*!< Clock Divider Control Register 9 */
+    #define    REG_CLK_APLLCON      (CLK_BA+0x60) /*!< APLL Control Register */
+    #define    REG_CLK_UPLLCON      (CLK_BA+0x64) /*!< UPLL Control Register */
+    #define    REG_CLK_PLLSTBCNTR   (CLK_BA+0x80) /*!< PLL Stable Counter and Test Clock Control Register */
+
+    /**@}*/ /* end of CLK register group */
+
+
+    /*---------------------- External Bus Interface Controller -------------------------*/
+    /**
+    @addtogroup EBI External Bus Interface Controller(EBI)
+    Memory Mapped Structure for EBI Controller
+    @{ */
+
+    #define    REG_EBI_CTL          (EBI_BA+0x000)  /*!< EBI control register */
+    #define    REG_EBI_BNKCTL0      (EBI_BA+0x018)  /*!< External I/O 0 control register */
+    #define    REG_EBI_BNKCTL1      (EBI_BA+0x01C)  /*!< External I/O 1 control register */
+    #define    REG_EBI_BNKCTL2      (EBI_BA+0x020)  /*!< External I/O 2 control register */
+    #define    REG_EBI_BNKCTL3      (EBI_BA+0x024)  /*!< External I/O 3 control register */
+    #define    REG_EBI_BNKCTL4      (EBI_BA+0x028)  /*!< External I/O 4 control register */
+
+    /**@}*/ /* end of EBI register group */
+
+
+    /*---------------------- Ethernet MAC Controller -------------------------*/
+    /**
+    @addtogroup EMAC Ethernet MAC Controller(EMAC)
+    Memory Mapped Structure for EMAC Controller
+    @{ */
+
+    #define     REG_EMAC0_CAMCMR      (EMC0_BA+0x000) /*!< CAM Command Register */
+    #define     REG_EMAC0_CAMEN       (EMC0_BA+0x004) /*!< CAM Enable Register */
+    #define     REG_EMAC0_CAM0M       (EMC0_BA+0x008)  /*!< CAM0 Most Significant Word Register */
+    #define     REG_EMAC0_CAM0L       (EMC0_BA+0x00c)  /*!< CAM0 Least Significant Word Register */
+    #define     REG_EMAC0_CAMxM_Reg(x)(REG_EMAC0_CAM0M+(x)*0x8)  /*!< CAMx Most Significant Word Register */
+    #define     REG_EMAC0_CAMxL_Reg(x)(REG_EMAC0_CAM0L+(x)*0x8)  /*!< CAMx Least Significant Word Register */
+    #define     REG_EMAC0_TXDLSA      (EMC0_BA+0x088) /*!< Transmit Descriptor Link List Start Address Register */
+    #define     REG_EMAC0_RXDLSA      (EMC0_BA+0x08C) /*!< Receive Descriptor Link List Start Address Register */
+    #define     REG_EMAC0_MCMDR       (EMC0_BA+0x090) /*!< MAC Command Register */
+    #define     REG_EMAC0_MIID        (EMC0_BA+0x094) /*!< MII Management Data Register */
+    #define     REG_EMAC0_MIIDA       (EMC0_BA+0x098) /*!< MII Management Control and Address Register */
+    #define     REG_EMAC0_FFTCR       (EMC0_BA+0x09C) /*!< FIFO Threshold Control Register */
+    #define     REG_EMAC0_TSDR        (EMC0_BA+0x0a0) /*!< Transmit Start Demand Register */
+    #define     REG_EMAC0_RSDR        (EMC0_BA+0x0a4) /*!< Receive Start Demand Register */
+    #define     REG_EMAC0_DMARFC      (EMC0_BA+0x0a8) /*!< Maximum Receive Frame Control Register */
+    #define     REG_EMAC0_MIEN        (EMC0_BA+0x0ac) /*!< MAC Interrupt Enable Register */
+    #define     REG_EMAC0_MISTA       (EMC0_BA+0x0b0) /*!< MAC Interrupt Status Register */
+    #define     REG_EMAC0_MGSTA       (EMC0_BA+0x0b4) /*!< MAC General Status Register */
+    #define     REG_EMAC0_MPCNT       (EMC0_BA+0x0b8) /*!< Missed Packet Count Register */
+    #define     REG_EMAC0_MRPC        (EMC0_BA+0x0bc) /*!< MAC Receive Pause Count Register */
+    #define     REG_EMAC0_DMARFS      (EMC0_BA+0x0c8) /*!< DMA Receive Frame Status Register */
+    #define     REG_EMAC0_CTXDSA      (EMC0_BA+0x0cc) /*!< Current Transmit Descriptor Start Address Register */
+    #define     REG_EMAC0_CTXBSA      (EMC0_BA+0x0d0) /*!< Current Transmit Buffer Start Address Register */
+    #define     REG_EMAC0_CRXDSA      (EMC0_BA+0x0d4) /*!< Current Receive Descriptor Start Address Register */
+    #define     REG_EMAC0_CRXBSA      (EMC0_BA+0x0d8) /*!< Current Receive Buffer Start Address Register */
+    #define     REG_EMAC0_TSCTL       (EMC0_BA+0x100) /*!< Time Stamp Control Register */
+    #define     REG_EMAC0_TSSEC       (EMC0_BA+0x110) /*!< Time Stamp Counter Second Register */
+    #define     REG_EMAC0_TSSUBSEC    (EMC0_BA+0x114) /*!< Time Stamp Counter Sub Second Register */
+    #define     REG_EMAC0_TSINC       (EMC0_BA+0x118) /*!< Time Stamp Increment Register  */
+    #define     REG_EMAC0_TSADDEN     (EMC0_BA+0x11c) /*!< Time Stamp Addend Register */
+    #define     REG_EMAC0_TSUPDSEC    (EMC0_BA+0x120) /*!< Time Stamp Update Second Register */
+    #define     REG_EMAC0_TSUPDSUBSEC (EMC0_BA+0x124) /*!< Time Stamp Update Sub Second Register */
+    #define     REG_EMAC0_TSALMSEC    (EMC0_BA+0x128) /*!< Time Stamp Alarm Second Register */
+    #define     REG_EMAC0_TSALMSUBSEC (EMC0_BA+0x12c) /*!< Time Stamp Alarm Sub Second Register */
+
+    #define     REG_EMAC1_CAMCMR      (EMC1_BA+0x000) /*!< CAM Command Register */
+    #define     REG_EMAC1_CAMEN       (EMC1_BA+0x004) /*!< CAM Enable Register */
+    #define     REG_EMAC1_CAM0M       (EMC1_BA+0x008)  /*!< CAM0 Most Significant Word Register */
+    #define     REG_EMAC1_CAM0L       (EMC1_BA+0x00c)  /*!< CAM0 Least Significant Word Register */
+    #define     REG_EMAC1_CAMxM_Reg(x)(REG_EMAC1_CAM0M+(x)*0x8)  /*!< CAMx Most Significant Word Register */
+    #define     REG_EMAC1_CAMxL_Reg(x)(REG_EMAC1_CAM0L+(x)*0x8)  /*!< CAMx Least Significant Word Register */
+    #define     REG_EMAC1_TXDLSA      (EMC1_BA+0x088) /*!< Transmit Descriptor Link List Start Address Register */
+    #define     REG_EMAC1_RXDLSA      (EMC1_BA+0x08C) /*!< Receive Descriptor Link List Start Address Register */
+    #define     REG_EMAC1_MCMDR       (EMC1_BA+0x090) /*!< MAC Command Register */
+    #define     REG_EMAC1_MIID        (EMC1_BA+0x094) /*!< MII Management Data Register */
+    #define     REG_EMAC1_MIIDA       (EMC1_BA+0x098) /*!< MII Management Control and Address Register */
+    #define     REG_EMAC1_FFTCR       (EMC1_BA+0x09C) /*!< FIFO Threshold Control Register */
+    #define     REG_EMAC1_TSDR        (EMC1_BA+0x0a0) /*!< Transmit Start Demand Register */
+    #define     REG_EMAC1_RSDR        (EMC1_BA+0x0a4) /*!< Receive Start Demand Register */
+    #define     REG_EMAC1_DMARFC      (EMC1_BA+0x0a8) /*!< Maximum Receive Frame Control Register */
+    #define     REG_EMAC1_MIEN        (EMC1_BA+0x0ac) /*!< MAC Interrupt Enable Register */
+    #define     REG_EMAC1_MISTA       (EMC1_BA+0x0b0) /*!< MAC Interrupt Status Register */
+    #define     REG_EMAC1_MGSTA       (EMC1_BA+0x0b4) /*!< MAC General Status Register */
+    #define     REG_EMAC1_MPCNT       (EMC1_BA+0x0b8) /*!< Missed Packet Count Register */
+    #define     REG_EMAC1_MRPC        (EMC1_BA+0x0bc) /*!< MAC Receive Pause Count Register */
+    #define     REG_EMAC1_DMARFS      (EMC1_BA+0x0c8) /*!< DMA Receive Frame Status Register */
+    #define     REG_EMAC1_CTXDSA      (EMC1_BA+0x0cc) /*!< Current Transmit Descriptor Start Address Register */
+    #define     REG_EMAC1_CTXBSA      (EMC1_BA+0x0d0) /*!< Current Transmit Buffer Start Address Register */
+    #define     REG_EMAC1_CRXDSA      (EMC1_BA+0x0d4) /*!< Current Receive Descriptor Start Address Register */
+    #define     REG_EMAC1_CRXBSA      (EMC1_BA+0x0d8) /*!< Current Receive Buffer Start Address Register */
+    #define     REG_EMAC1_TSCTL       (EMC1_BA+0x100) /*!< Time Stamp Control Register */
+    #define     REG_EMAC1_TSSEC       (EMC1_BA+0x110) /*!< Time Stamp Counter Second Register */
+    #define     REG_EMAC1_TSSUBSEC    (EMC1_BA+0x114) /*!< Time Stamp Counter Sub Second Register */
+    #define     REG_EMAC1_TSINC       (EMC1_BA+0x118) /*!< Time Stamp Increment Register  */
+    #define     REG_EMAC1_TSADDEN     (EMC1_BA+0x11c) /*!< Time Stamp Addend Register */
+    #define     REG_EMAC1_TSUPDSEC    (EMC1_BA+0x120) /*!< Time Stamp Update Second Register */
+    #define     REG_EMAC1_TSUPDSUBSEC (EMC1_BA+0x124) /*!< Time Stamp Update Sub Second Register */
+    #define     REG_EMAC1_TSALMSEC    (EMC1_BA+0x128) /*!< Time Stamp Alarm Second Register */
+    #define     REG_EMAC1_TSALMSUBSEC (EMC1_BA+0x12c) /*!< Time Stamp Alarm Sub Second Register */
+
+    /**@}*/ /* end of EMAC register group */
+
+    /*----------------------  General Direct Memory Access Controller -------------------------*/
+    /**
+    @addtogroup GDMA  General Direct Memory Access Controller(GDMA)
+    Memory Mapped Structure for GDMA Controller
+    @{ */
+
+    #define     REG_GDMA_CTL0   (GDMA_BA+0x000)  /*!< Channel 0 Control Register */
+    #define     REG_GDMA_SRCB0  (GDMA_BA+0x004)  /*!< Channel 0 Source Base Address Register */
+    #define     REG_GDMA_DSTB0  (GDMA_BA+0x008)  /*!< Channel 0 Destination Base Address Register */
+    #define     REG_GDMA_TCNT0  (GDMA_BA+0x00C)  /*!< Channel 0 Transfer Count Register */
+    #define     REG_GDMA_CSRC0  (GDMA_BA+0x010)  /*!< Channel 0 Current Source Address Register */
+    #define     REG_GDMA_CDST0  (GDMA_BA+0x014)  /*!< Channel 0 Current Destination Address Register */
+    #define     REG_GDMA_CTCNT0 (GDMA_BA+0x018)  /*!< Channel 0 Current Transfer Count Register */
+    #define     REG_GDMA_DADR0  (GDMA_BA+0x01C)  /*!< Channel 0 Descriptor Address Register */
+    #define     REG_GDMA_CTL1   (GDMA_BA+0x020)  /*!< Channel 1 Control Register */
+    #define     REG_GDMA_SRCB1  (GDMA_BA+0x024)  /*!< Channel 1 Source Base Address Register */
+    #define     REG_GDMA_DSTB1  (GDMA_BA+0x028)  /*!< Channel 1 Destination Base Address Register */
+    #define     REG_GDMA_TCNT1  (GDMA_BA+0x02C)  /*!< Channel 1 Transfer Count Register */
+    #define     REG_GDMA_CSRC1  (GDMA_BA+0x030)  /*!< Channel 1 Current Source Address Register */
+    #define     REG_GDMA_CDST1  (GDMA_BA+0x034)  /*!< Channel 1 Current Destination Address Register */
+    #define     REG_GDMA_CTCNT1 (GDMA_BA+0x038)  /*!< Channel 1 Current Transfer Count Register */
+    #define     REG_GDMA_DADR1  (GDMA_BA+0x03C)  /*!< Channel 1 Descriptor Address Register */
+    #define     REG_GDMA_INTBUF0    (GDMA_BA+0x080)  /*!< GDMA Internal Buffer Word 0 */
+    #define     REG_GDMA_INTBUF1    (GDMA_BA+0x084)  /*!< GDMA Internal Buffer Word 1 */
+    #define     REG_GDMA_INTBUF2    (GDMA_BA+0x088)  /*!< GDMA Internal Buffer Word 2 */
+    #define     REG_GDMA_INTBUF3    (GDMA_BA+0x08C)  /*!< GDMA Internal Buffer Word 3 */
+    #define     REG_GDMA_INTBUF4    (GDMA_BA+0x090)  /*!< GDMA Internal Buffer Word 4 */
+    #define     REG_GDMA_INTBUF5    (GDMA_BA+0x094)  /*!< GDMA Internal Buffer Word 5 */
+    #define     REG_GDMA_INTBUF6    (GDMA_BA+0x098)  /*!< GDMA Internal Buffer Word 6 */
+    #define     REG_GDMA_INTBUF7    (GDMA_BA+0x09C)  /*!< GDMA Internal Buffer Word 7 */
+    #define     REG_GDMA_INTCS  (GDMA_BA+0x0A0)  /*!< Interrupt Control and Status Register */
+
+    /**@}*/ /* end of GDMA register group */
+
+
+
+    /*---------------------- USB Device Controller -------------------------*/
+    /**
+    @addtogroup USBD USB Device Controller(USBD)
+    Memory Mapped Structure for USBD Controller
+    @{ */
+    #define     REG_USBD_GINTSTS        (USBD_BA+0x00)  /*!< Interrupt Status Low Register */
+    #define     REG_USBD_GINTEN         (USBD_BA+0x08)  /*!< Interrupt Enable Low Register */
+    #define     REG_USBD_BUSINTSTS      (USBD_BA+0x10)  /*!< USB Bus Interrupt Status Register */
+    #define     REG_USBD_BUSINTEN       (USBD_BA+0x14)  /*!< USB Bus Interrupt Enable Register */
+    #define     REG_USBD_OPER           (USBD_BA+0x18)  /*!< USB Operational Register */
+    #define     REG_USBD_FRAMECNT       (USBD_BA+0x1C)  /*!< USB Frame Count Register */
+    #define     REG_USBD_FADDR          (USBD_BA+0x20)  /*!< USB Function Address Register */
+    #define     REG_USBD_TEST           (USBD_BA+0x24)  /*!< USB Test Mode Register */
+    #define     REG_USBD_CEPDAT         (USBD_BA+0x28)  /*!< Control-ep data buffer register */
+    #define     REG_USBD_CEPCTL         (USBD_BA+0x2C)  /*!< Control-ep control and status register */
+    #define     REG_USBD_CEPINTEN       (USBD_BA+0x30)  /*!< Control-ep interrupt enable register */
+    #define     REG_USBD_CEPINTSTS      (USBD_BA+0x34)  /*!< Control-ep interrupt status register */
+    #define     REG_USBD_CEPTXCNT       (USBD_BA+0x38)  /*!< In-transfer data count register */
+    #define     REG_USBD_CEPRXCNT       (USBD_BA+0x3C)  /*!< Out-transfer data count register */
+    #define     REG_USBD_CEPDATCNT      (USBD_BA+0x40)  /*!< Control-ep data count register */
+    #define     REG_USBD_SETUP1_0       (USBD_BA+0x44)  /*!< Setup byte1 & byte0 register */
+    #define     REG_USBD_SETUP3_2       (USBD_BA+0x48)  /*!< Setup byte3 & byte2 register */
+    #define     REG_USBD_SETUP5_4       (USBD_BA+0x4C)  /*!< Setup byte5 & byte4 register */
+    #define     REG_USBD_SETUP7_6       (USBD_BA+0x50)  /*!< Setup byte7 & byte6 register */
+    #define     REG_USBD_CEPBUFSTART    (USBD_BA+0x54)  /*!< Control-ep ram start address register */
+    #define     REG_USBD_CEPBUFEND      (USBD_BA+0x58)  /*!< Control-ep ram end address register */
+    #define     REG_USBD_DMACTL         (USBD_BA+0x5C)  /*!< Dma control and status register */
+    #define     REG_USBD_DMACNT         (USBD_BA+0x60)  /*!< Dma count register */
+
+    #define     REG_USBD_EPADAT         (USBD_BA+0x64)  /*!< Endpoint A data buffer register */
+    #define     REG_USBD_EPAINTSTS      (USBD_BA+0x68)  /*!< Endpoint A interrupt status register */
+    #define     REG_USBD_EPAINTEN       (USBD_BA+0x6C)  /*!< Endpoint A interrupt enable register */
+    #define     REG_USBD_EPADATCNT      (USBD_BA+0x70)  /*!< Data count available in endpoint A buffer */
+    #define     REG_USBD_EPARSPCTL      (USBD_BA+0x74)  /*!< Endpoint A response register set/clear */
+    #define     REG_USBD_EPAMPS         (USBD_BA+0x78)  /*!< Endpoint A max packet size register */
+    #define     REG_USBD_EPATXCNT       (USBD_BA+0x7C)  /*!< Endpoint A transfer count register */
+    #define     REG_USBD_EPACFG         (USBD_BA+0x80)  /*!< Endpoint A configuration register */
+    #define     REG_USBD_EPABUFSTART    (USBD_BA+0x84)  /*!< Endpoint A ram start address register */
+    #define     REG_USBD_EPABUFEND      (USBD_BA+0x88)  /*!< Endpoint A ram end address register */
+
+    #define     REG_USBD_EPBDAT         (USBD_BA+0x8C)  /*!< Endpoint B data buffer register */
+    #define     REG_USBD_EPBINTSTS      (USBD_BA+0x90)  /*!< Endpoint B interrupt status register */
+    #define     REG_USBD_EPBINTEN       (USBD_BA+0x94)  /*!< Endpoint B interrupt enable register */
+    #define     REG_USBD_EPBDATCNT      (USBD_BA+0x98)  /*!< Data count available in endpoint B buffer */
+    #define     REG_USBD_EPBRSPCTL      (USBD_BA+0x9C)  /*!< Endpoint B response register set/clear */
+    #define     REG_USBD_EPBMPS         (USBD_BA+0xA0)  /*!< Endpoint B max packet size register */
+    #define     REG_USBD_EPBTXCNT       (USBD_BA+0xA4)  /*!< Endpoint B transfer count register */
+    #define     REG_USBD_EPBCFG         (USBD_BA+0xA8)  /*!< Endpoint B configuration register */
+    #define     REG_USBD_EPBBUFSTART    (USBD_BA+0xAC)  /*!< Endpoint B ram start address register */
+    #define     REG_USBD_EPBBUFEND      (USBD_BA+0xB0)  /*!< Endpoint B ram end address register */
+
+    #define     REG_USBD_EPCDAT         (USBD_BA+0xB4)  /*!< Endpoint C data buffer register */
+    #define     REG_USBD_EPCINTSTS      (USBD_BA+0xB8)  /*!< Endpoint C interrupt status register */
+    #define     REG_USBD_EPCINTEN       (USBD_BA+0xBC)  /*!< Endpoint C interrupt enable register */
+    #define     REG_USBD_EPCDATCNT      (USBD_BA+0xC0)  /*!< Data count available in endpoint C buffer */
+    #define     REG_USBD_EPCRSPCTL      (USBD_BA+0xC4)  /*!< Endpoint C response register set/clear */
+    #define     REG_USBD_EPCMPS         (USBD_BA+0xC8)  /*!< Endpoint C max packet size register */
+    #define     REG_USBD_EPCTXCNT       (USBD_BA+0xCC)  /*!< Endpoint C transfer count register */
+    #define     REG_USBD_EPCCFG         (USBD_BA+0xD0)  /*!< Endpoint C configuration register */
+    #define     REG_USBD_EPCBUFSTART    (USBD_BA+0xD4)  /*!< Endpoint C ram start address register */
+    #define     REG_USBD_EPCBUFEND      (USBD_BA+0xD8)  /*!< Endpoint C ram end address register */
+
+    #define     REG_USBD_EPDDAT         (USBD_BA+0xDC)  /*!< Endpoint D data buffer register */
+    #define     REG_USBD_EPDINTSTS      (USBD_BA+0xE0)  /*!< Endpoint D interrupt status register */
+    #define     REG_USBD_EPDINTEN       (USBD_BA+0xE4)  /*!< Endpoint D interrupt enable register */
+    #define     REG_USBD_EPDDATCNT      (USBD_BA+0xE8)  /*!< Data count available in endpoint D buffer */
+    #define     REG_USBD_EPDRSPCTL      (USBD_BA+0xEC)  /*!< Endpoint D response register set/clear */
+    #define     REG_USBD_EPDMPS         (USBD_BA+0xF0)  /*!< Endpoint D max packet size register */
+    #define     REG_USBD_EPDTXCNT       (USBD_BA+0xF4)  /*!< Endpoint D transfer count register */
+    #define     REG_USBD_EPDCFG         (USBD_BA+0xF8)  /*!< Endpoint D configuration register */
+    #define     REG_USBD_EPDBUFSTART    (USBD_BA+0xFC)  /*!< Endpoint D ram start address register */
+    #define     REG_USBD_EPDBUFEND      (USBD_BA+0x100) /*!< Endpoint D ram end address register */
+
+    #define     REG_USBD_EPEDAT         (USBD_BA+0x104) /*!< Endpoint E data buffer register */
+    #define     REG_USBD_EPEINTSTS      (USBD_BA+0x108) /*!< Endpoint E interrupt status register */
+    #define     REG_USBD_EPEINTEN       (USBD_BA+0x10C) /*!< Endpoint E interrupt enable register */
+    #define     REG_USBD_EPEDATCNT      (USBD_BA+0x110) /*!< Data count available in endpoint E buffer */
+    #define     REG_USBD_EPERSPCTL      (USBD_BA+0x114) /*!< Endpoint E response register set/clear */
+    #define     REG_USBD_EPEMPS         (USBD_BA+0x118) /*!< Endpoint E max packet size register */
+    #define     REG_USBD_EPETXCNT       (USBD_BA+0x11C) /*!< Endpoint E transfer count register */
+    #define     REG_USBD_EPECFG         (USBD_BA+0x120) /*!< Endpoint E configuration register */
+    #define     REG_USBD_EPEBUFSTART    (USBD_BA+0x124) /*!< Endpoint E ram start address register */
+    #define     REG_USBD_EPEBUFEND      (USBD_BA+0x128) /*!< Endpoint E ram end address register */
+
+    #define     REG_USBD_EPFDAT         (USBD_BA+0x12C) /*!< Endpoint F data buffer register */
+    #define     REG_USBD_EPFINTSTS      (USBD_BA+0x130) /*!< Endpoint F interrupt status register */
+    #define     REG_USBD_EPFINTEN       (USBD_BA+0x134) /*!< Endpoint F interrupt enable register */
+    #define     REG_USBD_EPFDATCNT      (USBD_BA+0x138) /*!< Data count available in endpoint F buffer */
+    #define     REG_USBD_EPFRSPCTL      (USBD_BA+0x13C) /*!< Endpoint F response register set/clear */
+    #define     REG_USBD_EPFMPS         (USBD_BA+0x140) /*!< Endpoint F max packet size register */
+    #define     REG_USBD_EPFTXCNT       (USBD_BA+0x144) /*!< Endpoint F transfer count register */
+    #define     REG_USBD_EPFCFG         (USBD_BA+0x148) /*!< Endpoint F configuration register */
+    #define     REG_USBD_EPFBUFSTART    (USBD_BA+0x14C) /*!< Endpoint F ram start address register */
+    #define     REG_USBD_EPFBUFEND      (USBD_BA+0x150) /*!< Endpoint F ram end address register */
+
+    #define     REG_USBD_EPGDAT         (USBD_BA+0x154) /*!< Endpoint G data buffer register */
+    #define     REG_USBD_EPGINTSTS      (USBD_BA+0x158) /*!< Endpoint G interrupt status register */
+    #define     REG_USBD_EPGINTEN       (USBD_BA+0x15C) /*!< Endpoint G interrupt enable register */
+    #define     REG_USBD_EPGDATCNT      (USBD_BA+0x160) /*!< Data count available in endpoint G buffer */
+    #define     REG_USBD_EPGRSPCTL      (USBD_BA+0x164) /*!< Endpoint G response register set/clear */
+    #define     REG_USBD_EPGMPS         (USBD_BA+0x168) /*!< Endpoint G max packet size register */
+    #define     REG_USBD_EPGTXCNT       (USBD_BA+0x16C) /*!< Endpoint G transfer count register */
+    #define     REG_USBD_EPGCFG         (USBD_BA+0x170) /*!< Endpoint G configuration register */
+    #define     REG_USBD_EPGBUFSTART    (USBD_BA+0x174) /*!< Endpoint G ram start address register */
+    #define     REG_USBD_EPGBUFEND      (USBD_BA+0x178) /*!< Endpoint G ram end address register */
+
+    #define     REG_USBD_EPHDAT         (USBD_BA+0x17C) /*!< Endpoint H data buffer register */
+    #define     REG_USBD_EPHINTSTS      (USBD_BA+0x180) /*!< Endpoint H interrupt status register */
+    #define     REG_USBD_EPHINTEN       (USBD_BA+0x184) /*!< Endpoint H interrupt enable register */
+    #define     REG_USBD_EPHDATCNT      (USBD_BA+0x188) /*!< Data count available in endpoint H buffer */
+    #define     REG_USBD_EPHRSPCTL      (USBD_BA+0x18C) /*!< Endpoint H response register set/clear */
+    #define     REG_USBD_EPHMPS         (USBD_BA+0x190) /*!< Endpoint H max packet size register */
+    #define     REG_USBD_EPHTXCNT       (USBD_BA+0x194) /*!< Endpoint H transfer count register */
+    #define     REG_USBD_EPHCFG         (USBD_BA+0x198) /*!< Endpoint H configuration register */
+    #define     REG_USBD_EPHBUFSTART    (USBD_BA+0x19C) /*!< Endpoint H ram start address register */
+    #define     REG_USBD_EPHBUFEND      (USBD_BA+0x1A0) /*!< Endpoint H ram end address register */
+
+    #define     REG_USBD_EPIDAT         (USBD_BA+0x1A4) /*!< Endpoint I data buffer register */
+    #define     REG_USBD_EPIINTSTS      (USBD_BA+0x1A8) /*!< Endpoint I interrupt status register */
+    #define     REG_USBD_EPIINTEN       (USBD_BA+0x1AC) /*!< Endpoint I interrupt enable register */
+    #define     REG_USBD_EPIDATCNT      (USBD_BA+0x1B0) /*!< Data count available in endpoint I buffer */
+    #define     REG_USBD_EPIRSPCTL      (USBD_BA+0x1B4) /*!< Endpoint I response register set/clear */
+    #define     REG_USBD_EPIMPS         (USBD_BA+0x1B8) /*!< Endpoint I max packet size register */
+    #define     REG_USBD_EPITXCNT       (USBD_BA+0x1BC) /*!< Endpoint I transfer count register */
+    #define     REG_USBD_EPICFG         (USBD_BA+0x1C0) /*!< Endpoint I configuration register */
+    #define     REG_USBD_EPIBUFSTART    (USBD_BA+0x1C4) /*!< Endpoint I ram start address register */
+    #define     REG_USBD_EPIBUFEND      (USBD_BA+0x1C8) /*!< Endpoint I ram end address register */
+
+    #define     REG_USBD_EPJDAT         (USBD_BA+0x1CC) /*!< Endpoint J data buffer register */
+    #define     REG_USBD_EPJINTSTS      (USBD_BA+0x1D0) /*!< Endpoint J interrupt status register */
+    #define     REG_USBD_EPJINTEN       (USBD_BA+0x1D4) /*!< Endpoint J interrupt enable register */
+    #define     REG_USBD_EPJDATCNT      (USBD_BA+0x1D8) /*!< Data count available in endpoint J buffer */
+    #define     REG_USBD_EPJRSPCTL      (USBD_BA+0x1DC) /*!< Endpoint J response register set/clear */
+    #define     REG_USBD_EPJMPS         (USBD_BA+0x1E0) /*!< Endpoint J max packet size register */
+    #define     REG_USBD_EPJTXCNT       (USBD_BA+0x1E4) /*!< Endpoint J transfer count register */
+    #define     REG_USBD_EPJCFG         (USBD_BA+0x1E8) /*!< Endpoint J configuration register */
+    #define     REG_USBD_EPJBUFSTART    (USBD_BA+0x1EC) /*!< Endpoint J ram start address register */
+    #define     REG_USBD_EPJBUFEND      (USBD_BA+0x1F0) /*!< Endpoint J ram end address register */
+
+    #define     REG_USBD_EPKDAT         (USBD_BA+0x1F4) /*!< Endpoint K data buffer register */
+    #define     REG_USBD_EPKINTSTS      (USBD_BA+0x1F8) /*!< Endpoint K interrupt status register */
+    #define     REG_USBD_EPKINTEN       (USBD_BA+0x1FC) /*!< Endpoint K interrupt enable register */
+    #define     REG_USBD_EPKDATCNT      (USBD_BA+0x200) /*!< Data count available in endpoint K buffer */
+    #define     REG_USBD_EPKRSPCTL      (USBD_BA+0x204) /*!< Endpoint K response register set/clear */
+    #define     REG_USBD_EPKMPS         (USBD_BA+0x208) /*!< Endpoint K max packet size register */
+    #define     REG_USBD_EPKTXCNT       (USBD_BA+0x20C) /*!< Endpoint K transfer count register */
+    #define     REG_USBD_EPKCFG         (USBD_BA+0x210) /*!< Endpoint K configuration register */
+    #define     REG_USBD_EPKBUFSTART    (USBD_BA+0x214) /*!< Endpoint K ram start address register */
+    #define     REG_USBD_EPKBUFEND      (USBD_BA+0x218) /*!< Endpoint K ram end address register */
+
+    #define     REG_USBD_EPLDAT         (USBD_BA+0x21C) /*!< Endpoint L data buffer register */
+    #define     REG_USBD_EPLINTSTS      (USBD_BA+0x220) /*!< Endpoint L interrupt status register */
+    #define     REG_USBD_EPLINTEN       (USBD_BA+0x224) /*!< Endpoint L interrupt enable register */
+    #define     REG_USBD_EPLDATCNT      (USBD_BA+0x228) /*!< Data count available in endpoint L buffer */
+    #define     REG_USBD_EPLRSPCTL      (USBD_BA+0x22C) /*!< Endpoint L response register set/clear */
+    #define     REG_USBD_EPLMPS         (USBD_BA+0x230) /*!< Endpoint L max packet size register */
+    #define     REG_USBD_EPLTXCNT       (USBD_BA+0x234) /*!< Endpoint L transfer count register */
+    #define     REG_USBD_EPLCFG         (USBD_BA+0x238) /*!< Endpoint L configuration register */
+    #define     REG_USBD_EPLBUFSTART    (USBD_BA+0x23C) /*!< Endpoint L ram start address register */
+    #define     REG_USBD_EPLBUFEND      (USBD_BA+0x240) /*!< Endpoint L ram end address register */
+    #define     REG_USBD_DMAADDR        (USBD_BA+0x700) /*!< AHB_DMA address register */
+    #define     REG_USBD_PHYCTL         (USBD_BA+0x704) /*!< USB PHY control register */
+
+    /**@}*/ /* end of USBD register group */
+
+
+    /*----------------------  LCD Display Interface Controller -------------------------*/
+    /**
+    @addtogroup LCM  LCD Display Interface Controller(LCM)
+    Memory Mapped Structure for LCM Controller
+    @{ */
+
+    #define     REG_LCM_DCCS        (LCM_BA+0x00)  /*!< Display Controller Control/Status Register */
+    #define     REG_LCM_DEV_CTRL    (LCM_BA+0x04)  /*!< Display Output Device Control Register */
+    #define     REG_LCM_MPU_CMD     (LCM_BA+0x08)  /*!< MPU-Interface LCD Write Command */
+    #define     REG_LCM_INT_CS      (LCM_BA+0x0c)  /*!< Interrupt Control/Status Register */
+    #define     REG_LCM_CRTC_SIZE   (LCM_BA+0x10)  /*!< CRTC Display Size Control Register */
+    #define     REG_LCM_CRTC_DEND   (LCM_BA+0x14)  /*!< CRTC Display Enable End */
+    #define     REG_LCM_CRTC_HR     (LCM_BA+0x18)  /*!< CRTC Internal Horizontal Retrace Control Register */
+    #define     REG_LCM_CRTC_HSYNC  (LCM_BA+0x1C)  /*!< CRTC Horizontal Sync Control Register */
+    #define     REG_LCM_CRTC_VR     (LCM_BA+0x20)  /*!< CRTC Internal Vertical Retrace Control Register */
+    #define     REG_LCM_VA_BADDR0   (LCM_BA+0x24)  /*!< Video Stream Frame Buffer-0 Starting Address */
+    #define     REG_LCM_VA_BADDR1   (LCM_BA+0x28)  /*!< Video Stream Frame Buffer-1 Starting Address */
+    #define     REG_LCM_VA_FBCTRL   (LCM_BA+0x2C)  /*!< Video Stream Frame Buffer Control Register */
+    #define     REG_LCM_VA_SCALE    (LCM_BA+0x30)  /*!< Video Stream Scaling Control Register */
+    #define     REG_LCM_VA_WIN      (LCM_BA+0x38)  /*!< Image Stream Active Window Coordinates */
+    #define     REG_LCM_VA_STUFF    (LCM_BA+0x3C)  /*!< Image Stream Stuff Pixel */
+    #define     REG_LCM_OSD_WINS    (LCM_BA+0x40)  /*!< OSD Window Starting Coordinates */
+    #define     REG_LCM_OSD_WINE    (LCM_BA+0x44)  /*!< OSD Window Ending Coordinates */
+    #define     REG_LCM_OSD_BADDR   (LCM_BA+0x48)  /*!< OSD Stream Frame Buffer Starting Address */
+    #define     REG_LCM_OSD_FBCTRL  (LCM_BA+0x4c)  /*!< OSD Stream Frame Buffer Control Register */
+    #define     REG_LCM_OSD_OVERLAY (LCM_BA+0x50)  /*!< OSD Overlay Control Register */
+    #define     REG_LCM_OSD_CKEY    (LCM_BA+0x54)  /*!< OSD Overlay Color-Key Pattern Register */
+    #define     REG_LCM_OSD_CMASK   (LCM_BA+0x58)  /*!< OSD Overlay Color-Key Mask Register */
+    #define     REG_LCM_OSD_SKIP1   (LCM_BA+0x5C)  /*!< OSD Window Skip1 Register */
+    #define     REG_LCM_OSD_SKIP2   (LCM_BA+0x60)  /*!< OSD Window Skip2 Register */
+    #define     REG_LCM_OSD_SCALE   (LCM_BA+0x64)  /*!< OSD horizontal up scaling control register */
+    #define     REG_LCM_MPU_VSYNC   (LCM_BA+0x68)  /*!< MPU Vsync control register */
+    #define     REG_LCM_HC_CTRL     (LCM_BA+0x6C)  /*!< Hardware cursor control Register */
+    #define     REG_LCM_HC_POS      (LCM_BA+0x70)  /*!< Hardware cursot tip point potison on va picture */
+    #define     REG_LCM_HC_WBCTRL   (LCM_BA+0x74)  /*!< Hardware Cursor Window Buffer Control Register */
+    #define     REG_LCM_HC_BADDR    (LCM_BA+0x78)  /*!< Hardware cursor memory base address register */
+    #define     REG_LCM_HC_COLOR0   (LCM_BA+0x7C)  /*!< Hardware cursor color ram register mapped to bpp = 0 */
+    #define     REG_LCM_HC_COLOR1   (LCM_BA+0x80)  /*!< Hardware cursor color ram register mapped to bpp = 1 */
+    #define     REG_LCM_HC_COLOR2   (LCM_BA+0x84)  /*!< Hardware cursor color ram register mapped to bpp = 2 */
+    #define     REG_LCM_HC_COLOR3   (LCM_BA+0x88)  /*!< Hardware cursor color ram register mapped to bpp = 3 */
+
+    /**@}*/ /* end of LCM register group */
+
+
+    /*---------------------- I2S Interface Controller -------------------------*/
+    /**
+    @addtogroup I2S I2S Interface Controller(I2S)
+    Memory Mapped Structure for I2S Controller
+    @{ */
+
+    #define     REG_ACTL_CON            (ACTL_BA+0x00)      /*!< Audio controller control register */
+    #define     REG_ACTL_RESET          (ACTL_BA+0x04)      /*!< Sub block reset control register */
+    #define     REG_ACTL_RDESB          (ACTL_BA+0x08)      /*!< DMA destination base address register for record */
+    #define     REG_ACTL_RDES_LENGTH    (ACTL_BA+0x0C)      /*!< DMA destination length register for record */
+    #define     REG_ACTL_RDESC          (ACTL_BA+0x10)      /*!< DMA destination current address for record */
+    #define     REG_ACTL_PDESB          (ACTL_BA+0x14)      /*!< DMA destination current address for play */
+    #define     REG_ACTL_PDES_LENGTH    (ACTL_BA+0x18)      /*!< DMA destination length register for play */
+    #define     REG_ACTL_PDESC          (ACTL_BA+0x1C)      /*!< DMA destination current address register for play */
+    #define     REG_ACTL_RSR            (ACTL_BA+0x20)      /*!< Record status register */
+    #define     REG_ACTL_PSR            (ACTL_BA+0x24)      /*!< Play status register */
+    #define     REG_ACTL_I2SCON         (ACTL_BA+0x28)      /*!< I2S control register */
+    #define     REG_ACTL_COUNTER        (ACTL_BA+0x2C)      /*!< DMA count down values */
+    #define     REG_ACTL_PCMCON         (ACTL_BA+0x30)      /*!< PCM interface control register */
+    #define     REG_ACTL_PCMS1ST        (ACTL_BA+0x34)      /*!< PCM interface slot1 start register */
+    #define     REG_ACTL_PCMS2ST        (ACTL_BA+0x38)      /*!< PCM interface slot2 start register */
+    #define     REG_ACTL_RDESB2         (ACTL_BA+0x40)      /*!< DMA destination base address register for record right channel */
+    #define     REG_ACTL_PDESB2         (ACTL_BA+0x44)      /*!< DMA destination base address register for play right channel */
+
+    /**@}*/ /* end of I2S register group */
+
+    /*---------------------- 2D Graphic Engine -------------------------*/
+    /**
+    @addtogroup GE2D 2D Graphic Engine(GE2D)
+    Memory Mapped Structure for GE2D Controller
+    @{ */
+
+    #define     REG_GE2D_TRG            (GE_BA+0x00)  /*!< Graphic Engine Trigger Control Register */
+    #define     REG_GE2D_XYSORG         (GE_BA+0x04)  /*!< Graphic Engine XY Mode Source Origin Starting Register */
+    #define     REG_GE2D_TCNTVHSF       (GE_BA+0x08)  /*!< Graphic Engine Tile Width/Height or V/H Scale Factor N/M */
+    #define     REG_GE2D_XYRRP          (GE_BA+0x0C)  /*!< Graphic Engine Rotate Reference Point XY Address */
+    #define     REG_GE2D_INTSTS         (GE_BA+0x10)  /*!< Graphic Engine Interrupt Status Register */
+    #define     REG_GE2D_PATSA          (GE_BA+0x14)  /*!< Graphic Engine Pattern Location Starting Address Register */
+    #define     REG_GE2D_BETSC          (GE_BA+0x18)  /*!< GE Bresenham Error Term Stepping Constant Register */
+    #define     REG_GE2D_BIEPC          (GE_BA+0x1C)  /*!< GE Bresenham Initial Error, Pixel Count Major M Register */
+    #define     REG_GE2D_CTL            (GE_BA+0x20)  /*!< Graphic Engine Control Register */
+    #define     REG_GE2D_BGCOLR         (GE_BA+0x24)  /*!< Graphic Engine Background Color Register */
+    #define     REG_GE2D_FGCOLR         (GE_BA+0x28)  /*!< Graphic Engine Foreground Color Register */
+    #define     REG_GE2D_TRNSCOLR       (GE_BA+0x2C)  /*!< Graphic Engine Transparency Color Register */
+    #define     REG_GE2D_TCMSK          (GE_BA+0x30)  /*!< Graphic Engine Transparency Color Mask Register */
+    #define     REG_GE2D_XYDORG         (GE_BA+0x34)  /*!< Graphic Engine XY Mode Display Origin Starting Register */
+    #define     REG_GE2D_SDPITCH        (GE_BA+0x38)  /*!< Graphic Engine Source/Destination Pitch Register */
+    #define     REG_GE2D_SRCSPA         (GE_BA+0x3C)  /*!< Graphic Engine Source Start XY/Linear Address Register */
+    #define     REG_GE2D_DSTSPA         (GE_BA+0x40)  /*!< Graphic Engine Destination Start XY/Linear Register */
+    #define     REG_GE2D_RTGLSZ         (GE_BA+0x44)  /*!< Graphic Engine Dimension XY/Linear Register */
+    #define     REG_GE2D_CLPBTL         (GE_BA+0x48)  /*!< Graphic Engine Clipping Boundary Top/Left Register */
+    #define     REG_GE2D_CLPBBR         (GE_BA+0x4C)  /*!< Graphic Engine Clipping Boundary Bottom/Right Register */
+    #define     REG_GE2D_PTNA           (GE_BA+0x50)  /*!< Graphic Engine Pattern A Register */
+    #define     REG_GE2D_PTNB           (GE_BA+0x54)  /*!< Graphic Engine Pattern B Register */
+    #define     REG_GE2D_WRPLNMSK       (GE_BA+0x58)  /*!< Graphic Engine Write Plane Mask Register */
+    #define     REG_GE2D_MISCTL         (GE_BA+0x5C)  /*!< Graphic Engine Miscellaneous Control Register */
+    #define     REG_GE2D_GEHBDW0        (GE_BA+0x60)  /*!< Graphic Engine HostBLT data Port 0 Register */
+    #define     REG_GE2D_GEHBDW1        (GE_BA+0x64)  /*!< Graphic Engine HostBLT data Port 1 Register */
+    #define     REG_GE2D_GEHBDW2        (GE_BA+0x68)  /*!< Graphic Engine HostBLT data Port 2 Register */
+    #define     REG_GE2D_GEHBDW3        (GE_BA+0x6C)  /*!< Graphic Engine HostBLT data Port 3 Register */
+    #define     REG_GE2D_GEHBDW4        (GE_BA+0x70)  /*!< Graphic Engine HostBLT data Port 4 Register */
+    #define     REG_GE2D_GEHBDW5        (GE_BA+0x74)  /*!< Graphic Engine HostBLT data Port 5 Register */
+    #define     REG_GE2D_GEHBDW6        (GE_BA+0x78)  /*!< Graphic Engine HostBLT data Port 6 Register */
+    #define     REG_GE2D_GEHBDW7        (GE_BA+0x7C)  /*!< Graphic Engine HostBLT data Port 7 Register */
+
+    /**@}*/ /* end of GE2D register group */
+
+    /*---------------------- Flash Memory Interface -------------------------*/
+    /**
+    @addtogroup FMI Flash Memory Interface(FMI)
+    Memory Mapped Structure for FMI Controller
+    @{ */
+
+    /* DMAC Control Registers*/
+    #define     REG_FMI_BUFFER      (FMI_BA+0x000)   /*!< FMI Embedded Buffer Word */
+    #define     REG_FMI_DMACTL      (FMI_BA+0x400)   /*!< FMI DMA Control Register */
+    #define     REG_FMI_DMASA       (FMI_BA+0x408)   /*!< FMI DMA Transfer Starting Address Register */
+    #define     REG_FMI_DMABCNT     (FMI_BA+0x40C)   /*!< FMI DMA Transfer Byte Count Register */
+    #define     REG_FMI_DMAINTEN    (FMI_BA+0x410)   /*!< FMI DMA Interrupt Enable Register */
+    #define     REG_FMI_DMAINTSTS   (FMI_BA+0x414)   /*!< FMI DMA Interrupt Status Register */
+
+    #define     REG_FMI_CTL         (FMI_BA+0x800)   /*!< Global Control and Status Register */
+    #define     REG_FMI_INTEN       (FMI_BA+0x804)   /*!< Global Interrupt Control Register */
+    #define     REG_FMI_INTSTS      (FMI_BA+0x808)   /*!< Global Interrupt Status Register */
+
+    /* eMMC Registers */
+    #define     REG_FMI_EMMCCTL     (FMI_BA+0x820)   /*!< eMMC control and status register */
+    #define     REG_FMI_EMMCCMD     (FMI_BA+0x824)   /*!< eMMC command argument register */
+    #define     REG_FMI_EMMCINTEN   (FMI_BA+0x828)   /*!< eMMC interrupt enable register */
+    #define     REG_FMI_EMMCINTSTS  (FMI_BA+0x82C)   /*!< eMMC interrupt status register */
+    #define     REG_FMI_EMMCRESP0   (FMI_BA+0x830)   /*!< eMMC receive response token register 0 */
+    #define     REG_FMI_EMMCRESP1   (FMI_BA+0x834)   /*!< eMMC receive response token register 1 */
+    #define     REG_FMI_EMMCBLEN    (FMI_BA+0x838)   /*!< eMMC block length register */
+    #define     REG_FMI_EMMCTOUT    (FMI_BA+0x83C)   /*!< eMMC block length register */
+
+    /* NAND-type Flash Registers */
+    #define     REG_NANDCTL         (FMI_BA+0x8A0)   /*!< NAND Flash Control and Status Register */
+    #define     REG_NANDTMCTL       (FMI_BA+0x8A4)   /*!< NAND Flash Timing Control Register */
+    #define     REG_NANDINTEN       (FMI_BA+0x8A8)   /*!< NAND Flash Interrupt Control Register */
+    #define     REG_NANDINTSTS      (FMI_BA+0x8AC)   /*!< NAND Flash Interrupt Status Register */
+    #define     REG_NANDCMD         (FMI_BA+0x8B0)   /*!< NAND Flash Command Port Register */
+    #define     REG_NANDADDR        (FMI_BA+0x8B4)   /*!< NAND Flash Address Port Register */
+    #define     REG_NANDDATA        (FMI_BA+0x8B8)   /*!< NAND Flash Data Port Register */
+    #define     REG_NANDRACTL       (FMI_BA+0x8BC)   /*!< NAND Flash Redundant Area Control Register */
+    #define     REG_NANDECTL        (FMI_BA+0x8C0)   /*!< NAND Flash Extend Control Regsiter */
+    #define     REG_NANDECCES0      (FMI_BA+0x8D0)   /*!< NAND Flash ECC Error Status 0 */
+    #define     REG_NANDECCES1      (FMI_BA+0x8D4)   /*!< NAND Flash ECC Error Status 1 */
+    #define     REG_NANDECCES2      (FMI_BA+0x8D8)   /*!< NAND Flash ECC Error Status 2 */
+    #define     REG_NANDECCES3      (FMI_BA+0x8DC)   /*!< NAND Flash ECC Error Status 3 */
+    #define     REG_NANDPROTA0      (FMI_BA+0x8E0)   /*!< NAND Flash Protect Region End Address 0 */
+    #define     REG_NANDPROTA1      (FMI_BA+0x8E4)   /*!< NAND Flash Protect Region End Address 1 */
+
+    /* NAND-type Flash BCH Error Address Registers */
+    #define     REG_NANDECCEA0      (FMI_BA+0x900)   /*!< NAND Flash ECC Error Byte Address 0 */
+    #define     REG_NANDECCEA1      (FMI_BA+0x904)   /*!< NAND Flash ECC Error Byte Address 1 */
+    #define     REG_NANDECCEA2      (FMI_BA+0x908)   /*!< NAND Flash ECC Error Byte Address 2 */
+    #define     REG_NANDECCEA3      (FMI_BA+0x90C)   /*!< NAND Flash ECC Error Byte Address 3 */
+    #define     REG_NANDECCEA4      (FMI_BA+0x910)   /*!< NAND Flash ECC Error Byte Address 4 */
+    #define     REG_NANDECCEA5      (FMI_BA+0x914)   /*!< NAND Flash ECC Error Byte Address 5 */
+    #define     REG_NANDECCEA6      (FMI_BA+0x918)   /*!< NAND Flash ECC Error Byte Address 6 */
+    #define     REG_NANDECCEA7      (FMI_BA+0x91C)   /*!< NAND Flash ECC Error Byte Address 7 */
+    #define     REG_NANDECCEA8      (FMI_BA+0x920)   /*!< NAND Flash ECC Error Byte Address 8 */
+    #define     REG_NANDECCEA9      (FMI_BA+0x924)   /*!< NAND Flash ECC Error Byte Address 9 */
+    #define     REG_NANDECCEA10     (FMI_BA+0x928)   /*!< NAND Flash ECC Error Byte Address 10 */
+    #define     REG_NANDECCEA11     (FMI_BA+0x92C)   /*!< NAND Flash ECC Error Byte Address 11 */
+
+    /* NAND-type Flash BCH Error Data Registers */
+    #define     REG_NANDECCED0      (FMI_BA+0x960)   /*!< NAND Flash ECC Error Data Register 0 */
+    #define     REG_NANDECCED1      (FMI_BA+0x964)   /*!< NAND Flash ECC Error Data Register 1 */
+    #define     REG_NANDECCED2      (FMI_BA+0x968)   /*!< NAND Flash ECC Error Data Register 2 */
+    #define     REG_NANDECCED3      (FMI_BA+0x96C)   /*!< NAND Flash ECC Error Data Register 3 */
+    #define     REG_NANDECCED4      (FMI_BA+0x970)   /*!< NAND Flash ECC Error Data Register 4 */
+    #define     REG_NANDECCED5      (FMI_BA+0x974)   /*!< NAND Flash ECC Error Data Register 5 */
+
+    /* NAND-type Flash Redundant Area Registers */
+    #define     REG_NANDRA0         (FMI_BA+0xA00)   /*!< NAND Flash Redundant Area Register */
+    #define     REG_NANDRA1         (FMI_BA+0xA04)   /*!< NAND Flash Redundant Area Register */
+
+    /**@}*/ /* end of FMI register group */
+
+
+    /*---------------------- SD/SDIO Host Controller -------------------------*/
+    /**
+    @addtogroup SDH SD/SDIO Host Controller(SDH)
+    Memory Mapped Structure for SDH Controller
+    @{ */
+
+    /* DMAC Control Registers*/
+    #define     REG_SDH_FB0         (SDH_BA+0x000)   /*!< SD Host Embedded Buffer Word */
+    #define     REG_SDH_DMACTL      (SDH_BA+0x400)   /*!< SD Host DMA Control and Status Register */
+    #define     REG_SDH_DMASA       (SDH_BA+0x408)   /*!< SD Host DMA Transfer Starting Address Register */
+    #define     REG_SDH_DMABCNT     (SDH_BA+0x40C)   /*!< SD Host DMA Transfer Byte Count Register */
+    #define     REG_SDH_DMAINTEN    (SDH_BA+0x410)   /*!< SD Host DMA Interrupt Enable Register */
+    #define     REG_SDH_DMAINTSTS   (SDH_BA+0x414)   /*!< SD Host DMA Interrupt Status Register */
+
+    #define     REG_SDH_GCTL        (SDH_BA+0x800)   /*!< SD Host Global Control and Status Register */
+    #define     REG_SDH_GINTEN      (SDH_BA+0x804)   /*!< SD Host Global Interrupt Control Register */
+    #define     REG_SDH_GINTSTS     (SDH_BA+0x808)   /*!< SD Host Global Interrupt Status Register */
+
+    /* Secure Digit Registers */
+    #define     REG_SDH_CTL         (SDH_BA+0x820)   /*!< SD Host control and status register */
+    #define     REG_SDH_CMD         (SDH_BA+0x824)   /*!< SD Host command argument register */
+    #define     REG_SDH_INTEN       (SDH_BA+0x828)   /*!< SD Host interrupt enable register */
+    #define     REG_SDH_INTSTS      (SDH_BA+0x82C)   /*!< SD Host interrupt status register */
+    #define     REG_SDH_RESP0       (SDH_BA+0x830)   /*!< SD Host receive response token register 0 */
+    #define     REG_SDH_RESP1       (SDH_BA+0x834)   /*!< SD Host receive response token register 1 */
+    #define     REG_SDH_BLEN        (SDH_BA+0x838)   /*!< SD Host block length register */
+    #define     REG_SDH_TMOUT       (SDH_BA+0x83C)   /*!< SD Host Response/Data-in Time-out register */
+    #define     REG_SDH_ECTL        (SDH_BA+0x840)   /*!< SD Host Extend Control Register */
+
+    /**@}*/ /* end of SDH register group */
+
+
+    /*---------------------- Cryptographic Accelerator -------------------------*/
+    /**
+    @addtogroup CRYPTO Cryptographic Accelerator(CRYPTO)
+    Memory Mapped Structure for Cryptographic Accelerator registers
+    @{ */
+
+    /* Crypto Control Registers */
+    #define     CRPT_INTEN          (CRPT_BA+0x000)  /*!< Crypto Interrupt Enable Control Register      */
+    #define     CRPT_INTSTS         (CRPT_BA+0x004)  /*!< Crypto Interrupt Flag                         */
+
+    /* PRNG Registers */
+    #define     CRPT_PRNG_CTL       (CRPT_BA+0x008)  /*!< PRNG Control Register                         */
+    #define     CRPT_PRNG_SEED      (CRPT_BA+0x00C)  /*!< Seed for PRNG                                 */
+    #define     CRPT_PRNG_KEY0      (CRPT_BA+0x010)  /*!< PRNG Generated Key 0                          */
+    #define     CRPT_PRNG_KEY1      (CRPT_BA+0x014)  /*!< PRNG Generated Key 1                          */
+    #define     CRPT_PRNG_KEY2      (CRPT_BA+0x018)  /*!< PRNG Generated Key 2                          */
+    #define     CRPT_PRNG_KEY3      (CRPT_BA+0x01C)  /*!< PRNG Generated Key 3                          */
+    #define     CRPT_PRNG_KEY4      (CRPT_BA+0x020)  /*!< PRNG Generated Key 4                          */
+    #define     CRPT_PRNG_KEY5      (CRPT_BA+0x024)  /*!< PRNG Generated Key 5                          */
+    #define     CRPT_PRNG_KEY6      (CRPT_BA+0x028)  /*!< PRNG Generated Key 6                          */
+    #define     CRPT_PRNG_KEY7      (CRPT_BA+0x02C)  /*!< PRNG Generated Key 7                          */
+
+    /* AES/TDES feedback Registers */
+    #define     CRPT_AES_FDBCK0     (CRPT_BA+0x050)  /*!< AES Engine Output Feedback Data after Cryptographic Operation   */
+    #define     CRPT_AES_FDBCK1     (CRPT_BA+0x054)  /*!< AES Engine Output Feedback Data after Cryptographic Operation   */
+    #define     CRPT_AES_FDBCK2     (CRPT_BA+0x058)  /*!< AES Engine Output Feedback Data after Cryptographic Operation   */
+    #define     CRPT_AES_FDBCK3     (CRPT_BA+0x05C)  /*!< AES Engine Output Feedback Data after Cryptographic Operation   */
+    #define     CRPT_TDES_FDBCKH    (CRPT_BA+0x060)  /*!< TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation  */
+    #define     CRPT_TDES_FDBCKL    (CRPT_BA+0x064)  /*!< TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation   */
+
+    /* AES Control Registers */
+    #define     CRPT_AES_CTL        (CRPT_BA+0x100)   /*!< AES Control Register                               */
+    #define     CRPT_AES_STS        (CRPT_BA+0x104)   /*!< AES Engine Flag                                    */
+    #define     CRPT_AES_DATIN      (CRPT_BA+0x108)   /*!< AES Engine Data Input Port Register                */
+    #define     CRPT_AES_DATOUT     (CRPT_BA+0x10C)   /*!< AES Engine Data Output Port Register               */
+    #define     CRPT_AES0_KEY0      (CRPT_BA+0x110)   /*!< AES Key Word 0 Register for Channel 0              */
+    #define     CRPT_AES0_KEY1      (CRPT_BA+0x114)   /*!< AES Key Word 1 Register for Channel 0              */
+    #define     CRPT_AES0_KEY2      (CRPT_BA+0x118)   /*!< AES Key Word 2 Register for Channel 0              */
+    #define     CRPT_AES0_KEY3      (CRPT_BA+0x11C)   /*!< AES Key Word 3 Register for Channel 0              */
+    #define     CRPT_AES0_KEY4      (CRPT_BA+0x120)   /*!< AES Key Word 4 Register for Channel 0              */
+    #define     CRPT_AES0_KEY5      (CRPT_BA+0x124)   /*!< AES Key Word 5 Register for Channel 0              */
+    #define     CRPT_AES0_KEY6      (CRPT_BA+0x128)   /*!< AES Key Word 6 Register for Channel 0              */
+    #define     CRPT_AES0_KEY7      (CRPT_BA+0x12C)   /*!< AES Key Word 7 Register for Channel 0              */
+    #define     CRPT_AES0_IV0       (CRPT_BA+0x130)   /*!< AES Initial Vector Word 0 Register for Channel 0   */
+    #define     CRPT_AES0_IV1       (CRPT_BA+0x134)   /*!< AES Initial Vector Word 1 Register for Channel 0   */
+    #define     CRPT_AES0_IV2       (CRPT_BA+0x138)   /*!< AES Initial Vector Word 2 Register for Channel 0   */
+    #define     CRPT_AES0_IV3       (CRPT_BA+0x13C)   /*!< AES Initial Vector Word 3 Register for Channel 0   */
+    #define     CRPT_AES0_SADDR     (CRPT_BA+0x140)   /*!< AES DMA Source Address Register for Channel 0      */
+    #define     CRPT_AES0_DADDR     (CRPT_BA+0x144)   /*!< AES DMA Destination Address Register for Channel 0 */
+    #define     CRPT_AES0_CNT       (CRPT_BA+0x148)   /*!< AES Byte Count Register for Channel 0              */
+    #define     CRPT_AES1_KEY0      (CRPT_BA+0x14C)   /*!< AES Key Word 0 Register for Channel 1              */
+    #define     CRPT_AES1_KEY1      (CRPT_BA+0x150)   /*!< AES Key Word 1 Register for Channel 1              */
+    #define     CRPT_AES1_KEY2      (CRPT_BA+0x154)   /*!< AES Key Word 2 Register for Channel 1              */
+    #define     CRPT_AES1_KEY3      (CRPT_BA+0x158)   /*!< AES Key Word 3 Register for Channel 1              */
+    #define     CRPT_AES1_KEY4      (CRPT_BA+0x15C)   /*!< AES Key Word 4 Register for Channel 1              */
+    #define     CRPT_AES1_KEY5      (CRPT_BA+0x160)   /*!< AES Key Word 5 Register for Channel 1              */
+    #define     CRPT_AES1_KEY6      (CRPT_BA+0x164)   /*!< AES Key Word 6 Register for Channel 1              */
+    #define     CRPT_AES1_KEY7      (CRPT_BA+0x168)   /*!< AES Key Word 7 Register for Channel 1              */
+    #define     CRPT_AES1_IV0       (CRPT_BA+0x16C)   /*!< AES Initial Vector Word 0 Register for Channel 1   */
+    #define     CRPT_AES1_IV1       (CRPT_BA+0x170)   /*!< AES Initial Vector Word 1 Register for Channel 1   */
+    #define     CRPT_AES1_IV2       (CRPT_BA+0x174)   /*!< AES Initial Vector Word 2 Register for Channel 1   */
+    #define     CRPT_AES1_IV3       (CRPT_BA+0x178)   /*!< AES Initial Vector Word 3 Register for Channel 1   */
+    #define     CRPT_AES1_SADDR     (CRPT_BA+0x17C)   /*!< AES DMA Source Address Register for Channel 1      */
+    #define     CRPT_AES1_DADDR     (CRPT_BA+0x180)   /*!< AES DMA Destination Address Register for Channel 1 */
+    #define     CRPT_AES1_CNT       (CRPT_BA+0x184)   /*!< AES Byte Count Register for Channel 1              */
+    #define     CRPT_AES2_KEY0      (CRPT_BA+0x188)   /*!< AES Key Word 0 Register for Channel 2              */
+    #define     CRPT_AES2_KEY1      (CRPT_BA+0x18C)   /*!< AES Key Word 1 Register for Channel 2              */
+    #define     CRPT_AES2_KEY2      (CRPT_BA+0x190)   /*!< AES Key Word 2 Register for Channel 2              */
+    #define     CRPT_AES2_KEY3      (CRPT_BA+0x194)   /*!< AES Key Word 3 Register for Channel 2              */
+    #define     CRPT_AES2_KEY4      (CRPT_BA+0x198)   /*!< AES Key Word 4 Register for Channel 2              */
+    #define     CRPT_AES2_KEY5      (CRPT_BA+0x19C)   /*!< AES Key Word 5 Register for Channel 2              */
+    #define     CRPT_AES2_KEY6      (CRPT_BA+0x1A0)   /*!< AES Key Word 6 Register for Channel 2              */
+    #define     CRPT_AES2_KEY7      (CRPT_BA+0x1A4)   /*!< AES Key Word 7 Register for Channel 2              */
+    #define     CRPT_AES2_IV0       (CRPT_BA+0x1A8)   /*!< AES Initial Vector Word 0 Register for Channel 2   */
+    #define     CRPT_AES2_IV1       (CRPT_BA+0x1AC)   /*!< AES Initial Vector Word 1 Register for Channel 2   */
+    #define     CRPT_AES2_IV2       (CRPT_BA+0x1B0)   /*!< AES Initial Vector Word 2 Register for Channel 2   */
+    #define     CRPT_AES2_IV3       (CRPT_BA+0x1B4)   /*!< AES Initial Vector Word 3 Register for Channel 2   */
+    #define     CRPT_AES2_SADDR     (CRPT_BA+0x1B8)   /*!< AES DMA Source Address Register for Channel 2      */
+    #define     CRPT_AES2_DADDR     (CRPT_BA+0x1BC)   /*!< AES DMA Destination Address Register for Channel 2 */
+    #define     CRPT_AES2_CNT       (CRPT_BA+0x1C0)   /*!< AES Byte Count Register for Channel 2              */
+    #define     CRPT_AES3_KEY0      (CRPT_BA+0x1C4)   /*!< AES Key Word 0 Register for Channel 3              */
+    #define     CRPT_AES3_KEY1      (CRPT_BA+0x1C8)   /*!< AES Key Word 1 Register for Channel 3              */
+    #define     CRPT_AES3_KEY2      (CRPT_BA+0x1CC)   /*!< AES Key Word 2 Register for Channel 3              */
+    #define     CRPT_AES3_KEY3      (CRPT_BA+0x1D0)   /*!< AES Key Word 3 Register for Channel 3              */
+    #define     CRPT_AES3_KEY4      (CRPT_BA+0x1D4)   /*!< AES Key Word 4 Register for Channel 3              */
+    #define     CRPT_AES3_KEY5      (CRPT_BA+0x1D8)   /*!< AES Key Word 5 Register for Channel 3              */
+    #define     CRPT_AES3_KEY6      (CRPT_BA+0x1DC)   /*!< AES Key Word 6 Register for Channel 3              */
+    #define     CRPT_AES3_KEY7      (CRPT_BA+0x1E0)   /*!< AES Key Word 7 Register for Channel 3              */
+    #define     CRPT_AES3_IV0       (CRPT_BA+0x1E4)   /*!< AES Initial Vector Word 0 Register for Channel 3   */
+    #define     CRPT_AES3_IV1       (CRPT_BA+0x1E8)   /*!< AES Initial Vector Word 1 Register for Channel 3   */
+    #define     CRPT_AES3_IV2       (CRPT_BA+0x1EC)   /*!< AES Initial Vector Word 2 Register for Channel 3   */
+    #define     CRPT_AES3_IV3       (CRPT_BA+0x1F0)   /*!< AES Initial Vector Word 3 Register for Channel 3   */
+    #define     CRPT_AES3_SADDR     (CRPT_BA+0x1F4)   /*!< AES DMA Source Address Register for Channel 3      */
+    #define     CRPT_AES3_DADDR     (CRPT_BA+0x1F8)   /*!< AES DMA Destination Address Register for Channel 3 */
+    #define     CRPT_AES3_CNT       (CRPT_BA+0x1FC)   /*!< AES Byte Count Register for Channel 3              */
+
+    /* DES/TDES Control Registers */
+    #define     CRPT_TDES_CTL       (CRPT_BA+0x200)   /*!< TDES/DES Control Register                          */
+    #define     CRPT_TDES_STS       (CRPT_BA+0x204)   /*!< TDES/DES Engine Flag                               */
+    #define     CRPT_TDES0_KEY1H    (CRPT_BA+0x208)   /*!< TDES/DES Key 1 High Word Register for Channel 0    */
+    #define     CRPT_TDES0_KEY1L    (CRPT_BA+0x20C)   /*!< TDES/DES Key 1 Low Word Register for Channel 0     */
+    #define     CRPT_TDES0_KEY2H    (CRPT_BA+0x210)   /*!< TDES/DES Key 2 High Word Register for Channel 0    */
+    #define     CRPT_TDES0_KEY2L    (CRPT_BA+0x214)   /*!< TDES/DES Key 2 Low Word Register for Channel 0     */
+    #define     CRPT_TDES0_KEY3H    (CRPT_BA+0x218)   /*!< TDES/DES Key 3 High Word Register for Channel 0    */
+    #define     CRPT_TDES0_KEY3L    (CRPT_BA+0x21C)   /*!< TDES/DES Key 3 Low Word Register for Channel 0     */
+    #define     CRPT_TDES0_IVH      (CRPT_BA+0x220)   /*!< TDES/DES Initial Vector High Word Register for Channel 0 */
+    #define     CRPT_TDES0_IVL      (CRPT_BA+0x224)   /*!< TDES/DES Initial Vector Low Word Register for Channel 0  */
+    #define     CRPT_TDES0_SADDR    (CRPT_BA+0x228)   /*!< TDES/DES DMA Source Address Register for Channel 0       */
+    #define     CRPT_TDES0_DADDR    (CRPT_BA+0x22C)   /*!< TDES/DES DMA Destination Address Register for Channel 0  */
+    #define     CRPT_TDES0_CNT      (CRPT_BA+0x230)   /*!< TDES/DES Byte Count Register for Channel 0         */
+    #define     CRPT_TDES_DATIN     (CRPT_BA+0x234)   /*!< TDES/DES Engine Input data Word Register           */
+    #define     CRPT_TDES_DATOUT    (CRPT_BA+0x238)   /*!< TDES/DES Engine Output data Word Register          */
+    #define     CRPT_TDES1_KEY1H    (CRPT_BA+0x248)   /*!< TDES/DES Key 1 High Word Register for Channel 1    */
+    #define     CRPT_TDES1_KEY1L    (CRPT_BA+0x24C)   /*!< TDES/DES Key 1 Low Word Register for Channel 1     */
+    #define     CRPT_TDES1_KEY2H    (CRPT_BA+0x250)   /*!< TDES/DES Key 2 High Word Register for Channel 1    */
+    #define     CRPT_TDES1_KEY2L    (CRPT_BA+0x254)   /*!< TDES/DES Key 2 Low Word Register for Channel 1     */
+    #define     CRPT_TDES1_KEY3H    (CRPT_BA+0x258)   /*!< TDES/DES Key 3 High Word Register for Channel 1    */
+    #define     CRPT_TDES1_KEY3L    (CRPT_BA+0x25C)   /*!< TDES/DES Key 3 Low Word Register for Channel 1     */
+    #define     CRPT_TDES1_IVH      (CRPT_BA+0x260)   /*!< TDES/DES Initial Vector High Word Register for Channel 1 */
+    #define     CRPT_TDES1_IVL      (CRPT_BA+0x264)   /*!< TDES/DES Initial Vector Low Word Register for Channel 1  */
+    #define     CRPT_TDES1_SADDR    (CRPT_BA+0x268)   /*!< TDES/DES DMA Source Address Register for Channel 1       */
+    #define     CRPT_TDES1_DADDR    (CRPT_BA+0x26C)   /*!< TDES/DES DMA Destination Address Register for Channel 1  */
+    #define     CRPT_TDES1_CNT      (CRPT_BA+0x270)   /*!< TDES/DES Byte Count Register for Channel 1         */
+    #define     CRPT_TDES2_KEY1H    (CRPT_BA+0x288)   /*!< TDES/DES Key 1 High Word Register for Channel 2    */
+    #define     CRPT_TDES2_KEY1L    (CRPT_BA+0x28C)   /*!< TDES/DES Key 1 Low Word Register for Channel 2     */
+    #define     CRPT_TDES2_KEY2H    (CRPT_BA+0x290)   /*!< TDES/DES Key 2 High Word Register for Channel 2    */
+    #define     CRPT_TDES2_KEY2L    (CRPT_BA+0x294)   /*!< TDES/DES Key 2 Low Word Register for Channel 2     */
+    #define     CRPT_TDES2_KEY3H    (CRPT_BA+0x298)   /*!< TDES/DES Key 3 High Word Register for Channel 2    */
+    #define     CRPT_TDES2_KEY3L    (CRPT_BA+0x29C)   /*!< TDES/DES Key 3 Low Word Register for Channel 2     */
+    #define     CRPT_TDES2_IVH      (CRPT_BA+0x2A0)   /*!< TDES/DES Initial Vector High Word Register for Channel 2 */
+    #define     CRPT_TDES2_IVL      (CRPT_BA+0x2A4)   /*!< TDES/DES Initial Vector Low Word Register for Channel 2  */
+    #define     CRPT_TDES2_SADDR    (CRPT_BA+0x2A8)   /*!< TDES/DES DMA Source Address Register for Channel 2       */
+    #define     CRPT_TDES2_DADDR    (CRPT_BA+0x2AC)   /*!< TDES/DES DMA Destination Address Register for Channel 2  */
+    #define     CRPT_TDES2_CNT      (CRPT_BA+0x2B0)   /*!< TDES/DES Byte Count Register for Channel 3         */
+    #define     CRPT_TDES3_KEY1H    (CRPT_BA+0x2C8)   /*!< TDES/DES Key 1 High Word Register for Channel 3    */
+    #define     CRPT_TDES3_KEY1L    (CRPT_BA+0x2CC)   /*!< TDES/DES Key 1 Low Word Register for Channel 3     */
+    #define     CRPT_TDES3_KEY2H    (CRPT_BA+0x2D0)   /*!< TDES/DES Key 2 High Word Register for Channel 3    */
+    #define     CRPT_TDES3_KEY2L    (CRPT_BA+0x2D4)   /*!< TDES/DES Key 2 Low Word Register for Channel 3     */
+    #define     CRPT_TDES3_KEY3H    (CRPT_BA+0x2D8)   /*!< TDES/DES Key 3 High Word Register for Channel 3    */
+    #define     CRPT_TDES3_KEY3L    (CRPT_BA+0x2DC)   /*!< TDES/DES Key 3 Low Word Register for Channel 3     */
+    #define     CRPT_TDES3_IVH      (CRPT_BA+0x2E0)   /*!< TDES/DES Initial Vector High Word Register for Channel 3 */
+    #define     CRPT_TDES3_IVL      (CRPT_BA+0x2E4)   /*!< TDES/DES Initial Vector Low Word Register for Channel 3  */
+    #define     CRPT_TDES3_SADDR    (CRPT_BA+0x2E8)   /*!< TDES/DES DMA Source Address Register for Channel 3       */
+    #define     CRPT_TDES3_DADDR    (CRPT_BA+0x2EC)   /*!< TDES/DES DMA Destination Address Register for Channel 3  */
+    #define     CRPT_TDES3_CNT      (CRPT_BA+0x2F0)   /*!< TDES/DES Byte Count Register for Channel 3         */
+
+    /* SHA/HMAC Control Registers */
+    #define     CRPT_HMAC_CTL       (CRPT_BA+0x300)   /*!< SHA/HMAC Control Register                          */
+    #define     CRPT_HMAC_STS       (CRPT_BA+0x304)   /*!< SHA/HMAC Status Flag                               */
+    #define     CRPT_HMAC_DGST0     (CRPT_BA+0x308)   /*!< SHA/HMAC Digest Message 0                          */
+    #define     CRPT_HMAC_DGST1     (CRPT_BA+0x30C)   /*!< SHA/HMAC Digest Message 1                          */
+    #define     CRPT_HMAC_DGST2     (CRPT_BA+0x310)   /*!< SHA/HMAC Digest Message 2                          */
+    #define     CRPT_HMAC_DGST3     (CRPT_BA+0x314)   /*!< SHA/HMAC Digest Message 3                          */
+    #define     CRPT_HMAC_DGST4     (CRPT_BA+0x318)   /*!< SHA/HMAC Digest Message 4                          */
+    #define     CRPT_HMAC_DGST5     (CRPT_BA+0x31C)   /*!< SHA/HMAC Digest Message 5                          */
+    #define     CRPT_HMAC_DGST6     (CRPT_BA+0x320)   /*!< SHA/HMAC Digest Message 6                          */
+    #define     CRPT_HMAC_DGST7     (CRPT_BA+0x324)   /*!< SHA/HMAC Digest Message 7                          */
+    #define     CRPT_HMAC_DGST8     (CRPT_BA+0x328)   /*!< SHA/HMAC Digest Message 8                          */
+    #define     CRPT_HMAC_DGST9     (CRPT_BA+0x32C)   /*!< SHA/HMAC Digest Message 8                          */
+    #define     CRPT_HMAC_DGST10    (CRPT_BA+0x330)   /*!< SHA/HMAC Digest Message 10                         */
+    #define     CRPT_HMAC_DGST11    (CRPT_BA+0x334)   /*!< SHA/HMAC Digest Message 11                         */
+    #define     CRPT_HMAC_DGST12    (CRPT_BA+0x338)   /*!< SHA/HMAC Digest Message 12                         */
+    #define     CRPT_HMAC_DGST13    (CRPT_BA+0x33C)   /*!< SHA/HMAC Digest Message 13                         */
+    #define     CRPT_HMAC_DGST14    (CRPT_BA+0x340)   /*!< SHA/HMAC Digest Message 14                         */
+    #define     CRPT_HMAC_DGST15    (CRPT_BA+0x344)   /*!< SHA/HMAC Digest Message 15                         */
+    #define     CRPT_HMAC_KEYCNT    (CRPT_BA+0x348)   /*!< SHA/HMAC Key Byte Count                            */
+    #define     CRPT_HMAC_SADDR     (CRPT_BA+0x34C)   /*!< SHA/HMAC Key Byte Count                            */
+    #define     CRPT_HMAC_DMACNT    (CRPT_BA+0x350)   /*!< SHA/HMAC Byte Count Register                       */
+    #define     CRPT_HMAC_DATIN     (CRPT_BA+0x354)   /*!< SHA/HMAC Engine Non-DMA Mode Data Input Port Register  */
+
+    /**@}*/ /* end of Cryptographic Accelerator register group */
+
+
+
+
+    /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+    /**
+    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+    Memory Mapped Structure for UART Controller
+    @{ */
+
+    #define     REG_UART0_RBR    (UART0_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART0_THR    (UART0_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART0_IER    (UART0_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART0_FCR    (UART0_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART0_LCR    (UART0_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART0_MCR   (UART0_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART0_MSR    (UART0_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART0_FSR    (UART0_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART0_ISR   (UART0_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART0_TOR       (UART0_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART0_BAUD      (UART0_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART0_IRCR   (UART0_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART0_ALT_CSR   (UART0_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART0_FUN_SEL   (UART0_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART0_LIN_CTL   (UART0_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART0_LIN_SR    (UART0_BA+0x38)  /*!< LIN Status Register */
+
+
+
+
+    /*
+    UART1 Control Registers
+    */
+    #define     REG_UART1_RBR   (UART1_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART1_THR   (UART1_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART1_IER   (UART1_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART1_FCR   (UART1_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART1_LCR   (UART1_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART1_MCR   (UART1_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART1_MSR   (UART1_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART1_FSR       (UART1_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART1_ISR   (UART1_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART1_TOR       (UART1_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART1_BAUD      (UART1_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART1_IRCR      (UART1_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART1_ALT_CSR   (UART1_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART1_FUN_SEL   (UART1_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART1_LIN_CTL   (UART1_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART1_LIN_SR    (UART1_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART2 Control Registers
+    */
+    #define     REG_UART2_RBR   (UART2_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART2_THR   (UART2_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART2_IER   (UART2_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART2_FCR   (UART2_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART2_LCR   (UART2_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART2_MCR   (UART2_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART2_MSR   (UART2_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART2_FSR   (UART2_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART2_ISR   (UART2_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART2_TOR   (UART2_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART2_BAUD  (UART2_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART2_IRCR  (UART2_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART2_ALT_CSR   (UART2_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART2_FUN_SEL   (UART2_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART2_LIN_CTL   (UART2_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART2_LIN_SR    (UART2_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART3 Control Registers
+    */
+    #define     REG_UART3_RBR   (UART3_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART3_THR   (UART3_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART3_IER   (UART3_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART3_FCR   (UART3_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART3_LCR   (UART3_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART3_MCR   (UART3_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART3_MSR   (UART3_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART3_FSR   (UART3_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART3_ISR   (UART3_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART3_TOR   (UART3_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART3_BAUD  (UART3_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART3_IRCR  (UART3_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART3_ALT_CSR   (UART3_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART3_FUN_SEL   (UART3_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART3_LIN_CTL   (UART3_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART3_LIN_SR    (UART3_BA+0x38)  /*!< LIN Status Register */
+
+
+    /*
+    UART4 Control Registers
+    */
+    #define     REG_UART4_RBR   (UART4_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART4_THR   (UART4_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART4_IER   (UART4_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART4_FCR   (UART4_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART4_LCR   (UART4_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART4_MCR   (UART4_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART4_MSR   (UART4_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART4_FSR   (UART4_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART4_ISR   (UART4_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART4_TOR   (UART4_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART4_BAUD  (UART4_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART4_IRCR  (UART4_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART4_ALT_CSR   (UART4_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART4_FUN_SEL   (UART4_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART4_LIN_CTL   (UART4_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART4_LIN_SR    (UART4_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART5 Control Registers
+    */
+    #define     REG_UART5_RBR   (UART5_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART5_THR   (UART5_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART5_IER   (UART5_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART5_FCR   (UART5_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART5_LCR   (UART5_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART5_MCR   (UART5_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART5_MSR   (UART5_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART5_FSR   (UART5_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART5_ISR   (UART5_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART5_TOR   (UART5_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART5_BAUD  (UART5_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART5_IRCR  (UART5_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART5_ALT_CSR   (UART5_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART5_FUN_SEL   (UART5_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART5_LIN_CTL   (UART5_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART5_LIN_SR    (UART5_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART6 Control Registers
+    */
+    #define     REG_UART6_RBR   (UART6_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART6_THR   (UART6_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART6_IER   (UART6_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART6_FCR   (UART6_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART6_LCR   (UART6_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART6_MCR   (UART6_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART6_MSR   (UART6_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART6_FSR   (UART6_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART6_ISR   (UART6_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART6_TOR   (UART6_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART6_BAUD  (UART6_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART6_IRCR  (UART6_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART6_ALT_CSR   (UART6_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART6_FUN_SEL   (UART6_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART6_LIN_CTL   (UART6_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART6_LIN_SR    (UART6_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART7 Control Registers
+    */
+    #define     REG_UART7_RBR   (UART7_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART7_THR   (UART7_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART7_IER   (UART7_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART7_FCR   (UART7_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART7_LCR   (UART7_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART7_MCR   (UART7_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART7_MSR   (UART7_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART7_FSR   (UART7_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART7_ISR   (UART7_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART7_TOR   (UART7_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART7_BAUD  (UART7_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART7_IRCR  (UART7_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART7_ALT_CSR   (UART7_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART7_FUN_SEL   (UART7_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART7_LIN_CTL   (UART7_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART7_LIN_SR    (UART7_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART8 Control Registers
+    */
+    #define     REG_UART8_RBR   (UART8_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART8_THR   (UART8_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART8_IER   (UART8_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART8_FCR   (UART8_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART8_LCR   (UART8_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART8_MCR   (UART8_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART8_MSR   (UART8_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART8_FSR   (UART8_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART8_ISR   (UART8_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART8_TOR   (UART8_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART8_BAUD  (UART8_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART8_IRCR  (UART8_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART8_ALT_CSR   (UART8_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART8_FUN_SEL   (UART8_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART8_LIN_CTL   (UART8_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART8_LIN_SR    (UART8_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UART9 Control Registers
+    */
+    #define     REG_UART9_RBR   (UART9_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UART9_THR   (UART9_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UART9_IER   (UART9_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UART9_FCR   (UART9_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UART9_LCR   (UART9_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UART9_MCR   (UART9_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UART9_MSR   (UART9_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UART9_FSR   (UART9_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UART9_ISR   (UART9_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UART9_TOR   (UART9_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UART9_BAUD  (UART9_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UART9_IRCR  (UART9_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UART9_ALT_CSR   (UART9_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UART9_FUN_SEL   (UART9_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UART9_LIN_CTL   (UART9_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UART9_LIN_SR    (UART9_BA+0x38)  /*!< LIN Status Register */
+
+    /*
+    UARTA Control Registers
+    */
+    #define     REG_UARTA_RBR   (UARTA_BA+0x00)  /*!< Receive Buffer Register */
+    #define     REG_UARTA_THR   (UARTA_BA+0x00)  /*!< Transmit Holding Register */
+    #define     REG_UARTA_IER   (UARTA_BA+0x04)  /*!< Interrupt Enable Register */
+    #define     REG_UARTA_FCR   (UARTA_BA+0x08)  /*!< FIFO Control Register */
+    #define     REG_UARTA_LCR   (UARTA_BA+0x0C)  /*!< Line Control Register */
+    #define     REG_UARTA_MCR   (UARTA_BA+0x10)  /*!< Modem Control Register */
+    #define     REG_UARTA_MSR   (UARTA_BA+0x14)  /*!< MODEM Status Register */
+    #define     REG_UARTA_FSR   (UARTA_BA+0x18)  /*!< FIFO Status Register */
+    #define     REG_UARTA_ISR   (UARTA_BA+0x1C)  /*!< Interrupt Status Control Register */
+    #define     REG_UARTA_TOR   (UARTA_BA+0x20)  /*!< Time-out Register */
+    #define     REG_UARTA_BAUD  (UARTA_BA+0x24)  /*!< Baud Rate Divider Register */
+    #define     REG_UARTA_IRCR  (UARTA_BA+0x28)  /*!< IrDA Control Register */
+    #define     REG_UARTA_ALT_CSR   (UARTA_BA+0x2C)  /*!< Alternate Control Register */
+    #define     REG_UARTA_FUN_SEL   (UARTA_BA+0x30)  /*!< UART Function Select REgister */
+    #define     REG_UARTA_LIN_CTL   (UARTA_BA+0x34)  /*!< UART LIN Control Register */
+    #define     REG_UARTA_LIN_SR    (UARTA_BA+0x38)  /*!< LIN Status Register */
+
+
+    /**@}*/ /* end of UART register group */
+
+
+    /*---------------------- Timer Controller -------------------------*/
+    /**
+    @addtogroup TIMER Timer Controller(TIMER)
+    Memory Mapped Structure for TIMER Controller
+    @{ */
+
+    #define     REG_TMR0_CSR    (TMR0_BA+0x00)  /*!< Timer Control and Status Register 0  */
+    #define     REG_TMR0_CMPR   (TMR0_BA+0x04)  /*!< Timer Compare Register 0             */
+    #define     REG_TMR0_DR     (TMR0_BA+0x08)  /*!< Timer Data Register 0                */
+
+    #define     REG_TMR1_CSR    (TMR1_BA+0x00)  /*!< Timer Control and Status Register 1  */
+    #define     REG_TMR1_CMPR   (TMR1_BA+0x04)  /*!< Timer Compare Register 1             */
+    #define     REG_TMR1_TDR    (TMR1_BA+0x08)  /*!< Timer Data Register 1                */
+
+    #define     REG_TMR2_CSR    (TMR2_BA+0x00)  /*!< Timer Control and Status Register 2  */
+    #define     REG_TMR2_CMPR   (TMR2_BA+0x04)  /*!< Timer Compare Register 2             */
+    #define     REG_TMR2_DR     (TMR2_BA+0x08)  /*!< Timer Data Register 2                */
+
+    #define     REG_TMR3_CSR    (TMR3_BA+0x00)  /*!< Timer Control and Status Register 3  */
+    #define     REG_TMR3_CMPR   (TMR3_BA+0x04)  /*!< Timer Compare Register 3             */
+    #define     REG_TMR3_DR     (TMR3_BA+0x08)  /*!< Timer Data Register 3                */
+
+    #define     REG_TMR4_CSR    (TMR4_BA+0x00)  /*!< Timer Control and Status Register 4  */
+    #define     REG_TMR4_CMPR   (TMR4_BA+0x04)  /*!< Timer Compare Register 4             */
+    #define     REG_TMR4_DR     (TMR4_BA+0x08)  /*!< Timer Data Register 4                */
+
+    #define     REG_TMR_ISR     (TMR0_BA+0x60)  /*!< Timer Interrupt Status Register      */
+
+    /**@}*/ /* end of TIMER register group */
+
+    /*---------------------- Enhance Timer Controller -------------------------*/
+    /**
+    @addtogroup ETIMER Enhance Timer Controller(ETIMER)
+    Memory Mapped Structure for TIMER Controller
+    @{ */
+
+    #define     REG_ETMR0_CTL       (ETMR0_BA+0x00)  /*!< Enhance Timer 0 Control Register */
+    #define     REG_ETMR0_PRECNT    (ETMR0_BA+0x04)  /*!< Enhance Timer 0 Pre-Scale Counter Register */
+    #define     REG_ETMR0_CMPR      (ETMR0_BA+0x08)  /*!< Enhance Timer 0 Compare Register */
+    #define     REG_ETMR0_IER       (ETMR0_BA+0x0C)  /*!< Enhance Timer 0 Interrupt Enable Register */
+    #define     REG_ETMR0_ISR       (ETMR0_BA+0x10)  /*!< Enhance Timer 0 Interrupt Status Register  */
+    #define     REG_ETMR0_DR        (ETMR0_BA+0x14)  /*!< Enhance Timer 0 Data Register */
+    #define     REG_ETMR0_TCAP      (ETMR0_BA+0x18)  /*!< Enhance Timer 0 Capture Data Register  */
+
+    #define     REG_ETMR1_CTL       (ETMR1_BA+0x00)  /*!< Enhance Timer 1 Control Register */
+    #define     REG_ETMR1_PRECNT    (ETMR1_BA+0x04)  /*!< Enhance Timer 1 Pre-Scale Counter Register */
+    #define     REG_ETMR1_CMPR      (ETMR1_BA+0x08)  /*!< Enhance Timer 1 Compare Register */
+    #define     REG_ETMR1_IER       (ETMR1_BA+0x0C)  /*!< Enhance Timer 1 Interrupt Enable Register */
+    #define     REG_ETMR1_ISR       (ETMR1_BA+0x10)  /*!< Enhance Timer 1 Interrupt Status Register  */
+    #define     REG_ETMR1_DR        (ETMR1_BA+0x14)  /*!< Enhance Timer 1 Data Register */
+    #define     REG_ETMR1_TCAP      (ETMR1_BA+0x18)  /*!< Enhance Timer 1 Capture Data Register  */
+
+    #define     REG_ETMR2_CTL       (ETMR2_BA+0x00)  /*!< Enhance Timer 2 Control Register */
+    #define     REG_ETMR2_PRECNT    (ETMR2_BA+0x04)  /*!< Enhance Timer 2 Pre-Scale Counter Register */
+    #define     REG_ETMR2_CMPR      (ETMR2_BA+0x08)  /*!< Enhance Timer 2 Compare Register */
+    #define     REG_ETMR2_IER       (ETMR2_BA+0x0C)  /*!< Enhance Timer 2 Interrupt Enable Register */
+    #define     REG_ETMR2_ISR       (ETMR2_BA+0x10)  /*!< Enhance Timer 2 Interrupt Status Register  */
+    #define     REG_ETMR2_DR        (ETMR2_BA+0x14)  /*!< Enhance Timer 2 Data Register */
+    #define     REG_ETMR2_TCAP      (ETMR2_BA+0x18)  /*!< Enhance Timer 2 Capture Data Register  */
+
+    #define     REG_ETMR3_CTL       (ETMR3_BA+0x00)  /*!< Enhance Timer 3 Control Register */
+    #define     REG_ETMR3_PRECNT    (ETMR3_BA+0x04)  /*!< Enhance Timer 3 Pre-Scale Counter Register */
+    #define     REG_ETMR3_CMPR      (ETMR3_BA+0x08)  /*!< Enhance Timer 3 Compare Register */
+    #define     REG_ETMR3_IER       (ETMR3_BA+0x0C)  /*!< Enhance Timer 3 Interrupt Enable Register */
+    #define     REG_ETMR3_ISR       (ETMR3_BA+0x10)  /*!< Enhance Timer 3 Interrupt Status Register  */
+    #define     REG_ETMR3_DR        (ETMR3_BA+0x14)  /*!< Enhance Timer 3 Data Register */
+    #define     REG_ETMR3_TCAP      (ETMR3_BA+0x18)  /*!< Enhance Timer 3 Capture Data Register  */
+    /**@}*/ /* end of ETIMER register group */
+
+    /*---------------------- WDT Controller -------------------------*/
+    /**
+    @addtogroup WDT Watch Dog Timer Controller(WDT)
+    Memory Mapped Structure for WDT Controller
+    @{ */
+
+    #define     REG_WDT_CTL         (WDT_BA+0x00)  /*!< WDT Control Register              */
+    #define     REG_WDT_ALTCTL      (WDT_BA+0x04)  /*!< WDT Alternative Control Register  */
+
+    /**@}*/ /* end of WDT register group */
+
+    /*---------------------- WWDT Controller -------------------------*/
+    /**
+    @addtogroup WWDT Window Watch Dog Timer Controller(WWDT)
+    Memory Mapped Structure for WWDT Controller
+    @{ */
+
+    #define     REG_WWDT_RLDCNT     (WWDT_BA+0x00)  /*!< WWDT Reload Counter Register             */
+    #define     REG_WWDT_CTL        (WWDT_BA+0x04)  /*!< WWDT Control Register                    */
+    #define     REG_WWDT_STATUS     (WWDT_BA+0x08)  /*!< WWDT Status Register                     */
+    #define     REG_WWDT_CNT        (WWDT_BA+0x0C)  /*!< WWDT Counter Value Register              */
+
+    /**@}*/ /* end of WWDT register group */
+
+    /*---------------------- SC Host Interface -------------------------*/
+    /**
+    @addtogroup SC Smart Card Host Interface (SC)
+    Memory Mapped Structure for Smart Card Host Interface
+    @{ */
+
+    #define     REG_SC0_DAT     (SC0_BA+0x00)  /*!< SC0 Receiving/Transmit Holding Buffer Register */
+    #define     REG_SC0_CTL     (SC0_BA+0x04)  /*!< SC0 Control Register */
+    #define     REG_SC0_ALTCTL  (SC0_BA+0x08)  /*!< SC0 Alternate Control Register  */
+    #define     REG_SC0_EGT     (SC0_BA+0x0C)  /*!< SC0 Extend Guard Time Register  */
+    #define     REG_SC0_RXTOUT  (SC0_BA+0x10)  /*!< SC0 Receive Buffer Time-out Register */
+    #define     REG_SC0_ETUCTL  (SC0_BA+0x14)  /*!< SC0 ETU Control Register */
+    #define     REG_SC0_INTEN   (SC0_BA+0x18)  /*!< SC0 Interrupt Enable Control Register */
+    #define     REG_SC0_INTSTS  (SC0_BA+0x1C)  /*!< SC0 Interrupt Status Register */
+    #define     REG_SC0_STATUS  (SC0_BA+0x20)  /*!< SC0 Status Register */
+    #define     REG_SC0_PINCTL  (SC0_BA+0x24)  /*!< SC0 Pin Control State Register */
+    #define     REG_SC0_TMRCTL0 (SC0_BA+0x28)  /*!< SC0 Internal Timer Control Register 0 */
+    #define     REG_SC0_TMRCTL1 (SC0_BA+0x2C)  /*!< SC0 Internal Timer Control Register 1 */
+    #define     REG_SC0_TMRCTL2 (SC0_BA+0x30)  /*!< SC0 Internal Timer Control Register 2 */
+    #define     REG_SC0_UARTCTL (SC0_BA+0x34)  /*!< SC0 UART Mode Control Register */
+    #define     REG_SC0_TMRDAT0 (SC0_BA+0x38)  /*!< SC0 Timer Current Data Register 0 */
+    #define     REG_SC0_TMRDAT1 (SC0_BA+0x3C)  /*!< SC0 Timer Current Data Register 1 */
+
+    #define     REG_SC1_DAT     (SC1_BA+0x00)  /*!< SC1 Receiving/Transmit Holding Buffer Register */
+    #define     REG_SC1_CTL     (SC1_BA+0x04)  /*!< SC1 Control Register */
+    #define     REG_SC1_ALTCTL  (SC1_BA+0x08)  /*!< SC1 Alternate Control Register  */
+    #define     REG_SC1_EGT     (SC1_BA+0x0C)  /*!< SC1 Extend Guard Time Register  */
+    #define     REG_SC1_RXTOUT  (SC1_BA+0x10)  /*!< SC1 Receive Buffer Time-out Register */
+    #define     REG_SC1_ETUCTL  (SC1_BA+0x14)  /*!< SC1 ETU Control Register */
+    #define     REG_SC1_INTEN   (SC1_BA+0x18)  /*!< SC1 Interrupt Enable Control Register */
+    #define     REG_SC1_INTSTS  (SC1_BA+0x1C)  /*!< SC1 Interrupt Status Register */
+    #define     REG_SC1_STATUS  (SC1_BA+0x20)  /*!< SC1 Status Register */
+    #define     REG_SC1_PINCTL  (SC1_BA+0x24)  /*!< SC1 Pin Control State Register */
+    #define     REG_SC1_TMRCTL0 (SC1_BA+0x28)  /*!< SC1 Internal Timer Control Register 0 */
+    #define     REG_SC1_TMRCTL1 (SC1_BA+0x2C)  /*!< SC1 Internal Timer Control Register 1 */
+    #define     REG_SC1_TMRCTL2 (SC1_BA+0x30)  /*!< SC1 Internal Timer Control Register 2 */
+    #define     REG_SC1_UARTCTL (SC1_BA+0x34)  /*!< SC1 UART Mode Control Register */
+    #define     REG_SC1_TMRDAT0 (SC1_BA+0x38)  /*!< SC1 Timer Current Data Register 0 */
+    #define     REG_SC1_TMRDAT1 (SC1_BA+0x3C)  /*!< SC1 Timer Current Data Register 1 */
+
+    /**@}*/ /* end of SC register group */
+
+
+    /*---------------------- Advance Interrupt Controller -------------------------*/
+    /**
+    @addtogroup AIC Advance Interrupt Controller(AIC)
+    Memory Mapped Structure for AIC Controller
+    @{ */
+
+    #define     REG_AIC_SCR1    (AIC_BA+0x00)    /*!< Source control register 1 */
+    #define     REG_AIC_SCR2    (AIC_BA+0x04)    /*!< Source control register 2 */
+    #define     REG_AIC_SCR3    (AIC_BA+0x08)    /*!< Source control register 3 */
+    #define     REG_AIC_SCR4    (AIC_BA+0x0C)    /*!< Source control register 4 */
+    #define     REG_AIC_SCR5    (AIC_BA+0x10)    /*!< Source control register 5 */
+    #define     REG_AIC_SCR6    (AIC_BA+0x14)    /*!< Source control register 6 */
+    #define     REG_AIC_SCR7    (AIC_BA+0x18)    /*!< Source control register 7 */
+    #define     REG_AIC_SCR8    (AIC_BA+0x1C)    /*!< Source control register 8 */
+    #define     REG_AIC_SCR9    (AIC_BA+0x20)    /*!< Source control register 9 */
+    #define     REG_AIC_SCR10   (AIC_BA+0x24)    /*!< Source control register 10 */
+    #define     REG_AIC_SCR11   (AIC_BA+0x28)    /*!< Source control register 11 */
+    #define     REG_AIC_SCR12   (AIC_BA+0x2C)    /*!< Source control register 12 */
+    #define     REG_AIC_SCR13   (AIC_BA+0x30)    /*!< Source control register 13 */
+    #define     REG_AIC_SCR14   (AIC_BA+0x34)    /*!< Source control register 14 */
+    #define     REG_AIC_SCR15   (AIC_BA+0x38)    /*!< Source control register 15 */
+    #define     REG_AIC_SCR16   (AIC_BA+0x3C)    /*!< Source control register 16 */
+    #define     REG_AIC_IRSR    (AIC_BA+0x100)   /*!< Interrupt raw status register */
+    #define     REG_AIC_IRSRH   (AIC_BA+0x104)   /*!< Interrupt raw status register (Hign) */
+    #define     REG_AIC_IASR    (AIC_BA+0x108)   /*!< Interrupt active status register */
+    #define     REG_AIC_IASRH   (AIC_BA+0x10C)   /*!< Interrupt active status register (Hign) */
+    #define     REG_AIC_ISR     (AIC_BA+0x110)   /*!< Interrupt status register */
+    #define     REG_AIC_ISRH    (AIC_BA+0x114)   /*!< Interrupt status register (High) */
+    #define     REG_AIC_IPER    (AIC_BA+0x118)   /*!< Interrupt priority encoding register */
+    #define     REG_AIC_ISNR    (AIC_BA+0x120)   /*!< Interrupt source number register */
+    #define     REG_AIC_OISR    (AIC_BA+0x124)   /*!< Output interrupt status register */
+    #define     REG_AIC_IMR     (AIC_BA+0x128)   /*!< Interrupt mask register */
+    #define     REG_AIC_IMRH    (AIC_BA+0x12C)   /*!< Interrupt mask register (High) */
+    #define     REG_AIC_MECR    (AIC_BA+0x130)   /*!< Mask enable command register */
+    #define     REG_AIC_MECRH   (AIC_BA+0x134)   /*!< Mask enable command register (High) */
+    #define     REG_AIC_MDCR    (AIC_BA+0x138)   /*!< Mask disable command register */
+    #define     REG_AIC_MDCRH   (AIC_BA+0x13C)   /*!< Mask disable command register (High) */
+    #define     REG_AIC_SSCR    (AIC_BA+0x140)   /*!< Source Set Command Register */
+    #define     REG_AIC_SSCRH   (AIC_BA+0x144)   /*!< Source Set Command Register (High) */
+    #define     REG_AIC_SCCR    (AIC_BA+0x148)   /*!< Source Clear Command Register */
+    #define     REG_AIC_SCCRH   (AIC_BA+0x14C)   /*!< Source Clear Command Register (High) */
+    #define     REG_AIC_EOSCR   (AIC_BA+0x150)   /*!< End of service command register */
+
+    /**@}*/ /* end of AIC register group */
+
+
+    /*---------------------- General Purpose Input/Output Controller -------------------------*/
+    /**
+    @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+    Memory Mapped Structure for GPIO Controller
+    @{ */
+
+    #define     REG_GPIOA_DIR       (GPIO_BA+0x000)  /*!< GPIO portA direction control register */
+    #define     REG_GPIOA_DATAOUT   (GPIO_BA+0x004)  /*!< GPIO portA data output register */
+    #define     REG_GPIOA_DATAIN    (GPIO_BA+0x008)  /*!< GPIO portA data input register */
+    #define     REG_GPIOA_IMD       (GPIO_BA+0x00C)  /*!< GPIO Port A Interrupt Mode Register */
+    #define     REG_GPIOA_IREN      (GPIO_BA+0x010)  /*!< GPIO Port A Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOA_IFEN      (GPIO_BA+0x014)  /*!< GPIO Port A Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOA_ISR       (GPIO_BA+0x018)  /*!< GPIO Port A Interrupt Status Register */
+    #define     REG_GPIOA_DBEN      (GPIO_BA+0x01C)  /*!< GPIO Port A De-bounce Enable Register */
+    #define     REG_GPIOA_PUEN      (GPIO_BA+0x020)  /*!< GPIO Port A Pull-Up Enable Register */
+    #define     REG_GPIOA_PDEN      (GPIO_BA+0x024)  /*!< GPIO Port A Pull-Down Enable Register */
+    #define     REG_GPIOA_ICEN      (GPIO_BA+0x028)  /*!< GPIO Port A CMOS Input Enable Register */
+    #define     REG_GPIOA_ISEN      (GPIO_BA+0x02C)  /*!< GPIO Port A Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOB_DIR       (GPIO_BA+0x040)  /*!< GPIO port B direction control register */
+    #define     REG_GPIOB_DATAOUT   (GPIO_BA+0x044)  /*!< GPIO port B data output register */
+    #define     REG_GPIOB_DATAIN    (GPIO_BA+0x048)  /*!< GPIO port B data input register */
+    #define     REG_GPIOB_IMD       (GPIO_BA+0x04C)  /*!< GPIO Port B Interrupt Mode Register */
+    #define     REG_GPIOB_IREN      (GPIO_BA+0x050)  /*!< GPIO Port B Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOB_IFEN      (GPIO_BA+0x054)  /*!< GPIO Port B Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOB_ISR       (GPIO_BA+0x058)  /*!< GPIO Port B Interrupt Status Register */
+    #define     REG_GPIOB_DBEN      (GPIO_BA+0x05C)  /*!< GPIO Port B De-bounce Enable Register */
+    #define     REG_GPIOB_PUEN      (GPIO_BA+0x060)  /*!< GPIO Port B Pull-Up Enable Register */
+    #define     REG_GPIOB_PDEN      (GPIO_BA+0x064)  /*!< GPIO Port B Pull-Down Enable Register */
+    #define     REG_GPIOB_ICEN      (GPIO_BA+0x068)  /*!< GPIO Port B CMOS Input Enable Register */
+    #define     REG_GPIOB_ISEN      (GPIO_BA+0x06C)  /*!< GPIO Port B Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOC_DIR       (GPIO_BA+0x080)  /*!< GPIO port C direction control register */
+    #define     REG_GPIOC_DATAOUT   (GPIO_BA+0x084)  /*!< GPIO port C data output register */
+    #define     REG_GPIOC_DATAIN    (GPIO_BA+0x088)  /*!< GPIO port C data input register */
+    #define     REG_GPIOC_IMD       (GPIO_BA+0x08C)  /*!< GPIO Port C Interrupt Mode Register */
+    #define     REG_GPIOC_IREN      (GPIO_BA+0x090)  /*!< GPIO Port C Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOC_IFEN      (GPIO_BA+0x094)  /*!< GPIO Port C Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOC_ISR       (GPIO_BA+0x098)  /*!< GPIO Port C Interrupt Status Register */
+    #define     REG_GPIOC_DBEN      (GPIO_BA+0x09C)  /*!< GPIO Port C De-bounce Enable Register */
+    #define     REG_GPIOC_PUEN      (GPIO_BA+0x0A0)  /*!< GPIO Port C Pull-Up Enable Register */
+    #define     REG_GPIOC_PDEN      (GPIO_BA+0x0A4)  /*!< GPIO Port C Pull-Down Enable Register */
+    #define     REG_GPIOC_ICEN      (GPIO_BA+0x0A8)  /*!< GPIO Port C CMOS Input Enable Register */
+    #define     REG_GPIOC_ISEN      (GPIO_BA+0x0AC)  /*!< GPIO Port C Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOD_DIR       (GPIO_BA+0x0C0)  /*!< GPIO port D direction control register */
+    #define     REG_GPIOD_DATAOUT   (GPIO_BA+0x0C4)  /*!< GPIO port D data output register */
+    #define     REG_GPIOD_DATAIN    (GPIO_BA+0x0C8)  /*!< GPIO port D data input register */
+    #define     REG_GPIOD_IMD       (GPIO_BA+0x0CC)  /*!< GPIO Port D Interrupt Mode Register */
+    #define     REG_GPIOD_IREN      (GPIO_BA+0x0D0)  /*!< GPIO Port D Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOD_IFEN      (GPIO_BA+0x0D4)  /*!< GPIO Port D Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOD_ISR       (GPIO_BA+0x0D8)  /*!< GPIO Port D Interrupt Status Register */
+    #define     REG_GPIOD_DBEN      (GPIO_BA+0x0DC)  /*!< GPIO Port D De-bounce Enable Register */
+    #define     REG_GPIOD_PUEN      (GPIO_BA+0x0E0)  /*!< GPIO Port D Pull-Up Enable Register */
+    #define     REG_GPIOD_PDEN      (GPIO_BA+0x0E4)  /*!< GPIO Port D Pull-Down Enable Register */
+    #define     REG_GPIOD_ICEN      (GPIO_BA+0x0E8)  /*!< GPIO Port D CMOS Input Enable Register */
+    #define     REG_GPIOD_ISEN      (GPIO_BA+0x0EC)  /*!< GPIO Port D Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOE_DIR       (GPIO_BA+0x100)  /*!< GPIO port E direction control register */
+    #define     REG_GPIOE_DATAOUT   (GPIO_BA+0x104)  /*!< GPIO port E data output register */
+    #define     REG_GPIOE_DATAIN    (GPIO_BA+0x108)  /*!< GPIO port E data input register */
+    #define     REG_GPIOE_IMD       (GPIO_BA+0x10C)  /*!< GPIO Port E Interrupt Mode Register */
+    #define     REG_GPIOE_IREN      (GPIO_BA+0x110)  /*!< GPIO Port E Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOE_IFEN      (GPIO_BA+0x114)  /*!< GPIO Port E Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOE_ISR       (GPIO_BA+0x118)  /*!< GPIO Port E Interrupt Status Register */
+    #define     REG_GPIOE_DBEN      (GPIO_BA+0x11C)  /*!< GPIO Port E De-bounce Enable Register */
+    #define     REG_GPIOE_PUEN      (GPIO_BA+0x120)  /*!< GPIO Port E Pull-Up Enable Register */
+    #define     REG_GPIOE_PDEN      (GPIO_BA+0x124)  /*!< GPIO Port E Pull-Down Enable Register */
+    #define     REG_GPIOE_ICEN      (GPIO_BA+0x128)  /*!< GPIO Port E CMOS Input Enable Register */
+    #define     REG_GPIOE_ISEN      (GPIO_BA+0x12C)  /*!< GPIO Port E Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOF_DIR       (GPIO_BA+0x140)  /*!< GPIO port F direction control register */
+    #define     REG_GPIOF_DATAOUT   (GPIO_BA+0x144)  /*!< GPIO port F data output register */
+    #define     REG_GPIOF_DATAIN    (GPIO_BA+0x148)  /*!< GPIO port F data input register */
+    #define     REG_GPIOF_IMD       (GPIO_BA+0x14C)  /*!< GPIO Port F Interrupt Mode Register */
+    #define     REG_GPIOF_IREN      (GPIO_BA+0x150)  /*!< GPIO Port F Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOF_IFEN      (GPIO_BA+0x154)  /*!< GPIO Port F Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOF_ISR       (GPIO_BA+0x158)  /*!< GPIO Port F Interrupt Status Register */
+    #define     REG_GPIOF_DBEN      (GPIO_BA+0x15C)  /*!< GPIO Port F De-bounce Enable Register */
+    #define     REG_GPIOF_PUEN      (GPIO_BA+0x160)  /*!< GPIO Port F Pull-Up Enable Register */
+    #define     REG_GPIOF_PDEN      (GPIO_BA+0x164)  /*!< GPIO Port F Pull-Down Enable Register */
+    #define     REG_GPIOF_ICEN      (GPIO_BA+0x168)  /*!< GPIO Port F CMOS Input Enable Register */
+    #define     REG_GPIOF_ISEN      (GPIO_BA+0x16C)  /*!< GPIO Port F Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOG_DIR       (GPIO_BA+0x180)  /*!< GPIO port G direction control register */
+    #define     REG_GPIOG_DATAOUT   (GPIO_BA+0x184)  /*!< GPIO port G data output register */
+    #define     REG_GPIOG_DATAIN    (GPIO_BA+0x188)  /*!< GPIO port G data input register */
+    #define     REG_GPIOG_IMD       (GPIO_BA+0x18C)  /*!< GPIO Port G Interrupt Mode Register */
+    #define     REG_GPIOG_IREN      (GPIO_BA+0x190)  /*!< GPIO Port G Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOG_IFEN      (GPIO_BA+0x194)  /*!< GPIO Port G Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOG_ISR       (GPIO_BA+0x198)  /*!< GPIO Port G Interrupt Status Register */
+    #define     REG_GPIOG_DBEN      (GPIO_BA+0x19C)  /*!< GPIO Port G De-bounce Enable Register */
+    #define     REG_GPIOG_PUEN      (GPIO_BA+0x1A0)  /*!< GPIO Port G Pull-Up Enable Register */
+    #define     REG_GPIOG_PDEN      (GPIO_BA+0x1A4)  /*!< GPIO Port G Pull-Down Enable Register */
+    #define     REG_GPIOG_ICEN      (GPIO_BA+0x1A8)  /*!< GPIO Port G CMOS Input Enable Register */
+    #define     REG_GPIOG_ISEN      (GPIO_BA+0x1AC)  /*!< GPIO Port G Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOH_DIR       (GPIO_BA+0x1C0)  /*!< GPIO port H direction control register */
+    #define     REG_GPIOH_DATAOUT   (GPIO_BA+0x1C4)  /*!< GPIO port H data output register */
+    #define     REG_GPIOH_DATAIN    (GPIO_BA+0x1C8)  /*!< GPIO port H data input register */
+    #define     REG_GPIOH_IMD       (GPIO_BA+0x1CC)  /*!< GPIO Port H Interrupt Mode Register */
+    #define     REG_GPIOH_IREN      (GPIO_BA+0x1D0)  /*!< GPIO Port H Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOH_IFEN      (GPIO_BA+0x1D4)  /*!< GPIO Port H Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOH_ISR       (GPIO_BA+0x1D8)  /*!< GPIO Port H Interrupt Status Register */
+    #define     REG_GPIOH_DBEN      (GPIO_BA+0x1DC)  /*!< GPIO Port H De-bounce Enable Register */
+    #define     REG_GPIOH_PUEN      (GPIO_BA+0x1E0)  /*!< GPIO Port H Pull-Up Enable Register */
+    #define     REG_GPIOH_PDEN      (GPIO_BA+0x1E4)  /*!< GPIO Port H Pull-Down Enable Register */
+    #define     REG_GPIOH_ICEN      (GPIO_BA+0x1E8)  /*!< GPIO Port H CMOS Input Enable Register */
+    #define     REG_GPIOH_ISEN      (GPIO_BA+0x1EC)  /*!< GPIO Port H Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOI_DIR       (GPIO_BA+0x200)  /*!< GPIO port I direction control register */
+    #define     REG_GPIOI_DATAOUT   (GPIO_BA+0x204)  /*!< GPIO port I data output register */
+    #define     REG_GPIOI_DATAIN    (GPIO_BA+0x208)  /*!< GPIO port I data input register */
+    #define     REG_GPIOI_IMD       (GPIO_BA+0x20C)  /*!< GPIO Port I Interrupt Mode Register */
+    #define     REG_GPIOI_IREN      (GPIO_BA+0x210)  /*!< GPIO Port I Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOI_IFEN      (GPIO_BA+0x214)  /*!< GPIO Port I Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOI_ISR       (GPIO_BA+0x218)  /*!< GPIO Port I Interrupt Status Register */
+    #define     REG_GPIOI_DBEN      (GPIO_BA+0x21C)  /*!< GPIO Port I De-bounce Enable Register */
+    #define     REG_GPIOI_PUEN      (GPIO_BA+0x220)  /*!< GPIO Port I Pull-Up Enable Register */
+    #define     REG_GPIOI_PDEN      (GPIO_BA+0x224)  /*!< GPIO Port I Pull-Down Enable Register */
+    #define     REG_GPIOI_ICEN      (GPIO_BA+0x228)  /*!< GPIO Port I CMOS Input Enable Register */
+    #define     REG_GPIOI_ISEN      (GPIO_BA+0x22C)  /*!< GPIO Port I Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIOJ_DIR       (GPIO_BA+0x240)  /*!< GPIO port J direction control register */
+    #define     REG_GPIOJ_DATAOUT   (GPIO_BA+0x244)  /*!< GPIO port J data output register */
+    #define     REG_GPIOJ_DATAIN    (GPIO_BA+0x248)  /*!< GPIO port J data input register */
+    #define     REG_GPIOJ_IMD       (GPIO_BA+0x24C)  /*!< GPIO Port J Interrupt Mode Register */
+    #define     REG_GPIOJ_IREN      (GPIO_BA+0x250)  /*!< GPIO Port J Interrupt Rising-Edge or Level-High Enable Register */
+    #define     REG_GPIOJ_IFEN      (GPIO_BA+0x254)  /*!< GPIO Port J Interrupt Falling-Edge or Level-Low Enable Register */
+    #define     REG_GPIOJ_ISR       (GPIO_BA+0x258)  /*!< GPIO Port J Interrupt Status Register */
+    #define     REG_GPIOJ_DBEN      (GPIO_BA+0x25C)  /*!< GPIO Port J De-bounce Enable Register */
+    #define     REG_GPIOJ_PUEN      (GPIO_BA+0x260)  /*!< GPIO Port J Pull-Up Enable Register */
+    #define     REG_GPIOJ_PDEN      (GPIO_BA+0x264)  /*!< GPIO Port J Pull-Down Enable Register */
+    #define     REG_GPIOJ_ICEN      (GPIO_BA+0x268)  /*!< GPIO Port J CMOS Input Enable Register */
+    #define     REG_GPIOJ_ISEN      (GPIO_BA+0x26C)  /*!< GPIO Port J Schmitt-Trigger Input Enable Register */
+
+    #define     REG_GPIO_DBNCECON   (GPIO_BA+0x3F0)  /*!< GPIO Debounce Control Register */
+    #define     REG_GPIO_ISR        (GPIO_BA+0x3FC)  /*!< GPIO Port Interrupt Status Register */
+
+    /**@}*/ /* end of GPIO register group */
+
+
+    /*---------------------- Real Time Clock Controller -------------------------*/
+    /**
+    @addtogroup RTC Real Time Clock Controller(RTC)
+    Memory Mapped Structure for RTC Controller
+    @{ */
+
+    #define     REG_RTC_INIT    (RTC_BA+0x00)   /*!< RTC Initiation Register */
+    #define     REG_RTC_RWEN    (RTC_BA+0x04)   /*!< RTC Access Enable Register */
+    #define     REG_RTC_FREQADJ (RTC_BA+0x08)   /*!< RTC Frequency Compensation Register */
+    #define     REG_RTC_TIME    (RTC_BA+0x0C)   /*!< Time Loading Register */
+    #define     REG_RTC_CAL     (RTC_BA+0x10)   /*!< Calendar Loading Register */
+    #define     REG_RTC_TIMEFMT (RTC_BA+0x14)   /*!< Time Format Selection Register */
+    #define     REG_RTC_WEEKDAY (RTC_BA+0x18)   /*!< Day of the Week Register */
+    #define     REG_RTC_TALM    (RTC_BA+0x1C)   /*!< Time Alarm Register */
+    #define     REG_RTC_CALM    (RTC_BA+0x20)   /*!< Calendar Alarm Register */
+    #define     REG_RTC_LEAPYEAR    (RTC_BA+0x24)   /*!< Leap year Indicator Register */
+    #define     REG_RTC_INTEN   (RTC_BA+0x28)   /*!< RTC Interrupt Enable Register */
+    #define     REG_RTC_INTSTS  (RTC_BA+0x2C)   /*!< RTC Interrupt Indicator Register */
+    #define     REG_RTC_TICK    (RTC_BA+0x30)   /*!< RTC Time Tick Register */
+    #define     REG_RTC_PWRCTL      (RTC_BA+0x34)   /*!< Power Control Register */
+    #define     REG_RTC_PWRCNT      (RTC_BA+0x38)   /*!< Power Control Counter Register */
+    #define     REG_RTC_SPR0        (RTC_BA+0x40)   /*!< Spare REgistger 0 */
+    #define     REG_RTC_SPR1        (RTC_BA+0x44)   /*!< Spare REgistger 1 */
+    #define     REG_RTC_SPR2        (RTC_BA+0x48)   /*!< Spare REgistger 2 */
+    #define     REG_RTC_SPR3        (RTC_BA+0x4C)   /*!< Spare REgistger 3 */
+    #define     REG_RTC_SPR4        (RTC_BA+0x50)   /*!< Spare REgistger 4 */
+    #define     REG_RTC_SPR5        (RTC_BA+0x54)   /*!< Spare REgistger 5 */
+    #define     REG_RTC_SPR6        (RTC_BA+0x58)   /*!< Spare REgistger 6 */
+    #define     REG_RTC_SPR7        (RTC_BA+0x5C)   /*!< Spare REgistger 7 */
+    #define     REG_RTC_SPR8        (RTC_BA+0x60)   /*!< Spare REgistger 8 */
+    #define     REG_RTC_SPR9        (RTC_BA+0x64)   /*!< Spare REgistger 9 */
+    #define     REG_RTC_SPR10       (RTC_BA+0x68)   /*!< Spare REgistger 10 */
+    #define     REG_RTC_SPR11       (RTC_BA+0x6C)   /*!< Spare REgistger 11 */
+    #define     REG_RTC_SPR12       (RTC_BA+0x70)   /*!< Spare REgistger 12 */
+    #define     REG_RTC_SPR13       (RTC_BA+0x74)   /*!< Spare REgistger 13 */
+    #define     REG_RTC_SPR14       (RTC_BA+0x78)   /*!< Spare REgistger 14 */
+    #define     REG_RTC_SPR15       (RTC_BA+0x7C)   /*!< Spare REgistger 15 */
+
+    /**@}*/ /* end of RTC register group */
+
+    /*---------------------- Inter-IC Bus Controller -------------------------*/
+    /**
+    @addtogroup I2C Inter-IC Bus Controller(I2C)
+    Memory Mapped Structure for I2C Controller
+    @{ */
+
+    #define     REG_I2C0_CSR        (I2C0_BA+0x00)  /*!< Control and Status Register */
+    #define     REG_I2C0_DIVIDER    (I2C0_BA+0x04)  /*!< Clock Prescale Register */
+    #define     REG_I2C0_CMDR       (I2C0_BA+0x08)  /*!< Command Register */
+    #define     REG_I2C0_SWR        (I2C0_BA+0x0C)  /*!< Software Mode Control Register */
+    #define     REG_I2C0_RXR        (I2C0_BA+0x10)  /*!< Data Receive Register */
+    #define     REG_I2C0_TXR        (I2C0_BA+0x14)  /*!< Data Transmit Register */
+
+    #define     REG_I2C1_CSR        (I2C1_BA+0x00)  /*!< Control and Status Register */
+    #define     REG_I2C1_DIVIDER    (I2C1_BA+0x04)  /*!< Clock Prescale Register */
+    #define     REG_I2C1_CMDR       (I2C1_BA+0x08)  /*!< Command Register */
+    #define     REG_I2C1_SWR        (I2C1_BA+0x0C)  /*!< Software Mode Control Register */
+    #define     REG_I2C1_RXR        (I2C1_BA+0x10)  /*!< Data Receive Register */
+    #define     REG_I2C1_TXR        (I2C1_BA+0x14)  /*!< Data Transmit Register */
+
+    /**@}*/ /* end of I2C register group */
+
+
+    /*---------------------- Serial Peripheral Interface Controller -------------------------*/
+    /**
+    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+    Memory Mapped Structure for SPI Controller
+    @{ */
+
+    #define     REG_SPI0_CNTRL   (SPI0_BA+0x00)  /*!< Control and Status Register */
+    #define     REG_SPI0_DIVIDER (SPI0_BA+0x04)  /*!< Clock Divider Register */
+    #define     REG_SPI0_SSR     (SPI0_BA+0x08)  /*!< Slave Select Register */
+    #define     REG_SPI0_RX0     (SPI0_BA+0x10)  /*!< Data Receive Register 0 */
+    #define     REG_SPI0_RX1     (SPI0_BA+0x14)  /*!< Data Receive Register 1 */
+    #define     REG_SPI0_RX2     (SPI0_BA+0x18)  /*!< Data Receive Register 2 */
+    #define     REG_SPI0_RX3     (SPI0_BA+0x1C)  /*!< Data Receive Register 3 */
+    #define     REG_SPI0_TX0     (SPI0_BA+0x10)  /*!< Data Transmit Register 0 */
+    #define     REG_SPI0_TX1     (SPI0_BA+0x14)  /*!< Data Transmit Register 1 */
+    #define     REG_SPI0_TX2     (SPI0_BA+0x18)  /*!< Data Transmit Register 2 */
+    #define     REG_SPI0_TX3     (SPI0_BA+0x1C)  /*!< Data Transmit Register 3 */
+
+    #define     REG_SPI1_CNTRL   (SPI1_BA+0x00)  /*!< Control and Status Register */
+    #define     REG_SPI1_DIVIDER (SPI1_BA+0x04)  /*!< Clock Divider Register */
+    #define     REG_SPI1_SSR     (SPI1_BA+0x08)  /*!< Slave Select Register */
+    #define     REG_SPI1_RX0     (SPI1_BA+0x10)  /*!< Data Receive Register 0 */
+    #define     REG_SPI1_RX1     (SPI1_BA+0x14)  /*!< Data Receive Register 1 */
+    #define     REG_SPI1_RX2     (SPI1_BA+0x18)  /*!< Data Receive Register 2 */
+    #define     REG_SPI1_RX3     (SPI1_BA+0x1C)  /*!< Data Receive Register 3 */
+    #define     REG_SPI1_TX0     (SPI1_BA+0x10)  /*!< Data Transmit Register 0 */
+    #define     REG_SPI1_TX1     (SPI1_BA+0x14)  /*!< Data Transmit Register 1 */
+    #define     REG_SPI1_TX2     (SPI1_BA+0x18)  /*!< Data Transmit Register 2 */
+    #define     REG_SPI1_TX3     (SPI1_BA+0x1C)  /*!< Data Transmit Register 3 */
+
+    /**@}*/ /* end of SPI register group */
+
+
+    /*---------------------- Pulse Width Modulation Controller -------------------------*/
+    /**
+    @addtogroup PWM Pulse Width Modulation Controller(PWM)
+    Memory Mapped Structure for PWM Controller
+    @{ */
+
+    #define     REG_PWM_PPR     (PWM_BA+0x00)  /*!< PWM Pre-scale Register 0 */
+    #define     REG_PWM_CSR     (PWM_BA+0x04)  /*!< PWM Clock Select Register */
+    #define     REG_PWM_PCR     (PWM_BA+0x08)  /*!< PWM Control Register */
+    #define     REG_PWM_CNR0    (PWM_BA+0x0C)  /*!< PWM Counter Register 0 */
+    #define     REG_PWM_CMR0    (PWM_BA+0x10)  /*!< PWM Comparator Register 0 */
+    #define     REG_PWM_PDR0    (PWM_BA+0x14)  /*!< PWM Data Register 0 */
+    #define     REG_PWM_CNR1    (PWM_BA+0x18)  /*!< PWM Counter Register 1 */
+    #define     REG_PWM_CMR1    (PWM_BA+0x1C)  /*!< PWM Comparator Register 1 */
+    #define     REG_PWM_PDR1    (PWM_BA+0x20)  /*!< PWM Data Register 1 */
+    #define     REG_PWM_CNR2    (PWM_BA+0x24)  /*!< PWM Counter Register 2 */
+    #define     REG_PWM_CMR2    (PWM_BA+0x28)  /*!< PWM Comparator Register 2 */
+    #define     REG_PWM_PDR2    (PWM_BA+0x2C)  /*!< PWM Data Register 2 */
+    #define     REG_PWM_CNR3    (PWM_BA+0x30)  /*!< PWM Counter Register 3 */
+    #define     REG_PWM_CMR3    (PWM_BA+0x34)  /*!< PWM Comparator Register 3 */
+    #define     REG_PWM_PDR3    (PWM_BA+0x38)  /*!< PWM Data Register 3 */
+    #define     REG_PWM_PIER    (PWM_BA+0x3C)  /*!< PWM Timer Interrupt Enable Register */
+    #define     REG_PWM_PIIR    (PWM_BA+0x40)  /*!< PWM Timer Interrupt Identification Register */
+
+    /**@}*/ /* end of PWM register group */
+
+
+    /*---------------------- Analog to Digital Converter -------------------------*/
+    /**
+    @addtogroup ADC Analog to Digital Converter(ADC)
+    Memory Mapped Structure for ADC Controller
+    @{ */
+
+    #define REG_ADC_CTL       (ADC_BA+0x000) /*!< ADC Contrl */
+    #define REG_ADC_CONF      (ADC_BA+0x004) /*!< ADC Configure */
+    #define REG_ADC_IER       (ADC_BA+0x008) /*!< ADC Interrupt Enable Register */
+    #define REG_ADC_ISR       (ADC_BA+0x00C) /*!< ADC Interrupt Status Register */
+    #define REG_ADC_WKISR     (ADC_BA+0x010) /*!< ADC Wake Up Interrupt Status Register */
+    #define REG_ADC_XYDATA    (ADC_BA+0x020) /*!< ADC Touch XY Pressure Data */
+    #define REG_ADC_ZDATA     (ADC_BA+0x024) /*!< ADC Touch Z Pressure Data */
+    #define REG_ADC_DATA      (ADC_BA+0x028) /*!< ADC Normal Conversion Data */
+    #define REG_ADC_VBADATA   (ADC_BA+0x02C) /*!< ADC Battery Detection Data */
+    #define REG_ADC_KPDATA    (ADC_BA+0x030) /*!< ADC Key Pad Data */
+    #define REG_ADC_SELFDATA  (ADC_BA+0x034) /*!< ADC Self-Test Data */
+    #define REG_ADC_XYSORT0   (ADC_BA+0x1F4) /*!< ADC Touch XY Position Mean Value Sort 0 */
+    #define REG_ADC_XYSORT1   (ADC_BA+0x1F8) /*!< ADC Touch XY Position Mean Value Sort 1 */
+    #define REG_ADC_XYSORT2   (ADC_BA+0x1FC) /*!< ADC Touch XY Position Mean Value Sort 2 */
+    #define REG_ADC_XYSORT3   (ADC_BA+0x200) /*!< ADC Touch XY Position Mean Value Sort 3 */
+    #define REG_ADC_ZSORT0    (ADC_BA+0x204) /*!< ADC Touch Z Pressure Mean Value Sort 0 */
+    #define REG_ADC_ZSORT1    (ADC_BA+0x208) /*!< ADC Touch Z Pressure Mean Value Sort 1 */
+    #define REG_ADC_ZSORT2    (ADC_BA+0x20C) /*!< ADC Touch Z Pressure Mean Value Sort 2 */
+    #define REG_ADC_ZSORT3    (ADC_BA+0x210) /*!< ADC Touch Z Pressure Mean Value Sort 3 */
+    #define REG_ADC_MTMULCK   (ADC_BA+0x220) /*!< ADC Manual Test Mode Unlock */
+    #define REG_ADC_MTCONF    (ADC_BA+0x224) /*!< ADC Manual Test Mode Configure */
+    #define REG_ADC_MTCON     (ADC_BA+0x228) /*!< ADC Manual Test Mode Control */
+    #define REG_ADC_ADCAII    (ADC_BA+0x22C) /*!< ADC Analog Interface Information */
+    #define REG_ADC_ADCAIIRLT (ADC_BA+0x230) /*!< ADC Analog Interface Information Result */
+
+    /**@}*/ /* end of ADC register group */
+
+    /*------------------ Capture Sensor Interface Controller ---------------------*/
+    /**
+    @addtogroup CAP Capture Sensor Interface Controller(CAP)
+    Memory Mapped Structure for CAP Controller
+    @{ */
+
+    #define REG_CAP_CTL            (CAP_BA+0x000)  /*!< Image Capture Interface Control Register */
+    #define REG_CAP_PAR            (CAP_BA+0x004)  /*!< Image Capture Interface Parameter Register */
+    #define REG_CAP_INT            (CAP_BA+0x008)  /*!< Image Capture Interface Interrupt Registe */
+    #define REG_CAP_POSTERIZE      (CAP_BA+0x00C)  /*!< YUV Component Posterizing Factor Register */
+    #define REG_CAP_MD             (CAP_BA+0x010)  /*!< Motion Detection Register */
+    #define REG_CAP_MDADDR         (CAP_BA+0x014)  /*!< Motion Detection Output Address Register */
+    #define REG_CAP_MDYADDR        (CAP_BA+0x018)  /*!< Motion Detection Temp YOutput Address Register */
+    #define REG_CAP_SEPIA          (CAP_BA+0x01C)  /*!< Sepia Effect Control Register */
+    #define REG_CAP_CWSP           (CAP_BA+0x020)  /*!< Cropping Window Starting Address Register */
+    #define REG_CAP_CWS            (CAP_BA+0x024)  /*!< Cropping Window Size Register */
+    #define REG_CAP_PKTSL          (CAP_BA+0x028)  /*!< Packet Scaling Vertical/Horizontal Factor Register (LSB) */
+    #define REG_CAP_PLNSL          (CAP_BA+0x02C)  /*!< Planar Scaling Vertical/Horizontal Factor Register (LSB) */
+    #define REG_CAP_FRCTL          (CAP_BA+0x030)  /*!< Scaling Frame Rate Factor Register */
+    #define REG_CAP_STRIDE         (CAP_BA+0x034)  /*!< Frame Output Pixel Stride Register */
+    #define REG_CAP_FIFOTH         (CAP_BA+0x03C)  /*!< FIFO threshold Register */
+    #define REG_CAP_CMPADDR        (CAP_BA+0x040)  /*!< Compare Packet Memory Base Address Register */
+    #define REG_CAP_PKTSM          (CAP_BA+0x048)  /*!< Packet Scaling Vertical/Horizontal Factor Register (MSB) */
+    #define REG_CAP_PLNSM          (CAP_BA+0x04C)  /*!< Planar Scaling Vertical/Horizontal Factor Register (MSB) */
+    #define REG_CAP_CURADDRP       (CAP_BA+0x050)  /*!< Current Packet System Memory Address Register */
+    #define REG_CAP_CURADDRY       (CAP_BA+0x054)  /*!< Current Planar Y System Memory Address Register */
+    #define REG_CAP_CURADDRU       (CAP_BA+0x058)  /*!< Current Planar U System Memory Address Register */
+    #define REG_CAP_CURADDRV       (CAP_BA+0x05C)  /*!< Current Planar V System Memory Address Register */
+    #define REG_CAP_PKTBA0         (CAP_BA+0x060)  /*!< System Memory Packet Base Address Register */
+    #define REG_CAP_PKTBA1         (CAP_BA+0x064)  /*!< System Memory Packet Base Address Register */
+    #define REG_CAP_YBA            (CAP_BA+0x080)  /*!< System Memory Planar Y Base Address Register */
+    #define REG_CAP_UBA            (CAP_BA+0x084)  /*!< System Memory Planar U Base Address Register */
+    #define REG_CAP_VBA            (CAP_BA+0x088)  /*!< System Memory Planar V Base Address Register */
+
+    /**@}*/ /* end of CAP register group */
+
+    /*------------------ SDRAM Interface Controller ---------------------*/
+    /**
+    @addtogroup SDIC SDRAM Interface Controller(SDIC)
+    Memory Mapped Structure for SDIC Controller
+    @{ */
+
+    #define REG_SDIC_OPMCTL     (SDIC_BA+0x000)    /*!< SDRAM Controller Operation Mode Control Register */
+    #define REG_SDIC_CMD        (SDIC_BA+0x004)    /*!< SDRAM Command Register */
+    #define REG_SDIC_REFCTL     (SDIC_BA+0x008)    /*!< SDRAM Controller Refresh Control Register */
+    #define REG_SDIC_SIZE0      (SDIC_BA+0x010)    /*!< SDRAM 0 Size Register */
+    #define REG_SDIC_SIZE1      (SDIC_BA+0x014)    /*!< SDRAM 1 Size Register */
+    #define REG_SDIC_MR         (SDIC_BA+0x018)    /*!< SDRAM Mode Register */
+    #define REG_SDIC_EMR        (SDIC_BA+0x01C)    /*!< SDRAM Extended Mode Register */
+    #define REG_SDIC_EMR2       (SDIC_BA+0x020)    /*!< SDRAM Extended Mode Register 2 */
+    #define REG_SDIC_EMR3       (SDIC_BA+0x024)    /*!< SDRAM Extended Mode Register 3 */
+    #define REG_SDIC_TIME       (SDIC_BA+0x028)    /*!< SDRAM Timing Control Register */
+    #define REG_SDIC_DQSODS     (SDIC_BA+0x030)    /*!< DQS Output Delay Selection Register */
+    #define REG_SDIC_CKDQSDS    (SDIC_BA+0x034)    /*!< Clock and DQS Delay Selection Register */
+    #define REG_SDIC_DAENSEL    (SDIC_BA+0x038)    /*!< Data Latch Enable Selection Register */
+
+    /**@}*/ /* end of SDIC register group */
+
+    /*---------------------- Controller Area Network -------------------------*/
+    /**
+    @addtogroup CAN Controller Area Network(CAN)
+    Memory Mapped Structure for CAN Controller
+    @{ */
+
+    #define REG_CAN0_CON       (CAN0_BA+0x00) /*!< Control Register */
+    #define REG_CAN0_STATUS    (CAN0_BA+0x04) /*!< Status Register */
+    #define REG_CAN0_ERR       (CAN0_BA+0x08) /*!< Error Counter Register */
+    #define REG_CAN0_BTIME     (CAN0_BA+0x0C) /*!< Bit Time Register */
+    #define REG_CAN0_IIDR      (CAN0_BA+0x10) /*!< Interrupt Identifier Register */
+    #define REG_CAN0_TEST      (CAN0_BA+0x14) /*!< Test Register */
+    #define REG_CAN0_BRPE      (CAN0_BA+0x18) /*!< BRP Extension Register */
+    #define REG_CAN0_IF1_CREQ  (CAN0_BA+0x20) /*!< IF1 Command Request Register */
+    #define REG_CAN0_IF2_CREQ  (CAN0_BA+0x80) /*!< IF2 Command Request Register */
+    #define REG_CAN0_IF1_CMASK (CAN0_BA+0x24) /*!< IF1 Command Mask Register */
+    #define REG_CAN0_IF2_CMASK (CAN0_BA+0x84) /*!< IF2 Command Mask Register */
+    #define REG_CAN0_IF1_MASK1 (CAN0_BA+0x28) /*!< IF1 Msak 1 Register */
+    #define REG_CNA0_IF2_MASK1 (CAN0_BA+0x88) /*!< IF2 Mask 1 Register */
+    #define REG_CAN0_IF1_MASK2 (CAN0_BA+0x2C) /*!< IF1 Mask 2 Register */
+    #define REG_CAN0_IF2_MASK2 (CAN0_BA+0x8C) /*!< IF2 Mask 2 REgister */
+    #define REG_CAN0_IF1_ARB1  (CAN0_BA+0x30) /*!< IF1 Arbitration 1 Register */
+    #define REG_CAN0_IF2_ARB1  (CAN0_BA+0x90) /*!< IF2 Arbitration 1 Register */
+    #define REG_CAN0_IF1_ARB2  (CAN0_BA+0x34) /*!< IF1 Arbitration 2 Register */
+    #define REG_CAN0_IF2_ARB2  (CAN0_BA+0x94) /*!< IF2 Arbitration 2 Register */
+    #define REG_CAN0_IF1_MCON  (CAN0_BA+0x38) /*!< IF1 Message Control Register */
+    #define REG_CAN0_IF2_MCON  (CAN0_BA+0x98) /*!< IF2 Message Control Register */
+    #define REG_CAN0_IF1_DAT_A1 (CAN0_BA+0x3C) /*!< IF1 Data A1 Register */
+    #define REG_CAN0_IF1_DAT_A2 (CAN0_BA+0x40) /*!< IF1 Data A2 Register */
+    #define REG_CAN0_IF1_DAT_B1 (CAN0_BA+0x44) /*!< IF1 Data B1 Register */
+    #define REG_CAN0_IF1_DAT_B2 (CAN0_BA+0x48) /*!< IF1 Data B2 Register */
+    #define REG_CAN0_IF2_DAT_A1 (CAN0_BA+0x9C) /*!< IF2 Data A1 Register */
+    #define REG_CAN0_IF2_DAT_A2 (CAN0_BA+0xA0) /*!< IF2 Data A2 Register */
+    #define REG_CAN0_IF2_DAT_B1 (CAN0_BA+0xA4) /*!< IF2 Data B1 Register */
+    #define REG_CAN0_IF2_DAT_B2 (CAN0_BA+0xA8) /*!< IF2 Data B2 Register */
+    #define REG_CAN0_TXREQ1     (CAN0_BA+0x100) /*!< Transmission Request Register 1 */
+    #define REG_CAN0_TXREQ2     (CAN0_BA+0x104) /*!< Transmission Request Register 2 */
+    #define REG_CAN0_NDAT1      (CAN0_BA+0x120) /*!< New Data Register 1 */
+    #define REG_CAN0_NDAT2      (CAN0_BA+0x124) /*!< New Data Register 2 */
+    #define REG_CAN0_IPND1      (CAN0_BA+0x140) /*!< Interrupt Pending Register 1 */
+    #define REG_CAN0_IPND2      (CAN0_BA+0x142) /*!< Interrupt Pending Register 2 */
+    #define REG_CAN0_MVLD1      (CAN0_BA+0x160) /*!< Message Valid Register 1 */
+    #define REG_CAN0_MVLD2      (CAN0_BA+0x164) /*!< Message Valid Register 2 */
+    #define REG_CAN0_WU_EN      (CAN0_BA+0x168) /*!< Wake-up Function Enable */
+    #define REG_CAN0_WU_STATUS  (CAN0_BA+0x16C) /*!< Wake-up Function Status */
+
+    #define REG_CAN1_CON       (CAN1_BA+0x00) /*!< Control Register */
+    #define REG_CAN1_STATUS    (CAN1_BA+0x04) /*!< Status Register */
+    #define REG_CAN1_ERR       (CAN1_BA+0x08) /*!< Error Counter Register */
+    #define REG_CAN1_BTIME     (CAN1_BA+0x0C) /*!< Bit Time Register */
+    #define REG_CAN1_IIDR      (CAN1_BA+0x10) /*!< Interrupt Identifier Register */
+    #define REG_CAN1_TEST      (CAN1_BA+0x14) /*!< Test Register */
+    #define REG_CAN1_BRPE      (CAN1_BA+0x18) /*!< BRP Extension Register */
+    #define REG_CAN1_IF1_CREQ  (CAN1_BA+0x20) /*!< IF1 Command Request Register */
+    #define REG_CAN1_IF2_CREQ  (CAN1_BA+0x80) /*!< IF2 Command Request Register */
+    #define REG_CAN1_IF1_CMASK (CAN1_BA+0x24) /*!< IF1 Command Mask Register */
+    #define REG_CAN1_IF2_CMASK (CAN1_BA+0x84) /*!< IF2 Command Mask Register */
+    #define REG_CAN1_IF1_MASK1 (CAN1_BA+0x28) /*!< IF1 Msak 1 Register */
+    #define REG_CNA1_IF2_MASK1 (CAN1_BA+0x88) /*!< IF2 Mask 1 Register */
+    #define REG_CAN1_IF1_MASK2 (CAN1_BA+0x2C) /*!< IF1 Mask 2 Register */
+    #define REG_CAN1_IF2_MASK2 (CAN1_BA+0x8C) /*!< IF2 Mask 2 REgister */
+    #define REG_CAN1_IF1_ARB1  (CAN1_BA+0x30) /*!< IF1 Arbitration 1 Register */
+    #define REG_CAN1_IF2_ARB1  (CAN1_BA+0x90) /*!< IF2 Arbitration 1 Register */
+    #define REG_CAN1_IF1_ARB2  (CAN1_BA+0x34) /*!< IF1 Arbitration 2 Register */
+    #define REG_CAN1_IF2_ARB2  (CAN1_BA+0x94) /*!< IF2 Arbitration 2 Register */
+    #define REG_CAN1_IF1_MCON  (CAN1_BA+0x38) /*!< IF1 Message Control Register */
+    #define REG_CAN1_IF2_MCON  (CAN1_BA+0x98) /*!< IF2 Message Control Register */
+    #define REG_CAN1_IF1_DAT_A1 (CAN1_BA+0x3C) /*!< IF1 Data A1 Register */
+    #define REG_CAN1_IF1_DAT_A2 (CAN1_BA+0x40) /*!< IF1 Data A2 Register */
+    #define REG_CAN1_IF1_DAT_B1 (CAN1_BA+0x44) /*!< IF1 Data B1 Register */
+    #define REG_CAN1_IF1_DAT_B2 (CAN1_BA+0x48) /*!< IF1 Data B2 Register */
+    #define REG_CAN1_IF2_DAT_A1 (CAN1_BA+0x9C) /*!< IF2 Data A1 Register */
+    #define REG_CAN1_IF2_DAT_A2 (CAN1_BA+0xA0) /*!< IF2 Data A2 Register */
+    #define REG_CAN1_IF2_DAT_B1 (CAN1_BA+0xA4) /*!< IF2 Data B1 Register */
+    #define REG_CAN1_IF2_DAT_B2 (CAN1_BA+0xA8) /*!< IF2 Data B2 Register */
+    #define REG_CAN1_TXREQ1     (CAN1_BA+0x100) /*!< Transmission Request Register 1 */
+    #define REG_CAN1_TXREQ2     (CAN1_BA+0x104) /*!< Transmission Request Register 2 */
+    #define REG_CAN1_NDAT1      (CAN1_BA+0x120) /*!< New Data Register 1 */
+    #define REG_CAN1_NDAT2      (CAN1_BA+0x124) /*!< New Data Register 2 */
+    #define REG_CAN1_IPND1      (CAN1_BA+0x140) /*!< Interrupt Pending Register 1 */
+    #define REG_CAN1_IPND2      (CAN1_BA+0x142) /*!< Interrupt Pending Register 2 */
+    #define REG_CAN1_MVLD1      (CAN1_BA+0x160) /*!< Message Valid Register 1 */
+    #define REG_CAN1_MVLD2      (CAN1_BA+0x164) /*!< Message Valid Register 2 */
+    #define REG_CAN1_WU_EN      (CAN1_BA+0x168) /*!< Wake-up Function Enable */
+    #define REG_CAN1_WU_STATUS  (CAN1_BA+0x16C) /*!< Wake-up Function Status */
+
+    /**@}*/ /* end of CAN register group */
+
+
+    /*------------------- Multi-Time Programmable Controller --------------------*/
+    /**
+    @addtogroup MTP Multi-Time Programmable Controller (MTP)
+    Memory Mapped Structure for MTP Controller
+    @{ */
+
+    #define     MTP_KEYEN           (MTP_BA+0x000)   /*!< MTP Key Enable Register                       */
+    #define     MTP_USERDATA        (MTP_BA+0x00C)   /*!< MTP User Defined Data Register                */
+    #define     MTP_KEY0            (MTP_BA+0x010)   /*!< MTP KEY 0 Register                            */
+    #define     MTP_KEY1            (MTP_BA+0x014)   /*!< MTP KEY 1 Register                            */
+    #define     MTP_KEY2            (MTP_BA+0x018)   /*!< MTP KEY 2 Register                            */
+    #define     MTP_KEY3            (MTP_BA+0x01C)   /*!< MTP KEY 3 Register                            */
+    #define     MTP_KEY4            (MTP_BA+0x020)   /*!< MTP KEY 4 Register                            */
+    #define     MTP_KEY5            (MTP_BA+0x024)   /*!< MTP KEY 5 Register                            */
+    #define     MTP_KEY6            (MTP_BA+0x028)   /*!< MTP KEY 6 Register                            */
+    #define     MTP_KEY7            (MTP_BA+0x02C)   /*!< MTP KEY 7 Register                            */
+    #define     MTP_PCYCLE          (MTP_BA+0x030)   /*!< MTP Program Cycle Program Count Register      */
+    #define     MTP_CTL             (MTP_BA+0x034)   /*!< MTP Control Register                          */
+    #define     MTP_PSTART          (MTP_BA+0x038)   /*!< MTP Program Start Registe                     */
+    #define     MTP_STATUS          (MTP_BA+0x040)   /*!< MTP Status Registe                            */
+    #define     MTP_REGLCTL         (MTP_BA+0x050)   /*!< MTP Register Write-Protection Control Register*/
+
+    /**@}*/ /* end of MTP register group */
+
+
+    /*------------------- JPEG Controller --------------------*/
+    /**
+    @addtogroup JPEG JPEG Controller (JPEG)
+    Memory Mapped Structure for JPEG Controller
+    @{ */
+    #define JMCR           (JPEG_BA+0x00)           /*!< JPEG Mode Control Register  */
+    #define JHEADER        (JPEG_BA+0x04)           /*!< JPEG Encode Header Control Register  */
+    #define JITCR          (JPEG_BA+0x08)           /*!< JPEG Image Type Control Register  */
+    #define JPRIQC         (JPEG_BA+0x10)           /*!< JPEG Primary Q-Table Control Register  */
+    #define JTHBQC         (JPEG_BA+0x14)           /*!< JPEG Thumbnail Q-Table Control Register  */
+    #define JPRIWH         (JPEG_BA+0x18)           /*!< JPEG Encode Primary Width/Height Register  */
+    #define JTHBWH         (JPEG_BA+0x1C)           /*!< JPEG Encode Thumbnail Width/Height Register  */
+    #define JPRST          (JPEG_BA+0x20)           /*!< JPEG Encode Primary Restart Interval Register  */
+    #define JTRST          (JPEG_BA+0x24)           /*!< JPEG Encode Thumbnail Restart Interval  */
+    #define JDECWH         (JPEG_BA+0x28)           /*!< JPEG Decode Image Width/Height Register  */
+    #define JINTCR         (JPEG_BA+0x2C)           /*!< JPEG Interrupt Control and Status Register  */
+    #define JDOWFBS        (JPEG_BA+0x3c)           /*!< JPEG Decoding Output Wait Frame Buffer Size  */
+    #define JPEG_BSBAD     (JPEG_BA+0x40)           /*!< JPEG Test Control Register  */
+    #define JWINDEC0       (JPEG_BA+0x44)           /*!< JPEG Window Decode Mode Control Register 0  */
+    #define JWINDEC1       (JPEG_BA+0x48)           /*!< JPEG Window Decode Mode Control Register 1  */
+    #define JWINDEC2       (JPEG_BA+0x4C)           /*!< JPEG Window Decode Mode Control Register 2  */
+    #define JMACR          (JPEG_BA+0x50)           /*!< JPEG Memory Address Mode Control Register  */
+    #define JPSCALU        (JPEG_BA+0x54)           /*!< JPEG Primary Scaling-Up Control Register  */
+    #define JPSCALD        (JPEG_BA+0x58)           /*!< JPEG Primary Scaling-Down Control Register  */
+    #define JTSCALD        (JPEG_BA+0x5C)           /*!< JPEG Thumbnail  Scaling-Down Control Register  */
+    #define JDBCR          (JPEG_BA+0x60)           /*!< JPEG Dual-Buffer Control Register  */
+    #define JRESERVE       (JPEG_BA+0x70)           /*!< JPEG Encode Primary Bit-stream Reserved Size Register  */
+    #define JOFFSET        (JPEG_BA+0x74)           /*!< JPEG Offset Between Primary & Thumbnail Register  */
+    #define JFSTRIDE       (JPEG_BA+0x78)           /*!< JPEG Encode Bit-stream Frame Stride Register  */
+    #define JYADDR0        (JPEG_BA+0x7C)           /*!< JPEG Y Component Frame Buffer-0 Starting Address Register  */
+    #define JUADDR0        (JPEG_BA+0x80)           /*!< JPEG U Component Frame Buffer-0 Starting Address Register  */
+    #define JVADDR0        (JPEG_BA+0x84)           /*!< JPEG V Component Frame Buffer-0 Starting Address Register  */
+    #define JYADDR1        (JPEG_BA+0x88)           /*!< JPEG Y Component Frame Buffer-1 Starting Address Register  */
+    #define JUADDR1        (JPEG_BA+0x8C)           /*!< JPEG U Component Frame Buffer-1 Starting Address Register  */
+    #define JVADDR1        (JPEG_BA+0x90)           /*!< JPEG V Component Frame Buffer-1 Starting Address Register  */
+    #define JYSTRIDE       (JPEG_BA+0x94)           /*!< JPEG Y Component Frame Buffer Stride Register  */
+    #define JUSTRIDE       (JPEG_BA+0x98)           /*!< JPEG U Component Frame Buffer Stride Register  */
+    #define JVSTRIDE       (JPEG_BA+0x9C)           /*!< JPEG V Component Frame Buffer Stride Register  */
+    #define JIOADDR0       (JPEG_BA+0xA0)           /*!< JPEG Bit-stream Frame Buffer-0 Starting Address Register  */
+    #define JIOADDR1       (JPEG_BA+0xA4)           /*!< JPEG Bit-stream Frame Buffer-1 Starting Address Register  */
+    #define JPRI_SIZE      (JPEG_BA+0xA8)           /*!< JPEG Encode Primary Image Bit-stream Size Register  */
+    #define JTHB_SIZE      (JPEG_BA+0xAC)           /*!< JPEG Encode Thumbnail Image Bit-stream Size Register  */
+    #define JUPRAT         (JPEG_BA+0xB0)           /*!< JPEG Encode Up-Scale Ratio Register  */
+    #define JBSFIFO        (JPEG_BA+0xB4)           /*!< JPEG Bit-stream FIFO Control Register  */
+    #define JSRCH          (JPEG_BA+0xB8)           /*!< JPEG Encode Source Image Height  */
+    #define JQTAB0         (JPEG_BA+0x100)          /*!< JPEG Quantization-Table 0 Register  */
+    #define JQTAB1         (JPEG_BA+0x140)          /*!< JPEG Quantization-Table 1 Register  */
+    #define JQTAB2         (JPEG_BA+0x180)          /*!< JPEG Quantization-Table 2 Register  */
+
+    /**@}*/ /* end of JPEG register group */
+
+
+
+    /*@}*/ /* end of group N9H30_Peripherals */
+
+
+    /** @addtogroup N9H30_IO_ROUTINE N9H30 I/O Routines
+    The Declaration of N9H30 I/O Routines
+    @{
+    */
+
+    typedef volatile unsigned char  vu8;        ///< Define 8-bit unsigned volatile data type
+    typedef volatile unsigned short vu16;       ///< Define 16-bit unsigned volatile data type
+    typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile data type
+
+    /**
+    * @brief Get a 8-bit unsigned value from specified address
+    * @param[in] addr Address to get 8-bit data from
+    * @return  8-bit unsigned value stored in specified address
+    */
+    #define M8(addr)  (*((vu8  *) (addr)))
+
+    /**
+    * @brief Get a 16-bit unsigned value from specified address
+    * @param[in] addr Address to get 16-bit data from
+    * @return  16-bit unsigned value stored in specified address
+    * @note The input address must be 16-bit aligned
+    */
+    #define M16(addr) (*((vu16 *) (addr)))
+
+    /**
+    * @brief Get a 32-bit unsigned value from specified address
+    * @param[in] addr Address to get 32-bit data from
+    * @return  32-bit unsigned value stored in specified address
+    * @note The input address must be 32-bit aligned
+    */
+    #define M32(addr) (*((vu32 *) (addr)))
+
+    /**
+    * @brief Set a 32-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 32-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    * @note The output port must be 32-bit aligned
+    */
+    #define outpw(port,value)     *((volatile unsigned int *)(port)) = value
+
+    /**
+    * @brief Get a 32-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 32-bit data from
+    * @return  32-bit unsigned value stored in specified I/O port
+    * @note The input port must be 32-bit aligned
+    */
+    #define inpw(port)            (*((volatile unsigned int *)(port)))
+
+    /**
+    * @brief Set a 16-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 16-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    * @note The output port must be 16-bit aligned
+    */
+    #define outps(port,value)     *((volatile unsigned short *)(port)) = value
+
+    /**
+    * @brief Get a 16-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 16-bit data from
+    * @return  16-bit unsigned value stored in specified I/O port
+    * @note The input port must be 16-bit aligned
+    */
+    #define inps(port)            (*((volatile unsigned short *)(port)))
+
+    /**
+    * @brief Set a 8-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 8-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    */
+    #define outpb(port,value)     *((volatile unsigned char *)(port)) = value
+
+    /**
+    * @brief Get a 8-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 8-bit data from
+    * @return  8-bit unsigned value stored in specified I/O port
+    */
+    #define inpb(port)            (*((volatile unsigned char *)(port)))
+
+    /**
+    * @brief Set a 32-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 32-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    * @note The output port must be 32-bit aligned
+    */
+    #define outp32(port,value)    *((volatile unsigned int *)(port)) = value
+
+    /**
+    * @brief Get a 32-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 32-bit data from
+    * @return  32-bit unsigned value stored in specified I/O port
+    * @note The input port must be 32-bit aligned
+    */
+    #define inp32(port)           (*((volatile unsigned int *)(port)))
+
+    /**
+    * @brief Set a 16-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 16-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    * @note The output port must be 16-bit aligned
+    */
+    #define outp16(port,value)    *((volatile unsigned short *)(port)) = value
+
+    /**
+    * @brief Get a 16-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 16-bit data from
+    * @return  16-bit unsigned value stored in specified I/O port
+    * @note The input port must be 16-bit aligned
+    */
+    #define inp16(port)           (*((volatile unsigned short *)(port)))
+
+    /**
+    * @brief Set a 8-bit unsigned value to specified I/O port
+    * @param[in] port Port address to set 8-bit data
+    * @param[in] value Value to write to I/O port
+    * @return  None
+    */
+    #define outp8(port,value)     *((volatile unsigned char *)(port)) = value
+
+    /**
+    * @brief Get a 8-bit unsigned value from specified I/O port
+    * @param[in] port Port address to get 8-bit data from
+    * @return  8-bit unsigned value stored in specified I/O port
+    */
+    #define inp8(port)            (*((volatile unsigned char *)(port)))
+
+
+    /*@}*/ /* end of group N9H30_IO_ROUTINE */
+
+    /******************************************************************************/
+    /*                Legacy Constants                                            */
+    /******************************************************************************/
+    /** @addtogroup N9H30_legacy_Constants N9H30 Legacy Constants
+    N9H30 Legacy Constants
+    @{
+    */
+    typedef void             *PVOID;    ///< Define void pointer data type
+    typedef void              VOID;     ///< Define void data type
+    typedef char              BOOL;     ///< Define bool data type
+    typedef char             *PBOOL;    ///< Define bool pointer data type
+
+    typedef char              INT8;     ///< Define 8-bit singed data type
+    typedef char              CHAR;     ///< Define char data type
+    typedef char             *PINT8;    ///< Define 8-bit singed pointer data type
+    typedef char             *PCHAR;    ///< Define char pointer data type
+    typedef unsigned char     UINT8;    ///< Define 8-bit unsigned data type
+    typedef unsigned char     UCHAR;    ///< Define char unsigned data type
+    typedef unsigned char    *PUINT8;   ///< Define 8-bit unsigned pointer data type
+    typedef unsigned char    *PUCHAR;   ///< Define char unsigned pointer data type
+    typedef char             *PSTR;     ///< Define string pointer data type
+    typedef const char       *PCSTR;    ///< Define constant string pointer data type
+
+    typedef short             SHORT;    ///< Define short signed data type
+    typedef short            *PSHORT;   ///< Define short signed pointer data type
+    typedef unsigned short    USHORT;   ///< Define short unsigned data type
+    typedef unsigned short   *PUSHORT;  ///< Define short unsigned pointer data type
+
+    typedef short             INT16;    ///< Define 16-bit signed data type
+    typedef short            *PINT16;   ///< Define 16-bit signed pointer data type
+    typedef unsigned short    UINT16;   ///< Define 16-bit unsigned data type
+    typedef unsigned short   *PUINT16;  ///< Define 16-bit unsigned pointer data type
+
+    typedef int               INT;      ///< Define integer signed data type
+    typedef int              *PINT;     ///< Define integer signed pointer data type
+    typedef unsigned int      UINT;     ///< Define integer unsigned data type
+    typedef unsigned int     *PUINT;    ///< Define integer unsigned pointer data type
+
+    typedef int               INT32;    ///< Define 32-bit signed data type
+    typedef int              *PINT32;   ///< Define 32-bit signed pointer data type
+    typedef unsigned int      UINT32;   ///< Define 32-bit unsigned data type
+    typedef unsigned int     *PUINT32;  ///< Define 32-bit unsigned pointer data type
+
+    #if defined ( __GNUC__ ) && !(__CC_ARM)
+        typedef long long           INT64;
+        typedef unsigned long long  UINT64;
+    #else
+        typedef __int64           INT64;    ///< Define 64-bit signed data type
+        typedef unsigned __int64  UINT64;   ///< Define 64-bit unsigned data type
+    #endif
+
+    typedef float             FLOAT;    ///< Define float data type
+    typedef float            *PFLOAT;   ///< Define float pointer data type
+
+    typedef double            DOUBLE;   ///< Define double data type
+    typedef double           *PDOUBLE;  ///< Define double pointer data type
+
+    typedef int               SIZE_T;   ///< Define size of data type
+
+    typedef unsigned char     REG8;     ///< Define 8-bit register data type
+    typedef unsigned short    REG16;    ///< Define 16-bit register data type
+    typedef unsigned int      REG32;    ///< Define 32-bit register data type
+
+
+    #ifndef NULL
+        #define NULL           (0)      ///< NULL pointer
+    #endif
+
+    #define TRUE           (1)      ///< Boolean true, define to use in API parameters or return value
+    #define FALSE          (0)      ///< Boolean false, define to use in API parameters or return value
+
+    #define ENABLE         (1)      ///< Enable, define to use in API parameters
+    #define DISABLE        (0)      ///< Disable, define to use in API parameters
+
+
+    #define   Successful  0         ///< Function return value success
+    #define   Fail        1         ///< Function return value failed
+
+    /* Define one bit mask */
+    #define BIT0     (0x00000001)       ///< Bit 0 mask of an 32 bit integer
+    #define BIT1     (0x00000002)       ///< Bit 1 mask of an 32 bit integer
+    #define BIT2     (0x00000004)       ///< Bit 2 mask of an 32 bit integer
+    #define BIT3     (0x00000008)       ///< Bit 3 mask of an 32 bit integer
+    #define BIT4     (0x00000010)       ///< Bit 4 mask of an 32 bit integer
+    #define BIT5     (0x00000020)       ///< Bit 5 mask of an 32 bit integer
+    #define BIT6     (0x00000040)       ///< Bit 6 mask of an 32 bit integer
+    #define BIT7     (0x00000080)       ///< Bit 7 mask of an 32 bit integer
+    #define BIT8     (0x00000100)       ///< Bit 8 mask of an 32 bit integer
+    #define BIT9     (0x00000200)       ///< Bit 9 mask of an 32 bit integer
+    #define BIT10    (0x00000400)       ///< Bit 10 mask of an 32 bit integer
+    #define BIT11    (0x00000800)       ///< Bit 11 mask of an 32 bit integer
+    #define BIT12    (0x00001000)       ///< Bit 12 mask of an 32 bit integer
+    #define BIT13    (0x00002000)       ///< Bit 13 mask of an 32 bit integer
+    #define BIT14    (0x00004000)       ///< Bit 14 mask of an 32 bit integer
+    #define BIT15    (0x00008000)       ///< Bit 15 mask of an 32 bit integer
+    #define BIT16    (0x00010000)       ///< Bit 16 mask of an 32 bit integer
+    #define BIT17    (0x00020000)       ///< Bit 17 mask of an 32 bit integer
+    #define BIT18    (0x00040000)       ///< Bit 18 mask of an 32 bit integer
+    #define BIT19    (0x00080000)       ///< Bit 19 mask of an 32 bit integer
+    #define BIT20    (0x00100000)       ///< Bit 20 mask of an 32 bit integer
+    #define BIT21    (0x00200000)       ///< Bit 21 mask of an 32 bit integer
+    #define BIT22    (0x00400000)       ///< Bit 22 mask of an 32 bit integer
+    #define BIT23    (0x00800000)       ///< Bit 23 mask of an 32 bit integer
+    #define BIT24    (0x01000000)       ///< Bit 24 mask of an 32 bit integer
+    #define BIT25    (0x02000000)       ///< Bit 25 mask of an 32 bit integer
+    #define BIT26    (0x04000000)       ///< Bit 26 mask of an 32 bit integer
+    #define BIT27    (0x08000000)       ///< Bit 27 mask of an 32 bit integer
+    #define BIT28    (0x10000000)       ///< Bit 28 mask of an 32 bit integer
+    #define BIT29    (0x20000000)       ///< Bit 29 mask of an 32 bit integer
+    #define BIT30    (0x40000000)       ///< Bit 30 mask of an 32 bit integer
+    #define BIT31    (0x80000000)       ///< Bit 31 mask of an 32 bit integer
+
+    /* Byte Mask Definitions */
+    #define BYTE0_Msk              (0x000000FF)         ///< Mask to get bit0~bit7 from a 32 bit integer
+    #define BYTE1_Msk              (0x0000FF00)         ///< Mask to get bit8~bit15 from a 32 bit integer
+    #define BYTE2_Msk              (0x00FF0000)         ///< Mask to get bit16~bit23 from a 32 bit integer
+    #define BYTE3_Msk              (0xFF000000)         ///< Mask to get bit24~bit31 from a 32 bit integer
+
+    #define GET_BYTE0(u32Param)    ((u32Param & BYTE0_Msk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
+    #define GET_BYTE1(u32Param)    ((u32Param & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
+    #define GET_BYTE2(u32Param)    ((u32Param & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+    #define GET_BYTE3(u32Param)    ((u32Param & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+    #ifdef __cplusplus
+        #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+    #else
+        #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+    #endif
+    #define     __O     volatile             /*!< Defines 'write only' permissions                */
+    #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+    extern void __nop(void);
+
+#endif /* __N9H30_H__ */
+
+/*@}*/ /* end of group N9H30_legacy_Constants */

bsp/nuvoton/libraries/n9h30/Driver/Include/NuMicro.h

@@ -0,0 +1,51 @@
+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "N9H30.h"
+#include "nu_adc.h"
+#include "nu_uart.h"
+#include "nu_spi.h"
+#include "nu_i2c.h"
+#include "nu_etimer.h"
+#include "nu_emac.h"
+#include "nu_sdh.h"
+#include "nu_gpio.h"
+#include "nu_rtc.h"
+#include "nu_wdt.h"
+//#include "nu_ebi.h"
+#include "nu_scuart.h"
+#include "nu_pwm.h"
+//#include "nu_crypto.h"
+#include "nu_can.h"
+#include "nu_i2s.h"
+#include "nu_usbd.h"
+#include "nu_lcd.h"
+#include "nu_jpegcodec.h"
+#include "nu_2d.h"
+#include "nu_crypto.h"
+
+#include "nu_sys.h"
+
+#ifndef __STATIC_INLINE
+    #define __STATIC_INLINE  static __inline
+#endif
+
+#ifndef __CLZ
+    #if defined(__CC_ARM)
+        #define __CLZ  __clz
+    #else
+        #define __CLZ  __builtin_clz
+    #endif
+#endif
+
+#endif  /* __NUMICRO_H__ */
+
+

bsp/nuvoton/libraries/n9h30/Driver/Include/emac_reg.h

@@ -0,0 +1,2063 @@
+/**************************************************************************//**
+ * @file     emac_reg.h
+ * @version  V1.00
+ * @brief    EMAC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EMAC_REG_H__
+#define __EMAC_REG_H__
+
+#if defined ( __CC_ARM   )
+    #pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup EMAC Ethernet MAC Controller(EMAC)
+    Memory Mapped Structure for EMAC Controller
+@{ */
+
+typedef struct
+{
+
+    /**
+     * @var EMAC_T::CAMCTL
+     * Offset: 0x00  CAM Comparison Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AUP       |Accept Unicast Packet
+     * |        |          |The AUP controls the unicast packet reception
+     * |        |          |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all unicast packets.
+     * |[1]     |AMP       |Accept Multicast Packet
+     * |        |          |The AMP controls the multicast packet reception
+     * |        |          |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all multicast packets.
+     * |[2]     |ABP       |Accept Broadcast Packet
+     * |        |          |The ABP controls the broadcast packet reception
+     * |        |          |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all broadcast packets.
+     * |[3]     |COMPEN    |Complement CAM Comparison Enable Bit
+     * |        |          |The COMPEN controls the complement of the CAM comparison result
+     * |        |          |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
+     * |        |          |configured in CAM entry will be dropped
+     * |        |          |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
+     * |        |          |0 = Complement CAM comparison result Disabled.
+     * |        |          |1 = Complement CAM comparison result Enabled.
+     * |[4]     |CMPEN     |CAM Compare Enable Bit
+     * |        |          |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
+     * |        |          |If software wants to receive a packet with specific destination MAC address, configures the MAC address
+     * |        |          |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
+     * |        |          |0 = CAM comparison function for destination MAC address recognition Disabled.
+     * |        |          |1 = CAM comparison function for destination MAC address recognition Enabled.
+     * @var EMAC_T::CAMEN
+     * Offset: 0x04  CAM Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAMxEN    |CAM Entry X Enable Bit
+     * |        |          |The CAMxEN controls the validation of CAM entry x.
+     * |        |          |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
+     * |        |          |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
+     * |        |          |entries all must be enabled first.
+     * |        |          |0 = CAM entry x Disabled.
+     * |        |          |1 = CAM entry x Enabled.
+     * @var EMAC_T::CAM0M
+     * Offset: 0x08  CAM0 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM0L
+     * Offset: 0x0C  CAM0 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM1M
+     * Offset: 0x10  CAM1 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM1L
+     * Offset: 0x14  CAM1 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM2M
+     * Offset: 0x18  CAM2 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM2L
+     * Offset: 0x1C  CAM2 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM3M
+     * Offset: 0x20  CAM3 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM3L
+     * Offset: 0x24  CAM3 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM4M
+     * Offset: 0x28  CAM4 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM4L
+     * Offset: 0x2C  CAM4 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM5M
+     * Offset: 0x30  CAM5 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM5L
+     * Offset: 0x34  CAM5 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM6M
+     * Offset: 0x38  CAM6 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM6L
+     * Offset: 0x3C  CAM6 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM7M
+     * Offset: 0x40  CAM7 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM7L
+     * Offset: 0x44  CAM7 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM8M
+     * Offset: 0x48  CAM8 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM8L
+     * Offset: 0x4C  CAM8 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM9M
+     * Offset: 0x50  CAM9 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM9L
+     * Offset: 0x54  CAM9 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM10M
+     * Offset: 0x58  CAM10 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM10L
+     * Offset: 0x5C  CAM10 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM11M
+     * Offset: 0x60  CAM11 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM11L
+     * Offset: 0x64  CAM11 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM12M
+     * Offset: 0x68  CAM12 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM12L
+     * Offset: 0x6C  CAM12 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM13M
+     * Offset: 0x70  CAM13 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM13L
+     * Offset: 0x74  CAM13 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM14M
+     * Offset: 0x78  CAM14 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM14L
+     * Offset: 0x7C  CAM14 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM15MSB
+     * Offset: 0x80  CAM15 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |OPCODE    |OP Code Field of PAUSE Control Frame
+     * |        |          |In the PAUSE control frame, an op code field defined and is 0x0001.
+     * |[31:16] |LENGTH    |LENGTH Field of PAUSE Control Frame
+     * |        |          |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
+     * @var EMAC_T::CAM15LSB
+     * Offset: 0x84  CAM15 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:24] |OPERAND   |Pause Parameter
+     * |        |          |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
+     * |        |          |Ethernet MAC Controller paused
+     * |        |          |The unit of the OPERAND is a slot time, the 512-bit time.
+     * @var EMAC_T::TXDSA
+     * Offset: 0x88  Transmit Descriptor Link List Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXDSA     |Transmit Descriptor Link-list Start Address
+     * |        |          |The TXDSA keeps the start address of transmit descriptor link-list
+     * |        |          |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
+     * |        |          |current transmit descriptor start address register (EMAC_CTXDSA)
+     * |        |          |The TXDSA does not be updated by EMAC
+     * |        |          |During the operation, EMAC will ignore the bits [1:0] of TXDSA
+     * |        |          |This means that TX descriptors must locate at word boundary memory address.
+     * @var EMAC_T::RXDSA
+     * Offset: 0x8C  Receive Descriptor Link List Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXDSA     |Receive Descriptor Link-list Start Address
+     * |        |          |The RXDSA keeps the start address of receive descriptor link-list
+     * |        |          |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
+     * |        |          |receive descriptor start address register (EMAC_CRXDSA)
+     * |        |          |The RXDSA does not be updated by EMAC
+     * |        |          |During the operation, EMAC will ignore the bits [1:0] of RXDSA
+     * |        |          |This means that RX descriptors must locate at word boundary memory address.
+     * @var EMAC_T::CTL
+     * Offset: 0x90  MAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXON      |Frame Reception ON
+     * |        |          |The RXON controls the normal packet reception of EMAC
+     * |        |          |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
+     * |        |          |descriptor fetching, packet reception and RX descriptor modification.
+     * |        |          |It is necessary to finish EMAC initial sequence before enable RXON
+     * |        |          |Otherwise, the EMAC operation is undefined.
+     * |        |          |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
+     * |        |          |reception process after the current packet reception finished.
+     * |        |          |0 = Packet reception process stopped.
+     * |        |          |1 = Packet reception process started.
+     * |[1]     |ALP       |Accept Long Packet
+     * |        |          |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
+     * |        |          |If the ALP is set to high, the EMAC will accept the long packet.
+     * |        |          |Otherwise, the long packet will be dropped.
+     * |        |          |0 = Ethernet MAC controller dropped the long packet.
+     * |        |          |1 = Ethernet MAC controller received the long packet.
+     * |[2]     |ARP       |Accept Runt Packet
+     * |        |          |The ARP controls the runt packet, which length is less than 64 bytes, reception
+     * |        |          |If the ARP is set to high, the EMAC will accept the runt packet.
+     * |        |          |Otherwise, the runt packet will be dropped.
+     * |        |          |0 = Ethernet MAC controller dropped the runt packet.
+     * |        |          |1 = Ethernet MAC controller received the runt packet.
+     * |[3]     |ACP       |Accept Control Packet
+     * |        |          |The ACP controls the control frame reception
+     * |        |          |If the ACP is set to high, the EMAC will accept the control frame
+     * |        |          |Otherwise, the control frame will be dropped
+     * |        |          |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
+     * |        |          |0 = Ethernet MAC controller dropped the control frame.
+     * |        |          |1 = Ethernet MAC controller received the control frame.
+     * |[4]     |AEP       |Accept CRC Error Packet
+     * |        |          |The AEP controls the EMAC accepts or drops the CRC error packet
+     * |        |          |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
+     * |        |          |0 = Ethernet MAC controller dropped the CRC error packet.
+     * |        |          |1 = Ethernet MAC controller received the CRC error packet.
+     * |[5]     |STRIPCRC  |Strip CRC Checksum
+     * |        |          |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
+     * |        |          |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
+     * |        |          |0 = The 4 bytes CRC checksum is included in packet length calculation.
+     * |        |          |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
+     * |[6]     |WOLEN     |Wake on LAN Enable Bit
+     * |        |          |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
+     * |        |          |is Magic Packet and wakeup system from Power-down mode.
+     * |        |          |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
+     * |        |          |would generate a wakeup event to wake system up from Power-down mode.
+     * |        |          |0 = Wake-up by Magic Packet function Disabled.
+     * |        |          |1 = Wake-up by Magic Packet function Enabled.
+     * |[8]     |TXON      |Frame Transmission ON
+     * |        |          |The TXON controls the normal packet transmission of EMAC
+     * |        |          |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
+     * |        |          |descriptor fetching, packet transmission and TX descriptor modification.
+     * |        |          |It is must to finish EMAC initial sequence before enable TXON
+     * |        |          |Otherwise, the EMAC operation is undefined.
+     * |        |          |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
+     * |        |          |transmission process after the current packet transmission finished.
+     * |        |          |0 = Packet transmission process stopped.
+     * |        |          |1 = Packet transmission process started.
+     * |[9]     |NODEF     |No Deferral
+     * |        |          |The NODEF controls the enable of deferral exceed counter
+     * |        |          |If NODEF is set to high, the deferral exceed counter is disabled
+     * |        |          |The NODEF is only useful while EMAC is operating on half duplex mode.
+     * |        |          |0 = The deferral exceed counter Enabled.
+     * |        |          |1 = The deferral exceed counter Disabled.
+     * |[16]    |SDPZ      |Send PAUSE Frame
+     * |        |          |The SDPZ controls the PAUSE control frame transmission.
+     * |        |          |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
+     * |        |          |first and the corresponding CAM enable bit of CAMEN register also must be set.
+     * |        |          |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
+     * |        |          |The SDPZ is a self-clear bit
+     * |        |          |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
+     * |        |          |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
+     * |        |          |0 = PAUSE control frame transmission completed.
+     * |        |          |1 = PAUSE control frame transmission Enabled.
+     * |[17]    |SQECHKEN  |SQE Checking Enable Bit
+     * |        |          |The SQECHKEN controls the enable of SQE checking
+     * |        |          |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
+     * |        |          |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
+     * |        |          |or full duplex mode.
+     * |        |          |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
+     * |        |          |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
+     * |[18]    |FUDUP     |Full Duplex Mode Selection
+     * |        |          |The FUDUP controls that if EMAC is operating on full or half duplex mode.
+     * |        |          |0 = EMAC operates in half duplex mode.
+     * |        |          |1 = EMAC operates in full duplex mode.
+     * |[19]    |RMIIRXCTL |RMII RX Control
+     * |        |          |The RMIIRXCTL control the receive data sample in RMII mode
+     * |        |          |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
+     * |        |          |0 = RMII RX control disabled.
+     * |        |          |1 = RMII RX control enabled.
+     * |[20]    |OPMODE    |Operation Mode Selection
+     * |        |          |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
+     * |        |          |The RST (EMAC_CTL[24]) would not affect OPMODE value.
+     * |        |          |0 = EMAC operates in 10Mbps mode.
+     * |        |          |1 = EMAC operates in 100Mbps mode.
+     * |[22]    |RMIIEN    |RMII Mode Enable Bit
+     * |        |          |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
+     * |        |          |interface or RMII interface
+     * |        |          |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
+     * |        |          |0 = Ethernet MAC controller RMII mode Disabled.
+     * |        |          |1 = Ethernet MAC controller RMII mode Enabled.
+     * |        |          |NOTE: This field must keep 1.
+     * |[24]    |RST       |Software Reset
+     * |        |          |The RST implements a reset function to make the EMAC return default state
+     * |        |          |The RST is a self-clear bit
+     * |        |          |This means after the software reset finished, the RST will be cleared automatically
+     * |        |          |Enable RST can also reset all control and status registers, exclusive of the control bits
+     * |        |          |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
+     * |        |          |The EMAC re-initial is necessary after the software reset completed.
+     * |        |          |0 = Software reset completed.
+     * |        |          |1 = Software reset Enabled.
+     * @var EMAC_T::MIIMDAT
+     * Offset: 0x94  MII Management Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DATA      |MII Management Data
+     * |        |          |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
+     * |        |          |Management write command or the data from the registers of external PHY for MII Management read command.
+     * @var EMAC_T::MIIMCTL
+     * Offset: 0x98  MII Management Control and Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |PHYREG    |PHY Register Address
+     * |        |          |The PHYREG keeps the address to indicate which register of external PHY is the target of the
+     * |        |          |MII management command.
+     * |[12:8]  |PHYADDR   |PHY Address
+     * |        |          |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
+     * |[16]    |WRITE     |Write Command
+     * |        |          |The Write defines the MII management command is a read or write.
+     * |        |          |0 = MII management command is a read command.
+     * |        |          |1 = MII management command is a write command.
+     * |[17]    |BUSY      |Busy Bit
+     * |        |          |The BUSY controls the enable of the MII management frame generation
+     * |        |          |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
+     * |        |          |the MII management frame to external PHY through MII Management I/F
+     * |        |          |The BUSY is a self-clear bit
+     * |        |          |This means the BUSY will be cleared automatically after the MII management command finished.
+     * |        |          |0 = MII management command generation finished.
+     * |        |          |1 = MII management command generation Enabled.
+     * |[18]    |PREAMSP   |Preamble Suppress
+     * |        |          |The PREAMSP controls the preamble field generation of MII management frame
+     * |        |          |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
+     * |        |          |0 = Preamble field generation of MII management frame not skipped.
+     * |        |          |1 = Preamble field generation of MII management frame skipped.
+     * |[19]    |MDCON     |MDC Clock ON
+     * |        |          |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
+     * |        |          |0 = MDC clock off.
+     * |        |          |1 = MDC clock on.
+     * @var EMAC_T::FIFOCTL
+     * Offset: 0x9C  FIFO Threshold Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RXFIFOTH  |RXFIFO Low Threshold
+     * |        |          |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO
+     * |        |          |and system memory
+     * |        |          |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold
+     * |        |          |The low threshold is the half of high threshold always
+     * |        |          |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
+     * |        |          |transfer frame data from RXFIFO to system memory
+     * |        |          |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
+     * |        |          |data to system memory.
+     * |        |          |00 = Depend on the burst length setting
+     * |        |          |If the burst length is 8 words, high threshold is 8 words, too.
+     * |        |          |01 = RXFIFO high threshold is 64B and low threshold is 32B.
+     * |        |          |10 = RXFIFO high threshold is 128B and low threshold is 64B.
+     * |        |          |11 = RXFIFO high threshold is 192B and low threshold is 96B.
+     * |[9:8]   |TXFIFOTH  |TXFIFO Low Threshold
+     * |        |          |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system
+     * |        |          |memory and TXFIFO
+     * |        |          |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold
+     * |        |          |The high threshold is the twice of low threshold always
+     * |        |          |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
+     * |        |          |generate request to transfer frame data from system memory to TXFIFO
+     * |        |          |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
+     * |        |          |from system memory to TXFIFO.
+     * |        |          |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network
+     * |        |          |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
+     * |        |          |during the transmission of the frame
+     * |        |          |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
+     * |        |          |out after the frame data are all inside the TXFIFO.
+     * |        |          |00 = Undefined.
+     * |        |          |01 = TXFIFO low threshold is 64B and high threshold is 128B.
+     * |        |          |10 = TXFIFO low threshold is 80B and high threshold is 160B.
+     * |        |          |11 = TXFIFO low threshold is 96B and high threshold is 192B.
+     * |[21:20] |BURSTLEN  |DMA Burst Length
+     * |        |          |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
+     * |        |          |00 = 4 words.
+     * |        |          |01 = 8 words.
+     * |        |          |10 = 16 words.
+     * |        |          |11 = 16 words.
+     * @var EMAC_T::TXST
+     * Offset: 0xA0  Transmit Start Demand Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXST      |Transmit Start Demand
+     * |        |          |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
+     * |        |          |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
+     * |        |          |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
+     * |        |          |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
+     * |        |          |The EMAC_TXST is a write only register and read from this register is undefined.
+     * |        |          |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
+     * @var EMAC_T::RXST
+     * Offset: 0xA4  Receive Start Demand Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXST      |Receive Start Demand
+     * |        |          |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
+     * |        |          |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
+     * |        |          |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
+     * |        |          |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
+     * |        |          |The EMAC_RXST is a write only register and read from this register is undefined.
+     * |        |          |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
+     * @var EMAC_T::MRFL
+     * Offset: 0xA8  Maximum Receive Frame Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MRFL      |Maximum Receive Frame Length
+     * |        |          |The MRFL defines the maximum frame length for received frame
+     * |        |          |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8])
+     * |        |          |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
+     * |        |          |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to
+     * |        |          |receive a frame which length is greater than 1518 bytes.
+     * @var EMAC_T::INTEN
+     * Offset: 0xAC  MAC Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXIEN     |Receive Interrupt Enable Bit
+     * |        |          |The RXIEN controls the RX interrupt generation.
+     * |        |          |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU
+     * |        |          |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1]
+     * |        |          |is set and the corresponding bit of EMAC_INTEN is enabled
+     * |        |          |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
+     * |        |          |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
+     * |        |          |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
+     * |        |          |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
+     * |[1]     |CRCEIEN   |CRC Error Interrupt Enable Bit
+     * |        |          |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation
+     * |        |          |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |CRCEIF (EMAC_INTSTS[1]) is set.
+     * |        |          |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
+     * |        |          |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
+     * |[2]     |RXOVIEN   |Receive FIFO Overflow Interrupt Enable Bit
+     * |        |          |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation
+     * |        |          |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXOVIF (EMAC_INTSTS[2]) is set.
+     * |        |          |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
+     * |[3]     |LPIEN     |Long Packet Interrupt Enable Bit
+     * |        |          |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation
+     * |        |          |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+     * |        |          |generates the RX interrupt to CPU
+     * |        |          |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
+     * |        |          |(EMAC_INTSTS[3]) is set.
+     * |        |          |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
+     * |        |          |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
+     * |[4]     |RXGDIEN   |Receive Good Interrupt Enable Bit
+     * |        |          |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation
+     * |        |          |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXGDIF (EMAC_INTSTS[4]) is set.
+     * |        |          |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
+     * |[5]     |ALIEIEN   |Alignment Error Interrupt Enable Bit
+     * |        |          |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation
+     * |        |          |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |ALIEIF (EMAC_INTSTS[5]) is set.
+     * |        |          |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
+     * |        |          |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
+     * |[6]     |RPIEN     |Runt Packet Interrupt Enable Bit
+     * |        |          |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation
+     * |        |          |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+     * |        |          |generates the RX interrupt to CPU
+     * |        |          |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RPIF (EMAC_INTSTS[6]) is set.
+     * |        |          |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
+     * |        |          |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
+     * |[7]     |MPCOVIEN  |Miss Packet Counter Overrun Interrupt Enable Bit
+     * |        |          |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation
+     * |        |          |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+     * |        |          |the EMAC generates the RX interrupt to CPU
+     * |        |          |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |MPCOVIF (EMAC_INTSTS[7]) is set.
+     * |        |          |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
+     * |        |          |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
+     * |[8]     |MFLEIEN   |Maximum Frame Length Exceed Interrupt Enable Bit
+     * |        |          |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation
+     * |        |          |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |MFLEIF (EMAC_INTSTS[8]) is set.
+     * |        |          |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
+     * |        |          |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
+     * |[9]     |DENIEN    |DMA Early Notification Interrupt Enable Bit
+     * |        |          |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation
+     * |        |          |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |DENIF (EMAC_INTSTS[9]) is set.
+     * |        |          |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
+     * |        |          |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
+     * |[10]    |RDUIEN    |Receive Descriptor Unavailable Interrupt Enable Bit
+     * |        |          |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation
+     * |        |          |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RDUIF (EMAC_MIOSTA[10]) register is set.
+     * |        |          |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
+     * |        |          |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
+     * |[11]    |RXBEIEN   |Receive Bus Error Interrupt Enable Bit
+     * |        |          |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation
+     * |        |          |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXBEIF (EMAC_INTSTS[11]) is set.
+     * |        |          |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
+     * |[14]    |CFRIEN    |Control Frame Receive Interrupt Enable Bit
+     * |        |          |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation
+     * |        |          |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |CFRIF (EMAC_INTSTS[14]) register is set.
+     * |        |          |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
+     * |        |          |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
+     * |[15]    |WOLIEN    |Wake on LAN Interrupt Enable Bit
+     * |        |          |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation
+     * |        |          |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+     * |        |          |the EMAC generates the RX interrupt to CPU
+     * |        |          |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |WOLIF (EMAC_INTSTS[15]) is set.
+     * |        |          |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
+     * |        |          |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
+     * |[16]    |TXIEN     |Transmit Interrupt Enable Bit
+     * |        |          |The TXIEN controls the TX interrupt generation.
+     * |        |          |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU
+     * |        |          |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
+     * |        |          |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled
+     * |        |          |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
+     * |        |          |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
+     * |        |          |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
+     * |        |          |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
+     * |[17]    |TXUDIEN   |Transmit FIFO Underflow Interrupt Enable Bit
+     * |        |          |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation
+     * |        |          |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even
+     * |        |          |the TXUDIF (EMAC_INTSTS[17]) is set.
+     * |        |          |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
+     * |        |          |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
+     * |[18]    |TXCPIEN   |Transmit Completion Interrupt Enable Bit
+     * |        |          |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation
+     * |        |          |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXCPIF (EMAC_INTSTS[18]) is set.
+     * |        |          |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
+     * |[19]    |EXDEFIEN  |Defer Exceed Interrupt Enable Bit
+     * |        |          |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation
+     * |        |          |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |EXDEFIF (EMAC_INTSTS[19]) is set.
+     * |        |          |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
+     * |        |          |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
+     * |[20]    |NCSIEN    |No Carrier Sense Interrupt Enable Bit
+     * |        |          |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation
+     * |        |          |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |NCSIF (EMAC_INTSTS[20]) is set.
+     * |        |          |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
+     * |        |          |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
+     * |[21]    |TXABTIEN  |Transmit Abort Interrupt Enable Bit
+     * |        |          |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation
+     * |        |          |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXABTIF (EMAC_INTSTS[21]) is set.
+     * |        |          |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
+     * |[22]    |LCIEN     |Late Collision Interrupt Enable Bit
+     * |        |          |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation
+     * |        |          |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |LCIF (EMAC_INTSTS[22]) is set.
+     * |        |          |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
+     * |        |          |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
+     * |[23]    |TDUIEN    |Transmit Descriptor Unavailable Interrupt Enable Bit
+     * |        |          |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation
+     * |        |          |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TDUIF (EMAC_INTSTS[23]) is set.
+     * |        |          |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
+     * |        |          |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
+     * |[24]    |TXBEIEN   |Transmit Bus Error Interrupt Enable Bit
+     * |        |          |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation
+     * |        |          |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXBEIF (EMAC_INTSTS[24]) is set.
+     * |        |          |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
+     * |[28]    |TSALMIEN  |Time Stamp Alarm Interrupt Enable Bit
+     * |        |          |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation
+     * |        |          |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the
+     * |        |          |TXTSALMIF (EMAC_INTEN[28]) is set.
+     * |        |          |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
+     * @var EMAC_T::INTSTS
+     * Offset: 0xB0  MAC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXIF      |Receive Interrupt
+     * |        |          |The RXIF indicates the RX interrupt status.
+     * |        |          |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates
+     * |        |          |the EMAC generates RX interrupt to CPU
+     * |        |          |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
+     * |        |          |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]
+     * |        |          |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in
+     * |        |          |EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
+     * |        |          |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
+     * |        |          |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
+     * |        |          |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in
+     * |        |          |EMAC_INTEN[15:1] is enabled, too.
+     * |[1]     |CRCEIF    |CRC Error Interrupt
+     * |        |          |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
+     * |        |          |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
+     * |        |          |CRCEIF will not be set.
+     * |        |          |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the CRCEIF status.
+     * |        |          |0 = The frame does not incur CRC error.
+     * |        |          |1 = The frame incurred CRC error.
+     * |[2]     |RXOVIF    |Receive FIFO Overflow Interrupt
+     * |        |          |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
+     * |        |          |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
+     * |        |          |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
+     * |        |          |the RXFIFOTH of FFTCR register, to higher level.
+     * |        |          |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXOVIF status.
+     * |        |          |0 = No RXFIFO overflow occurred during packet reception.
+     * |        |          |1 = RXFIFO overflow occurred during packet reception.
+     * |[3]     |LPIF      |Long Packet Interrupt Flag
+     * |        |          |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
+     * |        |          |incoming packet is dropped
+     * |        |          |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
+     * |        |          |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the LPIF status.
+     * |        |          |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
+     * |        |          |1 = The incoming frame is a long frame and dropped.
+     * |[4]     |RXGDIF    |Receive Good Interrupt
+     * |        |          |The RXGDIF high indicates the frame reception has completed.
+     * |        |          |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXGDIF status.
+     * |        |          |0 = The frame reception has not complete yet.
+     * |        |          |1 = The frame reception has completed.
+     * |[5]     |ALIEIF    |Alignment Error Interrupt
+     * |        |          |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
+     * |        |          |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the ALIEIF status.
+     * |        |          |0 = The frame length is a multiple of byte.
+     * |        |          |1 = The frame length is not a multiple of byte.
+     * |[6]     |RPIF      |Runt Packet Interrupt
+     * |        |          |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
+     * |        |          |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
+     * |        |          |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RPIF status.
+     * |        |          |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
+     * |        |          |1 = The incoming frame is a short frame and dropped.
+     * |[7]     |MPCOVIF   |Missed Packet Counter Overrun Interrupt Flag
+     * |        |          |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
+     * |        |          |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the MPCOVIF status.
+     * |        |          |0 = The MPCNT has not rolled over yet.
+     * |        |          |1 = The MPCNT has rolled over yet.
+     * |[8]     |MFLEIF    |Maximum Frame Length Exceed Interrupt Flag
+     * |        |          |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
+     * |        |          |configured in DMARFC register and the incoming packet is dropped
+     * |        |          |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the MFLEIF status.
+     * |        |          |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
+     * |        |          |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
+     * |[9]     |DENIF     |DMA Early Notification Interrupt
+     * |        |          |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
+     * |        |          |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the DENIF status.
+     * |        |          |0 = The LENGTH field of incoming packet has not received yet.
+     * |        |          |1 = The LENGTH field of incoming packet has received.
+     * |[10]    |RDUIF     |Receive Descriptor Unavailable Interrupt
+     * |        |          |The RDUIF high indicates that there is no available RX descriptor for packet reception and
+     * |        |          |RXDMA will stay at Halt state
+     * |        |          |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
+     * |        |          |make RXDMA leave Halt state while new RX descriptor is available.
+     * |        |          |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RDUIF status.
+     * |        |          |0 = RX descriptor is available.
+     * |        |          |1 = RX descriptor is unavailable.
+     * |[11]    |RXBEIF    |Receive Bus Error Interrupt
+     * |        |          |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
+     * |        |          |system memory through RXDMA during packet reception process
+     * |        |          |Reset EMAC is recommended while RXBEIF status is high.
+     * |        |          |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXBEIF status.
+     * |        |          |0 = No ERROR response is received.
+     * |        |          |1 = ERROR response is received.
+     * |[14]    |CFRIF     |Control Frame Receive Interrupt
+     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
+     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
+     * |        |          |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the CFRIF status.
+     * |        |          |0 = The EMAC does not receive the flow control frame.
+     * |        |          |1 = The EMAC receives a flow control frame.
+     * |[15]    |WOLIF     |Wake on LAN Interrupt Flag
+     * |        |          |The WOLIF high indicates EMAC receives a Magic Packet
+     * |        |          |The CFRIF only available while system is in power down mode and WOLEN is set high.
+     * |        |          |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the WOLIF status.
+     * |        |          |0 = The EMAC does not receive the Magic Packet.
+     * |        |          |1 = The EMAC receives a Magic Packet.
+     * |[16]    |TXIF      |Transmit Interrupt
+     * |        |          |The TXIF indicates the TX interrupt status.
+     * |        |          |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates
+     * |        |          |the EMAC generates TX interrupt to CPU
+     * |        |          |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
+     * |        |          |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]
+     * |        |          |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit
+     * |        |          |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high
+     * |        |          |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
+     * |        |          |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
+     * |        |          |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit
+     * |        |          |in EMAC_INTEN[28:17] is enabled, too.
+     * |[17]    |TXUDIF    |Transmit FIFO Underflow Interrupt
+     * |        |          |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
+     * |        |          |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
+     * |        |          |without S/W intervention
+     * |        |          |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
+     * |        |          |the TXFIFOTH of FFTCR register, to higher level.
+     * |        |          |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXUDIF status.
+     * |        |          |0 = No TXFIFO underflow occurred during packet transmission.
+     * |        |          |1 = TXFIFO underflow occurred during packet transmission.
+     * |[18]    |TXCPIF    |Transmit Completion Interrupt
+     * |        |          |The TXCPIF indicates the packet transmission has completed correctly.
+     * |        |          |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXCPIF status.
+     * |        |          |0 = The packet transmission not completed.
+     * |        |          |1 = The packet transmission has completed.
+     * |[19]    |EXDEFIF   |Defer Exceed Interrupt
+     * |        |          |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
+     * |        |          |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
+     * |        |          |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
+     * |        |          |is operating on half-duplex mode.
+     * |        |          |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the EXDEFIF status.
+     * |        |          |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+     * |        |          |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+     * |[20]    |NCSIF     |No Carrier Sense Interrupt
+     * |        |          |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
+     * |        |          |the packet transmission
+     * |        |          |The NCSIF is only available while EMAC is operating on half-duplex mode
+     * |        |          |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the NCSIF status.
+     * |        |          |0 = CRS signal actives correctly.
+     * |        |          |1 = CRS signal does not active at the start of or during the packet transmission.
+     * |[21]    |TXABTIF   |Transmit Abort Interrupt
+     * |        |          |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
+     * |        |          |and then the transmission process for this packet is aborted
+     * |        |          |The transmission abort is only available while EMAC is operating on half-duplex mode.
+     * |        |          |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXABTIF status.
+     * |        |          |0 = Packet does not incur 16 consecutive collisions during transmission.
+     * |        |          |1 = Packet incurred 16 consecutive collisions during transmission.
+     * |[22]    |LCIF      |Late Collision Interrupt
+     * |        |          |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
+     * |        |          |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
+     * |        |          |still occurred.
+     * |        |          |The late collision check will only be done while EMAC is operating on half-duplex mode
+     * |        |          |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the LCIF status.
+     * |        |          |0 = No collision occurred in the outside of 64 bytes collision window.
+     * |        |          |1 = Collision occurred in the outside of 64 bytes collision window.
+     * |[23]    |TDUIF     |Transmit Descriptor Unavailable Interrupt
+     * |        |          |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
+     * |        |          |TXDMA will stay at Halt state.
+     * |        |          |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
+     * |        |          |TXDMA leave Halt state while new TX descriptor is available.
+     * |        |          |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TDUIF status.
+     * |        |          |0 = TX descriptor is available.
+     * |        |          |1 = TX descriptor is unavailable.
+     * |[24]    |TXBEIF    |Transmit Bus Error Interrupt
+     * |        |          |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
+     * |        |          |memory through TXDMA during packet transmission process
+     * |        |          |Reset EMAC is recommended while TXBEIF status is high.
+     * |        |          |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TXBEIF status.
+     * |        |          |0 = No ERROR response is received.
+     * |        |          |1 = ERROR response is received.
+     * |[28]    |TSALMIF   |Time Stamp Alarm Interrupt
+     * |        |          |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
+     * |        |          |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
+     * |        |          |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TSALMIF status.
+     * |        |          |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
+     * |        |          |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
+     * @var EMAC_T::GENSTS
+     * Offset: 0xB4  MAC General Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CFR       |Control Frame Received
+     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
+     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
+     * |        |          |0 = The EMAC does not receive the flow control frame.
+     * |        |          |1 = The EMAC receives a flow control frame.
+     * |[1]     |RXHALT    |Receive Halted
+     * |        |          |The RXHALT high indicates the next normal packet reception process will be halted because
+     * |        |          |the bit RXON of MCMDR is disabled be S/W.
+     * |        |          |0 = Next normal packet reception process will go on.
+     * |        |          |1 = Next normal packet reception process will be halted.
+     * |[2]     |RXFFULL   |RXFIFO Full
+     * |        |          |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
+     * |        |          |and the following incoming packet will be dropped.
+     * |        |          |0 = The RXFIFO is not full.
+     * |        |          |1 = The RXFIFO is full and the following incoming packet will be dropped.
+     * |[7:4]   |COLCNT    |Collision Count
+     * |        |          |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
+     * |        |          |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
+     * |        |          |0 and bit TXABTIF will be set to 1.
+     * |[8]     |DEF       |Deferred Transmission
+     * |        |          |The DEF high indicates the packet transmission has deferred once
+     * |        |          |The DEF is only available while EMAC is operating on half-duplex mode.
+     * |        |          |0 = Packet transmission does not defer.
+     * |        |          |1 = Packet transmission has deferred once.
+     * |[9]     |TXPAUSED  |Transmission Paused
+     * |        |          |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
+     * |        |          |because EMAC received a PAUSE control frame.
+     * |        |          |0 = Next normal packet transmission process will go on.
+     * |        |          |1 = Next normal packet transmission process will be paused.
+     * |[10]    |SQE       |Signal Quality Error
+     * |        |          |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
+     * |        |          |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
+     * |        |          |is operating on 10Mbps half-duplex mode.
+     * |        |          |0 = No SQE error found at end of packet transmission.
+     * |        |          |1 = SQE error found at end of packet transmission.
+     * |[11]    |TXHALT    |Transmission Halted
+     * |        |          |The TXHALT high indicates the next normal packet transmission process will be halted because
+     * |        |          |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
+     * |        |          |0 = Next normal packet transmission process will go on.
+     * |        |          |1 = Next normal packet transmission process will be halted.
+     * |[12]    |RPSTS     |Remote Pause Status
+     * |        |          |The RPSTS indicates that remote pause counter down counting actives.
+     * |        |          |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
+     * |        |          |counter down counting
+     * |        |          |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
+     * |        |          |transmission until the down counting done.
+     * |        |          |0 = Remote pause counter down counting done.
+     * |        |          |1 = Remote pause counter down counting actives.
+     * @var EMAC_T::MPCNT
+     * Offset: 0xB8  Missed Packet Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MPCNT     |Miss Packet Count
+     * |        |          |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
+     * |        |          |The following type of receiving error makes missed packet counter increase:
+     * |        |          |1. Incoming packet is incurred RXFIFO overflow.
+     * |        |          |2. Incoming packet is dropped due to RXON is disabled.
+     * |        |          |3. Incoming packet is incurred CRC error.
+     * @var EMAC_T::RPCNT
+     * Offset: 0xBC  MAC Receive Pause Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RPCNT     |MAC Receive Pause Count
+     * |        |          |The RPCNT keeps the OPERAND field of the PAUSE control frame
+     * |        |          |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
+     * @var EMAC_T::FRSTS
+     * Offset: 0xC8  DMA Receive Frame Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXFLT     |Receive Frame LENGTH
+     * |        |          |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
+     * |        |          |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has
+     * |        |          |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
+     * |        |          |And, the content of LENGTH field will be stored in RXFLT.
+     * @var EMAC_T::CTXDSA
+     * Offset: 0xCC  Current Transmit Descriptor Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CTXDSA    |Current Transmit Descriptor Start Address
+     * |        |          |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
+     * |        |          |The CTXDSA is read only and write to this register has no effect.
+     * @var EMAC_T::CTXBSA
+     * Offset: 0xD0  Current Transmit Buffer Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CTXBSA    |Current Transmit Buffer Start Address
+     * |        |          |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
+     * |        |          |The CTXBSA is read only and write to this register has no effect.
+     * @var EMAC_T::CRXDSA
+     * Offset: 0xD4  Current Receive Descriptor Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CRXDSA    |Current Receive Descriptor Start Address
+     * |        |          |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
+     * |        |          |The CRXDSA is read only and write to this register has no effect.
+     * @var EMAC_T::CRXBSA
+     * Offset: 0xD8  Current Receive Buffer Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CRXBSA    |Current Receive Buffer Start Address
+     * |        |          |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
+     * |        |          |The CRXBSA is read only and write to this register has no effect.
+     * @var EMAC_T::TSCTL
+     * Offset: 0x100  Time Stamp Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TSEN      |Time Stamp Function Enable Bit
+     * |        |          |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
+     * |        |          |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
+     * |        |          |to disable IEEE 1588 PTP time stamp function.
+     * |        |          |0 = I EEE 1588 PTP time stamp function Disabled.
+     * |        |          |1 = IEEE 1588 PTP time stamp function Enabled.
+     * |[1]     |TSIEN     |Time Stamp Counter Initialization Enable Bit
+     * |        |          |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
+     * |        |          |and EMAC_UPDSUBSEC to PTP time stamp counter.
+     * |        |          |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
+     * |        |          |0 = Time stamp counter initialization done.
+     * |        |          |1 = Time stamp counter initialization Enabled.
+     * |[2]     |TSMODE    |Time Stamp Fine Update Enable Bit
+     * |        |          |This bit chooses the time stamp counter update mode.
+     * |        |          |0 = Time stamp counter is in coarse update mode.
+     * |        |          |1 = Time stamp counter is in fine update mode.
+     * |[3]     |TSUPDATE  |Time Stamp Counter Time Update Enable Bit
+     * |        |          |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
+     * |        |          |EMAC_UPDSUBSEC to PTP time stamp counter.
+     * |        |          |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
+     * |        |          |0 = No action.
+     * |        |          |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
+     * |[5]     |TSALMEN   |Time Stamp Alarm Enable Bit
+     * |        |          |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when
+     * |        |          |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * |        |          |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * |        |          |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * @var EMAC_T::TSSEC
+     * Offset: 0x110  Time Stamp Counter Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second
+     * |        |          |This register reflects the bit [63:32] value of 64-bit reference timing counter
+     * |        |          |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+     * @var EMAC_T::TSSUBSEC
+     * Offset: 0x114  Time Stamp Counter Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second
+     * |        |          |This register reflects the bit [31:0] value of 64-bit reference timing counter
+     * |        |          |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+     * @var EMAC_T::TSINC
+     * Offset: 0x118  Time Stamp Increment Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNTINC    |Time Stamp Counter Increment
+     * |        |          |Time stamp counter increment value.
+     * |        |          |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
+     * |        |          |time when it wants to increase the EMAC_TSSUBSEC value.
+     * @var EMAC_T::TSADDEND
+     * Offset: 0x11C  Time Stamp Addend Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ADDEND    |Time Stamp Counter Addend
+     * |        |          |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
+     * |        |          |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
+     * |        |          |with this 32-bit value in each HCLK
+     * |        |          |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
+     * |        |          |value kept in register EMAC_TSINC.
+     * @var EMAC_T::UPDSEC
+     * Offset: 0x120  Time Stamp Update Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second Update
+     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
+     * |        |          |EMAC loads this 32-bit value to EMAC_TSSEC directly
+     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
+     * @var EMAC_T::UPDSUBSEC
+     * Offset: 0x124  Time Stamp Update Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Update
+     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
+     * |        |          |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
+     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
+     * @var EMAC_T::ALMSEC
+     * Offset: 0x128  Time Stamp Alarm Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second Alarm
+     * |        |          |Time stamp counter second part alarm value.
+     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+     * @var EMAC_T::ALMSUBSEC
+     * Offset: 0x12C  Time Stamp Alarm Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Alarm
+     * |        |          |Time stamp counter sub-second part alarm value.
+     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+     */
+    __IO uint32_t CAMCTL;                /*!< [0x0000] CAM Comparison Control Register                                  */
+    __IO uint32_t CAMEN;                 /*!< [0x0004] CAM Enable Register                                              */
+    __IO uint32_t CAM0M;                 /*!< [0x0008] CAM0 Most Significant Word Register                              */
+    __IO uint32_t CAM0L;                 /*!< [0x000c] CAM0 Least Significant Word Register                             */
+    __IO uint32_t CAM1M;                 /*!< [0x0010] CAM1 Most Significant Word Register                              */
+    __IO uint32_t CAM1L;                 /*!< [0x0014] CAM1 Least Significant Word Register                             */
+    __IO uint32_t CAM2M;                 /*!< [0x0018] CAM2 Most Significant Word Register                              */
+    __IO uint32_t CAM2L;                 /*!< [0x001c] CAM2 Least Significant Word Register                             */
+    __IO uint32_t CAM3M;                 /*!< [0x0020] CAM3 Most Significant Word Register                              */
+    __IO uint32_t CAM3L;                 /*!< [0x0024] CAM3 Least Significant Word Register                             */
+    __IO uint32_t CAM4M;                 /*!< [0x0028] CAM4 Most Significant Word Register                              */
+    __IO uint32_t CAM4L;                 /*!< [0x002c] CAM4 Least Significant Word Register                             */
+    __IO uint32_t CAM5M;                 /*!< [0x0030] CAM5 Most Significant Word Register                              */
+    __IO uint32_t CAM5L;                 /*!< [0x0034] CAM5 Least Significant Word Register                             */
+    __IO uint32_t CAM6M;                 /*!< [0x0038] CAM6 Most Significant Word Register                              */
+    __IO uint32_t CAM6L;                 /*!< [0x003c] CAM6 Least Significant Word Register                             */
+    __IO uint32_t CAM7M;                 /*!< [0x0040] CAM7 Most Significant Word Register                              */
+    __IO uint32_t CAM7L;                 /*!< [0x0044] CAM7 Least Significant Word Register                             */
+    __IO uint32_t CAM8M;                 /*!< [0x0048] CAM8 Most Significant Word Register                              */
+    __IO uint32_t CAM8L;                 /*!< [0x004c] CAM8 Least Significant Word Register                             */
+    __IO uint32_t CAM9M;                 /*!< [0x0050] CAM9 Most Significant Word Register                              */
+    __IO uint32_t CAM9L;                 /*!< [0x0054] CAM9 Least Significant Word Register                             */
+    __IO uint32_t CAM10M;                /*!< [0x0058] CAM10 Most Significant Word Register                             */
+    __IO uint32_t CAM10L;                /*!< [0x005c] CAM10 Least Significant Word Register                            */
+    __IO uint32_t CAM11M;                /*!< [0x0060] CAM11 Most Significant Word Register                             */
+    __IO uint32_t CAM11L;                /*!< [0x0064] CAM11 Least Significant Word Register                            */
+    __IO uint32_t CAM12M;                /*!< [0x0068] CAM12 Most Significant Word Register                             */
+    __IO uint32_t CAM12L;                /*!< [0x006c] CAM12 Least Significant Word Register                            */
+    __IO uint32_t CAM13M;                /*!< [0x0070] CAM13 Most Significant Word Register                             */
+    __IO uint32_t CAM13L;                /*!< [0x0074] CAM13 Least Significant Word Register                            */
+    __IO uint32_t CAM14M;                /*!< [0x0078] CAM14 Most Significant Word Register                             */
+    __IO uint32_t CAM14L;                /*!< [0x007c] CAM14 Least Significant Word Register                            */
+    __IO uint32_t CAM15MSB;              /*!< [0x0080] CAM15 Most Significant Word Register                             */
+    __IO uint32_t CAM15LSB;              /*!< [0x0084] CAM15 Least Significant Word Register                            */
+    __IO uint32_t TXDSA;                 /*!< [0x0088] Transmit Descriptor Link List Start Address Register             */
+    __IO uint32_t RXDSA;                 /*!< [0x008c] Receive Descriptor Link List Start Address Register              */
+    __IO uint32_t CTL;                   /*!< [0x0090] MAC Control Register                                             */
+    __IO uint32_t MIIMDAT;               /*!< [0x0094] MII Management Data Register                                     */
+    __IO uint32_t MIIMCTL;               /*!< [0x0098] MII Management Control and Address Register                      */
+    __IO uint32_t FIFOCTL;               /*!< [0x009c] FIFO Threshold Control Register                                  */
+    __O  uint32_t TXST;                  /*!< [0x00a0] Transmit Start Demand Register                                   */
+    __O  uint32_t RXST;                  /*!< [0x00a4] Receive Start Demand Register                                    */
+    __IO uint32_t MRFL;                  /*!< [0x00a8] Maximum Receive Frame Control Register                           */
+    __IO uint32_t INTEN;                 /*!< [0x00ac] MAC Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x00b0] MAC Interrupt Status Register                                    */
+    __IO uint32_t GENSTS;                /*!< [0x00b4] MAC General Status Register                                      */
+    __IO uint32_t MPCNT;                 /*!< [0x00b8] Missed Packet Count Register                                     */
+    __I  uint32_t RPCNT;                 /*!< [0x00bc] MAC Receive Pause Count Register                                 */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[2];
+    /** @endcond */
+    __IO uint32_t FRSTS;                 /*!< [0x00c8] DMA Receive Frame Status Register                                */
+    __I  uint32_t CTXDSA;                /*!< [0x00cc] Current Transmit Descriptor Start Address Register               */
+    __I  uint32_t CTXBSA;                /*!< [0x00d0] Current Transmit Buffer Start Address Register                   */
+    __I  uint32_t CRXDSA;                /*!< [0x00d4] Current Receive Descriptor Start Address Register                */
+    __I  uint32_t CRXBSA;                /*!< [0x00d8] Current Receive Buffer Start Address Register                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE1[9];
+    /** @endcond */
+    __IO uint32_t TSCTL;                 /*!< [0x0100] Time Stamp Control Register                                      */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE2[3];
+    /** @endcond */
+    __I  uint32_t TSSEC;                 /*!< [0x0110] Time Stamp Counter Second Register                               */
+    __I  uint32_t TSSUBSEC;              /*!< [0x0114] Time Stamp Counter Sub Second Register                           */
+    __IO uint32_t TSINC;                 /*!< [0x0118] Time Stamp Increment Register                                    */
+    __IO uint32_t TSADDEND;              /*!< [0x011c] Time Stamp Addend Register                                       */
+    __IO uint32_t UPDSEC;                /*!< [0x0120] Time Stamp Update Second Register                                */
+    __IO uint32_t UPDSUBSEC;             /*!< [0x0124] Time Stamp Update Sub Second Register                            */
+    __IO uint32_t ALMSEC;                /*!< [0x0128] Time Stamp Alarm Second Register                                 */
+    __IO uint32_t ALMSUBSEC;             /*!< [0x012c] Time Stamp Alarm Sub Second Register                             */
+
+} EMAC_T;
+
+/**
+    @addtogroup EMAC_CONST EMAC Bit Field Definition
+    Constant Definitions for EMAC Controller
+@{ */
+
+#define EMAC_CAMCTL_AUP_Pos              (0)                                               /*!< EMAC_T::CAMCTL: AUP Position           */
+#define EMAC_CAMCTL_AUP_Msk              (0x1ul << EMAC_CAMCTL_AUP_Pos)                    /*!< EMAC_T::CAMCTL: AUP Mask               */
+
+#define EMAC_CAMCTL_AMP_Pos              (1)                                               /*!< EMAC_T::CAMCTL: AMP Position           */
+#define EMAC_CAMCTL_AMP_Msk              (0x1ul << EMAC_CAMCTL_AMP_Pos)                    /*!< EMAC_T::CAMCTL: AMP Mask               */
+
+#define EMAC_CAMCTL_ABP_Pos              (2)                                               /*!< EMAC_T::CAMCTL: ABP Position           */
+#define EMAC_CAMCTL_ABP_Msk              (0x1ul << EMAC_CAMCTL_ABP_Pos)                    /*!< EMAC_T::CAMCTL: ABP Mask               */
+
+#define EMAC_CAMCTL_COMPEN_Pos           (3)                                               /*!< EMAC_T::CAMCTL: COMPEN Position        */
+#define EMAC_CAMCTL_COMPEN_Msk           (0x1ul << EMAC_CAMCTL_COMPEN_Pos)                 /*!< EMAC_T::CAMCTL: COMPEN Mask            */
+
+#define EMAC_CAMCTL_CMPEN_Pos            (4)                                               /*!< EMAC_T::CAMCTL: CMPEN Position         */
+#define EMAC_CAMCTL_CMPEN_Msk            (0x1ul << EMAC_CAMCTL_CMPEN_Pos)                  /*!< EMAC_T::CAMCTL: CMPEN Mask             */
+
+#define EMAC_CAMEN_CAMxEN_Pos            (0)                                               /*!< EMAC_T::CAMEN: CAMxEN Position         */
+#define EMAC_CAMEN_CAMxEN_Msk            (0x1ul << EMAC_CAMEN_CAMxEN_Pos)                  /*!< EMAC_T::CAMEN: CAMxEN Mask             */
+
+#define EMAC_CAM0M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM0M: MACADDR2 Position       */
+#define EMAC_CAM0M_MACADDR2_Msk          (0xfful << EMAC_CAM0M_MACADDR2_Pos)               /*!< EMAC_T::CAM0M: MACADDR2 Mask           */
+
+#define EMAC_CAM0M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM0M: MACADDR3 Position       */
+#define EMAC_CAM0M_MACADDR3_Msk          (0xfful << EMAC_CAM0M_MACADDR3_Pos)               /*!< EMAC_T::CAM0M: MACADDR3 Mask           */
+
+#define EMAC_CAM0M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM0M: MACADDR4 Position       */
+#define EMAC_CAM0M_MACADDR4_Msk          (0xfful << EMAC_CAM0M_MACADDR4_Pos)               /*!< EMAC_T::CAM0M: MACADDR4 Mask           */
+
+#define EMAC_CAM0M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM0M: MACADDR5 Position       */
+#define EMAC_CAM0M_MACADDR5_Msk          (0xfful << EMAC_CAM0M_MACADDR5_Pos)               /*!< EMAC_T::CAM0M: MACADDR5 Mask           */
+
+#define EMAC_CAM0L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM0L: MACADDR0 Position       */
+#define EMAC_CAM0L_MACADDR0_Msk          (0xfful << EMAC_CAM0L_MACADDR0_Pos)               /*!< EMAC_T::CAM0L: MACADDR0 Mask           */
+
+#define EMAC_CAM0L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM0L: MACADDR1 Position       */
+#define EMAC_CAM0L_MACADDR1_Msk          (0xfful << EMAC_CAM0L_MACADDR1_Pos)               /*!< EMAC_T::CAM0L: MACADDR1 Mask           */
+
+#define EMAC_CAM1M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM1M: MACADDR2 Position       */
+#define EMAC_CAM1M_MACADDR2_Msk          (0xfful << EMAC_CAM1M_MACADDR2_Pos)               /*!< EMAC_T::CAM1M: MACADDR2 Mask           */
+
+#define EMAC_CAM1M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM1M: MACADDR3 Position       */
+#define EMAC_CAM1M_MACADDR3_Msk          (0xfful << EMAC_CAM1M_MACADDR3_Pos)               /*!< EMAC_T::CAM1M: MACADDR3 Mask           */
+
+#define EMAC_CAM1M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM1M: MACADDR4 Position       */
+#define EMAC_CAM1M_MACADDR4_Msk          (0xfful << EMAC_CAM1M_MACADDR4_Pos)               /*!< EMAC_T::CAM1M: MACADDR4 Mask           */
+
+#define EMAC_CAM1M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM1M: MACADDR5 Position       */
+#define EMAC_CAM1M_MACADDR5_Msk          (0xfful << EMAC_CAM1M_MACADDR5_Pos)               /*!< EMAC_T::CAM1M: MACADDR5 Mask           */
+
+#define EMAC_CAM1L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM1L: MACADDR0 Position       */
+#define EMAC_CAM1L_MACADDR0_Msk          (0xfful << EMAC_CAM1L_MACADDR0_Pos)               /*!< EMAC_T::CAM1L: MACADDR0 Mask           */
+
+#define EMAC_CAM1L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM1L: MACADDR1 Position       */
+#define EMAC_CAM1L_MACADDR1_Msk          (0xfful << EMAC_CAM1L_MACADDR1_Pos)               /*!< EMAC_T::CAM1L: MACADDR1 Mask           */
+
+#define EMAC_CAM2M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM2M: MACADDR2 Position       */
+#define EMAC_CAM2M_MACADDR2_Msk          (0xfful << EMAC_CAM2M_MACADDR2_Pos)               /*!< EMAC_T::CAM2M: MACADDR2 Mask           */
+
+#define EMAC_CAM2M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM2M: MACADDR3 Position       */
+#define EMAC_CAM2M_MACADDR3_Msk          (0xfful << EMAC_CAM2M_MACADDR3_Pos)               /*!< EMAC_T::CAM2M: MACADDR3 Mask           */
+
+#define EMAC_CAM2M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM2M: MACADDR4 Position       */
+#define EMAC_CAM2M_MACADDR4_Msk          (0xfful << EMAC_CAM2M_MACADDR4_Pos)               /*!< EMAC_T::CAM2M: MACADDR4 Mask           */
+
+#define EMAC_CAM2M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM2M: MACADDR5 Position       */
+#define EMAC_CAM2M_MACADDR5_Msk          (0xfful << EMAC_CAM2M_MACADDR5_Pos)               /*!< EMAC_T::CAM2M: MACADDR5 Mask           */
+
+#define EMAC_CAM2L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM2L: MACADDR0 Position       */
+#define EMAC_CAM2L_MACADDR0_Msk          (0xfful << EMAC_CAM2L_MACADDR0_Pos)               /*!< EMAC_T::CAM2L: MACADDR0 Mask           */
+
+#define EMAC_CAM2L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM2L: MACADDR1 Position       */
+#define EMAC_CAM2L_MACADDR1_Msk          (0xfful << EMAC_CAM2L_MACADDR1_Pos)               /*!< EMAC_T::CAM2L: MACADDR1 Mask           */
+
+#define EMAC_CAM3M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM3M: MACADDR2 Position       */
+#define EMAC_CAM3M_MACADDR2_Msk          (0xfful << EMAC_CAM3M_MACADDR2_Pos)               /*!< EMAC_T::CAM3M: MACADDR2 Mask           */
+
+#define EMAC_CAM3M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM3M: MACADDR3 Position       */
+#define EMAC_CAM3M_MACADDR3_Msk          (0xfful << EMAC_CAM3M_MACADDR3_Pos)               /*!< EMAC_T::CAM3M: MACADDR3 Mask           */
+
+#define EMAC_CAM3M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM3M: MACADDR4 Position       */
+#define EMAC_CAM3M_MACADDR4_Msk          (0xfful << EMAC_CAM3M_MACADDR4_Pos)               /*!< EMAC_T::CAM3M: MACADDR4 Mask           */
+
+#define EMAC_CAM3M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM3M: MACADDR5 Position       */
+#define EMAC_CAM3M_MACADDR5_Msk          (0xfful << EMAC_CAM3M_MACADDR5_Pos)               /*!< EMAC_T::CAM3M: MACADDR5 Mask           */
+
+#define EMAC_CAM3L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM3L: MACADDR0 Position       */
+#define EMAC_CAM3L_MACADDR0_Msk          (0xfful << EMAC_CAM3L_MACADDR0_Pos)               /*!< EMAC_T::CAM3L: MACADDR0 Mask           */
+
+#define EMAC_CAM3L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM3L: MACADDR1 Position       */
+#define EMAC_CAM3L_MACADDR1_Msk          (0xfful << EMAC_CAM3L_MACADDR1_Pos)               /*!< EMAC_T::CAM3L: MACADDR1 Mask           */
+
+#define EMAC_CAM4M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM4M: MACADDR2 Position       */
+#define EMAC_CAM4M_MACADDR2_Msk          (0xfful << EMAC_CAM4M_MACADDR2_Pos)               /*!< EMAC_T::CAM4M: MACADDR2 Mask           */
+
+#define EMAC_CAM4M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM4M: MACADDR3 Position       */
+#define EMAC_CAM4M_MACADDR3_Msk          (0xfful << EMAC_CAM4M_MACADDR3_Pos)               /*!< EMAC_T::CAM4M: MACADDR3 Mask           */
+
+#define EMAC_CAM4M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM4M: MACADDR4 Position       */
+#define EMAC_CAM4M_MACADDR4_Msk          (0xfful << EMAC_CAM4M_MACADDR4_Pos)               /*!< EMAC_T::CAM4M: MACADDR4 Mask           */
+
+#define EMAC_CAM4M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM4M: MACADDR5 Position       */
+#define EMAC_CAM4M_MACADDR5_Msk          (0xfful << EMAC_CAM4M_MACADDR5_Pos)               /*!< EMAC_T::CAM4M: MACADDR5 Mask           */
+
+#define EMAC_CAM4L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM4L: MACADDR0 Position       */
+#define EMAC_CAM4L_MACADDR0_Msk          (0xfful << EMAC_CAM4L_MACADDR0_Pos)               /*!< EMAC_T::CAM4L: MACADDR0 Mask           */
+
+#define EMAC_CAM4L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM4L: MACADDR1 Position       */
+#define EMAC_CAM4L_MACADDR1_Msk          (0xfful << EMAC_CAM4L_MACADDR1_Pos)               /*!< EMAC_T::CAM4L: MACADDR1 Mask           */
+
+#define EMAC_CAM5M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM5M: MACADDR2 Position       */
+#define EMAC_CAM5M_MACADDR2_Msk          (0xfful << EMAC_CAM5M_MACADDR2_Pos)               /*!< EMAC_T::CAM5M: MACADDR2 Mask           */
+
+#define EMAC_CAM5M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM5M: MACADDR3 Position       */
+#define EMAC_CAM5M_MACADDR3_Msk          (0xfful << EMAC_CAM5M_MACADDR3_Pos)               /*!< EMAC_T::CAM5M: MACADDR3 Mask           */
+
+#define EMAC_CAM5M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM5M: MACADDR4 Position       */
+#define EMAC_CAM5M_MACADDR4_Msk          (0xfful << EMAC_CAM5M_MACADDR4_Pos)               /*!< EMAC_T::CAM5M: MACADDR4 Mask           */
+
+#define EMAC_CAM5M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM5M: MACADDR5 Position       */
+#define EMAC_CAM5M_MACADDR5_Msk          (0xfful << EMAC_CAM5M_MACADDR5_Pos)               /*!< EMAC_T::CAM5M: MACADDR5 Mask           */
+
+#define EMAC_CAM5L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM5L: MACADDR0 Position       */
+#define EMAC_CAM5L_MACADDR0_Msk          (0xfful << EMAC_CAM5L_MACADDR0_Pos)               /*!< EMAC_T::CAM5L: MACADDR0 Mask           */
+
+#define EMAC_CAM5L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM5L: MACADDR1 Position       */
+#define EMAC_CAM5L_MACADDR1_Msk          (0xfful << EMAC_CAM5L_MACADDR1_Pos)               /*!< EMAC_T::CAM5L: MACADDR1 Mask           */
+
+#define EMAC_CAM6M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM6M: MACADDR2 Position       */
+#define EMAC_CAM6M_MACADDR2_Msk          (0xfful << EMAC_CAM6M_MACADDR2_Pos)               /*!< EMAC_T::CAM6M: MACADDR2 Mask           */
+
+#define EMAC_CAM6M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM6M: MACADDR3 Position       */
+#define EMAC_CAM6M_MACADDR3_Msk          (0xfful << EMAC_CAM6M_MACADDR3_Pos)               /*!< EMAC_T::CAM6M: MACADDR3 Mask           */
+
+#define EMAC_CAM6M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM6M: MACADDR4 Position       */
+#define EMAC_CAM6M_MACADDR4_Msk          (0xfful << EMAC_CAM6M_MACADDR4_Pos)               /*!< EMAC_T::CAM6M: MACADDR4 Mask           */
+
+#define EMAC_CAM6M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM6M: MACADDR5 Position       */
+#define EMAC_CAM6M_MACADDR5_Msk          (0xfful << EMAC_CAM6M_MACADDR5_Pos)               /*!< EMAC_T::CAM6M: MACADDR5 Mask           */
+
+#define EMAC_CAM6L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM6L: MACADDR0 Position       */
+#define EMAC_CAM6L_MACADDR0_Msk          (0xfful << EMAC_CAM6L_MACADDR0_Pos)               /*!< EMAC_T::CAM6L: MACADDR0 Mask           */
+
+#define EMAC_CAM6L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM6L: MACADDR1 Position       */
+#define EMAC_CAM6L_MACADDR1_Msk          (0xfful << EMAC_CAM6L_MACADDR1_Pos)               /*!< EMAC_T::CAM6L: MACADDR1 Mask           */
+
+#define EMAC_CAM7M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM7M: MACADDR2 Position       */
+#define EMAC_CAM7M_MACADDR2_Msk          (0xfful << EMAC_CAM7M_MACADDR2_Pos)               /*!< EMAC_T::CAM7M: MACADDR2 Mask           */
+
+#define EMAC_CAM7M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM7M: MACADDR3 Position       */
+#define EMAC_CAM7M_MACADDR3_Msk          (0xfful << EMAC_CAM7M_MACADDR3_Pos)               /*!< EMAC_T::CAM7M: MACADDR3 Mask           */
+
+#define EMAC_CAM7M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM7M: MACADDR4 Position       */
+#define EMAC_CAM7M_MACADDR4_Msk          (0xfful << EMAC_CAM7M_MACADDR4_Pos)               /*!< EMAC_T::CAM7M: MACADDR4 Mask           */
+
+#define EMAC_CAM7M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM7M: MACADDR5 Position       */
+#define EMAC_CAM7M_MACADDR5_Msk          (0xfful << EMAC_CAM7M_MACADDR5_Pos)               /*!< EMAC_T::CAM7M: MACADDR5 Mask           */
+
+#define EMAC_CAM7L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM7L: MACADDR0 Position       */
+#define EMAC_CAM7L_MACADDR0_Msk          (0xfful << EMAC_CAM7L_MACADDR0_Pos)               /*!< EMAC_T::CAM7L: MACADDR0 Mask           */
+
+#define EMAC_CAM7L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM7L: MACADDR1 Position       */
+#define EMAC_CAM7L_MACADDR1_Msk          (0xfful << EMAC_CAM7L_MACADDR1_Pos)               /*!< EMAC_T::CAM7L: MACADDR1 Mask           */
+
+#define EMAC_CAM8M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM8M: MACADDR2 Position       */
+#define EMAC_CAM8M_MACADDR2_Msk          (0xfful << EMAC_CAM8M_MACADDR2_Pos)               /*!< EMAC_T::CAM8M: MACADDR2 Mask           */
+
+#define EMAC_CAM8M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM8M: MACADDR3 Position       */
+#define EMAC_CAM8M_MACADDR3_Msk          (0xfful << EMAC_CAM8M_MACADDR3_Pos)               /*!< EMAC_T::CAM8M: MACADDR3 Mask           */
+
+#define EMAC_CAM8M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM8M: MACADDR4 Position       */
+#define EMAC_CAM8M_MACADDR4_Msk          (0xfful << EMAC_CAM8M_MACADDR4_Pos)               /*!< EMAC_T::CAM8M: MACADDR4 Mask           */
+
+#define EMAC_CAM8M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM8M: MACADDR5 Position       */
+#define EMAC_CAM8M_MACADDR5_Msk          (0xfful << EMAC_CAM8M_MACADDR5_Pos)               /*!< EMAC_T::CAM8M: MACADDR5 Mask           */
+
+#define EMAC_CAM8L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM8L: MACADDR0 Position       */
+#define EMAC_CAM8L_MACADDR0_Msk          (0xfful << EMAC_CAM8L_MACADDR0_Pos)               /*!< EMAC_T::CAM8L: MACADDR0 Mask           */
+
+#define EMAC_CAM8L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM8L: MACADDR1 Position       */
+#define EMAC_CAM8L_MACADDR1_Msk          (0xfful << EMAC_CAM8L_MACADDR1_Pos)               /*!< EMAC_T::CAM8L: MACADDR1 Mask           */
+
+#define EMAC_CAM9M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM9M: MACADDR2 Position       */
+#define EMAC_CAM9M_MACADDR2_Msk          (0xfful << EMAC_CAM9M_MACADDR2_Pos)               /*!< EMAC_T::CAM9M: MACADDR2 Mask           */
+
+#define EMAC_CAM9M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM9M: MACADDR3 Position       */
+#define EMAC_CAM9M_MACADDR3_Msk          (0xfful << EMAC_CAM9M_MACADDR3_Pos)               /*!< EMAC_T::CAM9M: MACADDR3 Mask           */
+
+#define EMAC_CAM9M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM9M: MACADDR4 Position       */
+#define EMAC_CAM9M_MACADDR4_Msk          (0xfful << EMAC_CAM9M_MACADDR4_Pos)               /*!< EMAC_T::CAM9M: MACADDR4 Mask           */
+
+#define EMAC_CAM9M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM9M: MACADDR5 Position       */
+#define EMAC_CAM9M_MACADDR5_Msk          (0xfful << EMAC_CAM9M_MACADDR5_Pos)               /*!< EMAC_T::CAM9M: MACADDR5 Mask           */
+
+#define EMAC_CAM9L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM9L: MACADDR0 Position       */
+#define EMAC_CAM9L_MACADDR0_Msk          (0xfful << EMAC_CAM9L_MACADDR0_Pos)               /*!< EMAC_T::CAM9L: MACADDR0 Mask           */
+
+#define EMAC_CAM9L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM9L: MACADDR1 Position       */
+#define EMAC_CAM9L_MACADDR1_Msk          (0xfful << EMAC_CAM9L_MACADDR1_Pos)               /*!< EMAC_T::CAM9L: MACADDR1 Mask           */
+
+#define EMAC_CAM10M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM10M: MACADDR2 Position      */
+#define EMAC_CAM10M_MACADDR2_Msk         (0xfful << EMAC_CAM10M_MACADDR2_Pos)              /*!< EMAC_T::CAM10M: MACADDR2 Mask          */
+
+#define EMAC_CAM10M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM10M: MACADDR3 Position      */
+#define EMAC_CAM10M_MACADDR3_Msk         (0xfful << EMAC_CAM10M_MACADDR3_Pos)              /*!< EMAC_T::CAM10M: MACADDR3 Mask          */
+
+#define EMAC_CAM10M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM10M: MACADDR4 Position      */
+#define EMAC_CAM10M_MACADDR4_Msk         (0xfful << EMAC_CAM10M_MACADDR4_Pos)              /*!< EMAC_T::CAM10M: MACADDR4 Mask          */
+
+#define EMAC_CAM10M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM10M: MACADDR5 Position      */
+#define EMAC_CAM10M_MACADDR5_Msk         (0xfful << EMAC_CAM10M_MACADDR5_Pos)              /*!< EMAC_T::CAM10M: MACADDR5 Mask          */
+
+#define EMAC_CAM10L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM10L: MACADDR0 Position      */
+#define EMAC_CAM10L_MACADDR0_Msk         (0xfful << EMAC_CAM10L_MACADDR0_Pos)              /*!< EMAC_T::CAM10L: MACADDR0 Mask          */
+
+#define EMAC_CAM10L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM10L: MACADDR1 Position      */
+#define EMAC_CAM10L_MACADDR1_Msk         (0xfful << EMAC_CAM10L_MACADDR1_Pos)              /*!< EMAC_T::CAM10L: MACADDR1 Mask          */
+
+#define EMAC_CAM11M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM11M: MACADDR2 Position      */
+#define EMAC_CAM11M_MACADDR2_Msk         (0xfful << EMAC_CAM11M_MACADDR2_Pos)              /*!< EMAC_T::CAM11M: MACADDR2 Mask          */
+
+#define EMAC_CAM11M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM11M: MACADDR3 Position      */
+#define EMAC_CAM11M_MACADDR3_Msk         (0xfful << EMAC_CAM11M_MACADDR3_Pos)              /*!< EMAC_T::CAM11M: MACADDR3 Mask          */
+
+#define EMAC_CAM11M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM11M: MACADDR4 Position      */
+#define EMAC_CAM11M_MACADDR4_Msk         (0xfful << EMAC_CAM11M_MACADDR4_Pos)              /*!< EMAC_T::CAM11M: MACADDR4 Mask          */
+
+#define EMAC_CAM11M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM11M: MACADDR5 Position      */
+#define EMAC_CAM11M_MACADDR5_Msk         (0xfful << EMAC_CAM11M_MACADDR5_Pos)              /*!< EMAC_T::CAM11M: MACADDR5 Mask          */
+
+#define EMAC_CAM11L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM11L: MACADDR0 Position      */
+#define EMAC_CAM11L_MACADDR0_Msk         (0xfful << EMAC_CAM11L_MACADDR0_Pos)              /*!< EMAC_T::CAM11L: MACADDR0 Mask          */
+
+#define EMAC_CAM11L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM11L: MACADDR1 Position      */
+#define EMAC_CAM11L_MACADDR1_Msk         (0xfful << EMAC_CAM11L_MACADDR1_Pos)              /*!< EMAC_T::CAM11L: MACADDR1 Mask          */
+
+#define EMAC_CAM12M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM12M: MACADDR2 Position      */
+#define EMAC_CAM12M_MACADDR2_Msk         (0xfful << EMAC_CAM12M_MACADDR2_Pos)              /*!< EMAC_T::CAM12M: MACADDR2 Mask          */
+
+#define EMAC_CAM12M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM12M: MACADDR3 Position      */
+#define EMAC_CAM12M_MACADDR3_Msk         (0xfful << EMAC_CAM12M_MACADDR3_Pos)              /*!< EMAC_T::CAM12M: MACADDR3 Mask          */
+
+#define EMAC_CAM12M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM12M: MACADDR4 Position      */
+#define EMAC_CAM12M_MACADDR4_Msk         (0xfful << EMAC_CAM12M_MACADDR4_Pos)              /*!< EMAC_T::CAM12M: MACADDR4 Mask          */
+
+#define EMAC_CAM12M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM12M: MACADDR5 Position      */
+#define EMAC_CAM12M_MACADDR5_Msk         (0xfful << EMAC_CAM12M_MACADDR5_Pos)              /*!< EMAC_T::CAM12M: MACADDR5 Mask          */
+
+#define EMAC_CAM12L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM12L: MACADDR0 Position      */
+#define EMAC_CAM12L_MACADDR0_Msk         (0xfful << EMAC_CAM12L_MACADDR0_Pos)              /*!< EMAC_T::CAM12L: MACADDR0 Mask          */
+
+#define EMAC_CAM12L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM12L: MACADDR1 Position      */
+#define EMAC_CAM12L_MACADDR1_Msk         (0xfful << EMAC_CAM12L_MACADDR1_Pos)              /*!< EMAC_T::CAM12L: MACADDR1 Mask          */
+
+#define EMAC_CAM13M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM13M: MACADDR2 Position      */
+#define EMAC_CAM13M_MACADDR2_Msk         (0xfful << EMAC_CAM13M_MACADDR2_Pos)              /*!< EMAC_T::CAM13M: MACADDR2 Mask          */
+
+#define EMAC_CAM13M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM13M: MACADDR3 Position      */
+#define EMAC_CAM13M_MACADDR3_Msk         (0xfful << EMAC_CAM13M_MACADDR3_Pos)              /*!< EMAC_T::CAM13M: MACADDR3 Mask          */
+
+#define EMAC_CAM13M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM13M: MACADDR4 Position      */
+#define EMAC_CAM13M_MACADDR4_Msk         (0xfful << EMAC_CAM13M_MACADDR4_Pos)              /*!< EMAC_T::CAM13M: MACADDR4 Mask          */
+
+#define EMAC_CAM13M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM13M: MACADDR5 Position      */
+#define EMAC_CAM13M_MACADDR5_Msk         (0xfful << EMAC_CAM13M_MACADDR5_Pos)              /*!< EMAC_T::CAM13M: MACADDR5 Mask          */
+
+#define EMAC_CAM13L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM13L: MACADDR0 Position      */
+#define EMAC_CAM13L_MACADDR0_Msk         (0xfful << EMAC_CAM13L_MACADDR0_Pos)              /*!< EMAC_T::CAM13L: MACADDR0 Mask          */
+
+#define EMAC_CAM13L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM13L: MACADDR1 Position      */
+#define EMAC_CAM13L_MACADDR1_Msk         (0xfful << EMAC_CAM13L_MACADDR1_Pos)              /*!< EMAC_T::CAM13L: MACADDR1 Mask          */
+
+#define EMAC_CAM14M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM14M: MACADDR2 Position      */
+#define EMAC_CAM14M_MACADDR2_Msk         (0xfful << EMAC_CAM14M_MACADDR2_Pos)              /*!< EMAC_T::CAM14M: MACADDR2 Mask          */
+
+#define EMAC_CAM14M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM14M: MACADDR3 Position      */
+#define EMAC_CAM14M_MACADDR3_Msk         (0xfful << EMAC_CAM14M_MACADDR3_Pos)              /*!< EMAC_T::CAM14M: MACADDR3 Mask          */
+
+#define EMAC_CAM14M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM14M: MACADDR4 Position      */
+#define EMAC_CAM14M_MACADDR4_Msk         (0xfful << EMAC_CAM14M_MACADDR4_Pos)              /*!< EMAC_T::CAM14M: MACADDR4 Mask          */
+
+#define EMAC_CAM14M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM14M: MACADDR5 Position      */
+#define EMAC_CAM14M_MACADDR5_Msk         (0xfful << EMAC_CAM14M_MACADDR5_Pos)              /*!< EMAC_T::CAM14M: MACADDR5 Mask          */
+
+#define EMAC_CAM14L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM14L: MACADDR0 Position      */
+#define EMAC_CAM14L_MACADDR0_Msk         (0xfful << EMAC_CAM14L_MACADDR0_Pos)              /*!< EMAC_T::CAM14L: MACADDR0 Mask          */
+
+#define EMAC_CAM14L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM14L: MACADDR1 Position      */
+#define EMAC_CAM14L_MACADDR1_Msk         (0xfful << EMAC_CAM14L_MACADDR1_Pos)              /*!< EMAC_T::CAM14L: MACADDR1 Mask          */
+
+#define EMAC_CAM15MSB_OPCODE_Pos         (0)                                               /*!< EMAC_T::CAM15MSB: OPCODE Position      */
+#define EMAC_CAM15MSB_OPCODE_Msk         (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)            /*!< EMAC_T::CAM15MSB: OPCODE Mask          */
+
+#define EMAC_CAM15MSB_LENGTH_Pos         (16)                                              /*!< EMAC_T::CAM15MSB: LENGTH Position      */
+#define EMAC_CAM15MSB_LENGTH_Msk         (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)            /*!< EMAC_T::CAM15MSB: LENGTH Mask          */
+
+#define EMAC_CAM15LSB_OPERAND_Pos        (24)                                              /*!< EMAC_T::CAM15LSB: OPERAND Position     */
+#define EMAC_CAM15LSB_OPERAND_Msk        (0xfful << EMAC_CAM15LSB_OPERAND_Pos)             /*!< EMAC_T::CAM15LSB: OPERAND Mask         */
+
+#define EMAC_TXDSA_TXDSA_Pos             (0)                                               /*!< EMAC_T::TXDSA: TXDSA Position          */
+#define EMAC_TXDSA_TXDSA_Msk             (0xfffffffful << EMAC_TXDSA_TXDSA_Pos)            /*!< EMAC_T::TXDSA: TXDSA Mask              */
+
+#define EMAC_RXDSA_RXDSA_Pos             (0)                                               /*!< EMAC_T::RXDSA: RXDSA Position          */
+#define EMAC_RXDSA_RXDSA_Msk             (0xfffffffful << EMAC_RXDSA_RXDSA_Pos)            /*!< EMAC_T::RXDSA: RXDSA Mask              */
+
+#define EMAC_CTL_RXON_Pos                (0)                                               /*!< EMAC_T::CTL: RXON Position             */
+#define EMAC_CTL_RXON_Msk                (0x1ul << EMAC_CTL_RXON_Pos)                      /*!< EMAC_T::CTL: RXON Mask                 */
+
+#define EMAC_CTL_ALP_Pos                 (1)                                               /*!< EMAC_T::CTL: ALP Position              */
+#define EMAC_CTL_ALP_Msk                 (0x1ul << EMAC_CTL_ALP_Pos)                       /*!< EMAC_T::CTL: ALP Mask                  */
+
+#define EMAC_CTL_ARP_Pos                 (2)                                               /*!< EMAC_T::CTL: ARP Position              */
+#define EMAC_CTL_ARP_Msk                 (0x1ul << EMAC_CTL_ARP_Pos)                       /*!< EMAC_T::CTL: ARP Mask                  */
+
+#define EMAC_CTL_ACP_Pos                 (3)                                               /*!< EMAC_T::CTL: ACP Position              */
+#define EMAC_CTL_ACP_Msk                 (0x1ul << EMAC_CTL_ACP_Pos)                       /*!< EMAC_T::CTL: ACP Mask                  */
+
+#define EMAC_CTL_AEP_Pos                 (4)                                               /*!< EMAC_T::CTL: AEP Position              */
+#define EMAC_CTL_AEP_Msk                 (0x1ul << EMAC_CTL_AEP_Pos)                       /*!< EMAC_T::CTL: AEP Mask                  */
+
+#define EMAC_CTL_STRIPCRC_Pos            (5)                                               /*!< EMAC_T::CTL: STRIPCRC Position         */
+#define EMAC_CTL_STRIPCRC_Msk            (0x1ul << EMAC_CTL_STRIPCRC_Pos)                  /*!< EMAC_T::CTL: STRIPCRC Mask             */
+
+#define EMAC_CTL_WOLEN_Pos               (6)                                               /*!< EMAC_T::CTL: WOLEN Position            */
+#define EMAC_CTL_WOLEN_Msk               (0x1ul << EMAC_CTL_WOLEN_Pos)                     /*!< EMAC_T::CTL: WOLEN Mask                */
+
+#define EMAC_CTL_TXON_Pos                (8)                                               /*!< EMAC_T::CTL: TXON Position             */
+#define EMAC_CTL_TXON_Msk                (0x1ul << EMAC_CTL_TXON_Pos)                      /*!< EMAC_T::CTL: TXON Mask                 */
+
+#define EMAC_CTL_NODEF_Pos               (9)                                               /*!< EMAC_T::CTL: NODEF Position            */
+#define EMAC_CTL_NODEF_Msk               (0x1ul << EMAC_CTL_NODEF_Pos)                     /*!< EMAC_T::CTL: NODEF Mask                */
+
+#define EMAC_CTL_SDPZ_Pos                (16)                                              /*!< EMAC_T::CTL: SDPZ Position             */
+#define EMAC_CTL_SDPZ_Msk                (0x1ul << EMAC_CTL_SDPZ_Pos)                      /*!< EMAC_T::CTL: SDPZ Mask                 */
+
+#define EMAC_CTL_SQECHKEN_Pos            (17)                                              /*!< EMAC_T::CTL: SQECHKEN Position         */
+#define EMAC_CTL_SQECHKEN_Msk            (0x1ul << EMAC_CTL_SQECHKEN_Pos)                  /*!< EMAC_T::CTL: SQECHKEN Mask             */
+
+#define EMAC_CTL_FUDUP_Pos               (18)                                              /*!< EMAC_T::CTL: FUDUP Position            */
+#define EMAC_CTL_FUDUP_Msk               (0x1ul << EMAC_CTL_FUDUP_Pos)                     /*!< EMAC_T::CTL: FUDUP Mask                */
+
+#define EMAC_CTL_RMIIRXCTL_Pos           (19)                                              /*!< EMAC_T::CTL: RMIIRXCTL Position        */
+#define EMAC_CTL_RMIIRXCTL_Msk           (0x1ul << EMAC_CTL_RMIIRXCTL_Pos)                 /*!< EMAC_T::CTL: RMIIRXCTL Mask            */
+
+#define EMAC_CTL_OPMODE_Pos              (20)                                              /*!< EMAC_T::CTL: OPMODE Position           */
+#define EMAC_CTL_OPMODE_Msk              (0x1ul << EMAC_CTL_OPMODE_Pos)                    /*!< EMAC_T::CTL: OPMODE Mask               */
+
+#define EMAC_CTL_RMIIEN_Pos              (22)                                              /*!< EMAC_T::CTL: RMIIEN Position           */
+#define EMAC_CTL_RMIIEN_Msk              (0x1ul << EMAC_CTL_RMIIEN_Pos)                    /*!< EMAC_T::CTL: RMIIEN Mask               */
+
+#define EMAC_CTL_RST_Pos                 (24)                                              /*!< EMAC_T::CTL: RST Position              */
+#define EMAC_CTL_RST_Msk                 (0x1ul << EMAC_CTL_RST_Pos)                       /*!< EMAC_T::CTL: RST Mask                  */
+
+#define EMAC_MIIMDAT_DATA_Pos            (0)                                               /*!< EMAC_T::MIIMDAT: DATA Position         */
+#define EMAC_MIIMDAT_DATA_Msk            (0xfffful << EMAC_MIIMDAT_DATA_Pos)               /*!< EMAC_T::MIIMDAT: DATA Mask             */
+
+#define EMAC_MIIMCTL_PHYREG_Pos          (0)                                               /*!< EMAC_T::MIIMCTL: PHYREG Position       */
+#define EMAC_MIIMCTL_PHYREG_Msk          (0x1ful << EMAC_MIIMCTL_PHYREG_Pos)               /*!< EMAC_T::MIIMCTL: PHYREG Mask           */
+
+#define EMAC_MIIMCTL_PHYADDR_Pos         (8)                                               /*!< EMAC_T::MIIMCTL: PHYADDR Position      */
+#define EMAC_MIIMCTL_PHYADDR_Msk         (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos)              /*!< EMAC_T::MIIMCTL: PHYADDR Mask          */
+
+#define EMAC_MIIMCTL_WRITE_Pos           (16)                                              /*!< EMAC_T::MIIMCTL: WRITE Position        */
+#define EMAC_MIIMCTL_WRITE_Msk           (0x1ul << EMAC_MIIMCTL_WRITE_Pos)                 /*!< EMAC_T::MIIMCTL: WRITE Mask            */
+
+#define EMAC_MIIMCTL_BUSY_Pos            (17)                                              /*!< EMAC_T::MIIMCTL: BUSY Position         */
+#define EMAC_MIIMCTL_BUSY_Msk            (0x1ul << EMAC_MIIMCTL_BUSY_Pos)                  /*!< EMAC_T::MIIMCTL: BUSY Mask             */
+
+#define EMAC_MIIMCTL_PREAMSP_Pos         (18)                                              /*!< EMAC_T::MIIMCTL: PREAMSP Position      */
+#define EMAC_MIIMCTL_PREAMSP_Msk         (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos)               /*!< EMAC_T::MIIMCTL: PREAMSP Mask          */
+
+#define EMAC_MIIMCTL_MDCON_Pos           (19)                                              /*!< EMAC_T::MIIMCTL: MDCON Position        */
+#define EMAC_MIIMCTL_MDCON_Msk           (0x1ul << EMAC_MIIMCTL_MDCON_Pos)                 /*!< EMAC_T::MIIMCTL: MDCON Mask            */
+
+#define EMAC_FIFOCTL_RXFIFOTH_Pos        (0)                                               /*!< EMAC_T::FIFOCTL: RXFIFOTH Position     */
+#define EMAC_FIFOCTL_RXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos)              /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask         */
+
+#define EMAC_FIFOCTL_TXFIFOTH_Pos        (8)                                               /*!< EMAC_T::FIFOCTL: TXFIFOTH Position     */
+#define EMAC_FIFOCTL_TXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos)              /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask         */
+
+#define EMAC_FIFOCTL_BURSTLEN_Pos        (20)                                              /*!< EMAC_T::FIFOCTL: BURSTLEN Position     */
+#define EMAC_FIFOCTL_BURSTLEN_Msk        (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos)              /*!< EMAC_T::FIFOCTL: BURSTLEN Mask         */
+
+#define EMAC_TXST_TXST_Pos               (0)                                               /*!< EMAC_T::TXST: TXST Position            */
+#define EMAC_TXST_TXST_Msk               (0xfffffffful << EMAC_TXST_TXST_Pos)              /*!< EMAC_T::TXST: TXST Mask                */
+
+#define EMAC_RXST_RXST_Pos               (0)                                               /*!< EMAC_T::RXST: RXST Position            */
+#define EMAC_RXST_RXST_Msk               (0xfffffffful << EMAC_RXST_RXST_Pos)              /*!< EMAC_T::RXST: RXST Mask                */
+
+#define EMAC_MRFL_MRFL_Pos               (0)                                               /*!< EMAC_T::MRFL: MRFL Position            */
+#define EMAC_MRFL_MRFL_Msk               (0xfffful << EMAC_MRFL_MRFL_Pos)                  /*!< EMAC_T::MRFL: MRFL Mask                */
+
+#define EMAC_INTEN_RXIEN_Pos             (0)                                               /*!< EMAC_T::INTEN: RXIEN Position          */
+#define EMAC_INTEN_RXIEN_Msk             (0x1ul << EMAC_INTEN_RXIEN_Pos)                   /*!< EMAC_T::INTEN: RXIEN Mask              */
+
+#define EMAC_INTEN_CRCEIEN_Pos           (1)                                               /*!< EMAC_T::INTEN: CRCEIEN Position        */
+#define EMAC_INTEN_CRCEIEN_Msk           (0x1ul << EMAC_INTEN_CRCEIEN_Pos)                 /*!< EMAC_T::INTEN: CRCEIEN Mask            */
+
+#define EMAC_INTEN_RXOVIEN_Pos           (2)                                               /*!< EMAC_T::INTEN: RXOVIEN Position        */
+#define EMAC_INTEN_RXOVIEN_Msk           (0x1ul << EMAC_INTEN_RXOVIEN_Pos)                 /*!< EMAC_T::INTEN: RXOVIEN Mask            */
+
+#define EMAC_INTEN_LPIEN_Pos             (3)                                               /*!< EMAC_T::INTEN: LPIEN Position          */
+#define EMAC_INTEN_LPIEN_Msk             (0x1ul << EMAC_INTEN_LPIEN_Pos)                   /*!< EMAC_T::INTEN: LPIEN Mask              */
+
+#define EMAC_INTEN_RXGDIEN_Pos           (4)                                               /*!< EMAC_T::INTEN: RXGDIEN Position        */
+#define EMAC_INTEN_RXGDIEN_Msk           (0x1ul << EMAC_INTEN_RXGDIEN_Pos)                 /*!< EMAC_T::INTEN: RXGDIEN Mask            */
+
+#define EMAC_INTEN_ALIEIEN_Pos           (5)                                               /*!< EMAC_T::INTEN: ALIEIEN Position        */
+#define EMAC_INTEN_ALIEIEN_Msk           (0x1ul << EMAC_INTEN_ALIEIEN_Pos)                 /*!< EMAC_T::INTEN: ALIEIEN Mask            */
+
+#define EMAC_INTEN_RPIEN_Pos             (6)                                               /*!< EMAC_T::INTEN: RPIEN Position          */
+#define EMAC_INTEN_RPIEN_Msk             (0x1ul << EMAC_INTEN_RPIEN_Pos)                   /*!< EMAC_T::INTEN: RPIEN Mask              */
+
+#define EMAC_INTEN_MPCOVIEN_Pos          (7)                                               /*!< EMAC_T::INTEN: MPCOVIEN Position       */
+#define EMAC_INTEN_MPCOVIEN_Msk          (0x1ul << EMAC_INTEN_MPCOVIEN_Pos)                /*!< EMAC_T::INTEN: MPCOVIEN Mask           */
+
+#define EMAC_INTEN_MFLEIEN_Pos           (8)                                               /*!< EMAC_T::INTEN: MFLEIEN Position        */
+#define EMAC_INTEN_MFLEIEN_Msk           (0x1ul << EMAC_INTEN_MFLEIEN_Pos)                 /*!< EMAC_T::INTEN: MFLEIEN Mask            */
+
+#define EMAC_INTEN_DENIEN_Pos            (9)                                               /*!< EMAC_T::INTEN: DENIEN Position         */
+#define EMAC_INTEN_DENIEN_Msk            (0x1ul << EMAC_INTEN_DENIEN_Pos)                  /*!< EMAC_T::INTEN: DENIEN Mask             */
+
+#define EMAC_INTEN_RDUIEN_Pos            (10)                                              /*!< EMAC_T::INTEN: RDUIEN Position         */
+#define EMAC_INTEN_RDUIEN_Msk            (0x1ul << EMAC_INTEN_RDUIEN_Pos)                  /*!< EMAC_T::INTEN: RDUIEN Mask             */
+
+#define EMAC_INTEN_RXBEIEN_Pos           (11)                                              /*!< EMAC_T::INTEN: RXBEIEN Position        */
+#define EMAC_INTEN_RXBEIEN_Msk           (0x1ul << EMAC_INTEN_RXBEIEN_Pos)                 /*!< EMAC_T::INTEN: RXBEIEN Mask            */
+
+#define EMAC_INTEN_CFRIEN_Pos            (14)                                              /*!< EMAC_T::INTEN: CFRIEN Position         */
+#define EMAC_INTEN_CFRIEN_Msk            (0x1ul << EMAC_INTEN_CFRIEN_Pos)                  /*!< EMAC_T::INTEN: CFRIEN Mask             */
+
+#define EMAC_INTEN_WOLIEN_Pos            (15)                                              /*!< EMAC_T::INTEN: WOLIEN Position         */
+#define EMAC_INTEN_WOLIEN_Msk            (0x1ul << EMAC_INTEN_WOLIEN_Pos)                  /*!< EMAC_T::INTEN: WOLIEN Mask             */
+
+#define EMAC_INTEN_TXIEN_Pos             (16)                                              /*!< EMAC_T::INTEN: TXIEN Position          */
+#define EMAC_INTEN_TXIEN_Msk             (0x1ul << EMAC_INTEN_TXIEN_Pos)                   /*!< EMAC_T::INTEN: TXIEN Mask              */
+
+#define EMAC_INTEN_TXUDIEN_Pos           (17)                                              /*!< EMAC_T::INTEN: TXUDIEN Position        */
+#define EMAC_INTEN_TXUDIEN_Msk           (0x1ul << EMAC_INTEN_TXUDIEN_Pos)                 /*!< EMAC_T::INTEN: TXUDIEN Mask            */
+
+#define EMAC_INTEN_TXCPIEN_Pos           (18)                                              /*!< EMAC_T::INTEN: TXCPIEN Position        */
+#define EMAC_INTEN_TXCPIEN_Msk           (0x1ul << EMAC_INTEN_TXCPIEN_Pos)                 /*!< EMAC_T::INTEN: TXCPIEN Mask            */
+
+#define EMAC_INTEN_EXDEFIEN_Pos          (19)                                              /*!< EMAC_T::INTEN: EXDEFIEN Position       */
+#define EMAC_INTEN_EXDEFIEN_Msk          (0x1ul << EMAC_INTEN_EXDEFIEN_Pos)                /*!< EMAC_T::INTEN: EXDEFIEN Mask           */
+
+#define EMAC_INTEN_NCSIEN_Pos            (20)                                              /*!< EMAC_T::INTEN: NCSIEN Position         */
+#define EMAC_INTEN_NCSIEN_Msk            (0x1ul << EMAC_INTEN_NCSIEN_Pos)                  /*!< EMAC_T::INTEN: NCSIEN Mask             */
+
+#define EMAC_INTEN_TXABTIEN_Pos          (21)                                              /*!< EMAC_T::INTEN: TXABTIEN Position       */
+#define EMAC_INTEN_TXABTIEN_Msk          (0x1ul << EMAC_INTEN_TXABTIEN_Pos)                /*!< EMAC_T::INTEN: TXABTIEN Mask           */
+
+#define EMAC_INTEN_LCIEN_Pos             (22)                                              /*!< EMAC_T::INTEN: LCIEN Position          */
+#define EMAC_INTEN_LCIEN_Msk             (0x1ul << EMAC_INTEN_LCIEN_Pos)                   /*!< EMAC_T::INTEN: LCIEN Mask              */
+
+#define EMAC_INTEN_TDUIEN_Pos            (23)                                              /*!< EMAC_T::INTEN: TDUIEN Position         */
+#define EMAC_INTEN_TDUIEN_Msk            (0x1ul << EMAC_INTEN_TDUIEN_Pos)                  /*!< EMAC_T::INTEN: TDUIEN Mask             */
+
+#define EMAC_INTEN_TXBEIEN_Pos           (24)                                              /*!< EMAC_T::INTEN: TXBEIEN Position        */
+#define EMAC_INTEN_TXBEIEN_Msk           (0x1ul << EMAC_INTEN_TXBEIEN_Pos)                 /*!< EMAC_T::INTEN: TXBEIEN Mask            */
+
+#define EMAC_INTEN_TSALMIEN_Pos          (28)                                              /*!< EMAC_T::INTEN: TSALMIEN Position       */
+#define EMAC_INTEN_TSALMIEN_Msk          (0x1ul << EMAC_INTEN_TSALMIEN_Pos)                /*!< EMAC_T::INTEN: TSALMIEN Mask           */
+
+#define EMAC_INTSTS_RXIF_Pos             (0)                                               /*!< EMAC_T::INTSTS: RXIF Position          */
+#define EMAC_INTSTS_RXIF_Msk             (0x1ul << EMAC_INTSTS_RXIF_Pos)                   /*!< EMAC_T::INTSTS: RXIF Mask              */
+
+#define EMAC_INTSTS_CRCEIF_Pos           (1)                                               /*!< EMAC_T::INTSTS: CRCEIF Position        */
+#define EMAC_INTSTS_CRCEIF_Msk           (0x1ul << EMAC_INTSTS_CRCEIF_Pos)                 /*!< EMAC_T::INTSTS: CRCEIF Mask            */
+
+#define EMAC_INTSTS_RXOVIF_Pos           (2)                                               /*!< EMAC_T::INTSTS: RXOVIF Position        */
+#define EMAC_INTSTS_RXOVIF_Msk           (0x1ul << EMAC_INTSTS_RXOVIF_Pos)                 /*!< EMAC_T::INTSTS: RXOVIF Mask            */
+
+#define EMAC_INTSTS_LPIF_Pos             (3)                                               /*!< EMAC_T::INTSTS: LPIF Position          */
+#define EMAC_INTSTS_LPIF_Msk             (0x1ul << EMAC_INTSTS_LPIF_Pos)                   /*!< EMAC_T::INTSTS: LPIF Mask              */
+
+#define EMAC_INTSTS_RXGDIF_Pos           (4)                                               /*!< EMAC_T::INTSTS: RXGDIF Position        */
+#define EMAC_INTSTS_RXGDIF_Msk           (0x1ul << EMAC_INTSTS_RXGDIF_Pos)                 /*!< EMAC_T::INTSTS: RXGDIF Mask            */
+
+#define EMAC_INTSTS_ALIEIF_Pos           (5)                                               /*!< EMAC_T::INTSTS: ALIEIF Position        */
+#define EMAC_INTSTS_ALIEIF_Msk           (0x1ul << EMAC_INTSTS_ALIEIF_Pos)                 /*!< EMAC_T::INTSTS: ALIEIF Mask            */
+
+#define EMAC_INTSTS_RPIF_Pos             (6)                                               /*!< EMAC_T::INTSTS: RPIF Position          */
+#define EMAC_INTSTS_RPIF_Msk             (0x1ul << EMAC_INTSTS_RPIF_Pos)                   /*!< EMAC_T::INTSTS: RPIF Mask              */
+
+#define EMAC_INTSTS_MPCOVIF_Pos          (7)                                               /*!< EMAC_T::INTSTS: MPCOVIF Position       */
+#define EMAC_INTSTS_MPCOVIF_Msk          (0x1ul << EMAC_INTSTS_MPCOVIF_Pos)                /*!< EMAC_T::INTSTS: MPCOVIF Mask           */
+
+#define EMAC_INTSTS_MFLEIF_Pos           (8)                                               /*!< EMAC_T::INTSTS: MFLEIF Position        */
+#define EMAC_INTSTS_MFLEIF_Msk           (0x1ul << EMAC_INTSTS_MFLEIF_Pos)                 /*!< EMAC_T::INTSTS: MFLEIF Mask            */
+
+#define EMAC_INTSTS_DENIF_Pos            (9)                                               /*!< EMAC_T::INTSTS: DENIF Position         */
+#define EMAC_INTSTS_DENIF_Msk            (0x1ul << EMAC_INTSTS_DENIF_Pos)                  /*!< EMAC_T::INTSTS: DENIF Mask             */
+
+#define EMAC_INTSTS_RDUIF_Pos            (10)                                              /*!< EMAC_T::INTSTS: RDUIF Position         */
+#define EMAC_INTSTS_RDUIF_Msk            (0x1ul << EMAC_INTSTS_RDUIF_Pos)                  /*!< EMAC_T::INTSTS: RDUIF Mask             */
+
+#define EMAC_INTSTS_RXBEIF_Pos           (11)                                              /*!< EMAC_T::INTSTS: RXBEIF Position        */
+#define EMAC_INTSTS_RXBEIF_Msk           (0x1ul << EMAC_INTSTS_RXBEIF_Pos)                 /*!< EMAC_T::INTSTS: RXBEIF Mask            */
+
+#define EMAC_INTSTS_CFRIF_Pos            (14)                                              /*!< EMAC_T::INTSTS: CFRIF Position         */
+#define EMAC_INTSTS_CFRIF_Msk            (0x1ul << EMAC_INTSTS_CFRIF_Pos)                  /*!< EMAC_T::INTSTS: CFRIF Mask             */
+
+#define EMAC_INTSTS_WOLIF_Pos            (15)                                              /*!< EMAC_T::INTSTS: WOLIF Position         */
+#define EMAC_INTSTS_WOLIF_Msk            (0x1ul << EMAC_INTSTS_WOLIF_Pos)                  /*!< EMAC_T::INTSTS: WOLIF Mask             */
+
+#define EMAC_INTSTS_TXIF_Pos             (16)                                              /*!< EMAC_T::INTSTS: TXIF Position          */
+#define EMAC_INTSTS_TXIF_Msk             (0x1ul << EMAC_INTSTS_TXIF_Pos)                   /*!< EMAC_T::INTSTS: TXIF Mask              */
+
+#define EMAC_INTSTS_TXUDIF_Pos           (17)                                              /*!< EMAC_T::INTSTS: TXUDIF Position        */
+#define EMAC_INTSTS_TXUDIF_Msk           (0x1ul << EMAC_INTSTS_TXUDIF_Pos)                 /*!< EMAC_T::INTSTS: TXUDIF Mask            */
+
+#define EMAC_INTSTS_TXCPIF_Pos           (18)                                              /*!< EMAC_T::INTSTS: TXCPIF Position        */
+#define EMAC_INTSTS_TXCPIF_Msk           (0x1ul << EMAC_INTSTS_TXCPIF_Pos)                 /*!< EMAC_T::INTSTS: TXCPIF Mask            */
+
+#define EMAC_INTSTS_EXDEFIF_Pos          (19)                                              /*!< EMAC_T::INTSTS: EXDEFIF Position       */
+#define EMAC_INTSTS_EXDEFIF_Msk          (0x1ul << EMAC_INTSTS_EXDEFIF_Pos)                /*!< EMAC_T::INTSTS: EXDEFIF Mask           */
+
+#define EMAC_INTSTS_NCSIF_Pos            (20)                                              /*!< EMAC_T::INTSTS: NCSIF Position         */
+#define EMAC_INTSTS_NCSIF_Msk            (0x1ul << EMAC_INTSTS_NCSIF_Pos)                  /*!< EMAC_T::INTSTS: NCSIF Mask             */
+
+#define EMAC_INTSTS_TXABTIF_Pos          (21)                                              /*!< EMAC_T::INTSTS: TXABTIF Position       */
+#define EMAC_INTSTS_TXABTIF_Msk          (0x1ul << EMAC_INTSTS_TXABTIF_Pos)                /*!< EMAC_T::INTSTS: TXABTIF Mask           */
+
+#define EMAC_INTSTS_LCIF_Pos             (22)                                              /*!< EMAC_T::INTSTS: LCIF Position          */
+#define EMAC_INTSTS_LCIF_Msk             (0x1ul << EMAC_INTSTS_LCIF_Pos)                   /*!< EMAC_T::INTSTS: LCIF Mask              */
+
+#define EMAC_INTSTS_TDUIF_Pos            (23)                                              /*!< EMAC_T::INTSTS: TDUIF Position         */
+#define EMAC_INTSTS_TDUIF_Msk            (0x1ul << EMAC_INTSTS_TDUIF_Pos)                  /*!< EMAC_T::INTSTS: TDUIF Mask             */
+
+#define EMAC_INTSTS_TXBEIF_Pos           (24)                                              /*!< EMAC_T::INTSTS: TXBEIF Position        */
+#define EMAC_INTSTS_TXBEIF_Msk           (0x1ul << EMAC_INTSTS_TXBEIF_Pos)                 /*!< EMAC_T::INTSTS: TXBEIF Mask            */
+
+#define EMAC_INTSTS_TSALMIF_Pos          (28)                                              /*!< EMAC_T::INTSTS: TSALMIF Position       */
+#define EMAC_INTSTS_TSALMIF_Msk          (0x1ul << EMAC_INTSTS_TSALMIF_Pos)                /*!< EMAC_T::INTSTS: TSALMIF Mask           */
+
+#define EMAC_GENSTS_CFR_Pos              (0)                                               /*!< EMAC_T::GENSTS: CFR Position           */
+#define EMAC_GENSTS_CFR_Msk              (0x1ul << EMAC_GENSTS_CFR_Pos)                    /*!< EMAC_T::GENSTS: CFR Mask               */
+
+#define EMAC_GENSTS_RXHALT_Pos           (1)                                               /*!< EMAC_T::GENSTS: RXHALT Position        */
+#define EMAC_GENSTS_RXHALT_Msk           (0x1ul << EMAC_GENSTS_RXHALT_Pos)                 /*!< EMAC_T::GENSTS: RXHALT Mask            */
+
+#define EMAC_GENSTS_RXFFULL_Pos          (2)                                               /*!< EMAC_T::GENSTS: RXFFULL Position       */
+#define EMAC_GENSTS_RXFFULL_Msk          (0x1ul << EMAC_GENSTS_RXFFULL_Pos)                /*!< EMAC_T::GENSTS: RXFFULL Mask           */
+
+#define EMAC_GENSTS_COLCNT_Pos           (4)                                               /*!< EMAC_T::GENSTS: COLCNT Position        */
+#define EMAC_GENSTS_COLCNT_Msk           (0xful << EMAC_GENSTS_COLCNT_Pos)                 /*!< EMAC_T::GENSTS: COLCNT Mask            */
+
+#define EMAC_GENSTS_DEF_Pos              (8)                                               /*!< EMAC_T::GENSTS: DEF Position           */
+#define EMAC_GENSTS_DEF_Msk              (0x1ul << EMAC_GENSTS_DEF_Pos)                    /*!< EMAC_T::GENSTS: DEF Mask               */
+
+#define EMAC_GENSTS_TXPAUSED_Pos         (9)                                               /*!< EMAC_T::GENSTS: TXPAUSED Position      */
+#define EMAC_GENSTS_TXPAUSED_Msk         (0x1ul << EMAC_GENSTS_TXPAUSED_Pos)               /*!< EMAC_T::GENSTS: TXPAUSED Mask          */
+
+#define EMAC_GENSTS_SQE_Pos              (10)                                              /*!< EMAC_T::GENSTS: SQE Position           */
+#define EMAC_GENSTS_SQE_Msk              (0x1ul << EMAC_GENSTS_SQE_Pos)                    /*!< EMAC_T::GENSTS: SQE Mask               */
+
+#define EMAC_GENSTS_TXHALT_Pos           (11)                                              /*!< EMAC_T::GENSTS: TXHALT Position        */
+#define EMAC_GENSTS_TXHALT_Msk           (0x1ul << EMAC_GENSTS_TXHALT_Pos)                 /*!< EMAC_T::GENSTS: TXHALT Mask            */
+
+#define EMAC_GENSTS_RPSTS_Pos            (12)                                              /*!< EMAC_T::GENSTS: RPSTS Position         */
+#define EMAC_GENSTS_RPSTS_Msk            (0x1ul << EMAC_GENSTS_RPSTS_Pos)                  /*!< EMAC_T::GENSTS: RPSTS Mask             */
+
+#define EMAC_MPCNT_MPCNT_Pos             (0)                                               /*!< EMAC_T::MPCNT: MPCNT Position          */
+#define EMAC_MPCNT_MPCNT_Msk             (0xfffful << EMAC_MPCNT_MPCNT_Pos)                /*!< EMAC_T::MPCNT: MPCNT Mask              */
+
+#define EMAC_RPCNT_RPCNT_Pos             (0)                                               /*!< EMAC_T::RPCNT: RPCNT Position          */
+#define EMAC_RPCNT_RPCNT_Msk             (0xfffful << EMAC_RPCNT_RPCNT_Pos)                /*!< EMAC_T::RPCNT: RPCNT Mask              */
+
+#define EMAC_FRSTS_RXFLT_Pos             (0)                                               /*!< EMAC_T::FRSTS: RXFLT Position          */
+#define EMAC_FRSTS_RXFLT_Msk             (0xfffful << EMAC_FRSTS_RXFLT_Pos)                /*!< EMAC_T::FRSTS: RXFLT Mask              */
+
+#define EMAC_CTXDSA_CTXDSA_Pos           (0)                                               /*!< EMAC_T::CTXDSA: CTXDSA Position        */
+#define EMAC_CTXDSA_CTXDSA_Msk           (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)          /*!< EMAC_T::CTXDSA: CTXDSA Mask            */
+
+#define EMAC_CTXBSA_CTXBSA_Pos           (0)                                               /*!< EMAC_T::CTXBSA: CTXBSA Position        */
+#define EMAC_CTXBSA_CTXBSA_Msk           (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)          /*!< EMAC_T::CTXBSA: CTXBSA Mask            */
+
+#define EMAC_CRXDSA_CRXDSA_Pos           (0)                                               /*!< EMAC_T::CRXDSA: CRXDSA Position        */
+#define EMAC_CRXDSA_CRXDSA_Msk           (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)          /*!< EMAC_T::CRXDSA: CRXDSA Mask            */
+
+#define EMAC_CRXBSA_CRXBSA_Pos           (0)                                               /*!< EMAC_T::CRXBSA: CRXBSA Position        */
+#define EMAC_CRXBSA_CRXBSA_Msk           (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)          /*!< EMAC_T::CRXBSA: CRXBSA Mask            */
+
+#define EMAC_TSCTL_TSEN_Pos              (0)                                               /*!< EMAC_T::TSCTL: TSEN Position           */
+#define EMAC_TSCTL_TSEN_Msk              (0x1ul << EMAC_TSCTL_TSEN_Pos)                    /*!< EMAC_T::TSCTL: TSEN Mask               */
+
+#define EMAC_TSCTL_TSIEN_Pos             (1)                                               /*!< EMAC_T::TSCTL: TSIEN Position          */
+#define EMAC_TSCTL_TSIEN_Msk             (0x1ul << EMAC_TSCTL_TSIEN_Pos)                   /*!< EMAC_T::TSCTL: TSIEN Mask              */
+
+#define EMAC_TSCTL_TSMODE_Pos            (2)                                               /*!< EMAC_T::TSCTL: TSMODE Position         */
+#define EMAC_TSCTL_TSMODE_Msk            (0x1ul << EMAC_TSCTL_TSMODE_Pos)                  /*!< EMAC_T::TSCTL: TSMODE Mask             */
+
+#define EMAC_TSCTL_TSUPDATE_Pos          (3)                                               /*!< EMAC_T::TSCTL: TSUPDATE Position       */
+#define EMAC_TSCTL_TSUPDATE_Msk          (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)                /*!< EMAC_T::TSCTL: TSUPDATE Mask           */
+
+#define EMAC_TSCTL_TSALMEN_Pos           (5)                                               /*!< EMAC_T::TSCTL: TSALMEN Position        */
+#define EMAC_TSCTL_TSALMEN_Msk           (0x1ul << EMAC_TSCTL_TSALMEN_Pos)                 /*!< EMAC_T::TSCTL: TSALMEN Mask            */
+
+#define EMAC_TSSEC_SEC_Pos               (0)                                               /*!< EMAC_T::TSSEC: SEC Position            */
+#define EMAC_TSSEC_SEC_Msk               (0xfffffffful << EMAC_TSSEC_SEC_Pos)              /*!< EMAC_T::TSSEC: SEC Mask                */
+
+#define EMAC_TSSUBSEC_SUBSEC_Pos         (0)                                               /*!< EMAC_T::TSSUBSEC: SUBSEC Position      */
+#define EMAC_TSSUBSEC_SUBSEC_Msk         (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)        /*!< EMAC_T::TSSUBSEC: SUBSEC Mask          */
+
+#define EMAC_TSINC_CNTINC_Pos            (0)                                               /*!< EMAC_T::TSINC: CNTINC Position         */
+#define EMAC_TSINC_CNTINC_Msk            (0xfful << EMAC_TSINC_CNTINC_Pos)                 /*!< EMAC_T::TSINC: CNTINC Mask             */
+
+#define EMAC_TSADDEND_ADDEND_Pos         (0)                                               /*!< EMAC_T::TSADDEND: ADDEND Position      */
+#define EMAC_TSADDEND_ADDEND_Msk         (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)        /*!< EMAC_T::TSADDEND: ADDEND Mask          */
+
+#define EMAC_UPDSEC_SEC_Pos              (0)                                               /*!< EMAC_T::UPDSEC: SEC Position           */
+#define EMAC_UPDSEC_SEC_Msk              (0xfffffffful << EMAC_UPDSEC_SEC_Pos)             /*!< EMAC_T::UPDSEC: SEC Mask               */
+
+#define EMAC_UPDSUBSEC_SUBSEC_Pos        (0)                                               /*!< EMAC_T::UPDSUBSEC: SUBSEC Position     */
+#define EMAC_UPDSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos)       /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask         */
+
+#define EMAC_ALMSEC_SEC_Pos              (0)                                               /*!< EMAC_T::ALMSEC: SEC Position           */
+#define EMAC_ALMSEC_SEC_Msk              (0xfffffffful << EMAC_ALMSEC_SEC_Pos)             /*!< EMAC_T::ALMSEC: SEC Mask               */
+
+#define EMAC_ALMSUBSEC_SUBSEC_Pos        (0)                                               /*!< EMAC_T::ALMSUBSEC: SUBSEC Position     */
+#define EMAC_ALMSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos)       /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask         */
+
+/**@}*/ /* EMAC_CONST */
+/**@}*/ /* end of EMAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+    #pragma no_anon_unions
+#endif
+
+#endif /* __EMAC_REG_H__ */

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_2d.h

@@ -0,0 +1,190 @@
+/**************************************************************************//**
+* @file     2d.h
+* @brief    N9H30 2DGE driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_2D_H__
+#define __NU_2D_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GE2D_Driver GE2D Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GE2D_EXPORTED_CONSTANTS GE2D Exported Constants
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+typedef struct
+{
+    UINT32    PatternA;
+    UINT32    PatternB;
+} MONOPATTERN;
+
+#define COLOR_KEY 0xFF000000
+/// @endcond HIDDEN_SYMBOLS
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of ROP2
+///////////////////////////////////////////////////////////////////////////////
+#define    BLACKNESS       0x00  /*!< rop code: 0 */
+#define    DSTINVERT       0x55  /*!< rop code: Dn  */
+#define    MERGECOPY       0xC0  /*!< rop code: PSa  */
+#define    MERGEPAINT      0xBB  /*!< rop code: DSno  */
+#define    NOTSRCCOPY      0x33  /*!< rop code: Sn  */
+#define    NOTSRCERASE     0x11  /*!< rop code: DSon  */
+#define    PATCOPY         0xF0  /*!< rop code: P  */
+#define    PATINVERT       0x5A  /*!< rop code: DPx  */
+#define    PATPAINT        0xFB  /*!< rop code: DPSnoo  */
+#define    SRCAND          0x88  /*!< rop code: DSa  */
+#define    SRCCOPY         0xCC  /*!< rop code: S  */
+#define    SRCERASE        0x44  /*!< rop code: SDna  */
+#define    SRCINVERT       0x66  /*!< rop code: DSx  */
+#define    SRCPAINT        0xEE  /*!< rop code: DSo  */
+#define    WHITENESS       0xFF  /*!< rop code: 1  */
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of Pen Styles
+///////////////////////////////////////////////////////////////////////////////
+#define PS_SOLID        0xffff     /*!< pan style: solid */ //1111111111111111 (1111111111111111)
+#define PS_DASH         0xcccc     /*!< pan style: dash */ //1100110011001100 (1111000011110000)
+#define PS_DOT          0xaaaa     /*!< pan style: dot */ //1010101010101010 (1100110011001100)
+#define PS_DASHDOT      0xe4e4     /*!< pan style: dash and dot */ //1110010011100100 (1111110000110000)
+#define PS_DASHDOTDOT   0xeaea     /*!< pan style: dash and two dots  */ //1110101011101010 (1111110011001100)
+#define PS_NULL         0x0000     /*!< pan style: null */ //0000000000000000 (0000000000000000)
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of Brush Styles
+//
+// HS_HORIZONTAL:   00000000     HS_BDIAGONAL:  00000001
+//                  00000000                    00000010
+//                  00000000                    00000100
+//                  00000000                    00001000
+//                  11111111                    00010000
+//                  00000000                    00100000
+//                  00000000                    01000000
+//                  00000000                    10000000
+//
+// HS_VERTICAL:     00001000     HS_CROSS:      00001000
+//                  00001000                    00001000
+//                  00001000                    00001000
+//                  00001000                    00001000
+//                  00001000                    11111111
+//                  00001000                    00001000
+//                  00001000                    00001000
+//                  00001000                    00001000
+//
+// HS_FDIAGONAL:    10000000     HS_DIAGCROSS:  10000001
+//                  01000000                    01000010
+//                  00100000                    00100100
+//                  00010000                    00011000
+//                  00001000                    00011000
+//                  00000100                    00100100
+//                  00000010                    01000010
+//                  00000001                    10000001
+///////////////////////////////////////////////////////////////////////////////
+#define HS_HORIZONTAL   0   /*!< brush style: horizontal */
+#define HS_VERTICAL     1   /*!< brush style: vertical */
+#define HS_FDIAGONAL    2   /*!< brush style: fdiagonal */
+#define HS_BDIAGONAL    3   /*!< brush style: bdiagonal */
+#define HS_CROSS        4   /*!< brush style: cross */
+#define HS_DIAGCROSS    5   /*!< brush style: diagcross */
+
+#define MODE_OPAQUE             0                   /*!< opaque mode */
+#define MODE_TRANSPARENT        1                   /*!< transparent mode */
+#define MODE_SRC_TRANSPARENT    MODE_TRANSPARENT    /*!< source transparent mode */
+#define MODE_DEST_TRANSPARENT   2                   /*!< destination transparent mode */
+
+#define MODE_INSIDE_CLIP    0   /*!< clip inside */
+#define MODE_OUTSIDE_CLIP   1   /*!< clip outside */
+
+#define TYPE_MONO           0   /*!< mono */
+#define TYPE_COLOR          1   /*!< color */
+
+#define GE_BPP_8    0x00000000  /*!< 8bpp display */
+#define GE_BPP_16   0x00000010  /*!< 16bpp display */
+#define GE_BPP_32   0x00000020  /*!< 32bpp display */
+
+#define RGB332 1    /*!< 8bpp display */
+#define RGB565 2    /*!< 16bpp display */
+#define RGB888 3    /*!< 24bpp display */
+
+#define F8x8            0   /*!< 8x8 font support */
+#define F8x16           1   /*!< 8x16 font support */
+
+/*@}*/ /* end of group N9H30_GE2D_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_GE2D_EXPORTED_FUNCTIONS GE2D Exported Functions
+  @{
+*/
+
+void ge2dClearScreen(int color);
+void ge2dSetWriteMask(int mask);
+void ge2dSetSourceOriginStarting(void *ptr);
+void ge2dSetDestinationOriginStarting(void *ptr);
+void ge2dInit(int bpp, int width, int height, void *destination);
+void ge2dReset(void);
+void ge2dResetFIFO(void);
+void ge2dBitblt_SetDrawMode(int opt, int ckey, int mask);
+int ge2dBitblt_SetAlphaMode(int opt, int ks, int kd);
+void ge2dBitblt_ScreenToScreen(int srcx, int srcy, int destx, int desty, int width, int height);
+void ge2dBitblt_ScreenToScreenRop(int srcx, int srcy, int destx, int desty, int width, int height, int rop);
+void ge2dBitblt_SourceToDestination(int srcx, int srcy, int destx, int desty, int width, int height, int srcpitch, int destpitch);
+void ge2dClip_SetClip(int x1, int y1, int x2, int y2);
+void ge2dClip_SetClipMode(int opt);
+void ge2dDrawFrame(int x1, int y1, int x2, int y2, int color, int opt);
+void ge2dLine_DrawSolidLine(int x1, int y1, int x2, int y2, int color);
+void ge2dLine_DrawSolidLine_RGB565(int x1, int y1, int x2, int y2, int color);
+void ge2dLine_DrawStyledLine(int x1, int y1, int x2, int y2, int style, int fgcolor, int bkcolor, int draw_mode);
+void ge2dLine_DrawStyledLine_RGB565(int x1, int y1, int x2, int y2, int style, int fgcolor, int bkcolor, int draw_mode);
+void ge2dFill_Solid(int dx, int dy, int width, int height, int color);
+void ge2dFill_Solid_RGB565(int dx, int dy, int width, int height, int color);
+void ge2dFill_SolidBackground(int dx, int dy, int width, int height, int color);
+void ge2dFill_ColorPattern(int dx, int dy, int width, int height);
+void ge2dFill_MonoPattern(int dx, int dy, int width, int height, int opt);
+void ge2dFill_ColorPatternROP(int sx, int sy, int width, int height, int rop);
+void ge2dFill_MonoPatternROP(int sx, int sy, int width, int height, int rop, int opt);
+void ge2dFill_TileBlt(int srcx, int srcy, int destx, int desty, int width, int height, int x_count, int y_count);
+void ge2dHostBlt_Write(int x, int y, int width, int height, void *buf);
+void ge2dHostBlt_Read(int x, int y, int width, int height, void *buf);
+void ge2dHostBlt_Sprite(int x, int y, int width, int height, void *buf);
+void ge2dRotation(int srcx, int srcy, int destx, int desty, int width, int height, int ctl);
+void ge2dSpriteBlt_Screen(int destx, int desty, int sprite_width, int sprite_height, void *buf);
+void ge2dSpriteBltx_Screen(int x, int y, int sprite_sx, int sprite_sy, int width, int height, int sprite_width, int sprite_height, void *buf);
+void ge2dSpriteBlt_ScreenRop(int x, int y, int sprite_width, int sprite_height, void *buf, int rop);
+void ge2dSpriteBltx_ScreenRop(int x, int y, int sprite_sx, int sprite_sy, int width, int height, int sprite_width, int sprite_height, void *buf, int rop);
+void ge2dColorExpansionBlt(int x, int y, int width, int height, int fore_color, int back_color, int opt, void *buf);
+void ge2dHostColorExpansionBlt(int x, int y, int width, int height, int fore_color, int back_color, int opt, void *buf);
+void ge2dInitMonoPattern(int opt, int fore_color, int back_color);
+void ge2dInitMonoInputPattern(UINT32 PatternA, UINT32 PatternB, int fore_color, int back_color);
+void ge2dInitColorPattern(int patformat, void *patdata);
+void ge2dFont_PutChar(int x, int y, char asc_code, int fore_color, int back_color, int draw_mode, int font_id);
+void ge2dFont_PutString(int x, int y, char *str, int fore_color, int back_color, int draw_mode, int font_id);
+
+/*@}*/ /* end of group N9H30_GE2D_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_GE2D_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_2D_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_adc.h

@@ -0,0 +1,198 @@
+/**************************************************************************//**
+* @file     adc.h
+* @brief    N9H30 ADC driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_ADC_H__
+#define __NU_ADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_ADC_Driver ADC Driver
+  @{
+*/
+
+/** @addtogroup N9H30_ADC_EXPORTED_CONSTANTS ADC Exported Constants
+  @{
+*/
+
+#define ADC_ERR_ARGS            1   /*!< The arguments is wrong */
+#define ADC_ERR_CMD             2   /*!< The command is wrong */
+
+/// @cond HIDDEN_SYMBOLS
+typedef int32_t(*ADC_CALLBACK)(uint32_t status, uint32_t userData);
+/// @endcond HIDDEN_SYMBOLS
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_CTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_CTL_ADEN            0x00000001  /*!< ADC Power Control */
+#define ADC_CTL_VBGEN       0x00000002  /*!< ADC Internal Bandgap Power Control */
+#define ADC_CTL_PWKPEN      0x00000004  /*!< ADC Keypad Power Enable Control */
+#define ADC_CTL_MST             0x00000100  /*!< Menu Start Conversion */
+#define ADC_CTL_PEDEEN      0x00000200  /*!< Pen Down Event Enable */
+#define ADC_CTL_WKPEN       0x00000400  /*!< Keypad Press Wake Up Enable */
+#define ADC_CTL_WKTEN       0x00000800  /*!< Touch Wake Up Enable */
+#define ADC_CTL_WMSWCH      0x00010000  /*!< Wire Mode Switch For 5-Wire/4-Wire Configuration */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_CONF constant definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_CONF_TEN                0x00000001  /*!< Touch Enable */
+#define ADC_CONF_ZEN                0x00000002  /*!< Press Enable */
+#define ADC_CONF_NACEN          0x00000004  /*!< Normal AD Conversion Enable */
+#define ADC_CONF_VBATEN         0x00000100  /*!< Voltage Battery Enable */
+#define ADC_CONF_KPCEN          0x00000200  /*!< Keypad Press Conversion Enable */
+#define ADC_CONF_SELFTEN        0x00000400  /*!< Selft Test Enable */
+#define ADC_CONF_DISTMAVEN  (1<<20)     /*!< Display T Mean Average Enable */
+#define ADC_CONF_DISZMAVEN  (1<<21)     /*!< Display Z Mean Average Enable */
+#define ADC_CONF_HSPEED         (1<<22)     /*!< High Speed Enable */
+
+#define ADC_CONF_CHSEL_Pos  3            /*!< Channel Selection Position */
+#define ADC_CONF_CHSEL_Msk  (7<<3)       /*!< Channel Selection Mask */
+#define ADC_CONF_CHSEL_VBT  (0<<3)       /*!< ADC input channel select VBT */
+#define ADC_CONF_CHSEL_VHS  (1<<3)       /*!< ADC input channel select VHS */
+#define ADC_CONF_CHSEL_A2       (2<<3)       /*!< ADC input channel select A2 */
+#define ADC_CONF_CHSEL_A3       (3<<3)       /*!< ADC input channel select A3 */
+#define ADC_CONF_CHSEL_YM       (4<<3)       /*!< ADC input channel select YM */
+#define ADC_CONF_CHSEL_YP       (5<<3)       /*!< ADC input channel select YP */
+#define ADC_CONF_CHSEL_XM       (6<<3)       /*!< ADC input channel select XM */
+#define ADC_CONF_CHSEL_XP       (7<<3)       /*!< ADC input channel select XP */
+
+#define ADC_CONF_REFSEL_Pos  6             /*!< Reference Selection Position */
+#define ADC_CONF_REFSEL_Msk     (3<<6)     /*!< Reference Selection Mask */
+#define ADC_CONF_REFSEL_VREF    (0<<6)     /*!< ADC reference select VREF input or 2.5v buffer output */
+#define ADC_CONF_REFSEL_YMYP    (1<<6)     /*!< ADC reference select YM vs YP */
+#define ADC_CONF_REFSEL_XMXP    (2<<6)     /*!< ADC reference select XM vs XP */
+#define ADC_CONF_REFSEL_AVDD33  (3<<6)     /*!< ADC reference select AGND33 vs AVDD33 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_IER constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_IER_MIEN                0x00000001  /*!< Menu Interrupt Enable */
+#define ADC_IER_KPEIEN          0x00000002  /*!< Keypad Press Event Interrupt Enable */
+#define ADC_IER_PEDEIEN         0x00000004  /*!< Pen Down Even Interrupt Enable */
+#define ADC_IER_WKTIEN          0x00000008  /*!< Wake Up Touch Interrupt Enable */
+#define ADC_IER_WKPIEN          0x00000010  /*!< Wake Up Keypad Press Interrupt Enable */
+#define ADC_IER_KPUEIEN         0x00000020  /*!< Keypad Press Up Event Interrupt Enable */
+#define ADC_IER_PEUEIEN         0x00000040  /*!< Pen Up Event Interrupt Enable */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_ISR constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_ISR_MF              0x00000001  /*!< Menu Complete Flag */
+#define ADC_ISR_KPEF            0x00000002  /*!< Keypad Press Event Flag */
+#define ADC_ISR_PEDEF           0x00000004  /*!< Pen Down Event Flag */
+#define ADC_ISR_KPUEF           0x00000008  /*!< Keypad Press Up Event Flag */
+#define ADC_ISR_PEUEF           0x00000010  /*!< Pen Up Event Flag */
+#define ADC_ISR_TF              0x00000100  /*!< Touch Conversion Finish */
+#define ADC_ISR_ZF              0x00000200  /*!< Press Conversion Finish */
+#define ADC_ISR_NACF            0x00000400  /*!< Normal AD Conversion Finish */
+#define ADC_ISR_VBF             0x00000800  /*!< Voltage Battery Conversion Finish */
+#define ADC_ISR_KPCF            0x00001000  /*!< Keypad Press Conversion Finish */
+#define ADC_ISR_SELFTF          0x00002000  /*!< Self-Test Conversion Finish */
+#define ADC_ISR_INTKP           0x00010000  /*!< Interrupt Signal For Keypad Detection */
+#define ADC_ISR_INTTC           0x00020000  /*!< Interrupt Signal For Touch Screen Touching Detection */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_WKISR constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_WKISR_WKPEF     0x00000001  /*!< Wake Up Pen Down Event Flag */
+#define ADC_WKISR_WPEDEF    0x00000002  /*!< Wake Up Keypad Press Event Flage */
+
+/** \brief  Structure type of ADC_CHAN
+ */
+typedef enum
+{
+    AIN0  = ADC_CONF_CHSEL_VBT,    /*!< ADC input channel select \ref ADC_CONF_CHSEL_VBT */
+    AIN1  = ADC_CONF_CHSEL_VHS,    /*!< ADC input channel select \ref ADC_CONF_CHSEL_VHS */
+    AIN2  = ADC_CONF_CHSEL_A2,     /*!< ADC input channel select \ref ADC_CONF_CHSEL_A2 */
+    AIN3  = ADC_CONF_CHSEL_A3,     /*!< ADC input channel select \ref ADC_CONF_CHSEL_A3 */
+    AIN4  = ADC_CONF_CHSEL_YM,     /*!< ADC input channel select \ref ADC_CONF_CHSEL_YM */
+    AIN5  = ADC_CONF_CHSEL_XP,     /*!< ADC input channel select \ref ADC_CONF_CHSEL_XP */
+    AIN6  = ADC_CONF_CHSEL_XM,     /*!< ADC input channel select \ref ADC_CONF_CHSEL_XM */
+    AIN7  = ADC_CONF_CHSEL_XP      /*!< ADC input channel select \ref ADC_CONF_CHSEL_XP */
+} ADC_CHAN;
+
+/** \brief  Structure type of ADC_CMD
+ */
+typedef enum
+{
+    START_MST,                  /*!<Menu Start Conversion with interrupt */
+    START_MST_POLLING,          /*!<Menu Start Conversion with polling */
+    VBPOWER_ON,                 /*!<Enable ADC Internal Bandgap Power */
+    VBPOWER_OFF,                    /*!<Disable ADC Internal Bandgap Power */
+    VBAT_ON,                            /*!<Enable Voltage Battery conversion function */
+    VBAT_OFF,                       /*!<Disable Voltage Battery conversion function */
+
+    KPPOWER_ON,                 /*!<Enable ADC Keypad power */
+    KPPOWER_OFF,                    /*!<Disable ADC Keypad power */
+    KPCONV_ON,                      /*!<Enable Keypad conversion function */
+    KPCONV_OFF,                 /*!<Disable Keypad conversion function */
+    KPPRESS_ON,                 /*!<Enable Keypad press event */
+    KPPRESS_OFF,                    /*!<Disable Keypad press event */
+    KPUP_ON,                            /*!<Enable Keypad up event */
+    KPUP_OFF,                       /*!<Disable Keypad up event */
+
+    PEPOWER_ON,                 /*!<Enable Pen Down Power ,It can control pen down event */
+    PEPOWER_OFF,                    /*!<Disable Pen Power */
+    PEDEF_ON,                       /*!<Enable Pen Down Event Flag */
+    PEDEF_OFF,                      /*!<Disable Pen Down Event Flag */
+
+    WKP_ON,                         /*!<Enable Keypad Press Wake Up */
+    WKP_OFF,                            /*!<Disable Keypad Press Wake Up */
+    WKT_ON,                         /*!<Enable Pen Down Wake Up */
+    WKT_OFF,                        /*!<Disable Pen Down Wake Up */
+    SWITCH_5WIRE_ON,            /*!<Wire Mode Switch to 5-Wire Configuration */
+    SWITCH_5WIRE_OFF,       /*!<Wire Mode Switch to 4-Wire Configuration */
+
+    T_ON,                               /*!<Enable Touch detection function */
+    T_OFF,                              /*!<Disable Touch detection function */
+    TAVG_ON,                            /*!<Enable Touch Mean average for X and Y function */
+    TAVG_OFF,                       /*!<Disable Touch Mean average for X and Y function */
+    Z_ON,                               /*!<Enable Press measure function */
+    Z_OFF,                              /*!<Disable Press measure function */
+    TZAVG_ON,                       /*!<Enable Pressure Mean average for Z1 and Z2 function */
+    TZAVG_OFF,                      /*!<Disable Pressure Mean average for Z1 and Z2 function */
+
+    NAC_ON,                         /*!<Enable Normal AD Conversion */
+    NAC_OFF,                            /*!<Disable Normal AD Conversion */
+    SWITCH_CH,                       /*!<Switch Channel */
+} ADC_CMD;
+
+/*@}*/ /* end of group N9H30_ADC_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
+  @{
+*/
+
+int adcOpen(void);
+int adcOpen2(uint32_t freq);
+int adcClose(void);
+int adcReadXY(short *bufX, short *bufY, int dataCnt);
+int adcReadZ(short *bufZ1, short *bufZ2, int dataCnt);
+int adcIoctl(ADC_CMD cmd, int arg1, int arg2);
+int adcChangeChannel(int channel);
+
+/*@}*/ /* end of group N9H30_ADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_ADC_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_ADC_H__

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_can.h

@@ -0,0 +1,459 @@
+/**************************************************************************//**
+ * @file     can.h
+ * @version  V2.00
+ * @brief    N9H30 Series CAN Driver Header File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CAN_H__
+#define __NU_CAN_H__
+
+#include "N9H30.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_NORMAL_MODE   0ul    /*!< CAN select normal mode \hideinitializer */
+#define    CAN_BASIC_MODE    1ul    /*!< CAN select basic mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_STD_ID    0ul    /*!< CAN select standard ID \hideinitializer */
+#define    CAN_EXT_ID    1ul    /*!< CAN select extended ID \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_REMOTE_FRAME    0ul    /*!< CAN frame select remote frame \hideinitializer */
+#define    CAN_DATA_FRAME    1ul      /*!< CAN frame select data frame \hideinitializer */
+
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+typedef struct
+{
+    __IO uint32_t CREQ;         /*!< [0x0020] IFn Command Request Register                                     */
+    __IO uint32_t CMASK;        /*!< [0x0024] IFn Command Mask Register                                        */
+    __IO uint32_t MASK1;        /*!< [0x0028] IFn Mask 1 Register                                              */
+    __IO uint32_t MASK2;        /*!< [0x002c] IFn Mask 2 Register                                              */
+    __IO uint32_t ARB1;         /*!< [0x0030] IFn Arbitration 1 Register                                       */
+    __IO uint32_t ARB2;         /*!< [0x0034] IFn Arbitration 2 Register                                       */
+    __IO uint32_t MCON;         /*!< [0x0038] IFn Message Control Register                                     */
+    __IO uint32_t DAT_A1;       /*!< [0x003c] IFn Data A1 Register                                             */
+    __IO uint32_t DAT_A2;       /*!< [0x0040] IFn Data A2 Register                                             */
+    __IO uint32_t DAT_B1;       /*!< [0x0044] IFn Data B1 Register                                             */
+    __IO uint32_t DAT_B2;       /*!< [0x0048] IFn Data B2 Register                                             */
+    __I uint32_t RESERVE0[13];
+} CAN_IF_T;
+
+typedef struct
+{
+    __IO uint32_t CON;                   /*!< [0x0000] Control Register                                                 */
+    __IO uint32_t STATUS;                /*!< [0x0004] Status Register                                                  */
+    __I  uint32_t ERR;                   /*!< [0x0008] Error Counter Register                                           */
+    __IO uint32_t BTIME;                 /*!< [0x000c] Bit Timing Register                                              */
+    __I  uint32_t IIDR;                  /*!< [0x0010] Interrupt Identifier Register                                    */
+    __IO uint32_t TEST;                  /*!< [0x0014] Test Register                                                    */
+    __IO uint32_t BRPE;                  /*!< [0x0018] Baud Rate Prescaler Extension Register                           */
+    __I  uint32_t RESERVE0[1];
+    __IO CAN_IF_T IF[2];
+    __I  uint32_t RESERVE2[8];
+    __I  uint32_t TXREQ1;                /*!< [0x0100] Transmission Request Register 1                                  */
+    __I  uint32_t TXREQ2;                /*!< [0x0104] Transmission Request Register 2                                  */
+    __I  uint32_t RESERVE3[6];
+    __I  uint32_t NDAT1;                 /*!< [0x0120] New Data Register 1                                              */
+    __I  uint32_t NDAT2;                 /*!< [0x0124] New Data Register 2                                              */
+    __I  uint32_t RESERVE4[6];
+    __I  uint32_t IPND1;                 /*!< [0x0140] Interrupt Pending Register 1                                     */
+    __I  uint32_t IPND2;                 /*!< [0x0144] Interrupt Pending Register 2                                     */
+    __I  uint32_t RESERVE5[6];
+    __I  uint32_t MVLD1;                 /*!< [0x0160] Message Valid Register 1                                         */
+    __I  uint32_t MVLD2;                 /*!< [0x0164] Message Valid Register 2                                         */
+    __IO uint32_t WU_EN;                 /*!< [0x0168] Wake-up Enable Control Register                                  */
+    __IO uint32_t WU_STATUS;             /*!< [0x016c] Wake-up Status Register                                          */
+
+} CAN_T;
+
+
+
+
+#define CAN_CON_INIT_Pos                 (0)                                               /*!< CAN_T::CON: Init Position              */
+#define CAN_CON_INIT_Msk                 (0x1ul << CAN_CON_INIT_Pos)                       /*!< CAN_T::CON: Init Mask                  */
+
+#define CAN_CON_IE_Pos                   (1)                                               /*!< CAN_T::CON: IE Position                */
+#define CAN_CON_IE_Msk                   (0x1ul << CAN_CON_IE_Pos)                         /*!< CAN_T::CON: IE Mask                    */
+
+#define CAN_CON_SIE_Pos                  (2)                                               /*!< CAN_T::CON: SIE Position               */
+#define CAN_CON_SIE_Msk                  (0x1ul << CAN_CON_SIE_Pos)                        /*!< CAN_T::CON: SIE Mask                   */
+
+#define CAN_CON_EIE_Pos                  (3)                                               /*!< CAN_T::CON: EIE Position               */
+#define CAN_CON_EIE_Msk                  (0x1ul << CAN_CON_EIE_Pos)                        /*!< CAN_T::CON: EIE Mask                   */
+
+#define CAN_CON_DAR_Pos                  (5)                                               /*!< CAN_T::CON: DAR Position               */
+#define CAN_CON_DAR_Msk                  (0x1ul << CAN_CON_DAR_Pos)                        /*!< CAN_T::CON: DAR Mask                   */
+
+#define CAN_CON_CCE_Pos                  (6)                                               /*!< CAN_T::CON: CCE Position               */
+#define CAN_CON_CCE_Msk                  (0x1ul << CAN_CON_CCE_Pos)                        /*!< CAN_T::CON: CCE Mask                   */
+
+#define CAN_CON_TEST_Pos                 (7)                                               /*!< CAN_T::CON: Test Position              */
+#define CAN_CON_TEST_Msk                 (0x1ul << CAN_CON_TEST_Pos)                       /*!< CAN_T::CON: Test Mask                  */
+
+#define CAN_STATUS_LEC_Pos               (0)                                               /*!< CAN_T::STATUS: LEC Position            */
+#define CAN_STATUS_LEC_Msk               (0x7ul << CAN_STATUS_LEC_Pos)                     /*!< CAN_T::STATUS: LEC Mask                */
+
+#define CAN_STATUS_TXOK_Pos              (3)                                               /*!< CAN_T::STATUS: TxOK Position           */
+#define CAN_STATUS_TXOK_Msk              (0x1ul << CAN_STATUS_TXOK_Pos)                    /*!< CAN_T::STATUS: TxOK Mask               */
+
+#define CAN_STATUS_RXOK_Pos              (4)                                               /*!< CAN_T::STATUS: RxOK Position           */
+#define CAN_STATUS_RXOK_Msk              (0x1ul << CAN_STATUS_RXOK_Pos)                    /*!< CAN_T::STATUS: RxOK Mask               */
+
+#define CAN_STATUS_EPASS_Pos             (5)                                               /*!< CAN_T::STATUS: EPass Position          */
+#define CAN_STATUS_EPASS_Msk             (0x1ul << CAN_STATUS_EPASS_Pos)                   /*!< CAN_T::STATUS: EPass Mask              */
+
+#define CAN_STATUS_EWARN_Pos             (6)                                               /*!< CAN_T::STATUS: EWarn Position          */
+#define CAN_STATUS_EWARN_Msk             (0x1ul << CAN_STATUS_EWARN_Pos)                   /*!< CAN_T::STATUS: EWarn Mask              */
+
+#define CAN_STATUS_BOFF_Pos              (7)                                               /*!< CAN_T::STATUS: BOff Position           */
+#define CAN_STATUS_BOFF_Msk              (0x1ul << CAN_STATUS_BOFF_Pos)                    /*!< CAN_T::STATUS: BOff Mask               */
+
+#define CAN_ERR_TEC_Pos                  (0)                                               /*!< CAN_T::ERR: TEC Position               */
+#define CAN_ERR_TEC_Msk                  (0xfful << CAN_ERR_TEC_Pos)                       /*!< CAN_T::ERR: TEC Mask                   */
+
+#define CAN_ERR_REC_Pos                  (8)                                               /*!< CAN_T::ERR: REC Position               */
+#define CAN_ERR_REC_Msk                  (0x7ful << CAN_ERR_REC_Pos)                       /*!< CAN_T::ERR: REC Mask                   */
+
+#define CAN_ERR_RP_Pos                   (15)                                              /*!< CAN_T::ERR: RP Position                */
+#define CAN_ERR_RP_Msk                   (0x1ul << CAN_ERR_RP_Pos)                         /*!< CAN_T::ERR: RP Mask                    */
+
+#define CAN_BTIME_BRP_Pos                (0)                                               /*!< CAN_T::BTIME: BRP Position             */
+#define CAN_BTIME_BRP_Msk                (0x3ful << CAN_BTIME_BRP_Pos)                     /*!< CAN_T::BTIME: BRP Mask                 */
+
+#define CAN_BTIME_SJW_Pos                (6)                                               /*!< CAN_T::BTIME: SJW Position             */
+#define CAN_BTIME_SJW_Msk                (0x3ul << CAN_BTIME_SJW_Pos)                      /*!< CAN_T::BTIME: SJW Mask                 */
+
+#define CAN_BTIME_TSEG1_Pos              (8)                                               /*!< CAN_T::BTIME: TSeg1 Position           */
+#define CAN_BTIME_TSEG1_Msk              (0xful << CAN_BTIME_TSEG1_Pos)                    /*!< CAN_T::BTIME: TSeg1 Mask               */
+
+#define CAN_BTIME_TSEG2_Pos              (12)                                              /*!< CAN_T::BTIME: TSeg2 Position           */
+#define CAN_BTIME_TSEG2_Msk              (0x7ul << CAN_BTIME_TSEG2_Pos)                    /*!< CAN_T::BTIME: TSeg2 Mask               */
+
+#define CAN_IIDR_IntId_Pos               (0)                                               /*!< CAN_T::IIDR: IntId Position            */
+#define CAN_IIDR_IntId_Msk               (0xfffful << CAN_IIDR_IntId_Pos)                  /*!< CAN_T::IIDR: IntId Mask                */
+
+#define CAN_TEST_BASIC_Pos               (2)                                               /*!< CAN_T::TEST: Basic Position            */
+#define CAN_TEST_BASIC_Msk               (0x1ul << CAN_TEST_BASIC_Pos)                     /*!< CAN_T::TEST: Basic Mask                */
+
+#define CAN_TEST_SILENT_Pos              (3)                                               /*!< CAN_T::TEST: Silent Position           */
+#define CAN_TEST_SILENT_Msk              (0x1ul << CAN_TEST_SILENT_Pos)                    /*!< CAN_T::TEST: Silent Mask               */
+
+#define CAN_TEST_LBACK_Pos               (4)                                               /*!< CAN_T::TEST: LBack Position            */
+#define CAN_TEST_LBACK_Msk               (0x1ul << CAN_TEST_LBACK_Pos)                     /*!< CAN_T::TEST: LBack Mask                */
+
+#define CAN_TEST_Tx_Pos                  (5)                                               /*!< CAN_T::TEST: Tx Position               */
+#define CAN_TEST_Tx_Msk                  (0x3ul << CAN_TEST_Tx_Pos)                        /*!< CAN_T::TEST: Tx Mask                   */
+
+#define CAN_TEST_Rx_Pos                  (7)                                               /*!< CAN_T::TEST: Rx Position               */
+#define CAN_TEST_Rx_Msk                  (0x1ul << CAN_TEST_Rx_Pos)                        /*!< CAN_T::TEST: Rx Mask                   */
+
+#define CAN_BRPE_BRPE_Pos                (0)                                               /*!< CAN_T::BRPE: BRPE Position             */
+#define CAN_BRPE_BRPE_Msk                (0xful << CAN_BRPE_BRPE_Pos)                      /*!< CAN_T::BRPE: BRPE Mask                 */
+
+#define CAN_IF_CREQ_MSGNUM_Pos           (0)                                               /*!< CAN_IF_T::CREQ: MessageNumber Position*/
+#define CAN_IF_CREQ_MSGNUM_Msk           (0x3ful << CAN_IF_CREQ_MSGNUM_Pos)                /*!< CAN_IF_T::CREQ: MessageNumber Mask    */
+
+#define CAN_IF_CREQ_BUSY_Pos             (15)                                              /*!< CAN_IF_T::CREQ: Busy Position         */
+#define CAN_IF_CREQ_BUSY_Msk             (0x1ul << CAN_IF_CREQ_BUSY_Pos)                   /*!< CAN_IF_T::CREQ: Busy Mask             */
+
+#define CAN_IF_CMASK_DATAB_Pos           (0)                                               /*!< CAN_IF_T::CMASK: DAT_B Position       */
+#define CAN_IF_CMASK_DATAB_Msk           (0x1ul << CAN_IF_CMASK_DATAB_Pos)                 /*!< CAN_IF_T::CMASK: DAT_B Mask           */
+
+#define CAN_IF_CMASK_DATAA_Pos           (1)                                               /*!< CAN_IF_T::CMASK: DAT_A Position       */
+#define CAN_IF_CMASK_DATAA_Msk           (0x1ul << CAN_IF_CMASK_DATAA_Pos)                 /*!< CAN_IF_T::CMASK: DAT_A Mask           */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos    (2)                                               /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk    (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)          /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask   */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos       (3)                                               /*!< CAN_IF_T::CMASK: ClrIntPnd Position   */
+#define CAN_IF_CMASK_CLRINTPND_Msk       (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos)             /*!< CAN_IF_T::CMASK: ClrIntPnd Mask       */
+
+#define CAN_IF_CMASK_CONTROL_Pos         (4)                                               /*!< CAN_IF_T::CMASK: Control Position     */
+#define CAN_IF_CMASK_CONTROL_Msk         (0x1ul << CAN_IF_CMASK_CONTROL_Pos)               /*!< CAN_IF_T::CMASK: Control Mask         */
+
+#define CAN_IF_CMASK_ARB_Pos             (5)                                               /*!< CAN_IF_T::CMASK: Arb Position         */
+#define CAN_IF_CMASK_ARB_Msk             (0x1ul << CAN_IF_CMASK_ARB_Pos)                   /*!< CAN_IF_T::CMASK: Arb Mask             */
+
+#define CAN_IF_CMASK_MASK_Pos           (6)                                               /*!< CAN_IF_T::CMASK: Mask Position        */
+#define CAN_IF_CMASK_MASK_Msk           (0x1ul << CAN_IF_CMASK_MASK_Pos)                 /*!< CAN_IF_T::CMASK: Mask Mask            */
+
+#define CAN_IF_CMASK_WRRD_Pos           (7)                                               /*!< CAN_IF_T::CMASK: WR_RD Position       */
+#define CAN_IF_CMASK_WRRD_Msk           (0x1ul << CAN_IF_CMASK_WRRD_Pos)                /*!< CAN_IF_T::CMASK: WR_RD Mask           */
+
+#define CAN_IF_MASK1_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK1: Msk Position         */
+#define CAN_IF_MASK1_Msk_Msk            (0xfffful << CAN_IF_MASK1_Msk_Pos)               /*!< CAN_IF_T::MASK1: Msk Mask             */
+
+#define CAN_IF_MASK2_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK2: Msk Position         */
+#define CAN_IF_MASK2_Msk_Msk            (0x1ffful << CAN_IF_MASK2_Msk_Pos)               /*!< CAN_IF_T::MASK2: Msk Mask             */
+
+#define CAN_IF_MASK2_MDIR_Pos           (14)                                              /*!< CAN_IF_T::MASK2: MDir Position        */
+#define CAN_IF_MASK2_MDIR_Msk           (0x1ul << CAN_IF_MASK2_MDIR_Pos)                 /*!< CAN_IF_T::MASK2: MDir Mask            */
+
+#define CAN_IF_MASK2_MXTD_Pos           (15)                                              /*!< CAN_IF_T::MASK2: MXtd Position        */
+#define CAN_IF_MASK2_MXTD_Msk           (0x1ul << CAN_IF_MASK2_MXTD_Pos)                 /*!< CAN_IF_T::MASK2: MXtd Mask            */
+
+#define CAN_IF_ARB1_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB1: ID Position           */
+#define CAN_IF_ARB1_ID_Msk              (0xfffful << CAN_IF_ARB1_ID_Pos)                 /*!< CAN_IF_T::ARB1: ID Mask               */
+
+#define CAN_IF_ARB2_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB2: ID Position           */
+#define CAN_IF_ARB2_ID_Msk              (0x1ffful << CAN_IF_ARB2_ID_Pos)                 /*!< CAN_IF_T::ARB2: ID Mask               */
+
+#define CAN_IF_ARB2_DIR_Pos             (13)                                              /*!< CAN_IF_T::ARB2: Dir Position          */
+#define CAN_IF_ARB2_DIR_Msk             (0x1ul << CAN_IF_ARB2_DIR_Pos)                   /*!< CAN_IF_T::ARB2: Dir Mask              */
+
+#define CAN_IF_ARB2_XTD_Pos             (14)                                              /*!< CAN_IF_T::ARB2: Xtd Position          */
+#define CAN_IF_ARB2_XTD_Msk             (0x1ul << CAN_IF_ARB2_XTD_Pos)                   /*!< CAN_IF_T::ARB2: Xtd Mask              */
+
+#define CAN_IF_ARB2_MSGVAL_Pos          (15)                                              /*!< CAN_IF_T::ARB2: MsgVal Position       */
+#define CAN_IF_ARB2_MSGVAL_Msk          (0x1ul << CAN_IF_ARB2_MSGVAL_Pos)                /*!< CAN_IF_T::ARB2: MsgVal Mask           */
+
+#define CAN_IF_MCON_DLC_Pos             (0)                                               /*!< CAN_IF_T::MCON: DLC Position          */
+#define CAN_IF_MCON_DLC_Msk             (0xful << CAN_IF_MCON_DLC_Pos)                   /*!< CAN_IF_T::MCON: DLC Mask              */
+
+#define CAN_IF_MCON_EOB_Pos             (7)                                               /*!< CAN_IF_T::MCON: EoB Position          */
+#define CAN_IF_MCON_EOB_Msk             (0x1ul << CAN_IF_MCON_EOB_Pos)                   /*!< CAN_IF_T::MCON: EoB Mask              */
+
+#define CAN_IF_MCON_TxRqst_Pos          (8)                                               /*!< CAN_IF_T::MCON: TxRqst Position       */
+#define CAN_IF_MCON_TxRqst_Msk          (0x1ul << CAN_IF_MCON_TxRqst_Pos)                /*!< CAN_IF_T::MCON: TxRqst Mask           */
+
+#define CAN_IF_MCON_RmtEn_Pos           (9)                                               /*!< CAN_IF_T::MCON: RmtEn Position        */
+#define CAN_IF_MCON_RmtEn_Msk           (0x1ul << CAN_IF_MCON_RmtEn_Pos)                 /*!< CAN_IF_T::MCON: RmtEn Mask            */
+
+#define CAN_IF_MCON_RXIE_Pos            (10)                                              /*!< CAN_IF_T::MCON: RxIE Position         */
+#define CAN_IF_MCON_RXIE_Msk            (0x1ul << CAN_IF_MCON_RXIE_Pos)                  /*!< CAN_IF_T::MCON: RxIE Mask             */
+
+#define CAN_IF_MCON_TXIE_Pos            (11)                                              /*!< CAN_IF_T::MCON: TxIE Position         */
+#define CAN_IF_MCON_TXIE_Msk            (0x1ul << CAN_IF_MCON_TXIE_Pos)                  /*!< CAN_IF_T::MCON: TxIE Mask             */
+
+#define CAN_IF_MCON_UMASK_Pos           (12)                                              /*!< CAN_IF_T::MCON: UMask Position        */
+#define CAN_IF_MCON_UMASK_Msk           (0x1ul << CAN_IF_MCON_UMASK_Pos)                 /*!< CAN_IF_T::MCON: UMask Mask            */
+
+#define CAN_IF_MCON_IntPnd_Pos          (13)                                              /*!< CAN_IF_T::MCON: IntPnd Position       */
+#define CAN_IF_MCON_IntPnd_Msk          (0x1ul << CAN_IF_MCON_IntPnd_Pos)                /*!< CAN_IF_T::MCON: IntPnd Mask           */
+
+#define CAN_IF_MCON_MsgLst_Pos          (14)                                              /*!< CAN_IF_T::MCON: MsgLst Position       */
+#define CAN_IF_MCON_MsgLst_Msk          (0x1ul << CAN_IF_MCON_MsgLst_Pos)                /*!< CAN_IF_T::MCON: MsgLst Mask           */
+
+#define CAN_IF_MCON_NEWDAT_Pos          (15)                                              /*!< CAN_IF_T::MCON: NewDat Position       */
+#define CAN_IF_MCON_NEWDAT_Msk          (0x1ul << CAN_IF_MCON_NEWDAT_Pos)                 /*!< CAN_IF_T::MCON: NewDat Mask           */
+
+#define CAN_IF_DAT_A1_DATA0_Pos       (0)                                               /*!< CAN_IF_T::DAT_A1: Data_0_ Position    */
+#define CAN_IF_DAT_A1_DATA0_Msk       (0xfful << CAN_IF_DAT_A1_DATA0_Pos)            /*!< CAN_IF_T::DAT_A1: Data_0_ Mask        */
+
+#define CAN_IF_DAT_A1_DATA1_Pos       (8)                                               /*!< CAN_IF_T::DAT_A1: Data_1_ Position    */
+#define CAN_IF_DAT_A1_DATA1_Msk       (0xfful << CAN_IF_DAT_A1_DATA1_Pos)            /*!< CAN_IF_T::DAT_A1: Data_1_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA2_Pos       (0)                                               /*!< CAN_IF_T::DAT_A2: Data_2_ Position    */
+#define CAN_IF_DAT_A2_DATA2_Msk       (0xfful << CAN_IF_DAT_A2_DATA2_Pos)            /*!< CAN_IF_T::DAT_A2: Data_2_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA3_Pos       (8)                                               /*!< CAN_IF_T::DAT_A2: Data_3_ Position    */
+#define CAN_IF_DAT_A2_DATA3_Msk       (0xfful << CAN_IF_DAT_A2_DATA3_Pos)            /*!< CAN_IF_T::DAT_A2: Data_3_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA4_Pos       (0)                                               /*!< CAN_IF_T::DAT_B1: Data_4_ Position    */
+#define CAN_IF_DAT_B1_DATA4_Msk       (0xfful << CAN_IF_DAT_B1_DATA4_Pos)            /*!< CAN_IF_T::DAT_B1: Data_4_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA5_Pos       (8)                                               /*!< CAN_IF_T::DAT_B1: Data_5_ Position    */
+#define CAN_IF_DAT_B1_DATA5_Msk       (0xfful << CAN_IF_DAT_B1_DATA5_Pos)            /*!< CAN_IF_T::DAT_B1: Data_5_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA6_Pos       (0)                                               /*!< CAN_IF_T::DAT_B2: Data_6_ Position    */
+#define CAN_IF_DAT_B2_DATA6_Msk       (0xfful << CAN_IF_DAT_B2_DATA6_Pos)            /*!< CAN_IF_T::DAT_B2: Data_6_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA7_Pos       (8)                                               /*!< CAN_IF_T::DAT_B2: Data_7_ Position    */
+#define CAN_IF_DAT_B2_DATA7_Msk       (0xfful << CAN_IF_DAT_B2_DATA7_Pos)            /*!< CAN_IF_T::DAT_B2: Data_7_ Mask        */
+
+#define CAN_TXREQ1_TXRQST16_1_Pos        (0)                                               /*!< CAN_T::TXREQ1: TxRqst16_1 Position     */
+#define CAN_TXREQ1_TXRQST16_1_Msk        (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos)           /*!< CAN_T::TXREQ1: TxRqst16_1 Mask         */
+
+#define CAN_TXREQ2_TXRQST32_17_Pos       (0)                                               /*!< CAN_T::TXREQ2: TxRqst32_17 Position    */
+#define CAN_TXREQ2_TXRQST32_17_Msk       (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos)          /*!< CAN_T::TXREQ2: TxRqst32_17 Mask        */
+
+#define CAN_NDAT1_NewData16_1_Pos        (0)                                               /*!< CAN_T::NDAT1: NewData16_1 Position     */
+#define CAN_NDAT1_NewData16_1_Msk        (0xfffful << CAN_NDAT1_NewData16_1_Pos)           /*!< CAN_T::NDAT1: NewData16_1 Mask         */
+
+#define CAN_NDAT2_NewData32_17_Pos       (0)                                               /*!< CAN_T::NDAT2: NewData32_17 Position    */
+#define CAN_NDAT2_NewData32_17_Msk       (0xfffful << CAN_NDAT2_NewData32_17_Pos)          /*!< CAN_T::NDAT2: NewData32_17 Mask        */
+
+#define CAN_IPND1_IntPnd16_1_Pos         (0)                                               /*!< CAN_T::IPND1: IntPnd16_1 Position      */
+#define CAN_IPND1_IntPnd16_1_Msk         (0xfffful << CAN_IPND1_IntPnd16_1_Pos)            /*!< CAN_T::IPND1: IntPnd16_1 Mask          */
+
+#define CAN_IPND2_IntPnd32_17_Pos        (0)                                               /*!< CAN_T::IPND2: IntPnd32_17 Position     */
+#define CAN_IPND2_IntPnd32_17_Msk        (0xfffful << CAN_IPND2_IntPnd32_17_Pos)           /*!< CAN_T::IPND2: IntPnd32_17 Mask         */
+
+#define CAN_MVLD1_MsgVal16_1_Pos         (0)                                               /*!< CAN_T::MVLD1: MsgVal16_1 Position      */
+#define CAN_MVLD1_MsgVal16_1_Msk         (0xfffful << CAN_MVLD1_MsgVal16_1_Pos)            /*!< CAN_T::MVLD1: MsgVal16_1 Mask          */
+
+#define CAN_MVLD2_MsgVal32_17_Pos        (0)                                               /*!< CAN_T::MVLD2: MsgVal32_17 Position     */
+#define CAN_MVLD2_MsgVal32_17_Msk        (0xfffful << CAN_MVLD2_MsgVal32_17_Pos)           /*!< CAN_T::MVLD2: MsgVal32_17 Mask         */
+
+#define CAN_WU_EN_WAKUP_EN_Pos           (0)                                               /*!< CAN_T::WU_EN: WAKUP_EN Position        */
+#define CAN_WU_EN_WAKUP_EN_Msk           (0x1ul << CAN_WU_EN_WAKUP_EN_Pos)                 /*!< CAN_T::WU_EN: WAKUP_EN Mask            */
+
+#define CAN_WU_STATUS_WAKUP_STS_Pos      (0)                                               /*!< CAN_T::WU_STATUS: WAKUP_STS Position   */
+#define CAN_WU_STATUS_WAKUP_STS_Msk      (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos)            /*!< CAN_T::WU_STATUS: WAKUP_STS Mask       */
+
+#define CAN0                 ((CAN_T *)   CAN0_BA)
+#define CAN1                 ((CAN_T *)   CAN1_BA)
+
+/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
+  @{
+*/
+/**
+  * @details    CAN message structure
+  */
+typedef struct
+{
+    uint32_t  IdType;       /*!< ID type */
+    uint32_t  FrameType;    /*!< Frame type */
+    uint32_t  Id;           /*!< Message ID */
+    uint8_t   DLC;          /*!< Data length */
+    uint8_t   Data[8];      /*!< Data */
+} STR_CANMSG_T;
+
+/**
+  * @details    CAN mask message structure
+  */
+typedef struct
+{
+    uint8_t   u8Xtd;      /*!< Extended ID */
+    uint8_t   u8Dir;      /*!< Direction */
+    uint32_t  u32Id;      /*!< Message ID */
+    uint8_t   u8IdType;   /*!< ID type*/
+} STR_CANMASK_T;
+
+/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */
+
+/** @cond HIDDEN_SYMBOLS */
+#define MSG(id)  (id)
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ *          EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ *          with the highest priority, disregarding their chronological order.
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details  The macro is used to disable wake-up function.
+ * \hideinitializer
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * \hideinitializer
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ *          or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ * \hideinitializer
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg);
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
+void CAN_WaitMsg(CAN_T *tCAN);
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T *pCanMsg);
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+
+#endif /*__NU_CAN_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_cap.h

@@ -0,0 +1,316 @@
+/**************************************************************************//**
+* @file     cap.h
+* @version  V1.00
+* $Revision: 2 $
+* $Date: 15/06/12 8:48a $
+* @brief    N9H30 CAP driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_CAP_H__
+#define __NU_CAP_H__
+
+// #include header file
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CAP_Driver CAP Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CAP_EXPORTED_CONSTANTS CAP Exported Constants
+  @{
+*/
+
+/* Define data type (struct, union? */
+// #define Constant
+#include "N9H30.h"
+#include "nu_sys.h"
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_CTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAPEN     BIT0          /*!< Interrupt enable for VPE operations */
+#define ADDRSW    BIT3          /*!< Packet Buffer Address Switch */
+#define PLNEN     BIT5          /*!< Planar Output Enable */
+#define PKTEN     BIT6          /*!< Packet Output Enable */
+#define SHUTTER   BIT16         /*!< Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured */
+#define UPDATE    BIT20         /*!< Update Register At New Frame */
+#define VPRST     BIT24         /*!< Capture Interface Reset */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_PAR constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define INFMT     BIT0          /*!< Sensor Input Data Format */
+#define SENTYPE   BIT1          /*!< Sensor Input Type */
+#define INDATORD  (BIT2|BIT3)   /*!< Sensor Input Data Order */
+#define OUTFMT    (BIT4|BIT5)   /*!< Image Data Format Output To System Memory */
+#define RANGE     BIT6          /*!< Scale Input YUV CCIR601 Color Range To Full Range */
+#define PLNFMT    BIT7          /*!< Planar Output YUV Format */
+#define PCLKP     BIT8          /*!< Sensor Pixel Clock Polarity */
+#define HSP       BIT9          /*!< Sensor Hsync Polarity */
+#define VSP       BIT10         /*!< Sensor Vsync Polarity */
+#define COLORCTL  (BIT11|BIT12) /*!< Special COLORCTL Processing */
+#define FBB       BIT18         /*!< Field By Blank */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_INT constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define MDIEN       BIT20         /*!< Motion Detection Output Finish Interrupt Enable */
+#define ADDRMIEN    BIT19         /*!< Address Match Interrupt Enable */
+#define MEIEN       BIT17         /*!< System Memory Error Interrupt Enable */
+#define VIEN        BIT16         /*!< Video Frame End Interrupt Enable */
+#define MDINTF      BIT4          /*!< Motion Detection Output Finish Interrupt */
+#define ADDRMINTF   BIT3          /*!< Memory Address Match Interrupt */
+#define MEINTF      BIT1          /*!< Bus Master Transfer Error Interrupt */
+#define VINTF       BIT0          /*!< Video Frame End Interrupt */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_MD constant definitions                                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define MDEN        BIT0          /*!< Motion Detection Enable */
+#define MDBS        BIT8          /*!< Motion Detection Block Size */
+#define MDSM        BIT9          /*!< Motion Detection Save Mode */
+#define MDDF        (BIT10|BIT11) /*!< Motion Detection Detect Frequency */
+#define MDTHR       (BIT16|BIT17|BIT18|BIT19|BIT20) /*!< Motion Detection Differential Threshold */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_CWSP constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CWSADDRH    (0xFFF<<0)    /*!<Cropping Window Horizontal Starting Address */
+#define CWSADDRV    (0xFFF<<16)   /*!<Cropping Window Vertical Starting Address */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_CWS constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CWW   (0xFFF<<0)    /*!< Cropping Window Horizontal Starting Address */
+#define CWH   (0xFFF<<16)   /*!< Cropping Window Vertical Starting Address */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_PKTSL constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PKTSHML   (0xFFul<< 0) /*!< Packet Scaling Horizontal Factor M (Lower 8-Bit) */
+#define PKTSHNL   (0xFFul<< 8) /*!< Packet Scaling Horizontal Factor N (Lower 8-Bit) */
+#define PKTSVML   (0xFFul<<16) /*!< Packet Scaling Vertical Factor M (Lower 8-Bit) */
+#define PKTSVNL   (0xFFul<<24) /*!< Packet Scaling Vertical Factor N (Lower 8-Bit) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_PLNSL constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PLNSHML   (0xFFul<< 0) /*!< Planar Scaling Horizontal Factor M (Lower 8-Bit) */
+#define PLNSHNL   (0xFFul<< 8) /*!< Planar Scaling Horizontal Factor N (Lower 8-Bit) */
+#define PLNSVML   (0xFFul<<16) /*!< Planar Scaling Vertical Factor M (Lower 8-Bit) */
+#define PLNSVNL   (0xFFul<<24) /*!< Planar Scaling Vertical Factor N (Lower 8-Bit) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_PKTSM constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PKTSHMH   (0xFFul<< 0) /*!< Packet Scaling Horizontal Factor M (Higher 8-Bit) */
+#define PKTSHNH   (0xFFul<< 8) /*!< Packet Scaling Horizontal Factor N (Higher 8-Bit) */
+#define PKTSVMH   (0xFFul<<16) /*!< Packet Scaling Vertical Factor M (Higher 8-Bit) */
+#define PKTSVNH   (0xFFul<<24) /*!< Packet Scaling Vertical Factor N (Higher 8-Bit) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_PLNSM constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PLNSHMH   (0xFFul<< 0) /*!< Planar Scaling Horizontal Factor M (Higher 8-Bit) */
+#define PLNSHNH   (0xFFul<< 8) /*!< Planar Scaling Horizontal Factor N (Higher 8-Bit) */
+#define PLNSVMH   (0xFFul<<16) /*!< Planar Scaling Vertical Factor M (Higher 8-Bit) */
+#define PLNSVNH   (0xFFul<<24) /*!< Planar Scaling Vertical Factor N (Higher 8-Bit) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_FRCTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FRM   (0x3Ful<<0)  /*!< Scaling Frame Rate Factor M */
+#define FRN   (0x3Ful<<8)  /*!< Scaling Frame Rate Factor N */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAP_STRIDE constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PKTSTRIDE       (0x3FFFul<<0)   /*!< Packet Frame Output Pixel Stride Width */
+#define PLNSTRIDE       (0x3FFFul<<16)  /*!< Planar Frame Output Pixel Stride Width */
+
+#define VIN_ERR_ID      0xFFFF1000  /*!< CAP library ID */
+
+//Error message
+// E_CAP_INVALID_INT            Invalid interrupt
+// E_CAP_INVALID_BUF            Invalid buffer
+// E_CAP_INVALID_PIPE           Invalid pipe
+// E_CAP_INVALID_COLOR_MODE     Invalid color mode
+
+#define E_CAP_INVALID_INT             (VIN_ERR_ID | 0x01) /*!< CAP invalid interrupt */
+#define E_CAP_INVALID_BUF             (VIN_ERR_ID | 0x02) /*!< CAP invalid buffer */
+#define E_CAP_INVALID_PIPE            (VIN_ERR_ID | 0x03) /*!< CAP invalid pipe */
+#define E_CAP_INVALID_COLOR_MODE      (VIN_ERR_ID | 0x04) /*!< CAP invalid color mode */
+#define E_CAP_WRONG_COLOR_PARAMETER   (VIN_ERR_ID | 0x05) /*!< CAP worng color parameter */
+
+/// @cond HIDDEN_SYMBOLS
+typedef void (*PFN_CAP_CALLBACK)(UINT8 u8PacketBufID, UINT8 u8PlanarBufID, UINT8 u8FrameRate);
+/// @endcond HIDDEN_SYMBOLS
+
+/** \brief  Structure type of E_CAP_INT_TYPE
+ */
+typedef enum
+{
+    eCAP_MDINTF     = 0x100000,  /*!< Motion detection output finish interrupt */
+    eCAP_ADDRMINTF  = 0x80000,   /*!< Memory address match interrupt */
+    eCAP_MEINTF     = 0x20000,   /*!< Bus master transfer error interrupt */
+    eCAP_VINTF      = 0x10000    /*!< Video frame end interrupt */
+} E_CAP_INT_TYPE;
+
+
+/** \brief  Structure type of E_CAP_PIPE
+ */
+typedef enum
+{
+    eCAP_BOTH_PIPE_DISABLE  = 0,  /*!< Planar output disable and planar output disable */
+    eCAP_PLANAR             = 1,  /*!< Planar output enable */
+    eCAP_PACKET             = 2,  /*!< Packet output enable */
+    eCAP_BOTH_PIPE_ENABLE   = 3   /*!< Planar output enable and planar output enable */
+} E_CAP_PIPE;
+
+/** \brief  Structure type of E_CAP_BUFFER
+ */
+typedef enum
+{
+    eCAP_BUF0 = 0, /*!< System memory packet/planar base Address 0/Y */
+    eCAP_BUF1,     /*!< System memory packet/planar base Address 1/U */
+    eCAP_BUF2      /*!< System memory packet/planar base Address 2/V */
+} E_CAP_BUFFER;
+
+
+/** \brief  Structure type of E_CAP_ORDER
+ */
+typedef enum
+{
+    eCAP_IN_YUYV = 0, /*!< Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0 */
+    eCAP_IN_YVYU,   /*!< Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0 */
+    eCAP_IN_UYVY,   /*!< Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1 */
+    eCAP_IN_VYUY,   /*!< Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1 */
+} E_CAP_ORDER;
+
+/** \brief  Structure type of E_CAP_IN_FORMAT
+ */
+typedef enum
+{
+    eCAP_IN_YUV422 = 0, /*!< Sensor input data format is YUV222 */
+    eCAP_IN_RGB565      /*!< Sensor input data format is RGB565 */
+} E_CAP_IN_FORMAT;
+
+/** \brief  Structure type of E_CAP_OUT_FORMAT
+ */
+typedef enum
+{
+    eCAP_OUT_YUV422 = 0,  /*!< Image data format is YUV422 */
+    eCAP_OUT_ONLY_Y,      /*!< Image data format is Only output Y */
+    eCAP_OUT_RGB555,      /*!< Image data format is RGB555 */
+    eCAP_OUT_RGB565       /*!< Image data format is RGB565 */
+} E_CAP_OUT_FORMAT;
+
+/** \brief  Structure type of E_CAP_PLANAR_FORMAT
+ */
+typedef enum
+{
+    eCAP_PLANAR_YUV422 = 0, /*!< Planar output YUV format is YUV422 */
+    eCAP_PLANAR_YUV420,     /*!< Planar output YUV format is YUV420 */
+} E_CAP_PLANAR_FORMAT;
+
+/** \brief  Structure type of E_CAP_TYPE
+ */
+typedef enum
+{
+    eCAP_TYPE_CCIR601 = 0,  /*!< Sensor input type is CCIR601 */
+    eCAP_TYPE_CCIR656       /*!< Sensor input type is CCIR656 */
+} E_CAP_TYPE;
+
+/** \brief  Structure type of E_CAP_SNR_SRC
+ */
+typedef enum
+{
+    eCAP_SNR_APLL = 2,   /*!< CAP clock source is APLL */
+    eCAP_SNR_UPLL = 3    /*!< CAP clock source is UPLL */
+} E_CAP_SNR_SRC;
+
+/** \brief  Structure type of E_CAP_CEF
+ */
+typedef enum
+{
+    eCAP_CEF_NORMAL       = 0,  /*!< Image Processing is normal color */
+    eCAP_CEF_SEPIA        = 1,  /*!< Image Processing is sepia effect */
+    eCAP_CEF_NEGATIVE     = 2,  /*!< Image Processing is negative picture. */
+    eCAP_CEF_POSTERIZE    = 3   /*!< Image Processing is posterize image */
+} E_CAP_CEF;
+
+/*@}*/ /* end of group N9H30_CAP_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_CAP_EXPORTED_FUNCTIONS CAP Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+typedef struct
+{
+    void (*Init)(BOOL bIsEnableSnrClock, E_CAP_SNR_SRC eSnrSrc, UINT32 u32SensorFreqKHz);
+    INT32(*Open)(UINT32 u32SensorFreqKHz);
+    void (*Close)(void);
+    void (*SetPipeEnable)(BOOL bEngEnable, E_CAP_PIPE ePipeEnable);
+    void (*SetPlanarFormat)(E_CAP_PLANAR_FORMAT ePlanarFmt);
+    void (*SetCropWinSize)(UINT32 u32height, UINT32 u32width);
+    void (*SetCropWinStartAddr)(UINT32 u32VerticalStart, UINT32 u32HorizontalStart);
+    void (*SetStride)(UINT32 u16packetstride, UINT32 u32planarstride);
+    void (*GetStride)(PUINT32 pu32PacketStride, PUINT32 pu32PlanarStride);
+    INT32(*EnableInt)(E_CAP_INT_TYPE eIntType);
+    INT32(*DisableInt)(E_CAP_INT_TYPE eIntType);
+    INT32(*InstallCallback)(E_CAP_INT_TYPE eIntType, PFN_CAP_CALLBACK pfnCallback, PFN_CAP_CALLBACK *pfnOldCallback);
+    INT32(*SetBaseStartAddress)(E_CAP_PIPE ePipe, E_CAP_BUFFER eBuf, UINT32 u32BaseStartAddr);
+    void (*SetOperationMode)(BOOL bIsOneSutterMode);
+    BOOL (*GetOperationMode)(void);
+    void (*SetPacketFrameBufferControl)(BOOL bFrameSwitch);
+    void (*SetSensorPolarity)(BOOL bVsync, BOOL bHsync, BOOL bPixelClk);
+    INT32(*SetColorEffectParameter)(UINT8 u8YComp, UINT8 u8UComp, UINT8 u8VComp);
+    void (*SetDataFormatAndOrder)(E_CAP_ORDER eInputOrder, E_CAP_IN_FORMAT eInputFormat, E_CAP_OUT_FORMAT eOutputFormat);
+    void (*SetMotionDet)(BOOL bEnable, BOOL bBlockSize, BOOL bSaveMode);
+    void (*SetMotionDetEx)(UINT32 u32DetFreq, UINT32 u32Threshold, UINT32 u32OutBuffer, UINT32 u32LumBuffer);
+    void (*SetStandardCCIR656)(BOOL);
+    void (*SetShadowRegister)(void);
+} CAPDEV_T;
+/// @endcond HIDDEN_SYMBOLS
+
+/*@}*/ /* end of group N9H30_CAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_CAP_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_crypto.h

@@ -0,0 +1,689 @@
+/**************************************************************************//**
+ * @file     crypto.h
+ * @version  V1.10
+ * $Revision: 2 $
+ * $Date: 15/05/06 3:55p $
+ * @brief    Cryptographic Accelerator driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CRYPTO_H__
+#define __NU_CRYPTO_H__
+
+#include "N9H30.h"
+#include "nu_sys.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+typedef struct
+{
+    __IO uint32_t INTEN;           /*!< Offset: 0x000:  Crypto Interrupt Enable Control Register      */
+    __IO uint32_t INTSTS;          /*!< Offset: 0x004:  Crypto Interrupt Flag                         */
+    __IO uint32_t PRNG_CTL;        /*!< Offset: 0x008:  PRNG Control Flag                             */
+    __IO uint32_t PRNG_SEED;       /*!< Offset: 0x00C:  PRNG Control Flag                             */
+    __I  uint32_t PRNG_KEY[8];     /*!< Offset: 0x010:  PRNG Generated Key0 - Key7                    */
+    uint32_t RESERVE0[8];
+    __I  uint32_t AES_FDBCK0;      /*!< Offset: 0x050:  AES Engine Output Feedback Data after Cryptographic Operation */
+    __I  uint32_t AES_FDBCK1;      /*!< Offset: 0x054:  AES Engine Output Feedback Data after Cryptographic Operation */
+    __I  uint32_t AES_FDBCK2;      /*!< Offset: 0x058:  AES Engine Output Feedback Data after Cryptographic Operation */
+    __I  uint32_t AES_FDBCK3;      /*!< Offset: 0x05C:  AES Engine Output Feedback Data after Cryptographic Operation */
+    __I  uint32_t TDES_FDBCKH;     /*!< Offset: 0x060:  TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
+    __I  uint32_t TDES_FDBCKL;     /*!< Offset: 0x064:  TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation  */
+    uint32_t RESERVE1[38];
+    __IO uint32_t AES_CTL;         /*!< Offset: 0x100:  AES Control Register                          */
+    __IO uint32_t AES_STS;         /*!< Offset: 0x104:  AES Engine Flag                               */
+    __IO uint32_t AES_DATIN;       /*!< Offset: 0x108:  AES Engine Data Input Port Register           */
+    __I  uint32_t AES_DATOUT;      /*!< Offset: 0x10C:  AES Engine Data Output Port Register          */
+    __IO uint32_t AES0_KEY0;       /*!< Offset: 0x110:  AES Key Word 0 Register for Channel 0         */
+    __IO uint32_t AES0_KEY1;       /*!< Offset: 0x114:  AES Key Word 1 Register for Channel 0         */
+    __IO uint32_t AES0_KEY2;       /*!< Offset: 0x118:  AES Key Word 2 Register for Channel 0         */
+    __IO uint32_t AES0_KEY3;       /*!< Offset: 0x11C:  AES Key Word 3 Register for Channel 0         */
+    __IO uint32_t AES0_KEY4;       /*!< Offset: 0x120:  AES Key Word 4 Register for Channel 0         */
+    __IO uint32_t AES0_KEY5;       /*!< Offset: 0x124:  AES Key Word 5 Register for Channel 0         */
+    __IO uint32_t AES0_KEY6;       /*!< Offset: 0x128:  AES Key Word 6 Register for Channel 0         */
+    __IO uint32_t AES0_KEY7;       /*!< Offset: 0x12C:  AES Key Word 7 Register for Channel 0         */
+    __IO uint32_t AES0_IV0;        /*!< Offset: 0x130:  AES Initial Vector Word 0 Register for Channel 0   */
+    __IO uint32_t AES0_IV1;        /*!< Offset: 0x134:  AES Initial Vector Word 1 Register for Channel 0   */
+    __IO uint32_t AES0_IV2;        /*!< Offset: 0x138:  AES Initial Vector Word 2 Register for Channel 0   */
+    __IO uint32_t AES0_IV3;        /*!< Offset: 0x13C:  AES Initial Vector Word 3 Register for Channel 0   */
+    __IO uint32_t AES0_SADDR;      /*!< Offset: 0x140:  AES DMA Source Address Register for Channel 0      */
+    __IO uint32_t AES0_DADDR;      /*!< Offset: 0x144:  AES DMA Destination Address Register for Channel 0 */
+    __IO uint32_t AES0_CNT;        /*!< Offset: 0x148:  AES Byte Count Register for Channel 0              */
+    __IO uint32_t AES1_KEY0;       /*!< Offset: 0x14C:  AES Key Word 0 Register for Channel 1         */
+    __IO uint32_t AES1_KEY1;       /*!< Offset: 0x150:  AES Key Word 1 Register for Channel 1         */
+    __IO uint32_t AES1_KEY2;       /*!< Offset: 0x154:  AES Key Word 2 Register for Channel 1         */
+    __IO uint32_t AES1_KEY3;       /*!< Offset: 0x158:  AES Key Word 3 Register for Channel 1         */
+    __IO uint32_t AES1_KEY4;       /*!< Offset: 0x15C:  AES Key Word 4 Register for Channel 1         */
+    __IO uint32_t AES1_KEY5;       /*!< Offset: 0x160:  AES Key Word 5 Register for Channel 1         */
+    __IO uint32_t AES1_KEY6;       /*!< Offset: 0x164:  AES Key Word 6 Register for Channel 1         */
+    __IO uint32_t AES1_KEY7;       /*!< Offset: 0x168:  AES Key Word 7 Register for Channel 1         */
+    __IO uint32_t AES1_IV0;        /*!< Offset: 0x16C:  AES Initial Vector Word 0 Register for Channel 1   */
+    __IO uint32_t AES1_IV1;        /*!< Offset: 0x170:  AES Initial Vector Word 1 Register for Channel 1   */
+    __IO uint32_t AES1_IV2;        /*!< Offset: 0x174:  AES Initial Vector Word 2 Register for Channel 1   */
+    __IO uint32_t AES1_IV3;        /*!< Offset: 0x178:  AES Initial Vector Word 3 Register for Channel 1   */
+    __IO uint32_t AES1_SADDR;      /*!< Offset: 0x17C:  AES DMA Source Address Register for Channel 1      */
+    __IO uint32_t AES1_DADDR;      /*!< Offset: 0x180:  AES DMA Destination Address Register for Channel 1 */
+    __IO uint32_t AES1_CNT;        /*!< Offset: 0x184:  AES Byte Count Register for Channel 1              */
+    __IO uint32_t AES2_KEY0;       /*!< Offset: 0x188:  AES Key Word 0 Register for Channel 2         */
+    __IO uint32_t AES2_KEY1;       /*!< Offset: 0x18C:  AES Key Word 1 Register for Channel 2         */
+    __IO uint32_t AES2_KEY2;       /*!< Offset: 0x190:  AES Key Word 2 Register for Channel 2         */
+    __IO uint32_t AES2_KEY3;       /*!< Offset: 0x194:  AES Key Word 3 Register for Channel 2         */
+    __IO uint32_t AES2_KEY4;       /*!< Offset: 0x198:  AES Key Word 4 Register for Channel 2         */
+    __IO uint32_t AES2_KEY5;       /*!< Offset: 0x19C:  AES Key Word 5 Register for Channel 2         */
+    __IO uint32_t AES2_KEY6;       /*!< Offset: 0x1A0:  AES Key Word 6 Register for Channel 2         */
+    __IO uint32_t AES2_KEY7;       /*!< Offset: 0x1A4:  AES Key Word 7 Register for Channel 2         */
+    __IO uint32_t AES2_IV0;        /*!< Offset: 0x1A8:  AES Initial Vector Word 0 Register for Channel 2   */
+    __IO uint32_t AES2_IV1;        /*!< Offset: 0x1AC:  AES Initial Vector Word 1 Register for Channel 2   */
+    __IO uint32_t AES2_IV2;        /*!< Offset: 0x1B0:  AES Initial Vector Word 2 Register for Channel 2   */
+    __IO uint32_t AES2_IV3;        /*!< Offset: 0x1B4:  AES Initial Vector Word 3 Register for Channel 2   */
+    __IO uint32_t AES2_SADDR;      /*!< Offset: 0x1B8:  AES DMA Source Address Register for Channel 2      */
+    __IO uint32_t AES2_DADDR;      /*!< Offset: 0x1BC:  AES DMA Destination Address Register for Channel 2 */
+    __IO uint32_t AES2_CNT;        /*!< Offset: 0x1C0:  AES Byte Count Register for Channel 2              */
+    __IO uint32_t AES3_KEY0;       /*!< Offset: 0x1C4:  AES Key Word 0 Register for Channel 3         */
+    __IO uint32_t AES3_KEY1;       /*!< Offset: 0x1C8:  AES Key Word 1 Register for Channel 3         */
+    __IO uint32_t AES3_KEY2;       /*!< Offset: 0x1CC:  AES Key Word 2 Register for Channel 3         */
+    __IO uint32_t AES3_KEY3;       /*!< Offset: 0x1D0:  AES Key Word 3 Register for Channel 3         */
+    __IO uint32_t AES3_KEY4;       /*!< Offset: 0x1D4:  AES Key Word 4 Register for Channel 3         */
+    __IO uint32_t AES3_KEY5;       /*!< Offset: 0x1D8:  AES Key Word 5 Register for Channel 3         */
+    __IO uint32_t AES3_KEY6;       /*!< Offset: 0x1DC:  AES Key Word 6 Register for Channel 3         */
+    __IO uint32_t AES3_KEY7;       /*!< Offset: 0x1E0:  AES Key Word 7 Register for Channel 3         */
+    __IO uint32_t AES3_IV0;        /*!< Offset: 0x1E4:  AES Initial Vector Word 0 Register for Channel 3   */
+    __IO uint32_t AES3_IV1;        /*!< Offset: 0x1E8:  AES Initial Vector Word 1 Register for Channel 3   */
+    __IO uint32_t AES3_IV2;        /*!< Offset: 0x1EC:  AES Initial Vector Word 2 Register for Channel 3   */
+    __IO uint32_t AES3_IV3;        /*!< Offset: 0x1F0:  AES Initial Vector Word 3 Register for Channel 3   */
+    __IO uint32_t AES3_SADDR;      /*!< Offset: 0x1F4:  AES DMA Source Address Register for Channel 3      */
+    __IO uint32_t AES3_DADDR;      /*!< Offset: 0x1F8:  AES DMA Destination Address Register for Channel 3 */
+    __IO uint32_t AES3_CNT;        /*!< Offset: 0x1FC:  AES Byte Count Register for Channel 3              */
+    __IO uint32_t TDES_CTL;        /*!< Offset: 0x200:  TDES/DES Control Register                     */
+    __IO uint32_t TDES_STS;        /*!< Offset: 0x204:  TDES/DES Engine Flag                          */
+    __IO uint32_t TDES0_KEY1H;     /*!< Offset: 0x208:  TDES/DES Key 1 High Word Register for Channel 0    */
+    __IO uint32_t TDES0_KEY1L;     /*!< Offset: 0x20C:  TDES/DES Key 1 Low Word Register for Channel 0     */
+    __IO uint32_t TDES0_KEY2H;     /*!< Offset: 0x210:  TDES/DES Key 2 High Word Register for Channel 0    */
+    __IO uint32_t TDES0_KEY2L;     /*!< Offset: 0x214:  TDES/DES Key 2 Low Word Register for Channel 0     */
+    __IO uint32_t TDES0_KEY3H;     /*!< Offset: 0x218:  TDES/DES Key 3 High Word Register for Channel 0    */
+    __IO uint32_t TDES0_KEY3L;     /*!< Offset: 0x21C:  TDES/DES Key 3 Low Word Register for Channel 0     */
+    __IO uint32_t TDES0_IVH;       /*!< Offset: 0x220:  TDES/DES Initial Vector High Word Register for Channel 0  */
+    __IO uint32_t TDES0_IVL;       /*!< Offset: 0x224:  TDES/DES Initial Vector Low Word Register for Channel 0   */
+    __IO uint32_t TDES0_SADDR;     /*!< Offset: 0x228:  TDES/DES DMA Source Address Register for Channel 0        */
+    __IO uint32_t TDES0_DADDR;     /*!< Offset: 0x22C:  TDES/DES DMA Destination Address Register for Channel 0   */
+    __IO uint32_t TDES0_CNT;       /*!< Offset: 0x230:  TDES/DES Byte Count Register for Channel 0    */
+    __IO uint32_t TDES_DATIN;      /*!< Offset: 0x234:  TDES/DES Engine Input data Word Register      */
+    __IO uint32_t TDES_DATOUT;     /*!< Offset: 0x238:  TDES/DES Engine Output data Word Register     */
+    uint32_t RESERVE2[3];
+    __IO uint32_t TDES1_KEY1H;     /*!< Offset: 0x248:  TDES/DES Key 1 High Word Register for Channel 1    */
+    __IO uint32_t TDES1_KEY1L;     /*!< Offset: 0x24C:  TDES/DES Key 1 Low Word Register for Channel 1     */
+    __IO uint32_t TDES1_KEY2H;     /*!< Offset: 0x250:  TDES/DES Key 2 High Word Register for Channel 1    */
+    __IO uint32_t TDES1_KEY2L;     /*!< Offset: 0x254:  TDES/DES Key 2 Low Word Register for Channel 1     */
+    __IO uint32_t TDES1_KEY3H;     /*!< Offset: 0x258:  TDES/DES Key 3 High Word Register for Channel 1    */
+    __IO uint32_t TDES1_KEY3L;     /*!< Offset: 0x25C:  TDES/DES Key 3 Low Word Register for Channel 1     */
+    __IO uint32_t TDES1_IVH;       /*!< Offset: 0x260:  TDES/DES Initial Vector High Word Register for Channel 1  */
+    __IO uint32_t TDES1_IVL;       /*!< Offset: 0x264:  TDES/DES Initial Vector Low Word Register for Channel 1   */
+    __IO uint32_t TDES1_SADDR;     /*!< Offset: 0x268:  TDES/DES DMA Source Address Register for Channel 1        */
+    __IO uint32_t TDES1_DADDR;     /*!< Offset: 0x26C:  TDES/DES DMA Destination Address Register for Channel 1   */
+    __IO uint32_t TDES1_CNT;       /*!< Offset: 0x270:  TDES/DES Byte Count Register for Channel 1    */
+    uint32_t RESERVE3[5];
+    __IO uint32_t TDES2_KEY1H;     /*!< Offset: 0x288:  TDES/DES Key 1 High Word Register for Channel 2    */
+    __IO uint32_t TDES2_KEY1L;     /*!< Offset: 0x28C:  TDES/DES Key 1 Low Word Register for Channel 2     */
+    __IO uint32_t TDES2_KEY2H;     /*!< Offset: 0x290:  TDES/DES Key 2 High Word Register for Channel 2    */
+    __IO uint32_t TDES2_KEY2L;     /*!< Offset: 0x294:  TDES/DES Key 2 Low Word Register for Channel 2     */
+    __IO uint32_t TDES2_KEY3H;     /*!< Offset: 0x298:  TDES/DES Key 3 High Word Register for Channel 2    */
+    __IO uint32_t TDES2_KEY3L;     /*!< Offset: 0x29C:  TDES/DES Key 3 Low Word Register for Channel 2     */
+    __IO uint32_t TDES2_IVH;       /*!< Offset: 0x2A0:  TDES/DES Initial Vector High Word Register for Channel 2  */
+    __IO uint32_t TDES2_IVL;       /*!< Offset: 0x2A4:  TDES/DES Initial Vector Low Word Register for Channel 2   */
+    __IO uint32_t TDES2_SADDR;     /*!< Offset: 0x2A8:  TDES/DES DMA Source Address Register for Channel 2        */
+    __IO uint32_t TDES2_DADDR;     /*!< Offset: 0x2AC:  TDES/DES DMA Destination Address Register for Channel 2   */
+    __IO uint32_t TDES2_CNT;       /*!< Offset: 0x2B0:  TDES/DES Byte Count Register for Channel 2    */
+    uint32_t RESERVE4[5];
+    __IO uint32_t TDES3_KEY1H;     /*!< Offset: 0x2C8:  TDES/DES Key 1 High Word Register for Channel 3    */
+    __IO uint32_t TDES3_KEY1L;     /*!< Offset: 0x2CC:  TDES/DES Key 1 Low Word Register for Channel 3     */
+    __IO uint32_t TDES3_KEY2H;     /*!< Offset: 0x2D0:  TDES/DES Key 2 High Word Register for Channel 3    */
+    __IO uint32_t TDES3_KEY2L;     /*!< Offset: 0x2D4:  TDES/DES Key 2 Low Word Register for Channel 3     */
+    __IO uint32_t TDES3_KEY3H;     /*!< Offset: 0x2D8:  TDES/DES Key 3 High Word Register for Channel 3    */
+    __IO uint32_t TDES3_KEY3L;     /*!< Offset: 0x2DC:  TDES/DES Key 3 Low Word Register for Channel 3     */
+    __IO uint32_t TDES3_IVH;       /*!< Offset: 0x2E0:  TDES/DES Initial Vector High Word Register for Channel 3  */
+    __IO uint32_t TDES3_IVL;       /*!< Offset: 0x2E4:  TDES/DES Initial Vector Low Word Register for Channel 3   */
+    __IO uint32_t TDES3_SADDR;     /*!< Offset: 0x2E8:  TDES/DES DMA Source Address Register for Channel 3        */
+    __IO uint32_t TDES3_DADDR;     /*!< Offset: 0x2EC:  TDES/DES DMA Destination Address Register for Channel 3   */
+    __IO uint32_t TDES3_CNT;       /*!< Offset: 0x2F0:  TDES/DES Byte Count Register for Channel 3    */
+    uint32_t RESERVE5[3];
+    __IO uint32_t HMAC_CTL;        /*!< Offset: 0x300:  SHA/HMAC Control Register                     */
+    __IO uint32_t HMAC_STS;        /*!< Offset: 0x304:  SHA/HMAC Status Register                      */
+    __IO uint32_t HMAC_DGST0;      /*!< Offset: 0x308:  SHA/HMAC Digest Message 0                     */
+    __IO uint32_t HMAC_DGST1;      /*!< Offset: 0x30C:  SHA/HMAC Digest Message 1                     */
+    __IO uint32_t HMAC_DGST2;      /*!< Offset: 0x310:  SHA/HMAC Digest Message 2                     */
+    __IO uint32_t HMAC_DGST3;      /*!< Offset: 0x314:  SHA/HMAC Digest Message 3                     */
+    __IO uint32_t HMAC_DGST4;      /*!< Offset: 0x318:  SHA/HMAC Digest Message 4                     */
+    __IO uint32_t HMAC_DGST5;      /*!< Offset: 0x31C:  SHA/HMAC Digest Message 5                     */
+    __IO uint32_t HMAC_DGST6;      /*!< Offset: 0x320:  SHA/HMAC Digest Message 6                     */
+    __IO uint32_t HMAC_DGST7;      /*!< Offset: 0x324:  SHA/HMAC Digest Message 7                     */
+    __IO uint32_t HMAC_DGST8;      /*!< Offset: 0x328:  SHA/HMAC Digest Message 8                     */
+    __IO uint32_t HMAC_DGST9;      /*!< Offset: 0x32C:  SHA/HMAC Digest Message 9                     */
+    __IO uint32_t HMAC_DGST10;     /*!< Offset: 0x330:  SHA/HMAC Digest Message 10                    */
+    __IO uint32_t HMAC_DGST11;     /*!< Offset: 0x334:  SHA/HMAC Digest Message 11                    */
+    __IO uint32_t HMAC_DGST12;     /*!< Offset: 0x338:  SHA/HMAC Digest Message 12                    */
+    __IO uint32_t HMAC_DGST13;     /*!< Offset: 0x33C:  SHA/HMAC Digest Message 13                    */
+    __IO uint32_t HMAC_DGST14;     /*!< Offset: 0x340:  SHA/HMAC Digest Message 14                    */
+    __IO uint32_t HMAC_DGST15;     /*!< Offset: 0x344:  SHA/HMAC Digest Message 15                    */
+    __IO uint32_t HMAC_KEYCNT;     /*!< Offset: 0x348:  SHA/HMAC Key Byte Count                       */
+    __IO uint32_t HMAC_SADDR;      /*!< Offset: 0x34C:  SHA/HMAC DMA Source Address Register          */
+    __IO uint32_t HMAC_DMACNT;     /*!< Offset: 0x350:  SHA/HMAC Byte Count Register                  */
+    __IO uint32_t HMAC_DATIN;      /*!< Offset: 0x354:  SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
+} CRPT_T;
+
+
+#define CRPT            ((CRPT_T *) CRPT_BA)
+
+
+/**
+    @addtogroup CRPT_CONST CRPT Bit Field Definition
+    Constant Definitions for CRPT Controller
+@{ */
+
+#define CRPT_INTEN_AESIEN_Pos            (0)                                               /*!< CRPT INTEN: AESIEN Position            */
+#define CRPT_INTEN_AESIEN_Msk            (0x1ul << CRPT_INTEN_AESIEN_Pos)                  /*!< CRPT INTEN: AESIEN Mask                */
+
+#define CRPT_INTEN_AESERRIEN_Pos         (1)                                               /*!< CRPT INTEN: AESERRIEN Position         */
+#define CRPT_INTEN_AESERRIEN_Msk         (0x1ul << CRPT_INTEN_AESERRIEN_Pos)               /*!< CRPT INTEN: AESERRIEN Mask             */
+
+#define CRPT_INTEN_TDESIEN_Pos           (8)                                               /*!< CRPT INTEN: TDESIEN Position           */
+#define CRPT_INTEN_TDESIEN_Msk           (0x1ul << CRPT_INTEN_TDESIEN_Pos)                 /*!< CRPT INTEN: TDESIEN Mask               */
+
+#define CRPT_INTEN_TDESERRIEN_Pos        (9)                                               /*!< CRPT INTEN: TDESERRIEN Position        */
+#define CRPT_INTEN_TDESERRIEN_Msk        (0x1ul << CRPT_INTEN_TDESERRIEN_Pos)              /*!< CRPT INTEN: TDESERRIEN Mask            */
+
+#define CRPT_INTEN_PRNGIEN_Pos           (16)                                              /*!< CRPT INTEN: PRNGIEN Position           */
+#define CRPT_INTEN_PRNGIEN_Msk           (0x1ul << CRPT_INTEN_PRNGIEN_Pos)                 /*!< CRPT INTEN: PRNGIEN Mask               */
+
+#define CRPT_INTEN_SHAIEN_Pos            (24)                                              /*!< CRPT INTEN: SHAIEN Position            */
+#define CRPT_INTEN_SHAIEN_Msk            (0x1ul << CRPT_INTEN_SHAIEN_Pos)                  /*!< CRPT INTEN: SHAIEN Mask                */
+
+#define CRPT_INTEN_SHAERRIEN_Pos         (25)                                              /*!< CRPT INTEN: SHAERRIEN Position         */
+#define CRPT_INTEN_SHAERRIEN_Msk         (0x1ul << CRPT_INTEN_SHAERRIEN_Pos)               /*!< CRPT INTEN: SHAERRIEN Mask             */
+
+#define CRPT_INTSTS_AESIF_Pos            (0)                                               /*!< CRPT INTSTS: AESIF Position            */
+#define CRPT_INTSTS_AESIF_Msk            (0x1ul << CRPT_INTSTS_AESIF_Pos)                  /*!< CRPT INTSTS: AESIF Mask                */
+
+#define CRPT_INTSTS_AESERRIF_Pos         (1)                                               /*!< CRPT INTSTS: AESERRIF Position         */
+#define CRPT_INTSTS_AESERRIF_Msk         (0x1ul << CRPT_INTSTS_AESERRIF_Pos)               /*!< CRPT INTSTS: AESERRIF Mask             */
+
+#define CRPT_INTSTS_TDESIF_Pos           (8)                                               /*!< CRPT INTSTS: TDESIF Position           */
+#define CRPT_INTSTS_TDESIF_Msk           (0x1ul << CRPT_INTSTS_TDESIF_Pos)                 /*!< CRPT INTSTS: TDESIF Mask               */
+
+#define CRPT_INTSTS_TDESERRIF_Pos        (9)                                               /*!< CRPT INTSTS: TDESERRIF Position        */
+#define CRPT_INTSTS_TDESERRIF_Msk        (0x1ul << CRPT_INTSTS_TDESERRIF_Pos)              /*!< CRPT INTSTS: TDESERRIF Mask            */
+
+#define CRPT_INTSTS_PRNGIF_Pos           (16)                                              /*!< CRPT INTSTS: PRNGIF Position           */
+#define CRPT_INTSTS_PRNGIF_Msk           (0x1ul << CRPT_INTSTS_PRNGIF_Pos)                 /*!< CRPT INTSTS: PRNGIF Mask               */
+
+#define CRPT_INTSTS_SHAIF_Pos            (24)                                              /*!< CRPT INTSTS: SHAIF Position            */
+#define CRPT_INTSTS_SHAIF_Msk            (0x1ul << CRPT_INTSTS_SHAIF_Pos)                  /*!< CRPT INTSTS: SHAIF Mask                */
+
+#define CRPT_INTSTS_SHAERRIF_Pos         (25)                                              /*!< CRPT INTSTS: SHAERRIF Position         */
+#define CRPT_INTSTS_SHAERRIF_Msk         (0x1ul << CRPT_INTSTS_SHAERRIF_Pos)               /*!< CRPT INTSTS: SHAERRIF Mask             */
+
+#define CRPT_PRNG_CTL_START_Pos          (0)                                               /*!< CRPT PRNG_CTL: START Position          */
+#define CRPT_PRNG_CTL_START_Msk          (0x1ul << CRPT_PRNG_CTL_START_Pos)                /*!< CRPT PRNG_CTL: START Mask              */
+
+#define CRPT_PRNG_CTL_SEEDRLD_Pos        (1)                                               /*!< CRPT PRNG_CTL: SEEDRLD Position        */
+#define CRPT_PRNG_CTL_SEEDRLD_Msk        (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)              /*!< CRPT PRNG_CTL: SEEDRLD Mask            */
+
+#define CRPT_PRNG_CTL_KEYSZ_Pos          (2)                                               /*!< CRPT PRNG_CTL: KEYSZ Position          */
+#define CRPT_PRNG_CTL_KEYSZ_Msk          (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos)                /*!< CRPT PRNG_CTL: KEYSZ Mask              */
+
+#define CRPT_PRNG_CTL_BUSY_Pos           (8)                                               /*!< CRPT PRNG_CTL: BUSY Position           */
+#define CRPT_PRNG_CTL_BUSY_Msk           (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)                 /*!< CRPT PRNG_CTL: BUSY Mask               */
+
+#define CRPT_AES_CTL_START_Pos           (0)                                               /*!< CRPT AES_CTL: START Position           */
+#define CRPT_AES_CTL_START_Msk           (0x1ul << CRPT_AES_CTL_START_Pos)                 /*!< CRPT AES_CTL: START Mask               */
+
+#define CRPT_AES_CTL_STOP_Pos            (1)                                               /*!< CRPT AES_CTL: STOP Position            */
+#define CRPT_AES_CTL_STOP_Msk            (0x1ul << CRPT_AES_CTL_STOP_Pos)                  /*!< CRPT AES_CTL: STOP Mask                */
+
+#define CRPT_AES_CTL_KEYSZ_Pos           (2)                                               /*!< CRPT AES_CTL: KEYSZ Position           */
+#define CRPT_AES_CTL_KEYSZ_Msk           (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)                 /*!< CRPT AES_CTL: KEYSZ Mask               */
+
+#define CRPT_AES_CTL_DMALAST_Pos         (5)                                               /*!< CRPT AES_CTL: DMALAST Position         */
+#define CRPT_AES_CTL_DMALAST_Msk         (0x1ul << CRPT_AES_CTL_DMALAST_Pos)               /*!< CRPT AES_CTL: DMALAST Mask             */
+
+#define CRPT_AES_CTL_DMACSCAD_Pos        (6)                                               /*!< CRPT AES_CTL: DMACSCAD Position        */
+#define CRPT_AES_CTL_DMACSCAD_Msk        (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)              /*!< CRPT AES_CTL: DMACSCAD Mask            */
+
+#define CRPT_AES_CTL_DMAEN_Pos           (7)                                               /*!< CRPT AES_CTL: DMAEN Position           */
+#define CRPT_AES_CTL_DMAEN_Msk           (0x1ul << CRPT_AES_CTL_DMAEN_Pos)                 /*!< CRPT AES_CTL: DMAEN Mask               */
+
+#define CRPT_AES_CTL_OPMODE_Pos          (8)                                               /*!< CRPT AES_CTL: OPMODE Position          */
+#define CRPT_AES_CTL_OPMODE_Msk          (0xfful << CRPT_AES_CTL_OPMODE_Pos)               /*!< CRPT AES_CTL: OPMODE Mask              */
+
+#define CRPT_AES_CTL_ENCRPT_Pos          (16)                                              /*!< CRPT AES_CTL: ENCRPT Position          */
+#define CRPT_AES_CTL_ENCRPT_Msk          (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)                /*!< CRPT AES_CTL: ENCRPT Mask              */
+
+#define CRPT_AES_CTL_OUTSWAP_Pos         (22)                                              /*!< CRPT AES_CTL: OUTSWAP Position         */
+#define CRPT_AES_CTL_OUTSWAP_Msk         (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)               /*!< CRPT AES_CTL: OUTSWAP Mask             */
+
+#define CRPT_AES_CTL_INSWAP_Pos          (23)                                              /*!< CRPT AES_CTL: INSWAP Position          */
+#define CRPT_AES_CTL_INSWAP_Msk          (0x1ul << CRPT_AES_CTL_INSWAP_Pos)                /*!< CRPT AES_CTL: INSWAP Mask              */
+
+#define CRPT_AES_CTL_CHANNEL_Pos         (24)                                              /*!< CRPT AES_CTL: CHANNEL Position         */
+#define CRPT_AES_CTL_CHANNEL_Msk         (0x3ul << CRPT_AES_CTL_CHANNEL_Pos)               /*!< CRPT AES_CTL: CHANNEL Mask             */
+
+#define CRPT_AES_CTL_KEYUNPRT_Pos        (26)                                              /*!< CRPT AES_CTL: KEYUNPRT Position        */
+#define CRPT_AES_CTL_KEYUNPRT_Msk        (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)             /*!< CRPT AES_CTL: KEYUNPRT Mask            */
+
+#define CRPT_AES_CTL_KEYPRT_Pos          (31)                                              /*!< CRPT AES_CTL: KEYPRT Position          */
+#define CRPT_AES_CTL_KEYPRT_Msk          (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)                /*!< CRPT AES_CTL: KEYPRT Mask              */
+
+#define CRPT_AES_STS_BUSY_Pos            (0)                                               /*!< CRPT AES_STS: BUSY Position            */
+#define CRPT_AES_STS_BUSY_Msk            (0x1ul << CRPT_AES_STS_BUSY_Pos)                  /*!< CRPT AES_STS: BUSY Mask                */
+
+#define CRPT_AES_STS_INBUFEMPTY_Pos      (8)                                               /*!< CRPT AES_STS: INBUFEMPTY Position      */
+#define CRPT_AES_STS_INBUFEMPTY_Msk      (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)            /*!< CRPT AES_STS: INBUFEMPTY Mask          */
+
+#define CRPT_AES_STS_INBUFFULL_Pos       (9)                                               /*!< CRPT AES_STS: INBUFFULL Position       */
+#define CRPT_AES_STS_INBUFFULL_Msk       (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)             /*!< CRPT AES_STS: INBUFFULL Mask           */
+
+#define CRPT_AES_STS_INBUFERR_Pos        (10)                                              /*!< CRPT AES_STS: INBUFERR Position        */
+#define CRPT_AES_STS_INBUFERR_Msk        (0x1ul << CRPT_AES_STS_INBUFERR_Pos)              /*!< CRPT AES_STS: INBUFERR Mask            */
+
+#define CRPT_AES_STS_CNTERR_Pos          (12)                                              /*!< CRPT AES_STS: CNTERR Position          */
+#define CRPT_AES_STS_CNTERR_Msk          (0x1ul << CRPT_AES_STS_CNTERR_Pos)                /*!< CRPT AES_STS: CNTERR Mask              */
+
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos     (16)                                              /*!< CRPT AES_STS: OUTBUFEMPTY Position     */
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk     (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)           /*!< CRPT AES_STS: OUTBUFEMPTY Mask         */
+
+#define CRPT_AES_STS_OUTBUFFULL_Pos      (17)                                              /*!< CRPT AES_STS: OUTBUFFULL Position      */
+#define CRPT_AES_STS_OUTBUFFULL_Msk      (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)            /*!< CRPT AES_STS: OUTBUFFULL Mask          */
+
+#define CRPT_AES_STS_OUTBUFERR_Pos       (18)                                              /*!< CRPT AES_STS: OUTBUFERR Position       */
+#define CRPT_AES_STS_OUTBUFERR_Msk       (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)             /*!< CRPT AES_STS: OUTBUFERR Mask           */
+
+#define CRPT_AES_STS_BUSERR_Pos          (20)                                              /*!< CRPT AES_STS: BUSERR Position          */
+#define CRPT_AES_STS_BUSERR_Msk          (0x1ul << CRPT_AES_STS_BUSERR_Pos)                /*!< CRPT AES_STS: BUSERR Mask              */
+
+#define CRPT_TDES_CTL_START_Pos          (0)                                               /*!< CRPT TDES_CTL: START Position          */
+#define CRPT_TDES_CTL_START_Msk          (0x1ul << CRPT_TDES_CTL_START_Pos)                /*!< CRPT TDES_CTL: START Mask              */
+
+#define CRPT_TDES_CTL_STOP_Pos           (1)                                               /*!< CRPT TDES_CTL: STOP Position           */
+#define CRPT_TDES_CTL_STOP_Msk           (0x1ul << CRPT_TDES_CTL_STOP_Pos)                 /*!< CRPT TDES_CTL: STOP Mask               */
+
+#define CRPT_TDES_CTL_TMODE_Pos          (2)                                               /*!< CRPT TDES_CTL: TMODE Position          */
+#define CRPT_TDES_CTL_TMODE_Msk          (0x1ul << CRPT_TDES_CTL_TMODE_Pos)                /*!< CRPT TDES_CTL: TMODE Mask              */
+
+#define CRPT_TDES_CTL_3KEYS_Pos          (3)                                               /*!< CRPT TDES_CTL: 3KEYS Position          */
+#define CRPT_TDES_CTL_3KEYS_Msk          (0x1ul << CRPT_TDES_CTL_3KEYS_Pos)                /*!< CRPT TDES_CTL: 3KEYS Mask              */
+
+#define CRPT_TDES_CTL_DMALAST_Pos        (5)                                               /*!< CRPT TDES_CTL: DMALAST Position        */
+#define CRPT_TDES_CTL_DMALAST_Msk        (0x1ul << CRPT_TDES_CTL_DMALAST_Pos)              /*!< CRPT TDES_CTL: DMALAST Mask            */
+
+#define CRPT_TDES_CTL_DMACSCAD_Pos       (6)                                               /*!< CRPT TDES_CTL: DMACSCAD Position       */
+#define CRPT_TDES_CTL_DMACSCAD_Msk       (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos)             /*!< CRPT TDES_CTL: DMACSCAD Mask           */
+
+#define CRPT_TDES_CTL_DMAEN_Pos          (7)                                               /*!< CRPT TDES_CTL: DMAEN Position          */
+#define CRPT_TDES_CTL_DMAEN_Msk          (0x1ul << CRPT_TDES_CTL_DMAEN_Pos)                /*!< CRPT TDES_CTL: DMAEN Mask              */
+
+#define CRPT_TDES_CTL_OPMODE_Pos         (8)                                               /*!< CRPT TDES_CTL: OPMODE Position         */
+#define CRPT_TDES_CTL_OPMODE_Msk         (0x7ul << CRPT_TDES_CTL_OPMODE_Pos)               /*!< CRPT TDES_CTL: OPMODE Mask             */
+
+#define CRPT_TDES_CTL_ENCRPT_Pos         (16)                                              /*!< CRPT TDES_CTL: ENCRPT Position         */
+#define CRPT_TDES_CTL_ENCRPT_Msk         (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos)               /*!< CRPT TDES_CTL: ENCRPT Mask             */
+
+#define CRPT_TDES_CTL_BLKSWAP_Pos        (21)                                              /*!< CRPT TDES_CTL: BLKSWAP Position        */
+#define CRPT_TDES_CTL_BLKSWAP_Msk        (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos)              /*!< CRPT TDES_CTL: BLKSWAP Mask            */
+
+#define CRPT_TDES_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT TDES_CTL: OUTSWAP Position        */
+#define CRPT_TDES_CTL_OUTSWAP_Msk        (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos)              /*!< CRPT TDES_CTL: OUTSWAP Mask            */
+
+#define CRPT_TDES_CTL_INSWAP_Pos         (23)                                              /*!< CRPT TDES_CTL: INSWAP Position         */
+#define CRPT_TDES_CTL_INSWAP_Msk         (0x1ul << CRPT_TDES_CTL_INSWAP_Pos)               /*!< CRPT TDES_CTL: INSWAP Mask             */
+
+#define CRPT_TDES_CTL_CHANNEL_Pos        (24)                                              /*!< CRPT TDES_CTL: CHANNEL Position        */
+#define CRPT_TDES_CTL_CHANNEL_Msk        (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos)              /*!< CRPT TDES_CTL: CHANNEL Mask            */
+
+#define CRPT_TDES_CTL_KEYUNPRT_Pos       (26)                                              /*!< CRPT TDES_CTL: KEYUNPRT Position       */
+#define CRPT_TDES_CTL_KEYUNPRT_Msk       (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos)            /*!< CRPT TDES_CTL: KEYUNPRT Mask           */
+
+#define CRPT_TDES_CTL_KEYPRT_Pos         (31)                                              /*!< CRPT TDES_CTL: KEYPRT Position         */
+#define CRPT_TDES_CTL_KEYPRT_Msk         (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos)               /*!< CRPT TDES_CTL: KEYPRT Mask             */
+
+#define CRPT_TDES_STS_BUSY_Pos           (0)                                               /*!< CRPT TDES_STS: BUSY Position           */
+#define CRPT_TDES_STS_BUSY_Msk           (0x1ul << CRPT_TDES_STS_BUSY_Pos)                 /*!< CRPT TDES_STS: BUSY Mask               */
+
+#define CRPT_TDES_STS_INBUFEMPTY_Pos     (8)                                               /*!< CRPT TDES_STS: INBUFEMPTY Position     */
+#define CRPT_TDES_STS_INBUFEMPTY_Msk     (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos)           /*!< CRPT TDES_STS: INBUFEMPTY Mask         */
+
+#define CRPT_TDES_STS_INBUFFULL_Pos      (9)                                               /*!< CRPT TDES_STS: INBUFFULL Position      */
+#define CRPT_TDES_STS_INBUFFULL_Msk      (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos)            /*!< CRPT TDES_STS: INBUFFULL Mask          */
+
+#define CRPT_TDES_STS_INBUFERR_Pos       (10)                                              /*!< CRPT TDES_STS: INBUFERR Position       */
+#define CRPT_TDES_STS_INBUFERR_Msk       (0x1ul << CRPT_TDES_STS_INBUFERR_Pos)             /*!< CRPT TDES_STS: INBUFERR Mask           */
+
+#define CRPT_TDES_STS_OUTBUFEMPTY_Pos    (16)                                              /*!< CRPT TDES_STS: OUTBUFEMPTY Position    */
+#define CRPT_TDES_STS_OUTBUFEMPTY_Msk    (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos)          /*!< CRPT TDES_STS: OUTBUFEMPTY Mask        */
+
+#define CRPT_TDES_STS_OUTBUFFULL_Pos     (17)                                              /*!< CRPT TDES_STS: OUTBUFFULL Position     */
+#define CRPT_TDES_STS_OUTBUFFULL_Msk     (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos)           /*!< CRPT TDES_STS: OUTBUFFULL Mask         */
+
+#define CRPT_TDES_STS_OUTBUFERR_Pos      (18)                                              /*!< CRPT TDES_STS: OUTBUFERR Position      */
+#define CRPT_TDES_STS_OUTBUFERR_Msk      (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos)            /*!< CRPT TDES_STS: OUTBUFERR Mask          */
+
+#define CRPT_TDES_STS_BUSERR_Pos         (20)                                              /*!< CRPT TDES_STS: BUSERR Position         */
+#define CRPT_TDES_STS_BUSERR_Msk         (0x1ul << CRPT_TDES_STS_BUSERR_Pos)               /*!< CRPT TDES_STS: BUSERR Mask             */
+
+#define CRPT_HMAC_CTL_START_Pos          (0)                                               /*!< CRPT HMAC_CTL: START Position           */
+#define CRPT_HMAC_CTL_START_Msk          (0x1ul << CRPT_HMAC_CTL_START_Pos)                /*!< CRPT HMAC_CTL: START Mask               */
+
+#define CRPT_HMAC_CTL_STOP_Pos           (1)                                               /*!< CRPT HMAC_CTL: STOP Position            */
+#define CRPT_HMAC_CTL_STOP_Msk           (0x1ul << CRPT_HMAC_CTL_STOP_Pos)                 /*!< CRPT HMAC_CTL: STOP Mask                */
+
+#define CRPT_HMAC_CTL_HMACEN_Pos         (4)                                               /*!< CRPT HMAC_CTL: HMACEN Position          */
+#define CRPT_HMAC_CTL_HMACEN_Msk         (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos)               /*!< CRPT HMAC_CTL: HMACEN Mask              */
+
+#define CRPT_HMAC_CTL_DMALAST_Pos        (5)                                               /*!< CRPT HMAC_CTL: DMALAST Position         */
+#define CRPT_HMAC_CTL_DMALAST_Msk        (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos)              /*!< CRPT HMAC_CTL: DMALAST Mask             */
+
+#define CRPT_HMAC_CTL_DMAEN_Pos          (7)                                               /*!< CRPT HMAC_CTL: DMAEN Position           */
+#define CRPT_HMAC_CTL_DMAEN_Msk          (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos)                /*!< CRPT HMAC_CTL: DMAEN Mask               */
+
+#define CRPT_HMAC_CTL_OPMODE_Pos         (8)                                               /*!< CRPT HMAC_CTL: OPMODE Position          */
+#define CRPT_HMAC_CTL_OPMODE_Msk         (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos)               /*!< CRPT HMAC_CTL: OPMODE Mask              */
+
+#define CRPT_HMAC_CTL_COMPEN_Pos         (15)                                              /*!< CRPT HMAC_CTL: COMPEN Position          */
+#define CRPT_HMAC_CTL_COMPEN_Msk         (0x1ul << CRPT_HMAC_CTL_COMPEN_Pos)               /*!< CRPT HMAC_CTL: COMPEN Mask              */
+
+#define CRPT_HMAC_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT HMAC_CTL: OUTSWAP Position         */
+#define CRPT_HMAC_CTL_OUTSWAP_Msk        (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos)              /*!< CRPT HMAC_CTL: OUTSWAP Mask             */
+
+#define CRPT_HMAC_CTL_INSWAP_Pos         (23)                                              /*!< CRPT HMAC_CTL: INSWAP Position          */
+#define CRPT_HMAC_CTL_INSWAP_Msk         (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos)               /*!< CRPT HMAC_CTL: INSWAP Mask              */
+
+#define CRPT_HMAC_STS_BUSY_Pos           (0)                                               /*!< CRPT HMAC_STS: BUSY Position            */
+#define CRPT_HMAC_STS_BUSY_Msk           (0x1ul << CRPT_HMAC_STS_BUSY_Pos)                 /*!< CRPT HMAC_STS: BUSY Mask                */
+
+#define CRPT_HMAC_STS_DMABUSY_Pos        (1)                                               /*!< CRPT HMAC_STS: DMABUSY Position         */
+#define CRPT_HMAC_STS_DMABUSY_Msk        (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos)              /*!< CRPT HMAC_STS: DMABUSY Mask             */
+
+#define CRPT_HMAC_STS_DMAERR_Pos         (8)                                               /*!< CRPT HMAC_STS: DMAERR Position          */
+#define CRPT_HMAC_STS_DMAERR_Msk         (0x1ul << CRPT_HMAC_STS_DMAERR_Pos)               /*!< CRPT HMAC_STS: DMAERR Mask              */
+
+#define CRPT_HMAC_STS_COMPRES_Pos        (15)                                              /*!< CRPT HMAC_STS: COMPRES Position         */
+#define CRPT_HMAC_STS_COMPRES_Msk        (0x1ul << CRPT_HMAC_STS_COMPRES_Pos)              /*!< CRPT HMAC_STS: COMPRES Mask             */
+
+#define CRPT_HMAC_STS_DATINREQ_Pos       (16)                                              /*!< CRPT HMAC_STS: DATINREQ Position        */
+#define CRPT_HMAC_STS_DATINREQ_Msk       (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos)             /*!< CRPT HMAC_STS: DATINREQ Mask            */
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+
+/** @addtogroup N9H30_CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
+  @{
+*/
+
+#define PRNG_KEY_SIZE_64        0       /*!< Select to generate 64-bit random key    \hideinitializer */
+#define PRNG_KEY_SIZE_128       1       /*!< Select to generate 128-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_192       2       /*!< Select to generate 192-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_256       3       /*!< Select to generate 256-bit random key   \hideinitializer */
+
+#define PRNG_SEED_CONT          0       /*!< PRNG using current seed                 \hideinitializer */
+#define PRNG_SEED_RELOAD        1       /*!< PRNG reload new seed                    \hideinitializer */
+
+#define AES_KEY_SIZE_128        0       /*!< AES select 128-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_192        1       /*!< AES select 192-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_256        2       /*!< AES select 256-bit key length           \hideinitializer */
+
+#define AES_MODE_ECB            0       /*!< AES select ECB mode                     \hideinitializer */
+#define AES_MODE_CBC            1       /*!< AES select CBC mode                     \hideinitializer */
+#define AES_MODE_CFB            2       /*!< AES select CFB mode                     \hideinitializer */
+#define AES_MODE_OFB            3       /*!< AES select OFB mode                     \hideinitializer */
+#define AES_MODE_CTR            4       /*!< AES select CTR mode                     \hideinitializer */
+#define AES_MODE_CBC_CS1        0x10    /*!< AES select CBC CS1 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS2        0x11    /*!< AES select CBC CS2 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS3        0x12    /*!< AES select CBC CS3 mode                 \hideinitializer */
+
+#define AES_NO_SWAP             0       /*!< AES do not swap input and output data   \hideinitializer */
+#define AES_OUT_SWAP            1       /*!< AES swap output data                    \hideinitializer */
+#define AES_IN_SWAP             2       /*!< AES swap input data                     \hideinitializer */
+#define AES_IN_OUT_SWAP         3       /*!< AES swap both input and output data     \hideinitializer */
+
+#define DES_MODE_ECB            0x000   /*!< DES select ECB mode                     \hideinitializer */
+#define DES_MODE_CBC            0x100   /*!< DES select CBC mode                     \hideinitializer */
+#define DES_MODE_CFB            0x200   /*!< DES select CFB mode                     \hideinitializer */
+#define DES_MODE_OFB            0x300   /*!< DES select OFB mode                     \hideinitializer */
+#define DES_MODE_CTR            0x400   /*!< DES select CTR mode                     \hideinitializer */
+#define TDES_MODE_ECB           0x004   /*!< TDES select ECB mode                    \hideinitializer */
+#define TDES_MODE_CBC           0x104   /*!< TDES select CBC mode                    \hideinitializer */
+#define TDES_MODE_CFB           0x204   /*!< TDES select CFB mode                    \hideinitializer */
+#define TDES_MODE_OFB           0x304   /*!< TDES select OFB mode                    \hideinitializer */
+#define TDES_MODE_CTR           0x404   /*!< TDES select CTR mode                    \hideinitializer */
+
+#define TDES_NO_SWAP            0       /*!< TDES do not swap data                       \hideinitializer */
+#define TDES_WHL_SWAP           1       /*!< TDES swap high-low word                     \hideinitializer */
+#define TDES_OUT_SWAP           2       /*!< TDES swap output data                       \hideinitializer */
+#define TDES_OUT_WHL_SWAP       3       /*!< TDES swap output data and high-low word     \hideinitializer */
+#define TDES_IN_SWAP            4       /*!< TDES swap input data                        \hideinitializer */
+#define TDES_IN_WHL_SWAP        5       /*!< TDES swap input data and high-low word      \hideinitializer */
+#define TDES_IN_OUT_SWAP        6       /*!< TDES swap both input and output data        \hideinitializer */
+#define TDES_IN_OUT_WHL_SWAP    7       /*!< TDES swap input, output and high-low word   \hideinitializer */
+
+#define SHA_MODE_SHA1           0       /*!< SHA select SHA-1 160-bit                \hideinitializer */
+#define SHA_MODE_SHA224         5       /*!< SHA select SHA-224 224-bit              \hideinitializer */
+#define SHA_MODE_SHA256         4       /*!< SHA select SHA-256 256-bit              \hideinitializer */
+#define SHA_MODE_SHA384         7       /*!< SHA select SHA-384 384-bit              \hideinitializer */
+#define SHA_MODE_SHA512         6       /*!< SHA select SHA-512 512-bit              \hideinitializer */
+
+#define SHA_NO_SWAP             0       /*!< SHA do not swap input and output data   \hideinitializer */
+#define SHA_OUT_SWAP            1       /*!< SHA swap output data                    \hideinitializer */
+#define SHA_IN_SWAP             2       /*!< SHA swap input data                     \hideinitializer */
+#define SHA_IN_OUT_SWAP         3       /*!< SHA swap both input and output data     \hideinitializer */
+
+#define CRYPTO_DMA_FIRST        0x4     /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_ONE_SHOT     0x5     /*!< Do one shot encrypt/decrypt with DMA      \hideinitializer */
+#define CRYPTO_DMA_CONTINUE     0x6     /*!< Do one continuous encrypt/decrypt with DMA \hideinitializer */
+#define CRYPTO_DMA_LAST         0x7     /*!< Do last encrypt/decrypt with DMA          \hideinitializer */
+
+/*@}*/ /* end of group N9H30_CRYPTO_EXPORTED_CONSTANTS */
+
+
+
+
+/** @addtogroup N9H30_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/*----------------------------------------------------------------------------------------------*/
+/*  Macros                                                                                      */
+/*----------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief This macro enables PRNG interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_ENABLE_INT()       (CRPT->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro disables PRNG interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_DISABLE_INT()      (CRPT->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro gets PRNG interrupt flag.
+  * @return PRNG interrupt flag.
+  * \hideinitializer
+  */
+#define PRNG_GET_INT_FLAG()     (CRPT->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro clears PRNG interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_CLR_INT_FLAG()     (CRPT->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro enables AES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
+
+/**
+  * @brief This macro disables AES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
+
+/**
+  * @brief This macro gets AES interrupt flag.
+  * @return AES interrupt flag.
+  * \hideinitializer
+  */
+#define AES_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
+
+/**
+  * @brief This macro clears AES interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
+
+/**
+  * @brief This macro enables AES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_KEY_PROTECT()  (CRPT->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables AES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_KEY_PROTECT() (CRPT->AES_CTL = (CRPT->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16<<CRPT_AES_CTL_KEYUNPRT_Pos))
+
+/**
+  * @brief This macro enables TDES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_INT()       (CRPT->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
+
+/**
+  * @brief This macro disables TDES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_INT()      (CRPT->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
+
+/**
+  * @brief This macro gets TDES interrupt flag.
+  * @return TDES interrupt flag.
+  * \hideinitializer
+  */
+#define TDES_GET_INT_FLAG()     (CRPT->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
+
+/**
+  * @brief This macro clears TDES interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_CLR_INT_FLAG()     (CRPT->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
+
+/**
+  * @brief This macro enables TDES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_KEY_PROTECT()  (CRPT->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables TDES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_KEY_PROTECT() (CRPT->TDES_CTL = (CRPT->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16<<CRPT_TDES_CTL_KEYUNPRT_Pos))
+
+/**
+  * @brief This macro enables SHA interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
+
+/**
+  * @brief This macro disables SHA interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
+
+/**
+  * @brief This macro gets SHA interrupt flag.
+  * @return SHA interrupt flag.
+  * \hideinitializer
+  */
+#define SHA_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
+
+/**
+  * @brief This macro clears SHA interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Functions                                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+
+void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
+void PRNG_Start(void);
+void PRNG_Read(uint32_t u32RandKey[]);
+void AES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
+void AES_Start(int32_t u32Channel, uint32_t u32DMAMode);
+void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
+void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]);
+void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
+void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode);
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]);
+void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
+void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType, int hmac_key_len);
+void SHA_Start(uint32_t u32DMAMode);
+void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt);
+void SHA_Read(uint32_t u32Digest[]);
+
+
+/*@}*/ /* end of group N9H30_CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_CRYPTO_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __NU_CRYPTO_H__
+
+/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_emac.h

@@ -0,0 +1,396 @@
+/**************************************************************************//**
+ * @file     nu_emac.h
+ * @version  V1.00
+ * @brief    EMAC driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_EMAC_H__
+#define __NU_EMAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include "emac_reg.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EMAC_Driver EMAC Driver
+  @{
+*/
+
+/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+  @{
+*/
+
+#define EMAC_PHY_ADDR      1UL    /*!<  PHY address, this address is board dependent \hideinitializer */
+#define EMAC_RX_DESC_SIZE  64UL    /*!<  Number of Rx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_TX_DESC_SIZE  32UL    /*!<  Number of Tx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_CAMENTRY_NB   16UL   /*!<  Number of CAM \hideinitializer */
+#define EMAC_MAX_PKT_SIZE  1536UL /*!<  Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */
+
+#define EMAC_LINK_DOWN    0UL    /*!<  Ethernet link is down \hideinitializer */
+#define EMAC_LINK_100F    1UL    /*!<  Ethernet link is 100Mbps full duplex \hideinitializer */
+#define EMAC_LINK_100H    2UL    /*!<  Ethernet link is 100Mbps half duplex \hideinitializer */
+#define EMAC_LINK_10F     3UL    /*!<  Ethernet link is 10Mbps full duplex \hideinitializer */
+#define EMAC_LINK_10H     4UL    /*!<  Ethernet link is 10Mbps half duplex \hideinitializer */
+
+/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
+
+
+/** Tx/Rx buffer descriptor structure */
+typedef struct
+{
+    uint32_t u32Status1;   /*!<  Status word 1 */
+    uint32_t u32Data;      /*!<  Pointer to data buffer */
+    uint32_t u32Status2;   /*!<  Status word 2 */
+    uint32_t u32Next;      /*!<  Pointer to next descriptor */
+    uint32_t u32Backup1;   /*!<  For backup descriptor fields over written by time stamp */
+    uint32_t u32Backup2;   /*!<  For backup descriptor fields over written by time stamp */
+} EMAC_DESCRIPTOR_T;
+
+/** Tx/Rx buffer structure */
+typedef struct
+{
+    uint8_t au8Buf[EMAC_MAX_PKT_SIZE];
+} EMAC_FRAME_T;
+
+typedef struct
+{
+    EMAC_T  *psEmac;
+
+    uint32_t u32TxDescSize;
+    uint32_t u32RxDescSize;
+
+    EMAC_DESCRIPTOR_T *psRXDescs;
+    EMAC_FRAME_T *psRXFrames;
+    EMAC_DESCRIPTOR_T *psTXDescs;
+    EMAC_FRAME_T *psTXFrames;
+
+    EMAC_DESCRIPTOR_T *psCurrentTxDesc;
+    EMAC_DESCRIPTOR_T *psNextTxDesc;
+    EMAC_DESCRIPTOR_T *psCurrentRxDesc;
+
+} EMAC_MEMMGR_T;
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Enable EMAC Tx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_TX(EMAC) (EMAC->CTL |= EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Enable EMAC Rx function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RX(EMAC) do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
+
+/**
+  * @brief  Disable EMAC Tx function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_TX(EMAC) (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Disable EMAC Rx function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RX(EMAC) (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
+
+/**
+  * @brief  Enable EMAC Magic Packet Wakeup function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
+
+/**
+  * @brief  Enable EMAC to receive broadcast packets
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Disable EMAC to receive broadcast packets
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Enable EMAC to receive multicast packets
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Check if EMAC time stamp alarm interrupt occurred or not
+  * @param  The pointer of the specified EMAC module
+  * @return If time stamp alarm interrupt occurred or not
+  * @retval 0 Alarm interrupt does not occur
+  * @retval 1 Alarm interrupt occurred
+  * \hideinitializer
+  */
+#define EMAC_GET_ALARM_FLAG(EMAC) (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
+
+/**
+  * @brief  Clear EMAC time stamp alarm interrupt flag
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_CLR_ALARM_FLAG(EMAC) (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
+
+/**
+  * @brief  Trigger EMAC Rx function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  */
+#define EMAC_TRIGGER_RX(EMAC) do{EMAC->RXST = 0UL;}while(0)
+
+/**
+  * @brief  Trigger EMAC Tx function
+  * @param  The pointer of the specified EMAC module
+  * @return None
+  */
+#define EMAC_TRIGGER_TX(EMAC) do{EMAC->TXST = 0UL;}while(0)
+
+/**
+ *    @brief        Enable specified EMAC interrupt
+ *
+ *    @param[in]    EMAC        The pointer of the specified EMAC module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref EMAC_INTEN_RXIEN_Msk    : Receive
+ *                              - \ref EMAC_INTEN_CRCEIEN_Msk  : CRC Error
+ *                              - \ref EMAC_INTEN_RXOVIEN_Msk  : Receive FIFO Overflow
+ *                              - \ref EMAC_INTEN_LPIEN_Msk    : Long Packet
+ *                              - \ref EMAC_INTEN_RXGDIEN_Msk  : Receive Good
+ *                              - \ref EMAC_INTEN_ALIEIEN_Msk  : Alignment Error
+ *                              - \ref EMAC_INTEN_RPIEN_Msk    : Runt Packet
+ *                              - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
+ *                              - \ref EMAC_INTEN_MFLEIEN_Msk  : Maximum Frame Length Exceed
+ *                              - \ref EMAC_INTEN_DENIEN_Msk   : DMA Early Notification
+ *                              - \ref EMAC_INTEN_RDUIEN_Msk   : Receive Descriptor Unavailable
+ *                              - \ref EMAC_INTEN_RXBEIEN_Msk  : Receive Bus Error
+ *                              - \ref EMAC_INTEN_CFRIEN_Msk   : Control Frame Receive
+ *                              - \ref EMAC_INTEN_WOLIEN_Msk   : Wake on LAN Interrupt
+ *                              - \ref EMAC_INTEN_TXIEN_Msk    : Transmit
+ *                              - \ref EMAC_INTEN_TXUDIEN_Msk  : Transmit FIFO Underflow
+ *                              - \ref EMAC_INTEN_TXCPIEN_Msk  : Transmit Completion
+ *                              - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
+ *                              - \ref EMAC_INTEN_NCSIEN_Msk   : No Carrier Sense
+ *                              - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
+ *                              - \ref EMAC_INTEN_LCIEN_Msk    : Late Collision
+ *                              - \ref EMAC_INTEN_TDUIEN_Msk   : Transmit Descriptor Unavailable
+ *                              - \ref EMAC_INTEN_TXBEIEN_Msk  : Transmit Bus Error
+ *                              - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified EMAC interrupt.
+ *    \hideinitializer
+ */
+#define EMAC_ENABLE_INT(EMAC, u32eIntSel)    ((EMAC)->INTEN |= (u32eIntSel))
+
+/**
+ *    @brief        Disable specified EMAC interrupt
+ *
+ *    @param[in]    emac        The pointer of the specified EMAC module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref EMAC_INTEN_RXIEN_Msk    : Receive
+ *                              - \ref EMAC_INTEN_CRCEIEN_Msk  : CRC Error
+ *                              - \ref EMAC_INTEN_RXOVIEN_Msk  : Receive FIFO Overflow
+ *                              - \ref EMAC_INTEN_LPIEN_Msk    : Long Packet
+ *                              - \ref EMAC_INTEN_RXGDIEN_Msk  : Receive Good
+ *                              - \ref EMAC_INTEN_ALIEIEN_Msk  : Alignment Error
+ *                              - \ref EMAC_INTEN_RPIEN_Msk    : Runt Packet
+ *                              - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
+ *                              - \ref EMAC_INTEN_MFLEIEN_Msk  : Maximum Frame Length Exceed
+ *                              - \ref EMAC_INTEN_DENIEN_Msk   : DMA Early Notification
+ *                              - \ref EMAC_INTEN_RDUIEN_Msk   : Receive Descriptor Unavailable
+ *                              - \ref EMAC_INTEN_RXBEIEN_Msk  : Receive Bus Error
+ *                              - \ref EMAC_INTEN_CFRIEN_Msk   : Control Frame Receive
+ *                              - \ref EMAC_INTEN_WOLIEN_Msk   : Wake on LAN Interrupt
+ *                              - \ref EMAC_INTEN_TXIEN_Msk    : Transmit
+ *                              - \ref EMAC_INTEN_TXUDIEN_Msk  : Transmit FIFO Underflow
+ *                              - \ref EMAC_INTEN_TXCPIEN_Msk  : Transmit Completion
+ *                              - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
+ *                              - \ref EMAC_INTEN_NCSIEN_Msk   : No Carrier Sense
+ *                              - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
+ *                              - \ref EMAC_INTEN_LCIEN_Msk    : Late Collision
+ *                              - \ref EMAC_INTEN_TDUIEN_Msk   : Transmit Descriptor Unavailable
+ *                              - \ref EMAC_INTEN_TXBEIEN_Msk  : Transmit Bus Error
+ *                              - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified EMAC interrupt.
+ *    \hideinitializer
+ */
+#define EMAC_DISABLE_INT(EMAC, u32eIntSel)    ((EMAC)->INTEN &= ~ (u32eIntSel))
+
+/**
+ *    @brief        Get specified interrupt flag/status
+ *
+ *    @param[in]    emac            The pointer of the specified EMAC module
+ *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref EMAC_INTSTS_RXIF_Msk : Receive
+ *                                  - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
+ *                                  - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
+ *                                  - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
+ *                                  - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
+ *                                  - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
+ *                                  - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
+ *                                  - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
+ *                                  - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
+ *                                  - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
+ *                                  - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
+ *                                  - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
+ *                                  - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
+ *                                  - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
+ *                                  - \ref EMAC_INTSTS_TXIF_Msk : Transmit
+ *                                  - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
+ *                                  - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
+ *                                  - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
+ *                                  - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
+ *                                  - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
+ *                                  - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
+ *                                  - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
+ *                                  - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
+ *                                  - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
+ *
+ *    @return       None
+ *
+ *    @details      This macro get specified interrupt flag or interrupt indicator status.
+ *    \hideinitializer
+ */
+#define EMAC_GET_INT_FLAG(EMAC, u32eIntTypeFlag)    (((EMAC)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+/**
+ *    @brief        Clear specified interrupt flag/status
+ *
+ *    @param[in]    emac            The pointer of the specified EMAC module
+ *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref EMAC_INTSTS_RXIF_Msk : Receive
+ *                                  - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
+ *                                  - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
+ *                                  - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
+ *                                  - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
+ *                                  - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
+ *                                  - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
+ *                                  - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
+ *                                  - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
+ *                                  - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
+ *                                  - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
+ *                                  - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
+ *                                  - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
+ *                                  - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
+ *                                  - \ref EMAC_INTSTS_TXIF_Msk : Transmit
+ *                                  - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
+ *                                  - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
+ *                                  - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
+ *                                  - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
+ *                                  - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
+ *                                  - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
+ *                                  - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
+ *                                  - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
+ *                                  - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
+ *
+ *    @retval       0 The specified interrupt is not happened.
+ *                  1 The specified interrupt is happened.
+ *
+ *    @details      This macro clear specified interrupt flag or interrupt indicator status.
+ *    \hideinitializer
+ */
+#define EMAC_CLEAR_INT_FLAG(EMAC, u32eIntTypeFlag)    ((EMAC)->INTSTS |= (u32eIntTypeFlag))
+#define EMAC_CLEAR_ALL_INT_FLAG(EMAC)                 ((EMAC)->INTSTS |= (EMAC)->INTSTS)
+
+
+void EMAC_Open(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8MacAddr);
+void EMAC_Close(EMAC_T *EMAC);
+void EMAC_SetMacAddr(EMAC_T *EMAC, uint8_t *pu8MacAddr);
+void EMAC_EnableCamEntry(EMAC_T *EMAC, uint32_t u32Entry, uint8_t pu8MacAddr[]);
+void EMAC_DisableCamEntry(EMAC_T *EMAC, uint32_t u32Entry);
+
+uint32_t EMAC_RecvPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size);
+uint32_t EMAC_RecvPktTS(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_RecvPktDone(EMAC_MEMMGR_T *psMemMgr);
+
+uint32_t EMAC_SendPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t u32Size);
+uint32_t EMAC_SendPktDone(EMAC_MEMMGR_T *psMemMgr);
+uint32_t EMAC_SendPktDoneTS(EMAC_MEMMGR_T *psMemMgr, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+
+void EMAC_EnableTS(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableTS(EMAC_T *EMAC);
+void EMAC_GetTime(EMAC_T *EMAC, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_SetTime(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_UpdateTime(EMAC_T *EMAC, uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_EnableAlarm(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableAlarm(EMAC_T *EMAC);
+
+uint32_t EMAC_CheckLinkStatus(EMAC_T *EMAC);
+
+void EMAC_Reset(EMAC_T *EMAC);
+void EMAC_PhyInit(EMAC_T *EMAC);
+int32_t EMAC_FillCamEntry(EMAC_T *EMAC, uint8_t pu8MacAddr[]);
+uint8_t *EMAC_ClaimFreeTXBuf(EMAC_MEMMGR_T *psMemMgr);
+uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf);
+uint32_t EMAC_SendPktWoCopy(EMAC_MEMMGR_T *psMemMgr, uint32_t u32Size);
+void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr);
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EMAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EMAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_etimer.h

@@ -0,0 +1,717 @@
+/**************************************************************************//**
+ * @file     etimer.h
+ * @brief    N9H30 series ETIMER driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_ETIMER_H__
+#define __NU_ETIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "N9H30.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_ETIMER_Driver ETIMER Driver
+  @{
+*/
+
+/** @addtogroup N9H30_ETIMER_EXPORTED_CONSTANTS ETIMER Exported Constants
+  @{
+*/
+
+#define ETIMER_ONESHOT_MODE                      (0UL)          /*!< Timer working in one shot mode   */
+#define ETIMER_PERIODIC_MODE                     (1UL << 4)     /*!< Timer working in periodic mode   */
+#define ETIMER_TOGGLE_MODE                       (2UL << 4)     /*!< Timer working in toggle mode     */
+#define ETIMER_CONTINUOUS_MODE                   (3UL << 4)     /*!< Timer working in continuous mode */
+
+#define ETIMER_CAPTURE_FREE_COUNTING_MODE        (0UL)          /*!< Free counting mode    */
+#define ETIMER_CAPTURE_TRIGGER_COUNTING_MODE     (1UL << 20)    /*!< Trigger counting mode */
+#define ETIMER_CAPTURE_COUNTER_RESET_MODE        (1UL << 17)    /*!< Counter reset mode    */
+
+#define ETIMER_CAPTURE_FALLING_EDGE              (0UL)          /*!< Falling edge trigger timer capture */
+#define ETIMER_CAPTURE_RISING_EDGE               (1UL << 18)    /*!< Rising edge trigger timer capture  */
+#define ETIMER_CAPTURE_FALLING_THEN_RISING_EDGE  (2UL << 18)    /*!< Falling edge then rising edge trigger timer capture */
+#define ETIMER_CAPTURE_RISING_THEN_FALLING_EDGE  (3UL << 18)    /*!< Rising edge then falling edge trigger timer capture */
+
+#define ETIMER_TIMEOUT_TRIGGER                   (0UL)          /*!< Timer timeout trigger other modules */
+#define ETIMER_CAPTURE_TRIGGER                   (1UL << 11)    /*!< Timer capture trigger other modules */
+
+#define ETIMER_COUNTER_RISING_EDGE               (1UL << 13)    /*!< Counter increase on rising edge  */
+#define ETIMER_COUNTER_FALLING_EDGE              (0UL)          /*!< Counter increase on falling edge */
+
+/*@}*/ /* end of group ETIMER_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_ETIMER_EXPORTED_FUNCTIONS ETIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief This macro is used to set new Timer compared value
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @param[in] u32Value  Timer compare value. Valid values are between 2 to 0xFFFFFF
+  * @return None
+  * \hideinitializer
+  */
+#define ETIMER_SET_CMP_VALUE(timer, u32Value) \
+    do{\
+        if((timer) == 0) {\
+            outpw(REG_ETMR0_CMPR, u32Value);\
+        } else if((timer) == 1) {\
+            outpw(REG_ETMR1_CMPR, u32Value);\
+        } else if((timer) == 2) {\
+            outpw(REG_ETMR2_CMPR, u32Value);\
+        } else {\
+            outpw(REG_ETMR3_CMPR, u32Value);\
+        }\
+    }while(0)
+
+/**
+  * @brief This macro is used to set new Timer prescale value
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @param[in] u32Value  Timer prescale value. Valid values are between 0 to 0xFF
+  * @return None
+  * @note Clock input is divided by (prescale + 1) before it is fed into timer
+  * \hideinitializer
+  */
+#define ETIMER_SET_PRESCALE_VALUE(timer, u32Value) \
+    do{\
+        if((timer) == 0) {\
+            outpw(REG_ETMR0_PRECNT, u32Value);\
+        } else if((timer) == 1) {\
+            outpw(REG_ETMR1_PRECNT, u32Value);\
+        } else if((timer) == 2) {\
+            outpw(REG_ETMR2_PRECNT, u32Value);\
+        } else {\
+            outpw(REG_ETMR3_PRECNT, u32Value);\
+        }\
+    }while(0)
+
+/**
+* @brief      Select Timer operating mode
+*
+* @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+* @param[in]  u32OpMode   Operation mode. Possible options are
+*                         - \ref ETIMER_ONESHOT_MODE
+*                         - \ref ETIMER_PERIODIC_MODE
+*                         - \ref ETIMER_TOGGLE_MODE
+*                         - \ref ETIMER_CONTINUOUS_MODE
+*
+* @return     None
+* \hideinitializer
+*/
+#define ETIMER_SET_OPMODE(timer, u32OpMode)   \
+            do{\
+        if((timer) == 0) {\
+            outpw(REG_ETMR0_CTL, (inpw(REG_ETMR0_CTL)&~0x30) | u32OpMode);\
+        } else if((timer) == 1) {\
+            outpw(REG_ETMR1_CTL, (inpw(REG_ETMR1_CTL)&~0x30) | u32OpMode);\
+        } else if((timer) == 2) {\
+            outpw(REG_ETMR2_CTL, (inpw(REG_ETMR2_CTL)&~0x30) | u32OpMode);\
+        } else {\
+            outpw(REG_ETMR3_CTL, (inpw(REG_ETMR3_CTL)&~0x30) | u32OpMode);\
+        }\
+    }while(0)
+
+/*
+ * @brief This macro is used to check if specify Timer is inactive or active
+ * @param[in] timer ETIMER number. Range from 0 ~ 3
+ * @return timer is activate or inactivate
+ * @retval 0 Timer 24-bit up counter is inactive
+ * @retval 1 Timer 24-bit up counter is active
+ * \hideinitializer
+ */
+static __inline int ETIMER_Is_Active(UINT timer)
+{
+    int reg;
+
+    if (timer == 0)
+    {
+        reg = inpw(REG_ETMR0_CTL);
+    }
+    else if (timer == 1)
+    {
+        reg = inpw(REG_ETMR1_CTL);
+    }
+    else if (timer == 2)
+    {
+        reg = inpw(REG_ETMR2_CTL);
+    }
+    else
+    {
+        reg = inpw(REG_ETMR3_CTL);
+    }
+    return reg & 0x80 ? 1 : 0;
+}
+
+/**
+  * @brief This function is used to start Timer counting
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_Start(UINT timer)
+{
+
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) | 1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) | 1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) | 1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) | 1);
+    }
+}
+
+/**
+  * @brief This function is used to stop Timer counting
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_Stop(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) & ~1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) & ~1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) & ~1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) & ~1);
+    }
+}
+
+/**
+  * @brief This function is used to enable the Timer wake-up function
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  * @note  To wake the system from power down mode, timer clock source must be ether LXT or LIRC
+  */
+static __inline void ETIMER_EnableWakeup(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) | 4);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) | 4);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) | 4);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) | 4);
+    }
+}
+
+/**
+  * @brief This function is used to disable the Timer wake-up function
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_DisableWakeup(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) & ~4);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) & ~4);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) & ~4);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) & ~4);
+    }
+}
+
+
+/**
+  * @brief This function is used to enable the capture pin detection de-bounce function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_EnableCaptureDebounce(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) | 0x400000);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) | 0x400000);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) | 0x400000);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) | 0x400000);
+    }
+}
+
+/**
+  * @brief This function is used to disable the capture pin detection de-bounce function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_DisableCaptureDebounce(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) & ~0x400000);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) & ~0x400000);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) & ~0x400000);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) & ~0x400000);
+    }
+}
+
+
+/**
+  * @brief This function is used to enable the Timer time-out interrupt function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_EnableInt(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_IER, inpw(REG_ETMR0_IER) | 1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_IER, inpw(REG_ETMR1_IER) | 1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_IER, inpw(REG_ETMR2_IER) | 1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_IER, inpw(REG_ETMR3_IER) | 1);
+    }
+}
+
+/**
+  * @brief This function is used to disable the Timer time-out interrupt function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_DisableInt(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_IER, inpw(REG_ETMR0_IER) & ~1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_IER, inpw(REG_ETMR1_IER) & ~1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_IER, inpw(REG_ETMR2_IER) & ~1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_IER, inpw(REG_ETMR3_IER) & ~1);
+    }
+}
+
+/**
+  * @brief This function is used to enable the Timer capture trigger interrupt function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_EnableCaptureInt(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_IER, inpw(REG_ETMR0_IER) | 2);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_IER, inpw(REG_ETMR1_IER) | 2);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_IER, inpw(REG_ETMR2_IER) | 2);
+    }
+    else
+    {
+        outpw(REG_ETMR3_IER, inpw(REG_ETMR3_IER) | 2);
+    }
+}
+
+/**
+  * @brief This function is used to disable the Timer capture trigger interrupt function.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_DisableCaptureInt(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_IER, inpw(REG_ETMR0_IER) & ~2);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_IER, inpw(REG_ETMR1_IER) & ~2);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_IER, inpw(REG_ETMR2_IER) & ~2);
+    }
+    else
+    {
+        outpw(REG_ETMR3_IER, inpw(REG_ETMR3_IER) & ~2);
+    }
+}
+
+/**
+  * @brief This function indicates Timer time-out interrupt occurred or not.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer time-out interrupt occurred or not
+  * @retval 0 Timer time-out interrupt did not occur
+  * @retval 1 Timer time-out interrupt occurred
+  */
+static __inline UINT ETIMER_GetIntFlag(UINT timer)
+{
+    int reg;
+
+    if (timer == 0)
+    {
+        reg = inpw(REG_ETMR0_ISR);
+    }
+    else if (timer == 1)
+    {
+        reg = inpw(REG_ETMR1_ISR);
+    }
+    else if (timer == 2)
+    {
+        reg = inpw(REG_ETMR2_ISR);
+    }
+    else
+    {
+        reg = inpw(REG_ETMR3_ISR);
+    }
+    return reg & 1;
+}
+
+/**
+  * @brief This function clears the Timer time-out interrupt flag.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_ClearIntFlag(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_ISR, 1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_ISR, 1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_ISR, 1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_ISR, 1);
+    }
+}
+
+/**
+  * @brief This function indicates Timer capture interrupt occurred or not.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer capture interrupt occurred or not
+  * @retval 0 Timer capture interrupt did not occur
+  * @retval 1 Timer capture interrupt occurred
+  */
+static __inline UINT ETIMER_GetCaptureIntFlag(UINT timer)
+{
+    int reg;
+
+    if (timer == 0)
+    {
+        reg = inpw(REG_ETMR0_ISR);
+    }
+    else if (timer == 1)
+    {
+        reg = inpw(REG_ETMR1_ISR);
+    }
+    else if (timer == 2)
+    {
+        reg = inpw(REG_ETMR2_ISR);
+    }
+    else
+    {
+        reg = inpw(REG_ETMR3_ISR);
+    }
+    return (reg & 2) >> 1;
+}
+
+/**
+  * @brief This function clears the Timer capture interrupt flag.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_ClearCaptureIntFlag(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_ISR, 2);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_ISR, 2);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_ISR, 2);
+    }
+    else
+    {
+        outpw(REG_ETMR3_ISR, 2);
+    }
+}
+
+/**
+* @brief This function gets the Timer capture falling edge flag.
+* @param[in] timer ETIMER number. Range from 0 ~ 5
+* @return None
+*/
+static __inline UINT8 ETIMER_GetCaptureFallingEdgeFlag(UINT timer)
+{
+    UINT ret;
+
+    if (timer == 0)
+    {
+        ret = inpw(REG_ETMR0_ISR);
+    }
+    else if (timer == 1)
+    {
+        ret = inpw(REG_ETMR1_ISR);
+    }
+    else if (timer == 2)
+    {
+        ret = inpw(REG_ETMR2_ISR);
+    }
+    else
+    {
+        ret = inpw(REG_ETMR3_ISR);
+    }
+    return (ret & (1 << 6)) >> 6;
+}
+
+/*
+  * @brief This function indicates Timer has waked up system or not.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer has waked up system or not
+  * @retval 0 Timer did not wake up system
+  * @retval 1 Timer wake up system
+  */
+static __inline UINT ETIMER_GetWakeupFlag(UINT timer)
+{
+    int reg;
+
+    if (timer == 0)
+    {
+        reg = inpw(REG_ETMR0_ISR);
+    }
+    else if (timer == 1)
+    {
+        reg = inpw(REG_ETMR1_ISR);
+    }
+    else if (timer == 2)
+    {
+        reg = inpw(REG_ETMR2_ISR);
+    }
+    else
+    {
+        reg = inpw(REG_ETMR3_ISR);
+    }
+    return (reg & 0x10) >> 4;
+}
+
+/**
+  * @brief This function clears the Timer wakeup interrupt flag.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+static __inline void ETIMER_ClearWakeupFlag(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_ISR, 0x10);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_ISR, 0x10);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_ISR, 0x10);
+    }
+    else
+    {
+        outpw(REG_ETMR3_ISR, 0x10);
+    }
+}
+
+/**
+  * @brief This function gets the Timer compare value.
+  * @param[in] timer ETIMER number. Range from 0 ~ 5
+  * @return Timer compare data value
+  */
+static __inline UINT ETIMER_GetCompareData(UINT timer)
+{
+
+    if (timer == 0)
+    {
+        return inpw(REG_ETMR0_CMPR);
+    }
+    else if (timer == 1)
+    {
+        return inpw(REG_ETMR1_CMPR);
+    }
+    else if (timer == 2)
+    {
+        return inpw(REG_ETMR2_CMPR);
+    }
+    else
+    {
+        return inpw(REG_ETMR3_CMPR);
+    }
+}
+
+/**
+  * @brief This function gets the Timer capture data.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer capture data value
+  */
+static __inline UINT ETIMER_GetCaptureData(UINT timer)
+{
+
+    if (timer == 0)
+    {
+        return inpw(REG_ETMR0_TCAP);
+    }
+    else if (timer == 1)
+    {
+        return inpw(REG_ETMR1_TCAP);
+    }
+    else if (timer == 2)
+    {
+        return inpw(REG_ETMR2_TCAP);
+    }
+    else
+    {
+        return inpw(REG_ETMR3_TCAP);
+    }
+}
+
+/**
+  * @brief This function reports the current timer counter value.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer counter value
+  */
+static __inline UINT ETIMER_GetCounter(UINT timer)
+{
+    if (timer == 0)
+    {
+        return inpw(REG_ETMR0_DR);
+    }
+    else if (timer == 1)
+    {
+        return inpw(REG_ETMR1_DR);
+    }
+    else if (timer == 2)
+    {
+        return inpw(REG_ETMR2_DR);
+    }
+    else
+    {
+        return inpw(REG_ETMR3_DR);
+    }
+}
+
+static __inline UINT ETIMER_ClearCounter(UINT timer)
+{
+    if (timer == 0)
+    {
+        return outpw(REG_ETMR0_DR, 0);
+    }
+    else if (timer == 1)
+    {
+        return outpw(REG_ETMR1_DR, 0);
+    }
+    else if (timer == 2)
+    {
+        return outpw(REG_ETMR2_DR, 0);
+    }
+    else
+    {
+        return outpw(REG_ETMR3_DR, 0);
+    }
+}
+UINT ETIMER_Open(UINT timer, UINT u32Mode, UINT u32Freq);
+void ETIMER_Close(UINT timer);
+void ETIMER_Delay(UINT timer, UINT u32Usec);
+void ETIMER_EnableCapture(UINT timer, UINT u32CapMode, UINT u32Edge);
+void ETIMER_DisableCapture(UINT timer);
+UINT ETIMER_GetModuleClock(UINT timer);
+
+/*@}*/ /* end of group N9H30_ETIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_ETIMER_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_ETIMER_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_fmi.h

@@ -0,0 +1,315 @@
+/**************************************************************************//**
+ * @file     fmi.h
+ * @brief    N9H30 FMI eMMC driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+
+#ifndef __NU_FMI_H__
+#define __NU_FMI_H__
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_FMI_Driver FMI Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_FMI_EXPORTED_CONSTANTS FMI Exported Constants
+  @{
+*/
+
+/**
+    @addtogroup FMI_CONST FMI Bit Field Definition
+    Constant Definitions for FMI Controller
+@{ */
+
+#define FMI_DMACTL_DMAEN_Pos             (0)                                               /*!< FMI DMACTL: DMAEN Position             */
+#define FMI_DMACTL_DMAEN_Msk             (0x1ul << FMI_DMACTL_DMAEN_Pos)                   /*!< FMI DMACTL: DMAEN Mask                 */
+
+#define FMI_DMACTL_DMARST_Pos            (1)                                               /*!< FMI DMACTL: DMARST Position            */
+#define FMI_DMACTL_DMARST_Msk            (0x1ul << FMI_DMACTL_DMARST_Pos)                  /*!< FMI DMACTL: DMARST Mask                */
+
+#define FMI_DMACTL_SGEN_Pos              (3)                                               /*!< FMI DMACTL: SGEN Position              */
+#define FMI_DMACTL_SGEN_Msk              (0x1ul << FMI_DMACTL_SGEN_Pos)                    /*!< FMI DMACTL: SGEN Mask                  */
+
+#define FMI_DMACTL_DMABUSY_Pos           (9)                                               /*!< FMI DMACTL: DMABUSY Position           */
+#define FMI_DMACTL_DMABUSY_Msk           (0x1ul << FMI_DMACTL_DMABUSY_Pos)                 /*!< FMI DMACTL: DMABUSY Mask               */
+
+#define FMI_DMASA_ORDER_Pos              (0)                                               /*!< FMI DMASA: ORDER Position              */
+#define FMI_DMASA_ORDER_Msk              (0x1ul << FMI_DMASA_ORDER_Pos)                    /*!< FMI DMASA: ORDER Mask                  */
+
+#define FMI_DMASA_DMASA_Pos              (1)                                               /*!< FMI DMASA: DMASA Position              */
+#define FMI_DMASA_DMASA_Msk              (0x7ffffffful << FMI_DMASA_DMASA_Pos)             /*!< FMI DMASA: DMASA Mask                  */
+
+#define FMI_DMABCNT_BCNT_Pos             (0)                                               /*!< FMI DMABCNT: BCNT Position             */
+#define FMI_DMABCNT_BCNT_Msk             (0x3fffffful << FMI_DMABCNT_BCNT_Pos)             /*!< FMI DMABCNT: BCNT Mask                 */
+
+#define FMI_DMAINTEN_ABORTIEN_Pos        (0)                                               /*!< FMI DMAINTEN: ABORTIEN Position        */
+#define FMI_DMAINTEN_ABORTIEN_Msk        (0x1ul << FMI_DMAINTEN_ABORTIEN_Pos)              /*!< FMI DMAINTEN: ABORTIEN Mask            */
+
+#define FMI_DMAINTEN_WEOTIEN_Pos         (1)                                               /*!< FMI DMAINTEN: WEOTIEN Position         */
+#define FMI_DMAINTEN_WEOTIEN_Msk         (0x1ul << FMI_DMAINTEN_WEOTIEN_Pos)               /*!< FMI DMAINTEN: WEOTIEN Mask             */
+
+#define FMI_DMAINTSTS_ABORTIF_Pos        (0)                                               /*!< FMI DMAINTSTS: ABORTIF Position        */
+#define FMI_DMAINTSTS_ABORTIF_Msk        (0x1ul << FMI_DMAINTSTS_ABORTIF_Pos)              /*!< FMI DMAINTSTS: ABORTIF Mask            */
+
+#define FMI_DMAINTSTS_WEOTIF_Pos         (1)                                               /*!< FMI DMAINTSTS: WEOTIF Position         */
+#define FMI_DMAINTSTS_WEOTIF_Msk         (0x1ul << FMI_DMAINTSTS_WEOTIF_Pos)               /*!< FMI DMAINTSTS: WEOTIF Mask             */
+
+#define FMI_CTL_CTLRST_Pos               (0)                                               /*!< FMI CTL: CTLRST Position               */
+#define FMI_CTL_CTLRST_Msk               (0x1ul << FMI_CTL_CTLRST_Pos)                     /*!< FMI CTL: CTLRST Mask                   */
+
+#define FMI_CTL_EMMCEN_Pos               (1)                                               /*!< FMI CTL: EMMCEN Position               */
+#define FMI_CTL_EMMCEN_Msk               (0x1ul << FMI_CTL_EMMCEN_Pos)                     /*!< FMI CTL: EMMCEN Mask                   */
+
+#define FMI_CTL_NANDEN_Pos               (1)                                               /*!< FMI CTL: NANDEN Position               */
+#define FMI_CTL_NANDEN_Msk               (0x1ul << FMI_CTL_NANDEN_Pos)                     /*!< FMI CTL: NANDEN Mask                   */
+
+#define FMI_INTEN_DTAIEN_Pos             (0)                                               /*!< FMI INTEN: DTAIEN Position             */
+#define FMI_INTEN_DTAIEN_Msk             (0x1ul << FMI_INTEN_DTAIEN_Pos)                   /*!< FMI INTEN: DTAIEN Mask                 */
+
+#define FMI_INTSTS_DTAIF_Pos            (0)                                                /*!< FMI INTSTS: DTAIF Position             */
+#define FMI_INTSTS_DTAIF_Msk            (0x1ul << FMI_INTSTS_DTAIF_Pos)                    /*!< FMI INTSTS: DTAIF Mask                 */
+
+#define FMI_EMMCCTL_COEN_Pos            (0)                                                /*!< FMI EMMCCTL: COEN Position             */
+#define FMI_EMMCCTL_COEN_Msk            (0x1ul << FMI_EMMCCTL_COEN_Pos)                    /*!< FMI EMMCCTL: COEN Mask                 */
+
+#define FMI_EMMCCTL_RIEN_Pos            (1)                                                /*!< FMI EMMCCTL: RIEN Position             */
+#define FMI_EMMCCTL_RIEN_Msk            (0x1ul << FMI_EMMCCTL_RIEN_Pos)                    /*!< FMI EMMCCTL: RIEN Mask                 */
+
+#define FMI_EMMCCTL_DIEN_Pos            (2)                                                /*!< FMI EMMCCTL: DIEN Position             */
+#define FMI_EMMCCTL_DIEN_Msk            (0x1ul << FMI_EMMCCTL_DIEN_Pos)                    /*!< FMI EMMCCTL: DIEN Mask                 */
+
+#define FMI_EMMCCTL_DOEN_Pos            (3)                                                /*!< FMI EMMCCTL: DOEN Position             */
+#define FMI_EMMCCTL_DOEN_Msk            (0x1ul << FMI_EMMCCTL_DOEN_Pos)                    /*!< FMI EMMCCTL: DOEN Mask                 */
+
+#define FMI_EMMCCTL_R2EN_Pos            (4)                                                /*!< FMI EMMCCTL: R2EN Position             */
+#define FMI_EMMCCTL_R2EN_Msk            (0x1ul << FMI_EMMCCTL_R2EN_Pos)                    /*!< FMI EMMCCTL: R2EN Mask                 */
+
+#define FMI_EMMCCTL_CLK74OEN_Pos        (5)                                                /*!< FMI EMMCCTL: CLK74OEN Position         */
+#define FMI_EMMCCTL_CLK74OEN_Msk        (0x1ul << FMI_EMMCCTL_CLK74OEN_Pos)                /*!< FMI EMMCCTL: CLK74OEN Mask             */
+
+#define FMI_EMMCCTL_CLK8OEN_Pos         (6)                                                /*!< FMI EMMCCTL: CLK8OEN Position          */
+#define FMI_EMMCCTL_CLK8OEN_Msk         (0x1ul << FMI_EMMCCTL_CLK8OEN_Pos)                 /*!< FMI EMMCCTL: CLK8OEN Mask              */
+
+#define FMI_EMMCCTL_CLKKEEP0_Pos        (7)                                                /*!< FMI EMMCCTL: CLKKEEP0 Position         */
+#define FMI_EMMCCTL_CLKKEEP0_Msk        (0x1ul << FMI_EMMCCTL_CLKKEEP0_Pos)                /*!< FMI EMMCCTL: CLKKEEP0 Mask             */
+
+#define FMI_EMMCCTL_CMDCODE_Pos         (8)                                                /*!< FMI EMMCCTL: CMDCODE Position          */
+#define FMI_EMMCCTL_CMDCODE_Msk         (0x3ful << FMI_EMMCCTL_CMDCODE_Pos)                /*!< FMI EMMCCTL: CMDCODE Mask              */
+
+#define FMI_EMMCCTL_CTLRST_Pos          (14)                                               /*!< FMI EMMCCTL: CTLRST Position           */
+#define FMI_EMMCCTL_CTLRST_Msk          (0x1ul << FMI_EMMCCTL_CTLRST_Pos)                  /*!< FMI EMMCCTL: CTLRST Mask               */
+
+#define FMI_EMMCCTL_DBW_Pos             (15)                                               /*!< FMI EMMCCTL: DBW Position              */
+#define FMI_EMMCCTL_DBW_Msk             (0x1ul << FMI_EMMCCTL_DBW_Pos)                     /*!< FMI EMMCCTL: DBW Mask                  */
+
+#define FMI_EMMCCTL_BLKCNT_Pos          (16)                                               /*!< FMI EMMCCTL: BLKCNT Position           */
+#define FMI_EMMCCTL_BLKCNT_Msk          (0xfful << FMI_EMMCCTL_BLKCNT_Pos)                 /*!< FMI EMMCCTL: BLKCNT Mask               */
+
+#define FMI_EMMCCTL_SDNWR_Pos           (24)                                               /*!< FMI EMMCCTL: SDNWR Position            */
+#define FMI_EMMCCTL_SDNWR_Msk           (0xful << FMI_EMMCCTL_SDNWR_Pos)                   /*!< FMI EMMCCTL: SDNWR Mask                */
+
+#define FMI_EMMCCMD_ARGUMENT_Pos        (0)                                                /*!< FMI EMMCCMD: ARGUMENT Position         */
+#define FMI_EMMCCMD_ARGUMENT_Msk        (0xfffffffful << FMI_EMMCCMD_ARGUMENT_Pos)         /*!< FMI EMMCCMD: ARGUMENT Mask             */
+
+#define FMI_EMMCINTEN_BLKDIEN_Pos       (0)                                                /*!< FMI EMMCINTEN: BLKDIEN Position        */
+#define FMI_EMMCINTEN_BLKDIEN_Msk       (0x1ul << FMI_EMMCINTEN_BLKDIEN_Pos)               /*!< FMI EMMCINTEN: BLKDIEN Mask            */
+
+#define FMI_EMMCINTEN_CRCIEN_Pos        (1)                                                /*!< FMI EMMCINTEN: CRCIEN Position         */
+#define FMI_EMMCINTEN_CRCIEN_Msk        (0x1ul << FMI_EMMCINTEN_CRCIEN_Pos)                /*!< FMI EMMCINTEN: CRCIEN Mask             */
+
+#define FMI_EMMCINTEN_RTOIEN_Pos        (12)                                               /*!< FMI EMMCINTEN: RTOIEN Position         */
+#define FMI_EMMCINTEN_RTOIEN_Msk        (0x1ul << FMI_EMMCINTEN_RTOIEN_Pos)                /*!< FMI EMMCINTEN: RTOIEN Mask             */
+
+#define FMI_EMMCINTEN_DITOIEN_Pos       (13)                                               /*!< FMI EMMCINTEN: DITOIEN Position        */
+#define FMI_EMMCINTEN_DITOIEN_Msk       (0x1ul << FMI_EMMCINTEN_DITOIEN_Pos)               /*!< FMI EMMCINTEN: DITOIEN Mask            */
+
+#define FMI_EMMCINTSTS_BLKDIF_Pos       (0)                                                /*!< FMI EMMCINTSTS: BLKDIF Position        */
+#define FMI_EMMCINTSTS_BLKDIF_Msk       (0x1ul << FMI_EMMCINTSTS_BLKDIF_Pos)               /*!< FMI EMMCINTSTS: BLKDIF Mask            */
+
+#define FMI_EMMCINTSTS_CRCIF_Pos        (1)                                                /*!< FMI EMMCINTSTS: CRCIF Position         */
+#define FMI_EMMCINTSTS_CRCIF_Msk        (0x1ul << FMI_EMMCINTSTS_CRCIF_Pos)                /*!< FMI EMMCINTSTS: CRCIF Mask             */
+
+#define FMI_EMMCINTSTS_CRC7_Pos         (2)                                                /*!< FMI EMMCINTSTS: CRC7 Position          */
+#define FMI_EMMCINTSTS_CRC7_Msk         (0x1ul << FMI_EMMCINTSTS_CRC7_Pos)                 /*!< FMI EMMCINTSTS: CRC7 Mask              */
+
+#define FMI_EMMCINTSTS_CRC16_Pos        (3)                                                /*!< FMI EMMCINTSTS: CRC16 Position         */
+#define FMI_EMMCINTSTS_CRC16_Msk        (0x1ul << FMI_EMMCINTSTS_CRC16_Pos)                /*!< FMI EMMCINTSTS: CRC16 Mask             */
+
+#define FMI_EMMCINTSTS_CRCSTS_Pos       (4)                                                /*!< FMI EMMCINTSTS: CRCSTS Position        */
+#define FMI_EMMCINTSTS_CRCSTS_Msk       (0x7ul << FMI_EMMCINTSTS_CRCSTS_Pos)               /*!< FMI EMMCINTSTS: CRCSTS Mask            */
+
+#define FMI_EMMCINTSTS_DAT0STS_Pos      (7)                                                /*!< FMI EMMCINTSTS: DAT0STS Position       */
+#define FMI_EMMCINTSTS_DAT0STS_Msk      (0x1ul << FMI_EMMCINTSTS_DAT0STS_Pos)              /*!< FMI EMMCINTSTS: DAT0STS Mask           */
+
+#define FMI_EMMCINTSTS_RTOIF_Pos        (12)                                               /*!< FMI EMMCINTSTS: RTOIF Position         */
+#define FMI_EMMCINTSTS_RTOIF_Msk        (0x1ul << FMI_EMMCINTSTS_RTOIF_Pos)                /*!< FMI EMMCINTSTS: RTOIF Mask             */
+
+#define FMI_EMMCINTSTS_DINTOIF_Pos      (13)                                               /*!< FMI EMMCINTSTS: DINTOIF Position       */
+#define FMI_EMMCINTSTS_DINTOIF_Msk      (0x1ul << FMI_EMMCINTSTS_DINTOIF_Pos)              /*!< FMI EMMCINTSTS: DINTOIF Mask           */
+
+#define FMI_EMMCRESP0_RESPTK0_Pos       (0)                                                /*!< FMI EMMCRESP0: RESPTK0 Position        */
+#define FMI_EMMCRESP0_RESPTK0_Msk       (0xfffffffful << FMI_EMMCRESP0_RESPTK0_Pos)        /*!< FMI EMMCRESP0: RESPTK0 Mask            */
+
+#define FMI_EMMCRESP1_RESPTK1_Pos       (0)                                                /*!< FMI EMMCRESP1: RESPTK1 Position        */
+#define FMI_EMMCRESP1_RESPTK1_Msk       (0xfful << FMI_EMMCRESP1_RESPTK1_Pos)              /*!< FMI EMMCRESP1: RESPTK1 Mask            */
+
+#define FMI_EMMCBLEN_BLKLEN_Pos         (0)                                                /*!< FMI EMMCBLEN: BLKLEN Position          */
+#define FMI_EMMCBLEN_BLKLEN_Msk         (0x7fful << FMI_EMMCBLEN_BLKLEN_Pos)               /*!< FMI EMMCBLEN: BLKLEN Mask              */
+
+#define FMI_EMMCTOUT_TOUT_Pos           (0)                                                /*!< FMI EMMCTOUT: TOUT Position            */
+#define FMI_EMMCTOUT_TOUT_Msk           (0xfffffful << FMI_EMMCTOUT_TOUT_Pos)              /*!< FMI EMMCTOUT: TOUT Mask                */
+
+/**@}*/ /* FMI_CONST */
+
+//--- define type of SD card or MMC
+#define EMMC_TYPE_UNKNOWN     0           /*!< Card Type - Unknoen \hideinitializer */
+#define EMMC_TYPE_SD_HIGH     1           /*!< Card Type - SDH \hideinitializer */
+#define EMMC_TYPE_SD_LOW      2           /*!< Card Type - SD \hideinitializer */
+#define EMMC_TYPE_MMC         3           /*!< Card Type - MMC \hideinitializer */
+#define EMMC_TYPE_EMMC        4           /*!< Card Type - eMMC \hideinitializer */
+
+#define EMMC_ERR_ID       0xFFFF0180                /*!< FMI Error ID          \hideinitializer */
+#define EMMC_TIMEOUT          (EMMC_ERR_ID|0x01)    /*!< FMI Error - Timeout   \hideinitializer */
+#define EMMC_NO_MEMORY        (EMMC_ERR_ID|0x02)    /*!< FMI Error - No Memory \hideinitializer */
+/* EMMC error */
+#define EMMC_NO_CARD          (EMMC_ERR_ID|0x10)    /*!< FMI Error - No card   \hideinitializer */
+#define EMMC_ERR_DEVICE       (EMMC_ERR_ID|0x11)    /*!< FMI Error - device err \hideinitializer */
+#define EMMC_INIT_TIMEOUT     (EMMC_ERR_ID|0x12)    /*!< FMI Error - init timeout \hideinitializer */
+#define EMMC_SELECT_ERROR     (EMMC_ERR_ID|0x13)    /*!< FMI Error - select err \hideinitializer */
+#define EMMC_WRITE_PROTECT    (EMMC_ERR_ID|0x14)    /*!< FMI Error - write protect \hideinitializer */
+#define EMMC_INIT_ERROR       (EMMC_ERR_ID|0x15)    /*!< FMI Error - init err \hideinitializer */
+#define EMMC_CRC7_ERROR       (EMMC_ERR_ID|0x16)    /*!< FMI Error - crc7 err \hideinitializer */
+#define EMMC_CRC16_ERROR      (EMMC_ERR_ID|0x17)    /*!< FMI Error - crc16 err \hideinitializer */
+#define EMMC_CRC_ERROR        (EMMC_ERR_ID|0x18)    /*!< FMI Error - crc err \hideinitializer */
+#define EMMC_CMD8_ERROR       (EMMC_ERR_ID|0x19)    /*!< FMI Error - CMD8 err \hideinitializer */
+
+#define SD_FREQ         25000      /*!< Unit: kHz. Output 25MHz to SD  \hideinitializer */
+#define SDHC_FREQ       50000      /*!< Unit: kHz. Output 50MHz to SDH  \hideinitializer */
+#define MMC_FREQ        20000      /*!< Unit: kHz. Output 20MHz to MMC  \hideinitializer */
+#define EMMC_FREQ       26000      /*!< Unit: kHz. Output 26MHz to eMMC  \hideinitializer */
+
+/*@}*/ /* end of group N9H30_FMI_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_FMI_EXPORTED_TYPEDEF FMI Exported Type Defines
+  @{
+*/
+/** \brief  Structure type of Card information.
+ */
+typedef struct eMMC_info_t
+{
+    unsigned int    CardType;       /*!< SDHC, SD, or MMC */
+    unsigned int    RCA;            /*!< relative card address */
+    unsigned char   IsCardInsert;   /*!< card insert state */
+    unsigned int    totalSectorN;   /*!< total sector number */
+    unsigned int    diskSize;       /*!< disk size in Kbytes */
+    int             sectorSize;     /*!< sector size in bytes */
+} EMMC_INFO_T;
+
+/*@}*/ /* end of group N9H30_FMI_EXPORTED_TYPEDEF */
+
+/// @cond HIDDEN_SYMBOLS
+extern EMMC_INFO_T eMMC;
+extern unsigned char volatile _fmi_eMMCDataReady;
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup N9H30_FMI_EXPORTED_FUNCTIONS FMI Exported Functions
+  @{
+*/
+
+
+/**
+ *  @brief    Enable specified interrupt.
+ *
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref FMI_EMMCINTEN_BLKDIEN_Msk / \ref FMI_EMMCINTEN_CRCIEN_Msk /
+ *                           \ref FMI_EMMCINTEN_RTOIEN_Msk / \ref FMI_EMMCINTEN_DITOIEN_Msk /
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define FMI_EMMC_ENABLE_INT(u32IntMask)    (outpw(REG_FMI_EMMCINTEN, inpw(REG_FMI_EMMCINTEN)|(u32IntMask)))
+
+/**
+ *  @brief    Disable specified interrupt.
+ *
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref FMI_EMMCINTEN_BLKDIEN_Msk / \ref FMI_EMMCINTEN_CRCIEN_Msk /
+ *                           \ref FMI_EMMCINTEN_RTOIEN_Msk / \ref FMI_EMMCINTEN_DITOIEN_Msk /
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define FMI_EMMC_DISABLE_INT(u32IntMask)    (outpw(REG_FMI_EMMCINTEN, inpw(REG_FMI_EMMCINTEN) & ~(u32IntMask)))
+
+/**
+ *  @brief    Get specified interrupt flag/status.
+ *
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref FMI_EMMCINTSTS_BLKDIF_Msk / \ref FMI_EMMCINTSTS_CRCIF_Msk / \ref FMI_EMMCINTSTS_CRC7_Msk /
+ *                           \ref FMI_EMMCINTSTS_CRC16_Msk / \ref FMI_EMMCINTSTS_CRCSTS_Msk / \ref FMI_EMMCINTSTS_DAT0STS_Msk /
+ *                           \ref FMI_EMMCINTSTS_RTOIF_Msk / \ref FMI_EMMCINTSTS_DINTOIF_Msk /
+ *
+ *  @return  0 = The specified interrupt is not happened.
+ *            1 = The specified interrupt is happened.
+ * \hideinitializer
+ */
+#define FMI_EMMC_GET_INT_FLAG(u32IntMask) ((inpw(REG_FMI_EMMCINTSTS)&(u32IntMask))?1:0)
+
+
+/**
+ *  @brief    Clear specified interrupt flag/status.
+ *
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref FMI_EMMCINTSTS_BLKDIF_Msk / \ref FMI_EMMCINTSTS_CRCIF_Msk /
+ *                           \ref FMI_EMMCINTSTS_RTOIF_Msk / \ref FMI_EMMCINTSTS_DINTOIF_Msk
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define FMI_EMMC_CLR_INT_FLAG(u32IntMask) (outpw(REG_FMI_EMMCINTSTS, u32IntMask))
+
+
+/**
+ *  @brief    Check eMMC Card inserted or removed.
+ *
+ *  @return   1: Card inserted.
+ *            0: Card removed.
+ * \hideinitializer
+ */
+#define FMI_EMMC_IS_CARD_PRESENT() (eMMC.IsCardInsert)
+
+/**
+ *  @brief    Get eMMC Card capacity.
+ *
+ *  @return   eMMC Card capacity. (unit: KByte)
+ * \hideinitializer
+ */
+#define FMI_EMMC_GET_CARD_CAPACITY()  (eMMC.diskSize)
+
+
+void eMMC_Open(void);
+void eMMC_Probe(void);
+unsigned int eMMC_Read(unsigned char *pu8BufAddr, unsigned int u32StartSec, unsigned int u32SecCount);
+unsigned int eMMC_Write(unsigned char *pu8BufAddr, unsigned int u32StartSec, unsigned int u32SecCount);
+void FMI_SetReferenceClock(unsigned int u32Clock);
+void eMMC_Open_Disk(void);
+void eMMC_Close_Disk(void);
+
+
+/*@}*/ /* end of group N9H30_FMI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_FMI_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif  //end of __NU_FMI_H__
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_gpio.h

@@ -0,0 +1,162 @@
+/**************************************************************************//**
+* @file     gpio.h
+* @version  V1.00
+* @brief    N9H30 GPIO driver header file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_GPIO_H__
+#define __NU_GPIO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  MODE Constant Definitions                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+/// @cond HIDDEN_SYMBOLS
+#ifndef GPIO_ERR_PORT_BUSY
+#define GPIO_ERR_PORT_BUSY      -1
+#define GPIO_ERR_UNSUPPORTED    -2
+#define GPIO_ERR_BIT_BUSY       -3
+#define SUCCESSFUL              0
+#endif
+/// @endcond HIDDEN_SYMBOLS
+
+#define MAX_PORT 10  /*!< GPIO Port Number */
+
+#define GPIOA_MASK  0x0000FFFF  /*!< GPIO Port A Mask */
+#define GPIOB_MASK  0x0000FFFF  /*!< GPIO Port B Mask */
+#define GPIOC_MASK  0x00007FFF  /*!< GPIO Port C Mask */
+#define GPIOD_MASK  0x0000FFFF  /*!< GPIO Port D Mask */
+#define GPIOE_MASK  0x0000FFFF  /*!< GPIO Port E Mask */
+#define GPIOF_MASK  0x0000FFFF  /*!< GPIO Port F Mask */
+#define GPIOG_MASK  0x0000FFFF  /*!< GPIO Port G Mask */
+#define GPIOH_MASK  0x0000FFFF  /*!< GPIO Port H Mask */
+#define GPIOI_MASK  0x0000FFFF  /*!< GPIO Port I Mask */
+#define GPIOJ_MASK  0x0000003F  /*!< GPIO Port J Mask */
+
+/// @cond HIDDEN_SYMBOLS
+typedef INT32(*GPIO_CALLBACK)(UINT32 status, UINT32 userData);
+typedef INT32(*EINT_CALLBACK)(UINT32 status, UINT32 userData);
+/// @endcond HIDDEN_SYMBOLS
+
+/** \brief  Structure type of GPIO_PORT
+ */
+typedef enum
+{
+    GPIOA = 0x000, /*!< Port A offset of GPIO base address      */
+    GPIOB = 0x040, /*!< Port B offset of GPIO base address      */
+    GPIOC = 0x080, /*!< Port C offset of GPIO base address      */
+    GPIOD = 0x0C0, /*!< Port D offset of GPIO base address      */
+    GPIOE = 0x100, /*!< Port E offset of GPIO base address      */
+    GPIOF = 0x140, /*!< Port F offset of GPIO base address      */
+    GPIOG = 0x180, /*!< Port G offset of GPIO base address      */
+    GPIOH = 0x1C0, /*!< Port H offset of GPIO base address      */
+    GPIOI = 0x200, /*!< Port I offset of GPIO base address      */
+    GPIOJ = 0x240, /*!< Port J offset of GPIO base address      */
+} GPIO_PORT;
+
+/** \brief  Structure type of GPIO_DIR
+ */
+typedef enum
+{
+    DIR_INPUT,   /*!< GPIO Output mode      */
+    DIR_OUTPUT   /*!< GPIO Input mode      */
+} GPIO_DIR;
+
+/** \brief  Structure type of GPIO_PULL
+ */
+typedef enum
+{
+    NO_PULL_UP, /*!< GPIO Pull-Up Disable */
+    PULL_UP,    /*!< GPIO Pull-Up Enable */
+    PULL_DOWN   /*!< GPIO Pull-Down Enable */
+} GPIO_PULL;
+
+/** \brief  Structure type of GPIO_DRV
+ */
+typedef enum
+{
+    DRV_LOW,   /*!< GPIO Set to Low */
+    DRV_HIGH   /*!< GPIO Set to High */
+} GPIO_DRV;
+
+/** \brief  Structure type of GPIO_NIRQ
+ */
+typedef enum
+{
+    NIRQ0 = 0, /*!< External interrupt 0 */
+    NIRQ1,     /*!< External interrupt 1 */
+    NIRQ2,     /*!< External interrupt 2 */
+    NIRQ3,     /*!< External interrupt 3 */
+    NIRQ4,     /*!< External interrupt 4 */
+    NIRQ5,     /*!< External interrupt 5 */
+    NIRQ6,     /*!< External interrupt 6 */
+    NIRQ7,     /*!< External interrupt 7 */
+} GPIO_NIRQ;
+
+/** \brief  Structure type of GPIO_TRIGGER_TYPE
+ */
+typedef enum
+{
+    LOW,                   /*!< Trigger type set low */
+    HIGH,                  /*!< Trigger type set high */
+    FALLING,               /*!< Trigger type set falling edge */
+    RISING,                /*!< Trigger type set rising edge */
+    BOTH_EDGE              /*!< Trigger type set falling edge and rising edge */
+} GPIO_TRIGGER_TYPE;
+
+/// @cond HIDDEN_SYMBOLS
+/// @endcond HIDDEN_SYMBOLS
+
+/*@}*/ /* end of group N9H30_GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/* General GPIO bit function */
+INT32 GPIO_OpenBit(GPIO_PORT port, UINT32 bit, GPIO_DIR direction, GPIO_PULL pull);
+INT32 GPIO_CloseBit(GPIO_PORT port, UINT32 bit);
+INT32 GPIO_SetBit(GPIO_PORT port, UINT32 bit);
+INT32 GPIO_ClrBit(GPIO_PORT port, UINT32 bit);
+INT32 GPIO_ReadBit(GPIO_PORT port, UINT32 bit);
+INT32 GPIO_SetBitDir(GPIO_PORT port, UINT32 bit, GPIO_DIR direction);
+INT32 GPIO_EnableTriggerType(GPIO_PORT port, UINT32 bit, GPIO_TRIGGER_TYPE triggerType);
+INT32 GPIO_DisableTriggerType(GPIO_PORT port, UINT32 bit);
+
+/* External GPIO interrupt function */
+INT32 GPIO_EnableDebounce(INT32 debounceClkSel);
+INT32 GPIO_DisableDebounce(void);
+
+/*@}*/ /* end of group N9H30_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_GPIO_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_GPIO_H__
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_i2c.h

@@ -0,0 +1,105 @@
+/**************************************************************************//**
+* @file     i2c.h
+* @brief    N9H30 I2C driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_I2C_H__
+#define __NU_I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2C_Driver I2C Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2C_EXPORTED_CONSTANTS I2C Exported Constants
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+/*-----------------------------------------*/
+/* marco, type and constant definitions    */
+/*-----------------------------------------*/
+#define I2C_MAX_BUF_LEN         450
+
+/*-----------------------------------------*/
+/* global interface variables declarations */
+/*-----------------------------------------*/
+/*
+    bit map in CMDR
+*/
+#define I2C_CMD_START           0x10
+#define I2C_CMD_STOP            0x08
+#define I2C_CMD_READ            0x04
+#define I2C_CMD_WRITE           0x02
+#define I2C_CMD_NACK            0x01
+
+/*
+    for transfer use
+*/
+#define I2C_WRITE               0x00
+#define I2C_READ                0x01
+
+#define I2C_STATE_NOP           0x00
+#define I2C_STATE_READ          0x01
+#define I2C_STATE_WRITE         0x02
+#define I2C_STATE_PROBE         0x03
+
+/*
+    i2c register offset
+*/
+#define     I2C_CSR     (0x00)  /*!< Control and Status Register */
+#define     I2C_DIVIDER (0x04)  /*!< Clock Prescale Register */
+#define     I2C_CMDR    (0x08)  /*!< Command Register */
+#define     I2C_SWR     (0x0C)  /*!< Software Mode Control Register */
+#define     I2C_RxR     (0x10)  /*!< Data Receive Register */
+#define     I2C_TxR     (0x14)  /*!< Data Transmit Register */
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*
+    ioctl commands
+*/
+#define I2C_IOC_SET_DEV_ADDRESS     0  /*!< Set device slave address */
+#define I2C_IOC_SET_SUB_ADDRESS     1  /*!< Set sub address */
+#define I2C_IOC_SET_SPEED           2  /*!< Set I2C interface speed */
+
+/*
+    error code
+*/
+#define I2C_ERR_ID                  0xFFFF1100           /*!< I2C library ID                  */
+#define I2C_ERR_NOERROR             (0x00)               /*!< No error                        */
+#define I2C_ERR_LOSTARBITRATION     (0x01 | I2C_ERR_ID)  /*!< Arbitration lost error          */
+#define I2C_ERR_BUSBUSY             (0x02 | I2C_ERR_ID)  /*!< Bus busy error                  */
+#define I2C_ERR_NACK                (0x03 | I2C_ERR_ID)  /*!< data transfer error             */
+#define I2C_ERR_SLAVENACK           (0x04 | I2C_ERR_ID)  /*!< slave not respond after address */
+#define I2C_ERR_NODEV               (0x05 | I2C_ERR_ID)  /*!< Wrong device                    */
+#define I2C_ERR_BUSY                (0x06 | I2C_ERR_ID)  /*!< Device busy                     */
+#define I2C_ERR_IO                  (0x07 | I2C_ERR_ID)  /*!< Interface not open              */
+#define I2C_ERR_NOTTY               (0x08 | I2C_ERR_ID)  /*!< Command not support             */
+
+/*@}*/ /* end of group N9H30_I2C_EXPORTED_CONSTANTS */
+
+/*@}*/ /* end of group N9H30_I2C_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_I2C_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_i2s.h

@@ -0,0 +1,130 @@
+/**************************************************************************//**
+* @file     i2s.h
+* @brief    N9H30 I2S driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_I2S_H__
+#define __NU_I2S_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2S_EXPORTED_CONSTANTS I2S Exported Constants
+  @{
+*/
+
+#define I2S_ERR_BUSY    -1 /*!< Interface is busy  */
+#define I2S_ERR_IO      -2 /*!< IO contril error  */
+
+#define I2S_DISABLE     0  /*!< Enable I2S  */
+#define I2S_ENABLE      1  /*!< Disable I2S  */
+
+#define I2S_PLAY        0  /*!< Play I2S audio */
+#define I2S_REC         1  /*!< Reocrd I2S audio  */
+
+#define PCM_PLAY        0  /*!< Play PCM audio  */
+#define PCM_REC         1  /*!< Record PCM audio  */
+
+#define I2S_SET_PLAY                0   /*!< Start or stop to play  */
+#define I2S_START_PLAY  0  /*!< Start to play  */
+#define I2S_STOP_PLAY   1  /*!< Stop to play  */
+
+#define I2S_SET_RECORD              1   /*!< Start or stop to record  */
+#define I2S_START_REC   0  /*!< Start to record  */
+#define I2S_STOP_REC    1  /*!< Stop to record  */
+
+#define I2S_SELECT_BLOCK            2   /*!< Select block function */
+#define I2S_BLOCK_I2S   0  /*!< Select I2S function  */
+#define I2S_BLOCK_PCM   1  /*!< Select PCM function  */
+
+#define I2S_SELECT_BIT              3  /*!< Select data bit width  */
+#define I2S_BIT_WIDTH_8 0  /*!< 8-bit  */
+#define I2S_BIT_WIDTH_16    1  /*!< 16-bit  */
+#define I2S_BIT_WIDTH_24    2  /*!< 24-bit  */
+
+#define I2S_SET_PLAY_DMA_INT_SEL    4   /*!< Select play DMA interrupt request  */
+#define I2S_SET_REC_DMA_INT_SEL     5   /*!< Select record DMA interrupt request  */
+#define I2S_DMA_INT_END     0  /*!< End of buffer  */
+#define I2S_DMA_INT_HALF       1  /*!< Half of buffer  */
+#define I2S_DMA_INT_QUARTER    2  /*!< Quarter of buffer  */
+#define I2S_DMA_INT_EIGHTH     3  /*!< Eighth of buffer  */
+
+#define I2S_SET_ZEROCROSS           6  /*!< Enable or disable zero cross function  */
+#define I2S_SET_DMACOUNTER          7  /*!< Enable or disable DMA counter function  */
+
+#define I2S_SET_CHANNEL             8   /*!< Set channel number  */
+#define I2S_CHANNEL_P_I2S_ONE         2  /*!< I2S one channel  */
+#define I2S_CHANNEL_P_I2S_TWO         3  /*!< I2S two channels  */
+#define I2S_CHANNEL_P_PCM_TWO         3  /*!< PCM two slots  */
+#define I2S_CHANNEL_P_PCM_TWO_SLOT1   0  /*!< PCM two slots with all slot1 data  */
+#define I2S_CHANNEL_P_PCM_TWO_SLOT0   1  /*!< PCM two slots with all slot0 data  */
+#define I2S_CHANNEL_P_PCM_ONE_SLOT0   2  /*!< PCM one slot with all slot0 data  */
+
+#define I2S_CHANNEL_R_I2S_LEFT_PCM_SLOT0    1 /*!< I2S left channel or PCM slot0  */
+#define I2S_CHANNEL_R_I2S_RIGHT_PCM_SLOT1   2 /*!< I2S right channel or PCM slot1  */
+#define I2S_CHANNEL_R_I2S_TWO           3 /*!< I2S two channels  */
+
+#define I2S_SET_MODE                9   /*!< Select master or slave mode  */
+#define I2S_MODE_MASTER  0  /*!< master mode  */
+#define I2S_MODE_SLAVE   1  /*!< slave mode  */
+
+#define I2S_SET_SPLITDATA           10  /*!< Enable or disable split data function */
+#define I2S_SET_DMA_ADDRESS         11  /*!< Set DMA address  */
+#define I2S_SET_DMA_LENGTH          12  /*!< Set DMA length  */
+#define I2S_GET_DMA_CUR_ADDRESS     13  /*!< Get current DMA address  */
+
+#define I2S_SET_I2S_FORMAT          14  /*!< Select I2S format  */
+#define I2S_FORMAT_I2S  0  /*!< I2S format  */
+#define I2S_FORMAT_MSB  1  /*!< MSB foramt */
+
+#define I2S_SET_I2S_CALLBACKFUN     15  /*!< Install play or record call-back function */
+
+#define I2S_SET_PCMSLOT             16  /*!< Set PCM interface start position of slot */
+#define PCM_SLOT1_IN        0  /*!< Slot-1 in position */
+#define PCM_SLOT1_OUT       1  /*!< Slot-1 out position */
+#define PCM_SLOT2_IN        2  /*!< Slot-2 in position */
+#define PCM_SLOT2_OUT       3  /*!< Slot-2 out position */
+
+#define I2S_SET_PCM_FS_PERIOD       17  /*!< Set PCM FS pulse period */
+
+/*@}*/ /* end of group N9H30_I2S_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+
+int32_t i2sOpen(void);
+void i2sClose(void);
+void i2sInit(void);
+int32_t i2sIoctl(uint32_t cmd, uint32_t arg0, uint32_t arg1);
+void i2sSetSampleRate(uint32_t u32SourceClockRate, uint32_t u32SampleRate, uint32_t u32DataBit, uint32_t u32Channel);
+void i2sSetMCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32SampleRate);
+void i2sSetPCMBCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32Rate);
+
+/*@}*/ /* end of group N9H30_I2S_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_I2S_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_I2S_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_jpeg.h

@@ -0,0 +1,398 @@
+/**************************************************************************//**
+* @file     jpeg.h
+* @brief    N9H30 JPEG driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_JPEG_H__
+#define __NU_JPEG_H__
+
+#include "nu_jpegcodec.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_JPEG_Driver JPEG Driver
+  @{
+*/
+
+/** @addtogroup N9H30_JPEG_EXPORTED_CONSTANTS JPEG Exported Constants
+  @{
+*/
+
+
+/// @cond HIDDEN_SYMBOLS
+// Define bits mask
+#define NVTBIT(start,end) ((0xFFFFFFFFUL >> (31 - start)) & (0xFFFFFFFFUL >>end  << end))
+/// @endcond HIDDEN_SYMBOLS
+
+
+//JMCR
+#define RESUMEI     BIT9                /*!< Resume JPEG Operation for Input On-the-Fly Mode          */
+#define RESUMEO     BIT8                /*!< Resume JPEG Operation for Output On-the-Fly Mode   */
+#define ENC_DEC     BIT7                /*!< JPEG Encode/Decode Mode   */
+#define WIN_DEC     BIT6                /*!< JPEG Window Decode Mode   */
+#define PRI         BIT5                /*!< Encode Primary Image   */
+#define THB         BIT4                /*!< Encode Thumbnail Image   */
+#define EY422       BIT3                /*!< Encode Image Format   */
+#define QT_BUSY     BIT2                /*!< Quantization-Table Busy Status (Read-Only)   */
+#define ENG_RST     BIT1                /*!< Soft Reset JPEG Engine (Except JPEG Control Registers)   */
+#define JPG_EN      BIT0                /*!< JPEG Engine Operation Control  */
+
+//JHEADER
+#define P_JFIF      BIT7                /*!< Primary JPEG Bit-stream Include JFIF Header           */
+#define P_HTAB      BIT6                /*!< Primary JPEG Bit-stream Include Huffman-Table  */
+#define P_QTAB      BIT5                /*!< Primary JPEG Bit-stream Include Quantization-Table  */
+#define P_DRI       BIT4                /*!< Primary JPEG Bit-stream Include Restart Interval  */
+#define T_JFIF      BIT3                /*!< Thumbnail JPEG Bit-stream Include JFIF Header  */
+#define T_HTAB      BIT2                /*!< Thumbnail JPEG Bit-stream Include Huffman-Table  */
+#define T_QTAB      BIT1                /*!< Thumbnail JPEG Bit-stream Include Quantization-Table  */
+#define T_DRI       BIT0                /*!< Thumbnail JPEG Bit-stream Include Restart Interval  */
+
+//JITCR
+#define Dec_Scatter_Gather  BIT18
+#define DEC_OTF             BIT17               /*!< Decoder on the fly with VPE                                        */
+#define ARGB8888            BIT16               /*!< ARGB8888  */
+#define PLANAR_ON           BIT15               /*!< Packet On  */
+#define ORDER               BIT14               /*!< Decode Packet Data Order  */
+#define RGB_555_565         BIT13               /*!< RGB555 & RGB565  */
+#define ROTATE              NVTBIT(12,11)       /*!< Encode Image Rotate  */
+#define DYUV_MODE           NVTBIT(10,8)        /*!< Decoded Image YUV Color Format (Read-Only)  */
+#define EXIF                BIT7                /*!< Encode Quantization-Table & Huffman-Table Header Format Selection  */
+#define EY_ONLY             BIT6                /*!< Encode Gray-level (Y-component Only) Image                     */
+#define DHEND               BIT5                /*!< Header Decode Complete Stop Enable  */
+#define DTHB                BIT4                /*!< Decode Thumbnail Image Only  */
+#define E3QTAB              BIT3                /*!< Numbers of Quantization-Table are Used For Encode  */
+#define D3QTAB              BIT2                /*!< Numbers of Quantization-Table are Used For Decode (Read-Only)  */
+#define ERR_DIS             BIT1                /*!< Decode Error Engine Abort  */
+#define PDHTAB              BIT0                /*!< Programmable Huffman-Table Function For Decode  */
+
+//JPRIQC
+#define P_QADJUST   NVTBIT(7,4)         /*!< Primary Quantization-Table Adjustment       */
+#define P_QVS       NVTBIT(3,0)         /*!< Primary Quantization-Table Scaling Control  */
+
+//JTHBQC
+#define T_QADJUST   NVTBIT(7,4)         /*!< Thumbnail Quantization-Table Adjustment       */
+#define T_QVS       NVTBIT(3,0)         /*!< Thumbnail Quantization-Table Scaling Control  */
+
+//JPRIWH
+#define P_HEIGHT    NVTBIT(27,16)           /*!< Primary Encode Image Height   */
+#define P_WIDTH     NVTBIT(11,0)            /*!< Primary Encode Image Width    */
+
+//JTHBWH
+#define T_HEIGHT    NVTBIT(27,16)           /*!< Thumbnail Encode Image Height  */
+#define T_WIDTH     NVTBIT(11,0)            /*!< Thumbnail Encode Image Width   */
+
+//JPRST
+#define P_RST       NVTBIT(7,0)             /*!< Primary Encode Restart Interval Value  */
+
+//JTRST
+#define T_RST       NVTBIT(7,0)             /*!< Thumbnail Encode Restart Interval Value  */
+
+//JDECWH
+#define DEC_HEIGHT  NVTBIT(31,16)           /*!< 13-bit Bit Stream Buffer threshold  */
+#define DEC_WIDTH   NVTBIT(15,0)            /*!< 13-bit Header Offset Address        */
+
+//JINTCR
+#define JPG_DOW_INTE    BIT28               /*!< Decoding Output Wait Interrupt Enable  */
+#define JPG_DOW_INTS    BIT24               /*!< Status of Decoding Output Wait  */
+#define JPG_WAITI       BIT23               /*!< JPEG Input Wait Status (Read-Only)  */
+#define JPG_WAITO       BIT22               /*!< JPEG Output Wait Status (Read-Only)  */
+#define BAbort          BIT16               /*!< JPEG Memory Access Error Status (Read-Only)  */
+#define CER_INTE        BIT15               /*!< Un-complete Capture On-The-Fly Frame Occur Interrupt Enable  */
+#define DHE_INTE        BIT14               /*!< JPEG Header Decode End Wait Interrupt Enable  */
+#define IPW_INTE        BIT13               /*!< Input Wait Interrupt Enable  */
+#define OPW_INTE        BIT12               /*!< Output Wait Interrupt Enable  */
+#define ENC_INTE        BIT11               /*!< Encode Complete Interrupt Enable  */
+#define DEC_INTE        BIT10               /*!< Decode Complete Interrupt Enable  */
+#define DER_INTE        BIT9                /*!< Decode Error Interrupt Enable  */
+#define EER_INTE        BIT8                /*!< Encode (On-The-Fly) Error Interrupt Enable  */
+#define CER_INTS        BIT7                /*!< Un-complete Capture On-The-Fly Frame Occur Interrupt Status  */
+#define DHE_INTS        BIT6                /*!< JPEG  Header Decode End Wait Interrupt Status  */
+#define IPW_INTS        BIT5                /*!< Input Wait Interrupt Status  */
+#define OPW_INTS        BIT4                /*!< Output Wait Interrupt Status  */
+#define ENC_INTS        BIT3                /*!< Encode Complete Interrupt Status  */
+#define DEC_INTS        BIT2                /*!< Decode Complete Interrupt Status  */
+#define DER_INTS        BIT1                /*!< Decode Error Interrupt Status  */
+#define EER_INTS        BIT0                /*!< Encode (On-The-Fly) Error Interrupt Status  */
+
+//JPEG_BSBAD
+#define BIST_ST         NVTBIT(23,16)       /*!< Internal SRAM BIST Status (Read-Only)  */
+#define TEST_DOUT       NVTBIT(15,8)        /*!< Test Data Output (Read-Only)  */
+#define TEST_ON         BIT7                /*!< Test Enable  */
+#define BIST_ON         BIT6                /*!< Internal SRAM BIST Mode Enable  */
+#define BIST_FINI       BIT5                /*!< Internal SRAM BIST Mode Finish (Read-Only)  */
+#define BSBAD_BIST_FAIL BIT4                /*!< Internal SRAM BIST Mode Fail (Read-Only)  */
+#define TEST_SEL        NVTBIT(3,0)         /*!< Test Data Selection  */
+
+//JWINDEC0
+#define MCU_S_Y     NVTBIT(24,16)           /*!< MCU Start Position Y For Window Decode Mode  */
+#define MCU_S_X     NVTBIT(8,0)             /*!< MCU Start Position X For Window Decode Mode  */
+
+//JWINDEC1
+#define MCU_E_Y     NVTBIT(24,16)           /*!< MCU End Position Y For Window Decode Mode  */
+#define MCU_E_X     NVTBIT(8,0)             /*!< MCU End Position X For Window Decode Mode  */
+
+//JWINDEC2
+#define WD_WIDTH    NVTBIT(11,0))           /*!< Image Width (Y-Stride) For Window Decode Mode  */
+
+//JMACR
+#define FLY_SEL     NVTBIT(29,24)       /*!< Hardware Memory On-the-Fly Access Image Buffer-Size Selection for Encode  */
+#define FLY_TYPE    NVTBIT(23,22)       /*!< Dual/Single buffer on-the fly   */
+#define BSF_SEL     NVTBIT(17,8)        /*!< Memory On-the-Fly Access Bitstream Buffer-Size Selection  */
+#define FLY_ON      BIT7                /*!< Hardware Memory On-the-Fly Access Mode  */
+#define IP_SF_ON    BIT3                /*!< Software Memory On-the-Fly Access Mode for Data Input  */
+#define OP_SF_ON    BIT2                /*!< Software Memory On-the-Fly Access Mode for Data Output  */
+#define ENC_MODE    NVTBIT(1,0)         /*!< JPEG Memory Address Mode Control  */
+
+//JPSCALU
+#define JPSCALU_8X  BIT6                /*!< Primary Image Up-Scaling For Encode  */
+#define A_JUMP      BIT2                /*!< Reserve Buffer Size In JPEG Bit-stream For Software Application  */
+
+//JPSCALD
+#define PSX_ON      BIT15               /*!< Primary Image Horizontal Down-Scaling For Encode/Decode  */
+#define PS_LPF_ON   BIT14               /*!< Primary Image Down-Scaling Low Pass Filter For Decode  */
+#define PSCALX_F    NVTBIT(12,8)        /*!< Primary Image Horizontal Down-Scaling Factor  */
+#define PSCALY_F    NVTBIT(5,0)         /*!< Primary Image Vertical Down-Scaling Factor  */
+
+//JTSCALD
+#define TSX_ON      BIT15               /*!< Thumbnail Image Horizontal Down-Scaling For Encode/Decode  */
+#define TSCALX_F    NVTBIT(14,8)        /*!< Thumbnail Image Horizontal Down-Scaling Factor  */
+#define TSCALY_F    NVTBIT(7,0)         /*!< Thumbnail Image Vertical Down-Scaling Factor  */
+
+//JDBCR
+#define DBF_EN      BIT7                /*!< Dual Buffering Control  */
+#define IP_BUF      BIT4                /*!< Input Dual Buffer Control  */
+
+//JRESERVE
+#define RES_SIZE    NVTBIT(15,0)        /*!< Primary Encode Bit-stream Reserved Size  */
+
+//JOFFSET
+#define OFFSET_SIZE NVTBIT(23,0)        /*!< Primary/Thumbnail Starting Address Offset Size  */
+
+//JFSTRIDE
+#define F_STRIDE    NVTBIT(23,0)        /*!< JPEG Encode Bit-stream Frame Stride  */
+
+//JYADDR0
+#define Y_IADDR0    NVTBIT(31,0)        /*!< JPEG Y Component Frame Buffer-0 Starting Address  */
+
+//JUADDR0
+#define U_IADDR0    NVTBIT(31,0)        /*!< JPEG U Component Frame Buffer-0 Starting Address  */
+
+//JVADDR0
+#define V_IADDR0    NVTBIT(31,0)        /*!< JPEG V Component Frame Buffer-0 Starting Address  */
+
+//JYADDR1
+#define Y_IADDR1    NVTBIT(31,0)        /*!< JPEG Y Component Frame Buffer-1 Starting Address  */
+
+//JUADDR1
+#define U_IADDR1    NVTBIT(31,0)        /*!< JPEG U Component Frame Buffer-1 Starting Address  */
+
+//JVADDR1
+#define V_IADDR1    NVTBIT(31,0)        /*!< JPEG V Component Frame Buffer-1 Starting Address  */
+
+//JYSTRIDE
+#define Y_STRIDE    NVTBIT(11,0)        /*!< JPEG Y Component Frame Buffer Stride  */
+
+//JUSTRIDE
+#define U_STRIDE    NVTBIT(11,0)        /*!< JPEG U Component Frame Buffer Stride  */
+
+//JVSTRIDE
+#define V_STRIDE    NVTBIT(11,0)        /*!< JPEG V Component Frame Buffer Stride  */
+
+//JIOADDR0
+#define IO_IADDR0   NVTBIT(31,0)        /*!< JPEG Bit-stream Frame Buffer-0 Starting Address  */
+
+//JIOADDR1
+#define IO_IADDR1   NVTBIT(31,0)        /*!< JPEG Bit-stream Frame Buffer-1 Starting Address  */
+
+//JPRI_SIZE
+#define PRI_SIZE    NVTBIT(23,0)        /*!< JPEG Primary Image Encode Bit-stream Size  */
+
+//JTHB_SIZE
+#define THB_SIZE    NVTBIT(15,0)        /*!< JPEG Thumbnail Image Encode Bit-stream Size  */
+
+//JUPRAT
+#define S_HEIGHT    NVTBIT(29,16)       /*!< JPEG Image Height Up-Scale Ratio  */
+#define S_WIDTH     NVTBIT(13,0)        /*!< JPEG Image Width Up-Scale Ratio  */
+
+//JBSFIFO
+#define BSFIFO_HT   NVTBIT(6,4)         /*!< Bit-stream FIFO High-Threshold Control  */
+#define BSFIFO_LT   NVTBIT(2,0)         /*!< Bit-stream FIFO Low-Threshold Control  */
+
+//JSRCH
+#define JSRCH_JSRCH NVTBIT(11,0)        /*!< JPEG Encode Source Image Height  */
+
+/*@}*/ /* end of group N9H30_JPEG_EXPORTED_CONSTANTS */
+
+/// @cond HIDDEN_SYMBOLS
+
+//Define for Interrupt Status
+#define JPEG_EER_INTS   EER_INTS
+#define JPEG_DER_INTS   DER_INTS
+#define JPEG_DEC_INTS   DEC_INTS
+#define JPEG_ENC_INTS   ENC_INTS
+#define JPEG_DHE_INTS   DHE_INTS
+#define JPEG_IPW_INTS   IPW_INTS
+
+//Define for Scaling
+#define JPEG_ENC_UPSCALE_MODE               0
+#define JPEG_DEC_PACKET_DOWNSCALE_MODE      1
+#define JPEG_DEC_PLANAR_DOWNSCALE_MODE              2
+#define JPEG_ENC_PLANAR_PRIMARY_DOWNSCALE_MODE       3
+#define JPEG_ENC_PLANAR_THUMBNAIL_DOWNSCALE_MODE  4
+
+//Define for Interrupt Enable
+#define JPEG_EER_INTE   ERR_INTE
+#define JPEG_DER_INTE   DER_INTE
+#define JPEG_DEC_INTE   DEC_INTE
+#define JPEG_ENC_INTE   ENC_INTE
+#define JPEG_DHE_INTE   DHE_INTE
+#define JPEG_IPW_INTE   IPW_INTE
+
+//Register
+#define     REG_JMCR        JMCR             /*!< JPEG Mode Control Register  */
+#define     REG_JHEADER     JHEADER          /*!< JPEG Encode Header Control Register  */
+#define     REG_JITCR       JITCR            /*!< JPEG Image Type Control Register  */
+#define     REG_JPRIQC      JPRIQC           /*!< JPEG Primary Q-Table Control Register  */
+#define     REG_JTHBQC      JTHBQC           /*!< JPEG Thumbnail Q-Table Control Register  */
+#define     REG_JPRIWH      JPRIWH           /*!< JPEG Encode Primary Width/Height Register  */
+#define     REG_JTHBWH      JTHBWH           /*!< JPEG Encode Thumbnail Width/Height Register  */
+#define     REG_JPRST       JPRST            /*!< JPEG Encode Primary Restart Interval Register  */
+#define     REG_JTRST       JTRST            /*!< JPEG Encode Thumbnail Restart Interval  */
+#define     REG_JDECWH      JDECWH           /*!< JPEG Decode Image Width/Height Register  */
+#define     REG_JINTCR      JINTCR           /*!< JPEG Interrupt Control and Status Register  */
+#define     REG_JTEST       JTEST            /*!< JPEG Test Control Register  */
+#define     REG_JWINDEC0    JWINDEC0         /*!< JPEG Window Decode Mode Control Register 0  */
+#define     REG_JWINDEC1    JWINDEC1         /*!< JPEG Window Decode Mode Control Register 1  */
+#define     REG_JWINDEC2    JWINDEC2         /*!< JPEG Window Decode Mode Control Register 2  */
+#define     REG_JMACR       JMACR            /*!< JPEG Memory Address Mode Control Register  */
+#define     REG_JPSCALU     JPSCALU          /*!< JPEG Primary Scaling-Up Control Register  */
+#define     REG_JPSCALD     JPSCALD          /*!< JPEG Primary Scaling-Down Control Register  */
+#define     REG_JTSCALD     JTSCALD          /*!< JPEG Thumbnail  Scaling-Down Control Register  */
+#define     REG_JDBCR       JDBCR            /*!< JPEG Dual-Buffer Control Register  */
+#define     REG_JRESERVE    JRESERVE         /*!< JPEG Encode Primary Bit-stream Reserved Size Register  */
+#define     REG_JOFFSET     JOFFSET          /*!< JPEG Offset Between Primary & Thumbnail Register  */
+#define     REG_JFSTRIDE    JFSTRIDE         /*!< JPEG Encode Bit-stream Frame Stride Register  */
+#define     REG_JYADDR0     JYADDR0          /*!< JPEG Y Component Frame Buffer-0 Starting Address Register  */
+#define     REG_JUADDR0     JUADDR0          /*!< JPEG U Component Frame Buffer-0 Starting Address Register  */
+#define     REG_JVADDR0     JVADDR0          /*!< JPEG V Component Frame Buffer-0 Starting Address Register  */
+#define     REG_JYADDR1     JYADDR1          /*!< JPEG Y Component Frame Buffer-1 Starting Address Register  */
+#define     REG_JUADDR1     JUADDR1          /*!< JPEG U Component Frame Buffer-1 Starting Address Register  */
+#define     REG_JVADDR1     JVADDR1          /*!< JPEG V Component Frame Buffer-1 Starting Address Register  */
+#define     REG_JYSTRIDE    JYSTRIDE         /*!< JPEG Y Component Frame Buffer Stride Register  */
+#define     REG_JUSTRIDE    JUSTRIDE         /*!< JPEG U Component Frame Buffer Stride Register  */
+#define     REG_JVSTRIDE    JVSTRIDE         /*!< JPEG V Component Frame Buffer Stride Register  */
+#define     REG_JIOADDR0    JIOADDR0         /*!< JPEG Bit-stream Frame Buffer-0 Starting Address Register  */
+#define     REG_JIOADDR1    JIOADDR1         /*!< JPEG Bit-stream Frame Buffer-1 Starting Address Register  */
+#define     REG_JPRI_SIZE   JPRI_SIZE        /*!< JPEG Encode Primary Image Bit-stream Size Register  */
+#define     REG_JTHB_SIZE   JTHB_SIZE        /*!< JPEG Encode Thumbnail Image Bit-stream Size Register  */
+#define     REG_JUPRAT      JUPRAT           /*!< JPEG Encode Up-Scale Ratio Register  */
+#define     REG_JBSFIFO     JBSFIFO          /*!< JPEG Bit-stream FIFO Control Register  */
+#define     REG_JSRCH       JSRCH            /*!< JPEG Encode Source Image Height  */
+#define     REG_JQTAB0      JQTAB0           /*!< JPEG Quantization-Table 0 Register  */
+#define     REG_JQTAB1      JQTAB1           /*!< JPEG Quantization-Table 1 Register  */
+#define     REG_JQTAB2      JQTAB2           /*!< JPEG Quantization-Table 2 Register  */
+
+//Export functions
+#define JPEG_SET_YADDR(u32Address)              outp32(REG_JYADDR0, u32Address)
+#define JPEG_SET_UADDR(u32Address)              outp32(REG_JUADDR0, u32Address)
+#define JPEG_SET_VADDR(u32Address)              outp32(REG_JVADDR0, u32Address)
+#define JPEG_GET_YADDR()                        inp32(REG_JYADDR0)
+#define JPEG_GET_UADDR()                        inp32(REG_JUADDR0)
+#define JPEG_GET_VADDR()                        inp32(REG_JVADDR0)
+#define JPEG_SET_YSTRIDE(u32Stride)             outp32(REG_JYSTRIDE, u32Stride)
+#define JPEG_SET_USTRIDE(u32Stride)             outp32(REG_JUSTRIDE, u32Stride)
+#define JPEG_SET_VSTRIDE(u32Stride)             outp32(REG_JVSTRIDE, u32Stride)
+#define JPEG_GET_YSTRIDE()                      inp32(REG_JYSTRIDE)
+#define JPEG_GET_USTRIDE()                      inp32(REG_JUSTRIDE)
+#define JPEG_GET_VSTRIDE()                      inp32(REG_JVSTRIDE)
+#define JPEG_SET_BITSTREAM_ADDR(u32Address)     outp32(REG_JIOADDR0,u32Address)
+#define JPEG_GET_BITSTREAM_ADDR()               inp32(REG_JIOADDR0)
+#define JPEG_SET_ENC_DEC(u8Mode)                outp32(REG_JMCR, (inp32(REG_JMCR) & ~ENC_DEC) | (u8Mode << 7));
+
+//Encode
+#define JPEG_GET_ENC_PRIMARY_BITSTREAM_SIZE()   inp32(REG_JPRI_SIZE)
+#define JPEG_GET_ENC_THUMBNAIL_BITSTREAM_SIZE() inp32(REG_JTHB_SIZE)
+#define JPEG_SET_SOURCE_IMAGE_HEIGHT(u16Size)   outp32(REG_JSRCH,u16Size)
+#define JPEG_GET_SOURCE_IMAGE_HEIGHT()          inp32(REG_JSRCH)
+#define JPEG_ENC_ENABLE_UPSCALING()             outp32(REG_JPSCALU,inp32(REG_JPSCALU) | JPSCALU_8X)
+#define JPEG_ENC_DISABLE_UPSCALING()            outp32(REG_JPSCALU,inp32(REG_JPSCALU) & ~JPSCALU_8X)
+#define JPEG_ENC_ISENABLE_UPSCALING()           ((inp32(REG_JPSCALU) & JPSCALU_8X) >> 6)
+#define JPEG_ENC_SET_HEADER_CONTROL(u8Control)  outp32(REG_JHEADER, u8Control)
+#define JPEG_ENC_GET_HEADER_CONTROL()           inp32(REG_JHEADER)
+#define JPEG_ENC_SET_RDI_VALUE(u8Value)         outp32(REG_JPRST,u8Value)
+#define JPEG_ENC_GET_RDI_VALUE()                inp32(REG_JPRST)
+
+//Decode
+#define JPEG_DEC_ENABLE_DOWNSCALING()           outp32(REG_JPSCALD, PSX_ON)
+#define JPEG_DEC_ISENABLE_DOWNSCALING()         ((inp32(REG_JPSCALD) & PSX_ON) >> 15)
+#define JPEG_DEC_DISABLE_DOWNSCALING()          outp32(REG_JPSCALD,~PSX_ON)
+#define JPEG_DEC_GET_DECODED_IMAGE_FORMAT()     (inp32(REG_JITCR) & DYUV_MODE)
+#define JPEG_DEC_ENABLE_LOW_PASS_FILTER()       outp32(REG_JPSCALD,inp32(REG_JPSCALD) | PS_LPF_ON)
+#define JPEG_DEC_DISABLE_LOW_PASS_FILTER()      outp32(REG_JPSCALD,inp32(REG_JPSCALD) & ~PS_LPF_ON)
+#define JPEG_DEC_ISENABLE_LOW_PASS_FILTER()     ((inp32(REG_JPSCALD) & PS_LPF_ON) >> 14)
+#define JPEG_DEC_SET_INPUT_WAIT(u16Size)        outp32(REG_JMACR, 0x00400008 | ((u16Size & 0x3FF)<< 8) );
+#define JPEG_DEC_RESUME_INPUT_WAIT()            outp32(REG_JMCR,inp32(REG_JMCR) | RESUMEI);
+#define JPEG_DEC_DISABLE_WINDOWDECODE()         outp32(REG_JMCR, inp32(REG_JMCR) & ~(WIN_DEC));
+
+//Interrupt
+#define JPEG_INT_ENABLE(u32Intflag)             outp32(REG_JINTCR, u32Intflag)
+#define JPEG_INT_DISABLE(u32Intflag)            outp32(REG_JINTCR, inp32 (REG_JINTCR) & ~(u32Intflag))
+#define JPEG_GET_INT_STATUS()                   (inp32(REG_JINTCR) & 0x010000FF)
+#define JPEG_CLEAR_INT(u32Intflag)              outp32(REG_JINTCR, (inp32 (REG_JINTCR) & ~0xFF) | u32Intflag)
+
+static INT jpegSetEncodeMode(UINT8 u8SourceFormat, UINT16 u16JpegFormat);
+static INT jpegSetDecodeMode(UINT32 u8OutputFormat);
+static BOOL jpegPollInt(UINT32 u32Intflag);
+static VOID jpegEncodeTrigger(void);
+static VOID jpegDecodeTrigger(void);
+static VOID jpegGetDecodedDimension(
+    PUINT16 pu16Height,         //Decode/Encode Height
+    PUINT16 pu16Width           //Decode/Encode Width
+);
+static VOID jpegSetDimension(
+    UINT16 u16Height,           //Decode/Encode Height
+    UINT16 u16Width             //Decode/Encode Width
+);
+static VOID jpegGetDimension(
+    PUINT16 pu16Height,         //Decoded Height from bit stream
+    PUINT16 pu16Width           //Decoded Width  from bit stream
+);
+static INT jpegSetWindowDecode(
+    UINT16  u16StartMCUX,   //Start X MCU
+    UINT16  u16StartMCUY,   //Horizontal Scaling Factor
+    UINT16  u16EndMCUX,     //Vertical Scaling Factor
+    UINT16  u16EndMCUY,     //Horizontal Scaling Factor
+    UINT32  u32Stride       //Decode Output Stride
+);
+static INT jpegCalScalingFactor(
+    UINT8   u8Mode,                     //Up / Down Scaling
+    UINT16  u16Height,                  //Original Height
+    UINT16  u16Width,                   //Original Width
+    UINT16  u16ScalingHeight,           //Scaled Height
+    UINT16  u16ScalingWidth,            //Scaled Width
+    PUINT16 pu16RatioH,                 //Horizontal Ratio
+    PUINT16 pu16RatioW                  //Vertical Ratio
+);
+static INT jpegSetScalingFactor(
+    UINT8   u8Mode,                 //Up / Down Scaling
+    UINT16  u16FactorH,             //Vertical Scaling Factor
+    UINT16  u16FactorW              //Horizontal Scaling Factor
+);
+static VOID jpegGetScalingFactor(
+    UINT8   u8Mode,             //Up / Down Scaling
+    PUINT16 pu16FactorH,        //Vertical Scaling Factor
+    PUINT16 pu16FactorW         //Horizontal Scaling Factor
+);
+/// @endcond HIDDEN_SYMBOLS
+
+/*@}*/ /* end of group N9H30_JPEG_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_jpegcodec.h

@@ -0,0 +1,227 @@
+/**************************************************************************//**
+* @file     jpegcodec.h
+* @brief    N9H30 JPEG driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_JPEGCODEC_H__
+#define __NU_JPEGCODEC_H__
+
+//Include header file
+#include "N9H30.h"
+#include "nu_sys.h"
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_JPEG_Driver JPEG Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_JPEG_EXPORTED_CONSTANTS JPEG Exported Constants
+  @{
+*/
+
+#define E_FAIL      0             /*!< JPEG function Error */
+#define E_SUCCESS   1             /*!< JPEG function Success */
+#define E_JPEG_INVALID_PARAM 2    /*!< Input invalid paramater */
+#define E_JPEG_TIMEOUT  3         /*!< JPEG function Time-out */
+
+
+#define JPEG_ENC_PRIMARY        0   /*!< JPEG encode Primary */
+#define JPEG_ENC_THUMBNAIL  1       /*!< JPEG encode Thumbanil */
+
+//Define for Encode input Format
+#define JPEG_ENC_SOURCE_PLANAR  0   /*!< JPEG encode input formate is Planar */
+#define JPEG_ENC_SOURCE_PACKET  1   /*!< JPEG encode input formate is Packet */
+
+//Define for Decode Output Format
+
+//(PLANAR_ON | PDHTAB | DHEND)
+#define JPEG_DEC_PRIMARY_PLANAR_YUV     0x8021  /*!< JPEG decode output Primary Planar YUV */
+//(PDHTAB | DHEND)
+#define JPEG_DEC_PRIMARY_PACKET_YUV422  0x0021  /*!< JPEG decode output Primary Packet YUV422 */
+
+//(PDHTAB | DHEND | ORDER)
+#define JPEG_DEC_PRIMARY_PACKET_RGB555  0x04021  /*!< JPEG decode output Primary Packet RGB555 */
+//(PDHTAB | DHEND | RGB555_565 | ORDER )
+#define JPEG_DEC_PRIMARY_PACKET_RGB565  0x06021  /*!< JPEG decode output Primary Packet RGB565 */
+
+//(PDHTAB | DHEND | ORDER)
+#define JPEG_DEC_PRIMARY_PACKET_RGB555R1    0x404021  /*!< JPEG decode output Primary Packet RGB555R1 */
+//(PDHTAB | DHEND | RGB555_565 | ORDER )
+#define JPEG_DEC_PRIMARY_PACKET_RGB565R1    0x406021  /*!< JPEG decode output Primary Packet RGB565R1 */
+
+#define JPEG_DEC_PRIMARY_PACKET_RGB565R2    0x806021  /*!< JPEG decode output Primary Packet RGB565R2 */
+//(PDHTAB | DHEND | ORDER)
+#define JPEG_DEC_PRIMARY_PACKET_RGB555R2    0x804021  /*!< JPEG decode output Primary Packet RGB555R2 */
+
+//(PDHTAB | DHEND | RGB555_565 | ORDER )
+#define JPEG_DEC_PRIMARY_PACKET_RGB888  0x14021  /*!< JPEG decode Primary Packet RGB888 */
+//(PLANAR_ON | DTHB | PDHTAB)
+#define JPEG_DEC_THUMBNAIL_PLANAR_YUV   0x8031  /*!< JPEG decode Thumbnail Planar YUV */
+//(DTHB | PDHTAB | DHEND)
+#define JPEG_DEC_THUMBNAIL_PACKET_YUV422    0x0031  /*!< JPEG decode Thumbnail Packet YUV422 */
+//(DTHB | PDHTAB | DHEND | ORDER)
+#define JPEG_DEC_THUMBNAIL_PACKET_RGB555    0x4031  /*!< JPEG decode Thumbnail Packet RGB555 */
+
+//Define for Encode Image Format
+#define JPEG_ENC_PRIMARY_YUV420     0xA0  /*!< JPEG encode Primary YUV420 */
+#define JPEG_ENC_PRIMARY_YUV422     0xA8  /*!< JPEG encode Primary YUV422 */
+#define JPEG_ENC_PRIMARY_GRAY       0xA1  /*!< JPEG encode Primary Gray */
+#define JPEG_ENC_THUMBNAIL_YUV420   0x90  /*!< JPEG encode Thumbnail YUV420 */
+#define JPEG_ENC_THUMBNAIL_YUV422   0x98  /*!< JPEG encode Thumbnail YUV422 */
+#define JPEG_ENC_THUMBNAIL_GRAY     0x91  /*!< JPEG encode Thumbnail Gray */
+
+//Define for Decode Image Format
+#define JPEG_DEC_YUV420     0x000  /*!< JPEG decode image formatr is YUV420 */
+#define JPEG_DEC_YUV422     0x100  /*!< JPEG decode image formatr is YUV422 */
+#define JPEG_DEC_YUV444     0x200  /*!< JPEG decode image formatr is YUV444 */
+#define JPEG_DEC_YUV411     0x300  /*!< JPEG decode image formatr is YUV411 */
+#define JPEG_DEC_GRAY       0x400  /*!< JPEG decode image formatr is Gray */
+#define JPEG_DEC_YUV422T    0x500  /*!< JPEG decode image formatr is YUV422T */
+
+//Define for Encode Image Header
+/*P_DRI*/
+#define JPEG_ENC_PRIMARY_DRI    0x10  /*!< JPEG encode image header Primary DRI */
+/*P_QTAB*/
+#define JPEG_ENC_PRIMARY_QTAB   0x20  /*!< JPEG encode image header Primary Q Table */
+/*P_HTAB*/
+#define JPEG_ENC_PRIMARY_HTAB   0x40  /*!< JPEG encode image header Primary H Table */
+/*P_JFIF*/
+#define JPEG_ENC_PRIMARY_JFIF   0x80  /*!< JPEG encode image header Primary JFIF */
+/*T_DRI*/
+#define JPEG_ENC_THUMBNAIL_DRI  0x1  /*!< JPEG encode image header Thumbnail DRI */
+/*T_QTAB*/
+#define JPEG_ENC_THUMBNAIL_QTAB 0x2  /*!< JPEG encode image header Thumbnail Q Table */
+/*T_HTAB*/
+#define JPEG_ENC_THUMBNAIL_HTAB 0x4  /*!< JPEG encode image header Thumbnail H Table */
+/*T_JFIF*/
+#define JPEG_ENC_THUMBNAIL_JFIF 0x8  /*!< JPEG encode image header Thumbnail JFIF */
+
+
+#define JPEG_IOCTL_SET_YADDR                                0    /*!< Set Y Component Frame Buffer-0 Starting Address Register  */
+#define JPEG_IOCTL_SET_YSTRIDE                              1    /*!< Set Y Component Frame Buffer Stride Register  */
+#define JPEG_IOCTL_SET_USTRIDE                              2    /*!< Set U Component Frame Buffer Stride Register  */
+#define JPEG_IOCTL_SET_VSTRIDE                              3    /*!< Set V Component Frame Buffer Stride Register  */
+#define JPEG_IOCTL_SET_BITSTREAM_ADDR                       4    /*!< Set Bit-stream Frame Buffer-0 Starting Address Register  */
+#define JPEG_IOCTL_SET_SOURCE_IMAGE_HEIGHT                  5    /*!< Set JPEG Bit-stream FIFO Control Register */
+#define JPEG_IOCTL_ENC_SET_HEADER_CONTROL                   6    /*!< Set JPEG Encode Header Control Register  */
+#define JPEG_IOCTL_SET_DEFAULT_QTAB                         7    /*!< Set Default Q Table  */
+#define JPEG_IOCTL_SET_DECODE_MODE                          8    /*!< Set Decode Mode  */
+#define JPEG_IOCTL_SET_ENCODE_MODE                          9    /*!< Set Encode Mode  */
+#define JPEG_IOCTL_SET_DIMENSION                            10   /*!< Set Encode Primary Width/Height  */
+#define JPEG_IOCTL_ENCODE_TRIGGER                           11   /*!< Encode Trigger  */
+#define JPEG_IOCTL_DECODE_TRIGGER                           12   /*!< Decode Trigger  */
+#define JPEG_IOCTL_WINDOW_DECODE                            13   /*!< Window Decode Setting  */
+#define JPEG_IOCTL_SET_DECODE_STRIDE                        14   /*!< Set Decode Stride  */
+#define JPEG_IOCTL_SET_DECODE_DOWNSCALE                     15   /*!< Set Decode Downscale  */
+#define JPEG_IOCTL_SET_ENCODE_UPSCALE                       16   /*!< Set Encode Upscale  */
+#define JPEG_IOCTL_SET_HEADERDECODE_CALBACKFUN              17   /*!< Set Header decode call back function  */
+#define JPEG_IOCTL_SET_DECINPUTWAIT_CALBACKFUN              18   /*!< Set Decode Input Wait call back function  */
+#define JPEG_IOCTL_ADJUST_QTAB                              19   /*!< Set Primary or Thumbnail Q Table  */
+#define JPEG_IOCTL_ENC_RESERVED_FOR_SOFTWARE                20   /*!< Set Encode Reserved Size  */
+#define JPEG_IOCTL_SET_UADDR                                21   /*!< Set U Component Frame Buffer-0 Starting Address Register  */
+#define JPEG_IOCTL_SET_VADDR                                22   /*!< Set V Component Frame Buffer-0 Starting Address Register  */
+#define JPEG_IOCTL_SET_ENCODE_PRIMARY_RESTART_INTERVAL      23   /*!< Set Encode Primary restart interval  */
+#define JPEG_IOCTL_SET_ENCODE_THUMBNAIL_RESTART_INTERVAL    24   /*!< Set Encode Thumbnail restart interval  */
+#define JPEG_IOCTL_GET_ENCODE_PRIMARY_RESTART_INTERVAL      25   /*!< Get Encode Primary restart interval  */
+#define JPEG_IOCTL_GET_ENCODE_THUMBNAIL_RESTART_INTERVAL    26   /*!< Get Encode Thumbnail restart interval  */
+#define JPEG_IOCTL_SET_THUMBNAIL_DIMENSION                  27   /*!< Set Encode Thumbnail Width/Height  */
+#define JPEG_IOCTL_SET_ENCODE_SW_OFFSET                     28   /*!< Set Offset Between Primary & Thumbnail Register  */
+#define JPEG_IOCTL_GET_THUMBNAIL_DIMENSION                  29   /*!< Get Thumbnail Width/Height  */
+#define JPEG_IOCTL_GET_ENCODE_SW_OFFSET                     30   /*!< Get Offset Between Primary & Thumbnail Register  */
+#define JPEG_IOCTL_SET_ENCODE_PRIMARY_DOWNSCALE             31   /*!< Set Enciode Primary Downscale  */
+#define JPEG_IOCTL_SET_ENCODE_THUMBNAIL_DOWNSCALE           32   /*!< Set Encode Thumbnail Downscale  */
+#define JPEG_IOCTL_SET_ENCODE_PRIMARY_ROTATE_RIGHT          33   /*!< Set Encode Primary rotate right  */
+#define JPEG_IOCTL_SET_ENCODE_PRIMARY_ROTATE_LEFT           34   /*!< Set Encode Primary rotate left  */
+#define JPEG_IOCTL_SET_ENCODE_PRIMARY_ROTATE_NORMAL         35   /*!< Set Encode Primary rotate normal  */
+#define JPEG_IOCTL_SET_DECOUTPUTWAIT_CALBACKFUN             36   /*!< Set Decode Output wait call back function  */
+#define JPEG_IOCTL_SET_DECOUTPUTWAIT                        37   /*!< Set Decode Output wait  */
+#define JPEG_IOCTL_GET_DECOUTPUTWAIT_ADDR                   38   /*!< Get Decode Output wait address  */
+#define JPEG_IOCTL_GET_DECOUTPUTWAIT_SIZE                   39   /*!< Get Decode Output wait size  */
+#define JPEG_IOCTL_SET_DECODE_COMPLETE_CALBACKFUN           40   /*!< Set Decode complete call back function  */
+#define JPEG_IOCTL_SET_ENCODE_COMPLETE_CALBACKFUN           41   /*!< Set Encode complete call back function  */
+#define JPEG_IOCTL_SET_DECODE_ERROR_CALBACKFUN              42   /*!< Set Decode Error call back function  */
+
+typedef BOOL (*PFN_JPEG_HEADERDECODE_CALLBACK)(void);   /*!< JPEG Header decode call back function */
+typedef BOOL (*PFN_JPEG_CALLBACK)(void);  /*!< JPEG call back function */
+typedef BOOL (*PFN_JPEG_DECWAIT_CALLBACK)(UINT32 u32Address, UINT32 u32Size); /*!< JPEG decode wait call back function */
+
+/** \brief  Structure type of JPEG encode/decode information
+ */
+typedef struct
+{
+    /*decode information*/
+    UINT32  yuvformat;      /*!< JPEG YUV Format for decode*/
+    UINT32  width;          /*!< Image Width */
+    UINT32  height;         /*!< Image High */
+    UINT32  jpeg_width;     /*!< JPEG decode width*/
+    UINT32  jpeg_height;    /*!< JPEG decode high*/
+    UINT32  stride;         /*!< Stride for decode*/
+    /*encode information*/
+    UINT32  bufferend;     /*!< Encode buffer */
+    UINT32  image_size[2]; /*!< Image size after encoded*/
+} JPEG_INFO_T;
+
+/** \brief  Structure type of JPEG Window Decode information
+ */
+typedef struct
+{
+    UINT16  u16StartMCUX;   /*!< Start X MCU  */
+    UINT16  u16StartMCUY;   /*!< Horizontal Scaling Factor */
+    UINT16  u16EndMCUX;     /*!< Vertical Scaling Factor */
+    UINT16  u16EndMCUY;     /*!< Horizontal Scaling Factor  */
+    UINT32  u32Stride;      /*!< Decode Output Stride */
+} JPEG_WINDOW_DECODE_T;
+
+struct nu_jpeg_ioctl
+{
+    UINT32 arg0;
+    UINT32 arg1;
+};
+typedef struct nu_jpeg_ioctl *nu_jpeg_ioctl_t;
+
+struct nu_jpeg_qtab
+{
+    PUINT8 puQTable0;
+    PUINT8 puQTable1;
+    PUINT8 puQTable2;
+    UINT8 u8num;
+};
+typedef struct nu_jpeg_qtab *nu_jpeg_qtab_t;
+
+/*@}*/ /* end of group N9H30_JPEG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_JPEG_EXPORTED_FUNCTIONS JPEG Exported Functions
+  @{
+*/
+#define JPEG_IOCTL_SET_QTAB               64   /*!< Set User-defined Q Table  */
+#define JPEG_IOCTL_INITIAL_CODEC          65   /*!< Reset Initial internal variables */
+#define JPEG_IOCTL_GET_INFO               66   /*!< Set Decode Error call back function */
+#define JPEG_IOCTL_IS_READY               67   /*!< Check JPEG codec is ready or not */
+#define JPEG_IOCTL_WAITDONE               68   /*!< Wait JPEG action done. */
+
+INT jpegSetQTAB(PUINT8 puQTable0, PUINT8 puQTable1, PUINT8 puQTable2, UINT8 u8num);
+INT jpegOpen(void);
+VOID jpegClose(void);
+VOID jpegInit(void);
+VOID jpegGetInfo(JPEG_INFO_T *info);
+BOOL jpegIsReady(void);
+INT jpegWait(void);
+VOID jpegIoctl(UINT32 cmd, UINT32 arg0, UINT32 arg1);
+
+/*@}*/ /* end of group N9H30_JPEG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_JPEG_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_lcd.h

@@ -0,0 +1,247 @@
+/**************************************************************************//**
+* @file     lcd.h
+* @version  V1.00
+* @brief    N9H30 LCD driver header file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_LCD_H__
+#define __NU_LCD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_LCD_Driver LCD Driver
+  @{
+*/
+
+/** @addtogroup N9H30_LCD_EXPORTED_CONSTANTS LCD Exported Constants
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+/* bit definition of REG_LCM_DCCS register */
+#define VPOSTB_HC_EN        ((UINT32)1<<31)
+#define VPOSTB_DISP_ON              (1<<25)
+#define VPOSTB_ITUEN                (1<<15)
+#define VPOSTB_OSD_SRC_YUV422       (0<<12)
+#define VPOSTB_OSD_SRC_YCBCR422     (1<<12)
+#define VPOSTB_OSD_SRC_RGB888       (2<<12)
+#define VPOSTB_OSD_SRC_RGB666       (3<<12)
+#define VPOSTB_OSD_SRC_RGB565       (4<<12)
+#define VPOSTB_OSD_SRC_RGB444_LOW   (5<<12)
+#define VPOSTB_OSD_SRC_RGB444_HIGH  (7<<12)
+#define VPOSTB_VA_SRC_YUV422        (0<<8 )
+#define VPOSTB_VA_SRC_YCBCR422      (1<<8 )
+#define VPOSTB_VA_SRC_RGB888        (2<<8 )
+#define VPOSTB_VA_SRC_RGB666        (3<<8 )
+#define VPOSTB_VA_SRC_RGB565        (4<<8 )
+#define VPOSTB_VA_SRC_RGB444_LOW    (5<<8 )
+#define VPOSTB_VA_SRC_RGB444_HIGH   (7<<8 )
+#define VPOSTB_SINGLE               (1<<7 )
+#define VPOSTB_FIELD_INTR           (1<<6 )
+#define VPOSTB_CMD_ON               (1<<5 )
+#define VPOSTB_DISP_INT_EN          (1<<4 )
+#define VPOSTB_DISP_OUT_EN          (1<<3 )
+#define VPOSTB_OSD_EN               (1<<2 )
+#define VPOSTB_VA_EN                (1<<1 )
+#define VPOSTB_ENG_RST              (1)
+
+
+/* bit definition of REG_LCM_DEV_CTRL register */
+#define VPOSTB_CMDHIGH  (0)
+#define VPOSTB_CMDLOW   ((UINT32)1<<31)
+#define VPOSTB_CM16t18LOW   (0)
+#define VPOSTB_CM16t18HIGH  ((UINT32)1<<30)
+#define VPOSTB_CMD8    (0)
+#define VPOSTB_CMD16    ((UINT32)1<<29)
+#define VPOSTB_IM256K_9or18 (0)
+#define VPOSTB_IM256K_8or16 ((UINT32)1<<28)
+#define VPOSTB_MPU80    (0)
+#define VPOSTB_MPU68    (1<<27)
+#define VPOSTB_DATA8or9   (0)
+#define VPOSTB_DATA16or18   (1<<26)
+#define VPOSTB_COLORTYPE_4K         (0)
+#define VPOSTB_COLORTYPE_64K        (1<<24)
+#define VPOSTB_COLORTYPE_256K       (2<<24)
+#define VPOSTB_COLORTYPE_16M        (3<<24)
+#define VPOSTB_LACE     (1<<23)
+#define VPOSTB_VR_LACE  (1<<22)
+#define VPOSTB_V_POL    (1<<21)
+#define VPOSTB_H_POL    (1<<20)
+#define VPOSTB_FAL_D    (1<<19)
+#define VPOSTB_YUV2CCIR (1<<16)
+#define VPOSTB_DEVICE_SYNC_YUV422       (0)
+#define VPOSTB_DEVICE_SYNC_UNIPAC       (4<<5)
+#define VPOSTB_DEVICE_SYNC_EPSON        (5<<5)
+#define VPOSTB_DEVICE_SYNC_HIGHCOLOR    (6<<5)
+#define VPOSTB_DEVICE_MPU               (7<<5)
+#define VPOSTB_SWAP_YUYV    (1<<1)
+
+/* bit definition of REG_LCM_INT_CS register */
+#define VPOSTB_DISP_F_INT           ((UINT32)1<<31)
+#define VPOSTB_DISP_F_STATUS        (1<<30)
+#define VPOSTB_UNDERRUN_INT         (1<<29)
+#define VPOSTB_BUS_ERROR_INT        (1<<28)
+#define VPOSTB_FLY_ERR              (1<<27)
+#define VPOSTB_UNDERRUN_EN          (1<<1)
+#define VPOSTB_DISP_F_EN            (1)
+
+/* bit definition of REG_LCM_VA_FBCTRL register */
+#define VPOSTB_DB_EN    ((UINT32)1<<31)
+#define VPOSTB_FLY_EN   (1<<12)
+
+/* bit definition of REG_LCM_OSD_OVERLAY register */
+#define VPOSTB_BLI_ON   (1<<9)
+#define VPOSTB_CKEY_ON  (1<<8)
+
+#define DISPLAY_VIDEO           (0)
+#define DISPLAY_OSD             (1)
+#define DISPLAY_SYNTHESIZED     (2)
+
+/// @endcond HIDDEN_SYMBOLS
+
+#define VA_SRC_YUV422       (0<<8 )     /*!< YUV422 format */
+#define VA_SRC_YCBCR422     (1<<8 )     /*!< YCBCR422 format */
+#define VA_SRC_RGB888       (2<<8 )     /*!< RGB888 format */
+#define VA_SRC_RGB666       (3<<8 )     /*!< RGB666 format */
+#define VA_SRC_RGB565       (4<<8 )     /*!< RGB565 format */
+#define VA_SRC_RGB444_LOW   (5<<8 )     /*!< RGB444 low nibble format */
+#define VA_SRC_RGB444_HIGH  (7<<8 )     /*!< RGB444 high nibble format */
+
+#define OSD_SRC_YUV422      (0<<12)     /*!< YUV422 format */
+#define OSD_SRC_YCBCR422    (1<<12)     /*!< YCBCR422 format */
+#define OSD_SRC_RGB888      (2<<12)     /*!< RGB888 format */
+#define OSD_SRC_RGB666      (3<<12)     /*!< RGB666 format */
+#define OSD_SRC_RGB565      (4<<12)     /*!< RGB565 format */
+#define OSD_SRC_RGB444_LOW  (5<<12)     /*!< RGB444 low nibble format */
+#define OSD_SRC_RGB444_HIGH (7<<12)     /*!< RGB444 high nibble format */
+#define OSD_SRC_RGB332      (6<<12)     /*!< RGB332 format */
+
+#define VPOST_DISPLAY_SINGLE        1   /*!< Single display mode */
+#define VPOST_DISPLAY_CONTINUOUS    0   /*!< Continuous display mode */
+
+#define VPOSTB_OSD_VUP_1X           (0<<16)     /*!< OSD vertical scale up 1x */
+#define VPOSTB_OSD_VUP_2X           (1<<16)     /*!< OSD vertical scale up 2x */
+#define VPOSTB_OSD_VUP_4X           (2<<16)     /*!< OSD vertical scale up 4x */
+
+#define DISPLAY_VIDEO           (0)     /*!< Display video data */
+#define DISPLAY_OSD             (1)     /*!< Display OSD data */
+#define DISPLAY_SYNTHESIZED     (2)     /*!< Display synthesized data */
+
+#define VA_SCALE_INTERPOLATION  (0)     /*!< Scale mode is interpolation */
+#define VA_SCALE_DUPLICATION    (1<<15) /*!< Scale mode is duplication */
+
+typedef enum va_hcmode_e
+{
+    HC_MODE0,           /*!< 32X32X2bpp 4 color */
+    HC_MODE1,           /*!< 32X32X2bpp 3 color and 1 transparent */
+    HC_MODE2,           /*!< 64X64X2bpp 4 color */
+    HC_MODE3,           /*!< 64X64X2bpp 3 color and 1 transparent */
+    HC_MODE4,           /*!< 128X128X1bpp 2 color */
+    HC_MODE5            /*!< 128X128X1bpp 1 color and 1 transparent */
+} VA_HCMODE_E;
+
+typedef struct
+{
+    uint32_t ucVASrcFormat;         /*!< User input Display source format */
+    uint32_t nScreenWidth;          /*!< Driver output,LCD width */
+    uint32_t nScreenHeight;         /*!< Driver output,LCD height */
+    uint32_t nFrameBufferSize;      /*!< Driver output,Frame buffer size(malloc by driver) */
+    uint8_t ucROT90;                /*!< Rotate 90 degree or not */
+} LCDFORMATEX;
+
+typedef struct
+{
+    uint32_t ucOSDSrcFormat;         /*!< User input, OSD source format */
+    uint32_t nXstart;                /*!< User input, OSD X axis position */
+    uint32_t nYstart;                /*!< User input, OSD Y axis position */
+    uint32_t nOSDWidth;              /*!< User input, OSD width */
+    uint32_t nOSDHeight;             /*!< User input, OSD height */
+    uint32_t nImageWidth;            /*!< User input, The width of OSD source image width */
+    uint32_t *pFrameBuffer;          /*!< User input, The address of OSD source image */
+} OSDFORMATEX;
+
+#define DIS_PANEL_E50A2V1       0
+#define DIS_PANEL_ILI9341_MPU80 1
+#define DIS_LSA40AT9001         2
+#define DIS_PANEL_FW070TFT      3
+typedef struct
+{
+    uint32_t u32DevWidth;           /*!< Panel width */
+    uint32_t u32DevHeight;          /*!< Panel height */
+    uint32_t u32CmdLow;             /*!< MPU command line low indicator */
+    uint32_t u32Cmd16t18;           /*!< MPU command width */
+    uint32_t u32CmdBusWidth;        /*!< MPU bus width */
+    uint32_t u32DataBusWidth;       /*!< Display bus width */
+    uint32_t u32MPU_Mode;           /*!< MPU mode */
+    uint32_t u32DisplayColors;      /*!< Display colors */
+    uint32_t u32DevType;            /*!< Type of display panel */
+    uint32_t u32Reg_CRTCSIZE;       /*!< CRTCSIZE register value */
+    uint32_t u32Reg_CRTCDEND;       /*!< CRTCDEND register value */
+    uint32_t u32Reg_CRTCHR;         /*!< CRTCHR register value */
+    uint32_t u32Reg_CRTCHSYNC;      /*!< CRTCHSYNC register value */
+    uint32_t u32Reg_CRTCVR;         /*!< CRTCVR register value */
+} VPOST_T;
+
+#define LCM_ERR_ID      0xFFFF0400  /*!< LCM library ID */
+
+/* error code */
+#define ERR_NULL_BUF            (LCM_ERR_ID | 0x04)  /*!< error memory location */
+#define ERR_NO_DEVICE           (LCM_ERR_ID | 0x05)  /*!< error no device */
+#define ERR_BAD_PARAMETER       (LCM_ERR_ID | 0x06)  /*!< error for bad parameter */
+#define ERR_POWER_STATE         (LCM_ERR_ID | 0x07)  /*!< error power state control */
+/*@}*/ /* end of group N9H30_LCD_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+  @{
+*/
+
+void vpostLCMInit(uint32_t u32DisplayPanelID);
+uint8_t *vpostGetFrameBuffer(void);
+uint8_t *vpostGetMultiFrameBuffer(uint32_t u32Cnt);
+void vpostLCMDeinit(void);
+void vpostSetDisplayMode(uint8_t u8DisplayMode);
+void vpostSetVASrc(uint32_t u32VASrcType);
+void vpostVAStartTrigger(void);
+void vpostVAStopTrigger(void);
+void vpostVAScalingCtrl(uint8_t u8HIntegral, uint16_t u16HDecimal, uint8_t u8VIntegral, uint16_t u16VDecimal, uint32_t u32Mode);
+
+void vpostOSDSetColKey(uint8_t u8CKeyColorR, uint8_t u8CKeyColorG, uint8_t u8CKeyColorB);
+void vpostOSDSetColMask(uint8_t u8MaskColorR, uint8_t u8MaskColorG, uint8_t u8MaskColorB);
+void vpostOSDSetBlinking(uint8_t u8OSDBlinkVcnt);
+void vpostOSDDisableBlinking(void);
+void vpostSetOSDSrc(uint32_t u32OSDSrcType);
+uint8_t *vpostGetOSDBuffer(void);
+void vpostOSDEnable(void);
+void vpostOSDDisable(void);
+void vpostOSDScalingCtrl(uint8_t u8HIntegral, uint16_t u16HDecimal, uint8_t u8VScall);
+void vpostOSDSetWindow(uint32_t u32XStart, uint32_t u32YStart, uint32_t u32Width, uint32_t u32Height);
+void vpostHCInit(uint32_t *u32CursorBMPBuff, VA_HCMODE_E ucMode);
+void vpostHCPosCtrl(uint32_t u32CursorX, uint32_t u32CursorY);
+void vpostOSDSetOverlay(uint8_t u8OSDDisplayMatch, uint8_t u8OSDDisplayUnMatch, uint8_t u8OSDSynW);
+void vpostMPUWriteAddr(uint16_t uscmd);
+void vpostMPUWriteData(uint16_t usdata);
+uint32_t vpostMPUReadData(void);
+VPOST_T *vpostLCMGetInstance(uint32_t u32DisplayPanelID);
+
+/*@}*/ /* end of group N9H30_LCD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_LCD_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_LCD_H__
+
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_pwm.h

@@ -0,0 +1,238 @@
+/**************************************************************************//**
+ * @file     pwm.h
+ * @brief    N9H30 series PWM driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_PWM_H__
+#define __NU_PWM_H__
+#include "N9H30.h"
+#include "nu_sys.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_PWM_Driver PWM Driver
+  @{
+*/
+
+/** @addtogroup N9H30_PWM_EXPORTED_CONSTANTS PWM Exported Constants
+  @{
+*/
+
+#define PWM_OFFSET      0xc ///< each channel has 3 control registers which occupies 12 bytes
+
+// Timer channel identity information
+#define PWM_TIMER_NUM   4   ///< Total PWM channel count
+#define PWM_TIMER_MIN   0   ///< Min PWM channel number
+#define PWM_TIMER_MAX   3   ///< Max PWM channel number
+#define PWM_TIMER0      0   ///< PWM channel 0
+#define PWM_TIMER1      1   ///< PWM channel 1
+#define PWM_TIMER2      2   ///< PWM channel 2
+#define PWM_TIMER3      3   ///< PWM channel 3
+
+//ioctl command
+#define START_PWMTIMER          0   ///< Start PWM ioctl command
+#define STOP_PWMTIMER           1   ///< Stop PWM ioctl command
+#define SET_CSR                 2   ///< Set CSR ioctl command
+#define SET_CP                  3   ///< Set CP ioctl command
+#define SET_DZI                 4   ///< Set dead zone ioctl command
+#define SET_INVERTER            5   ///< Set inverter ioctl command
+#define SET_MODE                6   ///< Set OP mode ioctl command
+#define ENABLE_DZ_GENERATOR     7   ///< Enable dead zone ioctl command
+#define DISABLE_DZ_GENERATOR    8   ///< Disable dead zone ioctl command
+#define ENABLE_PWMGPIOOUTPUT    9   ///< Enable PWM output ioctl command
+
+#define PWM_STOP_METHOD1    1        ///< PWM stop method 1
+#define PWM_STOP_METHOD2    2        ///< PWM stop method 2
+//#define PWM_STOP_METHOD3  3 not recommended
+
+//Timer default value
+#define DEFAULT_CSR     CSRD16        ///< Default CSR value
+#define DEFAULT_CP      255            ///< Default CP value
+#define DEFAULT_DZI     50            ///< Default DZI value
+#define DEFAULT_CNR     19531        ///< Default CNR value
+#define DEFAULT_CMR     (19531/4)    ///< Default CMR value
+#define DEFAULT_MODE    PWM_TOGGLE    ///< Default OP mode
+
+// for PWM_PPR
+#define DZI_MIN     0        ///< Min DZI value
+#define DZI_MAX     255        ///< Max DZI value
+#define CP_MIN      0        ///< Min CP value
+#define CP_MAX      255        ///< Max CP value
+
+// for PWM_CSR
+#define CSR_MIN     0        ///< Min CSR value
+#define CSR_MAX     4        ///< Mac SCR value
+#define CSRD2       0x0        ///< Div by 2
+#define CSRD4       0x1        ///< Div by 4
+#define CSRD8       0x2        ///< Div by 8
+#define CSRD16      0x3        ///< Div by 16
+#define CSRD1       0x4        ///< Div by 1
+
+// for PWM_PCR
+#define PWMDZG_ENABLE   1    ///< Enable PWM dead zone
+#define PWMDZG_DISABLE  0    ///< Disable PWM dead zone
+#define PWM_ENABLE      1   ///< Enable PWM channel
+#define PWM_DISABLE     0   ///< Disable PWM channel
+#define PWM_TOGGLE      1    ///< PWM toggle mode
+#define PWM_ONESHOT     0    ///< PWM one-shot mode
+#define PWM_INVON       1    ///< Enable PWM inverter
+#define PWM_INVOFF      0    ///< Disable PWM inverter
+
+// for PWM_CNR
+#define CNR_MIN     0        ///< Min CNR value
+#define CNR_MAX     65535    ///< Mac CNR value
+
+// for PWM_CMR
+#define CMR_MIN     0        ///< Min CMR value
+#define CMR_MAX     65535    ///< Max CMR value
+
+// for pin control
+#define PWM0_GPA12      0       ///< PWM0 output on GPA12
+#define PWM0_GPB2       1       ///< PWM0 output on GPB2
+#define PWM1_GPA13      4       ///< PWM1 output on GPA13
+#define PWM1_GPB3       5       ///< PWM1 output on GPB3
+#define PWM2_GPA14      7       ///< PWM2 output on GPA14
+#define PWM2_GPH2       9       ///< PWM2 output on GPH2
+#define PWM3_GPA15      10      ///< PWM3 output on GPA15
+#define PWM3_GPH3       12      ///< PWM3 output on GPH3
+
+#define PWM_ERR_ID      0xFFFF1300  ///< PWM library ID
+
+//PWM Error code
+#define pwmInvalidTimerChannel  (PWM_ERR_ID|1)    ///< Invalid channel number
+#define pwmInvalidStructLength  (PWM_ERR_ID|2)    ///< Invalid structure length
+#define pwmInvalidIoctlCommand  (PWM_ERR_ID|3)    ///< Invalid ioctl command
+#define pwmInvalidStopMethod    (PWM_ERR_ID|4)    ///< Invalid stop mode
+#define pwmInvalidCPValue       (PWM_ERR_ID|5)    ///< Invalid CP value
+#define pwmInvalidDZIValue      (PWM_ERR_ID|6)    ///< Invalid DZI value
+#define pwmInvalidCSRValue      (PWM_ERR_ID|7)    ///< Invalid CSR value
+#define pwmInvalidDZGStatus     (PWM_ERR_ID|8)    ///< Invalid DZ status
+#define pwmInvalidTimerStatus   (PWM_ERR_ID|9)    ///< Invalid timer status
+#define pwmInvalidInverterValue (PWM_ERR_ID|10)    ///< Invalid inverter value
+#define pwmInvalidModeStatus    (PWM_ERR_ID|11)    ///< Invalid OP mode
+#define pwmInvalidCNRValue      (PWM_ERR_ID|12)    ///< Invalid CNR value
+#define pwmInvalidCMRValue      (PWM_ERR_ID|13)    ///< Invalid CMR value
+#define pwmTimerNotOpen         (PWM_ERR_ID|14)    ///< PWM channel not stop
+#define pwmTimerBusy            (PWM_ERR_ID|15)    ///< PWM channel is busy
+#define pwmInvalidPin           (PWM_ERR_ID|16)    ///< Invalid PWM output pin
+
+/*@}*/ /* end of group N9H30_PWM_EXPORTED_CONSTANTS */
+
+/// @cond HIDDEN_SYMBOLS
+/** @addtogroup N9H30_PWM_EXPORTED_STRUCTS PWM Exported Structs
+  @{
+*/
+
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT cp0: 8, cp1: 8, dzi0: 8, dzi1: 8;
+    } field;
+} typePPR;
+
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT   csr0: 3, _reserved3: 1,
+               csr1: 3, _reserved7: 1,
+               csr2: 3, _reserved11: 1,
+               csr3: 3, _reserved15: 1,
+               _reserved16_31: 16;
+    } field;
+} typeCSR;
+
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT   ch0_en: 1, _reserved1: 1, ch0_inverter: 1, ch0_mode: 1,
+               grpup0_dzen: 1, grpup1_dzen: 1,
+               _reserved6_7: 2,
+               ch1_en: 1, _reserved9: 1, ch1_inverter: 1, ch1_mode: 1,
+               ch2_en: 1, _reserved13: 1, ch2_inverter: 1, ch2_mode: 1,
+               ch3_en: 1, _reserved17: 1, ch3_inverter: 1, ch3_mode: 1,
+               _reserved20_31: 12;
+    } field;
+} typePCR;
+
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT cnr: 16, _reserved16_31: 16;
+    } field;
+} typeCNR;
+
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT cmr: 16, _reserved16_31: 16;
+    } field;
+} typeCMR;
+
+// for write operation
+typedef union
+{
+    UINT value;
+    struct
+    {
+        UINT cnr: 16, cmr: 16;
+    } field;
+} typePWMVALUE;
+
+// for read operation
+typedef struct
+{
+    UINT volatile PDR;
+    BOOL volatile InterruptFlag;
+    BOOL _reversed0;
+    BOOL _reversed1;
+    BOOL _reversed2;
+} typePWMSTATUS;
+
+/*@}*/ /* end of group N9H30_PWM_EXPORTED_STRUCTS */
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/** @addtogroup N9H30_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+  @{
+*/
+
+// function definition
+INT pwmInit(void);
+INT pwmExit(void);
+INT pwmOpen(const INT nTimerIdentity);
+INT pwmClose(const INT nTimerIdentity);
+INT pwmRead(const INT nTimerIdentity, PUCHAR pucStatusValue, const UINT uLength);
+INT pwmWrite(const INT nTimerIdentity, PUCHAR pucCNRCMRValue, const UINT uLength);
+INT pwmIoctl(const INT nTimerIdentity, const UINT uCommand, const UINT uIndication, UINT uValue);
+
+/*@}*/ /* end of group N9H30_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_PWM_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_PWM_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_rtc.h

@@ -0,0 +1,508 @@
+/**************************************************************************//**
+* @file     RTC.h
+* @brief    N9H30 RTC driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_RTC_H__
+#define __NU_RTC_H__
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Includes of system headers                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "N9H30.h"
+#include "nu_sys.h"
+
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup N9H30_RTC_EXPORTED_CONSTANTS RTC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Error Code                                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define E_RTC_SUCCESS                   0   /*!< success */
+#define E_RTC_ERR_CALENDAR_VALUE        1   /*!< Wrong Calendar Value */
+#define E_RTC_ERR_TIMESACLE_VALUE       2   /*!< Wrong Time Scale Value */
+#define E_RTC_ERR_TIME_VALUE            3   /*!< Wrong Time Value */
+#define E_RTC_ERR_DWR_VALUE             4   /*!< Wrong Day Value */
+#define E_RTC_ERR_FCR_VALUE             5   /*!< Wrong Compenation value */
+#define E_RTC_ERR_EIO                   6   /*!< Initial RTC Failed */
+#define E_RTC_ERR_ENOTTY                7   /*!< Command not support, or parameter incorrect */
+#define E_RTC_ERR_ENODEV                8   /*!< Interface number incorrect */
+
+#define RTC_FCR_REFERENCE       32761   /*!< RTC Reference for frequency compensation */
+
+#define RTC_INIT_KEY        0xa5eb1357   /*!< RTC Access Key   \hideinitializer */
+#define RTC_WRITE_KEY       0xa965       /*!< RTC Access Key  \hideinitializer */
+
+#define RTC_WAIT_COUNT      0xFFFFFFFF  /*!< Initial Time Out Value  \hideinitializer */
+
+#define RTC_YEAR2000            2000   /*!< RTC Reference \hideinitializer */
+
+#define RTC_LEAP_YEAR       1     /*!< RTC leap year \hideinitializer */
+
+#define RTC_CLOCK_12            0   /*!< RTC 12 Hour  */
+#define RTC_CLOCK_24            1   /*!< RTC 24 Hour  */
+
+#define RTC_AM              1    /*!< RTC AM \hideinitializer */
+#define RTC_PM              2    /*!< RTC PM \hideinitializer */
+
+#define RTC_INIT_ACTIVE_Pos              (0)                                               /*!< RTC INIT: ACTIVE Position              */
+#define RTC_INIT_ACTIVE_Msk              (0x1ul << RTC_INIT_ACTIVE_Pos)                    /*!< RTC INIT: ACTIVE Mask                  */
+
+#define RTC_INIT_INIT_Pos                (0)                                               /*!< RTC INIT: INIT Position                */
+#define RTC_INIT_INIT_Msk                (0xfffffffful << RTC_INIT_INIT_Pos)               /*!< RTC INIT: INIT Mask                    */
+
+#define RTC_RWEN_RWENPASSWD_Pos          (0)                                               /*!< RTC RWEN: RWEN Position                */
+#define RTC_RWEN_RWENPASSWD_Msk          (0xfffful << RTC_RWEN_RWEN_Pos)                   /*!< RTC RWEN: RWEN Mask                    */
+
+#define RTC_RWEN_RWENF_Pos               (16)                                              /*!< RTC RWEN: RWENF Position               */
+#define RTC_RWEN_RWENF_Msk               (0x1ul << RTC_RWEN_RWENF_Pos)                     /*!< RTC RWEN: RWENF Mask                   */
+
+#define RTC_FREQADJ_FRACTION_Pos         (0)                                               /*!< RTC FREQADJ: FRACTION Position         */
+#define RTC_FREQADJ_FRACTION_Msk         (0x3ful << RTC_FREQADJ_FRACTION_Pos)              /*!< RTC FREQADJ: FRACTION Mask             */
+
+#define RTC_FREQADJ_INTEGER_Pos          (8)                                               /*!< RTC FREQADJ: INTEGER Position          */
+#define RTC_FREQADJ_INTEGER_Msk          (0xful << RTC_FREQADJ_INTEGER_Pos)                /*!< RTC FREQADJ: INTEGER Mask              */
+
+#define RTC_TIME_SEC_Pos                 (0)                                               /*!< RTC TIME: SEC Position                 */
+#define RTC_TIME_SEC_Msk                 (0xful << RTC_TIME_SEC_Pos)                       /*!< RTC TIME: SEC Mask                     */
+
+#define RTC_TIME_TENSEC_Pos              (4)                                               /*!< RTC TIME: TENSEC Position              */
+#define RTC_TIME_TENSEC_Msk              (0x7ul << RTC_TIME_TENSEC_Pos)                    /*!< RTC TIME: TENSEC Mask                  */
+
+#define RTC_TIME_MIN_Pos                 (8)                                               /*!< RTC TIME: MIN Position                 */
+#define RTC_TIME_MIN_Msk                 (0xful << RTC_TIME_MIN_Pos)                       /*!< RTC TIME: MIN Mask                     */
+
+#define RTC_TIME_TENMIN_Pos              (12)                                              /*!< RTC TIME: TENMIN Position              */
+#define RTC_TIME_TENMIN_Msk              (0x7ul << RTC_TIME_TENMIN_Pos)                    /*!< RTC TIME: TENMIN Mask                  */
+
+#define RTC_TIME_HR_Pos                  (16)                                              /*!< RTC TIME: HR Position                  */
+#define RTC_TIME_HR_Msk                  (0xful << RTC_TIME_HR_Pos)                        /*!< RTC TIME: HR Mask                      */
+
+#define RTC_TIME_TENHR_Pos               (20)                                              /*!< RTC TIME: TENHR Position               */
+#define RTC_TIME_TENHR_Msk               (0x3ul << RTC_TIME_TENHR_Pos)                     /*!< RTC TIME: TENHR Mask                   */
+
+#define RTC_CAL_DAY_Pos                  (0)                                               /*!< RTC CAL: DAY Position                  */
+#define RTC_CAL_DAY_Msk                  (0xful << RTC_CAL_DAY_Pos)                        /*!< RTC CAL: DAY Mask                      */
+
+#define RTC_CAL_TENDAY_Pos               (4)                                               /*!< RTC CAL: TENDAY Position               */
+#define RTC_CAL_TENDAY_Msk               (0x3ul << RTC_CAL_TENDAY_Pos)                     /*!< RTC CAL: TENDAY Mask                   */
+
+#define RTC_CAL_MON_Pos                  (8)                                               /*!< RTC CAL: MON Position                  */
+#define RTC_CAL_MON_Msk                  (0xful << RTC_CAL_MON_Pos)                        /*!< RTC CAL: MON Mask                      */
+
+#define RTC_CAL_TENMON_Pos               (12)                                              /*!< RTC CAL: TENMON Position               */
+#define RTC_CAL_TENMON_Msk               (0x1ul << RTC_CAL_TENMON_Pos)                     /*!< RTC CAL: TENMON Mask                   */
+
+#define RTC_CAL_YEAR_Pos                 (16)                                              /*!< RTC CAL: YEAR Position                 */
+#define RTC_CAL_YEAR_Msk                 (0xful << RTC_CAL_YEAR_Pos)                       /*!< RTC CAL: YEAR Mask                     */
+
+#define RTC_CAL_TENYEAR_Pos              (20)                                              /*!< RTC CAL: TENYEAR Position              */
+#define RTC_CAL_TENYEAR_Msk              (0xful << RTC_CAL_TENYEAR_Pos)                    /*!< RTC CAL: TENYEAR Mask                  */
+
+#define RTC_TIMEFMT_24HEN_Pos             (0)                                               /*!< RTC CLKFMT: 24HEN Position             */
+#define RTC_TIMEFMT_24HEN_Msk             (0x1ul << RTC_CLKFMT_24HEN_Pos)                   /*!< RTC CLKFMT: 24HEN Mask                 */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos          (0)                                               /*!< RTC WEEKDAY: WEEKDAY Position          */
+#define RTC_WEEKDAY_WEEKDAY_Msk          (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)                /*!< RTC WEEKDAY: WEEKDAY Mask              */
+
+#define RTC_TALM_SEC_Pos                 (0)                                               /*!< RTC TALM: SEC Position                 */
+#define RTC_TALM_SEC_Msk                 (0xful << RTC_TALM_SEC_Pos)                       /*!< RTC TALM: SEC Mask                     */
+
+#define RTC_TALM_TENSEC_Pos              (4)                                               /*!< RTC TALM: TENSEC Position              */
+#define RTC_TALM_TENSEC_Msk              (0x7ul << RTC_TALM_TENSEC_Pos)                    /*!< RTC TALM: TENSEC Mask                  */
+
+#define RTC_TALM_MIN_Pos                 (8)                                               /*!< RTC TALM: MIN Position                 */
+#define RTC_TALM_MIN_Msk                 (0xful << RTC_TALM_MIN_Pos)                       /*!< RTC TALM: MIN Mask                     */
+
+#define RTC_TALM_TENMIN_Pos              (12)                                              /*!< RTC TALM: TENMIN Position              */
+#define RTC_TALM_TENMIN_Msk              (0x7ul << RTC_TALM_TENMIN_Pos)                    /*!< RTC TALM: TENMIN Mask                  */
+
+#define RTC_TALM_HR_Pos                  (16)                                              /*!< RTC TALM: HR Position                  */
+#define RTC_TALM_HR_Msk                  (0xful << RTC_TALM_HR_Pos)                        /*!< RTC TALM: HR Mask                      */
+
+#define RTC_TALM_TENHR_Pos               (20)                                              /*!< RTC TALM: TENHR Position               */
+#define RTC_TALM_TENHR_Msk               (0x3ul << RTC_TALM_TENHR_Pos)                     /*!< RTC TALM: TENHR Mask                   */
+
+#define RTC_CALM_DAY_Pos                 (0)                                               /*!< RTC CALM: DAY Position                 */
+#define RTC_CALM_DAY_Msk                 (0xful << RTC_CALM_DAY_Pos)                       /*!< RTC CALM: DAY Mask                     */
+
+#define RTC_CALM_TENDAY_Pos              (4)                                               /*!< RTC CALM: TENDAY Position              */
+#define RTC_CALM_TENDAY_Msk              (0x3ul << RTC_CALM_TENDAY_Pos)                    /*!< RTC CALM: TENDAY Mask                  */
+
+#define RTC_CALM_MON_Pos                 (8)                                               /*!< RTC CALM: MON Position                 */
+#define RTC_CALM_MON_Msk                 (0xful << RTC_CALM_MON_Pos)                       /*!< RTC CALM: MON Mask                     */
+
+#define RTC_CALM_TENMON_Pos              (12)                                              /*!< RTC CALM: TENMON Position              */
+#define RTC_CALM_TENMON_Msk              (0x1ul << RTC_CALM_TENMON_Pos)                    /*!< RTC CALM: TENMON Mask                  */
+
+#define RTC_CALM_YEAR_Pos                (16)                                              /*!< RTC CALM: YEAR Position                */
+#define RTC_CALM_YEAR_Msk                (0xful << RTC_CALM_YEAR_Pos)                      /*!< RTC CALM: YEAR Mask                    */
+
+#define RTC_CALM_TENYEAR_Pos             (20)                                              /*!< RTC CALM: TENYEAR Position             */
+#define RTC_CALM_TENYEAR_Msk             (0xful << RTC_CALM_TENYEAR_Pos)                   /*!< RTC CALM: TENYEAR Mask                 */
+
+#define RTC_CALM_WEEKDAY_Pos             (24)                                              /*!< RTC CALM: WEEKDAY Position             */
+#define RTC_CALM_WEEKDAY_Msk             (0x7ul << RTC_CALM_WEEKDAY_Pos)                   /*!< RTC CALM: WEEKDAY Mask                 */
+
+#define RTC_CALM_DAYALM_MSK_Pos          (28)                                              /*!< RTC CALM: DAYALM_MSK Position             */
+#define RTC_CALM_DAYALM_MSK_Msk          (0x1ul << RTC_CALM_DAYALM_MSK_Pos)                /*!< RTC CALM: DAYALM_MSK Mask                 */
+
+#define RTC_CALM_MONALM_MSK_Pos          (29)                                              /*!< RTC CALM: MONALM_MSK Position             */
+#define RTC_CALM_MONALM_MSK_Msk          (0x1ul << RTC_CALM_MONALM_MSK_Pos)                /*!< RTC CALM: MONALM_MSK Mask                 */
+
+#define RTC_CALM_YRALM_MSK_Pos           (30)                                              /*!< RTC CALM: YRALM_MSK Position             */
+#define RTC_CALM_YRALM_MSK_Msk           (0x1ul << RTC_CALM_YRALM_MSK_Pos)                 /*!< RTC CALM: YRALM_MSK Mask                 */
+
+#define RTC_CALM_WKDALM_MSK_Pos          (31)                                              /*!< RTC CALM: WKDALM_MSK Position             */
+#define RTC_CALM_WKDALM_MSK_Msk          (0x1ul << RTC_CALM_WKDALM_MSK_Pos)                /*!< RTC CALM: WKDALM_MSK Mask                 */
+
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos        (0)                                               /*!< RTC LEAPYEAR: LEAPYEAR Position        */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk        (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)              /*!< RTC LEAPYEAR: LEAPYEAR Mask            */
+
+#define RTC_INTEN_ALMIEN_Pos             (0)                                               /*!< RTC INTEN: ALMIEN Position             */
+#define RTC_INTEN_ALMIEN_Msk             (0x1ul << RTC_INTEN_ALMIEN_Pos)                   /*!< RTC INTEN: ALMIEN Mask                 */
+
+#define RTC_INTEN_TICKIEN_Pos            (1)                                               /*!< RTC INTEN: TICKIEN Position            */
+#define RTC_INTEN_TICKIEN_Msk            (0x1ul << RTC_INTEN_TICKIEN_Pos)                  /*!< RTC INTEN: TICKIEN Mask                */
+
+#define RTC_INTEN_WAKEUPIEN_Pos          (2)                                               /*!< RTC INTEN: WAKEUPIEN Position            */
+#define RTC_INTEN_WAKEUPIEN_Msk          (0x1ul << RTC_INTEN_WAKEUPIEN_Pos)                /*!< RTC INTEN: WAKEUPIEN Mask                */
+
+#define RTC_INTEN_PWRSWIEN_Pos           (3)                                               /*!< RTC INTEN: PWRSWIEN Position            */
+#define RTC_INTEN_PWRSWIEN_Msk           (0x1ul << RTC_INTEN_PWRSWIEN_Pos)                 /*!< RTC INTEN: PWRSWIEN Mask                */
+
+#define RTC_INTEN_RELALMIEN_Pos          (4)                                               /*!< RTC INTEN: RELALMIEN Position            */
+#define RTC_INTEN_RELALMIEN_Msk          (0x1ul << RTC_INTEN_RELALMIEN_Pos)                /*!< RTC INTEN: RELALMIEN Mask                */
+
+#define RTC_INTEN_KEYPRESIEN_Pos         (5)                                               /*!< RTC INTEN: KEYPRESIEN Position            */
+#define RTC_INTEN_KEYPRESIEN_Msk         (0x1ul << RTC_INTEN_KEYPRESIEN_Pos)               /*!< RTC INTEN: KEYPRESIEN Mask                */
+
+
+#define RTC_INTSTS_ALMINT_Pos             (0)                                              /*!< RTC INTSTS: ALMINT Position             */
+#define RTC_INTSTS_ALMINT_Msk             (0x1ul << RTC_INTSTS_ALMINT_Pos)                 /*!< RTC INTSTS: ALMINT Mask                 */
+
+#define RTC_INTSTS_TICKINT_Pos            (1)                                              /*!< RTC INTSTS: TICKINT Position            */
+#define RTC_INTSTS_TICKINT_Msk            (0x1ul << RTC_INTSTS_TICKINT_Pos)                /*!< RTC INTSTS: TICKINT Mask                */
+
+#define RTC_INTSTS_WAKEUPINT_Pos          (2)                                              /*!< RTC INTSTS: WAKEUPINT Position            */
+#define RTC_INTSTS_WAKEUPINT_Msk          (0x1ul << RTC_INTSTS_WAKEUPINT_Pos)              /*!< RTC INTSTS: WAKEUPINT Mask                */
+
+#define RTC_INTSTS_PWRSWINT_Pos           (3)                                              /*!< RTC INTSTS: PWRSWINT Position            */
+#define RTC_INTSTS_PWRSWINT_Msk           (0x1ul << RTC_INTSTS_PWRSWINT_Pos)               /*!< RTC INTSTS: PWRSWINT Mask                */
+
+#define RTC_INTSTS_RELALMINT_Pos          (4)                                              /*!< RTC INTSTS: RELALMINT Position            */
+#define RTC_INTSTS_RELALMINT_Msk          (0x1ul << RTC_INTSTS_RELALMINT_Pos)              /*!< RTC INTSTS: RELALMINT Mask                */
+
+#define RTC_INTSTS_KEYPRESINT_Pos         (5)                                              /*!< RTC INTSTS: KEYPRESINT Position            */
+#define RTC_INTSTS_KEYPRESINT_Msk         (0x1ul << RTC_INTSTS_KEYPRESINT_Pos)             /*!< RTC INTSTS: KEYPRESINT Mask                */
+
+#define RTC_INTSTS_REGWRBUSY_Pos          (31)                                             /*!< RTC INTSTS: REGWRBUSY Position            */
+#define RTC_INTSTS_REGWRBUSY_Msk          (0x1ul << RTC_INTSTS_REGWRBUSY_Pos)              /*!< RTC INTSTS: REGWRBUSY Mask                */
+
+
+#define RTC_TICK_TTR_Pos                  (0)                                              /*!< RTC TICK: TTR Position                */
+#define RTC_TICK_TTR_Msk                  (0x7ul << RTC_TICK_TTR_Pos)                      /*!< RTC TICK: TTR Mask                    */
+
+#define RTC_PWRCTL_PWR_ON_Pos             (0)                                              /*!< RTC PWRCTL: PWR_ON Position               */
+#define RTC_PWRCTL_PWR_ON_Msk             (0x1ul << RTC_PWRCTL_PWR_ON_Pos)                 /*!< RTC PWRCTL: PWR_ON Mask                   */
+
+#define RTC_PWRCTL_SW_PCLR_Pos            (1)                                              /*!< RTC PWRCTL: SW_PCLR Position               */
+#define RTC_PWRCTL_SW_PCLR_Msk            (0x1ul << RTC_PWRCTL_SW_PCLR_Pos)                /*!< RTC PWRCTL: SW_PCLR Mask                   */
+
+#define RTC_PWRCTL_HW_PCLR_EN_Pos         (2)                                              /*!< RTC PWRCTL: HW_PCLR_EN Position               */
+#define RTC_PWRCTL_HW_PCLR_EN_Msk         (0x1ul << RTC_PWRCTL_HW_PCLR_EN_Pos)             /*!< RTC PWRCTL: HW_PCLR_EN Mask                   */
+
+#define RTC_PWRCTL_ALARM_EN_Pos           (3)                                              /*!< RTC PWRCTL: ALARM_EN Position               */
+#define RTC_PWRCTL_ALARM_EN_Msk           (0x1ul << RTC_PWRCTL_ALARM_EN_Pos)               /*!< RTC PWRCTL: ALARM_EN Mask                   */
+
+#define RTC_PWRCTL_REL_ALARM_EN_Pos       (4)                                              /*!< RTC PWRCTL: REL_ALARM_EN Position               */
+#define RTC_PWRCTL_REL_ALARM_EN_Msk       (0x1ul << RTC_PWRCTL_REL_ALARM_EN_Pos)           /*!< RTC PWRCTL: REL_ALARM_EN Mask                   */
+
+#define RTC_PWRCTL_EDGE_TRIG_Pos          (5)                                              /*!< RTC PWRCTL: EDGE_TRIG Position               */
+#define RTC_PWRCTL_EDGE_TRIG_Msk          (0x1ul << RTC_PWRCTL_EDGE_TRIG_Pos)              /*!< RTC PWRCTL: EDGE_TRIG Mask                   */
+
+#define RTC_PWRCTL_TIMEUNITL_Pos          (6)                                              /*!< RTC PWRCTL: TIMEUNITL Position               */
+#define RTC_PWRCTL_TIMEUNITL_Msk          (0x1ul << RTC_PWRCTL_TIMEUNITLPos)               /*!< RTC PWRCTL: TIMEUNITL Mask                   */
+
+#define RTC_PWRCTL_PWR_KEY_Pos            (7)                                              /*!< RTC PWRCTL: PWR_KEY Position               */
+#define RTC_PWRCTL_PWR_KEY_Msk            (0x1ul << RTC_PWRCTL_PWR_KEY_Pos)                /*!< RTC PWRCTL: PWR_KEY Mask                   */
+
+#define RTC_PWRCTL_PWRON_TIME_Pos         (8)                                              /*!< RTC PWRCTL: PWRON_TIME Position               */
+#define RTC_PWRCTL_PWRON_TIME_Msk         (0xful << RTC_PWRCTL_PWRON_TIME_Pos)             /*!< RTC PWRCTL: PWRON_TIME Mask                   */
+
+#define RTC_PWRCTL_PWROFF_TIME_Pos        (12)                                             /*!< RTC PWRCTL: PWROFF_TIME Position               */
+#define RTC_PWRCTL_PWROFF_TIME_Msk        (0xful << RTC_PWRCTL_PWROFF_TIME_Pos)            /*!< RTC PWRCTL: PWROFF_TIME Mask                   */
+
+#define RTC_PWRCTL_RELALM_TIME_Pos        (16)                                             /*!< RTC PWRCTL: RELALM_TIME Position               */
+#define RTC_PWRCTL_RELALM_TIME_Msk        (0xffful << RTC_PWRCTL_RELALM_TIME_Pos)          /*!< RTC PWRCTL: RELALM_TIME Mask                   */
+
+#define RTC_PWRCTL_ALARM_MODE_Pos         (28)                                             /*!< RTC PWRCTL: ALARM_MODE Position               */
+#define RTC_PWRCTL_ALARM_MODE_Msk         (0x1ul << RTC_PWRCTL_ALARM_MODE_Pos)             /*!< RTC PWRCTL: ALARM_MODE Mask                   */
+
+
+#define RTC_SPRCTL_SNPDEN_Pos            (0)                                               /*!< RTC SPRCTL: SNPDEN Position            */
+#define RTC_SPRCTL_SNPDEN_Msk            (0x1ul << RTC_SPRCTL_SNPDEN_Pos)                  /*!< RTC SPRCTL: SNPDEN Mask                */
+
+#define RTC_SPRCTL_SNPTYPE0_Pos          (1)                                               /*!< RTC SPRCTL: SNPTYPE0 Position          */
+#define RTC_SPRCTL_SNPTYPE0_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)                /*!< RTC SPRCTL: SNPTYPE0 Mask              */
+
+#define RTC_SPRCTL_SPRRWEN_Pos           (2)                                               /*!< RTC SPRCTL: SPRRWEN Position           */
+#define RTC_SPRCTL_SPRRWEN_Msk           (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)                 /*!< RTC SPRCTL: SPRRWEN Mask               */
+
+#define RTC_SPRCTL_SNPTYPE1_Pos          (3)                                               /*!< RTC SPRCTL: SNPTYPE1 Position          */
+#define RTC_SPRCTL_SNPTYPE1_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos)                /*!< RTC SPRCTL: SNPTYPE1 Mask              */
+
+#define RTC_SPRCTL_SPRCSTS_Pos           (5)                                               /*!< RTC SPRCTL: SPRCSTS Position           */
+#define RTC_SPRCTL_SPRCSTS_Msk           (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)                 /*!< RTC SPRCTL: SPRCSTS Mask               */
+
+#define RTC_SPRCTL_SPRRWRDY_Pos          (7)                                               /*!< RTC SPRCTL: SPRRWRDY Position          */
+#define RTC_SPRCTL_SPRRWRDY_Msk          (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos)                /*!< RTC SPRCTL: SPRRWRDY Mask              */
+
+#define RTC_SPR0_SPARE_Pos               (0)                                               /*!< RTC SPR0: SPARE Position               */
+#define RTC_SPR0_SPARE_Msk               (0xfffffffful << RTC_SPR0_SPARE_Pos)              /*!< RTC SPR0: SPARE Mask                   */
+
+#define RTC_SPR1_SPARE_Pos               (0)                                               /*!< RTC SPR1: SPARE Position               */
+#define RTC_SPR1_SPARE_Msk               (0xfffffffful << RTC_SPR1_SPARE_Pos)              /*!< RTC SPR1: SPARE Mask                   */
+
+#define RTC_SPR2_SPARE_Pos               (0)                                               /*!< RTC SPR2: SPARE Position               */
+#define RTC_SPR2_SPARE_Msk               (0xfffffffful << RTC_SPR2_SPARE_Pos)              /*!< RTC SPR2: SPARE Mask                   */
+
+#define RTC_SPR3_SPARE_Pos               (0)                                               /*!< RTC SPR3: SPARE Position               */
+#define RTC_SPR3_SPARE_Msk               (0xfffffffful << RTC_SPR3_SPARE_Pos)              /*!< RTC SPR3: SPARE Mask                   */
+
+#define RTC_SPR4_SPARE_Pos               (0)                                               /*!< RTC SPR4: SPARE Position               */
+#define RTC_SPR4_SPARE_Msk               (0xfffffffful << RTC_SPR4_SPARE_Pos)              /*!< RTC SPR4: SPARE Mask                   */
+
+#define RTC_SPR5_SPARE_Pos               (0)                                               /*!< RTC SPR5: SPARE Position               */
+#define RTC_SPR5_SPARE_Msk               (0xfffffffful << RTC_SPR5_SPARE_Pos)              /*!< RTC SPR5: SPARE Mask                   */
+
+#define RTC_SPR6_SPARE_Pos               (0)                                               /*!< RTC SPR6: SPARE Position               */
+#define RTC_SPR6_SPARE_Msk               (0xfffffffful << RTC_SPR6_SPARE_Pos)              /*!< RTC SPR6: SPARE Mask                   */
+
+#define RTC_SPR7_SPARE_Pos               (0)                                               /*!< RTC SPR7: SPARE Position               */
+#define RTC_SPR7_SPARE_Msk               (0xfffffffful << RTC_SPR7_SPARE_Pos)              /*!< RTC SPR7: SPARE Mask                   */
+
+#define RTC_SPR8_SPARE_Pos               (0)                                               /*!< RTC SPR8: SPARE Position               */
+#define RTC_SPR8_SPARE_Msk               (0xfffffffful << RTC_SPR8_SPARE_Pos)              /*!< RTC SPR8: SPARE Mask                   */
+
+#define RTC_SPR9_SPARE_Pos               (0)                                               /*!< RTC SPR9: SPARE Position               */
+#define RTC_SPR9_SPARE_Msk               (0xfffffffful << RTC_SPR9_SPARE_Pos)              /*!< RTC SPR9: SPARE Mask                   */
+
+#define RTC_SPR10_SPARE_Pos              (0)                                               /*!< RTC SPR10: SPARE Position              */
+#define RTC_SPR10_SPARE_Msk              (0xfffffffful << RTC_SPR10_SPARE_Pos)             /*!< RTC SPR10: SPARE Mask                  */
+
+#define RTC_SPR11_SPARE_Pos              (0)                                               /*!< RTC SPR11: SPARE Position              */
+#define RTC_SPR11_SPARE_Msk              (0xfffffffful << RTC_SPR11_SPARE_Pos)             /*!< RTC SPR11: SPARE Mask                  */
+
+#define RTC_SPR12_SPARE_Pos              (0)                                               /*!< RTC SPR12: SPARE Position              */
+#define RTC_SPR12_SPARE_Msk              (0xfffffffful << RTC_SPR12_SPARE_Pos)             /*!< RTC SPR12: SPARE Mask                  */
+
+#define RTC_SPR13_SPARE_Pos              (0)                                               /*!< RTC SPR13: SPARE Position              */
+#define RTC_SPR13_SPARE_Msk              (0xfffffffful << RTC_SPR13_SPARE_Pos)             /*!< RTC SPR13: SPARE Mask                  */
+
+#define RTC_SPR14_SPARE_Pos              (0)                                               /*!< RTC SPR14: SPARE Position              */
+#define RTC_SPR14_SPARE_Msk              (0xfffffffful << RTC_SPR14_SPARE_Pos)             /*!< RTC SPR14: SPARE Mask                  */
+
+#define RTC_SPR15_SPARE_Pos              (0)                                               /*!< RTC SPR15: SPARE Position              */
+#define RTC_SPR15_SPARE_Msk              (0xfffffffful << RTC_SPR15_SPARE_Pos)             /*!< RTC SPR15: SPARE Mask                  */
+
+#define RTC_SPR16_SPARE_Pos              (0)                                               /*!< RTC SPR16: SPARE Position              */
+#define RTC_SPR16_SPARE_Msk              (0xfffffffful << RTC_SPR16_SPARE_Pos)             /*!< RTC SPR16: SPARE Mask                  */
+
+#define RTC_SPR17_SPARE_Pos              (0)                                               /*!< RTC SPR17: SPARE Position              */
+#define RTC_SPR17_SPARE_Msk              (0xfffffffful << RTC_SPR17_SPARE_Pos)             /*!< RTC SPR17: SPARE Mask                  */
+
+#define RTC_SPR18_SPARE_Pos              (0)                                               /*!< RTC SPR18: SPARE Position              */
+#define RTC_SPR18_SPARE_Msk              (0xfffffffful << RTC_SPR18_SPARE_Pos)             /*!< RTC SPR18: SPARE Mask                  */
+
+#define RTC_SPR19_SPARE_Pos              (0)                                               /*!< RTC SPR19: SPARE Position              */
+#define RTC_SPR19_SPARE_Msk              (0xfffffffful << RTC_SPR19_SPARE_Pos)             /*!< RTC SPR19: SPARE Mask                  */
+
+/**
+  * @brief  RTC define interrupt source
+  */
+typedef enum
+{
+    RTC_ALARM_INT           = 0x01, /*!< Alarm interrupt */
+    RTC_TICK_INT            = 0x02, /*!< Tick interrupt */
+    RTC_WAKEUP_INT          = 0x04, /*!< Wake-up interrupt */
+    RTC_PSWI_INT            = 0x08, /*!< Power switch interrupt */
+    RTC_RELATIVE_ALARM_INT  = 0x10, /*!< Releative Alarm interrupt */
+    RTC_KEY_PRESS_INT       = 0x20, /*!< Power Key press interrupt */
+    RTC_ALL_INT             = 0x3F  /*!< All interrupt */
+} RTC_INT_SOURCE;
+
+/**
+  * @brief  Define Ioctl commands
+  */
+typedef enum
+{
+    RTC_IOC_IDENTIFY_LEAP_YEAR      =  0,    /*!< Identify leap year */
+    RTC_IOC_SET_TICK_MODE           =  1,    /*!< Set tick mode */
+    RTC_IOC_GET_TICK                =  2,    /*!< Get tick count */
+    RTC_IOC_RESTORE_TICK            =  3,    /*!< Reset tick count */
+    RTC_IOC_ENABLE_INT              =  4,    /*!< Enable RTC interrupt */
+    RTC_IOC_DISABLE_INT             =  5,    /*!< Disable RTC interrupt */
+    RTC_IOC_SET_CURRENT_TIME        =  6,    /*!< Set current time */
+    RTC_IOC_SET_ALAMRM_TIME         =  7,    /*!< set alarm time */
+    RTC_IOC_SET_FREQUENCY           =  8,    /*!< Set frequency compensation value */
+    RTC_IOC_SET_POWER_ON            =  9,    /*!< Set Power on */
+    RTC_IOC_SET_POWER_OFF           =  10,    /*!< Set Power off*/
+    RTC_IOC_SET_POWER_OFF_PERIOD    =  11,    /*!< Set Power off period */
+    RTC_IOC_ENABLE_HW_POWEROFF      =  12,    /*!< Enable H/W Power off */
+    RTC_IOC_DISABLE_HW_POWEROFF     =  13,    /*!< Disable H/W Power off */
+    RTC_IOC_GET_POWERKEY_STATUS     =  14,    /*!< Get Power key status */
+    RTC_IOC_SET_PSWI_CALLBACK       =  15,    /*!< Set Power switch isr call back function */
+    //RTC_IOC_GET_SW_STATUS         =  16,
+    //RTC_IOC_SET_SW_STATUS         =  17,
+    RTC_IOC_SET_RELEATIVE_ALARM     =  18,    /*!< Set releative alarm */
+    //RTC_IOC_SET_POWER_KEY_DELAY   =  19,
+    //RTC_IOC_SET_CLOCK_SOURCE      =  20,
+    //RTC_IOC_GET_CLOCK_SOURCE      =  21
+} E_RTC_CMD;
+
+/**
+  * @brief  RTC define Tick mode
+  */
+typedef enum
+{
+    RTC_TICK_1_SEC       =         0,      /*!< Time tick is 1 second     */
+    RTC_TICK_1_2_SEC     =         1,      /*!< Time tick is 1/2 second   */
+    RTC_TICK_1_4_SEC     =         2,      /*!< Time tick is 1/4 second   */
+    RTC_TICK_1_8_SEC     =         3,      /*!< Time tick is 1/8 second   */
+    RTC_TICK_1_16_SEC    =         4,      /*!< Time tick is 1/16 second  */
+    RTC_TICK_1_32_SEC    =         5,      /*!< Time tick is 1/32 second  */
+    RTC_TICK_1_64_SEC    =         6,      /*!< Time tick is 1/64 second  */
+    RTC_TICK_1_128_SEC   =         7       /*!< Time tick is 1/128 second */
+} RTC_TICK;
+
+typedef void (PFN_RTC_CALLBACK)(void);  /*!< Call back function \hideinitializer */
+
+/**
+  * @brief  RTC current/alarm time select
+  */
+typedef enum
+{
+    RTC_CURRENT_TIME    =    0,   /*!< Select current time */
+    RTC_ALARM_TIME      =    1    /*!< Select alarm time */
+} E_RTC_TIME_SELECT;
+
+/**
+  * @brief  RTC define Day of week parameter
+  */
+typedef enum
+{
+    RTC_SUNDAY         =   0,   /*!< Sunday    */
+    RTC_MONDAY         =   1,   /*!< Monday    */
+    RTC_TUESDAY        =   2,   /*!< Tuesday   */
+    RTC_WEDNESDAY      =   3,   /*!< Wednesday */
+    RTC_THURSDAY       =   4,   /*!< Thursday  */
+    RTC_FRIDAY         =   5,   /*!< Friday    */
+    RTC_SATURDAY       =   6    /*!< Saturday  */
+} E_RTC_DWR_PARAMETER;
+
+
+/**
+  * @brief  RTC define Time Data Struct
+  */
+typedef struct
+{
+    UINT8 u8cClockDisplay;            /*!<  12-Hour, 24-Hour */
+    UINT8 u8cAmPm;                    /*!<  Time Scale select 12-hr/24-hr */
+    UINT32 u32cSecond;                /*!<  Second value */
+    UINT32 u32cMinute;                /*!<  Minute value */
+    UINT32 u32cHour;                  /*!<  Hour value */
+    UINT32 u32cDayOfWeek;             /*!<  Day of week value */
+    UINT32 u32cDay;                   /*!<  Day value */
+    UINT32 u32cMonth;                 /*!<  Month value */
+    UINT32 u32Year;                   /*!<  Year value */
+    UINT32 u32AlarmMaskSecond;        /*!<  Alarm mask second */
+    UINT32 u32AlarmMaskMinute;        /*!<  Alarm mask minute */
+    UINT32 u32AlarmMaskHour;          /*!<  Alarm mask hour */
+    PFN_RTC_CALLBACK *pfnAlarmCallBack;    /*!< Alarm ISR call back function */
+} S_RTC_TIME_DATA_T;
+
+
+/**
+  * @brief  RTC define Tick Struct
+  */
+typedef struct
+{
+    UINT8 ucMode;                           /*!< Tick Mode  */
+    PFN_RTC_CALLBACK *pfnTickCallBack;      /*!< Tick ISR call back function  */
+} RTC_TICK_T;
+
+/*@}*/ /* end of group N9H30_RTC_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+UINT32 RTC_Init(void);
+UINT32 RTC_Open(S_RTC_TIME_DATA_T *sPt);
+UINT32 RTC_Ioctl(INT32 i32Num, E_RTC_CMD eCmd, UINT32 u32Arg0, UINT32 u32Arg1);
+UINT32 RTC_Read(E_RTC_TIME_SELECT eTime, S_RTC_TIME_DATA_T *sPt);
+UINT32 RTC_Write(E_RTC_TIME_SELECT eTime, S_RTC_TIME_DATA_T *sPt);
+UINT32 RTC_DoFrequencyCompensation(INT32 i32FrequencyX100);
+UINT32 RTC_WriteEnable(BOOL bEnable);
+UINT32 RTC_Close(void);
+void RTC_EnableClock(BOOL bEnable);
+VOID RTC_Check(void);
+
+#define RTC_DisableInt(u32IntFlag) RTC_Ioctl(0, RTC_IOC_DISABLE_INT, u32IntFlag, 0)
+#define RTC_EnableInt(u32IntFlag)  RTC_Ioctl(0, RTC_IOC_ENABLE_INT, u32IntFlag, 0)
+#define RTC_GET_TICK_INT_FLAG()    (inp32(REG_RTC_INTSTS)&RTC_TICK_INT)
+#define RTC_GET_ALARM_INT_FLAG()   (inp32(REG_RTC_INTSTS)&RTC_ALARM_INT)
+
+static __inline void RTC_CLEAR_TICK_INT_FLAG(void)
+{
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_INTSTS, RTC_TICK_INT);
+    RTC_Check();
+}
+
+static __inline void RTC_CLEAR_ALARM_INT_FLAG(void)
+{
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_INTSTS, RTC_ALARM_INT);
+    RTC_Check();
+}
+
+
+/*@}*/ /* end of group N9H30_RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_RTC_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* __NU_RTC_H__ */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+
+
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_scuart.h

@@ -0,0 +1,335 @@
+/**************************************************************************//**
+ * @file     scuart.h
+ * @brief    N9H30 series Smartcard UART mode (SCUART) driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SCUART_H__
+#define __NU_SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SCUART_Driver SCUART Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+  @{
+*/
+#define SCUART_CHAR_LEN_5     (0x3ul << 4)  /*!< Set SCUART word length to 5 bits */
+#define SCUART_CHAR_LEN_6     (0x2ul << 4)  /*!< Set SCUART word length to 6 bits */
+#define SCUART_CHAR_LEN_7     (0x1ul << 4)  /*!< Set SCUART word length to 7 bits */
+#define SCUART_CHAR_LEN_8     (0)                            /*!< Set SCUART word length to 8 bits */
+
+#define SCUART_PARITY_NONE    (0x00000040)                   /*!< Set SCUART transfer with no parity   */
+#define SCUART_PARITY_ODD     (0x00000080)                   /*!< Set SCUART transfer with odd parity  */
+#define SCUART_PARITY_EVEN    (0)                            /*!< Set SCUART transfer with even parity */
+
+#define SCUART_STOP_BIT_1     (0x00008000)                   /*!< Set SCUART transfer with one stop bit  */
+#define SCUART_STOP_BIT_2     (0)                            /*!< Set SCUART transfer with two stop bits */
+
+#define SC_STATUS_RXEMPTY_Msk   0x00000002
+#define SC_STATUS_RXFULL_Msk    0x00000004
+#define SC_STATUS_PEF_Msk       0x00000010
+#define SC_STATUS_FEF_Msk       0x00000020
+#define SC_STATUS_BEF_Msk       0x00000040
+#define SC_STATUS_TXEMPTY_Msk   0x00000200
+#define SC_STATUS_TXFULL_Msk    0x00000400
+#define SC_STATUS_TXACT_Msk     0x80000000
+
+#define SC_INTEN_RXTOIEN_Msk    0x00000200
+#define SC_INTEN_TERRIEN_Msk    0x00000004
+#define SC_INTEN_TBEIEN_Msk     0x00000002
+#define SC_INTEN_RDAIEN_Msk     0x00000001
+
+#define SC_INTSTS_RBTOIF_Msk    0x00000200
+#define SC_INTSTS_TERRIF_Msk    0x00000004
+#define SC_INTSTS_TBEIF_Msk     0x00000002
+#define SC_INTSTS_RDAIF_Msk     0x00000001
+
+#define SC_CTL_SCEN_Msk         0x00000001
+#define SC_CTL_NSB_Msk          0x00008000
+
+#define SC_UARTCTL_UARTEN_Msk   0x00000001
+
+/*@}*/ /* end of group N9H30_SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/* TX Macros */
+/**
+  * @brief Write Data to Tx data register.
+  * @param[in] sc Smartcard module number
+  * @param[in] u8Data Data byte to transmit.
+  * @return None
+  * @details By writing data to DAT register, the SC will send out an 8-bit data.
+  * \hideinitializer
+  */
+#define SCUART_WRITE(sc, u8Data) \
+do {\
+    if(sc == 0)\
+        outpw(REG_SC0_DAT, u8Data);\
+    else\
+        outpw(REG_SC1_DAT, u8Data);\
+}while(0)
+
+/**
+  * @brief Get TX FIFO empty flag status from register.
+  * @param[in] sc Smartcard module number
+  * @return Transmit FIFO empty status.
+  * @retval 0 Transmit FIFO is not empty.
+  * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty.
+  * @details When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY bit (SC_STATUS[9]) high.
+  *          It will be cleared when writing data into DAT (SC_DAT[7:0]).
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_EMPTY(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_TXEMPTY_Msk) : (inpw(REG_SC1_STATUS) & SC_STATUS_TXEMPTY_Msk))
+
+/**
+  * @brief Get TX FIFO full flag status from register.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Transmit FIFO is not full.
+  * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full.
+  * @details TXFULL(SC_STATUS[10]) is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_FULL(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_TXFULL_Msk) : (inpw(REG_SC1_STATUS) & SC_STATUS_TXFULL_Msk))
+
+/**
+  * @brief Wait specified smartcard port transmission complete.
+  * @param[in] sc Smartcard module number
+  * @return None
+  * @details TXACT (SC_STATUS[31]) is cleared automatically when TX transfer is finished or the last byte transmission has completed.
+  * @note This macro blocks until transmit complete.
+  * \hideinitializer
+  */
+#define SCUART_WAIT_TX_EMPTY(sc)\
+do {\
+    if(sc == 0)\
+        while(inpw(REG_SC0_STATUS) & SC_STATUS_TXACT_Msk);\
+    else\
+        while(inpw(REG_SC1_STATUS) & SC_STATUS_TXACT_Msk);\
+}while(0)
+
+/**
+  * @brief Check specified smartcard port transmit FIFO is full or not.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Transmit FIFO is not full.
+  * @retval 1 Transmit FIFO is full.
+  * @details TXFULL(SC_STATUS[10]) indicates TX buffer full or not.
+  *          This is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_FULL(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_TXFULL_Msk ? 1 : 0) : (inpw(REG_SC1_STATUS) & SC_STATUS_TXFULL_Msk ? 1 : 0))
+
+/**
+  * @brief Check specified smartcard port transmission is over.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Transmit is not complete.
+  * @retval 1 Transmit complete.
+  * @details TXACT (SC_STATUS[31]) is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_EMPTY(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_TXACT_Msk ? 1 : 0) : (inpw(REG_SC1_STATUS) & SC_STATUS_TXACT_Msk ? 1 : 0))
+
+/* RX Macros */
+
+/**
+  * @brief Read Rx data register.
+  * @param[in] sc Smartcard module number
+  * @return The oldest data byte in RX FIFO.
+  * @details By reading DAT register, the SC will return an 8-bit received data.
+  * \hideinitializer
+  */
+#define SCUART_READ(sc) (sc == 0 ? inpw(REG_SC0_DAT) : inpw(REG_SC1_DAT))
+
+/**
+  * @brief Get RX FIFO empty flag status from register.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Receive FIFO is not empty.
+  * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty.
+  * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY(SC_STATUS[1]) high.
+  *          It will be cleared when SC receives any new data.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_EMPTY(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_RXEMPTY_Msk) : (inpw(REG_SC1_STATUS) & SC_STATUS_RXEMPTY_Msk))
+
+
+/**
+  * @brief Get RX FIFO full flag status from register.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Receive FIFO is not full.
+  * @retval SC_STATUS_RXFULL_Msk Receive FIFO is full.
+  * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_FULL(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_RXFULL_Msk) : (inpw(REG_SC1_STATUS) & SC_STATUS_RXFULL_Msk))
+
+/**
+  * @brief Check if receive data number in FIFO reach FIFO trigger level or not.
+  * @param[in] sc Smartcard module number
+  * @retval 0 The number of bytes in receive FIFO is less than trigger level.
+  * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level.
+  * @details RDAIF(SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+  * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_READY(sc) (sc == 0 ? (inpw(REG_SC0_INTSTS) & SC_INTSTS_RDAIF_Msk ? 1 : 0) : (inpw(REG_SC1_INTSTS) & SC_INTSTS_RDAIF_Msk ? 1 : 0))
+
+/**
+  * @brief Check specified smartcard port receive FIFO is full or not.
+  * @param[in] sc Smartcard module number
+  * @retval 0 Receive FIFO is not full.
+  * @retval 1 Receive FIFO is full.
+  * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_FULL(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & SC_STATUS_RXFULL_Msk ? 1 : 0) : (inpw(REG_SC1_STATUS) & SC_STATUS_RXFULL_Msk ? 1 : 0))
+
+/* Interrupt Macros */
+
+/**
+  * @brief Enable specified interrupts.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Mask Interrupt masks to enable, a combination of following bits.
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
+  *          transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_ENABLE_INT(sc, u32Mask)\
+do {\
+    if(sc == 0)\
+        outpw(REG_SC0_INTEN, inpw(REG_SC0_INTEN) | (u32Mask));\
+    else\
+        outpw(REG_SC1_INTEN, inpw(REG_SC1_INTEN) | (u32Mask));\
+}while(0)
+
+/**
+  * @brief Disable specified interrupts.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Mask Interrupt masks to disable, a combination of following bits.
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
+  *          transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_DISABLE_INT(sc, u32Mask)\
+do {\
+    if(sc == 0)\
+        outpw(REG_SC0_INTEN, inpw(REG_SC0_INTEN) & ~(u32Mask));\
+    else\
+        outpw(REG_SC1_INTEN, inpw(REG_SC1_INTEN) & ~(u32Mask));\
+}while(0)
+
+/**
+  * @brief Get specified interrupt flag/status.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Type Interrupt flag/status to check, could be one of following value:
+  *             - \ref SC_INTSTS_RBTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  *             - \ref SC_INTSTS_RDAIF_Msk
+  * @return The status of specified interrupt.
+  * @retval 0 Specified interrupt does not happened.
+  * @retval 1 Specified interrupt happened.
+  * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
+  *          transmit buffer empty interrupt status or receive data reach interrupt status.
+  * \hideinitializer
+  */
+#define SCUART_GET_INT_FLAG(sc, u32Type) (sc == 0 ? (inpw(REG_SC0_INTSTS) & (u32Type) ? 1 : 0) : (inpw(REG_SC1_INTSTS) & (u32Type) ? 1 : 0))
+
+/**
+  * @brief Clear specified interrupt flag/status.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values:
+  *             - \ref SC_INTSTS_RBTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  * @return None
+  * @details The macro is used to clear receiver buffer time-out interrupt flag, transfer error interrupt flag or
+  *          transmit buffer empty interrupt flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) \
+do {\
+    if(sc == 0)\
+        outpw(REG_SC0_INTSTS, (u32Type));\
+    else\
+        outpw(REG_SC1_INTSTS, (u32Type));\
+}while(0)
+
+/**
+  * @brief Get receive error flag/status.
+  * @param[in] sc Smartcard module number
+  * @return Current receive error status, could one of following errors:
+  * @retval SC_STATUS_PEF_Msk Parity error.
+  * @retval SC_STATUS_FEF_Msk Frame error.
+  * @retval SC_STATUS_BEF_Msk Break error.
+  * @details The macro is used to get receiver parity error status, receiver frame error status or
+  *          receiver break error status.
+  * \hideinitializer
+  */
+#define SCUART_GET_ERR_FLAG(sc) (sc == 0 ? (inpw(REG_SC0_STATUS) & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) : (inpw(REG_SC1_STATUS) & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)))
+
+/**
+  * @brief Clear specified receive error flag/status.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Mask Receive error flag/status to clear, combination following values:
+  *             - \ref SC_STATUS_PEF_Msk
+  *             - \ref SC_STATUS_FEF_Msk
+  *             - \ref SC_STATUS_BEF_Msk
+  * @return None
+  * @details The macro is used to clear receiver parity error flag, receiver frame error flag or
+  *          receiver break error flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask)\
+do {\
+    if(sc == 0)\
+        outpw(REG_SC0_STATUS, (u32Mask));\
+    else\
+        outpw(REG_SC1_STATUS, (u32Mask));\
+}while(0)
+
+void SCUART_Close(UINT sc);
+UINT SCUART_Open(UINT sc, UINT u32baudrate);
+UINT SCUART_Read(UINT sc, char *pu8RxBuf, UINT u32ReadBytes);
+UINT SCUART_SetLineConfig(UINT sc, UINT u32Baudrate, UINT u32DataWidth, UINT u32Parity, UINT  u32StopBits);
+void SCUART_SetTimeoutCnt(UINT sc, UINT u32TOC);
+void SCUART_Write(UINT sc, char *pu8TxBuf, UINT u32WriteBytes);
+
+/*@}*/ /* end of group N9H30_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SCUART_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_SCUART_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_sdh.h

@@ -0,0 +1,757 @@
+/**************************************************************************//**
+ * @file     sdh.h
+ * @brief    N9H30 SDH driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+
+#ifndef __NU_SDH_H__
+#define __NU_SDH_H__
+
+#ifdef __cplusplus
+    #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+    #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+#define TIMER0 0
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup SDH SD/SDIO Host Controller(SDH)
+    Memory Mapped Structure for SDH Controller
+@{ */
+
+typedef struct
+{
+
+    /**
+     * @var SDH_T::FB
+     * Offset: 0x00~0x7C  Shared Buffer (FIFO)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |BUFFER    |Shared Buffer
+     * |        |          |Buffer for DMA transfer
+     * @var SDH_T::DMACTL
+     * Offset: 0x400  DMA Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DMAEN     |DMA Engine Enable Bit
+     * |        |          |0 = DMA Disabled.
+     * |        |          |1 = DMA Enabled.
+     * |        |          |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
+     * |        |          |Note: If target abort is occurred, DMAEN will be cleared.
+     * |[1]     |DMARST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset internal state machine and pointers
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto be cleared after few clock cycles.
+     * |        |          |Note: The software reset DMA related registers.
+     * |[3]     |SGEN      |Scatter-gather Function Enable Bit
+     * |        |          |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
+     * |        |          |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
+     * |        |          |The format of these Pads' will be described later).
+     * |[9]     |DMABUSY   |DMA Transfer Is in Progress
+     * |        |          |This bit indicates if SD Host is granted and doing DMA transfer or not.
+     * |        |          |0 = DMA transfer is not in progress.
+     * |        |          |1 = DMA transfer is in progress.
+     * @var SDH_T::DMASA
+     * Offset: 0x408  DMA Transfer Starting Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ORDER     |Determined to the PAD Table Fetching Is in Order or Out of Order
+     * |        |          |0 = PAD table is fetched in order.
+     * |        |          |1 = PAD table is fetched out of order.
+     * |        |          |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
+     * |[31:1]  |DMASA     |DMA Transfer Starting Address
+     * |        |          |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
+     * |        |          |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
+     * |        |          |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
+     * @var SDH_T::DMABCNT
+     * Offset: 0x40C  DMA Transfer Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[25:0]  |BCNT      |DMA Transfer Byte Count (Read Only)
+     * |        |          |This field indicates the remained byte count of DMA transfer
+     * |        |          |The value of this field is valid only when DMA is busy; otherwise, it is 0.
+     * @var SDH_T::DMAINTEN
+     * Offset: 0x410  DMA Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIEN  |DMA Read/Write Target Abort Interrupt Enable Bit
+     * |        |          |0 = Target abort interrupt generation Disabled during DMA transfer.
+     * |        |          |1 = Target abort interrupt generation Enabled during DMA transfer.
+     * |[1]     |WEOTIEN   |Wrong EOT Encountered Interrupt Enable Bit
+     * |        |          |0 = Interrupt generation Disabled when wrong EOT is encountered.
+     * |        |          |1 = Interrupt generation Enabled when wrong EOT is encountered.
+     * @var SDH_T::DMAINTSTS
+     * Offset: 0x414  DMA Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIF   |DMA Read/Write Target Abort Interrupt Flag
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note1: This bit is read only, but can be cleared by writing '1' to it.
+     * |        |          |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
+     * |        |          |DMA will stop transfer and respond this event and then go to IDLE state
+     * |        |          |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
+     * |[1]     |WEOTIF    |Wrong EOT Encountered Interrupt Flag
+     * |        |          |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
+     * |        |          |0 = No EOT encountered before DMA transfer finished.
+     * |        |          |1 = EOT encountered before DMA transfer finished.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::GCTL
+     * Offset: 0x800  Global Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GCTLRST   |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset SD host
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto cleared after reset complete.
+     * |[1]     |SDEN      |Secure Digital Functionality Enable Bit
+     * |        |          |0 = SD functionality disabled.
+     * |        |          |1 = SD functionality enabled.
+     * @var SDH_T::GINTEN
+     * Offset: 0x804  Global Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIEN    |DMA READ/WRITE Target Abort Interrupt Enable Bit
+     * |        |          |0 = DMA READ/WRITE target abort interrupt generation disabled.
+     * |        |          |1 = DMA READ/WRITE target abort interrupt generation enabled.
+     * @var SDH_T::GINTSTS
+     * Offset: 0x808  Global Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIF     |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
+     * |        |          |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
+     * |        |          |When Target Abort is occurred, please reset all engine.
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::CTL
+     * Offset: 0x820  SD Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |COEN      |Command Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output a command to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[1]     |RIEN      |Response Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[2]     |DIEN      |Data Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[3]     |DOEN      |Data Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[4]     |R2EN      |Response R2 Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[5]     |CLK74OEN  |Initial 74 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 74 clock cycles to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[6]     |CLK8OEN   |Generating 8 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 8 clock cycles.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[7]     |CLKKEEP   |SD Clock Enable Control
+     * |        |          |0 = SD host decided when to output clock and when to disable clock output automatically.
+     * |        |          |1 = SD clock always keeps free running.
+     * |[13:8]  |CMDCODE   |SD Command Code
+     * |        |          |This register contains the SD command code (0x00 - 0x3F).
+     * |[14]    |CTLRST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the internal state machine and counters
+     * |        |          |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared)
+     * |        |          |This bit will be auto cleared after few clock cycles.
+     * |[15]    |DBW       |SD Data Bus Width (for 1-bit / 4-bit Selection)
+     * |        |          |0 = Data bus width is 1-bit.
+     * |        |          |1 = Data bus width is 4-bit.
+     * |[23:16] |BLKCNT    |Block Counts to Be Transferred or Received
+     * |        |          |This field contains the block counts for data-in and data-out transfer
+     * |        |          |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
+     * |        |          |Don't fill 0x0 to this field.
+     * |        |          |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
+     * |[27:24] |SDNWR     |NWR Parameter for Block Write Operation
+     * |        |          |This value indicates the NWR parameter for data block write operation in SD clock counts
+     * |        |          |The actual clock cycle will be SDNWR+1.
+     * @var SDH_T::CMDARG
+     * Offset: 0x824  SD Command Argument Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ARGUMENT  |SD Command Argument
+     * |        |          |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
+     * |        |          |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
+     * @var SDH_T::INTEN
+     * Offset: 0x828  SD Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIEN   |Block Transfer Done Interrupt Enable Bit
+     * |        |          |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable.
+     * |        |          |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
+     * |[1]     |CRCIEN    |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
+     * |        |          |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable.
+     * |        |          |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
+     * |[8]     |CDIEN     |SD Card Detection Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when card is inserted or removed.
+     * |        |          |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable.
+     * |        |          |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
+     * |[12]    |RTOIEN    |Response Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled.
+     * |        |          |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
+     * |[13]    |DITOIEN   |Data Input Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when data input time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled.
+     * |        |          |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
+     * |[14]    |WKIEN     |Wake-up Signal Generating Enable Bit
+     * |        |          |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
+     * |        |          |0 = SD Card interrupt to wake-up chip Disabled.
+     * |        |          |1 = SD Card interrupt to wake-up chip Enabled.
+     * |[30]    |CDSRC     |SD Card Detect Source Selection
+     * |        |          |0 = From SD card's DAT3 pin.
+     * |        |          |Host need clock to got data on pin DAT3
+     * |        |          |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
+     * |        |          |1 = From GPIO pin.
+     * @var SDH_T::INTSTS
+     * Offset: 0x82C  SD Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIF    |Block Transfer Done Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has finished all data-in or data-out block transfer
+     * |        |          |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
+     * |        |          |0 = Not finished yet.
+     * |        |          |1 = Done.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[1]     |CRCIF     |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
+     * |        |          |When CRC error is occurred, software should reset SD engine
+     * |        |          |Some response (ex
+     * |        |          |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
+     * |        |          |In this condition, software should ignore CRC error and clears this bit manually.
+     * |        |          |0 = No CRC error is occurred.
+     * |        |          |1 = CRC error is occurred.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[2]     |CRC7      |CRC7 Check Status (Read Only)
+     * |        |          |SD host will check CRC7 correctness during each response in
+     * |        |          |If that response does not contain CRC7 information (ex
+     * |        |          |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[3]     |CRC16     |CRC16 Check Status of Data-in Transfer (Read Only)
+     * |        |          |SD host will check CRC16 correctness after data-in transfer.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[6:4]   |CRCSTS    |CRC Status Value of Data-out Transfer (Read Only)
+     * |        |          |SD host will record CRC status of data-out transfer
+     * |        |          |Software could use this value to identify what type of error is during data-out transfer.
+     * |        |          |010 = Positive CRC status.
+     * |        |          |101 = Negative CRC status.
+     * |        |          |111 = SD card programming error occurs.
+     * |[7]     |DAT0STS   |DAT0 Pin Status of Current Selected SD Port (Read Only)
+     * |        |          |This bit is the DAT0 pin status of current selected SD port.
+     * |[8]     |CDIF      |SD Card Detection Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD card is inserted or removed
+     * |        |          |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.
+     * |        |          |0 = No card is inserted or removed.
+     * |        |          |1 = There is a card inserted in or removed from SD.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[12]    |RTOIF     |Response Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Response time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[13]    |DITOIF    |Data Input Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Data input time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[16]    |CDSTS     |Card Detect Status of SD (Read Only)
+     * |        |          |This bit indicates the card detect pin status of SD, and is used for card detection
+     * |        |          |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
+     * |        |          |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
+     * |        |          |0 = Card removed.
+     * |        |          |1 = Card inserted.
+     * |        |          |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
+     * |        |          |0 = Card inserted.
+     * |        |          |1 = Card removed.
+     * |[18]    |DAT1STS   |DAT1 Pin Status of SD Port (Read Only)
+     * |        |          |This bit indicates the DAT1 pin status of SD port.
+     * @var SDH_T::RESP0
+     * Offset: 0x830  SD Receiving Response Token Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RESPTK0   |SD Receiving Response Token 0
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This field contains response bit 47-16 of the response token.
+     * @var SDH_T::RESP1
+     * Offset: 0x834  SD Receiving Response Token Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |RESPTK1   |SD Receiving Response Token 1
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This register contains the bit 15-8 of the response token.
+     * @var SDH_T::BLEN
+     * Offset: 0x838  SD Block Length Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |BLKLEN    |SD BLOCK LENGTH in Byte Unit
+     * |        |          |An 11-bit value specifies the SD transfer byte count of a block
+     * |        |          |The actual byte count is equal to BLKLEN+1.
+     * |        |          |Note: The default SD block length is 512 bytes
+     * @var SDH_T::TOUT
+     * Offset: 0x83C  SD Response/Data-in Time-out Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |TOUT      |SD Response/Data-in Time-out Value
+     * |        |          |A 24-bit value specifies the time-out counts of response and data input
+     * |        |          |SD host controller will wait start bit of response or data-in until this value reached
+     * |        |          |The time period depends on SD engine clock frequency
+     * |        |          |Do not write a small number into this field, or you may never get response or data due to time-out.
+     * |        |          |Note: Filling 0x0 into this field will disable hardware time-out function.
+     */
+
+    __IO uint32_t FB[32];                /*!< Shared Buffer (FIFO)                                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[224];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DMACTL;                /*!< [0x0400] DMA Control and Status Register                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DMASA;                 /*!< [0x0408] DMA Transfer Starting Address Register                           */
+    __I  uint32_t DMABCNT;               /*!< [0x040c] DMA Transfer Byte Count Register                                 */
+    __IO uint32_t DMAINTEN;              /*!< [0x0410] DMA Interrupt Enable Control Register                            */
+    __IO uint32_t DMAINTSTS;             /*!< [0x0414] DMA Interrupt Status Register                                    */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[250];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t GCTL;                  /*!< [0x0800] Global Control and Status Register                               */
+    __IO uint32_t GINTEN;                /*!< [0x0804] Global Interrupt Control Register                                */
+    __I  uint32_t GINTSTS;               /*!< [0x0808] Global Interrupt Status Register                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL;                   /*!< [0x0820] SD Control and Status Register                                   */
+    __IO uint32_t CMDARG;                /*!< [0x0824] SD Command Argument Register                                     */
+    __IO uint32_t INTEN;                 /*!< [0x0828] SD Interrupt Control Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x082c] SD Interrupt Status Register                                     */
+    __I  uint32_t RESP0;                 /*!< [0x0830] SD Receiving Response Token Register 0                           */
+    __I  uint32_t RESP1;                 /*!< [0x0834] SD Receiving Response Token Register 1                           */
+    __IO uint32_t BLEN;                  /*!< [0x0838] SD Block Length Register                                         */
+    __IO uint32_t TOUT;                  /*!< [0x083c] SD Response/Data-in Time-out Register                            */
+
+} SDH_T;
+
+
+/**
+    @addtogroup SDH_CONST SDH Bit Field Definition
+    Constant Definitions for SDH Controller
+@{ */
+
+#define SDH_DMACTL_DMAEN_Pos             (0)                                               /*!< SDH_T::DMACTL: DMAEN Position          */
+#define SDH_DMACTL_DMAEN_Msk             (0x1ul << SDH_DMACTL_DMAEN_Pos)                   /*!< SDH_T::DMACTL: DMAEN Mask              */
+
+#define SDH_DMACTL_DMARST_Pos            (1)                                               /*!< SDH_T::DMACTL: DMARST Position         */
+#define SDH_DMACTL_DMARST_Msk            (0x1ul << SDH_DMACTL_DMARST_Pos)                  /*!< SDH_T::DMACTL: DMARST Mask             */
+
+#define SDH_DMACTL_SGEN_Pos              (3)                                               /*!< SDH_T::DMACTL: SGEN Position           */
+#define SDH_DMACTL_SGEN_Msk              (0x1ul << SDH_DMACTL_SGEN_Pos)                    /*!< SDH_T::DMACTL: SGEN Mask               */
+
+#define SDH_DMACTL_DMABUSY_Pos           (9)                                               /*!< SDH_T::DMACTL: DMABUSY Position        */
+#define SDH_DMACTL_DMABUSY_Msk           (0x1ul << SDH_DMACTL_DMABUSY_Pos)                 /*!< SDH_T::DMACTL: DMABUSY Mask            */
+
+#define SDH_DMASA_ORDER_Pos              (0)                                               /*!< SDH_T::DMASA: ORDER Position           */
+#define SDH_DMASA_ORDER_Msk              (0x1ul << SDH_DMASA_ORDER_Pos)                    /*!< SDH_T::DMASA: ORDER Mask               */
+
+#define SDH_DMASA_DMASA_Pos              (1)                                               /*!< SDH_T::DMASA: DMASA Position           */
+#define SDH_DMASA_DMASA_Msk              (0x7ffffffful << SDH_DMASA_DMASA_Pos)             /*!< SDH_T::DMASA: DMASA Mask               */
+
+#define SDH_DMABCNT_BCNT_Pos             (0)                                               /*!< SDH_T::DMABCNT: BCNT Position          */
+#define SDH_DMABCNT_BCNT_Msk             (0x3fffffful << SDH_DMABCNT_BCNT_Pos)             /*!< SDH_T::DMABCNT: BCNT Mask              */
+
+#define SDH_DMAINTEN_ABORTIEN_Pos        (0)                                               /*!< SDH_T::DMAINTEN: ABORTIEN Position     */
+#define SDH_DMAINTEN_ABORTIEN_Msk        (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos)              /*!< SDH_T::DMAINTEN: ABORTIEN Mask         */
+
+#define SDH_DMAINTEN_WEOTIEN_Pos         (1)                                               /*!< SDH_T::DMAINTEN: WEOTIEN Position      */
+#define SDH_DMAINTEN_WEOTIEN_Msk         (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos)               /*!< SDH_T::DMAINTEN: WEOTIEN Mask          */
+
+#define SDH_DMAINTSTS_ABORTIF_Pos        (0)                                               /*!< SDH_T::DMAINTSTS: ABORTIF Position     */
+#define SDH_DMAINTSTS_ABORTIF_Msk        (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos)              /*!< SDH_T::DMAINTSTS: ABORTIF Mask         */
+
+#define SDH_DMAINTSTS_WEOTIF_Pos         (1)                                               /*!< SDH_T::DMAINTSTS: WEOTIF Position      */
+#define SDH_DMAINTSTS_WEOTIF_Msk         (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos)               /*!< SDH_T::DMAINTSTS: WEOTIF Mask          */
+
+#define SDH_GCTL_GCTLRST_Pos             (0)                                               /*!< SDH_T::GCTL: GCTLRST Position          */
+#define SDH_GCTL_GCTLRST_Msk             (0x1ul << SDH_GCTL_GCTLRST_Pos)                   /*!< SDH_T::GCTL: GCTLRST Mask              */
+
+#define SDH_GCTL_SDEN_Pos                (1)                                               /*!< SDH_T::GCTL: SDEN Position             */
+#define SDH_GCTL_SDEN_Msk                (0x1ul << SDH_GCTL_SDEN_Pos)                      /*!< SDH_T::GCTL: SDEN Mask                 */
+
+#define SDH_GINTEN_DTAIEN_Pos            (0)                                               /*!< SDH_T::GINTEN: DTAIEN Position         */
+#define SDH_GINTEN_DTAIEN_Msk            (0x1ul << SDH_GINTEN_DTAIEN_Pos)                  /*!< SDH_T::GINTEN: DTAIEN Mask             */
+
+#define SDH_GINTSTS_DTAIF_Pos            (0)                                               /*!< SDH_T::GINTSTS: DTAIF Position         */
+#define SDH_GINTSTS_DTAIF_Msk            (0x1ul << SDH_GINTSTS_DTAIF_Pos)                  /*!< SDH_T::GINTSTS: DTAIF Mask             */
+
+#define SDH_CTL_COEN_Pos                 (0)                                               /*!< SDH_T::CTL: COEN Position              */
+#define SDH_CTL_COEN_Msk                 (0x1ul << SDH_CTL_COEN_Pos)                       /*!< SDH_T::CTL: COEN Mask                  */
+
+#define SDH_CTL_RIEN_Pos                 (1)                                               /*!< SDH_T::CTL: RIEN Position              */
+#define SDH_CTL_RIEN_Msk                 (0x1ul << SDH_CTL_RIEN_Pos)                       /*!< SDH_T::CTL: RIEN Mask                  */
+
+#define SDH_CTL_DIEN_Pos                 (2)                                               /*!< SDH_T::CTL: DIEN Position              */
+#define SDH_CTL_DIEN_Msk                 (0x1ul << SDH_CTL_DIEN_Pos)                       /*!< SDH_T::CTL: DIEN Mask                  */
+
+#define SDH_CTL_DOEN_Pos                 (3)                                               /*!< SDH_T::CTL: DOEN Position              */
+#define SDH_CTL_DOEN_Msk                 (0x1ul << SDH_CTL_DOEN_Pos)                       /*!< SDH_T::CTL: DOEN Mask                  */
+
+#define SDH_CTL_R2EN_Pos                 (4)                                               /*!< SDH_T::CTL: R2EN Position              */
+#define SDH_CTL_R2EN_Msk                 (0x1ul << SDH_CTL_R2EN_Pos)                       /*!< SDH_T::CTL: R2EN Mask                  */
+
+#define SDH_CTL_CLK74OEN_Pos             (5)                                               /*!< SDH_T::CTL: CLK74OEN Position          */
+#define SDH_CTL_CLK74OEN_Msk             (0x1ul << SDH_CTL_CLK74OEN_Pos)                   /*!< SDH_T::CTL: CLK74OEN Mask              */
+
+#define SDH_CTL_CLK8OEN_Pos              (6)                                               /*!< SDH_T::CTL: CLK8OEN Position           */
+#define SDH_CTL_CLK8OEN_Msk              (0x1ul << SDH_CTL_CLK8OEN_Pos)                    /*!< SDH_T::CTL: CLK8OEN Mask               */
+
+#define SDH_CTL_CLKKEEP_Pos              (7)                                               /*!< SDH_T::CTL: CLKKEEP Position          */
+#define SDH_CTL_CLKKEEP_Msk              (0x1ul << SDH_CTL_CLKKEEP_Pos)                    /*!< SDH_T::CTL: CLKKEEP Mask              */
+
+#define SDH_CTL_CMDCODE_Pos              (8)                                               /*!< SDH_T::CTL: CMDCODE Position           */
+#define SDH_CTL_CMDCODE_Msk              (0x3ful << SDH_CTL_CMDCODE_Pos)                   /*!< SDH_T::CTL: CMDCODE Mask               */
+
+#define SDH_CTL_CTLRST_Pos               (14)                                              /*!< SDH_T::CTL: CTLRST Position            */
+#define SDH_CTL_CTLRST_Msk               (0x1ul << SDH_CTL_CTLRST_Pos)                     /*!< SDH_T::CTL: CTLRST Mask                */
+
+#define SDH_CTL_DBW_Pos                  (15)                                              /*!< SDH_T::CTL: DBW Position               */
+#define SDH_CTL_DBW_Msk                  (0x1ul << SDH_CTL_DBW_Pos)                        /*!< SDH_T::CTL: DBW Mask                   */
+
+#define SDH_CTL_BLKCNT_Pos               (16)                                              /*!< SDH_T::CTL: BLKCNT Position            */
+#define SDH_CTL_BLKCNT_Msk               (0xfful << SDH_CTL_BLKCNT_Pos)                    /*!< SDH_T::CTL: BLKCNT Mask                */
+
+#define SDH_CTL_SDNWR_Pos                (24)                                              /*!< SDH_T::CTL: SDNWR Position             */
+#define SDH_CTL_SDNWR_Msk                (0xful << SDH_CTL_SDNWR_Pos)                      /*!< SDH_T::CTL: SDNWR Mask                 */
+
+#define SDH_CTL_SDPORT_Pos               (29)                                              /*!< SDH CTL: SDPORT Position               */
+#define SDH_CTL_SDPORT_Msk               (0x3ul << SDH_CTL_SDPORT_Pos)                     /*!< SDH CTL: SDPORT Mask                   */
+
+#define SDH_CTL_CLKKEEP1_Pos             (31)                                              /*!< SDH CTL: CLKKEEP1 Position             */
+#define SDH_CTL_CLKKEEP1_Msk             (0x1ul << SDH_CTL_CLKKEEP1_Pos)                   /*!< SDH CTL: CLKKEEP1 Mask                 */
+
+#define SDH_CMDARG_ARGUMENT_Pos          (0)                                               /*!< SDH_T::CMDARG: ARGUMENT Position       */
+#define SDH_CMDARG_ARGUMENT_Msk          (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos)         /*!< SDH_T::CMDARG: ARGUMENT Mask           */
+
+#define SDH_INTEN_BLKDIEN_Pos            (0)                                               /*!< SDH_T::INTEN: BLKDIEN Position         */
+#define SDH_INTEN_BLKDIEN_Msk            (0x1ul << SDH_INTEN_BLKDIEN_Pos)                  /*!< SDH_T::INTEN: BLKDIEN Mask             */
+
+#define SDH_INTEN_CRCIEN_Pos             (1)                                               /*!< SDH_T::INTEN: CRCIEN Position          */
+#define SDH_INTEN_CRCIEN_Msk             (0x1ul << SDH_INTEN_CRCIEN_Pos)                   /*!< SDH_T::INTEN: CRCIEN Mask              */
+
+#define SDH_INTEN_CDIEN_Pos              (8)                                               /*!< SDH_T::INTEN: CDIEN Position          */
+#define SDH_INTEN_CDIEN_Msk              (0x1ul << SDH_INTEN_CDIEN_Pos)                    /*!< SDH_T::INTEN: CDIEN Mask              */
+
+#define SDH_INTEN_CDIEN1_Pos             (9)                                               /*!< SDH INTEN: CDIEN1 Position             */
+#define SDH_INTEN_CDIEN1_Msk             (0x1ul << SDH_INTEN_CDIEN1_Pos)                   /*!< SDH INTEN: CDIEN1 Mask                 */
+
+#define SDH_INTEN_SDHOST0IEN_Pos         (10)                                              /*!< SDH INTSTS: SDHOST0IEN Position        */
+#define SDH_INTEN_SDHOST0IEN_Msk         (0x1ul << SDH_INTEN_SDHOST0IEN_Pos)               /*!< SDH INTSTS: SDHOST0IEN Mask            */
+
+#define SDH_INTEN_SDHOST1IEN_Pos         (11)                                              /*!< SDH INTSTS: SDHOST1IEN Position        */
+#define SDH_INTEN_SDHOST1IEN_Msk         (0x1ul << SDH_INTEN_SDHOST1IEN_Pos)               /*!< SDH INTSTS: SDHOST1IEN Mask            */
+
+#define SDH_INTEN_RTOIEN_Pos             (12)                                              /*!< SDH INTEN: RTOIEN Position             */
+#define SDH_INTEN_RTOIEN_Msk             (0x1ul << SDH_INTEN_RTOIEN_Pos)                   /*!< SDH INTEN: RTOIEN Mask                 */
+
+#define SDH_INTEN_DITOIEN_Pos            (13)                                              /*!< SDH_T::INTEN: DITOIEN Position         */
+#define SDH_INTEN_DITOIEN_Msk            (0x1ul << SDH_INTEN_DITOIEN_Pos)                  /*!< SDH_T::INTEN: DITOIEN Mask             */
+
+#define SDH_INTEN_WKIEN_Pos              (14)                                              /*!< SDH_T::INTEN: WKIEN Position           */
+#define SDH_INTEN_WKIEN_Msk              (0x1ul << SDH_INTEN_WKIEN_Pos)                    /*!< SDH_T::INTEN: WKIEN Mask               */
+
+#define SDH_INTEN_CDSRC_Pos              (30)                                              /*!< SDH_T::INTEN: CDSRC Position          */
+#define SDH_INTEN_CDSRC_Msk              (0x1ul << SDH_INTEN_CDSRC_Pos)                    /*!< SDH_T::INTEN: CDSRC Mask              */
+
+#define SDH_INTEN_CDSRC1_Pos             (31)                                              /*!< SDH INTEN: CDSRC1 Position             */
+#define SDH_INTEN_CDSRC1_Msk             (0x1ul << SDH_INTEN_CDSRC1_Pos)                   /*!< SDH INTEN: CDSRC1 Mask                 */
+
+#define SDH_INTSTS_BLKDIF_Pos            (0)                                               /*!< SDH_T::INTSTS: BLKDIF Position         */
+#define SDH_INTSTS_BLKDIF_Msk            (0x1ul << SDH_INTSTS_BLKDIF_Pos)                  /*!< SDH_T::INTSTS: BLKDIF Mask             */
+
+#define SDH_INTSTS_CRCIF_Pos             (1)                                               /*!< SDH_T::INTSTS: CRCIF Position          */
+#define SDH_INTSTS_CRCIF_Msk             (0x1ul << SDH_INTSTS_CRCIF_Pos)                   /*!< SDH_T::INTSTS: CRCIF Mask              */
+
+#define SDH_INTSTS_CRC7_Pos              (2)                                               /*!< SDH_T::INTSTS: CRC7 Position           */
+#define SDH_INTSTS_CRC7_Msk              (0x1ul << SDH_INTSTS_CRC7_Pos)                    /*!< SDH_T::INTSTS: CRC7 Mask               */
+
+#define SDH_INTSTS_CRC16_Pos             (3)                                               /*!< SDH_T::INTSTS: CRC16 Position          */
+#define SDH_INTSTS_CRC16_Msk             (0x1ul << SDH_INTSTS_CRC16_Pos)                   /*!< SDH_T::INTSTS: CRC16 Mask              */
+
+#define SDH_INTSTS_CRCSTS_Pos            (4)                                               /*!< SDH_T::INTSTS: CRCSTS Position         */
+#define SDH_INTSTS_CRCSTS_Msk            (0x7ul << SDH_INTSTS_CRCSTS_Pos)                  /*!< SDH_T::INTSTS: CRCSTS Mask             */
+
+#define SDH_INTSTS_DAT0STS_Pos           (7)                                               /*!< SDH_T::INTSTS: DAT0STS Position        */
+#define SDH_INTSTS_DAT0STS_Msk           (0x1ul << SDH_INTSTS_DAT0STS_Pos)                 /*!< SDH_T::INTSTS: DAT0STS Mask            */
+
+#define SDH_INTSTS_CDIF_Pos              (8)                                               /*!< SDH_T::INTSTS: CDIF Position          */
+#define SDH_INTSTS_CDIF_Msk              (0x1ul << SDH_INTSTS_CDIF_Pos)                    /*!< SDH_T::INTSTS: CDIF Mask              */
+
+#define SDH_INTSTS_CDIF1_Pos             (9)                                               /*!< SDH INTSTS: CDIF1 Position             */
+#define SDH_INTSTS_CDIF1_Msk             (0x1ul << SDH_INTSTS_CDIF1_Pos)                   /*!< SDH INTSTS: CDIF1 Mask                 */
+
+#define SDH_INTSTS_SDHOST0IF_Pos         (10)                                              /*!< SDH INTSTS: SDHOST0IF Position         */
+#define SDH_INTSTS_SDHOST0IF_Msk         (0x1ul << SDH_INTSTS_SDHOST0IF_Pos)               /*!< SDH INTSTS: SDHOST0IF Mask             */
+
+#define SDH_INTSTS_SDHOST1IF_Pos         (11)                                              /*!< SDH INTSTS: SDHOST1IF Position         */
+#define SDH_INTSTS_SDHOST1IF_Msk         (0x1ul << SDH_INTSTS_SDHOST1IF_Pos)               /*!< SDH INTSTS: SDHOST1IF Mask             */
+
+#define SDH_INTSTS_RTOIF_Pos             (12)                                              /*!< SDH_T::INTSTS: RTOIF Position          */
+#define SDH_INTSTS_RTOIF_Msk             (0x1ul << SDH_INTSTS_RTOIF_Pos)                   /*!< SDH_T::INTSTS: RTOIF Mask              */
+
+#define SDH_INTSTS_DITOIF_Pos            (13)                                              /*!< SDH_T::INTSTS: DITOIF Position         */
+#define SDH_INTSTS_DITOIF_Msk            (0x1ul << SDH_INTSTS_DITOIF_Pos)                  /*!< SDH_T::INTSTS: DITOIF Mask             */
+
+#define SDH_INTSTS_CDSTS_Pos             (16)                                              /*!< SDH_T::INTSTS: CDSTS Position         */
+#define SDH_INTSTS_CDSTS_Msk             (0x1ul << SDH_INTSTS_CDSTS_Pos)                   /*!< SDH_T::INTSTS: CDSTS Mask             */
+
+#define SDH_INTSTS_CDSTS1_Pos            (17)                                              /*!< SDH INTSTS: CDSTS1 Position            */
+#define SDH_INTSTS_CDSTS1_Msk            (0x1ul << SDH_INTSTS_CDSTS1_Pos)                  /*!< SDH INTSTS: CDSTS1 Mask                */
+
+#define SDH_INTSTS_DAT1STS_Pos           (18)                                              /*!< SDH_T::INTSTS: DAT1STS Position        */
+#define SDH_INTSTS_DAT1STS_Msk           (0x1ul << SDH_INTSTS_DAT1STS_Pos)                 /*!< SDH_T::INTSTS: DAT1STS Mask            */
+
+#define SDH_RESP0_RESPTK0_Pos            (0)                                               /*!< SDH_T::RESP0: RESPTK0 Position         */
+#define SDH_RESP0_RESPTK0_Msk            (0xfffffffful << SDH_RESP0_RESPTK0_Pos)           /*!< SDH_T::RESP0: RESPTK0 Mask             */
+
+#define SDH_RESP1_RESPTK1_Pos            (0)                                               /*!< SDH_T::RESP1: RESPTK1 Position         */
+#define SDH_RESP1_RESPTK1_Msk            (0xfful << SDH_RESP1_RESPTK1_Pos)                 /*!< SDH_T::RESP1: RESPTK1 Mask             */
+
+#define SDH_BLEN_BLKLEN_Pos              (0)                                               /*!< SDH_T::BLEN: BLKLEN Position           */
+#define SDH_BLEN_BLKLEN_Msk              (0x7fful << SDH_BLEN_BLKLEN_Pos)                  /*!< SDH_T::BLEN: BLKLEN Mask               */
+
+#define SDH_TOUT_TOUT_Pos                (0)                                               /*!< SDH_T::TOUT: TOUT Position             */
+#define SDH_TOUT_TOUT_Msk                (0xfffffful << SDH_TOUT_TOUT_Pos)                 /*!< SDH_T::TOUT: TOUT Mask                 */
+
+/**@}*/ /* SDH_CONST */
+/**@}*/ /* end of SDH register group */
+/**@}*/ /* end of REGISTER group */
+
+#define SDH0                 ((SDH_T *)   FMI_BA)
+#define SDH1                 ((SDH_T *)   SDH_BA)
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SDH_Driver SDH Driver
+  @{
+*/
+
+
+/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants
+  @{
+*/
+
+#define SDH_ERR_ID       0xFFFF0100ul /*!< SDH error ID  \hideinitializer */
+
+#define SDH_TIMEOUT      (SDH_ERR_ID|0x01ul) /*!< Timeout  \hideinitializer */
+#define SDH_NO_MEMORY    (SDH_ERR_ID|0x02ul) /*!< OOM  \hideinitializer */
+
+/*--- define type of SD card or MMC */
+#define SDH_TYPE_UNKNOWN     0ul /*!< Unknown card type  \hideinitializer */
+#define SDH_TYPE_SD_HIGH     1ul /*!< SDHC card  \hideinitializer */
+#define SDH_TYPE_SD_LOW      2ul /*!< SD card  \hideinitializer */
+#define SDH_TYPE_MMC         3ul /*!< MMC card  \hideinitializer */
+#define SDH_TYPE_EMMC        4ul /*!< eMMC card  \hideinitializer */
+
+/* SD error */
+#define SDH_NO_SD_CARD       (SDH_ERR_ID|0x10ul) /*!< Card removed  \hideinitializer */
+#define SDH_ERR_DEVICE       (SDH_ERR_ID|0x11ul) /*!< Device error  \hideinitializer */
+#define SDH_INIT_TIMEOUT     (SDH_ERR_ID|0x12ul) /*!< Card init timeout  \hideinitializer */
+#define SDH_SELECT_ERROR     (SDH_ERR_ID|0x13ul) /*!< Card select error  \hideinitializer */
+#define SDH_WRITE_PROTECT    (SDH_ERR_ID|0x14ul) /*!< Card write protect  \hideinitializer */
+#define SDH_INIT_ERROR       (SDH_ERR_ID|0x15ul) /*!< Card init error  \hideinitializer */
+#define SDH_CRC7_ERROR       (SDH_ERR_ID|0x16ul) /*!< CRC 7 error  \hideinitializer */
+#define SDH_CRC16_ERROR      (SDH_ERR_ID|0x17ul) /*!< CRC 16 error  \hideinitializer */
+#define SDH_CRC_ERROR        (SDH_ERR_ID|0x18ul) /*!< CRC error  \hideinitializer */
+#define SDH_CMD8_ERROR       (SDH_ERR_ID|0x19ul) /*!< Command 8 error  \hideinitializer */
+
+#define MMC_FREQ        20000ul   /*!< output 20MHz to MMC  \hideinitializer */
+#define SD_FREQ         25000ul   /*!< output 25MHz to SD  \hideinitializer */
+#define SDHC_FREQ       50000ul   /*!< output 50MHz to SDH \hideinitializer */
+
+#define SD_PORT0        (1 << 0)  /*!< Card select SD0 \hideinitializer */
+#define SD_PORT1        (1 << 2)  /*!< Card select SD1 \hideinitializer */
+#define CardDetect_From_GPIO  (1ul << 8)   /*!< Card detection pin is GPIO \hideinitializer */
+#define CardDetect_From_DAT3  (1ul << 9)   /*!< Card detection pin is DAT3 \hideinitializer */
+
+/*@}*/ /* end of group N9H30_SDH_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_SDH_EXPORTED_TYPEDEF SDH Exported Type Defines
+  @{
+*/
+
+/** \brief  Structure type of inserted Card information.
+ */
+typedef struct SDH_info_t
+{
+    unsigned char   IsCardInsert;   /*!< Card insert state */
+    unsigned char   R3Flag;
+    unsigned char   R7Flag;
+    unsigned char volatile DataReadyFlag;
+    unsigned int    CardType;       /*!< SDHC, SD, or MMC */
+    unsigned int    RCA;            /*!< Relative card address */
+    unsigned int    totalSectorN;   /*!< Total sector number */
+    unsigned int    diskSize;       /*!< Disk size in K bytes */
+    int             sectorSize;     /*!< Sector size in bytes */
+    unsigned char   *dmabuf;
+} SDH_INFO_T;                      /*!< Structure holds SD card info */
+
+/*@}*/ /* end of group N9H30_SDH_EXPORTED_TYPEDEF */
+
+/// @cond HIDDEN_SYMBOLS
+extern SDH_INFO_T SD0, SD1;
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup N9H30_SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+
+
+/**
+ *  @brief    Enable specified interrupt.
+ *
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
+ *                           \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
+ *                           \ref SDH_INTEN_WKIEN_Msk
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_ENABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN |= (u32IntMask))
+
+/**
+ *  @brief    Disable specified interrupt.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
+ *                           \ref SDH_INTEN_SDHOST0IEN_Msk / \ref SDH_INTEN_SDHOST1IEN_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
+ *                           \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_DISABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN &= ~(u32IntMask))
+
+/**
+ *  @brief    Get specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
+ *                           \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / \ref SDH_INTSTS_CDIF0_Msk /
+ *                           \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_SDHOST0IF_Msk / \ref SDH_INTSTS_SDHOST1IF_Msk / \ref SDH_INTSTS_RTOIF_Msk /
+ *                           \ref SDH_INTSTS_DINTOIF_Msk / \ref SDH_INTSTS_CDSTS0_Msk / \ref SDH_INTSTS_CDSTS1_Msk / \ref SDH_INTSTS_DAT1STS_Msk
+ *
+ *
+ *  @return  0 = The specified interrupt is not happened.
+ *            1 = The specified interrupt is happened.
+ * \hideinitializer
+ */
+#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0)
+
+
+/**
+ *  @brief    Clear specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF0_Msk /
+ *                           \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_SDHOST0IF_Msk / \ref SDH_INTSTS_SDHOST1IF_Msk /
+ *                           \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DINTOIF_Msk
+ *
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask))
+
+
+/**
+ *  @brief    Check SD Card inserted or removed.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return   1: Card inserted.
+ *            0: Card removed.
+ * \hideinitializer
+ */
+#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert)
+
+/**
+ *  @brief    Get SD Card capacity.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return   SD Card capacity. (unit: KByte)
+ * \hideinitializer
+ */
+#define SDH_GET_CARD_CAPACITY(sdh)  (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize)
+
+
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
+uint32_t SDH_Probe(SDH_T *sdh);
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+
+uint32_t SDH_CardDetection(SDH_T *sdh);
+void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc);
+void SDH_Close_Disk(SDH_T *sdh);
+
+
+/*@}*/ /* end of group N9H30_SDH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SDH_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif  //end of __NU_SDH_H__
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_spi.h

@@ -0,0 +1,121 @@
+/**************************************************************************//**
+* @file     spi.h
+* @brief    N9H30 SPI driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_SPI_H__
+#define __NU_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SPI_Driver SPI Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SPI_EXPORTED_CONSTANTS SPI Exported Constants
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+#define CNTRL   0x00    /*!< Control Register Address */
+#define DIVIDER 0x04    /*!< Divider Register Address */
+#define SSR     0x08    /*!< Slave Select Register Address */
+#define RX0     0x10    /*!< Receive Register 0 Address */
+#define RX1     0x14    /*!< Receive Register 1 Address */
+#define RX2     0x18    /*!< Receive Register 2 Address */
+#define RX3     0x1C    /*!< Receive Register 3 Address */
+#define TX0     0x10    /*!< Transfer Register 0 Address */
+#define TX1     0x14    /*!< Transfer Register 1 Address */
+#define TX2     0x18    /*!< Transfer Register 2 Address */
+#define TX3     0x1C    /*!< Transfer Register 3 Address */
+
+#define SPI_INPUT_CLOCK         75000000        /* Unit: Hz */
+/// @endcond HIDDEN_SYMBOLS
+
+#define SPI_NUMBER  2       /*!< 2 spi interfaces  */
+
+#define SPI_NO_ERR      0   /*!< No error  */
+
+#define SPI_ERR_NODEV   -1  /*!< Wrong device id  */
+#define SPI_ERR_BUSY    -2  /*!< Interface is busy  */
+#define SPI_ERR_IO      -3  /*!< IO control error for not opened interface  */
+#define SPI_ERR_ARG     -4  /*!< Wrong argument in IO control  */
+
+#define SPI_IOC_TRIGGER                 0   /*!< Trigger SPI interface */
+#define SPI_IOC_SET_INTERRUPT           1   /*!< Enable/disable interrupt ,arguments could be \ref SPI_DISABLE_INTERRUPT and \ref SPI_ENABLE_INTERRUPT */
+#define SPI_IOC_SET_SPEED               2   /*!< Set SPI clock speed */
+#define SPI_IOC_SET_DUAL_QUAD_MODE      3   /*!< Enable/disable Quad/Dual mode ,arguments could be \ref SPI_DISABLE_DUAL_QUAD, \ref SPI_DUAL_MODE, \ref SPI_QUAD_MODE*/
+#define SPI_IOC_SET_DUAL_QUAD_DIR       4   /*!< Set Quad/Dual mode direction ,arguments could be \ref SPI_DUAL_QUAD_INPUT, \ref SPI_DUAL_QUAD_OUTPUT */
+#define SPI_IOC_SET_LSB_MSB             5   /*!< Set MSB/LSB ,arguments could be \ref SPI_MSB, \ref SPI_LSB */
+#define SPI_IOC_SET_TX_NUM              6   /*!< Set transfer number */
+#define SPI_IOC_SET_TX_BITLEN           7   /*!< Set transfer bit number */
+#define SPI_IOC_SET_MODE                8   /*!< Set SPI mode ,arguments could be \ref SPI_MODE_0, \ref SPI_MODE_1, \ref SPI_MODE_2, \ref SPI_MODE_3 */
+#define SPI_IOC_ENABLE_SS               9   /*!< Enable slave select pin */
+#define SPI_IOC_DISABLE_SS              10  /*!< Disable slave select pin */
+#define SPI_IOC_SET_AUTOSS              11  /*!< Enable/disable auto slave select function ,arguments could be \ref SPI_DISABLE_AUTOSS, \ref SPI_ENABLE_AUTOSS */
+#define SPI_IOC_SET_SS_ACTIVE_LEVEL     12  /*!< Set slave select active level ,arguments could be \ref SPI_SS_ACTIVE_LOW, \ref SPI_SS_ACTIVE_HIGH */
+
+#define SPI_DISABLE_INTERRUPT   0   /*!< Disable interrupt */
+#define SPI_ENABLE_INTERRUPT    1   /*!< Enable interrupt */
+
+#define SPI_DISABLE_DUAL_QUAD   0   /*!< Disable quad and dual mode */
+#define SPI_DUAL_MODE           1   /*!< Enable dual mode */
+#define SPI_QUAD_MODE           2   /*!< Enable quad mode */
+
+#define SPI_DUAL_QUAD_INPUT     0   /*!< Set dual/quad mode io direction to input */
+#define SPI_DUAL_QUAD_OUTPUT    1   /*!< Set dual/quad mode io direction to output */
+
+#define SPI_MSB                 0   /*!< Enable MSB */
+#define SPI_LSB                 1   /*!< Enable LSB */
+
+#define SPI_MODE_0              0   /*!< Set to SPI mode 0 */
+#define SPI_MODE_1              1   /*!< Set to SPI mode 1 */
+#define SPI_MODE_2              2   /*!< Set to SPI mode 2 */
+#define SPI_MODE_3              3   /*!< Set to SPI mode 3 */
+
+#define SPI_SS_SS0              0   /*!< Select SS0 */
+#define SPI_SS_SS1              1   /*!< Select SS1 */
+#define SPI_SS_BOTH             2   /*!< Select both SS0/SS1 */
+
+#define SPI_DISABLE_AUTOSS      0   /*!< Disable auto slave select function */
+#define SPI_ENABLE_AUTOSS       1   /*!< Enable auto slave select function */
+
+#define SPI_SS_ACTIVE_LOW       0   /*!< Set active level of slave select to low */
+#define SPI_SS_ACTIVE_HIGH      1   /*!< Set active level of slave select to high */
+
+/*@}*/ /* end of group N9H30_SPI_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+int32_t  spiInit(int32_t fd);
+int32_t spiIoctl(int32_t fd, uint32_t cmd, uint32_t arg0, uint32_t arg1);
+int spiOpen(int32_t fd);
+uint8_t spiGetBusyStatus(int32_t fd);
+uint32_t spiRead(int32_t fd, uint8_t buff_id);
+void spiWrite(int32_t fd, uint8_t buff_id, uint32_t data);
+/*@}*/ /* end of group N9H30_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SPI_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_SPI_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_sys.h

@@ -0,0 +1,373 @@
+/**************************************************************************//**
+* @file     sys.h
+* @brief    N9H30 SYS driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_SYS_H__
+#define __NU_SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SYS_Driver SYS Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SYS_EXPORTED_CONSTANTS SYS Exported Constants
+  @{
+*/
+
+/**
+ * @details  Interrupt Number Definition.
+ */
+typedef enum IRQn
+{
+
+    /******  N9H30 Specific Interrupt Numbers *****************************************/
+
+    WDT_IRQn                = 1,       /*!< Watch Dog Timer Interrupt                  */
+    WWDT_IRQn               = 2,       /*!< Windowed-WDT Interrupt                     */
+    LVD_IRQn                = 3,       /*!< Low Voltage Detect Interrupt               */
+    EINT0_IRQn              = 4,       /*!< External Interrupt 0                       */
+    EINT1_IRQn              = 5,       /*!< External Interrupt 1                       */
+    EINT2_IRQn              = 6,       /*!< External Interrupt 2                       */
+    EINT3_IRQn              = 7,       /*!< External Interrupt 3                       */
+    EINT4_IRQn              = 8,       /*!< External Interrupt 4                       */
+    EINT5_IRQn              = 9,       /*!< External Interrupt 5                       */
+    EINT6_IRQn              = 10,      /*!< External Interrupt 6                       */
+    EINT7_IRQn              = 11,      /*!< External Interrupt 7                       */
+    ACTL_IRQn               = 12,      /*!< Audio Controller Interrupt                 */
+    LCD_IRQn                = 13,      /*!< LCD Controller Interrupt                   */
+    CAP_IRQn                = 14,      /*!< Sensor Interface Controller Interrupt      */
+    RTC_IRQn                = 15,      /*!< Real Time Clock Interrupt                  */
+    TMR0_IRQn               = 16,      /*!< Timer 0 Interrupt                          */
+    TMR1_IRQn               = 17,      /*!< Timer 1 Interrupt                          */
+    ADC_IRQn                = 18,      /*!< ADC Interrupt                              */
+    EMC0_RX_IRQn            = 19,      /*!< EMC 0 RX Interrupt                         */
+    EMC1_RX_IRQn            = 20,      /*!< EMC 1 RX Interrupt                         */
+    EMC0_TX_IRQn            = 21,      /*!< EMC 0 TX Interrupt                         */
+    EMC1_TX_IRQn            = 22,      /*!< EMC 1 TX Interrupt                         */
+    EHCI_IRQn               = 23,      /*!< USB 2.0 Host Controller Interrupt          */
+    OHCI_IRQn               = 24,      /*!< USB 1.1 Host Controller Interrupt          */
+    GDMA0_IRQn              = 25,      /*!< GDMA Channel 0 Interrupt                   */
+    GDMA1_IRQn              = 26,      /*!< GDMA Channel 1 Interrupt                   */
+    SDH_IRQn                = 27,      /*!< SD/SDIO Host Interrupt                     */
+    FMI_IRQn                = 28,      /*!< FMI Interrupt                              */
+    USBD_IRQn               = 29,      /*!< USB Device Interrupt                       */
+    TMR2_IRQn               = 30,      /*!< Timer 2 Interrupt                          */
+    TMR3_IRQn               = 31,      /*!< Timer 3 Interrupt                          */
+    TMR4_IRQn               = 32,      /*!< Timer 4 Interrupt                          */
+    JPEG_IRQn               = 33,      /*!< JPEG Engine Interrupt                      */
+    GE2D_IRQn               = 34,      /*!< 2D Graphic Engine Interrupt                */
+    CRPT_IRQn               = 35,      /*!< Cryptographic Accelerator Interrupt        */
+    UART0_IRQn              = 36,      /*!< UART 0 Interrupt                           */
+    UART1_IRQn              = 37,      /*!< UART 1 Interrupt                           */
+    UART2_IRQn              = 38,      /*!< UART 2 Interrupt                           */
+    UART4_IRQn              = 39,      /*!< UART 4 Interrupt                           */
+    UART6_IRQn              = 40,      /*!< UART 6 Interrupt                           */
+    UART8_IRQn              = 41,      /*!< UART 8 Interrupt                           */
+    UART10_IRQn             = 42,      /*!< UART 10 Interrupt                          */
+    UART3_IRQn              = 43,      /*!< UART 3 Interrupt                           */
+    UART5_IRQn              = 44,      /*!< UART 5 Interrupt                           */
+    UART7_IRQn              = 45,      /*!< UART 7 Interrupt                           */
+    UART9_IRQn              = 46,      /*!< UART 9 Interrupt                           */
+    ETMR0_IRQn              = 47,      /*!< Enhanced Timer 0 Interrupt                 */
+    ETMR1_IRQn              = 48,      /*!< Enhanced Timer 1 Interrupt                 */
+    ETMR2_IRQn              = 49,      /*!< Enhanced Timer 2 Interrupt                 */
+    ETMR3_IRQn              = 50,      /*!< Enhanced Timer 3 Interrupt                 */
+    SPI0_IRQn               = 51,      /*!< SPI 0 Interrupt                            */
+    SPI1_IRQn               = 52,      /*!< SPI 1 Interrupt                            */
+    I2C0_IRQn               = 53,      /*!< I2C 0 Interrupt                            */
+    I2C1_IRQn               = 54,      /*!< I2C 1 Interrupt                            */
+    SC0_IRQn                = 55,      /*!< Smart Card 0 Interrupt                     */
+    SC1_IRQn                = 56,      /*!< Smart Card 1 Interrupt                     */
+    GPIO_IRQn               = 57,      /*!< GPIO Interrupt                             */
+    CAN0_IRQn               = 58,      /*!< CAN 0 Interrupt                            */
+    CAN1_IRQn               = 59,      /*!< CAN 1 Interrupt                            */
+    PWM_IRQn                = 60,      /*!< PWM Interrupt                              */
+
+    /* Renaming for RTT porting */
+    IRQ_WDT                = 1,       /*!< Watch Dog Timer Interrupt                  */
+    IRQ_WWDT               = 2,       /*!< Windowed-WDT Interrupt                     */
+    IRQ_LVD                = 3,       /*!< Low Voltage Detect Interrupt               */
+    IRQ_EINT0              = 4,       /*!< External Interrupt 0                       */
+    IRQ_EINT1              = 5,       /*!< External Interrupt 1                       */
+    IRQ_EINT2              = 6,       /*!< External Interrupt 2                       */
+    IRQ_EINT3              = 7,       /*!< External Interrupt 3                       */
+    IRQ_EINT4              = 8,       /*!< External Interrupt 4                       */
+    IRQ_EINT5              = 9,       /*!< External Interrupt 5                       */
+    IRQ_EINT6              = 10,      /*!< External Interrupt 6                       */
+    IRQ_EINT7              = 11,      /*!< External Interrupt 7                       */
+    IRQ_ACTL               = 12,      /*!< Audio Controller Interrupt                 */
+    IRQ_LCD                = 13,      /*!< LCD Controller Interrupt                   */
+    IRQ_CAP                = 14,      /*!< Sensor Interface Controller Interrupt      */
+    IRQ_RTC                = 15,      /*!< Real Time Clock Interrupt                  */
+    IRQ_TMR0               = 16,      /*!< Timer 0 Interrupt                          */
+    IRQ_TMR1               = 17,      /*!< Timer 1 Interrupt                          */
+    IRQ_ADC                = 18,      /*!< ADC Interrupt                              */
+    IRQ_EMC0_RX            = 19,      /*!< EMC 0 RX Interrupt                         */
+    IRQ_EMC1_RX            = 20,      /*!< EMC 1 RX Interrupt                         */
+    IRQ_EMC0_TX            = 21,      /*!< EMC 0 TX Interrupt                         */
+    IRQ_EMC1_TX            = 22,      /*!< EMC 1 TX Interrupt                         */
+    IRQ_EHCI               = 23,      /*!< USB 2.0 Host Controller Interrupt          */
+    IRQ_OHCI               = 24,      /*!< USB 1.1 Host Controller Interrupt          */
+    IRQ_GDMA0              = 25,      /*!< GDMA Channel 0 Interrupt                   */
+    IRQ_GDMA1              = 26,      /*!< GDMA Channel 1 Interrupt                   */
+    IRQ_SDH                = 27,      /*!< SD/SDIO Host Interrupt                     */
+    IRQ_FMI                = 28,      /*!< FMI Interrupt                              */
+    IRQ_USBD               = 29,      /*!< USB Device Interrupt                       */
+    IRQ_TMR2               = 30,      /*!< Timer 2 Interrupt                          */
+    IRQ_TMR3               = 31,      /*!< Timer 3 Interrupt                          */
+    IRQ_TMR4               = 32,      /*!< Timer 4 Interrupt                          */
+    IRQ_JPEG               = 33,      /*!< JPEG Engine Interrupt                      */
+    IRQ_GE2D               = 34,      /*!< 2D Graphic Engine Interrupt                */
+    IRQ_CRPT               = 35,      /*!< Cryptographic Accelerator Interrupt        */
+    IRQ_UART0              = 36,      /*!< UART 0 Interrupt                           */
+    IRQ_UART1              = 37,      /*!< UART 1 Interrupt                           */
+    IRQ_UART2              = 38,      /*!< UART 2 Interrupt                           */
+    IRQ_UART4              = 39,      /*!< UART 4 Interrupt                           */
+    IRQ_UART6              = 40,      /*!< UART 6 Interrupt                           */
+    IRQ_UART8              = 41,      /*!< UART 8 Interrupt                           */
+    IRQ_UART10             = 42,      /*!< UART 10 Interrupt                          */
+    IRQ_UART3              = 43,      /*!< UART 3 Interrupt                           */
+    IRQ_UART5              = 44,      /*!< UART 5 Interrupt                           */
+    IRQ_UART7              = 45,      /*!< UART 7 Interrupt                           */
+    IRQ_UART9              = 46,      /*!< UART 9 Interrupt                           */
+    IRQ_ETMR0              = 47,      /*!< Enhanced Timer 0 Interrupt                 */
+    IRQ_ETMR1              = 48,      /*!< Enhanced Timer 1 Interrupt                 */
+    IRQ_ETMR2              = 49,      /*!< Enhanced Timer 2 Interrupt                 */
+    IRQ_ETMR3              = 50,      /*!< Enhanced Timer 3 Interrupt                 */
+    IRQ_SPI0               = 51,      /*!< SPI 0 Interrupt                            */
+    IRQ_SPI1               = 52,      /*!< SPI 1 Interrupt                            */
+    IRQ_I2C0               = 53,      /*!< I2C 0 Interrupt                            */
+    IRQ_I2C1               = 54,      /*!< I2C 1 Interrupt                            */
+    IRQ_SC0                = 55,      /*!< Smart Card 0 Interrupt                     */
+    IRQ_SC1                = 56,      /*!< Smart Card 1 Interrupt                     */
+    IRQ_GPIO               = 57,      /*!< GPIO Interrupt                             */
+    IRQ_CAN0               = 58,      /*!< CAN 0 Interrupt                            */
+    IRQ_CAN1               = 59,      /*!< CAN 1 Interrupt                            */
+    IRQ_PWM                = 60,      /*!< PWM Interrupt                              */
+}
+IRQn_Type;
+
+/* Define constants for use timer in service parameters.  */
+#define TIMER0            0     /*!< Select Timer0 */
+#define TIMER1            1     /*!< Select Timer1 */
+
+#define ONE_SHOT_MODE     0     /*!< Timer Operation Mode - One Shot */
+#define PERIODIC_MODE     1     /*!< Timer Operation Mode - Periodic */
+#define TOGGLE_MODE       2     /*!< Timer Operation Mode - Toggle */
+
+/* The parameters for sysSetInterruptPriorityLevel() and
+   sysInstallISR() use */
+#define FIQ_LEVEL_0     0       /*!< FIQ Level 0 */
+#define IRQ_LEVEL_1     1       /*!< IRQ Level 1 */
+#define IRQ_LEVEL_2     2       /*!< IRQ Level 2 */
+#define IRQ_LEVEL_3     3       /*!< IRQ Level 3 */
+#define IRQ_LEVEL_4     4       /*!< IRQ Level 4 */
+#define IRQ_LEVEL_5     5       /*!< IRQ Level 5 */
+#define IRQ_LEVEL_6     6       /*!< IRQ Level 6 */
+#define IRQ_LEVEL_7     7       /*!< IRQ Level 7 */
+
+#define ONE_HALF_SECS     0     /*!< WDT interval - 1.5s */
+#define FIVE_SECS         1     /*!< WDT interval - 5s */
+#define TEN_SECS          2     /*!< WDT interval - 10s */
+#define TWENTY_SECS       3     /*!< WDT interval - 20s */
+
+/* Define constants for use AIC in service parameters.  */
+#define SYS_SWI           0     /*!< Exception - SWI */
+#define SYS_D_ABORT       1     /*!< Exception - Data abort */
+#define SYS_I_ABORT       2     /*!< Exception - Instruction abort */
+#define SYS_UNDEFINE      3     /*!< Exception - undefine */
+
+/* The parameters for sysSetLocalInterrupt() use */
+#define ENABLE_IRQ        0x7F  /*!< Enable I-bit of CP15  */
+#define ENABLE_FIQ        0xBF  /*!< Enable F-bit of CP15  */
+#define ENABLE_FIQ_IRQ    0x3F  /*!< Enable I-bit and F-bit of CP15  */
+#define DISABLE_IRQ       0x80  /*!< Disable I-bit of CP15  */
+#define DISABLE_FIQ       0x40  /*!< Disable F-bit of CP15  */
+#define DISABLE_FIQ_IRQ   0xC0  /*!< Disable I-bit and F-bit of CP15  */
+
+/* Define Cache type  */
+#define CACHE_WRITE_BACK        0     /*!< Cache Write-back mode  */
+#define CACHE_WRITE_THROUGH     1     /*!< Cache Write-through mode  */
+#define CACHE_DISABLE           -1    /*!< Cache Disable  */
+
+/** \brief  Structure type of clock source
+ */
+typedef enum CLKn
+{
+
+    SYS_UPLL     = 1,   /*!< UPLL clock */
+    SYS_APLL     = 2,   /*!< APLL clock */
+    SYS_SYSTEM   = 3,   /*!< System clock */
+    SYS_HCLK1    = 4,   /*!< HCLK1 clock */
+    SYS_HCLK234  = 5,   /*!< HCLK234 clock */
+    SYS_PCLK     = 6,   /*!< PCLK clock */
+    SYS_CPU      = 7,   /*!< CPU clock */
+
+}  CLK_Type;
+
+
+
+/// @cond HIDDEN_SYMBOLS
+typedef struct datetime_t
+{
+    UINT32  year;
+    UINT32  mon;
+    UINT32  day;
+    UINT32  hour;
+    UINT32  min;
+    UINT32  sec;
+} DateTime_T;
+
+/* The parameters for sysSetInterruptType() use */
+#define LOW_LEVEL_SENSITIVE        0x00
+#define HIGH_LEVEL_SENSITIVE       0x40
+#define NEGATIVE_EDGE_TRIGGER      0x80
+#define POSITIVE_EDGE_TRIGGER      0xC0
+
+/* The parameters for sysSetGlobalInterrupt() use */
+#define ENABLE_ALL_INTERRUPTS      0
+#define DISABLE_ALL_INTERRUPTS     1
+
+#define MMU_DIRECT_MAPPING  0
+#define MMU_INVERSE_MAPPING 1
+
+
+/* Define constants for use Cache in service parameters.  */
+#define CACHE_4M        2
+#define CACHE_8M        3
+#define CACHE_16M       4
+#define CACHE_32M       5
+#define I_CACHE         6
+#define D_CACHE         7
+#define I_D_CACHE       8
+
+
+/**
+  * @brief      Disable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function disable register write-protection function.
+  *             To unlock the protected register to allow write access.
+  */
+static __inline void SYS_UnlockReg(void)
+{
+    do
+    {
+        outpw(0xB00001FC, 0x59UL);
+        outpw(0xB00001FC, 0x16UL);
+        outpw(0xB00001FC, 0x88UL);
+    }
+    while (inpw(0xB00001FC) == 0UL);
+}
+
+/**
+  * @brief      Enable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function is used to enable register write-protection function.
+  *             To lock the protected register to forbid write access.
+  */
+static __inline void SYS_LockReg(void)
+{
+    outpw(0xB00001FC, 0);
+}
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*@}*/ /* end of group N9H30_SYS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+/* Define system library Timer functions */
+UINT32  sysGetTicks(INT32 nTimeNo);
+INT32   sysResetTicks(INT32 nTimeNo);
+INT32   sysUpdateTickCount(INT32 nTimeNo, UINT32 uCount);
+INT32   sysSetTimerReferenceClock(INT32 nTimeNo, UINT32 uClockRate);
+INT32   sysStartTimer(INT32 nTimeNo, UINT32 uTicksPerSecond, INT32 nOpMode);
+INT32   sysStopTimer(INT32 nTimeNo);
+void    sysClearWatchDogTimerCount(void);
+void    sysClearWatchDogTimerInterruptStatus(void);
+void    sysDisableWatchDogTimer(void);
+void    sysDisableWatchDogTimerReset(void);
+void    sysEnableWatchDogTimer(void);
+void    sysEnableWatchDogTimerReset(void);
+PVOID   sysInstallWatchDogTimerISR(INT32 nIntTypeLevel, PVOID pvNewISR);
+INT32   sysSetWatchDogTimerInterval(INT32 nWdtInterval);
+INT32   sysSetTimerEvent(INT32 nTimeNo, UINT32 uTimeTick, PVOID pvFun);
+void    sysClearTimerEvent(INT32 nTimeNo, UINT32 uTimeEventNo);
+void    sysSetLocalTime(DateTime_T ltime);          /*!< Set local time \hideinitializer */
+void    sysGetCurrentTime(DateTime_T *curTime);     /*!< Get current time \hideinitializer */
+void    sysDelay(UINT32 uTicks);
+
+/* Define system library UART functions */
+//INT8    sysGetChar(void);
+//INT32   sysInitializeUART(void);
+//void    sysprintf(PINT8 pcStr, ...);
+//void    sysPutChar(UINT8 ucCh);
+//INT     sysIsKbHit(void);
+
+/* Define system library AIC functions */
+INT32   sysDisableInterrupt(IRQn_Type eIntNo);
+INT32   sysEnableInterrupt(IRQn_Type eIntNo);
+BOOL    sysGetIBitState(void);              /*!< Get I bit state \hideinitializer */
+UINT32  sysGetInterruptEnableStatus(void);  /*!< Get interrupt enable status \hideinitializer */
+UINT32  sysGetInterruptEnableStatusH(void); /*!< Get interrupt enable status \hideinitializer */
+PVOID   sysInstallExceptionHandler(INT32 nExceptType, PVOID pvNewHandler);
+PVOID   sysInstallFiqHandler(PVOID pvNewISR);
+PVOID   sysInstallIrqHandler(PVOID pvNewISR);
+PVOID   sysInstallISR(INT32 nIntTypeLevel, IRQn_Type eIntNo, PVOID pvNewISR);
+INT32   sysSetGlobalInterrupt(INT32 nIntState);     /*!< Enable/Disable all interrupt \hideinitializer */
+INT32   sysSetInterruptPriorityLevel(IRQn_Type eIntNo, UINT32 uIntLevel);
+INT32   sysSetInterruptType(IRQn_Type eIntNo, UINT32 uIntSourceType);       /*!< Change interrupt type \hideinitializer */
+INT32   sysSetLocalInterrupt(INT32 nIntState);
+
+
+/* Define system library Cache functions */
+void    sysDisableCache(void);
+INT32   sysEnableCache(UINT32 uCacheOpMode);
+void    sysFlushCache(INT32 nCacheType);    /*!< flush cache \hideinitializer */
+BOOL    sysGetCacheState(void);             /*!< get cache state \hideinitializer */
+INT32   sysGetSdramSizebyMB(void);          /*!< Get DRAM size \hideinitializer */
+void    sysInvalidCache(void);              /*!< invalid cache \hideinitializer */
+INT32   sysSetCachePages(UINT32 addr, INT32 size, INT32 cache_mode);    /*!< set cache page \hideinitializer */
+
+int sysSetMMUMappingMethod(int mode);   /*!< MMU mapping \hideinitializer */
+
+UINT32 sysGetClock(CLK_Type clk);
+
+typedef void (*sys_pvFunPtr)();   /* function pointer */
+/// @cond HIDDEN_SYMBOLS
+extern sys_pvFunPtr sysIrqHandlerTable[];
+extern BOOL volatile _sys_bIsAICInitial;
+/// @endcond
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group N9H30_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SYS_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif //__NU_SYS_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_timer.h

@@ -0,0 +1,61 @@
+/**************************************************************************//**
+ * @file     timer.h
+ * @brief    N9H30 series TIMER driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TIMER_H__
+#define __NU_TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "N9H30.h"
+
+#define TIMER_COUNTER_ENABLE      (1UL << 30)     /*!< Timer counter enable  */
+#define TIMER_INTERRUPT_ENABLE    (1UL << 29)     /*!< Timer interrupt enable  */
+
+#define TIMER_ONESHOT_MODE        (0UL)           /*!< Timer working in one shot mode   */
+#define TIMER_PERIODIC_MODE       (1UL << 27)     /*!< Timer working in periodic mode   */
+#define TIMER_CONTINUOUS_MODE     (3UL << 27)     /*!< Timer working in continuous mode */
+
+#define TIMER_COUNTER_RESET       (1UL << 26)     /*!< Timer reset counter */
+#define TIMER_IS_ALIVE            (1UL << 25)     /*!< Timer is alive */
+
+static __inline void TIMER_ClearIntFlag(uint32_t timer)
+{
+    outpw(REG_TMR_ISR, (1 << timer));
+}
+
+static __inline uint32_t TIMER_GetIntFlag(uint32_t timer)
+{
+    return inpw(REG_TMR_ISR) & (1 << timer);
+}
+
+void TIMER_SET_CMP_VALUE(uint32_t timer, uint32_t u32Cmpr);
+void TIMER_SET_OPMODE(uint32_t timer, uint32_t u32OpMode);
+void TIMER_SET_PRESCALE_VALUE(uint32_t timer, uint32_t u32PreScale);
+uint32_t TIMER_GetModuleClock(uint32_t timer);
+void TIMER_Start(uint32_t timer);
+void TIMER_Stop(uint32_t timer);
+void TIMER_ClearCounter(uint32_t timer);
+uint32_t TIMER_GetCounter(uint32_t timer);
+uint32_t TIMER_GetCompareData(uint32_t timer);
+void TIMER_EnableInt(uint32_t timer);
+void TIMER_DisableInt(uint32_t timer);
+void TIMER_Close(uint32_t timer);
+uint32_t TIMER_Open(uint32_t timer, uint32_t u32Mode, uint32_t u32Freq);
+__inline void TIMER_ClearIntFlag(uint32_t timer);
+__inline uint32_t TIMER_GetIntFlag(uint32_t timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_TIMER_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_uart.h

@@ -0,0 +1,773 @@
+/**************************************************************************//**
+* @file     uart.h
+* @version  V1.00
+* @brief    N9H30 UART driver header file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_UART_H__
+#define __NU_UART_H__
+
+#include "N9H30.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_UART_Driver UART Driver
+  @{
+*/
+
+
+
+/*-----------------------------------------*/
+/* marco, type and constant definitions    */
+/*-----------------------------------------*/
+/// @cond HIDDEN_SYMBOLS
+#define UART_NUM         11
+
+#define UARTOFFSET       0x100
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup N9H30_UART_EXPORTED_CONSTANTS UART Exported Constants
+  @{
+*/
+
+#define UARTWRITESIZE    100 /*!< UART max. write size */
+
+#define UARTINTMODE      1   /*!< UART interrupt mode */
+#define UARTPOLLMODE     0   /*!< UART polling mode */
+#define DISABLEALLIER    0   /*!< Disable all interrupt */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART channel number                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ALLCHANNEL  11   /*!< UART ALL  channel */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_FCR constants definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FCR_RFITL_1BYTE      (0x0 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 1 bit */
+#define UART_FCR_RFITL_4BYTES     (0x1 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 4 bits */
+#define UART_FCR_RFITL_8BYTES     (0x2 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 8 bits */
+#define UART_FCR_RFITL_14BYTES    (0x3 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 14 bits */
+#define UART_FCR_RFITL_30BYTES    (0x4 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 30 bits */
+#define UART_FCR_RFITL_46BYTES    (0x5 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 46 bits */
+#define UART_FCR_RFITL_62BYTES    (0x6 << UART_FCR_RFITL_Pos)   /*!< UA_FCR setting to set RX FIFO Trigger Level to 62 bits */
+
+#define UART_FCR_RTS_TRI_LEV_1BYTE      (0x0 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 1 bit */
+#define UART_FCR_RTS_TRI_LEV_4BYTES     (0x1 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 4 bits */
+#define UART_FCR_RTS_TRI_LEV_8BYTES     (0x2 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 8 bits */
+#define UART_FCR_RTS_TRI_LEV_14BYTES    (0x3 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 14 bits */
+#define UART_FCR_RTS_TRI_LEV_30BYTES    (0x4 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 30 bits */
+#define UART_FCR_RTS_TRI_LEV_46BYTES    (0x5 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 46 bits */
+#define UART_FCR_RTS_TRI_LEV_62BYTES    (0x6 << UART_FCR_RTS_TRI_LEV_Pos)  /*!< UA_FCR setting to set RTS Trigger Level to 62 bits */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_LCR constants definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5     (0) /*!< UA_LCR setting to set UART word length to 5 bits */
+#define UART_WORD_LEN_6     (1) /*!< UA_LCR setting to set UART word length to 6 bits */
+#define UART_WORD_LEN_7     (2) /*!< UA_LCR setting to set UART word length to 7 bits */
+#define UART_WORD_LEN_8     (3) /*!< UA_LCR setting to set UART word length to 8 bits */
+
+#define UART_PARITY_NONE    (0x0 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as no parity   */
+#define UART_PARITY_ODD     (0x1 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as odd parity  */
+#define UART_PARITY_EVEN    (0x3 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as even parity */
+#define UART_PARITY_STICK    (0x8 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as stick parity */
+
+#define UART_STOP_BIT_1     (0x0 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for one stop bit  */
+#define UART_STOP_BIT_1_5   (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for 1.5 stop bit when 5-bit word length  */
+#define UART_STOP_BIT_2     (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for two stop bit when 6, 7, 8-bit word length */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS LEVEL TRIGGER constants definitions                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is High Level Tigger   */
+#define UART_RTS_IS_LOW_LEV_TRG  (0x0 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is Low Level Tigger    */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART CTS LEVEL TRIGGER constants definitions                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_CTS_IS_HIGH_LEV_TRG    (0x1 << UART_MSR_LEV_CTS_Pos) /*!< Set CTS is High Level Trigger   */
+#define UART_CTS_IS_LOW_LEV_TRG     (0x0 << UART_MSR_LEV_CTS_Pos) /*!< Set CTS is Low Level Trigger    */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_FUNC_SEL constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNC_SEL_UART  (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set UART Function  (Default) */
+#define UART_FUNC_SEL_LIN   (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set LIN Funciton             */
+#define UART_FUNC_SEL_IrDA  (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set IrDA Function            */
+#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set RS485 Function           */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_LIN_CTL constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_LIN_CTL_LINS_EN        (0x1UL << UART_LIN_CTL_LINS_EN_Pos)       /*!< UA_LIN_CTL setting to set LIN Slave Mode Enable */
+#define UART_LIN_CTL_LINS_HDET_EN   (0x1UL << UART_LIN_CTL_LINS_HDET_EN_Pos)  /*!< UA_LIN_CTL setting to set LIN Slave Header Detection Enable */
+#define UART_LIN_CTL_LINS_ARS_EN    (0x1UL << UART_LIN_CTL_LINS_ARS_EN_Pos)   /*!< UA_LIN_CTL setting to set LIN Slave Automatic Resynchronization Mode Enable */
+#define UART_LIN_CTL_LINS_DUM_EN    (0x1UL << UART_LIN_CTL_LINS_DUM_EN_Pos)   /*!< UA_LIN_CTL setting to set LIN Slave Divider Update Method Enable */
+#define UART_LIN_CTL_LIN_WAKE_EN    (0x1UL << UART_LIN_CTL_LIN_WAKE_EN_Pos)   /*!< UA_LIN_CTL setting to set LIN Wake-Up Mode Enable */
+#define UART_LIN_CTL_LIN_SHD        (0x1UL << UART_LIN_CTL_LIN_SHD_Pos)       /*!< UA_LIN_CTL setting to set LIN TX Send Header Enable */
+#define UART_LIN_CTL_LIN_IDPEN      (0x1UL << UART_LIN_CTL_LIN_IDPEN_Pos)     /*!< UA_LIN_CTL setting to set LIN ID Parity Enable */
+#define UART_LIN_CTL_LIN_BKDET_ENN  (0x1UL << UART_LIN_CTL_LIN_BKDET_EN_Pos)  /*!< UA_LIN_CTL setting to set LIN Break Detection Enable */
+#define UART_LIN_CTL_LIN_RX_DIS     (0x1UL << UART_LIN_CTL_LIN_RX_DIS_Pos)    /*!< UA_LIN_CTL setting to set LIN Receiver Disable */
+#define UART_LIN_CTL_BIT_ERR_EN     (0x1UL << UART_LIN_CTL_BIT_ERR_EN_Pos)    /*!< UA_LIN_CTL setting to set Bit Error Detect Enable */
+#define UART_LIN_CTL_LIN_BKFL(x)    (((x)-1) << UART_LIN_CTL_LIN_BKFL_Pos)  /*!< UA_LIN_CTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */
+#define UART_LIN_CTL_LIN_BS_LEN(x)  (((x)-1) << UART_LIN_CTL_LIN_BS_LEN_Pos)/*!< UA_LIN_CTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */
+#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK             (0x0UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos)    /*!< UA_LIN_CTL setting to set LIN Header Select to break field */
+#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK_SYNC        (0x1UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos)    /*!< UA_LIN_CTL setting to set LIN Header Select to break field and sync field */
+#define UART_LIN_CTL_LIN_HEAD_SEL_BREAK_SYNC_ID     (0x2UL << UART_LIN_CTL_LIN_HEAD_SEL_Pos)    /*!< UA_LIN_CTL setting to set LIN Header Select to break field, sync field and ID field*/
+#define UART_LIN_CTL_LIN_LIN_PID(x) ((x) << UART_LIN_CTL_LIN_PID_Pos)       /*!< UA_LIN_CTL setting to set LIN PID value */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* BAUD constants definitions                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_BAUD_MODE0        (0)  /*!< Set UART Baudrate Mode is Mode0 */
+#define UART_BAUD_MODE2        (UART_BAUD_DIV_X_EN_Msk | UART_BAUD_DIV_X_ONE_Msk)  /*!< Set UART Baudrate Mode is Mode2 */
+
+/* UART THR Bit Field Definitions */
+#define UART_THR_THR_Pos         0                                          /*!< UART THR: THR Position  */
+#define UART_THR_THR_Msk        (0xFFul << UART_THR_THR_Pos)                 /*!< UART THR: THR Mask      */
+
+/* UART RBR Bit Field Definitions */
+#define UART_RBR_RBR_Pos         0                                          /*!< UART RBR: RBR Posistion */
+#define UART_RBR_RBR_Msk        (0xFFul << UART_RBR_RBR_Pos)                 /*!< UART RBR: RBR Mask      */
+
+/* UART IER Bit Field Definitions */
+#define UART_IER_DMA_RX_EN_Pos      15                                      /*!< UART IER: RX DMA Enable Posistion */
+#define UART_IER_DMA_RX_EN_Msk      (1ul << UART_IER_DMA_RX_EN_Pos)         /*!< UART IER: RX DMA Enable Mask      */
+
+#define UART_IER_DMA_TX_EN_Pos      14                                      /*!< UART IER: TX DMA Enable Posistion */
+#define UART_IER_DMA_TX_EN_Msk      (1ul << UART_IER_DMA_TX_EN_Pos)         /*!< UART IER: TX DMA Enable Mask      */
+
+#define UART_IER_AUTO_CTS_EN_Pos    13                                      /*!< UART IER: AUTO_CTS_EN Posistion      */
+#define UART_IER_AUTO_CTS_EN_Msk    (1ul << UART_IER_AUTO_CTS_EN_Pos)       /*!< UART IER: AUTO_CTS_EN Mask           */
+
+#define UART_IER_AUTO_RTS_EN_Pos    12                                      /*!< UART IER: AUTO_RTS_EN Posistion      */
+#define UART_IER_AUTO_RTS_EN_Msk    (1ul << UART_IER_AUTO_RTS_EN_Pos)       /*!< UART IER: AUTO_RTS_EN Mask           */
+
+#define UART_IER_TIME_OUT_EN_Pos    11                                      /*!< UART IER: TIME_OUT_EN Posistion      */
+#define UART_IER_TIME_OUT_EN_Msk    (1ul << UART_IER_TIME_OUT_EN_Pos)       /*!< UART IER: TIME_OUT_EN Mask           */
+
+#define UART_IER_LIN_RX_BRK_IEN_Pos 8                                       /*!< UART IER: LIN_RX_BRK_IEN Posistion   */
+#define UART_IER_LIN_RX_BRK_IEN_Msk (1ul << UART_IER_LIN_RX_BRK_IEN_Pos)    /*!< UART IER: LIN_RX_BRK_IEN Mask        */
+
+#define UART_IER_WAKE_EN_Pos        6                                       /*!< UART IER: WAKE_EN Posistion          */
+#define UART_IER_WAKE_EN_Msk        (1ul << UART_IER_WAKE_EN_Pos)           /*!< UART IER: WAKE_EN Mask               */
+
+#define UART_IER_BUF_ERR_IEN_Pos    5                                       /*!< UART IER: BUF_ERR_IEN Posistion      */
+#define UART_IER_BUF_ERR_IEN_Msk    (1ul << UART_IER_BUF_ERR_IEN_Pos)       /*!< UART IER: BUF_ERR_IEN Mask           */
+
+#define UART_IER_RTO_IEN_Pos        4                                       /*!< UART IER: RTO_IEN Posistion          */
+#define UART_IER_RTO_IEN_Msk        (1ul << UART_IER_RTO_IEN_Pos)           /*!< UART IER: RTO_IEN Mask               */
+
+#define UART_IER_MODEM_IEN_Pos      3                                       /*!< UART IER: MODEM_IEN Posistion        */
+#define UART_IER_MODEM_IEN_Msk      (1ul << UART_IER_MODEM_IEN_Pos)         /*!< UART IER: MODEM_IEN Mask             */
+
+#define UART_IER_RLS_IEN_Pos        2                                       /*!< UART IER: RLS_IEN Posistion          */
+#define UART_IER_RLS_IEN_Msk        (1ul << UART_IER_RLS_IEN_Pos)           /*!< UART IER: RLS_IEN Mask               */
+
+#define UART_IER_THRE_IEN_Pos       1                                       /*!< UART IER: THRE_IEN Posistion         */
+#define UART_IER_THRE_IEN_Msk       (1ul << UART_IER_THRE_IEN_Pos)          /*!< UART IER: THRE_IEN Mask              */
+
+#define UART_IER_RDA_IEN_Pos        0                                       /*!< UART IER: RDA_IEN Position           */
+#define UART_IER_RDA_IEN_Msk        (1ul << UART_IER_RDA_IEN_Pos)           /*!< UART IER: RDA_IEN Mask               */
+
+/* UART FCR Bit Field Definitions */
+#define UART_FCR_RTS_TRI_LEV_Pos    16                                      /*!< UART FCR: RTS_TRI_LEV Position       */
+#define UART_FCR_RTS_TRI_LEV_Msk    (0xFul << UART_FCR_RTS_TRI_LEV_Pos)     /*!< UART FCR: RTS_TRI_LEV Mask           */
+
+#define UART_FCR_RX_DIS_Pos         8                                       /*!< UART FCR: RX_DIS Position            */
+#define UART_FCR_RX_DIS_Msk         (1ul << UART_FCR_RX_DIS_Pos)            /*!< UART FCR: RX_DIS Mask                */
+
+#define UART_FCR_RFITL_Pos          4                                       /*!< UART FCR: RFITL Position             */
+#define UART_FCR_RFITL_Msk          (0xFul << UART_FCR_RFITL_Pos)           /*!< UART FCR: RFITL Mask                 */
+
+#define UART_FCR_TFR_Pos            2                                       /*!< UART FCR: TFR Position               */
+#define UART_FCR_TFR_Msk            (1ul << UART_FCR_TFR_Pos)               /*!< UART FCR: TFR Mask                   */
+
+#define UART_FCR_RFR_Pos            1                                       /*!< UART FCR: RFR Position               */
+#define UART_FCR_RFR_Msk            (1ul << UART_FCR_RFR_Pos)               /*!< UART FCR: RFR Mask                   */
+
+/* UART LCR Bit Field Definitions */
+#define UART_LCR_BCB_Pos            6                                       /*!< UART LCR: BCB Position               */
+#define UART_LCR_BCB_Msk            (1ul << UART_LCR_BCB_Pos)               /*!< UART LCR: BCB Mask                   */
+
+#define UART_LCR_SPE_Pos            5                                       /*!< UART LCR: SPE Position               */
+#define UART_LCR_SPE_Msk            (1ul << UART_LCR_SPE_Pos)               /*!< UART LCR: SPE Mask                   */
+
+#define UART_LCR_EPE_Pos            4                                       /*!< UART LCR: EPE Position               */
+#define UART_LCR_EPE_Msk            (1ul << UART_LCR_EPE_Pos)               /*!< UART LCR: EPE Mask                   */
+
+#define UART_LCR_PBE_Pos            3                                       /*!< UART LCR: PBE Position               */
+#define UART_LCR_PBE_Msk            (1ul << UART_LCR_PBE_Pos)               /*!< UART LCR: PBE Mask                   */
+
+#define UART_LCR_NSB_Pos            2                                       /*!< UART LCR: NSB Position               */
+#define UART_LCR_NSB_Msk            (1ul << UART_LCR_NSB_Pos)               /*!< UART LCR: NSB Mask                   */
+
+#define UART_LCR_WLS_Pos            0                                       /*!< UART LCR: WLS Position               */
+#define UART_LCR_WLS_Msk            (0x3ul << UART_LCR_WLS_Pos)             /*!< UART LCR: WLS Mask                   */
+
+/* UART MCR Bit Field Definitions */
+#define UART_MCR_RTS_ST_Pos         13                                      /*!< UART MCR: RTS_ST Position            */
+#define UART_MCR_RTS_ST_Msk         (1ul << UART_MCR_RTS_ST_Pos)            /*!< UART MCR: RTS_ST Mask                */
+
+#define UART_MCR_LEV_RTS_Pos        9                                       /*!< UART MCR: LEV_RTS Position           */
+#define UART_MCR_LEV_RTS_Msk        (1ul << UART_MCR_LEV_RTS_Pos)           /*!< UART MCR: LEV_RTS Mask               */
+
+#define UART_MCR_RTS_Pos            1                                       /*!< UART MCR: RTS Position               */
+#define UART_MCR_RTS_Msk            (1ul << UART_MCR_RTS_Pos)               /*!< UART MCR: RTS Mask                   */
+
+/* UART MSR Bit Field Definitions */
+#define UART_MSR_LEV_CTS_Pos        8                                       /*!< UART MSR: LEV_CTS Position           */
+#define UART_MSR_LEV_CTS_Msk        (1ul << UART_MSR_LEV_CTS_Pos)           /*!< UART MSR: LEV_CTS Mask               */
+
+#define UART_MSR_CTS_ST_Pos         4                                       /*!< UART MSR: CTS_ST Position            */
+#define UART_MSR_CTS_ST_Msk         (1ul << UART_MSR_CTS_ST_Pos)            /*!< UART MSR: CTS_ST Mask                */
+
+#define UART_MSR_DCTSF_Pos          0                                       /*!< UART MSR: DCTST Position             */
+#define UART_MSR_DCTSF_Msk          (1ul << UART_MSR_DCTSF_Pos)             /*!< UART MSR: DCTST Mask                 */
+
+
+/* UART FSR Bit Field Definitions */
+#define UART_FSR_TE_FLAG_Pos        28                                      /*!< UART FSR: TE_FLAG Position           */
+#define UART_FSR_TE_FLAG_Msk        (1ul << UART_FSR_TE_FLAG_Pos)           /*!< UART FSR: TE_FLAG Mask               */
+
+#define UART_FSR_TX_OVER_IF_Pos     24                                      /*!< UART FSR: TX_OVER_IF Position        */
+#define UART_FSR_TX_OVER_IF_Msk     (1ul << UART_FSR_TX_OVER_IF_Pos)        /*!< UART FSR: TX_OVER_IF Mask            */
+
+#define UART_FSR_TX_FULL_Pos        23                                      /*!< UART FSR: TX_FULL Position           */
+#define UART_FSR_TX_FULL_Msk        (1ul << UART_FSR_TX_FULL_Pos)           /*!< UART FSR: TX_FULL Mask               */
+
+#define UART_FSR_TX_EMPTY_Pos       22                                      /*!< UART FSR: TX_EMPTY Position          */
+#define UART_FSR_TX_EMPTY_Msk       (1ul << UART_FSR_TX_EMPTY_Pos)          /*!< UART FSR: TX_EMPTY Mask              */
+
+#define UART_FSR_TX_POINTER_Pos     16                                      /*!< UART FSR: TX_POINTER Position        */
+#define UART_FSR_TX_POINTER_Msk     (0x3Ful << UART_FSR_TX_POINTER_Pos)     /*!< UART FSR: TX_POINTER Mask            */
+
+#define UART_FSR_RX_FULL_Pos        15                                      /*!< UART FSR: RX_FULL Position           */
+#define UART_FSR_RX_FULL_Msk        (1ul << UART_FSR_RX_FULL_Pos)           /*!< UART FSR: RX_FULL Mask               */
+
+#define UART_FSR_RX_EMPTY_Pos       14                                      /*!< UART FSR: RX_EMPTY Position          */
+#define UART_FSR_RX_EMPTY_Msk       (1ul << UART_FSR_RX_EMPTY_Pos)          /*!< UART FSR: RX_EMPTY Mask              */
+
+#define UART_FSR_RX_POINTER_Pos     8                                       /*!< UART FSR: RX_POINTERS Position       */
+#define UART_FSR_RX_POINTER_Msk     (0x3Ful << UART_FSR_RX_POINTER_Pos)     /*!< UART FSR: RX_POINTER Mask            */
+
+#define UART_FSR_BIF_Pos            6                                       /*!< UART FSR: BIF Position               */
+#define UART_FSR_BIF_Msk            (1ul << UART_FSR_BIF_Pos)               /*!< UART FSR: BIF Mask                   */
+
+#define UART_FSR_FEF_Pos            5                                       /*!< UART FSR: FEF Position               */
+#define UART_FSR_FEF_Msk            (1ul << UART_FSR_FEF_Pos)               /*!< UART FSR: FEF Mask                   */
+
+#define UART_FSR_PEF_Pos            4                                       /*!< UART FSR: PEF Position               */
+#define UART_FSR_PEF_Msk            (1ul << UART_FSR_PEF_Pos)               /*!< UART FSR: PEF Mask                   */
+
+#define UART_FSR_RS485_ADD_DETF_Pos 3                                       /*!< UART FSR: RS485_ADD_DETF Position    */
+#define UART_FSR_RS485_ADD_DETF_Msk (1ul << UART_FSR_RS485_ADD_DETF_Pos)    /*!< UART FSR: RS485_ADD_DETF Mask        */
+
+#define UART_FSR_RX_OVER_IF_Pos     0                                       /*!< UART FSR: RX_OVER_IF Position        */
+#define UART_FSR_RX_OVER_IF_Msk     (1ul << UART_FSR_RX_OVER_IF_Pos)        /*!< UART FSR: RX_OVER_IF Mask            */
+
+/* UART ISR Bit Field Definitions */
+#define UART_ISR_LIN_RX_BREAK_INT_Pos    15                                      /*!< UART ISR: LIN_RX_BREAK_INT Position       */
+#define UART_ISR_LIN_RX_BREAK_INT_Msk    (1ul << UART_ISR_LIN_RX_BREAK_INT_Pos)  /*!< UART ISR: LIN_RX_BREAK_INT Mask           */
+
+#define UART_ISR_BUF_ERR_INT_Pos    13                                      /*!< UART ISR: BUF_ERR_INT Position       */
+#define UART_ISR_BUF_ERR_INT_Msk    (1ul << UART_ISR_BUF_ERR_INT_Pos)       /*!< UART ISR: BUF_ERR_INT Mask           */
+
+#define UART_ISR_TOUT_INT_Pos       12                                      /*!< UART ISR: TOUT_INT Position          */
+#define UART_ISR_TOUT_INT_Msk       (1ul << UART_ISR_TOUT_INT_Pos)          /*!< UART ISR: TOUT_INT Mask              */
+
+#define UART_ISR_MODEM_INT_Pos      11                                      /*!< UART ISR: MODEM_INT Position         */
+#define UART_ISR_MODEM_INT_Msk      (1ul << UART_ISR_MODEM_INT_Pos)         /*!< UART ISR: MODEM_INT Mask             */
+
+#define UART_ISR_RLS_INT_Pos        10                                      /*!< UART ISR: RLS_INT Position           */
+#define UART_ISR_RLS_INT_Msk        (1ul << UART_ISR_RLS_INT_Pos)           /*!< UART ISR: RLS_INT Mask               */
+
+#define UART_ISR_THRE_INT_Pos       9                                       /*!< UART ISR: THRE_INT Position          */
+#define UART_ISR_THRE_INT_Msk       (1ul << UART_ISR_THRE_INT_Pos)          /*!< UART ISR: THRE_INT Mask              */
+
+#define UART_ISR_RDA_INT_Pos        8                                       /*!< UART ISR: RDA_INT Position           */
+#define UART_ISR_RDA_INT_Msk        (1ul << UART_ISR_RDA_INT_Pos)           /*!< UART ISR: RDA_INT Mask               */
+
+#define UART_ISR_LIN_RX_BREAK_IF_Pos 7                                      /*!< UART ISR: LIN RX BREAK IF Position   */
+#define UART_ISR_LIN_RX_BREAK_IF_Msk (1ul << UART_ISR_LIN_RX_BREAK_IF_Pos)  /*!< UART ISR: LIN RX BREAK IF Mask       */
+
+#define UART_ISR_BUF_ERR_IF_Pos     5                                       /*!< UART ISR: BUF_ERR_IF Position        */
+#define UART_ISR_BUF_ERR_IF_Msk     (1ul << UART_ISR_BUF_ERR_IF_Pos)        /*!< UART ISR: BUF_ERR_IF Mask            */
+
+#define UART_ISR_TOUT_IF_Pos        4                                       /*!< UART ISR: TOUT_IF Position           */
+#define UART_ISR_TOUT_IF_Msk        (1ul << UART_ISR_TOUT_IF_Pos)           /*!< UART ISR: TOUT_IF Mask               */
+
+#define UART_ISR_MODEM_IF_Pos       3                                       /*!< UART ISR: MODEM_IF Position          */
+#define UART_ISR_MODEM_IF_Msk       (1ul << UART_ISR_MODEM_IF_Pos)          /*!< UART ISR: MODEM_IF Mask              */
+
+#define UART_ISR_RLS_IF_Pos         2                                       /*!< UART ISR: RLS_IF Position            */
+#define UART_ISR_RLS_IF_Msk         (1ul << UART_ISR_RLS_IF_Pos)            /*!< UART ISR: RLS_IF Mask                */
+
+#define UART_ISR_THRE_IF_Pos        1                                       /*!< UART ISR: THRE_IF Position           */
+#define UART_ISR_THRE_IF_Msk        (1ul << UART_ISR_THRE_IF_Pos)           /*!< UART ISR: THRE_IF Mask               */
+
+#define UART_ISR_RDA_IF_Pos         0                                       /*!< UART ISR: RDA_IF Position            */
+#define UART_ISR_RDA_IF_Msk         (1ul << UART_ISR_RDA_IF_Pos)            /*!< UART ISR: RDA_IF Mask                */
+
+
+/* UART TOR Bit Field Definitions */
+#define UART_TOR_DLY_Pos           8                                        /*!< UART TOR: DLY Position               */
+#define UART_TOR_DLY_Msk           (0xFFul << UART_TOR_DLY_Pos)             /*!< UART TOR: DLY Mask                   */
+
+#define UART_TOR_TOIC_Pos          0                                        /*!< UART TOR: TOIC Position              */
+#define UART_TOR_TOIC_Msk          (0xFFul << UART_TOR_TOIC_Pos)            /*!< UART TOR: TOIC Mask                  */
+
+/* UART BAUD Bit Field Definitions */
+#define UART_BAUD_DIV_X_EN_Pos    29                                        /*!< UART BARD: DIV_X_EN Position         */
+#define UART_BAUD_DIV_X_EN_Msk    (1ul << UART_BAUD_DIV_X_EN_Pos)           /*!< UART BARD: DIV_X_EN Mask             */
+
+#define UART_BAUD_DIV_X_ONE_Pos   28                                        /*!< UART BARD: DIV_X_ONE Position        */
+#define UART_BAUD_DIV_X_ONE_Msk   (1ul << UART_BAUD_DIV_X_ONE_Pos)          /*!< UART BARD: DIV_X_ONE Mask            */
+
+#define UART_BAUD_DIVIDER_X_Pos   24                                        /*!< UART BARD: DIVIDER_X Position        */
+#define UART_BAUD_DIVIDER_X_Msk   (0xFul << UART_BAUD_DIVIDER_X_Pos)        /*!< UART BARD: DIVIDER_X Mask            */
+
+#define UART_BAUD_BRD_Pos         0                                         /*!< UART BARD: BRD Position              */
+#define UART_BAUD_BRD_Msk         (0xFFFFul << UART_BAUD_BRD_Pos)           /*!< UART BARD: BRD Mask                  */
+
+/* UART IRCR Bit Field Definitions */
+#define UART_IRCR_INV_RX_Pos      6                                         /*!< UART IRCR: INV_RX Position           */
+#define UART_IRCR_INV_RX_Msk     (1ul << UART_IRCR_INV_RX_Pos)              /*!< UART IRCR: INV_RX Mask               */
+
+#define UART_IRCR_INV_TX_Pos      5                                         /*!< UART IRCR: INV_TX Position           */
+#define UART_IRCR_INV_TX_Msk     (1ul << UART_IRCR_INV_TX_Pos)              /*!< UART IRCR: INV_TX Mask               */
+
+#define UART_IRCR_TX_SELECT_Pos   1                                         /*!< UART IRCR: TX_SELECT Position        */
+#define UART_IRCR_TX_SELECT_Msk   (1ul << UART_IRCR_TX_SELECT_Pos)          /*!< UART IRCR: TX_SELECT Mask            */
+
+/* UART ALT_CSR Bit Field Definitions */
+#define UART_ALT_CSR_ADDR_MATCH_Pos      24                                      /*!< UART ALT_CSR: ADDR_MATCH Position    */
+#define UART_ALT_CSR_ADDR_MATCH_Msk     (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos)  /*!< UART ALT_CSR: ADDR_MATCH Mask        */
+
+#define UART_ALT_CSR_RS485_ADD_EN_Pos   15                                       /*!< UART ALT_CSR: RS485_ADD_EN Position  */
+#define UART_ALT_CSR_RS485_ADD_EN_Msk   (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)   /*!< UART ALT_CSR: RS485_ADD_EN Mask      */
+
+#define UART_ALT_CSR_RS485_AUD_Pos      10                                       /*!< UART ALT_CSR: RS485_AUD Position     */
+#define UART_ALT_CSR_RS485_AUD_Msk      (1ul << UART_ALT_CSR_RS485_AUD_Pos)      /*!< UART ALT_CSR: RS485_AUD Mask         */
+
+#define UART_ALT_CSR_RS485_AAD_Pos      9                                        /*!< UART ALT_CSR: RS485_AAD Position     */
+#define UART_ALT_CSR_RS485_AAD_Msk      (1ul << UART_ALT_CSR_RS485_AAD_Pos)      /*!< UART ALT_CSR: RS485_AAD Mask         */
+
+#define UART_ALT_CSR_RS485_NMM_Pos      8                                        /*!< UART ALT_CSR: RS485_NMM Position     */
+#define UART_ALT_CSR_RS485_NMM_Msk      (1ul << UART_ALT_CSR_RS485_NMM_Pos)      /*!< UART ALT_CSR: RS485_NMM Mask         */
+
+#define UART_ALT_CSR_LIN_TX_EN_Pos      7                                        /*!< UART ALT_CSR: LIN TX Break Mode Enable Position     */
+#define UART_ALT_CSR_LIN_TX_EN_Msk      (1ul << UART_ALT_CSR_LIN_TX_EN_Pos)      /*!< UART ALT_CSR: LIN TX Break Mode Enable Mask         */
+
+#define UART_ALT_CSR_LIN_RX_EN_Pos      6                                        /*!< UART ALT_CSR: LIN RX Enable Position     */
+#define UART_ALT_CSR_LIN_RX_EN_Msk      (1ul << UART_ALT_CSR_LIN_RX_EN_Pos)      /*!< UART ALT_CSR: LIN RX Enable Mask         */
+
+#define UART_ALT_CSR_UA_LIN_BKFL_Pos    0                                        /*!< UART ALT_CSR: UART LIN Break Field Length Position     */
+#define UART_ALT_CSR_UA_LIN_BKFL_Msk    (0xFul << UART_ALT_CSR_UA_LIN_BKFL_Pos)  /*!< UART ALT_CSR: UART LIN Break Field Length Mask         */
+
+/* UART FUN_SEL Bit Field Definitions */
+#define UART_FUN_SEL_FUN_SEL_Pos        0                                        /*!< UART FUN_SEL: FUN_SEL Position       */
+#define UART_FUN_SEL_FUN_SEL_Msk       (0x3ul << UART_FUN_SEL_FUN_SEL_Pos)       /*!< UART FUN_SEL: FUN_SEL Mask           */
+
+/* UART LIN_CTL Bit Field Definitions */
+#define UART_LIN_CTL_LIN_PID_Pos        24                                        /*!< UART LIN_CTL: LIN_PID Position       */
+#define UART_LIN_CTL_LIN_PID_Msk        (0xFFul << UART_LIN_CTL_LIN_PID_Pos)      /*!< UART LIN_CTL: LIN_PID Mask           */
+
+#define UART_LIN_CTL_LIN_HEAD_SEL_Pos   22                                        /*!< UART LIN_CTL: LIN_HEAD_SEL Position       */
+#define UART_LIN_CTL_LIN_HEAD_SEL_Msk   (0x3ul << UART_LIN_CTL_LIN_HEAD_SEL_Pos)  /*!< UART LIN_CTL: LIN_HEAD_SEL Mask           */
+
+#define UART_LIN_CTL_LIN_BS_LEN_Pos     20                                        /*!< UART LIN_CTL: LIN_BS_LEN Position       */
+#define UART_LIN_CTL_LIN_BS_LEN_Msk     (0x3ul << UART_LIN_CTL_LIN_BS_LEN_Pos)    /*!< UART LIN_CTL: LIN_BS_LEN Mask           */
+
+#define UART_LIN_CTL_LIN_BKFL_Pos       16                                        /*!< UART LIN_CTL: LIN_BKFL Position       */
+#define UART_LIN_CTL_LIN_BKFL_Msk       (0xFul << UART_LIN_CTL_LIN_BKFL_Pos)      /*!< UART LIN_CTL: LIN_BKFL Mask           */
+
+#define UART_LIN_CTL_BIT_ERR_EN_Pos     12                                        /*!< UART LIN_CTL: BIT_ERR_EN Position       */
+#define UART_LIN_CTL_BIT_ERR_EN_Msk     (1ul << UART_LIN_CTL_BIT_ERR_EN_Pos)      /*!< UART LIN_CTL: BIT_ERR_EN Mask           */
+
+#define UART_LIN_CTL_LIN_RX_DIS_Pos     11                                        /*!< UART LIN_CTL: LIN_RX_DIS Position       */
+#define UART_LIN_CTL_LIN_RX_DIS_Msk     (1ul << UART_LIN_CTL_LIN_RX_DIS_Pos)      /*!< UART LIN_CTL: LIN_RX_DIS Mask           */
+
+#define UART_LIN_CTL_LIN_BKDET_EN_Pos   10                                        /*!< UART LIN_CTL: LIN_BKDET_EN Position       */
+#define UART_LIN_CTL_LIN_BKDET_EN_Msk   (1ul << UART_LIN_CTL_LIN_BKDET_EN_Pos)    /*!< UART LIN_CTL: LIN_BKDET_EN Mask           */
+
+#define UART_LIN_CTL_LIN_IDPEN_Pos      9                                         /*!< UART LIN_CTL: LIN_IDPEN Position       */
+#define UART_LIN_CTL_LIN_IDPEN_Msk      (1ul << UART_LIN_CTL_LIN_IDPEN_Pos)       /*!< UART LIN_CTL: LIN_IDPEN Mask           */
+
+#define UART_LIN_CTL_LIN_SHD_Pos        8                                         /*!< UART LIN_CTL: LIN_SHD Position       */
+#define UART_LIN_CTL_LIN_SHD_Msk        (1ul << UART_LIN_CTL_LIN_SHD_Pos)         /*!< UART LIN_CTL: LIN_SHD Mask           */
+
+#define UART_LIN_CTL_LIN_WAKE_EN_Pos    4                                          /*!< UART LIN_CTL: LIN_WAKE_EN Position       */
+#define UART_LIN_CTL_LIN_WAKE_EN_Msk    (1ul << UART_LIN_CTL_LIN_WAKE_EN_Pos)      /*!< UART LIN_CTL: LIN_WAKE_EN Mask           */
+
+#define UART_LIN_CTL_LINS_DUM_EN_Pos    3                                          /*!< UART LIN_CTL: LINS_DUM_EN Position       */
+#define UART_LIN_CTL_LINS_DUM_EN_Msk    (1ul << UART_LIN_CTL_LINS_DUM_EN_Pos)      /*!< UART LIN_CTL: LINS_DUM_EN Mask           */
+
+#define UART_LIN_CTL_LINS_ARS_EN_Pos    2                                          /*!< UART LIN_CTL: LINS_ARS_EN Position       */
+#define UART_LIN_CTL_LINS_ARS_EN_Msk    (1ul << UART_LIN_CTL_LINS_ARS_EN_Pos)      /*!< UART LIN_CTL: LINS_ARS_EN Mask           */
+
+#define UART_LIN_CTL_LINS_HDET_EN_Pos   1                                          /*!< UART LIN_CTL: LINS_HDET_EN Position       */
+#define UART_LIN_CTL_LINS_HDET_EN_Msk   (1ul << UART_LIN_CTL_LINS_HDET_EN_Pos)     /*!< UART LIN_CTL: LINS_HDET_EN Mask           */
+
+#define UART_LIN_CTL_LINS_EN_Pos        0                                          /*!< UART LIN_CTL: LINS_EN Position       */
+#define UART_LIN_CTL_LINS_EN_Msk        (1ul << UART_LIN_CTL_LINS_EN_Pos)          /*!< UART LIN_CTL: LINS_EN Mask           */
+
+/* UART LIN_SR Bit Field Definitions */
+#define UART_LIN_SR_LINS_SYNC_F_Pos     3                                           /*!< UART LIN_SR: LINS_SYNC_F Position       */
+#define UART_LIN_SR_LINS_SYNC_F_Msk     (1ul << UART_LIN_SR_LINS_SYNC_F_Pos)        /*!< UART LIN_SR: LINS_SYNC_F Mask           */
+
+#define UART_LIN_SR_LINS_IDPERR_F_Pos   2                                           /*!< UART LIN_SR: LINS_IDPERR_F Position       */
+#define UART_LIN_SR_LINS_IDPERR_F_Msk   (1ul << UART_LIN_SR_LINS_IDPERR_F_Pos)      /*!< UART LIN_SR: LINS_IDPERR_F Mask           */
+
+#define UART_LIN_SR_LINS_HERR_F_Pos     1                                           /*!< UART LIN_SR: LINS_HERR_F Position       */
+#define UART_LIN_SR_LINS_HERR_F_Msk     (1ul << UART_LIN_SR_LINS_HERR_F_Pos)        /*!< UART LIN_SR: LINS_HERR_F Mask           */
+
+#define UART_LIN_SR_LINS_HDET_F_Pos     0                                           /*!< UART LIN_SR: LINS_HDET_F Position       */
+#define UART_LIN_SR_LINS_HDET_F_Msk     (1ul << UART_LIN_SR_LINS_HDET_F_Pos)        /*!< UART LIN_SR: LINS_HDET_F Mask           */
+
+/* UART DEBUG Bit Field Definitions */
+#define UART_DEBUG_ERR_DIVIA_F_Pos      0                                           /*!< UART DEBUG: ERR_DIVIA_F Position       */
+#define UART_DEBUG_ERR_DIVIA_F_Msk      (1ul << UART_DEBUG_ERR_DIVIA_F_Pos)         /*!< UART DEBUG: ERR_DIVIA_F Mask           */
+
+#define UART_DEBUG_ERR_HETIME_OUT_F_Pos 1                                           /*!< UART DEBUG: ERR_HETIME_OUT_F Position  */
+#define UART_DEBUG_ERR_HETIME_OUT_F_Msk (1ul << UART_DEBUG_ERR_HETIME_OUT_F_Pos)    /*!< UART DEBUG: ERR_HETIME_OUT_F Mask      */
+
+#define UART_DEBUG_ERR_HEFE_F_Pos       2                                           /*!< UART DEBUG: ERR_HEFE_F Position        */
+#define UART_DEBUG_ERR_HEFE_F_Msk       (1ul << UART_DEBUG_ERR_HEFE_F_Pos)          /*!< UART DEBUG: ERR_HEFE_F Mask            */
+
+#define UART_DEBUG_ERR_SYNC_F_Pos       3                                           /*!< UART DEBUG: ERR_SYNC_F Position        */
+#define UART_DEBUG_ERR_SYNC_F_Msk       (1ul << UART_DEBUG_ERR_SYNC_F_Pos)          /*!< UART DEBUG: ERR_SYNC_F Mask            */
+
+/* UART SC_CTL Bit Field Definitions */
+#define UART_SC_CTL_RX_ERETRY_Pos       0                                           /*!< UART SC_CTL: RX_ERETRY Position        */
+#define UART_SC_CTL_RX_ERETRY_Msk       (7ul << UART_SC_CTL_RX_ERETRY_Pos)          /*!< UART SC_CTL: RX_ERETRY Mask            */
+
+#define UART_SC_CTL_RX_ERETRY_EN_Pos    3                                           /*!< UART SC_CTL: RX_ERETRY_EN Position     */
+#define UART_SC_CTL_RX_ERETRY_EN_Msk    (1ul << UART_SC_CTL_RX_ERETRY_EN_Pos)       /*!< UART SC_CTL: RX_ERETRY_EN Mask         */
+
+#define UART_SC_CTL_TX_ERETRY_Pos       4                                           /*!< UART SC_CTL: TX_ERETRY Position        */
+#define UART_SC_CTL_TX_ERETRY_Msk       (7ul << UART_SC_CTL_TX_ERETRY_Pos)          /*!< UART SC_CTL: TX_ERETRY Mask            */
+
+#define UART_SC_CTL_TX_ERETRY_EN_Pos    7                                           /*!< UART SC_CTL: TX_ERETRY_EN Position     */
+#define UART_SC_CTL_TX_ERETRY_EN_Msk    (1ul << UART_SC_CTL_TX_ERETRY_EN_Pos)       /*!< UART SC_CTL: TX_ERETRY_EN Mask         */
+
+/* UART SC_FSR Bit Field Definitions */
+#define UART_SC_FSR_RX_OVER_ERETRY_Pos      0                                       /*!< UART SC_FSR: RX_OVER_ERETRY Position   */
+#define UART_SC_FSR_RX_OVER_ERETRY_Msk      (1ul << UART_SC_FSR_RX_OVER_ERETRY_Pos) /*!< UART SC_FSR: RX_OVER_ERETRY Mask       */
+
+#define UART_SC_FSR_TX_OVER_ERETRY_Pos      1                                       /*!< UART SC_FSR: TX_OVER_ERETRY Position   */
+#define UART_SC_FSR_TX_OVER_ERETRY_Msk      (1ul << UART_SC_FSR_TX_OVER_ERETRY_Pos) /*!< UART SC_FSR: TX_OVER_ERETRY Mask       */
+
+#define UART_SC_FSR_RX_ERETRY_F_Pos         8                                       /*!< UART SC_FSR: RX_ERETRY_F Position      */
+#define UART_SC_FSR_RX_ERETRY_F_Msk         (1ul << UART_SC_FSR_RX_ERETRY_F_Pos)    /*!< UART SC_FSR: RX_ERETRY_F Mask          */
+
+#define UART_SC_FSR_TX_ERETRY_F_Pos         9                                       /*!< UART SC_FSR: TX_ERETRY_F Position      */
+#define UART_SC_FSR_TX_ERETRY_F_Msk         (1ul << UART_SC_FSR_TX_ERETRY_F_Pos)    /*!< UART SC_FSR: TX_ERETRY_F Mask          */
+
+/*  Enable/Disable IrDA Mode */
+#define ENABLEIrDA            1  /*!< Enable IrDA */
+#define DISABLEIrDA           0  /*!< Disable IrDA */
+
+/*  define IrDA Direction */
+#define IrDA_TX               0   /*!< Set IrDA Tx direction*/
+#define IrDA_RX               1   /*!< Set IrDA Rx direction*/
+
+/*  define RTS signal */
+#define UART_RTS_HIGH           1  /*!< Set RTS high*/
+#define UART_RTS_LOW            0  /*!< Set RTS low*/
+
+/* define IOCTL command of UART operation mode, interrupt or pooling mode */
+#define UART_IOC_SETTXMODE               1     /*!< Set Tx Mode */
+#define UART_IOC_SETRXMODE               2     /*!< Set Tx Mode */
+#define UART_IOC_GETRECCHARINFO          3     /*!< Get receive character */
+#define UART_IOC_SETUARTPARAMETER        4     /*!< Config UART */
+//#define UART_IOC_PERFORMBLUETOOTH      5
+#define UART_IOC_PERFORMIrDA             6     /*!< Config IrDA */
+#define UART_IOC_GETUARTREGISTERVALUE    7     /*!< Get UART register value*/
+#define UART_IOC_GETERRNO                8     /*!< Get rrror code */
+//#define UART_IOC_SETMODEMLOOPBACK      9
+//#define UART_IOC_GETDSRSTATE           10
+//#define UART_IOC_SETDTRSIGNAL          11
+#define UART_IOC_SETINTERRUPT            12    /*!< Set interrupt */
+#define UART_IOC_SETBREAKCONTROL         13    /*!< Set break */
+#define UART_IOC_GETBIISTATE             14    /*!< Get break status */
+#define UART_IOC_GETCTSSTATE             15    /*!< Get CTS status */
+#define UART_IOC_SETRTSSIGNAL            16    /*!< Set RTS signal */
+#define UART_IOC_SETMODEMINTERRUPT       17    /*!< Set modem interrupt */
+#define UART_IOC_ENABLEHWFLOWCONTROL     18    /*!< Enable H/W flow control */
+#define UART_IOC_DISABLEHWFLOWCONTROL    19    /*!< Disable H/W flow control */
+//#define UART_IOC_ENABLESWFLOWCONTROL   20    /*!< Enable S/W flow control */
+//#define UART_IOC_DISABLESWFLOWCONTROL  21    /*!< Disable S/W flow control */
+//#define UART_IOC_SETUART1FULLMODEM       22
+//#define UART_IOC_SETUART1HIGHSPEED       23
+
+#define UART_IOC_FLUSH_TX_BUFFER         24    /*!< Flush Tx buffer */
+#define UART_IOC_FLUSH_RX_BUFFER         25    /*!< Flus Rx buffer */
+
+#define UART_IOC_SET_RS485_MODE          26     /*!< Select RS485 Mode */
+#define UART_IOC_SEND_RS485_ADDRESS     27     /*!< Send RS485 Address*/
+#define UART_IOC_SET_RS485_RXOFF         28     /*!< Select RS485 Mode */
+#define UART_IOC_SET_ALTCTL_REG          29     /*!< Set ALT_CTL register */
+#define UART_IOC_GET_ALTCTL_REG          30     /*!< Get ALT_CTL register */
+
+#define UART_IOC_SET_LIN_MODE            31     /*!< Select LIN Mode */
+
+
+/*  Enable/Disable Modem interrupt */
+#define UART_ENABLE_MODEM_INT   0   /*!< Enable Modem interrupt */
+#define UART_DISABLE_MODEM_INT  1   /*!< Disable Modem interrupt */
+
+/* These error code can get from UART_IOC_GETERRNO */
+#define UART_ERR_PARITY_INVALID          -1   /*!< Parity invalid */
+#define UART_ERR_DATA_BITS_INVALID       -2   /*!< Data bits invalid */
+#define UART_ERR_STOP_BITS_INVALID       -3   /*!< Stop bit invalid */
+#define UART_ERR_TRIGGERLEVEL_INVALID    -4   /*!< Trigger level invalid */
+#define UART_ERR_CHANNEL_INVALID         -5   /*!< UART channel invalid */
+#define UART_ERR_ALLOC_MEMORY_FAIL       -6   /*!< Allocate memory error */
+//#define UART_ERR_CLOCK_SOURCE_INVALID    -7   /*!< Clock Source invalid */
+//#define UART_ERR_BAUDRATE_INVALID        -8   /*!< Baudrate invalid */
+//#define UART_ERR_CONFIGURE_BT_FAIL       -9
+#define UART_ERR_IrDA_COMMAND_INVALID    -10   /*!< IrDA mode invalid */
+#define UART_ERR_TX_BUF_NOT_ENOUGH       -11   /*!< Tx buffer not enough */
+#define UART_ERR_OPERATE_MODE_INVALID    -12   /*!< Operation mode invalid */
+#define UART_ERR_SET_BAUDRATE_FAIL       -13   /*!< Set baudrate fail */
+
+/* These are the error code actually returns to user application */
+#define UART_ERR_ID     0xFFFF1700        /*!< UART library ID */
+#define UART_ENOTTY    (1 | UART_ERR_ID)  /*!< Command not support           */
+#define UART_ENODEV    (2 | UART_ERR_ID)  /*!< Interface number out of range */
+#define UART_EIO       (3 | UART_ERR_ID)  /*!< Read/Write error              */
+
+/*@}*/ /* end of group N9H30_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_UART_EXPORTED_STRUCTS UART Exported Structs
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+/*----------------------------------------------------*/
+/* Define UART buffer structure                       */
+/*----------------------------------------------------*/
+typedef struct UART_BUFFER_STRUCT
+{
+    UINT32 volatile  uUartTxHead, uUartTxTail;
+    UINT32 volatile  uUartRxHead, uUartRxTail;
+
+    PUINT8    pucUartTxBuf;
+    PUINT8    pucUartRxBuf;
+    PVOID     pvUartVector;
+    BOOL      bIsUseUARTTxInt;
+    BOOL      bIsUseUARTRxInt;
+    BOOL      bIsUARTInitial;
+
+    PINT      pucUARTFlag;
+    PINT      pucLINFlag;
+    INT32 volatile nErrno;
+
+} UART_BUFFER_T;
+/// @endcond HIDDEN_SYMBOLS
+
+/** \brief  Structure type of UART data
+ */
+#if 0
+#define UART0       0     /*!< UART0  channel  */
+#define UART1       1     /*!< UART1  channel  */
+#define UART2       2     /*!< UART2  channel  */
+#define UART3       3     /*!< UART3  channel  */
+#define UART4       4     /*!< UART4  channel  */
+#define UART5       5     /*!< UART5  channel  */
+#define UART6       6     /*!< UART6  channel  */
+#define UART7       7     /*!< UART7  channel  */
+#define UART8       8     /*!< UART8  channel  */
+#define UART9       9     /*!< UART9  channel  */
+#define UARTA       10    /*!< UARTA  channel  */
+
+typedef struct UART_STRUCT
+{
+    UINT32      uFreq;       /*!< UART clock frequency */
+    UINT32      uBaudRate;   /*!< Baudrate */
+    UINT8       ucUartNo;    /*!< UART Port */
+    UINT8       ucDataBits;  /*!< Select Data length */
+    UINT8       ucStopBits;  /*!< Select stop bit length */
+    UINT8       ucParity;    /*!< Select Parity */
+    UINT8       ucRxTriggerLevel;  /*!< Select Rx FIFO trigger level */
+} UART_T;
+#else
+
+typedef struct
+{
+    __IO uint32_t DAT;                   /*!< [0x0000] UART Receive/Transmit Buffer Register                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] UART Interrupt Enable Register                                   */
+    __IO uint32_t FIFO;                  /*!< [0x0008] UART FIFO Control Register                                       */
+    __IO uint32_t LINE;                  /*!< [0x000c] UART Line Control Register                                       */
+    __IO uint32_t MODEM;                 /*!< [0x0010] UART Modem Control Register                                      */
+    __IO uint32_t MODEMSTS;              /*!< [0x0014] UART Modem Status Register                                       */
+    __IO uint32_t FIFOSTS;               /*!< [0x0018] UART FIFO Status Register                                        */
+    __IO uint32_t INTSTS;                /*!< [0x001c] UART Interrupt Status Register                                   */
+    __IO uint32_t TOUT;                  /*!< [0x0020] UART Time-out Register                                           */
+    __IO uint32_t BAUD;                  /*!< [0x0024] UART Baud Rate Divider Register                                  */
+    __IO uint32_t IRDA;                  /*!< [0x0028] UART IrDA Control Register                                       */
+    __IO uint32_t ALTCTL;                /*!< [0x002c] UART Alternate Control/Status Register                           */
+    __IO uint32_t FUNCSEL;               /*!< [0x0030] UART Function Select Register                                    */
+    __IO uint32_t LINCTL;                /*!< [0x0034] UART LIN Control Register                                        */
+    __IO uint32_t LINSTS;                /*!< [0x0038] UART LIN Status Register                                         */
+} UART_T;
+
+#define UART0       ((UART_T *) UART0_BA)     /*!< UART0  channel  */
+#define UART1       ((UART_T *) UART1_BA)     /*!< UART1  channel  */
+#define UART2       ((UART_T *) UART2_BA)     /*!< UART2  channel  */
+#define UART3       ((UART_T *) UART3_BA)     /*!< UART3  channel  */
+#define UART4       ((UART_T *) UART4_BA)     /*!< UART4  channel  */
+#define UART5       ((UART_T *) UART5_BA)     /*!< UART5  channel  */
+#define UART6       ((UART_T *) UART6_BA)     /*!< UART6  channel  */
+#define UART7       ((UART_T *) UART7_BA)     /*!< UART7  channel  */
+#define UART8       ((UART_T *) UART8_BA)     /*!< UART8  channel  */
+#define UART9       ((UART_T *) UART9_BA)     /*!< UART9  channel  */
+#define UARTA       ((UART_T *) UARTA_BA)     /*!< UARTA  channel  */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FUNCSEL constants definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FIFO_RFITL_Pos              (4)                                               /*!< UART_T::FIFO: RFITL Position           */
+#define UART_FIFO_RFITL_Msk              (0xful << UART_FIFO_RFITL_Pos)                    /*!< UART_T::FIFO: RFITL Mask               */
+
+#define UART_FIFO_RTSTRGLV_Pos           (16)                                              /*!< UART_T::FIFO: RTSTRGLV Position        */
+#define UART_FIFO_RTSTRGLV_Msk           (0xful << UART_FIFO_RTSTRGLV_Pos)                 /*!< UART_T::FIFO: RTSTRGLV Mask            */
+
+#define UART_FUNCSEL_FUNCSEL_Pos         (0)                                               /*!< UART_T::FUNCSEL: FUNCSEL Position      */
+#define UART_FUNCSEL_FUNCSEL_Msk         (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)               /*!< UART_T::FUNCSEL: FUNCSEL Mask          */
+
+#define UART_FUNCSEL_UART  (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function  (Default) \hideinitializer */
+#define UART_FUNCSEL_LIN   (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function             \hideinitializer */
+#define UART_FUNCSEL_IrDA  (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function            \hideinitializer */
+#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function           \hideinitializer */
+
+#endif
+
+/** \brief  Structure type of UART register
+ */
+typedef struct UART_REGISTER_STRUCT
+{
+    UINT32 uUartReg[14][2]; /*!< Store UART register value */
+} UART_REGISTER_T;
+
+/*@}*/ /* end of group N9H30_UART_EXPORTED_STRUCTS */
+
+
+/** @addtogroup N9H30_UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief   Calculate UART baudrate mode0 divider
+ *
+ *    @param[in]   u32SrcFreq      UART clock frequency
+ *    @param[in]   u32BaudRate     Baudrate of UART module
+ *
+ *    @return  UART baudrate mode0 divider
+ *  \hideinitializer
+ *
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate)    (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
+
+/**
+ *    @brief   Calculate UART baudrate mode2 divider
+ *
+ *    @param[in]   u32SrcFreq     UART clock frequency
+ *    @param[in]   u32BaudRate    Baudrate of UART module
+ *
+ *    @return  UART baudrate mode2 divider
+ * \hideinitializer
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)    (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not empty
+ *    @retval       >=1 Rx FIFO is empty
+ *
+ *    @details      This macro get Receiver FIFO empty register value.
+ *    \hideinitializer
+ */
+#define UART_GET_RX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FSR_RX_EMPTY_Msk)
+
+/**
+ *    @brief        Check TX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 TX FIFO is full
+ *    @retval       0 TX FIFO is not full
+ *
+ *    @details      This macro check TX FIFO is full or not.
+ *    \hideinitializer
+ */
+#define UART_IS_TX_FULL(uart)    (((uart)->FIFOSTS & UART_FSR_TX_FULL_Msk)>>UART_FSR_TX_FULL_Pos)
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ *    \hideinitializer
+ */
+#define UART_WRITE(uart, u8Data)    ((uart)->DAT = (u8Data))
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       The oldest data byte in RX FIFO.
+ *
+ *    @details      This macro read Rx data register.
+ *    \hideinitializer
+ */
+#define UART_READ(uart)    ((uart)->DAT)
+
+#define UART_ENABLE_INT(uart, u32eIntSel)    ((uart)->INTEN |= (u32eIntSel))
+#define UART_DISABLE_INT(uart, u32eIntSel)    ((uart)->INTEN &= ~ (u32eIntSel))
+
+/*-----------------------------------------*/
+/* interface function declarations         */
+/*-----------------------------------------*/
+INT uartOpen(PVOID param);
+INT uartInit(void);
+INT uartIoctl(INT nNum, UINT32 uCom, UINT32 uArg0, UINT32 uArg1);
+INT32 uartRelease(INT nNum);
+INT32 uartWrite(INT nNum, PUINT8 pucBuf, UINT32 uLen);
+INT32 uartRead(INT nNum, PUINT8 pucBuf, UINT32 uLen);
+
+
+void UART_Open(UART_T *uart, uint32_t u32baudrate);
+void UART_Close(UART_T *uart);
+void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits);
+/*@}*/ /* end of group N9H30_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_UART_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#endif

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_usbd.h

@@ -0,0 +1,937 @@
+/**************************************************************************//**
+ * @file     usbd.h
+ * @brief    N9H30 USBD driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_USBD_H__
+#define __NU_USBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_USBD_Driver USBD Driver
+  @{
+*/
+
+/** @addtogroup N9H30_USBD_EXPORTED_CONSTANTS USBD Exported Constants
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+#define USBD_MAX_EP     12
+
+#define Maximum(a,b)    (a)>(b) ? (a) : (b)
+#define Minimum(a,b)    (a)<(b) ? (a) : (b)
+
+
+#define CEP     0xff    /*!< Control Endpoint  \hideinitializer */
+#define EPA     0       /*!< Endpoint A  \hideinitializer */
+#define EPB     1       /*!< Endpoint B  \hideinitializer */
+#define EPC     2       /*!< Endpoint C  \hideinitializer */
+#define EPD     3       /*!< Endpoint D  \hideinitializer */
+#define EPE     4       /*!< Endpoint E  \hideinitializer */
+#define EPF     5       /*!< Endpoint F  \hideinitializer */
+#define EPG     6       /*!< Endpoint G  \hideinitializer */
+#define EPH     7       /*!< Endpoint H  \hideinitializer */
+#define EPI     8       /*!< Endpoint I  \hideinitializer */
+#define EPJ     9       /*!< Endpoint J  \hideinitializer */
+#define EPK     10      /*!< Endpoint K  \hideinitializer */
+#define EPL     11      /*!< Endpoint L  \hideinitializer */
+
+/* USB Request Type */
+#define REQ_STANDARD        0x00
+#define REQ_CLASS           0x20
+#define REQ_VENDOR          0x40
+
+/* USB Standard Request */
+#define GET_STATUS          0x00
+#define CLEAR_FEATURE       0x01
+#define SET_FEATURE         0x03
+#define SET_ADDRESS         0x05
+#define GET_DESCRIPTOR      0x06
+#define SET_DESCRIPTOR      0x07
+#define GET_CONFIGURATION   0x08
+#define SET_CONFIGURATION   0x09
+#define GET_INTERFACE       0x0A
+#define SET_INTERFACE       0x0B
+#define SYNC_FRAME          0x0C
+
+/* USB Descriptor Type */
+#define DESC_DEVICE         0x01
+#define DESC_CONFIG         0x02
+#define DESC_STRING         0x03
+#define DESC_INTERFACE      0x04
+#define DESC_ENDPOINT       0x05
+#define DESC_QUALIFIER      0x06
+#define DESC_OTHERSPEED     0x07
+#define DESC_IFPOWER        0x08
+#define DESC_OTG            0x09
+
+/* USB HID Descriptor Type */
+#define DESC_HID            0x21
+#define DESC_HID_RPT        0x22
+
+/* USB Descriptor Length */
+#define LEN_DEVICE          18
+#define LEN_QUALIFIER       10
+#define LEN_CONFIG          9
+#define LEN_INTERFACE       9
+#define LEN_ENDPOINT        7
+#define LEN_OTG             5
+#define LEN_HID             9
+
+/* USB Endpoint Type */
+#define EP_ISO              0x01
+#define EP_BULK             0x02
+#define EP_INT              0x03
+
+#define EP_INPUT            0x80
+#define EP_OUTPUT           0x00
+
+/* USB Feature Selector */
+#define FEATURE_DEVICE_REMOTE_WAKEUP    0x01
+#define FEATURE_ENDPOINT_HALT           0x00
+/// @endcond HIDDEN_SYMBOLS
+/********************* Bit definition of CEPCTL register **********************/
+#define USB_CEPCTL_NAKCLR               ((uint32_t)0x00000000)      /*!<NAK clear  \hideinitializer */
+#define USB_CEPCTL_STALL                ((uint32_t)0x00000002)      /*!<Stall  \hideinitializer */
+#define USB_CEPCTL_ZEROLEN              ((uint32_t)0x00000004)      /*!<Zero length packet  \hideinitializer */
+#define USB_CEPCTL_FLUSH                ((uint32_t)0x00000008)      /*!<CEP flush  \hideinitializer */
+
+/********************* Bit definition of EPxRSPCTL register **********************/
+#define USB_EP_RSPCTL_FLUSH             ((uint32_t)0x00000001)      /*!<Buffer Flush  \hideinitializer */
+#define USB_EP_RSPCTL_MODE_AUTO         ((uint32_t)0x00000000)      /*!<Auto-Validate Mode  \hideinitializer */
+#define USB_EP_RSPCTL_MODE_MANUAL       ((uint32_t)0x00000002)      /*!<Manual-Validate Mode  \hideinitializer */
+#define USB_EP_RSPCTL_MODE_FLY          ((uint32_t)0x00000004)      /*!<Fly Mode  \hideinitializer */
+#define USB_EP_RSPCTL_MODE_MASK         ((uint32_t)0x00000006)      /*!<Mode Mask  \hideinitializer */
+#define USB_EP_RSPCTL_TOGGLE            ((uint32_t)0x00000008)      /*!<Clear Toggle bit  \hideinitializer */
+#define USB_EP_RSPCTL_HALT              ((uint32_t)0x00000010)      /*!<Endpoint halt  \hideinitializer */
+#define USB_EP_RSPCTL_ZEROLEN           ((uint32_t)0x00000020)      /*!<Zero length packet IN  \hideinitializer */
+#define USB_EP_RSPCTL_SHORTTXEN         ((uint32_t)0x00000040)      /*!<Packet end  \hideinitializer */
+#define USB_EP_RSPCTL_DISBUF            ((uint32_t)0x00000080)      /*!<Disable buffer  \hideinitializer */
+
+/********************* Bit definition of EPxCFG register **********************/
+#define USB_EP_CFG_VALID                ((uint32_t)0x00000001)      /*!<Endpoint Valid  \hideinitializer */
+#define USB_EP_CFG_TYPE_BULK            ((uint32_t)0x00000002)      /*!<Endpoint type - bulk  \hideinitializer */
+#define USB_EP_CFG_TYPE_INT             ((uint32_t)0x00000004)      /*!<Endpoint type - interrupt  \hideinitializer */
+#define USB_EP_CFG_TYPE_ISO             ((uint32_t)0x00000006)      /*!<Endpoint type - isochronous  \hideinitializer */
+#define USB_EP_CFG_TYPE_MASK            ((uint32_t)0x00000006)      /*!<Endpoint type mask  \hideinitializer */
+#define USB_EP_CFG_DIR_OUT              ((uint32_t)0x00000000)      /*!<OUT endpoint  \hideinitializer */
+#define USB_EP_CFG_DIR_IN               ((uint32_t)0x00000008)      /*!<IN endpoint  \hideinitializer */
+
+
+/*@}*/ /* end of group N9H30_USBD_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_USBD_EXPORTED_STRUCT USBD Exported Struct
+  @{
+*/
+
+
+/** \brief  Structure type of USB Setup Packet.
+ */
+typedef struct usbd_cmd_struct
+{
+    uint8_t  bmRequestType; /*!< Request type */
+    uint8_t  bRequest;      /*!< Request */
+    uint16_t wValue;        /*!< value */
+    uint16_t wIndex;        /*!< index */
+    uint16_t wLength;       /*!< length */
+
+} S_USBD_CMD_T; /*!<USB Setup Packet Structure */
+
+
+/** \brief  Structure type of Device Descriptor
+ */
+typedef struct s_usbd_info
+{
+    uint8_t *gu8DevDesc;            /*!< Device descriptor */
+    uint8_t *gu8ConfigDesc;         /*!< Config descriptor */
+    uint8_t **gu8StringDesc;        /*!< Pointer for USB String Descriptor pointers */
+    uint8_t *gu8QualDesc;           /*!< Qualifier descriptor */
+    uint8_t *gu8OtherConfigDesc;    /*!< Other Speed Config descriptor */
+    uint8_t **gu8HidReportDesc;     /*!< Pointer for HID Report descriptor */
+    uint32_t *gu32HidReportSize;    /*!< Pointer for HID Report descriptor Size */
+
+} S_USBD_INFO_T; /*!<USB Information Structure */
+
+
+/*@}*/ /* end of group N9H30_USBD_EXPORTED_STRUCT */
+
+/// @cond HIDDEN_SYMBOLS
+extern uint32_t g_u32EpStallLock;
+extern uint8_t volatile g_usbd_Configured;
+extern uint8_t g_usbd_ShortPacket;
+extern uint8_t g_usbd_CtrlZero;
+extern uint8_t g_usbd_UsbAddr;
+extern uint8_t g_usbd_EpHalt[];
+extern uint32_t volatile g_usbd_DmaDone;
+extern uint32_t g_usbd_CtrlInSize;
+extern S_USBD_INFO_T gsInfo;
+extern S_USBD_CMD_T gUsbCmd;
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/// @cond HIDDEN_SYMBOLS
+typedef struct
+{
+
+    union
+    {
+        volatile uint32_t EPDAT;
+        volatile uint8_t  EPDAT_BYTE;
+
+    } ep;
+    volatile uint32_t EPINTSTS;
+    volatile uint32_t EPINTEN;
+    volatile const  uint32_t EPDATCNT;
+    volatile uint32_t EPRSPCTL;
+    volatile uint32_t EPMPS;
+    volatile uint32_t EPTXCNT;
+    volatile uint32_t EPCFG;
+    volatile uint32_t EPBUFSTART;
+    volatile uint32_t EPBUFEND;
+
+} USBD_EP_T;
+
+typedef struct
+{
+    volatile const  uint32_t GINTSTS;
+    uint32_t RESERVE0[1];
+    volatile uint32_t GINTEN;
+    uint32_t RESERVE1[1];
+    volatile uint32_t BUSINTSTS;
+    volatile uint32_t BUSINTEN;
+    volatile uint32_t OPER;
+    volatile const  uint32_t FRAMECNT;
+    volatile uint32_t FADDR;
+    volatile uint32_t TEST;
+    union
+    {
+        volatile uint32_t CEPDAT;
+        volatile uint8_t  CEPDAT_BYTE;
+    } cep;
+    volatile uint32_t CEPCTL;
+    volatile uint32_t CEPINTEN;
+    volatile uint32_t CEPINTSTS;
+    volatile uint32_t CEPTXCNT;
+    volatile const  uint32_t CEPRXCNT;
+    volatile const  uint32_t CEPDATCNT;
+    volatile const  uint32_t SETUP1_0;
+    volatile const  uint32_t SETUP3_2;
+    volatile const  uint32_t SETUP5_4;
+    volatile const  uint32_t SETUP7_6;
+    volatile uint32_t CEPBUFSTART;
+    volatile uint32_t CEPBUFEND;
+    volatile uint32_t DMACTL;
+    volatile uint32_t DMACNT;
+    USBD_EP_T EP[12];
+    uint32_t RESERVE2[303];
+    volatile uint32_t DMAADDR;
+    volatile uint32_t PHYCTL;
+
+} USBD_T;
+
+#define USBD   ((USBD_T *) USBD_BA)
+
+
+
+
+#define USBD_GINTSTS_USBIF_Pos           (0)                                               /*!< USBD GINTSTS: USBIF Position           */
+#define USBD_GINTSTS_USBIF_Msk           (0x1ul << USBD_GINTSTS_USBIF_Pos)                 /*!< USBD GINTSTS: USBIF Mask               */
+
+#define USBD_GINTSTS_CEPIF_Pos           (1)                                               /*!< USBD GINTSTS: CEPIF Position           */
+#define USBD_GINTSTS_CEPIF_Msk           (0x1ul << USBD_GINTSTS_CEPIF_Pos)                 /*!< USBD GINTSTS: CEPIF Mask               */
+
+#define USBD_GINTSTS_EPAIF_Pos           (2)                                               /*!< USBD GINTSTS: EPAIF Position           */
+#define USBD_GINTSTS_EPAIF_Msk           (0x1ul << USBD_GINTSTS_EPAIF_Pos)                 /*!< USBD GINTSTS: EPAIF Mask               */
+
+#define USBD_GINTSTS_EPBIF_Pos           (3)                                               /*!< USBD GINTSTS: EPBIF Position           */
+#define USBD_GINTSTS_EPBIF_Msk           (0x1ul << USBD_GINTSTS_EPBIF_Pos)                 /*!< USBD GINTSTS: EPBIF Mask               */
+
+#define USBD_GINTSTS_EPCIF_Pos           (4)                                               /*!< USBD GINTSTS: EPCIF Position           */
+#define USBD_GINTSTS_EPCIF_Msk           (0x1ul << USBD_GINTSTS_EPCIF_Pos)                 /*!< USBD GINTSTS: EPCIF Mask               */
+
+#define USBD_GINTSTS_EPDIF_Pos           (5)                                               /*!< USBD GINTSTS: EPDIF Position           */
+#define USBD_GINTSTS_EPDIF_Msk           (0x1ul << USBD_GINTSTS_EPDIF_Pos)                 /*!< USBD GINTSTS: EPDIF Mask               */
+
+#define USBD_GINTSTS_EPEIF_Pos           (6)                                               /*!< USBD GINTSTS: EPEIF Position           */
+#define USBD_GINTSTS_EPEIF_Msk           (0x1ul << USBD_GINTSTS_EPEIF_Pos)                 /*!< USBD GINTSTS: EPEIF Mask               */
+
+#define USBD_GINTSTS_EPFIF_Pos           (7)                                               /*!< USBD GINTSTS: EPFIF Position           */
+#define USBD_GINTSTS_EPFIF_Msk           (0x1ul << USBD_GINTSTS_EPFIF_Pos)                 /*!< USBD GINTSTS: EPFIF Mask               */
+
+#define USBD_GINTSTS_EPGIF_Pos           (8)                                               /*!< USBD GINTSTS: EPGIF Position           */
+#define USBD_GINTSTS_EPGIF_Msk           (0x1ul << USBD_GINTSTS_EPGIF_Pos)                 /*!< USBD GINTSTS: EPGIF Mask               */
+
+#define USBD_GINTSTS_EPHIF_Pos           (9)                                               /*!< USBD GINTSTS: EPHIF Position           */
+#define USBD_GINTSTS_EPHIF_Msk           (0x1ul << USBD_GINTSTS_EPHIF_Pos)                 /*!< USBD GINTSTS: EPHIF Mask               */
+
+#define USBD_GINTSTS_EPIIF_Pos           (10)                                              /*!< USBD GINTSTS: EPIIF Position           */
+#define USBD_GINTSTS_EPIIF_Msk           (0x1ul << USBD_GINTSTS_EPIIF_Pos)                 /*!< USBD GINTSTS: EPIIF Mask               */
+
+#define USBD_GINTSTS_EPJIF_Pos           (11)                                              /*!< USBD GINTSTS: EPJIF Position           */
+#define USBD_GINTSTS_EPJIF_Msk           (0x1ul << USBD_GINTSTS_EPJIF_Pos)                 /*!< USBD GINTSTS: EPJIF Mask               */
+
+#define USBD_GINTSTS_EPKIF_Pos           (12)                                              /*!< USBD GINTSTS: EPKIF Position           */
+#define USBD_GINTSTS_EPKIF_Msk           (0x1ul << USBD_GINTSTS_EPKIF_Pos)                 /*!< USBD GINTSTS: EPKIF Mask               */
+
+#define USBD_GINTSTS_EPLIF_Pos           (13)                                              /*!< USBD GINTSTS: EPLIF Position           */
+#define USBD_GINTSTS_EPLIF_Msk           (0x1ul << USBD_GINTSTS_EPLIF_Pos)                 /*!< USBD GINTSTS: EPLIF Mask               */
+
+#define USBD_GINTEN_USBIE_Pos            (0)                                               /*!< USBD GINTEN: USBIE Position            */
+#define USBD_GINTEN_USBIE_Msk            (0x1ul << USBD_GINTEN_USBIE_Pos)                  /*!< USBD GINTEN: USBIE Mask                */
+
+#define USBD_GINTEN_CEPIE_Pos            (1)                                               /*!< USBD GINTEN: CEPIE Position            */
+#define USBD_GINTEN_CEPIE_Msk            (0x1ul << USBD_GINTEN_CEPIE_Pos)                  /*!< USBD GINTEN: CEPIE Mask                */
+
+#define USBD_GINTEN_EPAIE_Pos            (2)                                               /*!< USBD GINTEN: EPAIE Position            */
+#define USBD_GINTEN_EPAIE_Msk            (0x1ul << USBD_GINTEN_EPAIE_Pos)                  /*!< USBD GINTEN: EPAIE Mask                */
+
+#define USBD_GINTEN_EPBIE_Pos            (3)                                               /*!< USBD GINTEN: EPBIE Position            */
+#define USBD_GINTEN_EPBIE_Msk            (0x1ul << USBD_GINTEN_EPBIE_Pos)                  /*!< USBD GINTEN: EPBIE Mask                */
+
+#define USBD_GINTEN_EPCIE_Pos            (4)                                               /*!< USBD GINTEN: EPCIE Position            */
+#define USBD_GINTEN_EPCIE_Msk            (0x1ul << USBD_GINTEN_EPCIE_Pos)                  /*!< USBD GINTEN: EPCIE Mask                */
+
+#define USBD_GINTEN_EPDIE_Pos            (5)                                               /*!< USBD GINTEN: EPDIE Position            */
+#define USBD_GINTEN_EPDIE_Msk            (0x1ul << USBD_GINTEN_EPDIE_Pos)                  /*!< USBD GINTEN: EPDIE Mask                */
+
+#define USBD_GINTEN_EPEIE_Pos            (6)                                               /*!< USBD GINTEN: EPEIE Position            */
+#define USBD_GINTEN_EPEIE_Msk            (0x1ul << USBD_GINTEN_EPEIE_Pos)                  /*!< USBD GINTEN: EPEIE Mask                */
+
+#define USBD_GINTEN_EPFIE_Pos            (7)                                               /*!< USBD GINTEN: EPFIE Position            */
+#define USBD_GINTEN_EPFIE_Msk            (0x1ul << USBD_GINTEN_EPFIE_Pos)                  /*!< USBD GINTEN: EPFIE Mask                */
+
+#define USBD_GINTEN_EPGIE_Pos            (8)                                               /*!< USBD GINTEN: EPGIE Position            */
+#define USBD_GINTEN_EPGIE_Msk            (0x1ul << USBD_GINTEN_EPGIE_Pos)                  /*!< USBD GINTEN: EPGIE Mask                */
+
+#define USBD_GINTEN_EPHIE_Pos            (9)                                               /*!< USBD GINTEN: EPHIE Position            */
+#define USBD_GINTEN_EPHIE_Msk            (0x1ul << USBD_GINTEN_EPHIE_Pos)                  /*!< USBD GINTEN: EPHIE Mask                */
+
+#define USBD_GINTEN_EPIIE_Pos            (10)                                              /*!< USBD GINTEN: EPIIE Position            */
+#define USBD_GINTEN_EPIIE_Msk            (0x1ul << USBD_GINTEN_EPIIE_Pos)                  /*!< USBD GINTEN: EPIIE Mask                */
+
+#define USBD_GINTEN_EPJIE_Pos            (11)                                              /*!< USBD GINTEN: EPJIE Position            */
+#define USBD_GINTEN_EPJIE_Msk            (0x1ul << USBD_GINTEN_EPJIE_Pos)                  /*!< USBD GINTEN: EPJIE Mask                */
+
+#define USBD_GINTEN_EPKIE_Pos            (12)                                              /*!< USBD GINTEN: EPKIE Position            */
+#define USBD_GINTEN_EPKIE_Msk            (0x1ul << USBD_GINTEN_EPKIE_Pos)                  /*!< USBD GINTEN: EPKIE Mask                */
+
+#define USBD_GINTEN_EPLIE_Pos            (13)                                              /*!< USBD GINTEN: EPLIE Position            */
+#define USBD_GINTEN_EPLIE_Msk            (0x1ul << USBD_GINTEN_EPLIE_Pos)                  /*!< USBD GINTEN: EPLIE Mask                */
+
+#define USBD_BUSINTSTS_SOFIF_Pos         (0)                                               /*!< USBD BUSINTSTS: SOFIF Position         */
+#define USBD_BUSINTSTS_SOFIF_Msk         (0x1ul << USBD_BUSINTSTS_SOFIF_Pos)               /*!< USBD BUSINTSTS: SOFIF Mask             */
+
+#define USBD_BUSINTSTS_RSTIF_Pos         (1)                                               /*!< USBD BUSINTSTS: RSTIF Position         */
+#define USBD_BUSINTSTS_RSTIF_Msk         (0x1ul << USBD_BUSINTSTS_RSTIF_Pos)               /*!< USBD BUSINTSTS: RSTIF Mask             */
+
+#define USBD_BUSINTSTS_RESUMEIF_Pos      (2)                                               /*!< USBD BUSINTSTS: RESUMEIF Position      */
+#define USBD_BUSINTSTS_RESUMEIF_Msk      (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos)            /*!< USBD BUSINTSTS: RESUMEIF Mask          */
+
+#define USBD_BUSINTSTS_SUSPENDIF_Pos     (3)                                               /*!< USBD BUSINTSTS: SUSPENDIF Position     */
+#define USBD_BUSINTSTS_SUSPENDIF_Msk     (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos)           /*!< USBD BUSINTSTS: SUSPENDIF Mask         */
+
+#define USBD_BUSINTSTS_HISPDIF_Pos       (4)                                               /*!< USBD BUSINTSTS: HISPDIF Position       */
+#define USBD_BUSINTSTS_HISPDIF_Msk       (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos)             /*!< USBD BUSINTSTS: HISPDIF Mask           */
+
+#define USBD_BUSINTSTS_DMADONEIF_Pos     (5)                                               /*!< USBD BUSINTSTS: DMADONEIF Position     */
+#define USBD_BUSINTSTS_DMADONEIF_Msk     (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos)           /*!< USBD BUSINTSTS: DMADONEIF Mask         */
+
+#define USBD_BUSINTSTS_PHYCLKVLDIF_Pos   (6)                                               /*!< USBD BUSINTSTS: PHYCLKVLDIF Position   */
+#define USBD_BUSINTSTS_PHYCLKVLDIF_Msk   (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos)         /*!< USBD BUSINTSTS: PHYCLKVLDIF Mask       */
+
+#define USBD_BUSINTSTS_VBUSDETIF_Pos     (8)                                               /*!< USBD BUSINTSTS: VBUSDETIF Position     */
+#define USBD_BUSINTSTS_VBUSDETIF_Msk     (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos)           /*!< USBD BUSINTSTS: VBUSDETIF Mask         */
+
+#define USBD_BUSINTEN_SOFIEN_Pos         (0)                                               /*!< USBD BUSINTEN: SOFIEN Position         */
+#define USBD_BUSINTEN_SOFIEN_Msk         (0x1ul << USBD_BUSINTEN_SOFIEN_Pos)               /*!< USBD BUSINTEN: SOFIEN Mask             */
+
+#define USBD_BUSINTEN_RSTIEN_Pos         (1)                                               /*!< USBD BUSINTEN: RSTIEN Position         */
+#define USBD_BUSINTEN_RSTIEN_Msk         (0x1ul << USBD_BUSINTEN_RSTIEN_Pos)               /*!< USBD BUSINTEN: RSTIEN Mask             */
+
+#define USBD_BUSINTEN_RESUMEIEN_Pos      (2)                                               /*!< USBD BUSINTEN: RESUMEIEN Position      */
+#define USBD_BUSINTEN_RESUMEIEN_Msk      (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos)            /*!< USBD BUSINTEN: RESUMEIEN Mask          */
+
+#define USBD_BUSINTEN_SUSPENDIEN_Pos     (3)                                               /*!< USBD BUSINTEN: SUSPENDIEN Position     */
+#define USBD_BUSINTEN_SUSPENDIEN_Msk     (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos)           /*!< USBD BUSINTEN: SUSPENDIEN Mask         */
+
+#define USBD_BUSINTEN_HISPDIEN_Pos       (4)                                               /*!< USBD BUSINTEN: HISPDIEN Position       */
+#define USBD_BUSINTEN_HISPDIEN_Msk       (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos)             /*!< USBD BUSINTEN: HISPDIEN Mask           */
+
+#define USBD_BUSINTEN_DMADONEIEN_Pos     (5)                                               /*!< USBD BUSINTEN: DMADONEIEN Position     */
+#define USBD_BUSINTEN_DMADONEIEN_Msk     (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos)           /*!< USBD BUSINTEN: DMADONEIEN Mask         */
+
+#define USBD_BUSINTEN_PHYCLKVLDIEN_Pos   (6)                                               /*!< USBD BUSINTEN: PHYCLKVLDIEN Position   */
+#define USBD_BUSINTEN_PHYCLKVLDIEN_Msk   (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos)         /*!< USBD BUSINTEN: PHYCLKVLDIEN Mask       */
+
+#define USBD_BUSINTEN_VBUSDETIEN_Pos     (8)                                               /*!< USBD BUSINTEN: VBUSDETIEN Position     */
+#define USBD_BUSINTEN_VBUSDETIEN_Msk     (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos)           /*!< USBD BUSINTEN: VBUSDETIEN Mask         */
+
+#define USBD_OPER_RESUMEEN_Pos           (0)                                               /*!< USBD OPER: RESUMEEN Position           */
+#define USBD_OPER_RESUMEEN_Msk           (0x1ul << USBD_OPER_RESUMEEN_Pos)                 /*!< USBD OPER: RESUMEEN Mask               */
+
+#define USBD_OPER_HISPDEN_Pos            (1)                                               /*!< USBD OPER: HISPDEN Position            */
+#define USBD_OPER_HISPDEN_Msk            (0x1ul << USBD_OPER_HISPDEN_Pos)                  /*!< USBD OPER: HISPDEN Mask                */
+
+#define USBD_OPER_CURSPD_Pos             (2)                                               /*!< USBD OPER: CURSPD Position             */
+#define USBD_OPER_CURSPD_Msk             (0x1ul << USBD_OPER_CURSPD_Pos)                   /*!< USBD OPER: CURSPD Mask                 */
+
+#define USBD_FRAMECNT_MFRAMECNT_Pos      (0)                                               /*!< USBD FRAMECNT: MFRAMECNT Position      */
+#define USBD_FRAMECNT_MFRAMECNT_Msk      (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos)            /*!< USBD FRAMECNT: MFRAMECNT Mask          */
+
+#define USBD_FRAMECNT_FRAMECNT_Pos       (3)                                               /*!< USBD FRAMECNT: FRAMECNT Position       */
+#define USBD_FRAMECNT_FRAMECNT_Msk       (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos)           /*!< USBD FRAMECNT: FRAMECNT Mask           */
+
+#define USBD_FADDR_FADDR_Pos             (0)                                               /*!< USBD FADDR: FADDR Position             */
+#define USBD_FADDR_FADDR_Msk             (0x7ful << USBD_FADDR_FADDR_Pos)                  /*!< USBD FADDR: FADDR Mask                 */
+
+#define USBD_TEST_TESTMODE_Pos           (0)                                               /*!< USBD TEST: TESTMODE Position           */
+#define USBD_TEST_TESTMODE_Msk           (0x7ul << USBD_TEST_TESTMODE_Pos)                 /*!< USBD TEST: TESTMODE Mask               */
+
+#define USBD_CEPDAT_DAT_Pos              (0)                                               /*!< USBD CEPDAT: DAT Position              */
+#define USBD_CEPDAT_DAT_Msk              (0xfffffffful << USBD_CEPDAT_DAT_Pos)             /*!< USBD CEPDAT: DAT Mask                  */
+
+#define USBD_CEPCTL_NAKCLR_Pos           (0)                                               /*!< USBD CEPCTL: NAKCLR Position           */
+#define USBD_CEPCTL_NAKCLR_Msk           (0x1ul << USBD_CEPCTL_NAKCLR_Pos)                 /*!< USBD CEPCTL: NAKCLR Mask               */
+
+#define USBD_CEPCTL_STALLEN_Pos          (1)                                               /*!< USBD CEPCTL: STALLEN Position          */
+#define USBD_CEPCTL_STALLEN_Msk          (0x1ul << USBD_CEPCTL_STALLEN_Pos)                /*!< USBD CEPCTL: STALLEN Mask              */
+
+#define USBD_CEPCTL_ZEROLEN_Pos          (2)                                               /*!< USBD CEPCTL: ZEROLEN Position          */
+#define USBD_CEPCTL_ZEROLEN_Msk          (0x1ul << USBD_CEPCTL_ZEROLEN_Pos)                /*!< USBD CEPCTL: ZEROLEN Mask              */
+
+#define USBD_CEPCTL_FLUSH_Pos            (3)                                               /*!< USBD CEPCTL: FLUSH Position            */
+#define USBD_CEPCTL_FLUSH_Msk            (0x1ul << USBD_CEPCTL_FLUSH_Pos)                  /*!< USBD CEPCTL: FLUSH Mask                */
+
+#define USBD_CEPINTEN_SETUPTKIEN_Pos     (0)                                               /*!< USBD CEPINTEN: SETUPTKIEN Position     */
+#define USBD_CEPINTEN_SETUPTKIEN_Msk     (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos)           /*!< USBD CEPINTEN: SETUPTKIEN Mask         */
+
+#define USBD_CEPINTEN_SETUPPKIEN_Pos     (1)                                               /*!< USBD CEPINTEN: SETUPPKIEN Position     */
+#define USBD_CEPINTEN_SETUPPKIEN_Msk     (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos)           /*!< USBD CEPINTEN: SETUPPKIEN Mask         */
+
+#define USBD_CEPINTEN_OUTTKIEN_Pos       (2)                                               /*!< USBD CEPINTEN: OUTTKIEN Position       */
+#define USBD_CEPINTEN_OUTTKIEN_Msk       (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos)             /*!< USBD CEPINTEN: OUTTKIEN Mask           */
+
+#define USBD_CEPINTEN_INTKIEN_Pos        (3)                                               /*!< USBD CEPINTEN: INTKIEN Position        */
+#define USBD_CEPINTEN_INTKIEN_Msk        (0x1ul << USBD_CEPINTEN_INTKIEN_Pos)              /*!< USBD CEPINTEN: INTKIEN Mask            */
+
+#define USBD_CEPINTEN_PINGIEN_Pos        (4)                                               /*!< USBD CEPINTEN: PINGIEN Position        */
+#define USBD_CEPINTEN_PINGIEN_Msk        (0x1ul << USBD_CEPINTEN_PINGIEN_Pos)              /*!< USBD CEPINTEN: PINGIEN Mask            */
+
+#define USBD_CEPINTEN_TXPKIEN_Pos        (5)                                               /*!< USBD CEPINTEN: TXPKIEN Position        */
+#define USBD_CEPINTEN_TXPKIEN_Msk        (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos)              /*!< USBD CEPINTEN: TXPKIEN Mask            */
+
+#define USBD_CEPINTEN_RXPKIEN_Pos        (6)                                               /*!< USBD CEPINTEN: RXPKIEN Position        */
+#define USBD_CEPINTEN_RXPKIEN_Msk        (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos)              /*!< USBD CEPINTEN: RXPKIEN Mask            */
+
+#define USBD_CEPINTEN_NAKIEN_Pos         (7)                                               /*!< USBD CEPINTEN: NAKIEN Position         */
+#define USBD_CEPINTEN_NAKIEN_Msk         (0x1ul << USBD_CEPINTEN_NAKIEN_Pos)               /*!< USBD CEPINTEN: NAKIEN Mask             */
+
+#define USBD_CEPINTEN_STALLIEN_Pos       (8)                                               /*!< USBD CEPINTEN: STALLIEN Position       */
+#define USBD_CEPINTEN_STALLIEN_Msk       (0x1ul << USBD_CEPINTEN_STALLIEN_Pos)             /*!< USBD CEPINTEN: STALLIEN Mask           */
+
+#define USBD_CEPINTEN_ERRIEN_Pos         (9)                                               /*!< USBD CEPINTEN: ERRIEN Position         */
+#define USBD_CEPINTEN_ERRIEN_Msk         (0x1ul << USBD_CEPINTEN_ERRIEN_Pos)               /*!< USBD CEPINTEN: ERRIEN Mask             */
+
+#define USBD_CEPINTEN_STSDONEIEN_Pos     (10)                                              /*!< USBD CEPINTEN: STSDONEIEN Position     */
+#define USBD_CEPINTEN_STSDONEIEN_Msk     (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos)           /*!< USBD CEPINTEN: STSDONEIEN Mask         */
+
+#define USBD_CEPINTEN_BUFFULLIEN_Pos     (11)                                              /*!< USBD CEPINTEN: BUFFULLIEN Position     */
+#define USBD_CEPINTEN_BUFFULLIEN_Msk     (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos)           /*!< USBD CEPINTEN: BUFFULLIEN Mask         */
+
+#define USBD_CEPINTEN_BUFEMPTYIEN_Pos    (12)                                              /*!< USBD CEPINTEN: BUFEMPTYIEN Position    */
+#define USBD_CEPINTEN_BUFEMPTYIEN_Msk    (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos)          /*!< USBD CEPINTEN: BUFEMPTYIEN Mask        */
+
+#define USBD_CEPINTSTS_SETUPTKIF_Pos     (0)                                               /*!< USBD CEPINTSTS: SETUPTKIF Position     */
+#define USBD_CEPINTSTS_SETUPTKIF_Msk     (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos)           /*!< USBD CEPINTSTS: SETUPTKIF Mask         */
+
+#define USBD_CEPINTSTS_SETUPPKIF_Pos     (1)                                               /*!< USBD CEPINTSTS: SETUPPKIF Position     */
+#define USBD_CEPINTSTS_SETUPPKIF_Msk     (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos)           /*!< USBD CEPINTSTS: SETUPPKIF Mask         */
+
+#define USBD_CEPINTSTS_OUTTKIF_Pos       (2)                                               /*!< USBD CEPINTSTS: OUTTKIF Position       */
+#define USBD_CEPINTSTS_OUTTKIF_Msk       (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos)             /*!< USBD CEPINTSTS: OUTTKIF Mask           */
+
+#define USBD_CEPINTSTS_INTKIF_Pos        (3)                                               /*!< USBD CEPINTSTS: INTKIF Position        */
+#define USBD_CEPINTSTS_INTKIF_Msk        (0x1ul << USBD_CEPINTSTS_INTKIF_Pos)              /*!< USBD CEPINTSTS: INTKIF Mask            */
+
+#define USBD_CEPINTSTS_PINGIF_Pos        (4)                                               /*!< USBD CEPINTSTS: PINGIF Position        */
+#define USBD_CEPINTSTS_PINGIF_Msk        (0x1ul << USBD_CEPINTSTS_PINGIF_Pos)              /*!< USBD CEPINTSTS: PINGIF Mask            */
+
+#define USBD_CEPINTSTS_TXPKIF_Pos        (5)                                               /*!< USBD CEPINTSTS: TXPKIF Position        */
+#define USBD_CEPINTSTS_TXPKIF_Msk        (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos)              /*!< USBD CEPINTSTS: TXPKIF Mask            */
+
+#define USBD_CEPINTSTS_RXPKIF_Pos        (6)                                               /*!< USBD CEPINTSTS: RXPKIF Position        */
+#define USBD_CEPINTSTS_RXPKIF_Msk        (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos)              /*!< USBD CEPINTSTS: RXPKIF Mask            */
+
+#define USBD_CEPINTSTS_NAKIF_Pos         (7)                                               /*!< USBD CEPINTSTS: NAKIF Position         */
+#define USBD_CEPINTSTS_NAKIF_Msk         (0x1ul << USBD_CEPINTSTS_NAKIF_Pos)               /*!< USBD CEPINTSTS: NAKIF Mask             */
+
+#define USBD_CEPINTSTS_STALLIF_Pos       (8)                                               /*!< USBD CEPINTSTS: STALLIF Position       */
+#define USBD_CEPINTSTS_STALLIF_Msk       (0x1ul << USBD_CEPINTSTS_STALLIF_Pos)             /*!< USBD CEPINTSTS: STALLIF Mask           */
+
+#define USBD_CEPINTSTS_ERRIF_Pos         (9)                                               /*!< USBD CEPINTSTS: ERRIF Position         */
+#define USBD_CEPINTSTS_ERRIF_Msk         (0x1ul << USBD_CEPINTSTS_ERRIF_Pos)               /*!< USBD CEPINTSTS: ERRIF Mask             */
+
+#define USBD_CEPINTSTS_STSDONEIF_Pos     (10)                                              /*!< USBD CEPINTSTS: STSDONEIF Position     */
+#define USBD_CEPINTSTS_STSDONEIF_Msk     (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos)           /*!< USBD CEPINTSTS: STSDONEIF Mask         */
+
+#define USBD_CEPINTSTS_BUFFULLIF_Pos     (11)                                              /*!< USBD CEPINTSTS: BUFFULLIF Position     */
+#define USBD_CEPINTSTS_BUFFULLIF_Msk     (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos)           /*!< USBD CEPINTSTS: BUFFULLIF Mask         */
+
+#define USBD_CEPINTSTS_BUFEMPTYIF_Pos    (12)                                              /*!< USBD CEPINTSTS: BUFEMPTYIF Position    */
+#define USBD_CEPINTSTS_BUFEMPTYIF_Msk    (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos)          /*!< USBD CEPINTSTS: BUFEMPTYIF Mask        */
+
+#define USBD_CEPTXCNT_TXCNT_Pos          (0)                                               /*!< USBD CEPTXCNT: TXCNT Position          */
+#define USBD_CEPTXCNT_TXCNT_Msk          (0xfful << USBD_CEPTXCNT_TXCNT_Pos)               /*!< USBD CEPTXCNT: TXCNT Mask              */
+
+#define USBD_CEPRXCNT_RXCNT_Pos          (0)                                               /*!< USBD CEPRXCNT: RXCNT Position          */
+#define USBD_CEPRXCNT_RXCNT_Msk          (0xfful << USBD_CEPRXCNT_RXCNT_Pos)               /*!< USBD CEPRXCNT: RXCNT Mask              */
+
+#define USBD_CEPDATCNT_DATCNT_Pos        (0)                                               /*!< USBD CEPDATCNT: DATCNT Position        */
+#define USBD_CEPDATCNT_DATCNT_Msk        (0xfffful << USBD_CEPDATCNT_DATCNT_Pos)           /*!< USBD CEPDATCNT: DATCNT Mask            */
+
+#define USBD_SETUP1_0_SETUP0_Pos         (0)                                               /*!< USBD SETUP1_0: SETUP0 Position         */
+#define USBD_SETUP1_0_SETUP0_Msk         (0xfful << USBD_SETUP1_0_SETUP0_Pos)              /*!< USBD SETUP1_0: SETUP0 Mask             */
+
+#define USBD_SETUP1_0_SETUP1_Pos         (8)                                               /*!< USBD SETUP1_0: SETUP1 Position         */
+#define USBD_SETUP1_0_SETUP1_Msk         (0xfful << USBD_SETUP1_0_SETUP1_Pos)              /*!< USBD SETUP1_0: SETUP1 Mask             */
+
+#define USBD_SETUP3_2_SETUP2_Pos         (0)                                               /*!< USBD SETUP3_2: SETUP2 Position         */
+#define USBD_SETUP3_2_SETUP2_Msk         (0xfful << USBD_SETUP3_2_SETUP2_Pos)              /*!< USBD SETUP3_2: SETUP2 Mask             */
+
+#define USBD_SETUP3_2_SETUP3_Pos         (8)                                               /*!< USBD SETUP3_2: SETUP3 Position         */
+#define USBD_SETUP3_2_SETUP3_Msk         (0xfful << USBD_SETUP3_2_SETUP3_Pos)              /*!< USBD SETUP3_2: SETUP3 Mask             */
+
+#define USBD_SETUP5_4_SETUP4_Pos         (0)                                               /*!< USBD SETUP5_4: SETUP4 Position         */
+#define USBD_SETUP5_4_SETUP4_Msk         (0xfful << USBD_SETUP5_4_SETUP4_Pos)              /*!< USBD SETUP5_4: SETUP4 Mask             */
+
+#define USBD_SETUP5_4_SETUP5_Pos         (8)                                               /*!< USBD SETUP5_4: SETUP5 Position         */
+#define USBD_SETUP5_4_SETUP5_Msk         (0xfful << USBD_SETUP5_4_SETUP5_Pos)              /*!< USBD SETUP5_4: SETUP5 Mask             */
+
+#define USBD_SETUP7_6_SETUP6_Pos         (0)                                               /*!< USBD SETUP7_6: SETUP6 Position         */
+#define USBD_SETUP7_6_SETUP6_Msk         (0xfful << USBD_SETUP7_6_SETUP6_Pos)              /*!< USBD SETUP7_6: SETUP6 Mask             */
+
+#define USBD_SETUP7_6_SETUP7_Pos         (8)                                               /*!< USBD SETUP7_6: SETUP7 Position         */
+#define USBD_SETUP7_6_SETUP7_Msk         (0xfful << USBD_SETUP7_6_SETUP7_Pos)              /*!< USBD SETUP7_6: SETUP7 Mask             */
+
+#define USBD_CEPBUFSTART_SADDR_Pos       (0)                                               /*!< USBD CEPBUFSTART: SADDR Position       */
+#define USBD_CEPBUFSTART_SADDR_Msk       (0xffful << USBD_CEPBUFSTART_SADDR_Pos)           /*!< USBD CEPBUFSTART: SADDR Mask           */
+
+#define USBD_CEPBUFEND_EADDR_Pos         (0)                                               /*!< USBD CEPBUFEND: EADDR Position         */
+#define USBD_CEPBUFEND_EADDR_Msk         (0xffful << USBD_CEPBUFEND_EADDR_Pos)             /*!< USBD CEPBUFEND: EADDR Mask             */
+
+#define USBD_DMACTL_EPNUM_Pos            (0)                                               /*!< USBD DMACTL: EPNUM Position            */
+#define USBD_DMACTL_EPNUM_Msk            (0xful << USBD_DMACTL_EPNUM_Pos)                  /*!< USBD DMACTL: EPNUM Mask                */
+
+#define USBD_DMACTL_DMARD_Pos            (4)                                               /*!< USBD DMACTL: DMARD Position            */
+#define USBD_DMACTL_DMARD_Msk            (0x1ul << USBD_DMACTL_DMARD_Pos)                  /*!< USBD DMACTL: DMARD Mask                */
+
+#define USBD_DMACTL_DMAEN_Pos            (5)                                               /*!< USBD DMACTL: DMAEN Position            */
+#define USBD_DMACTL_DMAEN_Msk            (0x1ul << USBD_DMACTL_DMAEN_Pos)                  /*!< USBD DMACTL: DMAEN Mask                */
+
+#define USBD_DMACTL_SGEN_Pos             (6)                                               /*!< USBD DMACTL: SGEN Position             */
+#define USBD_DMACTL_SGEN_Msk             (0x1ul << USBD_DMACTL_SGEN_Pos)                   /*!< USBD DMACTL: SGEN Mask                 */
+
+#define USBD_DMACTL_DMARST_Pos           (7)                                               /*!< USBD DMACTL: DMARST Position           */
+#define USBD_DMACTL_DMARST_Msk           (0x1ul << USBD_DMACTL_DMARST_Pos)                 /*!< USBD DMACTL: DMARST Mask               */
+
+#define USBD_DMACNT_DMACNT_Pos           (0)                                               /*!< USBD DMACNT: DMACNT Position           */
+#define USBD_DMACNT_DMACNT_Msk           (0xffffful << USBD_DMACNT_DMACNT_Pos)             /*!< USBD DMACNT: DMACNT Mask               */
+
+#define USBD_EPDAT_EPDAT_Pos             (0)                                               /*!< USBD EPDAT: EPDAT Position            */
+#define USBD_EPDAT_EPDAT_Msk             (0xfffffffful << USBD_EPDAT_EPDAT_Pos)            /*!< USBD EPDAT: EPDAT Mask                */
+
+#define USBD_EPINTSTS_BUFFULLIF_Pos      (0)                                               /*!< USBD EPINTSTS: BUFFULLIF Position     */
+#define USBD_EPINTSTS_BUFFULLIF_Msk      (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos)            /*!< USBD EPINTSTS: BUFFULLIF Mask         */
+
+#define USBD_EPINTSTS_BUFEMPTYIF_Pos     (1)                                               /*!< USBD EPINTSTS: BUFEMPTYIF Position    */
+#define USBD_EPINTSTS_BUFEMPTYIF_Msk     (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos)           /*!< USBD EPINTSTS: BUFEMPTYIF Mask        */
+
+#define USBD_EPINTSTS_SHORTTXIF_Pos      (2)                                               /*!< USBD EPINTSTS: SHORTTXIF Position     */
+#define USBD_EPINTSTS_SHORTTXIF_Msk      (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos)            /*!< USBD EPINTSTS: SHORTTXIF Mask         */
+
+#define USBD_EPINTSTS_TXPKIF_Pos         (3)                                               /*!< USBD EPINTSTS: TXPKIF Position        */
+#define USBD_EPINTSTS_TXPKIF_Msk         (0x1ul << USBD_EPINTSTS_TXPKIF_Pos)               /*!< USBD EPINTSTS: TXPKIF Mask            */
+
+#define USBD_EPINTSTS_RXPKIF_Pos         (4)                                               /*!< USBD EPINTSTS: RXPKIF Position        */
+#define USBD_EPINTSTS_RXPKIF_Msk         (0x1ul << USBD_EPINTSTS_RXPKIF_Pos)               /*!< USBD EPINTSTS: RXPKIF Mask            */
+
+#define USBD_EPINTSTS_OUTTKIF_Pos        (5)                                               /*!< USBD EPINTSTS: OUTTKIF Position       */
+#define USBD_EPINTSTS_OUTTKIF_Msk        (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos)              /*!< USBD EPINTSTS: OUTTKIF Mask           */
+
+#define USBD_EPINTSTS_INTKIF_Pos         (6)                                               /*!< USBD EPINTSTS: INTKIF Position        */
+#define USBD_EPINTSTS_INTKIF_Msk         (0x1ul << USBD_EPINTSTS_INTKIF_Pos)               /*!< USBD EPINTSTS: INTKIF Mask            */
+
+#define USBD_EPINTSTS_PINGIF_Pos         (7)                                               /*!< USBD EPINTSTS: PINGIF Position        */
+#define USBD_EPINTSTS_PINGIF_Msk         (0x1ul << USBD_EPINTSTS_PINGIF_Pos)               /*!< USBD EPINTSTS: PINGIF Mask            */
+
+#define USBD_EPINTSTS_NAKIF_Pos          (8)                                               /*!< USBD EPINTSTS: NAKIF Position         */
+#define USBD_EPINTSTS_NAKIF_Msk          (0x1ul << USBD_EPINTSTS_NAKIF_Pos)                /*!< USBD EPINTSTS: NAKIF Mask             */
+
+#define USBD_EPINTSTS_STALLIF_Pos        (9)                                               /*!< USBD EPINTSTS: STALLIF Position       */
+#define USBD_EPINTSTS_STALLIF_Msk        (0x1ul << USBD_EPINTSTS_STALLIF_Pos)              /*!< USBD EPINTSTS: STALLIF Mask           */
+
+#define USBD_EPINTSTS_NYETIF_Pos         (10)                                              /*!< USBD EPINTSTS: NYETIF Position        */
+#define USBD_EPINTSTS_NYETIF_Msk         (0x1ul << USBD_EPINTSTS_NYETIF_Pos)               /*!< USBD EPINTSTS: NYETIF Mask            */
+
+#define USBD_EPINTSTS_ERRIF_Pos          (11)                                              /*!< USBD EPINTSTS: ERRIF Position         */
+#define USBD_EPINTSTS_ERRIF_Msk          (0x1ul << USBD_EPINTSTS_ERRIF_Pos)                /*!< USBD EPINTSTS: ERRIF Mask             */
+
+#define USBD_EPINTSTS_SHORTRXIF_Pos      (12)                                              /*!< USBD EPINTSTS: SHORTRXIF Position     */
+#define USBD_EPINTSTS_SHORTRXIF_Msk      (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos)            /*!< USBD EPINTSTS: SHORTRXIF Mask         */
+
+#define USBD_EPINTEN_BUFFULLIEN_Pos      (0)                                               /*!< USBD EPINTEN: BUFFULLIEN Position     */
+#define USBD_EPINTEN_BUFFULLIEN_Msk      (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos)            /*!< USBD EPINTEN: BUFFULLIEN Mask         */
+
+#define USBD_EPINTEN_BUFEMPTYIEN_Pos     (1)                                               /*!< USBD EPINTEN: BUFEMPTYIEN Position    */
+#define USBD_EPINTEN_BUFEMPTYIEN_Msk     (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos)           /*!< USBD EPINTEN: BUFEMPTYIEN Mask        */
+
+#define USBD_EPINTEN_SHORTTXIEN_Pos      (2)                                               /*!< USBD EPINTEN: SHORTTXIEN Position     */
+#define USBD_EPINTEN_SHORTTXIEN_Msk      (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos)            /*!< USBD EPINTEN: SHORTTXIEN Mask         */
+
+#define USBD_EPINTEN_TXPKIEN_Pos         (3)                                               /*!< USBD EPINTEN: TXPKIEN Position        */
+#define USBD_EPINTEN_TXPKIEN_Msk         (0x1ul << USBD_EPINTEN_TXPKIEN_Pos)               /*!< USBD EPINTEN: TXPKIEN Mask            */
+
+#define USBD_EPINTEN_RXPKIEN_Pos         (4)                                               /*!< USBD EPINTEN: RXPKIEN Position        */
+#define USBD_EPINTEN_RXPKIEN_Msk         (0x1ul << USBD_EPINTEN_RXPKIEN_Pos)               /*!< USBD EPINTEN: RXPKIEN Mask            */
+
+#define USBD_EPINTEN_OUTTKIEN_Pos        (5)                                               /*!< USBD EPINTEN: OUTTKIEN Position       */
+#define USBD_EPINTEN_OUTTKIEN_Msk        (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos)              /*!< USBD EPINTEN: OUTTKIEN Mask           */
+
+#define USBD_EPINTEN_INTKIEN_Pos         (6)                                               /*!< USBD EPINTEN: INTKIEN Position        */
+#define USBD_EPINTEN_INTKIEN_Msk         (0x1ul << USBD_EPINTEN_INTKIEN_Pos)               /*!< USBD EPINTEN: INTKIEN Mask            */
+
+#define USBD_EPINTEN_PINGIEN_Pos         (7)                                               /*!< USBD EPINTEN: PINGIEN Position        */
+#define USBD_EPINTEN_PINGIEN_Msk         (0x1ul << USBD_EPINTEN_PINGIEN_Pos)               /*!< USBD EPINTEN: PINGIEN Mask            */
+
+#define USBD_EPINTEN_NAKIEN_Pos          (8)                                               /*!< USBD EPINTEN: NAKIEN Position         */
+#define USBD_EPINTEN_NAKIEN_Msk          (0x1ul << USBD_EPINTEN_NAKIEN_Pos)                /*!< USBD EPINTEN: NAKIEN Mask             */
+
+#define USBD_EPINTEN_STALLIEN_Pos        (9)                                               /*!< USBD EPINTEN: STALLIEN Position       */
+#define USBD_EPINTEN_STALLIEN_Msk        (0x1ul << USBD_EPINTEN_STALLIEN_Pos)              /*!< USBD EPINTEN: STALLIEN Mask           */
+
+#define USBD_EPINTEN_NYETIEN_Pos         (10)                                              /*!< USBD EPINTEN: NYETIEN Position        */
+#define USBD_EPINTEN_NYETIEN_Msk         (0x1ul << USBD_EPINTEN_NYETIEN_Pos)               /*!< USBD EPINTEN: NYETIEN Mask            */
+
+#define USBD_EPINTEN_ERRIEN_Pos          (11)                                              /*!< USBD EPINTEN: ERRIEN Position         */
+#define USBD_EPINTEN_ERRIEN_Msk          (0x1ul << USBD_EPINTEN_ERRIEN_Pos)                /*!< USBD EPINTEN: ERRIEN Mask             */
+
+#define USBD_EPINTEN_SHORTRXIEN_Pos      (12)                                              /*!< USBD EPINTEN: SHORTRXIEN Position     */
+#define USBD_EPINTEN_SHORTRXIEN_Msk      (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos)            /*!< USBD EPINTEN: SHORTRXIEN Mask         */
+
+#define USBD_EPDATCNT_DATCNT_Pos         (0)                                               /*!< USBD EPDATCNT: DATCNT Position        */
+#define USBD_EPDATCNT_DATCNT_Msk         (0xfffful << USBD_EPDATCNT_DATCNT_Pos)            /*!< USBD EPDATCNT: DATCNT Mask            */
+
+#define USBD_EPDATCNT_DMALOOP_Pos        (16)                                              /*!< USBD EPDATCNT: DMALOOP Position       */
+#define USBD_EPDATCNT_DMALOOP_Msk        (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos)           /*!< USBD EPDATCNT: DMALOOP Mask           */
+
+#define USBD_EPRSPCTL_FLUSH_Pos          (0)                                               /*!< USBD EPRSPCTL: FLUSH Position         */
+#define USBD_EPRSPCTL_FLUSH_Msk          (0x1ul << USBD_EPRSPCTL_FLUSH_Pos)                /*!< USBD EPRSPCTL: FLUSH Mask             */
+
+#define USBD_EPRSPCTL_MODE_Pos           (1)                                               /*!< USBD EPRSPCTL: MODE Position          */
+#define USBD_EPRSPCTL_MODE_Msk           (0x3ul << USBD_EPRSPCTL_MODE_Pos)                 /*!< USBD EPRSPCTL: MODE Mask              */
+
+#define USBD_EPRSPCTL_TOGGLE_Pos         (3)                                               /*!< USBD EPRSPCTL: TOGGLE Position        */
+#define USBD_EPRSPCTL_TOGGLE_Msk         (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos)               /*!< USBD EPRSPCTL: TOGGLE Mask            */
+
+#define USBD_EPRSPCTL_HALT_Pos           (4)                                               /*!< USBD EPRSPCTL: HALT Position          */
+#define USBD_EPRSPCTL_HALT_Msk           (0x1ul << USBD_EPRSPCTL_HALT_Pos)                 /*!< USBD EPRSPCTL: HALT Mask              */
+
+#define USBD_EPRSPCTL_ZEROLEN_Pos        (5)                                               /*!< USBD EPRSPCTL: ZEROLEN Position       */
+#define USBD_EPRSPCTL_ZEROLEN_Msk        (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos)              /*!< USBD EPRSPCTL: ZEROLEN Mask           */
+
+#define USBD_EPRSPCTL_SHORTTXEN_Pos      (6)                                               /*!< USBD EPRSPCTL: SHORTTXEN Position     */
+#define USBD_EPRSPCTL_SHORTTXEN_Msk      (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos)            /*!< USBD EPRSPCTL: SHORTTXEN Mask         */
+
+#define USBD_EPRSPCTL_DISBUF_Pos         (7)                                               /*!< USBD EPRSPCTL: DISBUF Position        */
+#define USBD_EPRSPCTL_DISBUF_Msk         (0x1ul << USBD_EPRSPCTL_DISBUF_Pos)               /*!< USBD EPRSPCTL: DISBUF Mask            */
+
+#define USBD_EPMPS_EPMPS_Pos             (0)                                               /*!< USBD EPMPS: EPMPS Position            */
+#define USBD_EPMPS_EPMPS_Msk             (0x7fful << USBD_EPMPS_EPMPS_Pos)                 /*!< USBD EPMPS: EPMPS Mask                */
+
+#define USBD_EPTXCNT_TXCNT_Pos           (0)                                               /*!< USBD EPTXCNT: TXCNT Position          */
+#define USBD_EPTXCNT_TXCNT_Msk           (0x7fful << USBD_EPTXCNT_TXCNT_Pos)               /*!< USBD EPTXCNT: TXCNT Mask              */
+
+#define USBD_EPCFG_EPEN_Pos              (0)                                               /*!< USBD EPCFG: EPEN Position             */
+#define USBD_EPCFG_EPEN_Msk              (0x1ul << USBD_EPCFG_EPEN_Pos)                    /*!< USBD EPCFG: EPEN Mask                 */
+
+#define USBD_EPCFG_EPTYPE_Pos            (1)                                               /*!< USBD EPCFG: EPTYPE Position           */
+#define USBD_EPCFG_EPTYPE_Msk            (0x3ul << USBD_EPCFG_EPTYPE_Pos)                  /*!< USBD EPCFG: EPTYPE Mask               */
+
+#define USBD_EPCFG_EPDIR_Pos             (3)                                               /*!< USBD EPCFG: EPDIR Position            */
+#define USBD_EPCFG_EPDIR_Msk             (0x1ul << USBD_EPCFG_EPDIR_Pos)                   /*!< USBD EPCFG: EPDIR Mask                */
+
+#define USBD_EPCFG_EPNUM_Pos             (4)                                               /*!< USBD EPCFG: EPNUM Position            */
+#define USBD_EPCFG_EPNUM_Msk             (0xful << USBD_EPCFG_EPNUM_Pos)                   /*!< USBD EPCFG: EPNUM Mask                */
+
+#define USBD_EPBUFSTART_SADDR_Pos        (0)                                               /*!< USBD EPBUFSTART: SADDR Position       */
+#define USBD_EPBUFSTART_SADDR_Msk        (0xffful << USBD_EPBUFSTART_SADDR_Pos)            /*!< USBD EPBUFSTART: SADDR Mask           */
+
+#define USBD_EPBUFEND_EADDR_Pos          (0)                                               /*!< USBD EPBUFEND: EADDR Position         */
+#define USBD_EPBUFEND_EADDR_Msk          (0xffful << USBD_EPBUFEND_EADDR_Pos)              /*!< USBD EPBUFEND: EADDR Mask             */
+
+#define USBD_DMAADDR_DMAADDR_Pos         (0)                                               /*!< USBD DMAADDR: DMAADDR Position         */
+#define USBD_DMAADDR_DMAADDR_Msk         (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos)        /*!< USBD DMAADDR: DMAADDR Mask             */
+
+#define USBD_PHYCTL_DPPUEN_Pos           (8)                                               /*!< USBD PHYCTL: DPPUEN Position           */
+#define USBD_PHYCTL_DPPUEN_Msk           (0x1ul << USBD_PHYCTL_DPPUEN_Pos)                 /*!< USBD PHYCTL: DPPUEN Mask               */
+
+#define USBD_PHYCTL_PHYEN_Pos            (9)                                               /*!< USBD PHYCTL: PHYEN Position            */
+#define USBD_PHYCTL_PHYEN_Msk            (0x1ul << USBD_PHYCTL_PHYEN_Pos)                  /*!< USBD PHYCTL: PHYEN Mask                */
+
+#define USBD_PHYCTL_WKEN_Pos             (24)                                              /*!< USBD PHYCTL: WKEN Position             */
+#define USBD_PHYCTL_WKEN_Msk             (0x1ul << USBD_PHYCTL_WKEN_Pos)                   /*!< USBD PHYCTL: WKEN Mask                 */
+
+#define USBD_PHYCTL_VBUSDET_Pos          (31)                                              /*!< USBD PHYCTL: VBUSDET Position          */
+#define USBD_PHYCTL_VBUSDET_Msk          (0x1ul << USBD_PHYCTL_VBUSDET_Pos)                /*!< USBD PHYCTL: VBUSDET Mask              */
+/// @endcond
+/** @addtogroup N9H30_USBD_EXPORTED_MACROS USBD Exported Macros
+  @{
+*/
+
+#define USBD_ENABLE_USB()               ((uint32_t)(USBD->PHYCTL |= (USBD_PHYCTL_PHYEN_Msk|USBD_PHYCTL_DPPUEN_Msk))) /*!<Enable USB  \hideinitializer */
+#define USBD_DISABLE_USB()              ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable USB  \hideinitializer */
+#define USBD_ENABLE_PHY()               ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_PHYEN_Msk)) /*!<Enable PHY  \hideinitializer */
+#define USBD_DISABLE_PHY()              ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_PHYEN_Msk)) /*!<Disable PHY  \hideinitializer */
+#define USBD_SET_SE0()                  ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Enable SE0, Force USB PHY Transceiver to Drive SE0  \hideinitializer */
+#define USBD_CLR_SE0()                  ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable SE0  \hideinitializer */
+#define USBD_SET_ADDR(addr)             (USBD->FADDR = (addr)) /*!<Set USB address  \hideinitializer */
+#define USBD_GET_ADDR()                 ((uint32_t)(USBD->FADDR)) /*!<Get USB address  \hideinitializer */
+#define USBD_ENABLE_USB_INT(intr)       (USBD->GINTEN = (intr)) /*!<Enable USB Interrupt  \hideinitializer */
+#define USBD_ENABLE_BUS_INT(intr)       (USBD->BUSINTEN = (intr)) /*!<Enable BUS Interrupt  \hideinitializer */
+#define USBD_GET_BUS_INT_FLAG()         (USBD->BUSINTSTS)        /*!<Clear Bus interrupt flag  \hideinitializer */
+#define USBD_CLR_BUS_INT_FLAG(flag)     (USBD->BUSINTSTS = flag) /*!<Clear Bus interrupt flag  \hideinitializer */
+#define USBD_ENABLE_CEP_INT(intr)       (USBD->CEPINTEN = (intr)) /*!<Enable CEP Interrupt  \hideinitializer */
+#define USBD_CLR_CEP_INT_FLAG(flag)     (USBD->CEPINTSTS = flag) /*!<Clear CEP interrupt flag  \hideinitializer */
+#define USBD_SET_CEP_STATE(flag)        (USBD->CEPCTL = flag) /*!<Set CEP state  \hideinitializer */
+#define USBD_START_CEP_IN(size)         (USBD->CEPTXCNT = size) /*!<Start CEP IN Transfer  \hideinitializer */
+#define USBD_SET_MAX_PAYLOAD(ep, size)  (USBD->EP[ep].EPMPS = (size)) /*!<Set EPx Maximum Packet Size  \hideinitializer */
+#define USBD_ENABLE_EP_INT(ep, intr)    (USBD->EP[ep].EPINTEN = (intr)) /*!<Enable EPx Interrupt  \hideinitializer */
+#define USBD_GET_EP_INT_FLAG(ep)        (USBD->EP[ep].EPINTSTS) /*!<Get EPx interrupt flag  \hideinitializer */
+#define USBD_CLR_EP_INT_FLAG(ep, flag)  (USBD->EP[ep].EPINTSTS = (flag)) /*!<Clear EPx interrupt flag  \hideinitializer */
+#define USBD_SET_DMA_LEN(len)           (USBD->DMACNT = len) /*!<Set DMA transfer length  \hideinitializer */
+#define USBD_SET_DMA_ADDR(addr)         (USBD->DMAADDR = addr) /*!<Set DMA transfer address  \hideinitializer */
+#define USBD_SET_DMA_READ(epnum)        (USBD->DMACTL = (USBD->DMACTL & ~USBD_DMACTL_EPNUM_Msk) | USBD_DMACTL_DMARD_Msk | epnum) /*!<Set DMA transfer type to read \hideinitializer */
+#define USBD_SET_DMA_WRITE(epnum)       (USBD->DMACTL = (USBD->DMACTL & ~(USBD_DMACTL_EPNUM_Msk | USBD_DMACTL_DMARD_Msk)) | epnum) /*!<Set DMA transfer type to write \hideinitializer */
+#define USBD_ENABLE_DMA()               (USBD->DMACTL |= USBD_DMACTL_DMAEN_Msk) /*!<Enable DMA transfer  \hideinitializer */
+#define USBD_IS_ATTACHED()              ((uint32_t)(USBD->PHYCTL & USBD_PHYCTL_VBUSDET_Msk)) /*!<Check cable connect state  \hideinitializer */
+
+/*@}*/ /* end of group N9H30_USBD_EXPORTED_MACROS */
+
+/** @addtogroup N9H30_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+/**
+  * @brief  USBD_memcpy, Copy bytes hardware limitation
+  * @param[in]  u8Dst   Destination pointer.
+  * @param[in]  u8Src   Source pointer.
+  * @param[in]  i32Size Copy size.
+  * @retval None.
+  */
+static __inline void USBD_MemCopy(uint8_t *u8Dst, uint8_t *u8Src, int32_t i32Size)
+{
+    while (i32Size--) *u8Dst++ = *u8Src++;
+}
+
+/**
+  * @brief  USBD_ResetDMA
+  * @param  None
+  * @retval None.
+  */
+static __inline void USBD_ResetDMA(void)
+{
+    USBD->DMACNT = 0;
+    USBD->DMACTL = 0x80;
+    USBD->DMACTL = 0x00;
+}
+/**
+  * @brief  USBD_SetEpBufAddr, Set Endpoint buffer address
+  * @param[in]  u32Ep      Endpoint Number
+  * @param[in]  u32Base    Buffer Start Address
+  * @param[in]  u32Len     Buffer length
+  * @retval None.
+  */
+static __inline void USBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len)
+{
+    if (u32Ep == CEP)
+    {
+        USBD->CEPBUFSTART = u32Base;
+        USBD->CEPBUFEND   = u32Base + u32Len - 1;
+    }
+    else
+    {
+        USBD->EP[u32Ep].EPBUFSTART = u32Base;
+        USBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1;
+    }
+}
+
+/**
+  * @brief  USBD_ConfigEp, Config Endpoint
+  * @param[in]  u32Ep      USB endpoint
+  * @param[in]  u32EpNum   Endpoint number
+  * @param[in]  u32EpType  Endpoint type
+  * @param[in]  u32EpDir   Endpoint direction
+  * @retval None.
+  */
+static __inline void USBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir)
+{
+    if (u32EpType == USB_EP_CFG_TYPE_BULK)
+        USBD->EP[u32Ep].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_AUTO);
+    else if (u32EpType == USB_EP_CFG_TYPE_INT)
+        USBD->EP[u32Ep].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_MANUAL);
+    else if (u32EpType == USB_EP_CFG_TYPE_ISO)
+        USBD->EP[u32Ep].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_FLY);
+
+    USBD->EP[u32Ep].EPCFG = (u32EpType | u32EpDir | USB_EP_CFG_VALID | (u32EpNum << 4));
+}
+
+/**
+  * @brief       Set USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @return      None
+  * @details     Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+  */
+static __inline void USBD_SetEpStall(uint32_t u32Ep)
+{
+    if (u32Ep == CEP)
+        USBD_SET_CEP_STATE(USB_CEPCTL_STALL);
+    else
+    {
+        USBD->EP[u32Ep].EPRSPCTL = USBD->EP[u32Ep].EPRSPCTL & 0xf7 | USB_EP_RSPCTL_HALT;
+    }
+}
+
+/**
+ * @brief       Set USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @return      None
+ *
+ * @details     Set USB endpoint stall state, endpoint will return STALL token.
+ */
+static __inline void USBD_SetStall(uint32_t u32EpNum)
+{
+    int i;
+
+    if (u32EpNum == 0)
+        USBD_SET_CEP_STATE(USB_CEPCTL_STALL);
+    else
+    {
+        for (i = 0; i < USBD_MAX_EP; i++)
+        {
+            if (((USBD->EP[i].EPCFG & 0xf0) >> 4) == u32EpNum)
+            {
+                USBD->EP[i].EPRSPCTL = USBD->EP[i].EPRSPCTL & 0xf7 | USB_EP_RSPCTL_HALT;
+            }
+        }
+    }
+}
+
+/**
+  * @brief       Clear USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @return      None
+  * @details     Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+  */
+static __inline void  USBD_ClearEpStall(uint32_t u32Ep)
+{
+    USBD->EP[u32Ep].EPRSPCTL = USB_EP_RSPCTL_TOGGLE;
+}
+
+/**
+ * @brief       Clear USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @return      None
+ *
+ * @details     Clear USB endpoint stall state, endpoint will return ACK/NAK token.
+ */
+static __inline void USBD_ClearStall(uint32_t u32EpNum)
+{
+    int i;
+
+    for (i = 0; i < USBD_MAX_EP; i++)
+    {
+        if (((USBD->EP[i].EPCFG & 0xf0) >> 4) == u32EpNum)
+        {
+            USBD->EP[i].EPRSPCTL = USB_EP_RSPCTL_TOGGLE;
+        }
+    }
+}
+
+/**
+  * @brief       Get USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  * @details     Get USB endpoint stall state of the specified endpoint ID.
+  */
+static __inline uint32_t USBD_GetEpStall(uint32_t u32Ep)
+{
+    return (USBD->EP[u32Ep].EPRSPCTL & USB_EP_RSPCTL_HALT);
+}
+
+/**
+ * @brief       Get USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @retval      0: USB endpoint is not stalled.
+ * @retval      non-0: USB endpoint is stalled.
+ *
+ * @details     Get USB endpoint stall state.
+ */
+static __inline uint32_t USBD_GetStall(uint32_t u32EpNum)
+{
+    int i;
+
+    for (i = 0; i < USBD_MAX_EP; i++)
+    {
+        if (((USBD->EP[i].EPCFG & 0xf0) >> 4) == u32EpNum)
+        {
+            return (USBD->EP[i].EPRSPCTL & USB_EP_RSPCTL_HALT);
+        }
+    }
+    return 0;
+}
+
+
+/*-------------------------------------------------------------------------------------------*/
+typedef void (*VENDOR_REQ)(void); /*!<USB Vendor request callback function */
+typedef void (*CLASS_REQ)(void); /*!<USB Class request callback function */
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!<USB Standard request "Set Interface" callback function */
+
+void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_UpdateDeviceState(void);
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_CtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+
+
+
+/*@}*/ /* end of group N9H30_USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_USBD_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_USBD_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_wdt.h

@@ -0,0 +1,185 @@
+/**************************************************************************//**
+ * @file     wdt.h
+ * @brief    NUC980 series WDT driver header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WDT_H__
+#define __NU_WDT_H__
+#include "N9H30.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT Time-out Interval Period Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4           (0UL << 8) /*!< Setting WDT time-out interval to  2^4 * WDT clocks */
+#define WDT_TIMEOUT_2POW6           (1UL << 8) /*!< Setting WDT time-out interval to  2^6 * WDT clocks */
+#define WDT_TIMEOUT_2POW8           (2UL << 8) /*!< Setting WDT time-out interval to  2^8 * WDT clocks */
+#define WDT_TIMEOUT_2POW10          (3UL << 8) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
+#define WDT_TIMEOUT_2POW12          (4UL << 8) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
+#define WDT_TIMEOUT_2POW14          (5UL << 8) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
+#define WDT_TIMEOUT_2POW16          (6UL << 8) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
+#define WDT_TIMEOUT_2POW18          (7UL << 8) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT  Reset Delay Period Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK     (0UL) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
+#define WDT_RESET_DELAY_130CLK      (1UL) /*!< Setting WDT reset delay period to  130 * WDT clocks */
+#define WDT_RESET_DELAY_18CLK       (2UL) /*!< Setting WDT reset delay period to   18 * WDT clocks */
+#define WDT_RESET_DELAY_3CLK        (3UL) /*!< Setting WDT reset delay period to    3 * WDT clocks */
+
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out reset system flag.
+  *
+  * \hideinitializer
+  */
+#define WDT_CLEAR_RESET_FLAG()          outpw(REG_WDT_CTL, (inpw(REG_WDT_CTL) & ~0x8) | 0x04)
+
+/**
+  * @brief      Clear WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out interrupt flag.
+  *
+  * \hideinitializer
+  */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG()    outpw(REG_WDT_CTL, (inpw(REG_WDT_CTL) & ~0x4) | 0x08)
+
+/**
+  * @brief      Get WDT Time-out Reset Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out reset system did not occur
+  * @retval     1   WDT time-out reset system occurred
+  *
+  * @details    This macro indicates system has been reset by WDT time-out reset or not.
+  *
+  * \hideinitializer
+  */
+#define WDT_GET_RESET_FLAG()            (inpw(REG_WDT_CTL) & 0x4 ? 1 : 0)
+
+/**
+  * @brief      Get WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt did not occur
+  * @retval     1   WDT time-out interrupt occurred
+  *
+  * @details    This macro indicates WDT time-out interrupt occurred or not.
+  *
+  * \hideinitializer
+  */
+#define WDT_GET_TIMEOUT_INT_FLAG()      (inpw(REG_WDT_CTL) & 0x8 ? 1 : 0)
+
+/**
+  * @brief      Reset WDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reset the internal 18-bit WDT up counter value.
+  * @note       If WDT is activated and time-out reset system function is enabled also, user should \n
+  *             reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+  *             reset system before the WDT time-out reset delay period expires.
+  *
+  * \hideinitializer
+  */
+#define WDT_RESET_COUNTER()   outpw(REG_WDT_CTL, inpw(REG_WDT_CTL) | (0x1))
+
+/**
+  * @brief      Stop WDT Counting
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will stop WDT counting and disable WDT module.
+  */
+static __inline void WDT_Close(void)
+{
+    outpw(REG_WDT_CTL, 0);
+    return;
+}
+
+/**
+  * @brief      Enable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will enable the WDT time-out interrupt function.
+  */
+static __inline void WDT_EnableInt(void)
+{
+    outpw(REG_WDT_CTL, inpw(REG_WDT_CTL) | 0x40);
+    return;
+}
+
+/**
+  * @brief      Disable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will disable the WDT time-out interrupt function.
+  */
+static __inline void WDT_DisableInt(void)
+{
+    /* Do not touch another write 1 clear bits */
+    outpw(REG_WDT_CTL, (inpw(REG_WDT_CTL) & ~0x6C) | 0x04);
+    return;
+}
+
+void WDT_Open(UINT32 u32TimeoutInterval, UINT32 u32ResetDelay, UINT32 u32EnableReset, UINT32 u32EnableWakeup);
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_WDT_H__ */
+

bsp/nuvoton/libraries/n9h30/Driver/Include/nu_wwdt.h

@@ -0,0 +1,120 @@
+/**************************************************************************//**
+ * @file     wwdt.h
+ * @brief    N9H30 WWDT driver header file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WWDT_H__
+#define __NU_WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "N9H30.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup N9H30_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+  @{
+*/
+#define WWDT_PRESCALER_1          (0UL << 8)   ///< WWDT setting prescaler to 1     \hideinitializer
+#define WWDT_PRESCALER_2          (1UL << 8)   ///< WWDT setting prescaler to 2     \hideinitializer
+#define WWDT_PRESCALER_4          (2UL << 8)   ///< WWDT setting prescaler to 4     \hideinitializer
+#define WWDT_PRESCALER_8          (3UL << 8)   ///< WWDT setting prescaler to 8     \hideinitializer
+#define WWDT_PRESCALER_16         (4UL << 8)   ///< WWDT setting prescaler to 16    \hideinitializer
+#define WWDT_PRESCALER_32         (5UL << 8)   ///< WWDT setting prescaler to 32    \hideinitializer
+#define WWDT_PRESCALER_64         (6UL << 8)   ///< WWDT setting prescaler to 64    \hideinitializer
+#define WWDT_PRESCALER_128        (7UL << 8)   ///< WWDT setting prescaler to 128   \hideinitializer
+#define WWDT_PRESCALER_192        (8UL << 8)   ///< WWDT setting prescaler to 192   \hideinitializer
+#define WWDT_PRESCALER_256        (9UL << 8)   ///< WWDT setting prescaler to 256   \hideinitializer
+#define WWDT_PRESCALER_384        (0xAUL << 8) ///< WWDT setting prescaler to 384   \hideinitializer
+#define WWDT_PRESCALER_512        (0xBUL << 8) ///< WWDT setting prescaler to 512   \hideinitializer
+#define WWDT_PRESCALER_768        (0xCUL << 8) ///< WWDT setting prescaler to 768   \hideinitializer
+#define WWDT_PRESCALER_1024       (0xDUL << 8) ///< WWDT setting prescaler to 1024  \hideinitializer
+#define WWDT_PRESCALER_1536       (0xEUL << 8) ///< WWDT setting prescaler to 1536  \hideinitializer
+#define WWDT_PRESCALER_2048       (0xFUL << 8) ///< WWDT setting prescaler to 2048  \hideinitializer
+
+#define WWDT_RELOAD_WORD          (0x00005AA5)                     ///< Fill this value to RLD register to reload WWDT counter  \hideinitializer
+/*@}*/ /* end of group N9H30_WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup N9H30_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief This macro clear WWDT time-out reset system flag.
+  * @return None
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_RESET_FLAG()  outpw(REG_WWDT_STATUS, 0x2)
+
+/**
+  * @brief This macro clear WWDT compare match interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_INT_FLAG() outpw(REG_WWDT_STATUS, 0x1)
+
+/**
+  * @brief This macro is use to get WWDT time-out reset system flag.
+  * @return WWDT reset system or not
+  * @retval 0 WWDT did not cause system reset
+  * @retval 1 WWDT caused system reset
+  * \hideinitializer
+  */
+#define WWDT_GET_RESET_FLAG() (inpw(REG_WWDT_STATUS) & 0x2 ? 1 : 0)
+
+/**
+  * @brief This macro is used to indicate WWDT compare match interrupt flag.
+  * @return WWDT compare match interrupt occurred or not
+  * @retval 0 WWDT compare match interrupt did not occur
+  * @retval 1 WWDT compare match interrupt occurred
+  * \hideinitializer
+  */
+#define WWDT_GET_INT_FLAG() (inpw(REG_WWDT_STATUS) & 0x1 ? 1 : 0)
+
+/**
+  * @brief This macro to reflects current WWDT counter value
+  * @return Return current WWDT counter value
+  * \hideinitializer
+  */
+#define WWDT_GET_COUNTER() inpw(REG_WWDT_CNT)
+
+/**
+  * @brief This macro is used to reload the WWDT counter value to 0x3F.
+  * @return None
+  * @details After WWDT enabled, application must reload WWDT counter while
+  *          current counter is less than compare value and larger than 0,
+  *          otherwise WWDT will cause system reset.
+  * \hideinitializer
+  */
+#define WWDT_RELOAD_COUNTER() outpw(REG_WWDT_RLDCNT, WWDT_RELOAD_WORD)
+
+
+void WWDT_Open(UINT u32PreScale, UINT u32CmpValue, UINT u32EnableInt);
+
+
+/*@}*/ /* end of group N9H30_WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_WWDT_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_WWDT_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/SConscript

@@ -0,0 +1,26 @@
+# RT-Thread building script for component
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+libs = []
+src = Glob('Source/*.c') + Glob('Source/*.cpp')
+cpppath = [cwd + '/Include']
+libpath = [cwd + '/Library']
+
+if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
+	if rtconfig.CROSS_TOOL == 'keil':
+		if GetOption('target') == 'mdk4' and os.path.isfile('./Library/libstddriver_keil4.lib'):
+			libs += ['libstddriver_keil4']
+		if GetOption('target') == 'mdk5' and os.path.isfile('./Library/libstddriver_keil.lib'):
+			libs += ['libstddriver_keil']
+	elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./Library/libstddriver_gcc.a'):
+		libs += ['libstddriver_gcc']
+
+if not libs:
+	group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
+else:
+	src = []
+	group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
+
+Return('group')

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_can.c

@@ -0,0 +1,1286 @@
+/**************************************************************************//**
+ * @file     can.c
+ * @version  V2.00
+ * @brief    N9H30 series CAN driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "nu_can.h"
+#include "nu_sys.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+static uint8_t gu8LockCanIf[4ul][2ul] = {0ul};    /* The chip have 4 CANs. */
+
+#define RETRY_COUNTS    (0x10000000ul)
+
+#define TSEG1_MIN 2ul
+#define TSEG1_MAX 16ul
+#define TSEG2_MIN 1ul
+#define TSEG2_MAX 8ul
+#define BRP_MIN   1ul
+#define BRP_MAX   1024ul  /* 6-bit BRP field + 4-bit BRPE field*/
+#define SJW_MAX   4ul
+#define BRP_INC   1ul
+
+/* #define DEBUG_PRINTF printf */
+#define DEBUG_PRINTF(...)
+
+static uint32_t CAN_Clock = 75000000ul;
+
+static uint32_t LockIF(CAN_T *tCAN);
+static uint32_t LockIF_TL(CAN_T *tCAN);
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo);
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2);
+
+/**
+  * @brief Check if any interface is available then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If a interface is
+  *          available, set a flag to lock the interface.
+  */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+    uint32_t u32CanNo;
+    uint32_t u32FreeIfNo = 2ul;
+    uint32_t u32IntMask;
+
+    if (tCAN == CAN0)
+        u32CanNo = 0ul;
+#if defined(CAN1)
+    else if (tCAN == CAN1)
+        u32CanNo = 1ul;
+#endif
+#if defined(CAN2)
+    else if (tCAN == CAN2)
+        u32CanNo = 2ul;
+#endif
+#if defined(CAN3)
+    else if (tCAN == CAN3)
+        u32CanNo = 3ul;
+#endif
+    else
+        return u32FreeIfNo;
+
+    /* Disable CAN interrupt */
+    u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+    tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+    /* Check interface 1 is available or not */
+    if ((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+    {
+        if (gu8LockCanIf[u32CanNo][0ul] == 0ul)
+        {
+            gu8LockCanIf[u32CanNo][0ul] = 1u;
+            u32FreeIfNo = 0ul;
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+
+    /* Or check interface 2 is available or not */
+    if (u32FreeIfNo == 2ul)
+    {
+        if ((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+        {
+            if (gu8LockCanIf[u32CanNo][1ul] == 0ul)
+            {
+                gu8LockCanIf[u32CanNo][1ul] = 1u;
+                u32FreeIfNo = 1ul;
+            }
+            else
+            {
+            }
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+
+    /* Enable CAN interrupt */
+    tCAN->CON |= u32IntMask;
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Check if any interface is available in a time limitation then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If no interface is
+  *          it will try again until time out. If a interface is available,  set a flag to
+  *          lock the interface.
+  */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+    uint32_t u32Count;
+    uint32_t u32FreeIfNo;
+
+    for (u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++)
+    {
+        if ((u32FreeIfNo = LockIF(tCAN)) != 2ul)
+        {
+            break;
+        }
+        else
+        {
+        }
+    }
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Release locked interface.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Info The interface number, 0 or 1.
+  * @return none
+  * @details Release the locked interface.
+  */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+    uint32_t u32IntMask;
+    uint32_t u32CanNo;
+
+    if (u32IfNo >= 2ul)
+    {
+    }
+    else
+    {
+        if (tCAN == CAN0)
+            u32CanNo = 0ul;
+#if defined(CAN1)
+        else if (tCAN == CAN1)
+            u32CanNo = 1ul;
+#endif
+#if defined(CAN2)
+        else if (tCAN == CAN2)
+            u32CanNo = 2ul;
+#endif
+#if defined(CAN3)
+        else if (tCAN == CAN3)
+            u32CanNo = 3ul;
+#endif
+        else
+            return ;
+
+
+        /* Disable CAN interrupt */
+        u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+        tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+        gu8LockCanIf[u32CanNo][u32IfNo] = 0u;
+
+        /* Enable CAN interrupt */
+        tCAN->CON |= u32IntMask;
+    }
+}
+
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)
+{
+    *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
+    if (*tseg2 < TSEG2_MIN)
+    {
+        *tseg2 = TSEG2_MIN;
+    }
+    else
+    {
+    }
+
+    if (*tseg2 > TSEG2_MAX)
+    {
+        *tseg2 = TSEG2_MAX;
+    }
+    else
+    {
+    }
+
+    *tseg1 = tseg - *tseg2;
+    if (*tseg1 > TSEG1_MAX)
+    {
+        *tseg1 = TSEG1_MAX;
+        *tseg2 = tseg - *tseg1;
+    }
+    else
+    {
+    }
+
+    return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief Enter initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8Mask Following values can be used.
+  *            \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+  *            \ref CAN_CON_EIE_Msk Enable error interrupt.
+  *            \ref CAN_CON_SIE_Msk Enable status interrupt.
+  *            \ref CAN_CON_IE_Msk CAN interrupt.
+  * @return None
+  * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+  *          register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+  *          to leave initialization mode and lock bit timing register to let new configuration
+  *          take effect.
+  */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+    tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+  * @brief Leave initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to set CAN to leave initialization mode to let
+  *          bit timing configuration take effect after configuration ready.
+  */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+    tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+    while (tCAN->CON & CAN_CON_INIT_Msk)
+    {
+        /* Check INIT bit is released */
+    }
+}
+
+/**
+  * @brief Wait message into message buffer in basic mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to wait message into message buffer in basic mode. Please notice the
+  *          function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+  */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+    tCAN->STATUS = 0x0ul; /* clr status */
+
+    while (1)
+    {
+        if (tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk)  /* check new data */
+        {
+            /* New Data IN */
+            break;
+        }
+        else
+        {
+        }
+
+        if (tCAN->STATUS & CAN_STATUS_RXOK_Msk)
+        {
+            /* Rx OK */
+        }
+        else
+        {
+        }
+
+        if (tCAN->STATUS & CAN_STATUS_LEC_Msk)
+        {
+            /* Error */
+        }
+        else
+        {
+        }
+    }
+}
+
+/**
+  * @brief Get current bit rate
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return Current Bit-Rate (kilo bit per second)
+  * @details Return current CAN bit rate according to the user bit-timing parameter settings
+  */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+    uint32_t u32Tseg1, u32Tseg2;
+    uint32_t u32Bpr;
+
+    u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
+    u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
+    u32Bpr   = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul);
+
+    return (CAN_Clock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul));
+}
+
+/**
+  * @brief Switch the CAN into test mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8TestMask Specifies the configuration in test modes
+  *                       \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+  *                       \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+  *                       \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+  *                       \ref CAN_TEST_Tx_Msk Control CAN_TX pin bit field
+  * @return None
+  * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+  *          LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+  *          must call CAN_LeaveInitMode() to let the setting take effect.
+  */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST = u8TestMask;
+}
+
+
+/**
+  * @brief Leave the test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return   None
+  * @details  This function is used to Leave the test mode (switch into normal mode).
+  */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+    tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+  * @brief Get the waiting status of a received message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @retval non-zero The corresponding message object has a new data bit is set.
+  * @retval 0 No message object has new data.
+  * @details This function is used to get the waiting status of a received message.
+  */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+    return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul)));
+}
+
+
+/**
+  * @brief Send CAN message in BASIC mode of test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+  * @return TRUE:  Transmission OK
+  *         FALSE: Check busy flag of interface 0 is timeout
+  * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+  *          the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+  *          basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+  */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg)
+{
+    uint32_t i = 0ul;
+    int32_t rev = 1l;
+
+    while (tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    if (pCanMsg->IdType == CAN_STD_ID)
+    {
+        /* standard ID*/
+        tCAN->IF[0].ARB1 = 0ul;
+        tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ;
+    }
+    else
+    {
+        /* extended ID*/
+        tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+        tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul  | CAN_IF_ARB2_XTD_Msk;
+
+    }
+
+    if (pCanMsg->FrameType)
+    {
+        tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+    }
+    else
+    {
+        tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+    }
+
+    tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+    tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]);
+    tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]);
+    tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]);
+    tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]);
+
+    /* request transmission*/
+    tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+    if (tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /* Cannot clear busy for sending ...*/
+        rev = 0l; /* return FALSE */
+    }
+    else
+    {
+        tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk;  /* sending */
+
+        for (i = 0ul; i < 0xFFFFFul; i++)
+        {
+            if ((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul)
+            {
+                break;
+            }
+            else
+            {
+            }
+        }
+
+        if (i >= 0xFFFFFul)
+        {
+            /* Cannot send out... */
+            rev = 0l; /* return FALSE */
+        }
+        else
+        {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Get a message information in BASIC mode.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @return FALSE No any message received.
+  *         TRUE Receive a message success.
+  *
+  */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg)
+{
+    int32_t rev = 1l;
+
+    if ((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul)
+    {
+        /* In basic mode, receive data always save in IF2 */
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+
+        tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+        tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+                            | CAN_IF_CMASK_CONTROL_Msk
+                            | CAN_IF_CMASK_DATAA_Msk
+                            | CAN_IF_CMASK_DATAB_Msk;
+
+        if ((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul)
+        {
+            /* standard ID*/
+            pCanMsg->IdType = CAN_STD_ID;
+            pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul;
+
+        }
+        else
+        {
+            /* extended ID*/
+            pCanMsg->IdType = CAN_EXT_ID;
+            pCanMsg->Id  = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16;
+            pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+        }
+
+        pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul;
+
+        pCanMsg->DLC     = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk);
+        pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+        pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+        pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+        pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+        pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+        pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+        pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+        pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set Rx message object, include ID mask.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u32idmask Specifies the identifier mask used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    /* Get and lock a free interface */
+    if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+    {
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+        /* Command Setting */
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+        if (u8idType == CAN_STD_ID)   /* According STD/EXT ID format,Configure Mask and Arbitration register */
+        {
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+        }
+        else
+        {
+            tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+        }
+
+        tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul);
+        tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul;
+
+        /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+        tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+        if (u8singleOrFifoLast)
+        {
+            tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+        }
+        else
+        {
+            tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_A2  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B2  = 0ul;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set Rx message object
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    /* Get and lock a free interface */
+    if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+    {
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+        /* Command Setting */
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+        if (u8idType == CAN_STD_ID)   /* According STD/EXT ID format,Configure Mask and Arbitration register */
+        {
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+        }
+        else
+        {
+            tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+        }
+
+        /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+        tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+        if (u8singleOrFifoLast)
+        {
+            tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+        }
+        else
+        {
+            tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_A2  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B2  = 0ul;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Gets the message
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8Release Specifies the message release indicator.
+  *                      This parameter can be one of the following values:
+  *                      TRUE: the message object is released when getting the data.
+  *                      FALSE:the message object is not released.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  * @retval TRUE Success
+  * @retval FALSE No any message received
+  * @details Gets the message, if received.
+  */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T *pCanMsg)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if (!CAN_IsNewDataReceived(tCAN, u8MsgObj))
+    {
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+        /* Get and lock a free interface */
+        if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+        {
+            rev = 0; /* return FALSE */
+        }
+        else
+        {
+            tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+            /* read the message contents*/
+            tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+                                          | CAN_IF_CMASK_ARB_Msk
+                                          | CAN_IF_CMASK_CONTROL_Msk
+                                          | CAN_IF_CMASK_CLRINTPND_Msk
+                                          | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul)
+                                          | CAN_IF_CMASK_DATAA_Msk
+                                          | CAN_IF_CMASK_DATAB_Msk;
+
+            tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+
+            while (tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+            {
+                /*Wait*/
+            }
+
+            if ((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul)
+            {
+                /* standard ID*/
+                pCanMsg->IdType = CAN_STD_ID;
+                pCanMsg->Id     = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul;
+            }
+            else
+            {
+                /* extended ID*/
+                pCanMsg->IdType = CAN_EXT_ID;
+                pCanMsg->Id  = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1;
+            }
+
+            pCanMsg->DLC     = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk);
+            pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+            pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+            pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+            pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+            pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+            pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+            pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+            pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+
+            ReleaseIF(tCAN, u32MsgIfNum);
+        }
+    }
+
+    return rev;
+}
+
+
+/**
+  * @brief Set bus baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  *
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+  */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+    long rate;
+    long best_error = 1000000000, error = 0;
+    int best_tseg = 0, best_brp = 0, brp = 0;
+    int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
+    int spt_error = 1000, spt = 0, sampl_pt;
+    uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1;
+    uint32_t sjw = (uint32_t)1;
+
+    CAN_EnterInitMode(tCAN, (uint8_t)0);
+
+    CAN_Clock = sysGetClock(SYS_PCLK) * 1000000;
+
+    clock_freq = CAN_Clock / u64PCLK_DIV;
+
+    if (u32BaudRate >= (uint32_t)1000000)
+    {
+        u32BaudRate = (uint32_t)1000000;
+    }
+
+    /* Use CIA recommended sample points */
+    if (u32BaudRate > (uint32_t)800000)
+    {
+        sampl_pt = (int)750;
+    }
+    else if (u32BaudRate > (uint32_t)500000)
+    {
+        sampl_pt = (int)800;
+    }
+    else
+    {
+        sampl_pt = (int)875;
+    }
+
+    /* tseg even = round down, odd = round up */
+    for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--)
+    {
+        tsegall = 1ul + tseg / 2ul;
+        /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
+        brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2;
+        /* chose brp step which is possible in system */
+        brp = (brp / BRP_INC) * BRP_INC;
+
+        if ((brp < BRP_MIN) || (brp > BRP_MAX))
+        {
+            continue;
+        }
+        rate = clock_freq / (brp * tsegall);
+
+        error = u32BaudRate - rate;
+
+        /* tseg brp biterror */
+        if (error < 0)
+        {
+            error = -error;
+        }
+        if (error > best_error)
+        {
+            continue;
+        }
+        best_error = error;
+        if (error == 0)
+        {
+            spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2);
+            error = sampl_pt - spt;
+            if (error < 0)
+            {
+                error = -error;
+            }
+            if (error > spt_error)
+            {
+                continue;
+            }
+            spt_error = error;
+        }
+        best_tseg = tseg / 2;
+        best_brp = brp;
+
+        if (error == 0)
+        {
+            break;
+        }
+    }
+
+    spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2);
+
+    /* check for sjw user settings */
+    /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */
+    if (sjw > SJW_MAX)
+    {
+        sjw = SJW_MAX;
+    }
+    /* bt->sjw must not be higher than tseg2 */
+    if (tseg2 < sjw)
+    {
+        sjw = tseg2;
+    }
+
+    /* real bit-rate */
+    u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1));
+
+    tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) |
+                  ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos);
+    tCAN->BRPE  = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful;
+
+    /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */
+
+    CAN_LeaveInitMode(tCAN);
+
+    return u32BaudRate;
+}
+
+/**
+  * @brief The function is used to disable all CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  *
+  * @return None
+  *
+  * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+  */
+void CAN_Close(CAN_T *tCAN)
+{
+    CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Set CAN operation mode and target baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  * @param[in] u32Mode The CAN operation mode. Valid values are:
+  *                    - \ref CAN_NORMAL_MODE Normal operation.
+  *                    - \ref CAN_BASIC_MODE Basic mode.
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details Set bus timing parameter according current clock and target baud-rate.
+  *          In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+  */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+    uint32_t u32CurrentBitRate;
+
+    u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+    if (u32Mode == CAN_BASIC_MODE)
+    {
+        CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk);
+    }
+    else
+    {
+    }
+
+    return u32CurrentBitRate;
+}
+
+/**
+  * @brief The function is used to configure a transmit object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Config message object success.
+  *
+  * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+  *          They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+  */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+    {
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+        /* update the contents needed for transmission*/
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk  | CAN_IF_CMASK_DATAB_Msk;
+
+        if (pCanMsg->IdType == CAN_STD_ID)
+        {
+            /* standard ID*/
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+        }
+        else
+        {
+            /* extended ID*/
+            tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 |
+                                         CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+        }
+
+        if (pCanMsg->FrameType)
+        {
+            tCAN->IF[u32MsgIfNum].ARB2 |=   CAN_IF_ARB2_DIR_Msk;
+        }
+        else
+        {
+            tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]);
+        tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]);
+        tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]);
+        tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]);
+
+        tCAN->IF[u32MsgIfNum].MCON   =  CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+        tCAN->IF[u32MsgIfNum].CREQ   = 1ul + u32MsgNum;
+
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set transmit request bit.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return TRUE: Start transmit message.
+  *
+  * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+  */
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+    {
+        rev = 0; /* return FALSE */
+    }
+    else
+    {
+        tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+        /* read the message contents*/
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+                                      | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+        while (tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+        {
+            /*Wait*/
+        }
+        tCAN->IF[u32MsgIfNum].CMASK  = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+        tCAN->IF[u32MsgIfNum].CREQ  = 1ul + u32MsgNum;
+
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Enable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. Valid values are:
+  *                    - \ref CAN_CON_IE_Msk Module interrupt enable.
+  *                    - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+  *                    - \ref CAN_CON_EIE_Msk Error interrupt enable.
+  *
+  * @return None
+  *
+  * @details The application software has two possibilities to follow the source of a message interrupt.
+  *          First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+  */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+                (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Disable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+  *
+  * @return None
+  *
+  * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+  */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32TimeOutCount = 0ul;
+
+    while (CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE)
+    {
+        if (++u32TimeOutCount >= RETRY_COUNTS)
+        {
+            rev = (int32_t)(FALSE); /* return FALSE */
+            break;
+        }
+        else
+        {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+    int32_t  rev = (int32_t)TRUE;
+    uint32_t u32TimeOutCount = 0ul;
+
+    while (CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE)
+    {
+        if (++u32TimeOutCount >= RETRY_COUNTS)
+        {
+            rev = (int32_t)FALSE;
+            break;
+        }
+        else
+        {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief The function is used to configure several receive message objects.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+  * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure receive message objects success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+    int32_t  rev = (int32_t)TRUE;
+    uint32_t i;
+    uint32_t u32TimeOutCount;
+    uint32_t u32EOB_Flag = 0ul;
+
+    for (i = 1ul; i <= u32MsgCount; i++)
+    {
+        u32TimeOutCount = 0ul;
+
+        u32MsgNum += (i - 1ul);
+
+        if (i == u32MsgCount)
+        {
+            u32EOB_Flag = 1ul;
+        }
+        else
+        {
+        }
+
+        while (CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE)
+        {
+            if (++u32TimeOutCount >= RETRY_COUNTS)
+            {
+                rev = (int32_t)FALSE;
+                break;
+            }
+            else
+            {
+            }
+        }
+    }
+
+    return rev;
+}
+
+
+/**
+  * @brief Send CAN message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+  *               2. When operation in normal mode: No useful interface. \n
+  * @retval TRUE Transmit Message success.
+  *
+  * @details The receive/transmit priority for the Message Objects is attached to the message number.
+  *          Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+  */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32Tmp;
+
+    u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+    if ((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp)
+    {
+        rev = CAN_BasicSendMsg(tCAN, pCanMsg);
+    }
+    else
+    {
+        if (CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
+        {
+            rev = (int32_t)FALSE;
+        }
+        else
+        {
+            CAN_TriggerTxMsg(tCAN, u32MsgNum);
+        }
+    }
+
+    return rev;
+}
+
+
+/**
+  * @brief Gets the message, if received.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No any message received.
+  * @retval TRUE Receive Message success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32Tmp;
+
+    u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+    if ((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp)
+    {
+        rev = CAN_BasicReceiveMsg(tCAN, pCanMsg);
+    }
+    else
+    {
+        rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Clear interrupt pending bit.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return None
+  *
+  * @details An interrupt remains pending until the application software has cleared it.
+  */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+    uint32_t u32MsgIfNum;
+
+    if ((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul)
+    {
+        u32MsgIfNum = 0ul;
+    }
+    else
+    {
+    }
+
+    tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+    ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_cap.c

@@ -0,0 +1,1520 @@
+/**************************************************************************//**
+* @file     cap.c
+* @version  V1.00
+* @brief    N9H30 CAP driver source file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_cap.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CAP_Driver CAP Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CAP_EXPORTED_FUNCTIONS CAP Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+PFN_CAP_CALLBACK(pfnCAP_IntHandlerTable)[4] = {0};
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ * @brief       CAP interrupt Handler
+ *
+ * @param       None
+ *
+ * @return      None
+ *
+ * @details     Driver internal use API to process the interrupt of CAP
+ *              As interrupt occurrence, the register call back function will be executed
+ */
+static UINT32 u32EscapeFrame = 0;
+//static UINT32 g_u32DeviceType = 0;
+static void CAP_IntHandler(void)
+{
+    UINT32 u32CapInt;
+    UINT32 uBuf = 0;
+
+    if ((inp32(REG_CLK_HCLKEN) & (0x1 << 26)) == (0x1 << 26)) /* CMOS sensor interface controller clock enabled */
+    {
+        u32CapInt = inp32(REG_CAP_INT);
+        if ((u32CapInt & (VIEN | VINTF)) == (VIEN | VINTF))
+        {
+            if (pfnCAP_IntHandlerTable[0] != 0)
+                pfnCAP_IntHandlerTable[0](uBuf, uBuf, u32EscapeFrame);
+            outp32(REG_CAP_INT, (u32CapInt & ~(MDINTF | ADDRMINTF | MEINTF)));    /* Clear Frame end interrupt */
+            u32EscapeFrame = u32EscapeFrame + 1;
+        }
+        else if ((u32CapInt & (ADDRMIEN | ADDRMINTF)) == (ADDRMIEN | ADDRMINTF))
+        {
+            if (pfnCAP_IntHandlerTable[1] != 0)
+                pfnCAP_IntHandlerTable[1](uBuf, uBuf, u32EscapeFrame);
+            outp32(REG_CAP_INT, (u32CapInt & ~(MDINTF | VINTF | MEINTF)));      /* Clear Address match interrupt */
+        }
+        else if ((u32CapInt & (MEIEN | MEINTF)) == (MEIEN | MEINTF))
+        {
+            if (pfnCAP_IntHandlerTable[2] != 0)
+                pfnCAP_IntHandlerTable[2](uBuf, uBuf, u32EscapeFrame);
+            outp32(REG_CAP_INT, (u32CapInt & ~(MDINTF | VINTF | ADDRMINTF)));   /* Clear Memory error interrupt */
+        }
+        else if ((u32CapInt & (MDIEN | MDINTF)) == (MDIEN | MDINTF))
+        {
+            if (pfnCAP_IntHandlerTable[3] != 0)
+                pfnCAP_IntHandlerTable[3](uBuf, uBuf, u32EscapeFrame);
+            outp32(REG_CAP_INT, (u32CapInt & ~(VINTF | MEINTF | ADDRMINTF)));       /* Clear Memory error interrupt */
+        }
+    }
+}
+
+/**
+ * @brief       Set Inital Frame
+ *
+ * @return      None
+ *
+ * @details     If enable interrupt, there is internal counter that records how many frames have pass.
+ *              Set the internal counters to zero. The internal counter may be not a constant
+ */
+void CAP_SetInitFrame(void)
+{
+    u32EscapeFrame = 0;
+}
+
+/**
+ * @brief       Get Inital Frame
+ *
+ * @retval      >0 Internal counters
+ *
+ * @details     If enable interrupt, there is internal counter that records how many frames have pass.
+ *              Get the internal counters. The internal counter may be not a constant
+ */
+UINT32 CAP_GetSkipFrame(void)
+{
+    return u32EscapeFrame;
+}
+
+/**
+ * @brief       CAP Initial
+ *
+ * @param[in]       bIsEnableSnrClock  Enable/Disable sensor clock
+ *                  1 : Enable
+ *                  0 : Disable
+ * @param[in]       eSnrSrc            Set CAP clock source. Including :
+ *                  - \ref   eCAP_SNR_APLL
+ *                  - \ref   eCAP_SNR_UPLL
+ * @param[in]       u32SensorFreqKHz   Specify the sensor clock
+ *
+ * @return      None
+ *
+ * @details     To Initial sensor source clock and frequency for CAP interface
+ */
+void CAP_Init(BOOL bIsEnableSnrClock, E_CAP_SNR_SRC eSnrSrc, UINT32 u32SensorFreqKHz/*KHz unit*/)
+{
+    UINT32 u32PllClock, u32SenDiv;// u32ExtFreq;
+    UINT32 u32Div0, u32Div1;
+    UINT32 u32SenSrc;
+    volatile UINT32 u32Divider;
+
+    /* MFP_GPI_L : I3=SEN_CLK0, I4=SEN_PCLK, I5=SEN_HSYNC, I6=SEN_VSYNC, I7=SEN_FIFLD*/
+    outpw(REG_SYS_GPI_MFPL, (inpw(REG_SYS_GPI_MFPL) & (0x00000FFF)) | 0x33333000);
+
+    /* MFP_GPI_H : SEN_PDATA[0~7]*/
+    outpw(REG_SYS_GPI_MFPH, (inpw(REG_SYS_GPI_MFPH) & (0xFFFFFFFF)) | 0x33333333);
+
+    u32SensorFreqKHz = u32SensorFreqKHz * 1000;
+    switch (eSnrSrc)
+    {
+    case eCAP_SNR_APLL:
+        u32PllClock = sysGetClock(SYS_APLL) * 1000000;
+        u32SenSrc = 0x2 << 19; //APLL for sensor clock
+        break;
+    case eCAP_SNR_UPLL:
+        u32PllClock = sysGetClock(SYS_UPLL) * 1000000;
+        u32SenSrc = 0x3 << 19; //UPLL for sensor clock
+        break;
+    }
+
+
+    u32SenDiv = u32PllClock / (u32SensorFreqKHz);
+    if (u32PllClock % u32SensorFreqKHz != 0) u32SenDiv = u32SenDiv + 1;
+    for (u32Div1 = 1; u32Div1 <= 16; u32Div1 = u32Div1 + 1)
+    {
+        for (u32Div0 = 1; u32Div0 <= 8; u32Div0 = u32Div0 + 1)
+            if (u32SenDiv == u32Div0 * u32Div1)  break;
+        if (u32Div0 >= 9)    continue;
+        if (u32SenDiv == u32Div0 * u32Div1)  break;
+    }
+    //sysprintf("Div0 and Div1 = %d, %d ", u32Div0, u32Div1);
+    u32Div0 = u32Div0 - 1;
+    u32Div1 = u32Div1 - 1;
+
+    if (bIsEnableSnrClock)
+    {
+        outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) | (1 << 27));          /* CMOS Sensor Reference Clock Output Enable */
+        outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) | (1 << 26));          /* CMOS Sensor Interface Controller Clock Enable */
+    }
+    else
+    {
+        outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(1 << 27));           /* CMOS Sensor Reference Clock Output Disabled */
+        outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(1 << 26));           /* CMOS Sensor Interface Controller Clock Disabled */
+    }
+    u32Divider  = u32SenSrc | ((u32Div0 << 16) | (u32Div1 << 24)) ;
+    //sysprintf("Sensor Divider = 0x%08x\n", u32Divider);
+
+    outp32(REG_CLK_DIVCTL3, (inp32(REG_CLK_DIVCTL3) & ~((0x3 << 19) | (0x7 << 16) | (0xF << 24))) | u32Divider);
+
+
+}
+
+/**
+ * @brief       CAP Open
+ *
+ * @param[in]   u32SensorFreqKHz  Specify the sensor clock
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     Initialize the CAP engine. Register a call back for driver internal using
+ */
+INT32 CAP_Open(UINT32 u32SensorFreqKHz)
+{
+
+    UINT32 u32PllClock;// u32ExtFreq;
+    UINT32 u32SenDiv;
+    UINT32 u32Div0, u32Div1;
+    UINT32 u32SenSrc;
+    volatile UINT32 u32Divider;
+
+    u32SensorFreqKHz = u32SensorFreqKHz * 1000;
+
+    outp32(REG_CLK_PMCON, inpw(REG_CLK_PMCON) | (0x1 << 4)) ; /* Sensor clock keep on high level */
+    outp32(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (0x1 << 26)); /* CMOS sensor interface controller clock enable */
+    outp32(REG_SYS_AHBIPRST, inp32(REG_SYS_AHBIPRST) | (1 << 10)); /* Video capture (CMOS sensor interface) reset enable. */
+    outp32(REG_SYS_AHBIPRST, inp32(REG_SYS_AHBIPRST) & ~(1 << 10)); /* Video capture (CMOS sensor interface) reset disable */
+
+    switch ((inpw(REG_CLK_DIVCTL3) >> 19) & 0x3)
+    {
+    case eCAP_SNR_APLL:
+        u32PllClock = sysGetClock(SYS_APLL) * 1000000;
+        u32SenSrc = 0x2 << 19; //APLL for sensor clock
+        break;
+    case eCAP_SNR_UPLL:
+        u32PllClock = sysGetClock(SYS_UPLL) * 1000000;
+        u32SenSrc = 0x3 << 19; //APLL for sensor clock
+        break;
+    }
+
+    u32SenDiv = u32PllClock / (u32SensorFreqKHz);
+    if (u32PllClock % u32SensorFreqKHz != 0)
+        u32SenDiv = u32SenDiv + 1;
+    for (u32Div1 = 1; u32Div1 <= 16; u32Div1 = u32Div1 + 1)
+    {
+        for (u32Div0 = 1; u32Div0 <= 8; u32Div0 = u32Div0 + 1)
+        {
+            if (u32SenDiv == u32Div0 * u32Div1)
+                break;
+        }
+        if (u32Div0 >= 9)    continue;
+        if (u32SenDiv == u32Div0 * u32Div1)
+            break;
+    }
+    //sysprintf("Div0 and Div1 = %d, %d ", u32Div0, u32Div1);
+    u32Div0 = u32Div0 - 1;
+    u32Div1 = u32Div1 - 1;
+    u32Divider  = u32SenSrc | ((u32Div0 << 16) | (u32Div1 << 24)) ;
+    //sysprintf("Sensor Divider = 0x%08x\n", u32Divider);
+
+    outp32(REG_CLK_DIVCTL3, (inp32(REG_CLK_DIVCTL3) & ~((0x3 << 19) | (0x7 << 16) | (0xF << 24))) | u32Divider);
+
+    sysInstallISR(IRQ_LEVEL_1, CAP_IRQn, (PVOID)CAP_IntHandler);
+    sysEnableInterrupt(CAP_IRQn);
+
+    return Successful;
+}
+
+
+/**
+ * @brief       videoIn Reset
+ *
+ * @return      None
+ *
+ * @details     Capture interface reset.
+ */
+void CAP_Reset(void)
+{
+    outp32(REG_CAP_CTL, inp32(REG_CAP_CTL) | (VPRST));
+    outp32(REG_CAP_CTL, inp32(REG_CAP_CTL) & (~VPRST));
+}
+
+/**
+ * @brief       videoIn Close
+ *
+ * @return      None
+ *
+ * @details     Disable pin function,engine clock and interrupt
+ */
+void CAP_Close(void)
+{
+    // 1. Disable IP's interrupt
+    sysDisableInterrupt(CAP_IRQn);
+    // 2. Disable IP's clock
+    outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 25));
+    CAP_Reset();
+    outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 26));
+    // 3. Disable Capture pin function
+}
+
+/**
+ * @brief       Configure packet frame buffer.
+ *
+ * @param[in]   bFrameSwitch    Software mode buffer select
+ *                              0: Packet buffer 0
+ *                              1: Packet buffer 1
+ * @return      None
+ *
+ * @details     This function set packet frame buffer control
+ */
+void CAP_SetPacketFrameBufferControl(BOOL bFrameSwitch)
+{
+    UINT32 u32Ctl;
+    u32Ctl = inp32(REG_CAP_CTL) & ~(ADDRSW);
+    outp32(REG_CAP_CTL, u32Ctl | (bFrameSwitch ? ADDRSW : 0));
+}
+
+/**
+* @brief        Get packet frame buffer.
+ *
+ * @param       pbFrameSwitch   Software mode buffer select
+ *                              0: Packet buffer 0
+ *                              1: Packet buffer 1
+ * @return      None
+ *
+ * @details     This function get packet frame buffer control
+ */
+void CAP_GetPacketFrameBufferControl(PBOOL pbFrameSwitch)
+{
+    UINT32 u32Ctl = inp32(REG_CAP_CTL);
+    *pbFrameSwitch = (u32Ctl & ADDRSW) >> 3;
+}
+
+/**
+* @brief        Configure callback function
+ *
+ * @param[in]   eIntType         Set interrupt type. Including :
+ *                               - \ref eCAP_MDINTF
+ *                               - \ref eCAP_ADDRMINTF
+ *                               - \ref eCAP_MEINTF
+ *                               - \ref eCAP_VINTF
+ * @param[in]   pfnCallback      Set Callback function.
+ *                                The callbakc function :
+ *                                  void (*PFN_CAP_CALLBACK)(UINT8 u8PacketBufID,UINT8 u8PlanarBufID, UINT8 u8FrameRate);
+ * @param[in]   pfnOldCallback   Set Old callback function
+ *                                The callbakc function :
+ *                                  void *(*PFN_CAP_CALLBACK)(UINT8 u8PacketBufID,UINT8 u8PlanarBufID, UINT8 u8FrameRate);
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function configure callback function and set trigger level
+ */
+INT32 CAP_InstallCallback(E_CAP_INT_TYPE eIntType, PFN_CAP_CALLBACK pfnCallback, PFN_CAP_CALLBACK *pfnOldCallback)
+{
+    if (eIntType == eCAP_VINTF)
+    {
+        *pfnOldCallback = pfnCAP_IntHandlerTable[0];
+        pfnCAP_IntHandlerTable[0] = (PFN_CAP_CALLBACK)(pfnCallback);
+    }
+    else if (eIntType == eCAP_ADDRMINTF)
+    {
+        *pfnOldCallback = pfnCAP_IntHandlerTable[1];
+        pfnCAP_IntHandlerTable[1] = (PFN_CAP_CALLBACK)(pfnCallback);
+    }
+    else if (eIntType == eCAP_MEINTF)
+    {
+        *pfnOldCallback = pfnCAP_IntHandlerTable[2];
+        pfnCAP_IntHandlerTable[2] = (PFN_CAP_CALLBACK)(pfnCallback);
+    }
+    else if (eIntType == eCAP_MDINTF)
+    {
+        *pfnOldCallback = pfnCAP_IntHandlerTable[3];
+        pfnCAP_IntHandlerTable[3] = (PFN_CAP_CALLBACK)(pfnCallback);
+    }
+    else
+        return E_CAP_INVALID_INT;
+    return Successful;
+}
+
+/**
+ * @brief       Enable videoIn interrupt.
+ *
+ * @param[in]   eIntType     Interrupt type. Incuding:
+ *                           - \ref eCAP_MDINTF
+ *                           - \ref eCAP_ADDRMINTF
+ *                           - \ref eCAP_MEINTF
+ *                           - \ref eCAP_VINTF
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to enable videoIn interrupt.
+ */
+INT32 CAP_EnableInt(E_CAP_INT_TYPE eIntType)
+{
+    switch (eIntType)
+    {
+    case eCAP_MDINTF:
+    case eCAP_ADDRMINTF:
+    case eCAP_MEINTF:
+    case eCAP_VINTF:
+        outp32(REG_CAP_INT, inp32(REG_CAP_INT) | eIntType);
+        break;
+    default:
+        return E_CAP_INVALID_INT;
+    }
+    return Successful;
+}
+
+/**
+ * @brief       Disable videoIn interrupt
+ *
+ * @param[in]   eIntType     Interrupt type. Incuding:
+ *                           - \ref eCAP_MDINTF
+ *                           - \ref eCAP_ADDRMINTF
+ *                           - \ref eCAP_MEINTF
+ *                           - \ref eCAP_VINTF
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to disable videoIn interrupt.
+ */
+INT32 CAP_DisableInt(E_CAP_INT_TYPE eIntType)
+{
+    switch (eIntType)
+    {
+    case eCAP_MDINTF:
+    case eCAP_ADDRMINTF:
+    case eCAP_MEINTF:
+    case eCAP_VINTF:
+        outp32(REG_CAP_INT, inp32(REG_CAP_INT) & ~eIntType);
+        break;
+    default:
+        return E_CAP_INVALID_INT;
+    }
+    return Successful;
+}
+
+/**
+ * @brief       Check videoIn interrupt
+ *
+ * @param[in]   eIntType     Interrupt type. Incuding:
+ *                           - \ref eCAP_MDINTF
+ *                           - \ref eCAP_ADDRMINTF
+ *                           - \ref eCAP_MEINTF
+ *                           - \ref eCAP_VINTF
+ * @retval      1 Enable
+ * @retval      0 Disable
+ *
+ * @details     This function is used to check videoIn interrupt.
+ */
+BOOL CAP_IsIntEnabled(E_CAP_INT_TYPE eIntType)
+{
+    UINT32 u32IntEnable = inp32(REG_CAP_INT);
+    switch (eIntType)
+    {
+    case eCAP_MDINTF:
+        u32IntEnable = u32IntEnable & eCAP_MDINTF;
+        break;
+    case eCAP_ADDRMINTF:
+        u32IntEnable = u32IntEnable & eCAP_ADDRMINTF;
+        break;
+    case eCAP_MEINTF:
+        u32IntEnable = u32IntEnable & eCAP_MEINTF;
+        break;
+    case eCAP_VINTF:
+        u32IntEnable = u32IntEnable & eCAP_VINTF;
+        break;
+    }
+    return (u32IntEnable ? TRUE : FALSE);
+}
+
+/**
+ * @brief       Clear videoIn interrupt flag.
+ *
+ * @param[in]   eIntType    Interrupt type. Incuding:
+ *                          - \ref eCAP_MDINTF
+ *                          - \ref eCAP_ADDRMINTF
+ *                          - \ref eCAP_MEINTF
+ *                          - \ref eCAP_VINTF
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to clear videoIn interrupt flag.
+ */
+INT32 CAP_ClearInt(E_CAP_INT_TYPE eIntType)
+{
+    UINT32 u32IntChannel = eIntType >> 16;
+    switch (eIntType)
+    {
+    case eCAP_MDINTF:
+        outp32(REG_CAP_INT, (inp32(REG_CAP_INT) & ~((eCAP_ADDRMINTF | eCAP_MEINTF | eCAP_VINTF) >> 16)) |
+               u32IntChannel);
+        break;
+    case eCAP_ADDRMINTF:
+        outp32(REG_CAP_INT, (inp32(REG_CAP_INT) & ~((eCAP_MDINTF | eCAP_MEINTF | eCAP_VINTF) >> 16)) |
+               u32IntChannel);
+        break;
+    case eCAP_MEINTF:
+        outp32(REG_CAP_INT, (inp32(REG_CAP_INT) & ~((eCAP_MDINTF | eCAP_ADDRMINTF | eCAP_VINTF) >> 16)) |
+               u32IntChannel);
+        break;
+    case eCAP_VINTF:
+        outp32(REG_CAP_INT, (inp32(REG_CAP_INT) & ~((eCAP_MDINTF | eCAP_MEINTF | eCAP_ADDRMINTF) >> 16)) |
+               u32IntChannel);
+        break;
+    default:
+        return E_CAP_INVALID_INT;
+    }
+    return Successful;
+
+
+}
+
+/**
+ * @brief       Polling videoIn interrupt flag.
+ *
+ * @param[in]   eIntType    Interrupt type. Incuding:
+ *                          - \ref eCAP_MDINTF
+ *                          - \ref eCAP_ADDRMINTF
+ *                          - \ref eCAP_MEINTF
+ *                          - \ref eCAP_VINTF
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to poll videoIn interrupt flag.
+ */
+BOOL CAP_PollInt(E_CAP_INT_TYPE eIntType)
+{
+    UINT32 u32IntStatus = inp32(REG_CAP_INT);
+    switch (eIntType)
+    {
+    case eCAP_MDINTF:
+        u32IntStatus = u32IntStatus & (eCAP_MDINTF >> 16);
+        break;
+    case eCAP_ADDRMINTF:
+        u32IntStatus = u32IntStatus & (eCAP_ADDRMINTF >> 16);
+        break;
+    case eCAP_MEINTF:
+        u32IntStatus = u32IntStatus & (eCAP_MEINTF >> 16);
+        break;
+    case eCAP_VINTF:
+        u32IntStatus = u32IntStatus & (eCAP_VINTF >> 16);
+        break;
+    }
+    return (u32IntStatus ? TRUE : FALSE);
+}
+
+/**
+ * @brief       Enable engine clock and turn on the pipe.
+ *
+ * @param[in]   bEngEnable      Enable engine clock.
+ *                              1 : Enable engine clock.
+ *                              0 : Disable engine clock.
+ * @param[in]   ePipeEnable     Enable pipe type. Incuding:
+ *                              - \ref eCAP_BOTH_PIPE_DISABLE
+ *                              - \ref eCAP_PLANAR
+ *                              - \ref eCAP_PACKET
+ *                              - \ref eCAP_BOTH_PIPE_ENABLE
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to enable engine clock and pipe type.
+ */
+void CAP_SetPipeEnable(
+    BOOL bEngEnable,
+    E_CAP_PIPE ePipeEnable
+)
+{
+    outp32(REG_CAP_CTL, (inp32(REG_CAP_CTL) & ~(CAPEN | PKTEN | PLNEN))
+           | (((bEngEnable ? CAPEN : 0x0))
+              // | ((ePipeEnable & ~(PKTEN | PLNEN))<<5)) );
+              | ((ePipeEnable & 0x03) << 5)));
+} // DrvVideoIn_SetPipeEnable
+
+/**
+ * @brief       Get engine clock and pipe type.
+ *
+ * @param[out]  pbEngEnable     Enable engine clock.
+ *                              1 : Enable engine clock.
+ *                              0 : Disable engine clock.
+ * @param[out]  pePipeEnable    Pipe type. Incuding:
+ *                              - \ref eCAP_BOTH_PIPE_DISABLE
+ *                              - \ref eCAP_PLANAR
+ *                              - \ref eCAP_PACKET
+ *                              - \ref eCAP_BOTH_PIPE_ENABLE
+ * @return      None
+ *
+ * @details     This function is used to get engin clock and pipe type.
+ */
+void CAP_GetPipeEnable(PBOOL pbEngEnable, E_CAP_PIPE *pePipeEnable)
+{
+    UINT32 u32Temp = inp32(REG_CAP_CTL);
+
+    *pbEngEnable = (u32Temp & CAPEN) ? TRUE : FALSE;
+    *pePipeEnable = (E_CAP_PIPE)((u32Temp & (PKTEN | PLNEN)) >> 5);
+} // DrvVideoIn_GetPipeEnable
+
+
+/**
+ * @brief       Set Shadow(Update) Register
+ *
+ * @details     This function is used to reload frame buffer address after
+ *              setting shoaw(update) register.
+ */
+void CAP_SetShadowRegister(void)
+{
+    outp32(REG_CAP_CTL,  inp32(REG_CAP_CTL) | UPDATE);
+} // DrvVideoIn_SetShadowRegister
+
+
+/**
+ * @brief      Set sensor polarity.
+ *
+ * @param[in]   bVsync     Sensor Vsync Polarity.
+ *                         1  : High Active
+ *                         0  : Low Active
+ * @param[in]   bHsync     Sensor Hsync Polarity.
+ *                         1  : High Active
+ *                         0  : Low Active
+ * @param[in]   bPixelClk  Sensor Vsync Polarity.
+ *                         1  : Falling Edge
+ *                         0  : Rising Edig
+ * @return       None
+ *
+ * @details     This function is used to set sensor polarity.
+ */
+void CAP_SetSensorPolarity(BOOL bVsync, BOOL bHsync, BOOL bPixelClk)
+{
+    UINT32 u32Polarity, u32RegVal;
+    u32RegVal = inp32(REG_CAP_PAR);
+    //sysprintf("Enter Register addr = 0x%x\n", (REG_CAP_PAR));
+    //sysprintf("Enter Register value = 0x%x\n", u32RegVal);
+    u32Polarity = (((bVsync ? VSP : 0x0) | (bHsync ? HSP : 0x0)) | (bPixelClk ? PCLKP : 0x0));
+    u32RegVal = (inp32(REG_CAP_PAR) & ~(VSP | HSP | PCLKP)) ;
+    //sysprintf("REG_VPEPAR = 0x%x", (u32RegVal | u32Polarity));
+    outp32((REG_CAP_PAR), (u32RegVal | u32Polarity));
+}
+
+/**
+ * @brief      Get sensor polarity.
+ *
+ * @param[out]   pbVsync     Sensor Vsync Polarity.
+ *                           1  : High Active
+ *                           0  : Low Active
+ * @param[out]   pbHsync     Sensor Hsync Polarity.
+ *                           1  : High Active
+ *                           0  : Low Active
+ * @param[out]   pbPixelClk  Sensor Vsync Polarity.
+ *                           1  : Falling Edge
+ *                           0  : Rising Edig
+ * @return       None
+ *
+ * @details     This function is used to get sensor polarity.
+ */
+void CAP_GetSensorPolarity(PBOOL pbVsync, PBOOL pbHsync, PBOOL pbPixelClk)
+{
+    UINT32 u32Temp = inp32(REG_CAP_PAR);
+
+    *pbVsync = (u32Temp & VSP)  ? TRUE : FALSE;
+    *pbHsync = (u32Temp & HSP) ? TRUE : FALSE;
+    *pbPixelClk = (u32Temp & PCLKP) ? TRUE : FALSE;
+}
+
+/**
+ * @brief      Set data format and order.
+ *
+ * @param[in]   eInputOrder     Data order for input format.Including :
+ *                              - \ref eCAP_IN_UYVY = Y0 U0 Y1 V0
+ *                              - \ref eCAP_IN_YUYV = Y0 V0 Y1 U0
+ *                              - \ref eCAP_IN_VYUY = U0 Y0 V0 Y1
+ *                              - \ref eCAP_IN_YVYU = V0 Y0 U0 Y1
+ * @param[in]   eInputFormat    Input data format.Including :
+ *                              - \ref eCAP_IN_YUV422
+ *                              - \ref eCAP_IN_RGB565
+ * @param[in]   eOutputFormat   Sensor Vsync Polarity.Including :
+ *                              - \ref eCAP_OUT_YUV422 = YCbCr422
+ *                              - \ref eCAP_OUT_ONLY_Y = only output Y
+ *                              - \ref eCAP_OUT_RGB555 = rgb555
+ *                              - \ref eCAP_OUT_RGB565 = rgb565
+ * @return      None
+ *
+ * @details     This function is used to set data format and order.
+ */
+void CAP_SetDataFormatAndOrder(E_CAP_ORDER eInputOrder, E_CAP_IN_FORMAT eInputFormat, E_CAP_OUT_FORMAT eOutputFormat)
+{
+    outp32((REG_CAP_PAR), (inp32(REG_CAP_PAR) & ~(OUTFMT | INDATORD | INFMT))
+           | ((((eInputOrder << 2) & INDATORD)
+               | (eInputFormat & INFMT))
+              | ((eOutputFormat << 4) & OUTFMT)));
+} // DrvVideoIn_SetDataFormatAndOrder
+
+/**
+ * @brief      Get data format and order.
+ *
+ * @param[out]   peInputOrder    Data order for input format.Including :
+ *                               - \ref eCAP_IN_UYVY
+ *                               - \ref eCAP_IN_YUYV
+ *                               - \ref eCAP_IN_VYUY
+ *                               - \ref eCAP_IN_YVYU
+ * @param[out]   peInputFormat   Input data format.Including :
+ *                               - \ref eCAP_IN_YUV422
+ *                               - \ref eCAP_IN_RGB565
+ * @param[out]   peOutputFormat  Sensor Vsync Polarity.Including :
+ *                               - \ref eCAP_OUT_YUV422 = YCbCr422
+ *                               - \ref eCAP_OUT_ONLY_Y = only output Y
+ *                               - \ref eCAP_OUT_RGB555 = rgb555
+ *                               - \ref eCAP_OUT_RGB565 = rgb565
+ * @return      None
+ *
+ * @details     This function is used to get data format and order.
+ */
+void CAP_GetDataFormatAndOrder(E_CAP_ORDER *peInputOrder, E_CAP_IN_FORMAT *peInputFormat, E_CAP_OUT_FORMAT *peOutputFormat)
+{
+    UINT32 u32Temp = inp32(REG_CAP_PAR);
+
+    *peInputOrder = (E_CAP_ORDER)((u32Temp & INDATORD) >> 2);
+    *peInputFormat = (E_CAP_IN_FORMAT)(u32Temp & INFMT);
+    *peOutputFormat = (E_CAP_OUT_FORMAT)((u32Temp & OUTFMT) >> 4);
+}
+
+/**
+ * @brief      Set planar format.
+ *
+ * @param[in]   ePlanarFmt     Data order for input format.Including :
+ *                              - \ref eCAP_PLANAR_YUV422
+ *                              - \ref eCAP_PLANAR_YUV420
+ * @return      None
+ *
+ * @details     This function is used to set planar format.
+ */
+void CAP_SetPlanarFormat(E_CAP_PLANAR_FORMAT ePlanarFmt)
+{
+    switch (ePlanarFmt)
+    {
+    case eCAP_PLANAR_YUV422:
+        outp32((REG_CAP_PAR), (inp32(REG_CAP_PAR) & ~(PLNFMT)));
+        break;
+    case eCAP_PLANAR_YUV420:
+        outp32((REG_CAP_PAR), ((inp32(REG_CAP_PAR) | (PLNFMT))));
+        break;
+    }
+}
+
+/**
+ * @brief      Get planar format.
+ *
+ * @retval      - \ref eCAP_PLANAR_YUV422 : Planar format is YUV420.
+ * @retval      - \ref eCAP_PLANAR_YUV420 : Planar format is YUV422.
+ *
+ * @details     This function is used to get planar format.
+ */
+BOOL CAP_GetPlanarFormat(void)
+{
+    return ((inp32(REG_CAP_PAR) & PLNFMT) >> 7);
+}
+
+/**
+ * @brief      Set motion detection parameter.
+ *
+ * @param[in]   bEnable      Enable Motion Detection.Including :
+ *                           0  : Disable motion detection.
+ *                           1  : Enable motion detection.
+ * @param[in]   bBlockSize   Motion Detection Block Size.Including :
+ *                           0  : Block size is set to 16x16.
+ *                           1  : Block size is set to 8x8.
+ * @param[in]   bSaveMode    Motion Detection Save Mode.Including :
+ *                           0  : 1 bit DIFF + 7 Y Differential.
+ *                           1  : 1 bit DIFF only.
+ * @return      None
+ *
+ * @details     This function is used to set motion detection parameter.
+ */
+void CAP_SetMotionDet(BOOL bEnable, BOOL bBlockSize, BOOL bSaveMode)
+{
+    outp32(REG_CAP_MD, (inp32(REG_CAP_MD) & ~(MDSM | MDBS | MDEN)) |
+           (((bEnable ? MDEN : 0) | (bBlockSize ? MDBS : 0)) |
+            (bSaveMode ? MDSM : 0)));
+}
+
+/**
+ * @brief      Get motion detection parameter.
+ *
+ * @param[out]   pbEnable      Enable Motion Detection.Including :
+ *                             0  : Disable motion detection.
+ *                             1  : Enable motion detection.
+ * @param[out]   pbBlockSize   Motion Detection Block Size.Including :
+ *                             0  : Block size is set to 16x16.
+ *                             1  : Block size is set to 8x8.
+ * @param[out]   pbSaveMode    Motion Detection Save Mode.Including :
+ *                             0  : 1 bit DIFF + 7 Y Differential.
+ *                             1  : 1 bit DIFF only.
+ * @return       None
+ *
+ * @details      This function is used to get motion detection parameter.
+ */
+void CAP_GetMotionDet(PBOOL pbEnable, PBOOL pbBlockSize, PBOOL pbSaveMode)
+{
+    UINT32 u32RegData = inp32(REG_CAP_MD);
+    *pbEnable = (u32RegData & MDEN);
+    *pbBlockSize = (u32RegData & MDBS) >> 8;
+    *pbSaveMode = (u32RegData & MDSM) >> 9;
+}
+
+/**
+ * @brief      Set motion detection parameter externtion.
+ *
+ * @param[in]   u32DetFreq        Motion Detection frequency.Including :
+ *                                0 : Each frame
+ *                                1 : Every 2 frame
+ *                                2 : Every 3 frame
+ *                                3 : Every 4 frame
+ * @param[in]   u32Threshold      Motion detection threshold.It should be 0~31.
+ *
+ * @param[in]   u32OutBuffer      Motion Detection Output Address Register.(Word Alignment)
+ *
+ * @param[in]   u32LumBuffer      Motion Detection Temp Y Output Address Register.(Word Alignment)
+ *
+ * @return       None
+ *
+ * @details      This function is used to set motion detection parameter externtion.
+ */
+void CAP_SetMotionDetEx(UINT32 u32DetFreq, UINT32 u32Threshold, UINT32 u32OutBuffer, UINT32 u32LumBuffer)
+{
+    outp32(REG_CAP_MD, (inp32(REG_CAP_MD) & ~MDDF) | ((u32DetFreq << 10) & MDDF));
+    outp32(REG_CAP_MD, (inp32(REG_CAP_MD) & ~MDTHR) | ((u32Threshold << 16) & MDTHR));
+    outp32(REG_CAP_MDADDR, u32OutBuffer);
+    outp32(REG_CAP_MDYADDR, u32LumBuffer);
+}
+
+/**
+ * @brief      Get motion detection parameter externtion.
+ *
+ * @param[out]   pu32DetFreq        Motion Detection frequency.Including :
+ *                                  0 : Each frame
+ *                                  1 : Every 2 frame
+ *                                  2 : Every 3 frame
+ *                                  3 : Every 4 frame
+ * @param[out]   pu32Threshold      Motion detection threshold.It should be 0~31.
+ *
+ * @param[out]   pu32OutBuffer      Motion Detection Output Address Register.(Word Alignment)
+ *
+ * @param[out]   pu32LumBuffer      Motion Detection Temp Y Output Address Register.(Word Alignment)
+ *
+ * @return       None
+ *
+ * @details      This function is used to get motion detection parameter externtion.
+ */
+void CAP_GetMotionDetEx(PUINT32 pu32DetFreq, PUINT32 pu32Threshold, PUINT32 pu32OutBuffer, PUINT32 pu32LumBuffer)
+{
+    UINT32 u32RegData;
+    u32RegData = inp32(REG_CAP_MD);
+    *pu32DetFreq = u32RegData & MDDF;
+    *pu32Threshold = u32RegData & MDTHR;
+    *pu32OutBuffer = inp32(REG_CAP_MDADDR);
+    *pu32LumBuffer = inp32(REG_CAP_MDYADDR);
+}
+
+/**
+ * @brief      Set motion detection frequency.
+ *
+ * @param[in]  u32DetFreq        Motion Detection frequency.Including :
+ *                               0 : Each frame
+ *                               1 : Every 2 frame
+ *                               2 : Every 3 frame
+ *                               3 : Every 4 frame
+ * @return     None
+ *
+ * @details    This function is used to set motion detection frequency.
+ */
+void CAP_SetMotionDetFreq(UINT32 u32DetFreq)
+{
+    outp32(REG_CAP_MD, (inp32(REG_CAP_MD) & ~MDDF) |
+           ((u32DetFreq << 10) & MDDF));
+}
+
+/**
+ * @brief      Get motion detection frequency.
+ *
+ * @param[out]  pu32DetFreq      Motion Detection frequency.Including :
+ *                               0 : Each frame
+ *                               1 : Every 2 frame
+ *                               2 : Every 3 frame
+ *                               3 : Every 4 frame
+ * @return     None
+ *
+ * @details    This function is used to get motion detection frequency.
+ */
+void CAP_GetMotionDetFreq(PUINT32 pu32DetFreq)
+{
+    UINT32 u32RegData;
+    u32RegData = inp32(REG_CAP_MD);
+    *pu32DetFreq = u32RegData & MDDF;
+}
+
+/**
+ * @brief      Set One shutte or continuous mode.
+ *
+ * @param[in]  bIsOneSutterMode      Enable One shutte.Including :
+ *                                   1 :  Enable  One shutte mode.
+ *                                   0 : Disable One shutte mode.
+ * @return     None
+ *
+ * @details    This function is used to set one shutte or continuous mode.
+ *             Image capture interface automatically disable the capture
+ *             inteface after a frame bad been captured.
+ */
+void CAP_SetOperationMode(BOOL bIsOneSutterMode)
+{
+    outp32(REG_CAP_CTL, (inp32(REG_CAP_CTL) & ~SHUTTER) |
+           ((bIsOneSutterMode << 16) & SHUTTER));
+} // DrvVideoIn_SetOperationMode
+
+/**
+ * @brief      Get One shutte or continuous mode.
+ *
+ * @retval     1 : Disable one shutte mode
+ * @retval     0 : Enable one shutte mode
+ *
+ * @details    This function is used to get one shutte or continuous mode.
+ *             Image capture interface automatically disable the capture
+ *             inteface after a frame bad been captured.
+ */
+BOOL CAP_GetOperationMode(void)
+{
+    return ((inp32(REG_CAP_CTL) & SHUTTER) ? TRUE : FALSE);
+} // DrvVideoIn_GetOperationMode
+
+
+/**
+ * @brief        Get packet/planar processed data count.
+ *
+ * @param[in]    ePipe  Pipe type. Including :
+ *               - \ref eCAP_PACKET
+ *               - \ref eCAP_PLANAR
+ *
+ * @return       Get current packet/planar processed data count.
+ *
+ * @details    This function is used to get packet/planar processed data count.
+ */
+UINT32 CAP_GetProcessedDataCount(E_CAP_PIPE ePipe)
+{
+    if (ePipe == eCAP_PACKET)
+        return inp32(REG_CAP_CURADDRP);       /* Packet pipe */
+    else if (ePipe == eCAP_PLANAR)
+        return inp32(REG_CAP_CURADDRY);       /* Planar pipe */
+    else
+        return 0;
+}
+
+
+/**
+ * @brief        Set cropping window vertical/horizontal starting address.
+ *
+ * @param[in]    u32VerticalStart   Cropping window vertical starting address.
+ * @param[in]    u32HorizontalStart Cropping window horizontal starting address.
+ *
+ * @return       None.
+ *
+ * @details    This function is used to set cropping window vertical/horizontal starting address.
+ */
+void CAP_SetCropWinStartAddr(UINT32 u32VerticalStart, UINT32 u32HorizontalStart)
+{
+    outp32(REG_CAP_CWSP, (inp32(REG_CAP_CWSP) & ~(CWSADDRV | CWSADDRH)) //(Y|X)
+           | ((u32VerticalStart << 16)
+              | u32HorizontalStart));
+}
+
+
+/**
+ * @brief        Get cropping window vertical/horizontal starting address.
+ *
+ * @param[out]   pu32VerticalStart   Cropping window vertical starting address.
+ * @param[out]   pu32HorizontalStart Cropping window horizontal starting address.
+ *
+ * @return       None.
+ *
+ * @details    This function is used to get cropping window vertical/horizontal starting address.
+ */
+void CAP_GetCropWinStartAddr(PUINT32 pu32VerticalStart, PUINT32 pu32HorizontalStart)
+{
+    UINT32 u32Temp = inp32(REG_CAP_CWSP);
+
+    *pu32VerticalStart = (u32Temp & CWSADDRV) >> 16;
+    *pu32HorizontalStart = u32Temp & CWSADDRH;
+}
+
+/**
+ * @brief        Set cropping window size.
+ *
+ * @param[in]    u32Width   Cropping window width.
+ * @param[in]    u32Height  Cropping window heigh.
+ *
+ * @return       None.
+ *
+ * @details    This function is used to set cropping window size.
+ */
+void CAP_SetCropWinSize(UINT32 u32Height, UINT32 u32Width)
+{
+    outp32(REG_CAP_CWS, (inp32(REG_CAP_CWS) & ~(CWH | CWW))
+           | ((u32Height << 16)
+              | u32Width));
+}
+
+
+/**
+ * @brief        Get cropping window size.
+ *
+ * @param[out]   pu32Width   Cropping window width.
+ * @param[out]   pu32Height  Cropping window heigh.
+ *
+ * @return       None.
+ *
+ * @details    This function is used to get cropping window size.
+ */
+void CAP_GetCropWinSize(PUINT32 pu32Height, PUINT32 pu32Width)
+{
+    UINT32 u32Temp = inp32(REG_CAP_CWS);
+
+    *pu32Height = (u32Temp & CWH) >> 16;
+    *pu32Width = u32Temp & CWW;
+}
+
+/**
+ * @brief       Set packet/planar scaling vertical factor.
+ *
+ * @param[in]   ePipe   Pipe type.Including.
+ *                      - \ref eCAP_PACKET.
+ *                      - \ref eCAP_PLANAR.
+ * @param[in]   u16Numerator  Scaling Vertical Factor N.
+ * @param[in]   u16Denominator  Scaling Vertical Factor M.
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to set packet/planar scaling vertical factor.
+ *              The output image width will be equal to the image width * N/M.
+ *              Note: The value of N must be equal to or less than M
+ */
+INT32 CAP_SetVerticalScaleFactor(E_CAP_PIPE ePipe, UINT16 u16Numerator, UINT16 u16Denominator)
+{
+    UINT8 u8NumeratorL = u16Numerator & 0xFF, u8NumeratorH = u16Numerator >> 8;
+    UINT8 u8DenominatorL = u16Denominator & 0xFF, u8DenominatorH = u16Denominator >> 8;
+    if (ePipe == eCAP_PACKET)
+    {
+        outp32(REG_CAP_PKTSL, (inp32(REG_CAP_PKTSL) & ~(PKTSVNL | PKTSVML))
+               | ((u8NumeratorL << 24)
+                  | (u8DenominatorL << 16)));
+        outp32(REG_CAP_PKTSM, (inp32(REG_CAP_PKTSM) & ~(PKTSHMH | PKTSVMH))
+               | ((u8NumeratorH << 24)
+                  | (u8DenominatorH << 16)));
+    }
+    else if (ePipe == eCAP_PLANAR)
+    {
+        outp32(REG_CAP_PLNSL, (inp32(REG_CAP_PLNSL) & ~(PKTSVNL | PKTSVML))
+               | ((u8NumeratorL << 24)
+                  | (u8DenominatorL << 16)));
+        outp32(REG_CAP_PLNSM, (inp32(REG_CAP_PLNSM) & ~(PKTSHMH | PKTSVMH))
+               | ((u8NumeratorH << 24)
+                  | (u8DenominatorH << 16)));
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    return Successful;
+}
+
+/**
+ * @brief       Get packet/planar scaling vertical factor.
+ *
+ * @param[in]   ePipe   Pipe type.Including.
+ *                      - \ref eCAP_PACKET.
+ *                      - \ref eCAP_PLANAR.
+ * @param[out]  pu16Numerator  Scaling Vertical Factor N.
+ * @param[out]  pu16Denominator  Scaling Vertical Factor M.
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to get packet/planar scaling vertical factor.
+ *              The output image width will be equal to the image width * N/M.
+ *              Note: The value of N must be equal to or less than M
+ */
+INT32 DrvCAP_GetVerticalScaleFactor(E_CAP_PIPE ePipe, PUINT16 pu16Numerator, PUINT16 pu16Denominator)
+{
+    UINT32 u32Temp1, u32Temp2;
+    if (ePipe == eCAP_PACKET)
+    {
+        u32Temp1 = inp32(REG_CAP_PKTSL);
+        u32Temp2 = inp32(REG_CAP_PKTSM);
+    }
+    else if (ePipe == eCAP_PLANAR)
+    {
+        u32Temp1 = inp32(REG_CAP_PLNSL);
+        u32Temp2 = inp32(REG_CAP_PLNSM);
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    *pu16Numerator = ((u32Temp1 & PKTSVNL) >> 24) | (((u32Temp2 & PKTSHMH) >> 24) << 8);
+    *pu16Denominator = (u32Temp1 & PKTSVML) >> 16 | (((u32Temp2 & PKTSVMH) >> 16) << 8);
+    return Successful;
+}
+
+/**
+ * @brief       Set packet/planar scaling horizontal factor.
+ *
+ * @param[in]   bPipe   Pipe type.Including.
+ *                      - \ref eCAP_PACKET.
+ *                      - \ref eCAP_PLANAR.
+ * @param[in]   u16Numerator  Scaling Horizontal Factor N.
+ * @param[in]   u16Denominator  Scaling Horizontal Factor M.
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to set packet/planar scaling horizontal factor.
+ *              The output image width will be equal to the image width * N/M.
+ *              Note: The value of N must be equal to or less than M
+ */
+INT32 CAP_SetHorizontalScaleFactor(E_CAP_PIPE bPipe, UINT16 u16Numerator, UINT16 u16Denominator)
+{
+    UINT8 u8NumeratorL = u16Numerator & 0xFF, u8NumeratorH = u16Numerator >> 8;
+    UINT8 u8DenominatorL = u16Denominator & 0xFF, u8DenominatorH = u16Denominator >> 8;
+    if (bPipe == eCAP_PACKET)
+    {
+        outp32(REG_CAP_PKTSL, (inp32(REG_CAP_PKTSL) & ~(PKTSHNL | PKTSHML))
+               | ((u8NumeratorL << 8)
+                  | u8DenominatorL));
+        outp32(REG_CAP_PKTSM, (inp32(REG_CAP_PKTSM) & ~(PKTSHNH | PKTSHMH))
+               | ((u8NumeratorH << 8)
+                  | u8DenominatorH));
+    }
+    else  if (bPipe == eCAP_PLANAR)
+    {
+        outp32(REG_CAP_PLNSL, (inp32(REG_CAP_PLNSL) & ~(PKTSHNL | PKTSHML))
+               | ((u8NumeratorL << 8)
+                  | u8DenominatorL));
+        outp32(REG_CAP_PLNSM, (inp32(REG_CAP_PLNSM) & ~(PKTSHNH | PKTSHMH))
+               | ((u8NumeratorH << 8)
+                  | u8DenominatorH));
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    return Successful;
+}
+
+/**
+ * @brief       Get packet/planar scaling horizontal factor.
+ *
+ * @param[in]   bPipe   Pipe type.Including.
+ *                      - \ref eCAP_PACKET.
+ *                      - \ref eCAP_PLANAR.
+ * @param[out]  pu16Numerator  Scaling Horizontal Factor N.
+ * @param[out]  pu16Denominator  Scaling Horizontal Factor M.
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details     This function is used to get packet/planar scaling horizontal factor.
+ *              The output image width will be equal to the image width * N/M.
+ *              Note: The value of N must be equal to or less than M.
+ */
+INT32 CAP_GetHorizontalScaleFactor(E_CAP_PIPE bPipe, PUINT16 pu16Numerator, PUINT16 pu16Denominator)
+{
+    UINT32 u32Temp1, u32Temp2;
+    if (bPipe == eCAP_PACKET)
+    {
+        u32Temp1 = inp32(REG_CAP_PKTSL);
+        u32Temp2 = inp32(REG_CAP_PKTSM);
+    }
+    else  if (bPipe == eCAP_PLANAR)
+    {
+        u32Temp1 = inp32(REG_CAP_PLNSL);
+        u32Temp2 = inp32(REG_CAP_PLNSM);
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    *pu16Numerator = ((u32Temp1 & PKTSHNL) >> 8) | (u32Temp2 & PKTSHNH);
+    *pu16Denominator = (u32Temp1 & PKTSHML) | ((u32Temp2 & PKTSHMH) << 8);
+    return Successful;
+}
+
+/**
+ * @brief      Set scaling frame rate factor.
+ *
+ * @param[in]  u8Numerator  Scaling Frame Rate Factor N.
+ * @param[in]  u8Denominator  Scaling Frame Rate Factor M.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to set scaling frame rate factor..
+ *             The output image frame rate will be equal to input image frame rate * (N/M).
+ *             Note: The value of N must be equal to or less than M.
+ */
+void DrvCAP_SetFrameRateScaleFactor(UINT8 u8Numerator, UINT8 u8Denominator)
+{
+    outp32(REG_CAP_FRCTL, (inp32(REG_CAP_FRCTL) & ~(FRN | FRM))
+           | (((u8Numerator << 8) & FRN)
+              | (u8Denominator & FRM)));
+} // DrvVideoIn_SetFrameRateScaleFactor
+
+/**
+ * @brief      Get scaling frame rate factor.
+ *
+ * @param[out] pu8Numerator  Scaling Frame Rate Factor N.
+ * @param[out] pu8Denominator  Scaling Frame Rate Factor M.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to get scaling frame rate factor..
+ *             The output image frame rate will be equal to input image frame rate * (N/M).
+ *             Note: The value of N must be equal to or less than M.
+ */
+void DrvCAP_GetFrameRateScaleFactor(PUINT8 pu8Numerator, PUINT8 pu8Denominator)
+{
+    UINT32 u32Temp = inp32(REG_CAP_FRCTL);
+
+    *pu8Numerator = (u32Temp & FRN) >> 8;
+    *pu8Denominator = u32Temp & FRM;
+}
+
+/**
+ * @brief      Set address match
+ *
+ * @param[in]  u32AddressMatch  Compare Memory Base Address.It should be 0~0xFFFFFFFF.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to set compare memory base address.
+ */
+void DrvCAP_SetAddressMatch(UINT32 u32AddressMatch)
+{
+    outp32(REG_CAP_CMPADDR, u32AddressMatch);
+}
+
+/**
+ * @brief      Get address match
+ *
+ * @param[out] pu32AddressMatch  Compare Memory Base Address.It should be 0~0xFFFFFFFF.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to get compare memory base address.
+ */
+void CAP_GetAddressMatch(PUINT32 pu32AddressMatch)
+{
+    *pu32AddressMatch = inp32(REG_CAP_CMPADDR);
+}
+
+/**
+ * @brief      Set frame output pixel stride width.
+ *
+ * @param[in] u32PacketStride  Packet frame output pixel stride width.It should be 0~0x3FFF.
+ * @param[in] u32PlanarStride  Planar frame output pixel stride width.It should be 0~0x3FFF.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to set frame output pixel stride width.
+ */
+void CAP_SetStride(UINT32 u32PacketStride, UINT32 u32PlanarStride)
+{
+    outp32(REG_CAP_STRIDE, ((u32PlanarStride << 16) & PLNSTRIDE) |
+           (u32PacketStride & PKTSTRIDE));
+}
+
+/**
+ * @brief      Get frame output pixel stride width.
+ *
+ * @param[out] pu32PacketStride  Packet frame output pixel stride width.It should be 0~0x3FFF.
+ * @param[out] pu32PlanarStride  Planar frame output pixel stride width.It should be 0~0x3FFF.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to get frame output pixel stride width.
+ */
+void CAP_GetStride(PUINT32  pu32PacketStride, PUINT32 pu32PlanarStride)
+{
+    UINT32 u32Tmp =  inp32(REG_CAP_STRIDE);
+    *pu32PlanarStride = (u32Tmp & PLNSTRIDE) >> 16;
+    *pu32PacketStride = u32Tmp & PKTSTRIDE;
+}
+
+/**
+ * @brief      Set system memory packet/planar base address.
+ *
+ * @param[in] ePipe             Pipe type.Including:
+ *                              - \ref eCAP_PACKET
+ *                              - \ref eCAP_PLANAR
+ *
+ * @param[in] eBuf              Packet/Planar buffer address.
+ *                              - \ref eCAP_BUF0 :
+ *                                     Packet : Packet base address 0
+ *                                     Planar : Planar Y base address
+ *                              - \ref eCAP_BUF1
+ *                                     Packet : Packet base address 1
+ *                                     Planar : Planar U base address
+ *                              - \ref eCAP_BUF2
+ *                                     Packet : None.
+ *                                     Planar : Planar V base address
+ *
+ * @param[in] u32BaseStartAddr  System Memory Base Address.It should be 0~0xFFFFFFFF.
+ *
+ * @retval      0 Success
+ * @retval      <0 Error code
+ *
+ * @details    This function is used to set system memory packet/planar base address.
+ */
+INT32 CAP_SetBaseStartAddress(E_CAP_PIPE ePipe, E_CAP_BUFFER eBuf, UINT32 u32BaseStartAddr)
+{
+    if (ePipe == eCAP_PACKET)
+    {
+        if (eBuf > eCAP_BUF1)
+            return E_CAP_INVALID_BUF;
+        outp32(REG_CAP_PKTBA0 + eBuf * 4, u32BaseStartAddr);
+    }
+    else if (ePipe == eCAP_PLANAR)
+    {
+        if (eBuf > eCAP_BUF2)
+            return E_CAP_INVALID_BUF;
+        outp32(REG_CAP_YBA + eBuf * 4, u32BaseStartAddr);
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    return Successful;
+}
+
+/**
+ * @brief      Get system memory packet/planar base address.
+ *
+ * @param[in]  ePipe              Pipe type.Including:
+ *                                - \ref eCAP_PACKET
+ *                                - \ref eCAP_PLANAR
+ *
+ * @param[in]  eBuf               Packet/Planar buffer address.
+ *                                - \ref eCAP_BUF0 :
+ *                                     Packet : Packet base address 0
+ *                                     Planar : Planar Y base address
+ *                                - \ref eCAP_BUF1
+ *                                     Packet : Packet base address 1
+ *                                     Planar : Planar U base address
+ *                                - \ref eCAP_BUF2
+ *                                     Packet : None.
+ *                                     Planar : Planar V base address
+ *
+ * @param[out] pu32BaseStartAddr  System Memory Base Address.It should be 0~0xFFFFFFFF.
+ *
+ * @retval     0 Success
+ * @retval     <0 Error code
+ *
+ * @details    This function is used to get system memory packet/planar base address.
+ */
+INT32 CAP_GetBaseStartAddress(E_CAP_PIPE ePipe, E_CAP_BUFFER eBuf, PUINT32 pu32BaseStartAddr)
+{
+    if (ePipe == eCAP_PACKET)
+    {
+        if (eBuf > eCAP_BUF1)
+            return E_CAP_INVALID_BUF;
+        *pu32BaseStartAddr = inp32(REG_CAP_PKTBA0 + eBuf * 4);
+    }
+    else if (ePipe == eCAP_PLANAR)
+    {
+        if (eBuf > eCAP_BUF2)
+            return E_CAP_INVALID_BUF;
+        *pu32BaseStartAddr = inp32(REG_CAP_YBA + eBuf * 4);
+    }
+    else
+        return E_CAP_INVALID_PIPE;
+    return Successful;
+}
+
+/**
+ * @brief       Set standard CCIR656.
+ *
+ * @param[in]   bIsStandard      Standard CCIR656.
+ *                               - 1 : Standard CCIR656 mode.
+ *                               - 0 : Non-Standard CCIR656 mode. (OV7725 or Hynix 702)
+ * @return      None.
+ *
+ * @details    This function is used to set standard CCIR65/non-standard CCIR65.
+ */
+void CAP_SetStandardCCIR656(BOOL bIsStandard)
+{
+    if (bIsStandard == TRUE)
+        outp32(REG_CAP_PAR, inp32(REG_CAP_PAR) & ~FBB);   // Standard
+    else
+        outp32(REG_CAP_PAR, inp32(REG_CAP_PAR) | FBB);      // Non-Standard
+}
+
+/**
+ * @brief      Set color effect
+ *
+ * @param[in]  eColorMode  Available as following.
+ *                         - \ref eCAP_CEF_NORMAL : Normal Color.
+ *                         - \ref eCAP_CEF_SEPIA : Sepia effect,
+ *                         corresponding U,V component value is set at register - \ref REG_CAP_SEPIA.
+ *                         - \ref eCAP_CEF_NEGATIVE  : Negative picture.
+ *                         - \ref eCAP_CEF_POSTERIZE : Posterize image,
+ *                         the Y, U, V components posterizing factor are set at register - \ref REG_CAP_POSTERIZE.
+ *
+ * @retval     0 Success
+ * @retval     <0 Error code
+ *
+ * @details    This function is used to set color effect.
+ */
+INT32 CAP_SetColorEffect(E_CAP_CEF eColorMode)
+{
+    if (eColorMode > eCAP_CEF_POSTERIZE)
+        return E_CAP_INVALID_COLOR_MODE;
+    outp32(REG_CAP_PAR, (inp32(REG_CAP_PAR) & ~COLORCTL) |
+           (eColorMode << 11));
+    return Successful;
+}
+
+/**
+ * @brief      Get color effect
+ *
+ * @param[out] peColorMode  Available as following.
+ *                         - \ref eCAP_CEF_NORMAL : Normal Color.
+ *                         - \ref eCAP_CEF_SEPIA : Sepia effect,
+ *                         corresponding U,V component value is set at register - \ref REG_CAP_SEPIA.
+ *                         - \ref eCAP_CEF_NEGATIVE  : Negative picture.
+ *                         - \ref eCAP_CEF_POSTERIZE : Posterize image,
+ *                         the Y, U, V components posterizing factor are set at register - \ref REG_CAP_POSTERIZE.
+ *
+ * @return     None.
+ *
+ * @details    This function is used to get color effect.
+ */
+void DrvCAP_GetColorEffect(E_CAP_CEF   *peColorMode)
+{
+    UINT32 u32Tmp = inp32(REG_CAP_PAR);
+    *peColorMode = (E_CAP_CEF)((u32Tmp & COLORCTL) >> 11);
+}
+
+/**
+ * @brief      Set color effect parameter
+ *
+ * @param[in]  u8YComp  The constant Y component.If eColorMode is set to
+ *                      eCAP_CEF_SEPIA : the constant Y component in - \ref REG_CAP_SEPIA.
+ *                      eCAP_CEF_POSTERIZE : the constant Y component in - \ref REG_CAP_POSTERIZE.
+ * @param[in]  u8UComp  The constant U component.
+ *                      eCAP_CEF_SEPIA : the constant U component in - \ref REG_CAP_SEPIA.
+ *                      eCAP_CEF_POSTERIZE : the constant U component in - \ref REG_CAP_POSTERIZE.
+ * @param[in]  u8VComp  The constant V component.
+ *                      eCAP_CEF_SEPIA : the constant V component in - \ref REG_CAP_SEPIA.
+ *                      eCAP_CEF_POSTERIZE : the constant V component in - \ref REG_CAP_POSTERIZE.
+ * @retval     0 Success
+ * @retval     <0 Error code
+ *
+ * @details    This function is used to set color effect parameter.
+ */
+INT32 CAP_SetColorEffectParameter(UINT8 u8YComp, UINT8 u8UComp, UINT8 u8VComp)
+{
+    UINT32 u32Tmp = inp32(REG_CAP_PAR);
+    UINT32 u32ColorMode = (u32Tmp & COLORCTL) >> 11;
+    if (u32ColorMode == eCAP_CEF_SEPIA)
+    {
+        outp32(REG_CAP_SEPIA, (((UINT32)u8UComp << 8) | u8VComp));
+    }
+    else if (u32ColorMode == eCAP_CEF_POSTERIZE)
+    {
+        outp32(REG_CAP_POSTERIZE, (((UINT32)u8YComp << 16) | ((UINT32)u8UComp << 8) | u8VComp));
+    }
+    else
+    {
+        return E_CAP_WRONG_COLOR_PARAMETER;
+    }
+    return Successful;
+}
+
+/**
+ * @brief      Get color effect parameter
+ *
+ * @param[out] pu8YComp  The constant Y component.If eColorMode is set to
+ *                       eCAP_CEF_SEPIA : the constant Y component in - \ref REG_CAP_SEPIA.
+ *                       eCAP_CEF_POSTERIZE : the constant Y component in - \ref REG_CAP_POSTERIZE.
+ * @param[out] pu8UComp  The constant U component.
+ *                       eCAP_CEF_SEPIA : the constant U component in - \ref REG_CAP_SEPIA.
+ *                       eCAP_CEF_POSTERIZE : the constant U component in - \ref REG_CAP_POSTERIZE.
+ * @param[out] pu8VComp  The constant V component.
+ *                       eCAP_CEF_SEPIA : the constant V component in - \ref REG_CAP_SEPIA.
+ *                       eCAP_CEF_POSTERIZE : the constant V component in - \ref REG_CAP_POSTERIZE.
+ * @retval     0 Success
+ * @retval     <0 Error code
+ *
+ * @details    This function is used to get color effect parameter.
+ */
+INT32 CAP_GetColorEffectParameter(PUINT8 pu8YComp, PUINT8 pu8UComp, PUINT8 pu8VComp)
+{
+    UINT32 u32Tmp = inp32(REG_CAP_PAR);
+    UINT32 u32ColorMode = (u32Tmp & COLORCTL) >> 11;
+    if (u32ColorMode == eCAP_CEF_SEPIA)
+    {
+        u32Tmp = inp32(REG_CAP_SEPIA);
+        *pu8UComp = (u32Tmp & 0xFF00) >> 8;
+        *pu8VComp = u32Tmp & 0xFF;
+    }
+    else if (u32ColorMode == eCAP_CEF_POSTERIZE)
+    {
+        u32Tmp = inp32(REG_CAP_POSTERIZE);
+        *pu8YComp = (u32Tmp & 0xFF0000) >> 16;
+        *pu8UComp = (u32Tmp & 0xFF00) >> 8;
+        *pu8VComp = u32Tmp & 0xFF;
+    }
+    else
+    {
+        return E_CAP_WRONG_COLOR_PARAMETER;
+    }
+    return Successful;
+}
+
+/// @cond HIDDEN_SYMBOLS
+CAPDEV_T CAP =
+{
+    CAP_Init,                         // void  (*Init)(BOOL bIsEnableSnrClock, E_CAP_SNR_SRC eSnrSrc, UINT32 u32SensorFreqKHz, E_CAP_DEV_TYPE eDevType):
+    CAP_Open,                         // INT32 (*Open)(UINT32 u32SensorFreqKHz);
+    CAP_Close,                        // void  (*Close)(void);
+    CAP_SetPipeEnable,                // void  (*SetPipeEnable)(BOOL bEngEnable, E_CAP_PIPE ePipeEnable);
+    CAP_SetPlanarFormat,              // void  (*SetPlanarFormat)(E_CAP_PLANAR_FORMAT ePlanarFmt);
+    CAP_SetCropWinSize,               // void  (*SetCropWinSize)(UINT32 u32height, UINT32 u32width);
+    CAP_SetCropWinStartAddr,          // void  (*SetCropWinStartAddr)(UINT32 u32VerticalStart, UINT32 u32HorizontalStart);
+    CAP_SetStride,                    // void  (*SetStride)(UINT32 u16packetstride, UINT32 u32planarstride);
+    CAP_GetStride,                    // void  (*GetStride)(PUINT32 pu32PacketStride, PUINT32 pu32PlanarStride);
+    CAP_EnableInt,                    // INT32 (*EnableInt)(E_CAP_INT_TYPE eIntType);
+    CAP_DisableInt,                   // INT32 (*DisableInt)(E_CAP_INT_TYPE eIntType);
+    CAP_InstallCallback,              // INT32 (*InstallCallback)(E_CAP_INT_TYPE eIntType, PFN_CAP_CALLBACK pfnCallback, PFN_CAP_CALLBACK *pfnOldCallback);
+    CAP_SetBaseStartAddress,          // INT32 (*SetBaseStartAddress(E_CAP_PIPE ePipe, E_CAP_BUFFER eBuf, UINT32 u32BaseStartAddr);
+    CAP_SetOperationMode,             // void  (*SetOperationMode(BOOL bIsOneSutterMode);
+    CAP_GetOperationMode,             // BOOL  (*GetOperationMode)(void);
+    CAP_SetPacketFrameBufferControl,  // void  (*videoIn1_SetPacketFrameBufferControl)(BOOL bFrameSwitch, BOOL bFrameBufferSel);
+    CAP_SetSensorPolarity,            // void  (*videoIn1_SetSensorPolarity)(BOOL bVsync, BOOL bHsync,  BOOL bPixelClk);
+    CAP_SetColorEffectParameter,      // INT32 (*SetColorEffectParameter)(UINT8 u8YComp, UINT8 u8UComp, UINT8 u8VComp);
+    CAP_SetDataFormatAndOrder,        // void  (*SetDataFormatAndOrder)(E_CAP_ORDER eInputOrder, E_CAP_IN_FORMAT eInputFormat, E_CAP_OUT_FORMAT eOutputFormat)
+    CAP_SetMotionDet,                 // void  (*SetMotionDet)(BOOL bEnable, BOOL bBlockSize,BOOL bSaveMode);
+    CAP_SetMotionDetEx,               // void  (*SetMotionDetEx)(UINT32 u32Threshold, UINT32 u32OutBuffer, UINT32 u32LumBuffer);
+    CAP_SetStandardCCIR656,           // void  (*SetStandardCcir656)(BOOL);
+    CAP_SetShadowRegister             // void  (*SetShadowRegister)(void);
+};
+/// @endcond HIDDEN_SYMBOLS
+
+/*@}*/ /* end of group N9H30_CAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_CAP_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_crypto.c

@@ -0,0 +1,394 @@
+/**************************************************************************//**
+ * @file     crypto.c
+ * @version  V1.10
+ * $Revision: 3 $
+ * $Date: 15/06/12 9:42a $
+ * @brief  Cryptographic Accelerator driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_crypto.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+static uint32_t g_AES_CTL[4];
+static uint32_t g_TDES_CTL[4];
+
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+  * @brief  Open PRNG function
+  * @param[in]  u32KeySize is PRNG key size, including:
+  *         - \ref PRNG_KEY_SIZE_64
+  *         - \ref PRNG_KEY_SIZE_128
+  *         - \ref PRNG_KEY_SIZE_192
+  *         - \ref PRNG_KEY_SIZE_256
+  * @param[in]  u32SeedReload is PRNG seed reload or not, including:
+  *         - \ref PRNG_SEED_CONT
+  *         - \ref PRNG_SEED_RELOAD
+  * @param[in]  u32Seed  The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
+  * @return None
+  */
+void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
+{
+    if (u32SeedReload)
+        CRPT->PRNG_SEED = u32Seed;
+
+    CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                     (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
+}
+
+/**
+  * @brief  Start to generate one PRNG key.
+  * @return None
+  */
+void PRNG_Start(void)
+{
+    CRPT->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
+}
+
+/**
+  * @brief  Read the PRNG key.
+  * @param[out]  u32RandKey  The key buffer to store newly generated PRNG key.
+  * @return None
+  */
+void PRNG_Read(uint32_t u32RandKey[])
+{
+    uint32_t  i, wcnt;
+
+    wcnt = (((CRPT->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;
+
+    for (i = 0U; i < wcnt; i++)
+    {
+        u32RandKey[i] = CRPT->PRNG_KEY[i];
+    }
+
+    CRPT->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;
+}
+
+
+/**
+  * @brief  Open AES encrypt/decrypt function.
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32EncDec    1: AES encode;  0: AES decode
+  * @param[in]  u32OpMode    AES operation mode, including:
+  *         - \ref AES_MODE_ECB
+  *         - \ref AES_MODE_CBC
+  *         - \ref AES_MODE_CFB
+  *         - \ref AES_MODE_OFB
+  *         - \ref AES_MODE_CTR
+  *         - \ref AES_MODE_CBC_CS1
+  *         - \ref AES_MODE_CBC_CS2
+  *         - \ref AES_MODE_CBC_CS3
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @param[in]  u32SwapType is AES input/output data swap control, including:
+  *         - \ref AES_NO_SWAP
+  *         - \ref AES_OUT_SWAP
+  *         - \ref AES_IN_SWAP
+  *         - \ref AES_IN_OUT_SWAP
+  * @return None
+  */
+void AES_Open(uint32_t u32Channel, uint32_t u32EncDec,
+              uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
+{
+    CRPT->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) |
+                    (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |
+                    (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
+                    (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
+                    (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
+    g_AES_CTL[u32Channel] = CRPT->AES_CTL;
+}
+
+/**
+  * @brief  Start AES encrypt/decrypt
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  u32DMAMode  AES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last AES encrypt/decrypt of a series of AES_Start.
+  * @return None
+  */
+void AES_Start(int32_t u32Channel, uint32_t u32DMAMode)
+{
+    CRPT->AES_CTL = g_AES_CTL[u32Channel];
+    CRPT->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set AES keys
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32Keys    An word array contains AES keys.
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @return None
+  */
+void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
+{
+    int       i, wcnt;
+    uint32_t  *key_ptr;
+
+    key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3C));
+    wcnt = 4 + u32KeySize * 2;
+    for (i = 0; i < wcnt; i++, key_ptr++)
+        *key_ptr = au32Keys[i];
+}
+
+/**
+  * @brief  Set AES initial vectors
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32IV      A four entry word array contains AES initial vectors.
+  * @return None
+  */
+void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[])
+{
+    int       i;
+    uint32_t  *key_ptr;
+
+    key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3C));
+    for (i = 0; i < 4; i++, key_ptr++)
+        *key_ptr = au32IV[i];
+}
+
+/**
+  * @brief  Set AES DMA transfer configuration.
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32SrcAddr   AES DMA source address
+  * @param[in]  u32DstAddr   AES DMA destination address
+  * @param[in]  u32TransCnt  AES DMA transfer byte count
+  * @return None
+  */
+void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
+                        uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+    *(uint32_t *)((uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3C)) = u32SrcAddr;
+    *(uint32_t *)((uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3C)) = u32DstAddr;
+    *(uint32_t *)((uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3C)) = u32TransCnt;
+}
+
+/**
+  * @brief  Open TDES encrypt/decrypt function.
+  * @param[in]  u32Channel   TDES channel. Must be 0~3.
+  * @param[in]  u32EncDec    1: TDES encode; 0: TDES decode
+  * @param[in]  u32OpMode    TDES operation mode, including:
+  *         - \ref TDES_MODE_ECB
+  *         - \ref TDES_MODE_CBC
+  *         - \ref TDES_MODE_CFB
+  *         - \ref TDES_MODE_OFB
+  *         - \ref TDES_MODE_CTR
+  * @param[in]  u32SwapType is TDES input/output data swap control and word swap control, including:
+  *         - \ref TDES_NO_SWAP
+  *         - \ref TDES_WHL_SWAP
+  *         - \ref TDES_OUT_SWAP
+  *         - \ref TDES_OUT_WHL_SWAP
+  *         - \ref TDES_IN_SWAP
+  *         - \ref TDES_IN_WHL_SWAP
+  *         - \ref TDES_IN_OUT_SWAP
+  *         - \ref TDES_IN_OUT_WHL_SWAP
+  * @return None
+  */
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key,
+               uint32_t u32OpMode, uint32_t u32SwapType)
+{
+    g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |
+                             (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |
+                             u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
+    if (Is3DES)
+    {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk;
+    }
+    if (Is3Key)
+    {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk;
+    }
+}
+
+/**
+  * @brief  Start TDES encrypt/decrypt
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  u32DMAMode  TDES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop TDES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous TDES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last TDES encrypt/decrypt of a series of TDES_Start.
+  * @return None
+  */
+void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode)
+{
+    g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos);
+    CRPT->TDES_CTL = g_TDES_CTL[u32Channel];
+}
+
+/**
+  * @brief  Set TDES keys
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  au8Keys     The TDES keys.
+  * @return None
+  */
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2])
+{
+    int         i;
+    uint32_t    *pu32TKey;
+
+    pu32TKey = (uint32_t *)((uint32_t)&CRPT->TDES0_KEY1H + (0x40 * u32Channel));
+    for (i = 0; i < 3; i++)
+    {
+        *pu32TKey = au32Keys[i][0];   /* TDESn_KEYxH */
+        pu32TKey++;
+        *pu32TKey = au32Keys[i][1];   /* TDESn_KEYxL */
+        pu32TKey++;
+    }
+}
+
+/**
+  * @brief  Set TDES initial vectors
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  u32IVH      TDES initial vector high word.
+  * @param[in]  u32IVL      TDES initial vector low word.
+  * @return None
+  */
+void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)
+{
+    *(uint32_t *)((uint32_t)&CRPT->TDES0_IVH + 0x40 * u32Channel) = u32IVH;
+    *(uint32_t *)((uint32_t)&CRPT->TDES0_IVL + 0x40 * u32Channel) = u32IVL;
+}
+
+/**
+  * @brief  Set TDES DMA transfer configuration.
+  * @param[in]  u32Channel   TDES channel. Must be 0~3.
+  * @param[in]  u32SrcAddr   TDES DMA source address
+  * @param[in]  u32DstAddr   TDES DMA destination address
+  * @param[in]  u32TransCnt  TDES DMA transfer byte count
+  * @return None
+  */
+void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
+                         uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+    *(uint32_t *)((uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40)) = u32SrcAddr;
+    *(uint32_t *)((uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40)) = u32DstAddr;
+    *(uint32_t *)((uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40)) = u32TransCnt;
+}
+
+/**
+  * @brief  Open SHA encrypt function.
+  * @param[in]  u32OpMode   SHA operation mode, including:
+  *         - \ref SHA_MODE_SHA1
+  *         - \ref SHA_MODE_SHA224
+  *         - \ref SHA_MODE_SHA256
+  *         - \ref SHA_MODE_SHA384
+  *         - \ref SHA_MODE_SHA512
+  * @param[in]  u32SwapType is SHA input/output data swap control, including:
+  *         - \ref SHA_NO_SWAP
+  *         - \ref SHA_OUT_SWAP
+  *         - \ref SHA_IN_SWAP
+  *         - \ref SHA_IN_OUT_SWAP
+  * @param[in]  hmac_key_len  The length of HMAC key if HMAC is employed.
+  *             If HMAC is not used, just give hmac_key_len a zero value.
+  * @return None
+  */
+void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType, int hmac_key_len)
+{
+    CRPT->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) |
+                     (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos);
+
+    if (hmac_key_len > 0)
+    {
+        CRPT->HMAC_KEYCNT = hmac_key_len;
+        CRPT->HMAC_CTL |= CRPT_HMAC_CTL_HMACEN_Msk;
+    }
+}
+
+
+/**
+  * @brief  Start SHA encrypt
+  * @param[in]  u32DMAMode  TDES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop SHA encrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous SHA encrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last SHA encrypt of a series of SHA_Start.
+  * @return None
+  */
+void SHA_Start(uint32_t u32DMAMode)
+{
+    CRPT->HMAC_CTL &= ~(0x7 << CRPT_HMAC_CTL_DMALAST_Pos);
+    CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set SHA DMA transfer
+  * @param[in]  u32SrcAddr   SHA DMA source address
+  * @param[in]  u32TransCnt  SHA DMA transfer byte count
+  * @return None
+  */
+void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt)
+{
+    CRPT->HMAC_SADDR = u32SrcAddr;
+    CRPT->HMAC_DMACNT = u32TransCnt;
+}
+
+/**
+  * @brief  Read the SHA digest.
+  * @param[out]  u32Digest  The SHA encrypt output digest.
+  * @return None
+  */
+void SHA_Read(uint32_t u32Digest[])
+{
+    uint32_t  i, wcnt;
+
+    i = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;
+    if (i == SHA_MODE_SHA1)
+    {
+        wcnt = 5UL;
+    }
+    else if (i == SHA_MODE_SHA224)
+    {
+        wcnt = 7UL;
+    }
+    else if (i == SHA_MODE_SHA256)
+    {
+        wcnt = 8UL;
+    }
+    else if (i == SHA_MODE_SHA384)
+    {
+        wcnt = 12UL;
+    }
+    else
+    {
+        /* SHA_MODE_SHA512 */
+        wcnt = 16UL;
+    }
+
+    for (i = 0; i < wcnt; i++)
+        u32Digest[i] = *(uint32_t *)((uint32_t) & (CRPT->HMAC_DGST0) + (i * 4));
+}
+
+
+/*@}*/ /* end of group N9H30_CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_CRYPTO_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_emac.c

@@ -0,0 +1,1158 @@
+/**************************************************************************//**
+ * @file     emac.c
+ * @version  V1.00
+ * @brief    M480 EMAC driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <string.h>
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EMAC_Driver EMAC Driver
+  @{
+*/
+
+
+/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+
+/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+  @{
+*/
+
+/* PHY Register Description */
+#define PHY_CNTL_REG    0x00UL        /*!<  PHY control register address */
+#define PHY_STATUS_REG  0x01UL        /*!<  PHY status register address */
+#define PHY_ID1_REG     0x02UL        /*!<  PHY ID1 register */
+#define PHY_ID2_REG     0x03UL        /*!<  PHY ID2 register */
+#define PHY_ANA_REG     0x04UL        /*!<  PHY auto-negotiation advertisement register */
+#define PHY_ANLPA_REG   0x05UL        /*!<  PHY auto-negotiation link partner availability register */
+#define PHY_ANE_REG     0x06UL        /*!<  PHY auto-negotiation expansion register */
+
+/* PHY Control Register */
+#define PHY_CNTL_RESET_PHY      (1UL << 15UL)
+#define PHY_CNTL_DR_100MB       (1UL << 13UL)
+#define PHY_CNTL_ENABLE_AN      (1UL << 12UL)
+#define PHY_CNTL_POWER_DOWN     (1UL << 11UL)
+#define PHY_CNTL_RESTART_AN     (1UL << 9UL)
+#define PHY_CNTL_FULLDUPLEX     (1UL << 8UL)
+
+/* PHY Status Register */
+#define PHY_STATUS_AN_COMPLETE   (1UL << 5UL)
+#define PHY_STATUS_LINK_VALID    (1UL << 2UL)
+
+/* PHY Auto-negotiation Advertisement Register */
+#define PHY_ANA_DR100_TX_FULL   (1UL << 8UL)
+#define PHY_ANA_DR100_TX_HALF   (1UL << 7UL)
+#define PHY_ANA_DR10_TX_FULL    (1UL << 6UL)
+#define PHY_ANA_DR10_TX_HALF    (1UL << 5UL)
+#define PHY_ANA_IEEE_802_3_CSMA_CD   (1UL << 0UL)
+
+/* PHY Auto-negotiation Link Partner Advertisement Register */
+#define PHY_ANLPA_DR100_TX_FULL   (1UL << 8UL)
+#define PHY_ANLPA_DR100_TX_HALF   (1UL << 7UL)
+#define PHY_ANLPA_DR10_TX_FULL    (1UL << 6UL)
+#define PHY_ANLPA_DR10_TX_HALF    (1UL << 5UL)
+
+/* EMAC Tx/Rx descriptor's owner bit */
+#define EMAC_DESC_OWN_EMAC 0x80000000UL  /*!<  Set owner to EMAC */
+#define EMAC_DESC_OWN_CPU  0x00000000UL  /*!<  Set owner to CPU */
+
+/* Rx Frame Descriptor Status */
+#define EMAC_RXFD_RTSAS   0x0080UL  /*!<  Time Stamp Available */
+#define EMAC_RXFD_RP      0x0040UL  /*!<  Runt Packet */
+#define EMAC_RXFD_ALIE    0x0020UL  /*!<  Alignment Error */
+#define EMAC_RXFD_RXGD    0x0010UL  /*!<  Receiving Good packet received */
+#define EMAC_RXFD_PTLE    0x0008UL  /*!<  Packet Too Long Error */
+#define EMAC_RXFD_CRCE    0x0002UL  /*!<  CRC Error */
+#define EMAC_RXFD_RXINTR  0x0001UL  /*!<  Interrupt on receive */
+
+/* Tx Frame Descriptor's Control bits */
+#define EMAC_TXFD_TTSEN     0x08UL      /*!<  Tx time stamp enable */
+#define EMAC_TXFD_INTEN     0x04UL      /*!<  Tx interrupt enable */
+#define EMAC_TXFD_CRCAPP    0x02UL      /*!<  Append CRC */
+#define EMAC_TXFD_PADEN     0x01UL      /*!<  Padding mode enable */
+
+/* Tx Frame Descriptor Status */
+#define EMAC_TXFD_TXINTR 0x0001UL  /*!<  Interrupt on Transmit */
+#define EMAC_TXFD_DEF    0x0002UL  /*!<  Transmit deferred  */
+#define EMAC_TXFD_TXCP   0x0008UL  /*!<  Transmission Completion  */
+#define EMAC_TXFD_EXDEF  0x0010UL  /*!<  Exceed Deferral */
+#define EMAC_TXFD_NCS    0x0020UL  /*!<  No Carrier Sense Error */
+#define EMAC_TXFD_TXABT  0x0040UL  /*!<  Transmission Abort  */
+#define EMAC_TXFD_LC     0x0080UL  /*!<  Late Collision  */
+#define EMAC_TXFD_TXHA   0x0100UL  /*!<  Transmission halted */
+#define EMAC_TXFD_PAU    0x0200UL  /*!<  Paused */
+#define EMAC_TXFD_SQE    0x0400UL  /*!<  SQE error  */
+#define EMAC_TXFD_TTSAS  0x0800UL  /*!<  Time Stamp available */
+
+/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
+
+/** @addtogroup EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines
+  @{
+*/
+
+/*@}*/ /* end of group EMAC_EXPORTED_TYPEDEF */
+
+/* local variables */
+static uint32_t s_u32EnableTs = 0UL;
+
+static void EMAC_MdioWrite(EMAC_T *EMAC, uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data);
+static uint32_t EMAC_MdioRead(EMAC_T *EMAC, uint32_t u32Reg, uint32_t u32Addr);
+
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec);
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec);
+static void EMAC_TxDescInit(EMAC_MEMMGR_T *psMemMgr);
+static void EMAC_RxDescInit(EMAC_MEMMGR_T *psMemMgr);
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Write PHY register
+  * @param[in]  u32Reg PHY register number
+  * @param[in]  u32Addr PHY address, this address is board dependent
+  * @param[in] u32Data data to write to PHY register
+  * @return None
+  */
+static void EMAC_MdioWrite(EMAC_T *EMAC, uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data)
+{
+    /* Set data register */
+    EMAC->MIIMDAT = u32Data ;
+    /* Set PHY address, PHY register address, busy bit and write bit */
+    EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
+
+    /* Wait write complete by polling busy bit. */
+    while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)
+    {
+        ;
+    }
+
+}
+
+/**
+  * @brief  Read PHY register
+  * @param[in]  u32Reg PHY register number
+  * @param[in]  u32Addr PHY address, this address is board dependent
+  * @return Value read from PHY register
+  */
+static uint32_t EMAC_MdioRead(EMAC_T *EMAC, uint32_t u32Reg, uint32_t u32Addr)
+{
+    /* Set PHY address, PHY register address, busy bit */
+    EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
+
+    /* Wait read complete by polling busy bit */
+    while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)
+    {
+        ;
+    }
+
+    /* Get return data */
+    return EMAC->MIIMDAT;
+}
+
+void EMAC_Reset(EMAC_T *EMAC)
+{
+    /* Reset MAC */
+    EMAC->CTL = 0x1000000;
+}
+
+/**
+  * @brief  Initialize PHY chip, check for the auto-negotiation result.
+  * @param  None
+  * @return None
+  */
+void EMAC_PhyInit(EMAC_T *EMAC)
+{
+    uint32_t reg;
+    uint32_t i = 0UL;
+
+    /* Reset Phy Chip */
+    EMAC_MdioWrite(EMAC, PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY);
+
+    /* Wait until reset complete */
+    while (1)
+    {
+        reg = EMAC_MdioRead(EMAC, PHY_CNTL_REG, EMAC_PHY_ADDR) ;
+
+        if ((reg & PHY_CNTL_RESET_PHY) == 0UL)
+        {
+            break;
+        }
+    }
+
+    while (!(EMAC_MdioRead(EMAC, PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
+    {
+        if (i++ > 10000UL)      /* Cable not connected */
+        {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+            break;
+        }
+    }
+
+    if (i <= 10000UL)
+    {
+        /* Configure auto negotiation capability */
+        EMAC_MdioWrite(EMAC, PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
+                       PHY_ANA_DR100_TX_HALF |
+                       PHY_ANA_DR10_TX_FULL |
+                       PHY_ANA_DR10_TX_HALF |
+                       PHY_ANA_IEEE_802_3_CSMA_CD);
+        /* Restart auto negotiation */
+        EMAC_MdioWrite(EMAC, PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(EMAC, PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN);
+
+        /* Wait for auto-negotiation complete */
+        while (!(EMAC_MdioRead(EMAC, PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE))
+        {
+            ;
+        }
+
+        /* Check link valid again. Some PHYs needs to check result after link valid bit set */
+        while (!(EMAC_MdioRead(EMAC, PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
+        {
+            ;
+        }
+
+        /* Check link partner capability */
+        reg = EMAC_MdioRead(EMAC, PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
+
+        if (reg & PHY_ANLPA_DR100_TX_FULL)
+        {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+        }
+        else if (reg & PHY_ANLPA_DR100_TX_HALF)
+        {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+        }
+        else if (reg & PHY_ANLPA_DR10_TX_FULL)
+        {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+        }
+        else
+        {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+        }
+    }
+}
+
+/**
+  * @brief  Initial EMAC Tx descriptors and get Tx descriptor base address
+  * @param  EMAC_MEMMGR_T pointer
+  * @return None
+  */
+static void EMAC_TxDescInit(EMAC_MEMMGR_T *psMemMgr)
+{
+    uint32_t i;
+
+    /* Get Frame descriptor's base address. */
+    psMemMgr->psNextTxDesc = psMemMgr->psCurrentTxDesc = (EMAC_DESCRIPTOR_T *)((uint32_t)&psMemMgr->psTXDescs[0] | BIT31);
+
+    for (i = 0UL; i < psMemMgr->u32TxDescSize; i++)
+    {
+
+        if (s_u32EnableTs)
+        {
+            psMemMgr->psTXDescs[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN;
+        }
+        else
+        {
+            psMemMgr->psTXDescs[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN;
+        }
+
+        psMemMgr->psTXDescs[i].u32Data = (uint32_t)& psMemMgr->psTXFrames[i] | BIT31;
+        psMemMgr->psTXDescs[i].u32Status2 = 0UL;
+        psMemMgr->psTXDescs[i].u32Next = (uint32_t)(&psMemMgr->psTXDescs[(i + 1UL) % EMAC_TX_DESC_SIZE]) | BIT31;
+        psMemMgr->psTXDescs[i].u32Backup1 = psMemMgr->psTXDescs[i].u32Data;
+        psMemMgr->psTXDescs[i].u32Backup2 = psMemMgr->psTXDescs[i].u32Next;
+    }
+    psMemMgr->psEmac->TXDSA = (uint32_t)psMemMgr->psCurrentTxDesc;
+}
+
+
+/**
+  * @brief  Initial EMAC Rx descriptors and get Rx descriptor base address
+  * @param  EMAC_MEMMGR_T pointer
+  * @return None
+  */
+static void EMAC_RxDescInit(EMAC_MEMMGR_T *psMemMgr)
+{
+
+    uint32_t i;
+
+    /* Get Frame descriptor's base address. */
+    psMemMgr->psCurrentRxDesc = (EMAC_DESCRIPTOR_T *)((uint32_t)&psMemMgr->psRXDescs[0] | BIT31);
+
+    for (i = 0UL; i < psMemMgr->u32RxDescSize; i++)
+    {
+        psMemMgr->psRXDescs[i].u32Status1 = EMAC_DESC_OWN_EMAC;
+        psMemMgr->psRXDescs[i].u32Data = (uint32_t)&psMemMgr->psRXFrames[i] | BIT31;
+        psMemMgr->psRXDescs[i].u32Status2 = 0UL;
+        psMemMgr->psRXDescs[i].u32Next = (uint32_t)(&psMemMgr->psRXDescs[(i + 1UL) % EMAC_RX_DESC_SIZE]) | BIT31;
+        psMemMgr->psRXDescs[i].u32Backup1 = psMemMgr->psRXDescs[i].u32Data;
+        psMemMgr->psRXDescs[i].u32Backup2 = psMemMgr->psRXDescs[i].u32Next;
+    }
+    psMemMgr->psEmac->RXDSA = (uint32_t)psMemMgr->psCurrentRxDesc;
+}
+
+/**
+  * @brief  Convert subsecond value to nano second
+  * @param[in]  subsec Subsecond value to be convert
+  * @return Nano second
+  */
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec)
+{
+    /* 2^31 subsec == 10^9 ns */
+    uint64_t i;
+    i = 1000000000ull * (uint64_t)subsec;
+    i >>= 31;
+    return ((uint32_t)i);
+}
+
+/**
+  * @brief  Convert nano second to subsecond value
+  * @param[in]  nsec Nano second to be convert
+  * @return Subsecond
+  */
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec)
+{
+    /* 10^9 ns =  2^31 subsec */
+    uint64_t i;
+    i = (1ull << 31) * nsec;
+    i /= 1000000000ull;
+    return ((uint32_t)i);
+}
+
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Initialize EMAC interface, including descriptors, MAC address, and PHY.
+  * @param[in]  pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with
+  *       \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT
+  * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to
+  *       enable receive and transmit function.
+  */
+void EMAC_Open(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8MacAddr)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+
+    /* Enable transmit and receive descriptor */
+    EMAC_TxDescInit(psMemMgr);
+    EMAC_RxDescInit(psMemMgr);
+
+    /* Set the CAM Control register and the MAC address value */
+    EMAC_SetMacAddr(EMAC, pu8MacAddr);
+
+    /* Configure the MAC interrupt enable register. */
+    EMAC->INTEN = EMAC_INTEN_RXIEN_Msk |
+                  EMAC_INTEN_TXIEN_Msk |
+                  EMAC_INTEN_RXGDIEN_Msk |
+                  EMAC_INTEN_TXCPIEN_Msk |
+                  EMAC_INTEN_RXBEIEN_Msk |
+                  EMAC_INTEN_TXBEIEN_Msk |
+                  EMAC_INTEN_RDUIEN_Msk |
+                  EMAC_INTEN_TSALMIEN_Msk |
+                  EMAC_INTEN_WOLIEN_Msk;
+
+    /* Configure the MAC control register. */
+    EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |
+                EMAC_CTL_RMIIEN_Msk;
+
+    /* Accept packets for us and all broadcast and multicast packets */
+    EMAC->CAMCTL =  EMAC_CAMCTL_CMPEN_Msk |
+                    EMAC_CAMCTL_AMP_Msk |
+                    EMAC_CAMCTL_ABP_Msk;
+
+    /* Limit the max receive frame length */
+    EMAC->MRFL = EMAC_MAX_PKT_SIZE;
+}
+
+/**
+  * @brief  This function stop all receive and transmit activity and disable MAC interface
+  * @param None
+  * @return None
+  */
+
+void EMAC_Close(EMAC_T *EMAC)
+{
+    EMAC->CTL |= EMAC_CTL_RST_Msk;
+
+    while (EMAC->CTL & EMAC_CTL_RST_Msk) {}
+}
+
+/**
+  * @brief  Set the device MAC address
+  * @param[in]  pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  */
+void EMAC_SetMacAddr(EMAC_T *EMAC, uint8_t *pu8MacAddr)
+{
+    EMAC_EnableCamEntry(EMAC, 0UL, pu8MacAddr);
+}
+
+/**
+  * @brief Fill a CAM entry for MAC address comparison.
+  * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it.
+  * @param[in] pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  */
+void EMAC_EnableCamEntry(EMAC_T *EMAC, uint32_t u32Entry, uint8_t pu8MacAddr[])
+{
+    uint32_t u32Lsw, u32Msw;
+    uint32_t reg;
+    u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) |
+                        ((uint32_t)pu8MacAddr[5] << 16));
+    u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24) |
+                        ((uint32_t)pu8MacAddr[1] << 16) |
+                        ((uint32_t)pu8MacAddr[2] << 8) |
+                        (uint32_t)pu8MacAddr[3]);
+
+    reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL;
+    *(uint32_t volatile *)reg = u32Msw;
+    reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL;
+    *(uint32_t volatile *)reg = u32Lsw;
+
+    EMAC->CAMEN |= (1UL << u32Entry);
+}
+
+/**
+  * @brief  Disable a specified CAM entry
+  * @param[in]  u32Entry CAM entry to be disabled
+  * @return None
+  */
+void EMAC_DisableCamEntry(EMAC_T *EMAC, uint32_t u32Entry)
+{
+    EMAC->CAMEN &= ~(1UL << u32Entry);
+}
+
+
+/**
+  * @brief Receive an Ethernet packet
+  * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+  * @param[in] pu32Size Received packet size (without 4 byte CRC).
+  * @return Packet receive success or not
+  * @retval 0 No packet available for receive
+  * @retval 1 A packet is received
+  * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+  */
+uint32_t EMAC_RecvPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size)
+{
+    uint32_t reg;
+    uint32_t u32Count = 0UL;
+    EMAC_T *EMAC = psMemMgr->psEmac;
+
+    /* Clear Rx interrupt flags */
+    reg = EMAC->INTSTS;
+    EMAC->INTSTS = reg & 0xFFFFUL;  /* Clear all RX related interrupt status */
+
+    if (reg & EMAC_INTSTS_RXBEIF_Msk)
+    {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while (1) {}
+    }
+    else
+    {
+        /* Get Rx Frame Descriptor */
+        EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
+
+        /* If we reach last recv Rx descriptor, leave the loop */
+        if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)   /* ownership=CPU */
+        {
+            uint32_t status = desc->u32Status1 >> 16;
+
+            /* If Rx frame is good, process received frame */
+            if (status & EMAC_RXFD_RXGD)
+            {
+                /* lower 16 bit in descriptor status1 stores the Rx packet length */
+                *pu32Size = desc->u32Status1 & 0xFFFFUL;
+                memcpy(pu8Data, (uint8_t *)desc->u32Data, *pu32Size);
+                u32Count = 1UL;
+            }
+            else
+            {
+                /* Save Error status if necessary */
+                if (status & EMAC_RXFD_RP) {}
+
+                if (status & EMAC_RXFD_ALIE) {}
+
+                if (status & EMAC_RXFD_PTLE) {}
+
+                if (status & EMAC_RXFD_CRCE) {}
+            }
+        }
+    }
+
+    return (u32Count);
+}
+
+/**
+  * @brief Receive an Ethernet packet and the time stamp while it's received
+  * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+  * @param[out] pu32Size Received packet size (without 4 byte CRC).
+  * @param[out] pu32Sec Second value while packet received
+  * @param[out] pu32Nsec Nano second value while packet received
+  * @return Packet receive success or not
+  * @retval 0 No packet available for receive
+  * @retval 1 A packet is received
+  * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+  * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give
+  *       a buffer large enough to store such packet
+  */
+uint32_t EMAC_RecvPktTS(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+    uint32_t reg;
+    uint32_t u32Count = 0UL;
+
+    /* Clear Rx interrupt flags */
+    reg = EMAC->INTSTS;
+    EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */
+
+    if (reg & EMAC_INTSTS_RXBEIF_Msk)
+    {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while (1) {}
+    }
+    else
+    {
+        /* Get Rx Frame Descriptor */
+        EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
+
+        /* If we reach last recv Rx descriptor, leave the loop */
+        if (EMAC->CRXDSA != (uint32_t)desc)
+        {
+            if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)   /* ownership=CPU */
+            {
+
+                uint32_t status = desc->u32Status1 >> 16;
+
+                /* If Rx frame is good, process received frame */
+                if (status & EMAC_RXFD_RXGD)
+                {
+                    /* lower 16 bit in descriptor status1 stores the Rx packet length */
+                    *pu32Size = desc->u32Status1 & 0xFFFFUL;
+                    memcpy(pu8Data, (uint8_t *)desc->u32Data, *pu32Size);
+
+                    *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+                    *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+
+                    u32Count = 1UL;
+                }
+                else
+                {
+                    /* Save Error status if necessary */
+                    if (status & EMAC_RXFD_RP) {}
+
+                    if (status & EMAC_RXFD_ALIE) {}
+
+                    if (status & EMAC_RXFD_PTLE) {}
+
+                    if (status & EMAC_RXFD_CRCE) {}
+                }
+            }
+        }
+    }
+
+    return (u32Count);
+}
+
+/**
+  * @brief Clean up process after a packet is received
+  * @param None
+  * @return None
+  * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process
+  * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
+  */
+void EMAC_RecvPktDone(EMAC_MEMMGR_T *psMemMgr)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+    /* Get Rx Frame Descriptor */
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
+
+    /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+    desc->u32Data = desc->u32Backup1;
+    desc->u32Next = desc->u32Backup2;
+
+    /* Change ownership to DMA for next use */
+    desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+    /* Get Next Frame Descriptor pointer to process */
+    desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+    /* Save last processed Rx descriptor */
+    psMemMgr->psCurrentRxDesc = desc;
+
+    EMAC_TRIGGER_RX(EMAC);
+}
+
+
+/**
+  * @brief Send an Ethernet packet
+  * @param[in] pu8Data Pointer to a buffer holds the packet to transmit
+  * @param[in] u32Size Packet size (without 4 byte CRC).
+  * @return Packet transmit success or not
+  * @retval 0 Transmit failed due to descriptor unavailable.
+  * @retval 1 Packet is copied to descriptor and triggered to transmit.
+  * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
+  */
+uint32_t EMAC_SendPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t u32Size)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+
+    /* Get Tx frame descriptor & data pointer */
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psNextTxDesc;
+    uint32_t status = desc->u32Status1;
+    uint32_t ret = 0UL;
+
+    /* Check descriptor ownership */
+    if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+    {
+        memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size);
+
+        /* Set Tx descriptor transmit byte count */
+        desc->u32Status2 = u32Size;
+
+        /* Change descriptor ownership to EMAC */
+        desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+        /* Get next Tx descriptor */
+        psMemMgr->psNextTxDesc = (EMAC_DESCRIPTOR_T *)(desc->u32Next);
+
+        /* Trigger EMAC to send the packet */
+        EMAC_TRIGGER_TX(EMAC);
+        ret = 1UL;
+    }
+
+    return (ret);
+}
+
+
+/**
+  * @brief Clean up process after packet(s) are sent
+  * @param None
+  * @return Number of packet sent between two function calls
+  * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to
+  *          release the resource use by transmit process
+  */
+uint32_t EMAC_SendPktDone(EMAC_MEMMGR_T *psMemMgr)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+
+    uint32_t status, reg;
+    uint32_t last_tx_desc;
+    uint32_t u32Count = 0UL;
+
+    reg = EMAC->INTSTS;
+    /* Clear Tx interrupt flags */
+    EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+    if (reg & EMAC_INTSTS_TXBEIF_Msk)
+    {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while (1) {}
+    }
+    else
+    {
+        /* Get our first descriptor to process */
+        EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentTxDesc;
+
+        /* Process the descriptor(s). */
+        last_tx_desc = EMAC->CTXDSA ;
+
+        do
+        {
+            /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+            if (desc->u32Status1 & EMAC_DESC_OWN_EMAC)
+            {
+                break;
+            }
+
+            /* Get Tx status stored in descriptor */
+            status = desc->u32Status2 >> 16UL;
+
+            if (status & EMAC_TXFD_TXCP)
+            {
+                u32Count++;
+            }
+            else
+            {
+                /* Do nothing here on error. */
+                if (status & EMAC_TXFD_TXABT) {}
+
+                if (status & EMAC_TXFD_DEF) {}
+
+                if (status & EMAC_TXFD_PAU) {}
+
+                if (status & EMAC_TXFD_EXDEF) {}
+
+                if (status & EMAC_TXFD_NCS) {}
+
+                if (status & EMAC_TXFD_SQE) {}
+
+                if (status & EMAC_TXFD_LC) {}
+
+                if (status & EMAC_TXFD_TXHA) {}
+            }
+
+            /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+            desc->u32Data = desc->u32Backup1;
+            desc->u32Next = desc->u32Backup2;
+            /* go to next descriptor in link */
+            desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+        }
+        while (last_tx_desc != (uint32_t)desc);      /* If we reach last sent Tx descriptor, leave the loop */
+
+        /* Save last processed Tx descriptor */
+        psMemMgr->psCurrentTxDesc = (EMAC_DESCRIPTOR_T *)desc;
+    }
+
+    return (u32Count);
+}
+
+/**
+  * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent
+  * @param[in]  pu32Sec Second value while packet sent
+  * @param[in]  pu32Nsec Nano second value while packet sent
+  * @return If a packet sent successfully
+  * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless
+  * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent
+  * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to
+  *          release the resource use by transmit process
+  */
+uint32_t EMAC_SendPktDoneTS(EMAC_MEMMGR_T *psMemMgr, uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+    uint32_t reg;
+    uint32_t u32Count = 0UL;
+
+    reg = EMAC->INTSTS;
+    /* Clear Tx interrupt flags */
+    EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+    if (reg & EMAC_INTSTS_TXBEIF_Msk)
+    {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while (1) {}
+    }
+    else
+    {
+        /* Process the descriptor.
+           Get our first descriptor to process */
+        EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentTxDesc;
+
+        /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+        if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+        {
+            /* Get Tx status stored in descriptor */
+            uint32_t status = desc->u32Status2 >> 16UL;
+
+            if (status & EMAC_TXFD_TXCP)
+            {
+                u32Count = 1UL;
+                *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+                *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+            }
+            else
+            {
+                /* Do nothing here on error. */
+                if (status & EMAC_TXFD_TXABT) {}
+
+                if (status & EMAC_TXFD_DEF) {}
+
+                if (status & EMAC_TXFD_PAU) {}
+
+                if (status & EMAC_TXFD_EXDEF) {}
+
+                if (status & EMAC_TXFD_NCS) {}
+
+                if (status & EMAC_TXFD_SQE) {}
+
+                if (status & EMAC_TXFD_LC) {}
+
+                if (status & EMAC_TXFD_TXHA) {}
+            }
+
+            /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+            desc->u32Data = desc->u32Backup1;
+            desc->u32Next = desc->u32Backup2;
+            /* go to next descriptor in link */
+            desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+            /* Save last processed Tx descriptor */
+            psMemMgr->psCurrentTxDesc = desc;
+        }
+    }
+
+    return (u32Count);
+}
+
+/**
+  * @brief  Enable IEEE1588 time stamp function and set current time
+  * @param[in]  u32Sec Second value
+  * @param[in]  u32Nsec Nano second value
+  * @return None
+  */
+void EMAC_EnableTS(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec)
+{
+#if 0
+    double f;
+    uint32_t reg;
+    EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+    EMAC->UPDSEC = u32Sec;   /* Assume current time is 0 sec + 0 nano sec */
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+
+    /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns
+       Assume we want to set each tick to 100ns.
+       Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
+       Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz
+       From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0
+       So:
+        EMAC->TSIR = 0xD7;
+        EMAC->TSAR = 0x1E70C600; */
+    f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5;
+    EMAC->TSINC = (reg = (uint32_t)f);
+    f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg);
+    EMAC->TSADDEND = (uint32_t)f;
+    EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */
+#endif
+}
+
+/**
+  * @brief  Disable IEEE1588 time stamp function
+  * @param None
+  * @return None
+  */
+void EMAC_DisableTS(EMAC_T *EMAC)
+{
+#if 0
+    EMAC->TSCTL = 0UL;
+#endif
+}
+
+/**
+  * @brief  Get current time stamp
+  * @param[out]  pu32Sec Current second value
+  * @param[out]  pu32Nsec Current nano second value
+  * @return None
+  */
+void EMAC_GetTime(EMAC_T *EMAC, uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+    /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */
+    *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC);
+    *pu32Sec = EMAC->TSSEC;
+}
+
+/**
+  * @brief  Set current time stamp
+  * @param[in]  u32Sec Second value
+  * @param[in]  u32Nsec Nano second value
+  * @return None
+  */
+void EMAC_SetTime(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec)
+{
+    /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */
+    EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+    EMAC->UPDSEC = u32Sec;
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+    EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk);
+
+}
+
+/**
+  * @brief  Enable alarm function and set alarm time
+  * @param[in]  u32Sec Second value to trigger alarm
+  * @param[in]  u32Nsec Nano second value to trigger alarm
+  * @return None
+  */
+void EMAC_EnableAlarm(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec)
+{
+
+    EMAC->ALMSEC = u32Sec;
+    EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+    EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+  * @brief  Disable alarm function
+  * @param  None
+  * @return None
+  */
+void EMAC_DisableAlarm(EMAC_T *EMAC)
+{
+
+    EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+  * @brief  Add a offset to current time
+  * @param[in]  u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0).
+  * @param[in]  u32Sec Second value to add to current time
+  * @param[in]  u32Nsec Nano second value to add to current time
+  * @return None
+  */
+void EMAC_UpdateTime(EMAC_T *EMAC, uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec)
+{
+    EMAC->UPDSEC = u32Sec;
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+
+    if (u32Neg)
+    {
+        EMAC->UPDSUBSEC |= BIT31;   /* Set bit 31 indicates this is a negative value */
+    }
+
+    EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk;
+
+}
+
+/**
+  * @brief  Check Ethernet link status
+  * @param  None
+  * @return Current link status, could be one of following value.
+  * - \ref EMAC_LINK_DOWN
+  * - \ref EMAC_LINK_100F
+  * - \ref EMAC_LINK_100H
+  * - \ref EMAC_LINK_10F
+  * - \ref EMAC_LINK_10H
+  * @note   This API should be called regularly to sync EMAC setting with real connection status
+  */
+uint32_t EMAC_CheckLinkStatus(EMAC_T *EMAC)
+{
+    uint32_t reg, ret = EMAC_LINK_DOWN;
+
+    /* Check link valid again */
+    if (EMAC_MdioRead(EMAC, PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)
+    {
+        /* Check link partner capability */
+        reg = EMAC_MdioRead(EMAC, PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
+
+        if (reg & PHY_ANLPA_DR100_TX_FULL)
+        {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+            ret = EMAC_LINK_100F;
+        }
+        else if (reg & PHY_ANLPA_DR100_TX_HALF)
+        {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+            ret = EMAC_LINK_100H;
+        }
+        else if (reg & PHY_ANLPA_DR10_TX_FULL)
+        {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+            ret = EMAC_LINK_10F;
+        }
+        else
+        {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+            ret = EMAC_LINK_10H;
+        }
+    }
+
+    return ret;
+}
+
+/**
+  * @brief  Fill a MAC address to list and enable.
+  * @param  A MAC address
+  * @return The CAM index
+  * @retval -1 Failed to fill the MAC address.
+  * @retval 0~(EMAC_CAMENTRY_NB-1) The index number of entry location.
+  */
+int32_t EMAC_FillCamEntry(EMAC_T *EMAC, uint8_t pu8MacAddr[])
+{
+    uint32_t *EMAC_CAMxM;
+    uint32_t *EMAC_CAMxL;
+    int32_t index;
+    uint8_t mac[6];
+
+    for (index = 0; index < EMAC_CAMENTRY_NB; index ++)
+    {
+        EMAC_CAMxM = (uint32_t *)((uint32_t)&EMAC->CAM0M + (index * 8));
+        EMAC_CAMxL = (uint32_t *)((uint32_t)&EMAC->CAM0L + (index * 8));
+
+        mac[0] = (*EMAC_CAMxM >> 24) & 0xff;
+        mac[1] = (*EMAC_CAMxM >> 16) & 0xff;
+        mac[2] = (*EMAC_CAMxM >> 8) & 0xff;
+        mac[3] = (*EMAC_CAMxM) & 0xff;
+        mac[4] = (*EMAC_CAMxL >> 24) & 0xff;
+        mac[5] = (*EMAC_CAMxL >> 16) & 0xff;
+
+        if (memcmp(mac, pu8MacAddr, sizeof(mac)) == 0)
+        {
+            goto exit_emac_fillcamentry;
+        }
+
+        if (*EMAC_CAMxM == 0 && *EMAC_CAMxL == 0)
+        {
+            break;
+        }
+    }
+
+    if (index < EMAC_CAMENTRY_NB)
+    {
+        EMAC_EnableCamEntry(EMAC, index, pu8MacAddr);
+        goto exit_emac_fillcamentry;
+    }
+
+    return -1;
+
+exit_emac_fillcamentry:
+
+    return index;
+}
+
+/**
+  * @brief Send an Ethernet packet
+  * @param[in] u32Size Packet size (without 4 byte CRC).
+  * @return Packet transmit success or not
+  * @retval 0 Transmit failed due to descriptor unavailable.
+  * @retval 1 Triggered to transmit.
+  * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
+  */
+uint32_t EMAC_SendPktWoCopy(EMAC_MEMMGR_T *psMemMgr, uint32_t u32Size)
+{
+    EMAC_T *EMAC = psMemMgr->psEmac;
+
+    /* Get Tx frame descriptor & data pointer */
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psNextTxDesc;
+    uint32_t status = desc->u32Status1;
+    uint32_t ret = 0UL;
+
+    /* Check descriptor ownership */
+    if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)
+    {
+        /* Set Tx descriptor transmit byte count */
+        desc->u32Status2 = u32Size;
+
+        /* Change descriptor ownership to EMAC */
+        desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+        /* Get next Tx descriptor */
+        psMemMgr->psNextTxDesc = (EMAC_DESCRIPTOR_T *)(desc->u32Next);
+
+        /* Trigger EMAC to send the packet */
+        EMAC_TRIGGER_TX(EMAC);
+        ret = 1UL;
+    }
+
+    return (ret);
+}
+
+/**
+  * @brief  Get avaiable TX buffer address
+  * @param  None
+  * @return An avaiable TX buffer.
+  * @note   This API should be called before EMAC_SendPkt_WoCopy calling. Caller will do data-copy.
+  */
+uint8_t *EMAC_ClaimFreeTXBuf(EMAC_MEMMGR_T *psMemMgr)
+{
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psNextTxDesc;
+
+    if (desc->u32Status1 & EMAC_DESC_OWN_EMAC)
+    {
+        return (NULL);
+    }
+    else
+    {
+        return (uint8_t *)desc->u32Data;
+    }
+}
+
+/**
+  * @brief  Get data length of avaiable RX buffer.
+  * @param  None
+  * @return An data length of avaiable RX buffer.
+  * @note   This API should be called before EMAC_RecvPktDone_WoTrigger calling. Caller will do data-copy.
+  */
+uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf)
+{
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
+
+    if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC)   /* ownership=CPU */
+    {
+        uint32_t status = desc->u32Status1 >> 16;
+
+        /* It is good and no CRC error. */
+        if ((status & EMAC_RXFD_RXGD) && !(status & EMAC_RXFD_CRCE))
+        {
+            *ppuDataBuf = (uint8_t *)desc->u32Data;
+            return desc->u32Status1 & 0xFFFFUL;
+        }
+        else
+        {
+            // Drop it
+            EMAC_RecvPktDone(psMemMgr);
+        }
+    }
+
+    return 0;
+}
+
+
+/**
+  * @brief Clean up process after a packet is received.
+  * @param None
+  * @return None
+  * @details Caller must call the function to release the resource.
+  * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
+  * @note This function is without doing EMAC_TRIGGER_RX.
+  */
+void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr)
+{
+    /* Get Rx Frame Descriptor */
+    EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
+
+    /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+    desc->u32Data = desc->u32Backup1;
+    desc->u32Next = desc->u32Backup2;
+
+    /* Change ownership to DMA for next use */
+    desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+    /* Get Next Frame Descriptor pointer to process */
+    desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+    /* Save last processed Rx descriptor */
+    psMemMgr->psCurrentRxDesc = desc;
+}
+
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EMAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_etimer.c

@@ -0,0 +1,341 @@
+/**************************************************************************//**
+ * @file     etimer.c
+ * @brief    N9H30 series ETIMER driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_sys.h"
+
+/// @cond HIDDEN_SYMBOLS
+/**
+  * @brief This API is used to get the clock frequency of Timer
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return Timer clock frequency
+  * @note This API cannot return correct clock rate if timer source is external clock input.
+  */
+UINT ETIMER_GetModuleClock(UINT timer)
+{
+    UINT src;
+
+    src = (inpw(REG_CLK_DIVCTL8) >> (16 + timer * 4)) & 0x3;
+
+    if (src == 0)
+        return 12000000;
+    else if (src == 1)
+        return (sysGetClock(SYS_PCLK) * 1000000);
+    else if (src == 2)
+        return (sysGetClock(SYS_PCLK) * 1000000 / 4096);
+    else
+        return 32768;
+
+}
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_ETIMER_Driver ETIMER Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_ETIMER_EXPORTED_FUNCTIONS ETIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief This API is used to configure timer to operate in specified mode
+  *        and frequency. If timer cannot work in target frequency, a closest
+  *        frequency will be chose and returned.
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @param[in] u32Mode Operation mode. Possible options are
+  *                 - \ref ETIMER_ONESHOT_MODE
+  *                 - \ref ETIMER_PERIODIC_MODE
+  *                 - \ref ETIMER_TOGGLE_MODE
+  *                 - \ref ETIMER_CONTINUOUS_MODE
+  * @param[in] u32Freq Target working frequency
+  * @return Real Timer working frequency
+  * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+  *       \ref ETIMER_Start macro or program registers directly
+  */
+UINT ETIMER_Open(UINT timer, UINT u32Mode, UINT u32Freq)
+{
+    UINT u32Clk = ETIMER_GetModuleClock(timer);
+    UINT u32Cmpr = 0, u32Prescale = 0;
+
+    // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
+    if (u32Freq > (u32Clk / 2))
+    {
+        u32Cmpr = 2;
+    }
+    else
+    {
+        if (u32Clk >= 0x4000000)
+        {
+            u32Prescale = 7;    // real prescaler value is 8
+            u32Clk >>= 3;
+        }
+        else if (u32Clk >= 0x2000000)
+        {
+            u32Prescale = 3;    // real prescaler value is 4
+            u32Clk >>= 2;
+        }
+        else if (u32Clk >= 0x1000000)
+        {
+            u32Prescale = 1;    // real prescaler value is 2
+            u32Clk >>= 1;
+        }
+        u32Cmpr = u32Clk / u32Freq;
+    }
+
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CMPR, u32Cmpr);
+        outpw(REG_ETMR0_PRECNT, u32Prescale);
+        outpw(REG_ETMR0_CTL, 1 | u32Mode);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CMPR, u32Cmpr);
+        outpw(REG_ETMR1_PRECNT, u32Prescale);
+        outpw(REG_ETMR1_CTL, 1 | u32Mode);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CMPR, u32Cmpr);
+        outpw(REG_ETMR2_PRECNT, u32Prescale);
+        outpw(REG_ETMR2_CTL, 1 | u32Mode);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CMPR, u32Cmpr);
+        outpw(REG_ETMR3_PRECNT, u32Prescale);
+        outpw(REG_ETMR3_CTL, 1 | u32Mode);
+    }
+
+    return (u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/**
+  * @brief This API stops Timer counting and disable the Timer interrupt function
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+void ETIMER_Close(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, 0);
+        outpw(REG_ETMR0_IER, 0);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, 0);
+        outpw(REG_ETMR1_IER, 0);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, 0);
+        outpw(REG_ETMR2_IER, 0);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, 0);
+        outpw(REG_ETMR3_IER, 0);
+    }
+}
+
+/**
+  * @brief This API is used to create a delay loop for u32usec micro seconds
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second)
+  * @return None
+  * @note This API overwrites the register setting of the timer used to count the delay time.
+  * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay
+  */
+void ETIMER_Delay(UINT timer, UINT u32Usec)
+{
+    UINT u32Clk = ETIMER_GetModuleClock(timer);
+    UINT u32Prescale = 0, delay = 300000000 / u32Clk;
+    float fCmpr;
+
+    // Clear current timer configuration
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, 0);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, 0);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, 0);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, 0);
+    }
+
+    if (u32Clk == 10000)          // min delay is 100us if timer clock source is LIRC 10k
+    {
+        u32Usec = ((u32Usec + 99) / 100) * 100;
+    }
+    else        // 10 usec every step
+    {
+        u32Usec = ((u32Usec + 9) / 10) * 10;
+    }
+
+    if (u32Clk >= 0x4000000)
+    {
+        u32Prescale = 7;    // real prescaler value is 8
+        u32Clk >>= 3;
+    }
+    else if (u32Clk >= 0x2000000)
+    {
+        u32Prescale = 3;    // real prescaler value is 4
+        u32Clk >>= 2;
+    }
+    else if (u32Clk >= 0x1000000)
+    {
+        u32Prescale = 1;    // real prescaler value is 2
+        u32Clk >>= 1;
+    }
+
+    // u32Usec * u32Clk might overflow if using UINT
+    fCmpr = ((float)u32Usec * (float)u32Clk) / 1000000.0;
+
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CMPR, (UINT)fCmpr);
+        outpw(REG_ETMR0_PRECNT, u32Prescale);
+        outpw(REG_ETMR0_CTL, 1);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CMPR, (UINT)fCmpr);
+        outpw(REG_ETMR1_PRECNT, u32Prescale);
+        outpw(REG_ETMR1_CTL, 1);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CMPR, (UINT)fCmpr);
+        outpw(REG_ETMR2_PRECNT, u32Prescale);
+        outpw(REG_ETMR2_CTL, 1);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CMPR, (UINT)fCmpr);
+        outpw(REG_ETMR3_PRECNT, u32Prescale);
+        outpw(REG_ETMR3_CTL, 1);
+    }
+
+    // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+    // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+    for (; delay > 0; delay--)
+    {
+#if defined (__GNUC__) && !(__CC_ARM)
+        __asm__ __volatile__
+        (
+            "nop  \n"
+        );
+#else
+        __asm
+        {
+            NOP
+        }
+#endif
+    }
+
+    if (timer == 0)
+    {
+        while (inpw(REG_ETMR0_CTL) & 0x80);
+    }
+    else if (timer == 1)
+    {
+        while (inpw(REG_ETMR1_CTL) & 0x80);
+    }
+    else if (timer == 2)
+    {
+        while (inpw(REG_ETMR2_CTL) & 0x80);
+    }
+    else
+    {
+        while (inpw(REG_ETMR3_CTL) & 0x80);
+    }
+}
+
+/**
+  * @brief This API is used to enable timer capture function with specified mode and capture edge
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @param[in] u32CapMode Timer capture mode. Could be
+  *                 - \ref ETIMER_CAPTURE_FREE_COUNTING_MODE
+  *                 - \ref ETIMER_CAPTURE_TRIGGER_COUNTING_MODE
+  *                 - \ref ETIMER_CAPTURE_COUNTER_RESET_MODE
+  * @param[in] u32Edge Timer capture edge. Possible values are
+  *                 - \ref ETIMER_CAPTURE_FALLING_EDGE
+  *                 - \ref ETIMER_CAPTURE_RISING_EDGE
+  *                 - \ref ETIMER_CAPTURE_FALLING_THEN_RISING_EDGE
+  *                 - \ref ETIMER_CAPTURE_RISING_THEN_FALLING_EDGE
+  * @return None
+  * @note Timer frequency should be configured separately by using \ref ETIMER_Open API, or program registers directly
+  */
+void ETIMER_EnableCapture(UINT timer, UINT u32CapMode, UINT u32Edge)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, (inpw(REG_ETMR0_CTL) & ~0x1E0000) | u32CapMode | u32Edge | 0x10000);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, (inpw(REG_ETMR1_CTL) & ~0x1E0000) | u32CapMode | u32Edge | 0x10000);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, (inpw(REG_ETMR2_CTL) & ~0x1E0000) | u32CapMode | u32Edge | 0x10000);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, (inpw(REG_ETMR3_CTL) & ~0x1E0000) | u32CapMode | u32Edge | 0x10000);
+    }
+}
+
+/**
+  * @brief This API is used to disable the Timer capture function
+  * @param[in] timer ETIMER number. Range from 0 ~ 3
+  * @return None
+  */
+void ETIMER_DisableCapture(UINT timer)
+{
+    if (timer == 0)
+    {
+        outpw(REG_ETMR0_CTL, inpw(REG_ETMR0_CTL) & ~0x10000);
+    }
+    else if (timer == 1)
+    {
+        outpw(REG_ETMR1_CTL, inpw(REG_ETMR1_CTL) & ~0x10000);
+    }
+    else if (timer == 2)
+    {
+        outpw(REG_ETMR2_CTL, inpw(REG_ETMR2_CTL) & ~0x10000);
+    }
+    else
+    {
+        outpw(REG_ETMR3_CTL, inpw(REG_ETMR3_CTL) & ~0x10000);
+    }
+
+}
+
+
+/*@}*/ /* end of group N9H30_ETIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_ETIMER_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_fmi.c

@@ -0,0 +1,920 @@
+/**************************************************************************//**
+ * @file     fmi.c
+ * @brief    N9H30 FMI eMMC driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_fmi.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_FMI_Driver FMI Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_FMI_EXPORTED_FUNCTIONS FMI Exported Functions
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+#define FMI_BLOCK_SIZE   512
+
+// global variables
+// For response R3 (such as ACMD41, CRC-7 is invalid; but FMI controller will still
+// calculate CRC-7 and get an error result, software should ignore this error and clear INTSTS [CRC_IF] flag
+// _fmi_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error
+unsigned int _fmi_uR3_CMD = 0;
+unsigned int _fmi_uR7_CMD = 0;
+unsigned char volatile _fmi_eMMCDataReady = FALSE;
+
+unsigned char *_fmi_peMMCBuffer;
+unsigned int gFMIReferenceClock;
+
+#ifdef __ICCARM__
+    #pragma data_alignment = 4096
+    unsigned char _fmi_uceMMCBuffer[512];
+#else
+    unsigned char _fmi_uceMMCBuffer[512] __attribute__((aligned(4096)));
+#endif
+
+int emmc_ok = 0;
+
+unsigned char peMMC_offset = 0;
+
+EMMC_INFO_T eMMC;
+
+void eMMC_CheckRB()
+{
+    while (1)
+    {
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+        while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+        if (inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_DAT0STS_Msk)
+            break;
+    }
+}
+
+
+int eMMC_Command(EMMC_INFO_T *pSD, unsigned char ucCmd, unsigned int uArg)
+{
+    volatile int buf;
+
+    outpw(REG_FMI_EMMCCMD, uArg);
+    buf = (inpw(REG_FMI_EMMCCTL) & (~FMI_EMMCCTL_CMDCODE_Msk)) | (ucCmd << 8) | (FMI_EMMCCTL_COEN_Msk);
+    outpw(REG_FMI_EMMCCTL, buf);
+
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_COEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+            return EMMC_NO_CARD;
+    }
+    return 0;
+}
+
+
+int eMMC_CmdAndRsp(EMMC_INFO_T *pSD, unsigned char ucCmd, unsigned int uArg, int ntickCount)
+{
+    volatile int buf;
+
+    outpw(REG_FMI_EMMCCMD, uArg);
+    buf = (inpw(REG_FMI_EMMCCTL) & (~FMI_EMMCCTL_CMDCODE_Msk)) | (ucCmd << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk);
+    outpw(REG_FMI_EMMCCTL, buf);
+
+    if (ntickCount > 0)
+    {
+        while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_RIEN_Msk)
+        {
+            if (ntickCount-- == 0)
+            {
+                outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CTLRST_Msk); // reset SD engine
+                return 2;
+            }
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+    }
+    else
+    {
+        while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_RIEN_Msk)
+        {
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+    }
+
+    if (_fmi_uR7_CMD)
+    {
+        if (((inpw(REG_FMI_EMMCRESP1) & 0xff) != 0x55) && ((inpw(REG_FMI_EMMCRESP0) & 0xf) != 0x01))
+        {
+            _fmi_uR7_CMD = 0;
+            return EMMC_CMD8_ERROR;
+        }
+    }
+
+    if (!_fmi_uR3_CMD)
+    {
+        if (inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC7_Msk)     // check CRC7
+            return 0;
+        else
+            return EMMC_CRC7_ERROR;
+    }
+    else     // ignore CRC error for R3 case
+    {
+        _fmi_uR3_CMD = 0;
+        outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_CRCIF_Msk);
+        return 0;
+    }
+}
+
+int eMMC_Swap32(int val)
+{
+    int buf;
+
+    buf = val;
+    val <<= 24;
+    val |= (buf << 8) & 0xff0000;
+    val |= (buf >> 8) & 0xff00;
+    val |= (buf >> 24) & 0xff;
+    return val;
+}
+
+// Get 16 bytes CID or CSD
+int eMMC_CmdAndRsp2(EMMC_INFO_T *pSD, unsigned char ucCmd, unsigned int uArg, unsigned int *puR2ptr)
+{
+    unsigned int i, buf;
+    unsigned int tmpBuf[5];
+
+    outpw(REG_FMI_EMMCCMD, uArg);
+    buf = (inpw(REG_FMI_EMMCCTL) & (~FMI_EMMCCTL_CMDCODE_Msk)) | (ucCmd << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_R2EN_Msk);
+    outpw(REG_FMI_EMMCCTL, buf);
+
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_R2EN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+            return EMMC_NO_CARD;
+    }
+
+    if (inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC7_Msk)
+    {
+        for (i = 0; i < 5; i++)
+            tmpBuf[i] = eMMC_Swap32(*(int *)(FMI_BA + i * 4));
+        for (i = 0; i < 4; i++)
+            *puR2ptr++ = ((tmpBuf[i] & 0x00ffffff) << 8) | ((tmpBuf[i + 1] & 0xff000000) >> 24);
+        return 0;
+    }
+    else
+        return EMMC_CRC7_ERROR;
+}
+
+
+int eMMC_CmdAndRspDataIn(EMMC_INFO_T *pSD, unsigned char ucCmd, unsigned int uArg)
+{
+    volatile int buf;
+
+    outpw(REG_FMI_EMMCCMD, uArg);
+    buf = (inpw(REG_FMI_EMMCCTL) & (~FMI_EMMCCTL_CMDCODE_Msk)) | (ucCmd << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk | FMI_EMMCCTL_DIEN_Msk);
+    outpw(REG_FMI_EMMCCTL, buf);
+
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_RIEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+            return EMMC_NO_CARD;
+    }
+
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_DIEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+            return EMMC_NO_CARD;
+    }
+
+    if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC7_Msk))      // check CRC7
+    {
+        return EMMC_CRC7_ERROR;
+    }
+
+    if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC16_Msk))     // check CRC16
+    {
+        return EMMC_CRC16_ERROR;
+    }
+    return 0;
+}
+
+// there are 3 bits for divider N0, maximum is 8
+#define EMMC_CLK_DIV0_MAX     8
+// there are 8 bits for divider N1, maximum is 256
+#define EMMC_CLK_DIV1_MAX     256
+
+void eMMC_Set_clock(unsigned int clock_khz)
+{
+    UINT32 rate, div0, div1, i;
+
+    //--- calculate the rate that 2 divider have to divide
+    // _fmi_uFMIReferenceClock is the input clock with unit KHz like as APLL/UPLL and
+    if (clock_khz > gFMIReferenceClock)
+    {
+        //sysprintf("ERROR: wrong eMMC clock %dKHz since it is faster than input clock %dKHz !\n", clock_khz, gFMIReferenceClock);
+        return;
+    }
+    rate = gFMIReferenceClock / clock_khz;
+    // choose slower clock if system clock cannot divisible by wanted clock
+    if (gFMIReferenceClock % clock_khz != 0)
+        rate++;
+
+    if (rate > (EMMC_CLK_DIV0_MAX * EMMC_CLK_DIV1_MAX))   // the maximum divider for EMMC_CLK is (EMMC_CLK_DIV0_MAX * EMMC_CLK_DIV1_MAX)
+    {
+        //sysprintf("ERROR: wrong SD clock %dKHz since it is slower than input clock %dKHz/%d !\n", clock_khz, gFMIReferenceClock, EMMC_CLK_DIV0_MAX * EMMC_CLK_DIV1_MAX);
+        return;
+    }
+
+    //--- choose a suitable value for first divider
+    for (div0 = EMMC_CLK_DIV0_MAX; div0 > 0; div0--)    // choose the maximum value if can exact division
+    {
+        if (rate % div0 == 0)
+            break;
+    }
+    if (div0 == 0)   // cannot exact division
+    {
+        // if rate <= EMMC_CLK_DIV1_MAX, set div0 to 1 since div1 can exactly divide input clock
+        div0 = (rate <= EMMC_CLK_DIV1_MAX) ? 1 : EMMC_CLK_DIV0_MAX;
+    }
+
+    //--- calculate the second divider
+    div1 = rate / div0;
+    div1 &= 0xFF;
+
+    //sysprintf("Set_clock(): wanted clock=%d, rate=%d, div0=%d, div1=%d\n", clock_khz, rate, div0, div1);
+
+    //--- setup register
+    outpw(REG_CLK_DIVCTL3, (inpw(REG_CLK_DIVCTL3) & ~0x18) | (0x3 << 3));
+    outpw(REG_CLK_DIVCTL3, (inpw(REG_CLK_DIVCTL3) & ~0x7) | (div0 - 1));
+    outpw(REG_CLK_DIVCTL3, (inpw(REG_CLK_DIVCTL3) & ~0xff00) | ((div1 - 1) << 8));
+    for (i = 0; i < 1000; i++); // waiting for clock become stable
+    return;
+}
+
+// Initial
+int eMMC_Init(EMMC_INFO_T *pSD)
+{
+    int volatile i, status;
+    unsigned int resp;
+    unsigned int CIDBuffer[4];
+    unsigned int volatile u32CmdTimeOut;
+
+    // set the clock to 300KHz
+    eMMC_Set_clock(300);
+
+    // power ON 74 clock
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK74OEN_Msk);
+
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK74OEN_Msk);
+
+    eMMC_Command(pSD, 0, 0);        // reset all cards
+    for (i = 0x1000; i > 0; i--);
+
+    // initial SDHC
+    _fmi_uR7_CMD = 1;
+    u32CmdTimeOut = 5000;
+
+    i = eMMC_CmdAndRsp(pSD, 8, 0x00000155, u32CmdTimeOut);
+    if (i == 0)
+    {
+        // SD 2.0
+        eMMC_CmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
+        _fmi_uR3_CMD = 1;
+        eMMC_CmdAndRsp(pSD, 41, 0x40ff8000, u32CmdTimeOut); // 2.7v-3.6v
+        resp = inpw(REG_FMI_EMMCRESP0);
+
+        while (!(resp & 0x00800000))        // check if card is ready
+        {
+            eMMC_CmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
+            _fmi_uR3_CMD = 1;
+            eMMC_CmdAndRsp(pSD, 41, 0x40ff8000, u32CmdTimeOut); // 3.0v-3.4v
+            resp = inpw(REG_FMI_EMMCRESP0);
+        }
+        if (resp & 0x00400000)
+            pSD->CardType = EMMC_TYPE_SD_HIGH;
+        else
+            pSD->CardType = EMMC_TYPE_SD_LOW;
+    }
+    else
+    {
+        // SD 1.1
+        eMMC_Command(pSD, 0, 0);        // reset all cards
+        for (i = 0x100; i > 0; i--);
+
+        i = eMMC_CmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
+        if (i == 2)     // MMC memory
+        {
+
+            eMMC_Command(pSD, 0, 0);        // reset
+            for (i = 0x100; i > 0; i--);
+
+            _fmi_uR3_CMD = 1;
+
+            if (eMMC_CmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut) != 2)    // eMMC memory
+            {
+                resp = inpw(REG_FMI_EMMCRESP0);
+                while (!(resp & 0x00800000))        // check if card is ready
+                {
+                    _fmi_uR3_CMD = 1;
+
+                    eMMC_CmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut);      // high voltage
+                    resp = inpw(REG_FMI_EMMCRESP0);
+                }
+
+                if (resp & 0x00400000)
+                    pSD->CardType = EMMC_TYPE_EMMC;
+                else
+                    pSD->CardType = EMMC_TYPE_MMC;
+            }
+            else
+            {
+                pSD->CardType = EMMC_TYPE_UNKNOWN;
+                return EMMC_ERR_DEVICE;
+            }
+        }
+        else if (i == 0)     // SD Memory
+        {
+            _fmi_uR3_CMD = 1;
+            eMMC_CmdAndRsp(pSD, 41, 0x00ff8000, u32CmdTimeOut); // 3.0v-3.4v
+            resp = inpw(REG_FMI_EMMCRESP0);
+            while (!(resp & 0x00800000))        // check if card is ready
+            {
+                eMMC_CmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
+                _fmi_uR3_CMD = 1;
+                eMMC_CmdAndRsp(pSD, 41, 0x00ff8000, u32CmdTimeOut); // 3.0v-3.4v
+                resp = inpw(REG_FMI_EMMCRESP0);
+            }
+            pSD->CardType = EMMC_TYPE_SD_LOW;
+        }
+        else
+        {
+            pSD->CardType = EMMC_TYPE_UNKNOWN;
+            return EMMC_INIT_ERROR;
+        }
+    }
+
+    // CMD2, CMD3
+    if (pSD->CardType != EMMC_TYPE_UNKNOWN)
+    {
+        eMMC_CmdAndRsp2(pSD, 2, 0x00, CIDBuffer);
+        if ((pSD->CardType == EMMC_TYPE_MMC) || (pSD->CardType == EMMC_TYPE_EMMC))
+        {
+            if ((status = eMMC_CmdAndRsp(pSD, 3, 0x10000, 0)) != 0)        // set RCA
+                return status;
+            pSD->RCA = 0x10000;
+        }
+        else
+        {
+            if ((status = eMMC_CmdAndRsp(pSD, 3, 0x00, 0)) != 0)       // get RCA
+                return status;
+            else
+                pSD->RCA = (inpw(REG_FMI_EMMCRESP0) << 8) & 0xffff0000;
+        }
+    }
+
+#if 0
+    if (pSD->CardType == EMMC_TYPE_SD_HIGH)
+        sysprintf("This is high capacity SD memory card\n");
+    if (pSD->CardType == EMMC_TYPE_SD_LOW)
+        sysprintf("This is standard capacity SD memory card\n");
+    if (pSD->CardType == EMMC_TYPE_EMMC)
+        sysprintf("This is eMMC memory card\n");
+#endif
+    return 0;
+}
+
+
+int eMMC_SwitchToHighSpeed(EMMC_INFO_T *pSD)
+{
+    int volatile status = 0;
+    unsigned short current_comsumption, busy_status0;
+
+    outpw(REG_FMI_DMASA, (unsigned int)_fmi_peMMCBuffer);    // set DMA transfer starting address
+    outpw(REG_FMI_EMMCBLEN, 63);    // 512 bit
+
+    if ((status = eMMC_CmdAndRspDataIn(pSD, 6, 0x00ffff01)) != 0)
+        return 1;
+
+    current_comsumption = _fmi_peMMCBuffer[0] << 8 | _fmi_peMMCBuffer[1];
+    if (!current_comsumption)
+        return 1;
+
+    busy_status0 = _fmi_peMMCBuffer[28] << 8 | _fmi_peMMCBuffer[29];
+
+    if (!busy_status0)   // function ready
+    {
+        outpw(REG_FMI_DMASA, (unsigned int)_fmi_peMMCBuffer);        // set DMA transfer starting address
+        outpw(REG_FMI_EMMCBLEN, 63);    // 512 bit
+
+        if ((status = eMMC_CmdAndRspDataIn(pSD, 6, 0x80ffff01)) != 0)
+            return 1;
+
+        // function change timing: 8 clocks
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+        while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+
+        current_comsumption = _fmi_peMMCBuffer[0] << 8 | _fmi_peMMCBuffer[1];
+        if (!current_comsumption)
+            return 1;
+
+        return 0;
+    }
+    else
+        return 1;
+}
+
+
+int eMMC_SelectCardType(EMMC_INFO_T *pSD)
+{
+    int volatile status = 0;
+    //unsigned int arg;
+
+    if ((status = eMMC_CmdAndRsp(pSD, 7, pSD->RCA, 0)) != 0)
+        return status;
+
+    eMMC_CheckRB();
+
+    // if SD card set 4bit
+    if (pSD->CardType == EMMC_TYPE_SD_HIGH)
+    {
+        _fmi_peMMCBuffer = (unsigned char *)((unsigned int)_fmi_uceMMCBuffer);
+        outpw(REG_FMI_DMASA, (unsigned int)_fmi_peMMCBuffer);    // set DMA transfer starting address
+        outpw(REG_FMI_EMMCBLEN, 0x07);  // 64 bit
+
+        if ((status = eMMC_CmdAndRsp(pSD, 55, pSD->RCA, 0)) != 0)
+            return status;
+        if ((status = eMMC_CmdAndRspDataIn(pSD, 51, 0x00)) != 0)
+            return status;
+
+        if ((_fmi_uceMMCBuffer[0] & 0xf) == 0x2)
+        {
+            status = eMMC_SwitchToHighSpeed(pSD);
+            if (status == 0)
+            {
+                /* divider */
+                eMMC_Set_clock(SDHC_FREQ);
+            }
+        }
+
+        if ((status = eMMC_CmdAndRsp(pSD, 55, pSD->RCA, 0)) != 0)
+            return status;
+        if ((status = eMMC_CmdAndRsp(pSD, 6, 0x02, 0)) != 0)   // set bus width
+            return status;
+
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_DBW_Msk);
+    }
+    else if (pSD->CardType == EMMC_TYPE_SD_LOW)
+    {
+        _fmi_peMMCBuffer = (unsigned char *)((unsigned int)_fmi_uceMMCBuffer);
+        outpw(REG_FMI_DMASA, (unsigned int) _fmi_peMMCBuffer); // set DMA transfer starting address
+        outpw(REG_FMI_EMMCBLEN, 0x07);  // 64 bit
+
+        if ((status = eMMC_CmdAndRsp(pSD, 55, pSD->RCA, 0)) != 0)
+            return status;
+        if ((status = eMMC_CmdAndRspDataIn(pSD, 51, 0x00)) != 0)
+            return status;
+
+        // set data bus width. ACMD6 for SD card, SDCR_DBW for host.
+        if ((status = eMMC_CmdAndRsp(pSD, 55, pSD->RCA, 0)) != 0)
+            return status;
+
+        if ((status = eMMC_CmdAndRsp(pSD, 6, 0x02, 0)) != 0)   // set bus width
+            return status;
+
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_DBW_Msk);
+    }
+    else if (pSD->CardType == EMMC_TYPE_MMC)
+    {
+
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) & ~FMI_EMMCCTL_DBW_Msk);
+
+    }
+    else if (pSD->CardType == EMMC_TYPE_EMMC)
+    {
+
+        //--- sent CMD6 to MMC card to set bus width to 4 bits mode, skymedi only support 1-bit
+        // set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode)
+//         arg = (3 << 24) | (183 << 16) | (1 << 8);
+//         if ((status = eMMC_CmdAndRsp(pSD, 6, arg, 0)) != 0)
+//             return status;
+//         eMMC_CheckRB();
+
+//         outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL)| FMI_EMMCCTL_DBW_Msk);
+        outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) & ~FMI_EMMCCTL_DBW_Msk);
+    }
+
+    if ((status = eMMC_CmdAndRsp(pSD, 16, FMI_BLOCK_SIZE, 0)) != 0) // set block length
+        return status;
+    outpw(REG_FMI_EMMCBLEN, FMI_BLOCK_SIZE - 1);           // set the block size
+
+    eMMC_Command(pSD, 7, 0);
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+
+    outpw(REG_FMI_EMMCINTEN, inpw(REG_FMI_EMMCINTEN) | FMI_EMMCINTEN_BLKDIEN_Msk);
+
+    return 0;
+}
+
+void eMMC_Get_info(EMMC_INFO_T *pSD)
+{
+    unsigned int R_LEN, C_Size, MULT, size;
+    unsigned int Buffer[4];
+    unsigned char *ptr;
+
+    eMMC_CmdAndRsp2(pSD, 9, pSD->RCA, Buffer);
+
+    if ((pSD->CardType == EMMC_TYPE_MMC) || (pSD->CardType == EMMC_TYPE_EMMC))
+    {
+        // for MMC/eMMC card
+        if ((Buffer[0] & 0xc0000000) == 0xc0000000)
+        {
+            // CSD_STRUCTURE [127:126] is 3
+            // CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB
+            eMMC_CmdAndRsp(pSD, 7, pSD->RCA, 0);
+
+            ptr = (unsigned char *)((unsigned int)_fmi_uceMMCBuffer);
+            outpw(REG_FMI_DMASA, (unsigned int)ptr);  // set DMA transfer starting address
+            outpw(REG_FMI_EMMCBLEN, 511);  // read 512 bytes for EXT_CSD
+
+            if (eMMC_CmdAndRspDataIn(pSD, 8, 0x00) != 0)
+                return;
+
+            eMMC_Command(pSD, 7, 0);
+            outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+            while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+
+            pSD->totalSectorN = (*(unsigned int *)(ptr + 212));
+            pSD->diskSize = pSD->totalSectorN / 2;
+        }
+        else
+        {
+            // CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB
+            R_LEN = (Buffer[1] & 0x000f0000) >> 16;
+            C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
+            MULT = (Buffer[2] & 0x00038000) >> 15;
+            size = (C_Size + 1) * (1 << (MULT + 2)) * (1 << R_LEN);
+
+            pSD->diskSize = size / 1024;
+            pSD->totalSectorN = size / 512;
+        }
+    }
+    else
+    {
+        if (Buffer[0] & 0xc0000000)
+        {
+            C_Size = ((Buffer[1] & 0x0000003f) << 16) | ((Buffer[2] & 0xffff0000) >> 16);
+            size = (C_Size + 1) * 512;  // Kbytes
+
+            pSD->diskSize = size;
+            pSD->totalSectorN = size << 1;
+        }
+        else
+        {
+            R_LEN = (Buffer[1] & 0x000f0000) >> 16;
+            C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
+            MULT = (Buffer[2] & 0x00038000) >> 15;
+            size = (C_Size + 1) * (1 << (MULT + 2)) * (1 << R_LEN);
+
+            pSD->diskSize = size / 1024;
+            pSD->totalSectorN = size / 512;
+        }
+    }
+    pSD->sectorSize = 512;
+    //sysprintf("The size is %d KB\n", pSD->diskSize);
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ *  @brief  This function use to tell FMI eMMC engine clock.
+ *
+ *  @param[in]  u32Clock   Set current eMMC engine clock
+ *
+ *  @return None
+ */
+void FMI_SetReferenceClock(unsigned int u32Clock)
+{
+    gFMIReferenceClock = u32Clock;  // kHz
+}
+
+/**
+ *  @brief  This function use to reset FMI eMMC function.
+ *
+ *  @return None
+ */
+void eMMC_Open(void)
+{
+    // enable DMAC
+    outpw(REG_FMI_DMACTL, FMI_DMACTL_DMARST_Msk);
+    while (inpw(REG_FMI_DMACTL) & FMI_DMACTL_DMARST_Msk);
+
+    outpw(REG_FMI_DMACTL, FMI_DMACTL_DMAEN_Msk);
+
+    //Reset Global
+    outpw(REG_FMI_CTL, FMI_CTL_CTLRST_Msk);
+    while (inpw(REG_FMI_CTL) & FMI_CTL_CTLRST_Msk);
+
+    // enable eMMC
+    outpw(REG_FMI_CTL, FMI_CTL_EMMCEN_Msk);
+
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CTLRST_Msk);
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CTLRST_Msk);
+
+    memset(&eMMC, 0, sizeof(EMMC_INFO_T));
+    eMMC.IsCardInsert = 1;
+}
+
+/**
+ *  @brief  This function use to initial eMMC card.
+ *
+ *  @return None
+ */
+void eMMC_Probe(void)
+{
+    // Disable FMI interrupt
+    outpw(REG_FMI_INTEN, 0);
+
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) & ~(FMI_EMMCCTL_SDNWR_Msk | FMI_EMMCCTL_BLKCNT_Msk | FMI_EMMCCTL_DBW_Msk));
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | (0x09 << FMI_EMMCCTL_SDNWR_Pos) | (0x01 << FMI_EMMCCTL_BLKCNT_Pos));
+
+    if (eMMC_Init(&eMMC) < 0)
+        return;
+
+    /* divider */
+    if ((eMMC.CardType == EMMC_TYPE_MMC) || (eMMC.CardType == EMMC_TYPE_EMMC))
+        eMMC_Set_clock(MMC_FREQ);
+    else
+        eMMC_Set_clock(SD_FREQ);
+
+    eMMC_Get_info(&eMMC);
+
+    if (eMMC_SelectCardType(&eMMC))
+        return;
+
+    emmc_ok = 1;
+}
+
+/**
+ *  @brief  This function use to read data from eMMC card.
+ *
+ *  @param[out]    pu8BufAddr    The buffer to receive the data from eMMC card.
+ *  @param[in]     u32StartSec   The start read sector address.
+ *  @param[in]     u32SecCount   The the read sector number of data
+ *
+ *  @return None
+ */
+unsigned int eMMC_Read(unsigned char *pu8BufAddr, unsigned int u32StartSec, unsigned int u32SecCount)
+{
+    char volatile bIsSendCmd = FALSE;
+    unsigned int volatile reg;
+    int volatile i, loop, status;
+    unsigned int blksize = FMI_BLOCK_SIZE;
+
+    EMMC_INFO_T *pSD;
+    pSD = &eMMC;
+
+    //--- check input parameters
+    if (u32SecCount == 0)
+        return EMMC_SELECT_ERROR;
+
+    if ((status = eMMC_CmdAndRsp(pSD, 7, pSD->RCA, 0)) != 0)
+        return status;
+    eMMC_CheckRB();
+
+    outpw(REG_FMI_EMMCBLEN, blksize - 1);       // the actual byte count is equal to (BLEN+1)
+
+    if ((pSD->CardType == EMMC_TYPE_SD_HIGH) || (pSD->CardType == EMMC_TYPE_EMMC))
+        outpw(REG_FMI_EMMCCMD, u32StartSec);
+    else
+        outpw(REG_FMI_EMMCCMD, u32StartSec * blksize);
+
+    outpw(REG_FMI_DMASA, (unsigned int)pu8BufAddr);
+
+    loop = u32SecCount / 255;
+    for (i = 0; i < loop; i++)
+    {
+        _fmi_eMMCDataReady = FALSE;
+
+        reg = inpw(REG_FMI_EMMCCTL) & ~FMI_EMMCCTL_CMDCODE_Msk;
+        reg = reg | 0xff0000;
+        if (bIsSendCmd == FALSE)
+        {
+            outpw(REG_FMI_EMMCCTL, reg | (18 << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk | FMI_EMMCCTL_DIEN_Msk));
+            bIsSendCmd = TRUE;
+        }
+        else
+            outpw(REG_FMI_EMMCCTL, reg | FMI_EMMCCTL_DIEN_Msk);
+
+        while (!_fmi_eMMCDataReady)
+        {
+//             if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_BLKDIF_Msk) && (!(inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_DIEN_Msk))) {
+//                 outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_BLKDIF_Msk);
+//                 break;
+//             }
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+
+        if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC7_Msk))      // check CRC7
+        {
+            return EMMC_CRC7_ERROR;
+        }
+
+        if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC16_Msk))     // check CRC16
+        {
+            return EMMC_CRC16_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255;
+    if (loop != 0)
+    {
+        _fmi_eMMCDataReady = FALSE;
+
+        reg = inpw(REG_FMI_EMMCCTL) & (~FMI_EMMCCTL_CMDCODE_Msk);
+        reg = reg & (~FMI_EMMCCTL_BLKCNT_Msk);
+        reg |= (loop << 16);
+
+        if (bIsSendCmd == FALSE)
+        {
+            outpw(REG_FMI_EMMCCTL, reg | (18 << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk | FMI_EMMCCTL_DIEN_Msk));
+            bIsSendCmd = TRUE;
+        }
+        else
+            outpw(REG_FMI_EMMCCTL, reg | FMI_EMMCCTL_DIEN_Msk);
+
+        while (!_fmi_eMMCDataReady)
+        {
+//             if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_BLKDIF_Msk) && (!(inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_DIEN_Msk))) {
+//                 outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_BLKDIF_Msk);
+//                 break;
+//             }
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+
+        if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC7_Msk))      // check CRC7
+        {
+            return EMMC_CRC7_ERROR;
+        }
+
+        if (!(inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRC16_Msk))     // check CRC16
+        {
+            return EMMC_CRC16_ERROR;
+        }
+    }
+
+    if (eMMC_CmdAndRsp(pSD, 12, 0, 0))      // stop command
+    {
+        //sysprintf("stop command fail !!\n");
+        return EMMC_CRC7_ERROR;
+    }
+    eMMC_CheckRB();
+
+    eMMC_Command(pSD, 7, 0);
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+
+    return 0;
+}
+
+
+/**
+ *  @brief  This function use to write data to eMMC card.
+ *
+ *  @param[in]    pu8BufAddr    The buffer to send the data to SD card.
+ *  @param[in]    u32StartSec   The start write sector address.
+ *  @param[in]    u32SecCount   The the write sector number of data.
+ *
+ *  @return   - \ref EMMC_SELECT_ERROR  u32SecCount is zero.
+ *            - \ref EMMC_NO_CARD  SD card be removed.
+ *            - \ref EMMC_CRC_ERROR  CRC error happen.
+ *            - \ref EMMC_CRC7_ERROR  CRC7 error happen.
+ *            - \ref Successful  Write data to eMMC card success.
+ */
+unsigned int eMMC_Write(unsigned char *pu8BufAddr, unsigned int u32StartSec, unsigned int u32SecCount)
+{
+    char volatile bIsSendCmd = FALSE;
+    unsigned int volatile reg;
+    int volatile i, loop, status;
+
+    EMMC_INFO_T *pSD;
+    pSD = &eMMC;
+
+    //--- check input parameters
+    if (u32SecCount == 0)
+        return EMMC_SELECT_ERROR;
+
+    if ((status = eMMC_CmdAndRsp(pSD, 7, pSD->RCA, 0)) != 0)
+        return status;
+
+    eMMC_CheckRB();
+
+    // According to SD Spec v2.0/ eMMC v4.4, the write CMD block size MUST be 512, and the start address MUST be 512*n.
+    outpw(REG_FMI_EMMCBLEN, FMI_BLOCK_SIZE - 1);           // set the block size
+
+    if ((pSD->CardType == EMMC_TYPE_SD_HIGH) || (pSD->CardType == EMMC_TYPE_EMMC))
+        outpw(REG_FMI_EMMCCMD, u32StartSec);
+    else
+        outpw(REG_FMI_EMMCCMD, u32StartSec * FMI_BLOCK_SIZE);  // set start address for CMD
+
+    outpw(REG_FMI_DMASA, (unsigned int)pu8BufAddr);
+    loop = u32SecCount / 255;   // the maximum block count is 0xFF=255
+    for (i = 0; i < loop; i++)
+    {
+        _fmi_eMMCDataReady = FALSE;
+
+        reg = inpw(REG_FMI_EMMCCTL) & 0xff00c080;
+        reg = reg | 0xff0000;
+        if (!bIsSendCmd)
+        {
+            outpw(REG_FMI_EMMCCTL, reg | (25 << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk | FMI_EMMCCTL_DOEN_Msk));
+            bIsSendCmd = TRUE;
+        }
+        else
+            outpw(REG_FMI_EMMCCTL, reg | FMI_EMMCCTL_DOEN_Msk);
+
+        while (!_fmi_eMMCDataReady)
+        {
+//             if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_BLKDIF_Msk) && (!(inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_DOEN_Msk))) {
+//                 outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_BLKDIF_Msk);
+//                 break;
+//             }
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+
+        if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRCIF_Msk) != 0)     // check CRC
+        {
+            outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_CRCIF_Msk);
+            return EMMC_CRC_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255;
+    if (loop != 0)
+    {
+        _fmi_eMMCDataReady = FALSE;
+
+        reg = (inpw(REG_FMI_EMMCCTL) & 0xff00c080) | (loop << 16);
+        if (!bIsSendCmd)
+        {
+            outpw(REG_FMI_EMMCCTL, reg | (25 << 8) | (FMI_EMMCCTL_COEN_Msk | FMI_EMMCCTL_RIEN_Msk | FMI_EMMCCTL_DOEN_Msk));
+            bIsSendCmd = TRUE;
+        }
+        else
+            outpw(REG_FMI_EMMCCTL, reg | FMI_EMMCCTL_DOEN_Msk);
+
+        while (!_fmi_eMMCDataReady)
+        {
+//             if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_BLKDIF_Msk) && (!(inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_DOEN_Msk))) {
+//                 outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_BLKDIF_Msk);
+//                 break;
+//             }
+            if (pSD->IsCardInsert == FALSE)
+                return EMMC_NO_CARD;
+        }
+
+        if ((inpw(REG_FMI_EMMCINTSTS) & FMI_EMMCINTSTS_CRCIF_Msk) != 0)     // check CRC
+        {
+            outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_CRCIF_Msk);
+            return EMMC_CRC_ERROR;
+        }
+    }
+    outpw(REG_FMI_EMMCINTSTS, FMI_EMMCINTSTS_CRCIF_Msk);
+
+    if (eMMC_CmdAndRsp(pSD, 12, 0, 0))      // stop command
+    {
+        return EMMC_CRC7_ERROR;
+    }
+    eMMC_CheckRB();
+
+    eMMC_Command(pSD, 7, 0);
+    outpw(REG_FMI_EMMCCTL, inpw(REG_FMI_EMMCCTL) | FMI_EMMCCTL_CLK8OEN_Msk);
+    while (inpw(REG_FMI_EMMCCTL) & FMI_EMMCCTL_CLK8OEN_Msk);
+
+    return 0;
+}
+
+
+/*@}*/ /* end of group N9H30_FMI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_FMI_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_gpio.c

@@ -0,0 +1,500 @@
+/**************************************************************************//**
+* @file     gpio.c
+* @version  V1.00
+* @brief    N9H30 GPIO driver source file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_gpio.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup N9H30_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set GPIO Port
+ *
+ * @param[in]   port       GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bitMap     GPIO port. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     This function is used to set GPIO port output data.
+ */
+INT32 GPIO_Set(GPIO_PORT port, UINT32 bitMap)
+{
+    INT32 offset;
+    INT32 reg;
+
+    offset = (INT32)port;
+
+    reg = inpw(REG_GPIOA_DATAOUT + offset);
+    reg = reg | bitMap;
+    outpw(REG_GPIOA_DATAOUT + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+/**
+* @brief       Clear GPIO port OUT Data
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bitMap      GPIO port data. It could be 0x00 ~ 0xFF.
+*
+* @retval      <0          Fail
+* @retval      0           Success
+*
+* @details     Clear GPIO port output data to 0.
+*/
+INT32 GPIO_Clr(GPIO_PORT port, UINT32 bitMap)
+{
+    INT32 offset;
+    INT32 reg;
+
+    offset = (INT32)port;
+
+    reg = inpw(REG_GPIOA_DATAOUT + offset);
+    reg = reg & (~bitMap);
+    outpw(REG_GPIOA_DATAOUT + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+
+
+/**
+ * @brief       Open GPIO bit
+ *
+ * @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ * @param[in]   direction   GPIO direction. It could be \ref DIR_INPUT or \ref DIR_OUTPUT
+ * @param[in]   pull        GPIO pull-up. It could be \ref NO_PULL_UP or \ref PULL_UP
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     This function is used to open gpio pin.
+ */
+INT32 GPIO_OpenBit(GPIO_PORT port, UINT32 bit, GPIO_DIR direction, GPIO_PULL pull)
+{
+    UINT32 reg;
+    UINT32 mask;
+    INT32 offset;
+
+    offset = (INT32)port;
+
+    mask = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DIR + offset);
+    reg = reg & (~mask);
+
+    if (direction == DIR_OUTPUT)
+    {
+        reg = reg | mask;
+    }
+
+    outpw(REG_GPIOA_DIR + offset, reg);
+
+    reg = inpw(REG_GPIOA_PUEN + offset);
+    reg = reg & (~mask);
+
+    if (pull == PULL_UP)
+    {
+        reg = reg | mask;
+        outpw(REG_GPIOA_PUEN + offset, reg);
+    }
+    else if (pull == PULL_DOWN)
+    {
+        reg = reg | mask;
+        outpw(REG_GPIOA_PDEN + offset, reg);
+    }
+    else
+    {
+        outpw(REG_GPIOA_PUEN + offset, reg);
+        outpw(REG_GPIOA_PDEN + offset, reg);
+    }
+
+    return SUCCESSFUL;
+}
+
+/**
+* @brief       Set GPIO pin OUT Data
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+*
+* @retval      <0              Fail
+* @retval      0               Success
+*
+* @details     Set the Data into specified GPIO pin.
+*/
+INT32 GPIO_CloseBit(GPIO_PORT port, UINT32 bit)
+{
+    UINT32 reg;
+    UINT32 mask;
+    INT32 offset;
+
+    offset = (INT32)port;
+    mask = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DIR + offset);
+    reg = reg & (~mask);
+    outpw(REG_GPIOA_DIR + offset, reg);
+
+    reg = inpw(REG_GPIOA_PUEN + offset);
+    reg = reg & (~mask);
+    outpw(REG_GPIOA_PUEN + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+
+/**
+ * @brief       Set GPIO pin OUT Data
+ *
+ * @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bit          GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     Set the Data into specified GPIO pin.
+ */
+INT32 GPIO_SetBit(GPIO_PORT port, UINT32 bit)
+{
+    UINT32 bitMap;
+    INT32 offset;
+    INT32 reg;
+
+    offset = (INT32)port;
+    bitMap = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DATAOUT + offset);
+    reg = reg | bitMap;
+    outpw(REG_GPIOA_DATAOUT + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+/**
+* @brief       Clear GPIO port Interrupt Flag
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bitMap      GPIO port data. It could be 0x00 ~ 0xFF.
+*
+* @retval      <0              Fail
+* @retval      0               Success
+*
+* @details     Clear the interrupt status of specified GPIO port.
+*/
+INT32 GPIO_ClrISR(GPIO_PORT port, UINT32 bitMap)
+{
+    INT32 offset;
+
+    offset = (INT32)port;
+
+    outpw(REG_GPIOA_ISR + offset, bitMap);
+
+    return SUCCESSFUL;
+}
+
+/**
+ * @brief       Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     Clear the interrupt status of specified GPIO pin.
+ */
+INT32 GPIO_ClrISRBit(GPIO_PORT port, UINT32 bit)
+{
+    UINT32 bitMap;
+    INT32 offset;
+
+    offset = (INT32)port;
+    bitMap = (UINT32)bit;
+
+    outpw(REG_GPIOA_ISR + offset, bitMap);
+
+    return SUCCESSFUL;
+}
+
+/**
+* @brief       Clear GPIO pin OUT Data
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+*
+* @retval      <0              Fail
+* @retval      0               Success
+*
+* @details     Set the Data into specified GPIO pin.
+*/
+INT32 GPIO_ClrBit(GPIO_PORT port, UINT32 bit)
+{
+    UINT32 bitMap;
+    INT32 offset;
+    INT32 reg;
+
+    offset = (INT32)port;
+    bitMap = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DATAOUT + offset);
+    reg = reg & (~bitMap);
+    outpw(REG_GPIOA_DATAOUT + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+/**
+* @brief       Read GPIO pin In Data
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+*
+* @retval      1/0         GPIO pin input data.
+*
+* @details     Read the In Data from GPIO pin.
+*/
+INT32 GPIO_ReadBit(GPIO_PORT port, UINT32 bit)
+{
+    UINT32 reg;
+    UINT32 bitMap;
+    INT32 offset;
+
+    offset = (INT32)port;
+    bitMap = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DATAIN + offset);
+
+    return ((reg & bitMap) ? 1 : 0);
+}
+
+/**
+* @brief       Set GPIO pin direction
+*
+* @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+* @param[in]   bit         GPIO pin. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+* @param[in]   direction   GPIO direction. It could be \ref DIR_INPUT, \ref DIR_OUTPUT.
+*
+* @retval      <0              Fail
+* @retval      0               Success
+*
+* @details     Set the GPIO direction into specified GPIO pin.
+*/
+INT32 GPIO_SetBitDir(GPIO_PORT port, UINT32 bit, GPIO_DIR direction)
+{
+    UINT32 reg;
+    UINT32 bitMap;
+    INT32 offset;
+
+    offset = (INT32)port;
+    bitMap = (UINT32)bit;
+
+    reg = inpw(REG_GPIOA_DIR + offset);
+    reg = reg & (~bitMap);
+
+    if (direction == DIR_OUTPUT)
+    {
+        reg = reg | bitMap;
+    }
+
+    outpw(REG_GPIOA_DIR + offset, reg);
+
+    return SUCCESSFUL;
+}
+
+/**
+ * @brief       Enable GPIO trigger type.
+ *
+ * @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bitMap      GPIO port. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ * @param[in]   triggerType The triggerType of specified GPIO pin. It could be \n
+ *                          \ref RISING, \ref FALLING, \ref BOTH_EDGE, \ref HIGH, \ref LOW.
+ *
+ * @retval      <0          Fail
+ * @retval      0           Success
+ *
+ * @details     This function is used to enable trigger type.
+ */
+INT32 GPIO_EnableTriggerType(GPIO_PORT port, UINT32 bitMap, GPIO_TRIGGER_TYPE triggerType)
+{
+    UINT32 reg;
+    INT32 offset;
+
+    offset = (INT32)port;
+
+    switch (triggerType)
+    {
+    case LOW:
+        reg = inpw(REG_GPIOA_IMD + offset);
+        outpw(REG_GPIOA_IMD + offset, reg | bitMap);
+
+        reg = inpw(REG_GPIOA_IREN + offset);
+        outpw(REG_GPIOA_IREN + offset, reg & ~bitMap);
+
+        reg = inpw(REG_GPIOA_IFEN + offset);
+        outpw(REG_GPIOA_IFEN + offset, reg  | bitMap);
+        break;
+    case HIGH:
+        reg = inpw(REG_GPIOA_IMD + offset);
+        outpw(REG_GPIOA_IMD + offset, reg | bitMap);
+
+        reg = inpw(REG_GPIOA_IREN + offset);
+        outpw(REG_GPIOA_IREN + offset, reg | bitMap);
+
+        reg = inpw(REG_GPIOA_IFEN + offset);
+        outpw(REG_GPIOA_IFEN + offset, reg & ~bitMap);
+        break;
+    case FALLING:
+        reg = inpw(REG_GPIOA_IMD + offset);
+        outpw(REG_GPIOA_IMD + offset, reg & ~bitMap);
+
+        reg = inpw(REG_GPIOA_IREN + offset);
+        outpw(REG_GPIOA_IREN + offset, reg & ~bitMap);
+
+        reg = inpw(REG_GPIOA_IFEN + offset);
+        outpw(REG_GPIOA_IFEN + offset, reg  | bitMap);
+        break;
+    case RISING:
+        reg = inpw(REG_GPIOA_IMD + offset);
+        outpw(REG_GPIOA_IMD + offset, reg & ~bitMap);
+
+        reg = inpw(REG_GPIOA_IREN + offset);
+        outpw(REG_GPIOA_IREN + offset, reg | bitMap);
+
+        reg = inpw(REG_GPIOA_IFEN + offset);
+        outpw(REG_GPIOA_IFEN + offset, reg & ~bitMap);
+        break;
+    case BOTH_EDGE:
+        reg = inpw(REG_GPIOA_IMD + offset);
+        outpw(REG_GPIOA_IMD + offset, reg & ~bitMap);
+
+        reg = inpw(REG_GPIOA_IREN + offset);
+        outpw(REG_GPIOA_IREN + offset, reg | bitMap);
+
+        reg = inpw(REG_GPIOA_IFEN + offset);
+        outpw(REG_GPIOA_IFEN + offset, reg | bitMap);
+        break;
+    }
+    return SUCCESSFUL;
+}
+
+/**
+ * @brief       Disable GPIO trigger type.
+ *
+ * @param[in]   port        GPIO port. It could be \ref GPIOA, \ref GPIOB, ... or \ref GPIOJ
+ * @param[in]   bitMap      GPIO port. It could be \ref BIT0 \ref BIT1, ... or \ref BIT31
+ *
+ * @retval      <0          Fail
+ * @retval      0           Success
+ *
+ * @details     This function is used to disable trigger type.
+ */
+INT32 GPIO_DisableTriggerType(GPIO_PORT port, UINT32 bitMap)
+{
+    UINT32 reg;
+    INT32 offset;
+
+    offset = (INT32)port;
+
+    reg = inpw(REG_GPIOA_IMD + offset);
+    outpw(REG_GPIOA_IMD + offset, reg & ~bitMap);
+
+    reg = inpw(REG_GPIOA_IREN + offset);
+    outpw(REG_GPIOA_IREN + offset, reg & ~bitMap);
+
+    reg = inpw(REG_GPIOA_IFEN + offset);
+    outpw(REG_GPIOA_IFEN + offset, reg & ~bitMap);
+
+    return SUCCESSFUL;
+}
+
+/**
+ * @brief       Enable GPIO De-bounce Function
+ *
+ * @param[in]   debounceClkSel        The de-bounce sampling cycle selection. It could be 0~0xF.  \n
+ *                                     0 = Sample interrupt input once per 1 clocks. \n
+ *                                     1 = Sample interrupt input once per 2 clocks. \n
+ *                                     2 = Sample interrupt input once per 4 clocks. \n
+ *                                     3 = Sample interrupt input once per 8 clocks. \n
+ *                                     4 = Sample interrupt input once per 16 clocks. \n
+ *                                     5 = Sample interrupt input once per 32 clocks. \n
+ *                                     6 = Sample interrupt input once per 64 clocks. \n
+ *                                     7 = Sample interrupt input once per 128 clocks. \n
+ *                                     8 = Sample interrupt input once per 256 clocks. \n
+ *                                     9 = Sample interrupt input once per 2*256 clocks. \n
+ *                                    10 = Sample interrupt input once per 4*256 clocks. \n
+ *                                    11 = Sample interrupt input once per 8*256 clocks. \n
+ *                                    12 = Sample interrupt input once per 16*256 clocks. \n
+ *                                    13 = Sample interrupt input once per 32*256 clocks. \n
+ *                                    14 = Sample interrupt input once per 64*256 clocks. \n
+ *                                    15 = Sample interrupt input once per 128*256 clocks
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     Enable the interrupt de-bounce function of specified GPIO.
+ */
+INT32 GPIO_EnableDebounce(INT32 debounceClkSel)
+{
+    UINT32 reg;
+
+    reg = inpw(REG_GPIO_DBNCECON);
+
+    /* Setting the debounce timing */
+    reg = ((reg & ~0xf) | debounceClkSel);
+
+    /* Enable the debounce function */
+    reg = reg | 0x20;
+    outpw(REG_GPIO_DBNCECON, reg);
+
+    return SUCCESSFUL;
+}
+
+/**
+ * @brief       Disable GPIO De-bounce Function.
+ *
+ * @retval      <0              Fail
+ * @retval      0               Success
+ *
+ * @details     Disable the interrupt de-bounce function of specified GPIO.
+ */
+INT32 GPIO_DisableDebounce(void)
+{
+    UINT32 reg;
+
+    reg = inpw(REG_GPIO_DBNCECON);
+
+    /* Setting the debounce timing */
+    reg = ((reg & ~0xf));
+
+    /* Enable the debounce function */
+    reg = reg | 0x20;
+    outpw(REG_GPIO_DBNCECON, reg);
+
+    return SUCCESSFUL;
+}
+
+/*@}*/ /* end of group N9H30_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_GPIO_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_i2s.c

@@ -0,0 +1,461 @@
+/**************************************************************************//**
+* @file     i2s.c
+* @brief    N9H30 I2S driver source file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_i2s.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup N9H30_I2S_EXPORTED_CONSTANTS I2S Exported Constants
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+typedef uint32_t (AU_CB_FUNC_T)(uint32_t);
+
+static AU_CB_FUNC_T *g_fnPlayCallBack;
+static AU_CB_FUNC_T *g_fnRecCallBack;
+static uint8_t i2sOpened = 0;
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group N9H30_I2S_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+/**
+  * @brief Start to play
+  * @param None
+  * @return None
+  */
+static void i2sStartPlay(void)
+{
+    /* start playing */
+    //sysprintf("IIS start playing...\n");
+
+    outpw(REG_ACTL_PSR, 0x1);
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 5));
+}
+
+/**
+  * @brief Stop to play
+  * @param None
+  * @return None
+  */
+static void i2sStopPlay(void)
+{
+    //sysprintf("IIS stop playing\n");
+
+    /* stop playing */
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 5));
+}
+
+/**
+  * @brief Start to record
+  * @param None
+  * @return None
+  */
+static void i2sStartRecord(void)
+{
+    /* start recording */
+    //sysprintf("IIS start recording...\n");
+
+    outpw(REG_ACTL_RSR, 0x1);
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 6));
+}
+
+/**
+  * @brief Stop to record
+  * @param None
+  * @return None
+  */
+static void i2sStopRecord(void)
+{
+    //sysprintf("I2S stop recording\n");
+
+    /* stop recording */
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 6));
+}
+
+/**
+  * @brief Delay function
+  * @param None
+  * @return None
+  */
+static void Delay(int nCnt)
+{
+    int volatile loop;
+    for (loop = 0; loop < nCnt * 10; loop++);
+}
+
+/**
+  * @brief Interrupt service routine for i2s
+  * @param None
+  * @return None
+  */
+static void i2sISR(void)
+{
+    uint8_t u8SN;
+
+    if (inpw(REG_ACTL_CON) & (1 << 10))
+    {
+        outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 10)); //Clear TX INT
+
+        if (inpw(REG_ACTL_PSR) & (1 << 4))
+        {
+            outpw(REG_ACTL_PSR, (1 << 4));
+            //sysprintf("\ndebug:DMA_COUNTER_IRQ occur");
+        }
+
+        if (inpw(REG_ACTL_PSR) & (1 << 3))
+        {
+            outpw(REG_ACTL_PSR, (1 << 3));
+            //sysprintf("\ndebug:DMA_DATA_ZERO_IRQ occur");
+        }
+
+        if (inpw(REG_ACTL_PSR) & 0x1)
+        {
+            outpw(REG_ACTL_PSR, 0x1);
+            u8SN = (inpw(REG_ACTL_PSR) >> 5) & 0x7;
+            g_fnPlayCallBack(u8SN);
+        }
+    }
+
+    if (inpw(REG_ACTL_CON) & (1 << 11))
+    {
+        outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 11)); //Clear RX INT
+
+        if (inpw(REG_ACTL_RSR) & 0x1)
+        {
+            outpw(REG_ACTL_RSR, 0x1);
+            u8SN = (inpw(REG_ACTL_RSR) >> 5) & 0x7;
+            g_fnRecCallBack(u8SN);
+        }
+    }
+}
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/**
+  * @brief Open i2s interface
+  * @return open status
+  * @retval I2S_ERR_BUSY error.
+  * @retval 0 success.
+  */
+int32_t i2sOpen(void)
+{
+    if (i2sOpened)
+        return I2S_ERR_BUSY;
+
+    /* reset audio interface */
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 16));
+    Delay(100);
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 16));
+    Delay(100);
+
+    /* reset IIS interface */
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x1);
+    Delay(100);
+    outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x1);
+    Delay(100);
+
+    outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 21) | (1 << 20));
+
+    i2sOpened = 1;
+
+    return 0;
+}
+
+/**
+  * @brief Close i2s interface
+  * @return None
+  */
+void i2sClose(void)
+{
+    // reset some variables
+    i2sOpened = 0;
+    g_fnPlayCallBack = NULL;
+    g_fnRecCallBack = NULL;
+
+    // reset i2s interface
+    outpw(REG_SYS_AHBIPRST, inpw(REG_SYS_AHBIPRST) | (1 << 8));
+    outpw(REG_SYS_AHBIPRST, inpw(REG_SYS_AHBIPRST) & ~(1 << 8));
+}
+
+/**
+  * @brief Initialize i2s interface and setup interrupt
+  * @return None
+  */
+void i2sInit(void)
+{
+    // enable i2s engine clock
+    outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (1 << 24));
+
+    // enable interrupt and set ISR
+    sysSetInterruptType(ACTL_IRQn, HIGH_LEVEL_SENSITIVE);
+    sysInstallISR(IRQ_LEVEL_1, ACTL_IRQn, (PVOID)i2sISR);
+    sysEnableInterrupt(ACTL_IRQn);
+    sysSetLocalInterrupt(ENABLE_IRQ);
+}
+
+/**
+  * @brief IO control for i2s interface
+  * @param[in] cmd Command for io control, value could be
+  *                                     - \ref I2S_SET_PLAY
+  *                                     - \ref I2S_SET_RECORD
+  *                                     - \ref I2S_SELECT_BLOCK
+  *                                     - \ref I2S_SELECT_BIT
+  *                                     - \ref I2S_SET_PLAY_DMA_INT_SEL
+  *                                     - \ref I2S_SET_REC_DMA_INT_SEL
+  *                                     - \ref I2S_SET_ZEROCROSS
+  *                                     - \ref I2S_SET_DMACOUNTER
+  *                                     - \ref I2S_SET_CHANNEL
+  *                                     - \ref I2S_SET_MODE
+  *                                     - \ref I2S_SET_SPLITDATA
+  *                                     - \ref I2S_SET_DMA_ADDRESS
+  *                                     - \ref I2S_SET_DMA_LENGTH
+  *                                     - \ref I2S_GET_DMA_CUR_ADDRESS
+  *                                     - \ref I2S_SET_I2S_FORMAT
+  *                                     - \ref I2S_SET_I2S_CALLBACKFUN
+  *                                     - \ref I2S_SET_PCMSLOT
+  * @param[in] arg0 argument 0 for io control
+  * @param[in] arg1 argument 1 for io control
+  * @retval I2S_ERR_IO Command error.
+  * @retval 0 success.
+  */
+int32_t i2sIoctl(uint32_t cmd, uint32_t arg0, uint32_t arg1)
+{
+    uint32_t *buf;
+    AU_CB_FUNC_T *ptr;
+
+    switch (cmd)
+    {
+    // #define I2S_START_PLAY  0
+    // #define I2S_STOP_PLAY   1
+    case I2S_SET_PLAY:
+        if (arg0 == I2S_START_PLAY)
+            i2sStartPlay();
+        else
+            i2sStopPlay();
+        break;
+    // #define I2S_START_REC  0
+    // #define I2S_STOP_REC   1
+    case I2S_SET_RECORD:
+        if (arg0 == I2S_START_REC)
+            i2sStartRecord();
+        else
+            i2sStopRecord();
+        break;
+    // #define I2S_BLOCK_I2S  0
+    // #define I2S_BLOCK_PCM   1
+    case I2S_SELECT_BLOCK:
+        if (arg0 == I2S_BLOCK_I2S)
+            outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3) | 0x1);
+        else
+            outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3) | 0x2);
+        break;
+    // #define I2S_BIT_WIDTH_8  0
+    // #define I2S_BIT_WIDTH_16 1
+    // #define I2S_BIT_WIDTH_24 2
+    case I2S_SELECT_BIT:
+        outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x300) | (arg0 << 8));
+        break;
+    // #define I2S_DMA_INT_END         0
+    // #define I2S_DMA_INT_HALF        1
+    // #define I2S_DMA_INT_QUARTER     2
+    // #define I2S_DMA_INT_EIGTH       3
+    case I2S_SET_PLAY_DMA_INT_SEL:
+        outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3000) | (arg0 << 12));
+        break;
+
+    case I2S_SET_REC_DMA_INT_SEL:
+        outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0xc000) | (arg0 << 14));
+        break;
+
+    case I2S_SET_ZEROCROSS:
+        if (arg0 == I2S_ENABLE)
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x8);
+        else
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x8);
+        break;
+
+    case I2S_SET_DMACOUNTER:
+        if (arg0 == I2S_ENABLE)
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x10);
+        else
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x10);
+        break;
+    // #define I2S_CHANNEL_I2S_ONE         2
+    // #define I2S_CHANNEL_I2S_TWO         3
+    // #define I2S_CHANNEL_PCM_TWO         3
+    // #define I2S_CHANNEL_PCM_TWO_SLOT1   0
+    // #define I2S_CHANNEL_PCM_TWO_SLOT0   1
+    // #define I2S_CHANNEL_PCM_ONE_SLOT0   2
+    case I2S_SET_CHANNEL:
+        if (arg0 == I2S_PLAY)
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x3 << 12) | (arg1 << 12));
+        else
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x3 << 14) | (arg1 << 14));
+        break;
+    // #define I2S_MODE_MASTER  0
+    // #define I2S_MODE_SLAVE  1
+    case I2S_SET_MODE:
+        if (arg0 == I2S_MODE_MASTER)
+            outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) & ~(0x1 << 20));
+        else
+            outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) | (0x1 << 20));
+        break;
+
+    case I2S_SET_SPLITDATA:
+        if (arg0 == I2S_ENABLE)
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (0x1 << 20));
+        else
+            outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x1 << 20));
+        break;
+
+    case I2S_SET_DMA_ADDRESS:
+        if (arg0 == I2S_PLAY)
+            outpw(REG_ACTL_PDESB, arg1 | 0x80000000);
+        else if (arg0 == I2S_REC)
+            outpw(REG_ACTL_RDESB, arg1 | 0x80000000);
+        else if (arg0 == PCM_PLAY)
+            outpw(REG_ACTL_PDESB2, arg1 | 0x80000000);
+        else
+            outpw(REG_ACTL_RDESB2, arg1 | 0x80000000);
+        break;
+
+    case I2S_SET_DMA_LENGTH:
+        if (arg0 == I2S_PLAY)
+            outpw(REG_ACTL_PDES_LENGTH, arg1);
+        else
+            outpw(REG_ACTL_RDES_LENGTH, arg1);
+        break;
+
+    case I2S_GET_DMA_CUR_ADDRESS:
+        buf = (uint32_t *)arg0;
+        if (arg0 == I2S_PLAY)
+            *buf = inpw(REG_ACTL_PDESC);
+        else
+            *buf = inpw(REG_ACTL_RDESC);
+        break;
+
+    // #define I2S_FORMAT_I2S  0
+    // #define I2S_FORMAT_MSB  1
+    case I2S_SET_I2S_FORMAT:
+        if (arg0 == I2S_FORMAT_I2S)
+            outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) & ~ 0x8);
+        else
+            outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) | 0x8);
+        break;
+
+    case I2S_SET_I2S_CALLBACKFUN:
+        ptr = (AU_CB_FUNC_T *)arg1;
+        if (arg0 == I2S_PLAY)
+            g_fnPlayCallBack = ptr;
+        else
+            g_fnRecCallBack = ptr;
+        break;
+    // #define PCM_SLOT1_IN        0
+    // #define PCM_SLOT1_OUT       1
+    // #define PCM_SLOT2_IN        2
+    // #define PCM_SLOT2_OUT       3
+    case I2S_SET_PCMSLOT:
+        if (arg0 == PCM_SLOT1_IN)
+            outpw(REG_ACTL_PCMS1ST, (inpw(REG_ACTL_PCMS1ST) & ~0x3ff) | (arg1 & 0x3ff));
+        else if (arg0 == PCM_SLOT1_OUT)
+            outpw(REG_ACTL_PCMS1ST, (inpw(REG_ACTL_PCMS1ST) & ~0x3ff0000) | ((arg1 & 0x3ff) << 16));
+        else if (arg0 == PCM_SLOT2_IN)
+            outpw(REG_ACTL_PCMS2ST, (inpw(REG_ACTL_PCMS2ST) & ~0x3ff) | (arg1 & 0x3ff));
+        else
+            outpw(REG_ACTL_PCMS2ST, (inpw(REG_ACTL_PCMS2ST) & ~0x3ff0000) | ((arg1 & 0x3ff) << 16));
+        break;
+
+    case I2S_SET_PCM_FS_PERIOD:
+        outpw(REG_ACTL_PCMCON, (inpw(REG_ACTL_PCMCON) & ~0x03FF0000 | (((arg0 - 1) & 0x3ff) << 16)));
+        break;
+
+    default:
+        return I2S_ERR_IO;
+    }
+    return 0;
+}
+
+/**
+  * @brief Configure sampling rate for audio
+  * @param[in] u32SourceClockRate source speed to i2s interface
+  * @param[in] u32SampleRate sampling rate
+  * @param[in] u32DataBit data width
+  * @param[in] u32Channel channel number
+  * @return None
+  */
+void i2sSetSampleRate(uint32_t u32SourceClockRate, uint32_t u32SampleRate, uint32_t u32DataBit, uint32_t u32Channel)
+{
+    uint32_t u32BCLKDiv;
+    uint32_t u32MCLK, u32MCLKDiv;
+
+    u32MCLK = (u32SampleRate * 256);
+    u32MCLKDiv = u32SourceClockRate / u32MCLK;
+    outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0x000F0000) | (u32MCLKDiv - 1) << 16);
+
+    u32BCLKDiv = u32MCLK / (u32SampleRate * u32DataBit * u32Channel);
+    u32BCLKDiv = u32BCLKDiv / 2 - 1;
+    outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0xF0) | u32BCLKDiv << 5);
+}
+
+/**
+  * @brief Configure MCLK frequency (master mode)
+  * @param[in] u32SourceClockRate source clock rate
+  * @param[in] u32SampleRate sampling rate
+  * @return None
+  */
+void i2sSetMCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32SampleRate)
+{
+    uint32_t u32MCLK, u32MCLKDiv;
+
+    u32MCLK = (u32SampleRate * 256);
+    u32MCLKDiv = u32SourceClockRate / u32MCLK;
+    outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0x000F0000) | (u32MCLKDiv - 1) << 16);
+}
+
+/**
+  * @brief Configure PCM BCLK frequency (master mode)
+  * @param[in] u32SourceClockRate source clock rate
+  * @param[in] u32Rate target rate
+  * @return None
+  */
+void i2sSetPCMBCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32Rate)
+{
+    uint32_t u32BCLKDiv;
+
+    u32BCLKDiv = (u32SourceClockRate / (2 * u32Rate)) - 1;
+    outpw(REG_ACTL_PCMCON, (inpw(REG_ACTL_PCMCON) & ~0x0000FF00) | (u32BCLKDiv << 8));
+}
+
+
+/*@}*/ /* end of group N9H30_I2S_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_I2S_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_lcd.c

@@ -0,0 +1,764 @@
+/**************************************************************************//**
+* @file     lcd.c
+* @brief    N9H30 LCD driver source file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_lcd.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_LCD_Driver LCD Driver
+  @{
+*/
+
+/** @addtogroup N9H30_LCD_EXPORTED_CONSTANTS LCD Exported Constants
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+/* LCD attributes */
+static VPOST_T DEF_E50A2V1 =
+{
+    800,                            /*!< Panel width */
+    480,                            /*!< Panel height */
+    0,                              /*!< MPU command line low indicator */
+    0,                              /*!< MPU command width */
+    0,                              /*!< MPU bus width */
+    VPOSTB_DATA16or18,              /*!< Display bus width */
+    0,                              /*!< MPU mode */
+    VPOSTB_COLORTYPE_64K,           /*!< Display colors */
+    VPOSTB_DEVICE_SYNC_HIGHCOLOR,   /*!< Type of display panel */
+    0x020d03a0,                     /*!< CRTCSIZE register value */
+    0x01e00320,                     /*!< CRTCDEND register value */
+    0x03250321,                     /*!< CRTCHR register value */
+    0x03780348,                     /*!< CRTCHSYNC register value */
+    0x01f001ed                      /*!< CRTCVR register value */
+};
+
+static VPOST_T DEF_ILI9341_MPU80 =
+{
+    240,                            /*!< Panel width */
+    320,                            /*!< Panel height */
+    VPOSTB_CMDLOW,                  /*!< MPU command line low indicator */
+    VPOSTB_CM16t18HIGH,             /*!< MPU command width */
+    VPOSTB_CMD8,                    /*!< MPU bus width */
+    VPOSTB_DATA16or18,              /*!< Display bus width */
+    VPOSTB_MPU80,                   /*!< MPU mode */
+    VPOSTB_COLORTYPE_64K,           /*!< Display colors */
+    VPOSTB_DEVICE_MPU,              /*!< Type of display panel */
+    0x01600100,                     /*!< CRTCSIZE register value */
+    0x014000F0,                     /*!< CRTCDEND register value */
+    0x00FA00F5,                     /*!< CRTCHR register value */
+    0x00FC00FA,                     /*!< CRTCHSYNC register value */
+    0x01500145                      /*!< CRTCVR register value */
+};
+
+static VPOST_T DEF_LSA40AT9001 =
+{
+    800,                            /*!< Panel width */
+    600,                            /*!< Panel height */
+    0,                              /*!< MPU command line low indicator */
+    0,                              /*!< MPU command width */
+    0,                              /*!< MPU bus width */
+    VPOSTB_DATA16or18,              /*!< Display bus width */
+    0,                              /*!< MPU mode */
+    VPOSTB_COLORTYPE_64K,           /*!< Display colors */
+    VPOSTB_DEVICE_SYNC_HIGHCOLOR,   /*!< Type of display panel */
+    0x02800425,                     /*!< CRTCSIZE register value */
+    0x02580320,                     /*!< CRTCDEND register value */
+    0x032F032A,                     /*!< CRTCHR register value */
+    0x0334032A,                     /*!< CRTCHSYNC register value */
+    0x026C0262                      /*!< CRTCVR register value */
+};
+
+
+static VPOST_T DEF_FW070TFT =
+{
+    800,                            /*!< Panel width */
+    480,                            /*!< Panel height */
+    0,                              /*!< MPU command line low indicator */
+    0,                              /*!< MPU command width */
+    0,                              /*!< MPU bus width */
+    VPOSTB_DATA16or18,              /*!< Display bus width */
+    0,                              /*!< MPU mode */
+    VPOSTB_COLORTYPE_16M,           /*!< Display colors */
+    VPOSTB_DEVICE_SYNC_HIGHCOLOR,   /*!< Type of display panel */
+    0x020d0420,                     /*!< CRTCSIZE register value */
+    0x01e00320,                     /*!< CRTCDEND register value */
+    0x033e0339,                     /*!< CRTCHR register value */
+    0x040c03f8,                     /*!< CRTCHSYNC register value */
+    0x020001f6                      /*!< CRTCVR register value */
+};
+
+/* LCD build-in support list */
+static VPOST_T *DisplayDevList[4] = {&DEF_E50A2V1, &DEF_ILI9341_MPU80, &DEF_LSA40AT9001, &DEF_FW070TFT};
+static VPOST_T curDisplayDev;
+static OSDFORMATEX curOSDDev = {0};
+static LCDFORMATEX curVADev = {0};
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group N9H30_I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+/* For align 32 */
+static uint32_t shift_pointer(uint32_t ptr, uint32_t align)
+{
+    uint32_t alignedPTR;
+    uint32_t remain;
+
+    //printf("pointer position is %x\n",ptr);
+    if ((ptr % align) != 0)
+    {
+        remain = ptr % align;
+        alignedPTR = ptr + (align - remain);
+        return alignedPTR;
+    }
+    return ptr;
+}
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/**
+  * @brief Configure attributes of LCD panel,install interrupt handler and enable LCD engine clock
+  * @param[in] u32DisplayPanelID is panel id to configure.
+  * @return none
+  */
+void vpostLCMInit(uint32_t u32DisplayPanelID)
+{
+    // enable lcd engine clock
+    outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (1 << 25));
+
+    memset((void *)&curDisplayDev, 0, sizeof(curDisplayDev));
+    memcpy((void *)&curDisplayDev, DisplayDevList[u32DisplayPanelID], sizeof(curDisplayDev));
+
+    outpw(REG_LCM_DEV_CTRL,   curDisplayDev.u32CmdLow
+          | curDisplayDev.u32Cmd16t18
+          | curDisplayDev.u32CmdBusWidth
+          | curDisplayDev.u32DataBusWidth
+          | curDisplayDev.u32MPU_Mode
+          | curDisplayDev.u32DisplayColors
+          | curDisplayDev.u32DevType);
+
+    outpw(REG_LCM_CRTC_SIZE,    curDisplayDev.u32Reg_CRTCSIZE);
+    outpw(REG_LCM_CRTC_DEND,    curDisplayDev.u32Reg_CRTCDEND);
+    outpw(REG_LCM_CRTC_HR,      curDisplayDev.u32Reg_CRTCHR);
+    outpw(REG_LCM_CRTC_HSYNC,   curDisplayDev.u32Reg_CRTCHSYNC);
+    outpw(REG_LCM_CRTC_VR,      curDisplayDev.u32Reg_CRTCVR);
+
+}
+
+/**
+  * @brief Query LCM capacity and configuration by ID
+  * @param[in] u32DisplayPanelID is panel id to configure.
+  * @return LCM instance
+  */
+VPOST_T *vpostLCMGetInstance(uint32_t u32DisplayPanelID)
+{
+    if (u32DisplayPanelID > (sizeof(DisplayDevList) / sizeof(VPOST_T *)))
+        return NULL;
+
+    return DisplayDevList[u32DisplayPanelID];
+}
+
+/**
+  * @brief Disable LCD engine
+  * @param none
+  * @return none
+  */
+void vpostLCMDeinit(void)
+{
+    // disable lcd engine clock
+    outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) & ~(1 << 25));
+
+    //sysDisableInterrupt(LCD_IRQn);
+}
+
+/**
+  * @brief Get the pointer of frame buffer
+  * @param none
+  * @return pointer of frame buffer
+  * @retval NULL fail.
+  * @note before calling this function, display width, height and source format must be set first.
+  */
+uint8_t *vpostGetFrameBuffer(void)
+{
+    uint8_t *u8BufPtr;
+    uint8_t u32BytePerPixel;
+
+    if ((curDisplayDev.u32DevWidth == 0) || (curDisplayDev.u32DevHeight == 0))
+        return NULL;
+
+    switch (curVADev.ucVASrcFormat)
+    {
+    case VA_SRC_YUV422:
+    case VA_SRC_YCBCR422:
+    case VA_SRC_RGB565:
+        u32BytePerPixel = 2;
+        break;
+
+    case VA_SRC_RGB666:
+    case VA_SRC_RGB888:
+        u32BytePerPixel = 4;
+        break;
+
+    default:
+        u32BytePerPixel = 2;
+    }
+
+    u8BufPtr = (uint8_t *)malloc((curDisplayDev.u32DevWidth * curDisplayDev.u32DevHeight * u32BytePerPixel) + 32);
+    if (u8BufPtr == NULL)
+        return NULL;
+    u8BufPtr = (uint8_t *)shift_pointer((uint32_t)u8BufPtr, 32);
+
+    outpw(REG_LCM_VA_BADDR0, (uint32_t)((uint32_t)u8BufPtr | 0x80000000));
+    outpw(REG_LCM_VA_FBCTRL, inpw(REG_LCM_VA_FBCTRL) & ~(1 << 30) & ~VPOSTB_DB_EN);
+
+    return (uint8_t *)((uint32_t)u8BufPtr | 0x80000000);
+}
+
+
+/**
+  * @brief Get the pointer of frame buffer
+  * @param[in] u32Cnt is the frame buffer count to allocate. Min value is 1.
+  * @return pointer of frame buffer
+  * @retval NULL fail.
+  * @note before calling this function, display width, height and source format must be set first.
+  */
+uint8_t *vpostGetMultiFrameBuffer(uint32_t u32Cnt)
+{
+    uint8_t *u8BufPtr;
+    uint8_t u32BytePerPixel;
+
+    if ((curDisplayDev.u32DevWidth == 0) || (curDisplayDev.u32DevHeight == 0) || (u32Cnt == 0))
+        return NULL;
+
+    switch (curVADev.ucVASrcFormat)
+    {
+    case VA_SRC_YUV422:
+    case VA_SRC_YCBCR422:
+    case VA_SRC_RGB565:
+        u32BytePerPixel = 2;
+        break;
+
+    case VA_SRC_RGB666:
+    case VA_SRC_RGB888:
+        u32BytePerPixel = 4;
+        break;
+
+    default:
+        u32BytePerPixel = 2;
+    }
+
+    u8BufPtr = (uint8_t *)malloc((curDisplayDev.u32DevWidth * curDisplayDev.u32DevHeight * u32BytePerPixel) * u32Cnt + 32);
+    if (u8BufPtr == NULL)
+        return NULL;
+    u8BufPtr = (uint8_t *)shift_pointer((uint32_t)u8BufPtr, 32);
+
+    outpw(REG_LCM_VA_BADDR0, (uint32_t)((uint32_t)u8BufPtr | 0x80000000));
+    outpw(REG_LCM_VA_FBCTRL, inpw(REG_LCM_VA_FBCTRL) & ~(1 << 30) & ~VPOSTB_DB_EN);
+
+    return (uint8_t *)((uint32_t)u8BufPtr | 0x80000000);
+}
+
+/**
+  * @brief Set active display window
+  * @param[in] u16StartY is y start position
+  * @param[in] u16EndY is y end position
+  * @param[in] u8BGColorR is background R color
+  * @param[in] u8BGColorG is background G color
+  * @param[in] u8BGColorB is background B color
+  * @return none
+  */
+void vpostSetActiveWindow(uint16_t u16StartY, uint16_t u16EndY, uint8_t u8BGColorR, uint8_t u8BGColorG, uint8_t u8BGColorB)
+{
+    outpw(REG_LCM_VA_WIN, (u16StartY << 16) | u16EndY);
+    outpw(REG_LCM_VA_STUFF, (u8BGColorR << 16) | (u8BGColorG << 8) | u8BGColorB);
+}
+
+/**
+  * @brief Configure LCD display mode
+  * @param[in] u8DisplayMode is display mode, value could be
+  *                                         - \ref VPOST_DISPLAY_SINGLE
+  *                                         - \ref VPOST_DISPLAY_CONTINUOUS
+  * @return none
+  */
+void vpostSetDisplayMode(uint8_t u8DisplayMode)
+{
+    if (u8DisplayMode == 0)
+        outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(1 << 7)); //clear setting
+    else
+        outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | (u8DisplayMode) << 7);
+}
+
+/**
+  * @brief Configure display attributes of video interface,
+  * @param[in] u32VASrcType is display type, value could be
+  *                                         - \ref VA_SRC_YUV422
+  *                                         - \ref VA_SRC_YCBCR422
+  *                                         - \ref VA_SRC_RGB888
+  *                                         - \ref VA_SRC_RGB666
+  *                                         - \ref VA_SRC_RGB565
+  *                                         - \ref VA_SRC_RGB444_LOW
+  *                                         - \ref VA_SRC_RGB444_HIGH
+  * @return none
+  */
+void vpostSetVASrc(uint32_t u32VASrcType)
+{
+    uint32_t u32BytePerPixel, VA_FF, VA_Sride;
+
+    curVADev.ucVASrcFormat = u32VASrcType;
+
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(7 << 8));
+    if (u32VASrcType != 0)
+        outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | u32VASrcType);
+    else
+        outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(7 << 8));
+
+    if ((u32VASrcType == VA_SRC_RGB888) || (u32VASrcType == VA_SRC_RGB666))
+        outpw(REG_LCM_VA_FBCTRL, inpw(REG_LCM_VA_FBCTRL) & ~0x7ff07ff | (curDisplayDev.u32DevWidth << 16) | curDisplayDev.u32DevWidth);
+    else
+        outpw(REG_LCM_VA_FBCTRL, inpw(REG_LCM_VA_FBCTRL) & ~0x7ff07ff | ((curDisplayDev.u32DevWidth / 2) << 16) | (curDisplayDev.u32DevWidth / 2));
+
+    switch (u32VASrcType)
+    {
+    case VA_SRC_YUV422:
+    case VA_SRC_YCBCR422:
+    case VA_SRC_RGB565:
+        u32BytePerPixel = 2;
+        break;
+
+    case VA_SRC_RGB666:
+    case VA_SRC_RGB888:
+        u32BytePerPixel = 4;
+        break;
+
+    default:
+        u32BytePerPixel = 2;
+    }
+
+    /* set video stream frame buffer control */
+    VA_FF = curDisplayDev.u32DevWidth * u32BytePerPixel / 4;
+    VA_Sride = curDisplayDev.u32DevWidth * u32BytePerPixel / 4;
+    outpw(REG_LCM_VA_FBCTRL, inpw(REG_LCM_VA_FBCTRL) & ~0x7ff07ff | (VA_FF << 16) | VA_Sride);
+}
+
+/**
+  * @brief Start to display
+  * @param none
+  * @return none
+  */
+void vpostVAStartTrigger(void)
+{
+    if ((inpw(REG_LCM_DCCS) & VPOSTB_SINGLE) == VPOSTB_SINGLE)
+        while ((inpw(REG_LCM_DCCS) & VPOSTB_VA_EN) == VPOSTB_VA_EN); //wait VA_EN low
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | VPOSTB_DISP_OUT_EN); //display_out-enable
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | VPOSTB_VA_EN); //va-enable
+}
+
+/**
+  * @brief Stop to display
+  * @param none
+  * @return none
+  */
+void vpostVAStopTrigger(void)
+{
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(VPOSTB_DISP_OUT_EN | VPOSTB_VA_EN)); //OSD disable
+}
+
+/**
+  * @brief Configure LCD scaling attribute
+  * @param[in] u8HIntegral is horizontal integral
+  * @param[in] u16HDecimal is horizontal decimal
+  * @param[in] u8VIntegral is vertical integral
+  * @param[in] u16VDecimal is vertical decimal
+  * @param[in] u32Mode is scale mode, value could be
+  *                                      - \ref VA_SCALE_INTERPOLATION
+  *                                      - \ref VA_SCALE_DUPLICATION
+  * @return none
+  */
+void vpostVAScalingCtrl(uint8_t u8HIntegral, uint16_t u16HDecimal, uint8_t u8VIntegral, uint16_t u16VDecimal, uint32_t u32Mode)
+{
+    outpw(REG_LCM_VA_SCALE, ((((uint32_t)u8VIntegral << 10) + ((uint32_t)ceil((double)1024 / 10)*u16VDecimal)) << 16)
+          | (((uint32_t)u8HIntegral << 10) + ((uint32_t)ceil((double)1024 / 10)*u16HDecimal)) | u32Mode);
+}
+
+/**
+  * @brief Set OSD color key
+  * @param[in] u8CKeyColorR is color key R color
+  * @param[in] u8CKeyColorG is color key G color
+  * @param[in] u8CKeyColorB is color key B color
+  * @return none
+  */
+void vpostOSDSetColKey(uint8_t u8CKeyColorR, uint8_t u8CKeyColorG, uint8_t u8CKeyColorB)
+{
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) & ~(VPOSTB_BLI_ON | VPOSTB_CKEY_ON)); //blinking disable, color-key disable
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | VPOSTB_CKEY_ON);//color-key enable
+    outpw(REG_LCM_OSD_CKEY, ((uint32_t)(u8CKeyColorR << 16) | (uint32_t)(u8CKeyColorG << 8) | u8CKeyColorB));
+}
+
+/**
+  * @brief Set OSD color mask, OSD data only will be displayed if the mask bit is set as 1.
+  * @param[in] u8MaskColorR is color key R color
+  * @param[in] u8MaskColorG is color key G color
+  * @param[in] u8MaskColorB is color key B color
+  * @return none
+  */
+void vpostOSDSetColMask(uint8_t u8MaskColorR, uint8_t u8MaskColorG, uint8_t u8MaskColorB)
+{
+    outpw(REG_LCM_OSD_CMASK, ((u8MaskColorR << 16) | (u8MaskColorG << 8) | u8MaskColorB));
+}
+
+/**
+  * @brief Set OSD blinking function
+  * @param[in] u8OSDBlinkVcnt is blinking cycle time, unit is VSync
+  * @return none
+  */
+void vpostOSDSetBlinking(uint8_t u8OSDBlinkVcnt)
+{
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) & ~(VPOSTB_BLI_ON | VPOSTB_CKEY_ON));  //blinking disable, color-key disable
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | VPOSTB_BLI_ON);
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | ((uint32_t)(u8OSDBlinkVcnt) << 16));
+}
+
+/**
+  * @brief Disable OSD blinking function
+  * @param none
+  * @return none
+  */
+void vpostOSDDisableBlinking(void)
+{
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) & ~ VPOSTB_BLI_ON);
+}
+
+/**
+  * @brief Configure display attributes of OSD
+  * @param[in] u32OSDSrcType is display type, value could be
+  *                                         - \ref OSD_SRC_YUV422
+  *                                         - \ref OSD_SRC_YCBCR422
+  *                                         - \ref OSD_SRC_RGB888
+  *                                         - \ref OSD_SRC_RGB666
+  *                                         - \ref OSD_SRC_RGB565
+  *                                         - \ref OSD_SRC_RGB444_LOW
+  *                                         - \ref OSD_SRC_RGB444_HIGH
+  *                                         - \ref OSD_SRC_RGB332
+  * @return none
+  */
+void vpostSetOSDSrc(uint32_t u32OSDSrcType)
+{
+    uint32_t u32BytePerPixel, VA_FF, VA_Sride;
+
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(7 << 12) | u32OSDSrcType);
+    curOSDDev.ucOSDSrcFormat = u32OSDSrcType;
+
+    switch (u32OSDSrcType)
+    {
+    case OSD_SRC_YUV422:
+    case OSD_SRC_YCBCR422:
+    case OSD_SRC_RGB565:
+        u32BytePerPixel = 2;
+        break;
+
+    case OSD_SRC_RGB666:
+    case OSD_SRC_RGB888:
+        u32BytePerPixel = 4;
+        break;
+
+    default:
+        u32BytePerPixel = 2;
+    }
+
+    /* set video stream frame buffer control */
+    VA_FF = curOSDDev.nOSDWidth * u32BytePerPixel / 4;
+    VA_Sride = curOSDDev.nOSDWidth * u32BytePerPixel / 4;
+    outpw(REG_LCM_OSD_FBCTRL, inpw(REG_LCM_OSD_FBCTRL) & ~0x7ff07ff | (VA_FF << 16) | VA_Sride);
+}
+
+/**
+  * @brief Get the pointer of OSD frame buffer
+  * @param none
+  * @return pointer of OSD frame buffer
+  * @retval NULL fail.
+  * @note Must call \ref vpostOSDSetWindow and \ref vpostSetOSDSrc before calling this function
+  */
+uint8_t *vpostGetOSDBuffer(void)
+{
+    uint32_t u32BytePerPixel;
+    uint8_t *u8BufPtr;
+
+    if ((curOSDDev.nOSDWidth == 0) || (curOSDDev.nOSDHeight == 0))
+    {
+        return NULL;
+    }
+
+    switch (curOSDDev.ucOSDSrcFormat)
+    {
+    case OSD_SRC_YUV422:
+    case OSD_SRC_YCBCR422:
+    case OSD_SRC_RGB565:
+        u32BytePerPixel = 2;
+        break;
+
+    case OSD_SRC_RGB666:
+    case OSD_SRC_RGB888:
+        u32BytePerPixel = 4;
+        break;
+
+    default:
+        u32BytePerPixel = 2;
+    }
+
+    u8BufPtr = (uint8_t *)malloc((curOSDDev.nOSDWidth * curOSDDev.nOSDHeight * u32BytePerPixel) + 32);
+    if (u8BufPtr == NULL)
+        return NULL;
+    u8BufPtr = (uint8_t *)shift_pointer((uint32_t)u8BufPtr, 32);
+
+    outpw(REG_LCM_OSD_BADDR, (uint32_t)((uint32_t)u8BufPtr | 0x80000000));
+
+    return (uint8_t *)((uint32_t)u8BufPtr | 0x80000000);
+}
+
+/**
+  * @brief Enable OSD function
+  * @param none
+  * @return none
+  */
+void vpostOSDEnable(void)
+{
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | VPOSTB_OSD_EN); //OSD enable
+}
+
+/**
+  * @brief Disable OSD function
+  * @param none
+  * @return none
+  */
+void vpostOSDDisable(void)
+{
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~VPOSTB_OSD_EN); //OSD disable
+}
+
+/**
+  * @brief Configure OSD scaling attribute
+  * @param[in] u8HIntegral is horizontal integral
+  * @param[in] u16HDecimal is horizontal decimal
+  * @param[in] u8VScall is scale mode, value could be
+  *                                      - \ref VPOSTB_OSD_VUP_1X
+  *                                      - \ref VPOSTB_OSD_VUP_2X
+  *                                      - \ref VPOSTB_OSD_VUP_4X
+  * @return none
+  */
+void vpostOSDScalingCtrl(uint8_t u8HIntegral, uint16_t u16HDecimal, uint8_t u8VScall)
+{
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & 0xfff0ffff); //clear OSD scaling setting
+    if (u8VScall != 0)
+        outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | (u8VScall << 16));
+    outpw(REG_LCM_OSD_SCALE, ((uint32_t)u8HIntegral << 10) | ((uint32_t)ceil((double)1024 / 10 * u16HDecimal)) << 6);
+}
+
+/**
+  * @brief Set OSD display window, including start position, width and height.
+  * @param[in] u32XStart is X start position
+  * @param[in] u32YStart is Y start position
+  * @param[in] u32Width is OSD display width
+  * @param[in] u32Height is OSD display height
+  * @return none
+  */
+void vpostOSDSetWindow(uint32_t u32XStart, uint32_t u32YStart, uint32_t u32Width, uint32_t u32Height)
+{
+    outpw(REG_LCM_OSD_WINS, ((u32YStart + 1) << 16) | (u32XStart + 1));
+    outpw(REG_LCM_OSD_WINE, ((u32YStart + u32Height) << 16) | (u32XStart + u32Width));
+
+    curOSDDev.nOSDWidth = u32Width;
+    curOSDDev.nOSDHeight = u32Height;
+}
+
+/**
+  * @brief Initialize hardware cursor function
+  * @param[in] u32CursorBMPBuff is pointer of hardware cursor image
+  * @param[in] ucMode is hardware cursor mode, value could be
+  *                                              - \ref HC_MODE0
+  *                                              - \ref HC_MODE1
+  *                                              - \ref HC_MODE2
+  *                                              - \ref HC_MODE3
+  *                                              - \ref HC_MODE4
+  *                                              - \ref HC_MODE5
+  * @return none
+  */
+void vpostHCInit(uint32_t *u32CursorBMPBuff, VA_HCMODE_E ucMode)
+{
+    int bpp = 2;
+    int BlockWidth = 32;
+    int bpw = 32;
+
+    outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x003f3f00 | (0x00 << 8) | (0x00 << 16)); //set TIP
+    if (ucMode == HC_MODE0)
+    {
+        bpp = 2;
+        BlockWidth = 32;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7); //set mode 0 32X32X2bpp 4 color
+
+    }
+    else if (ucMode == HC_MODE1)
+    {
+        bpp = 2;
+        BlockWidth = 32;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7 | 0x1); //set mode 1 32X32X2bpp 3 color and 1 transparent
+    }
+    else if (ucMode == HC_MODE2)
+    {
+        bpp = 2;
+        BlockWidth = 64;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7 | 0x2); //set mode 2 64X64X2bpp 4 color
+    }
+    else if (ucMode == HC_MODE3)
+    {
+        bpp = 2;
+        BlockWidth = 64;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7 | 0x3); //set mode 3 64X64X2bpp 3 color and 1 transparent
+    }
+    else if (ucMode == HC_MODE4)
+    {
+        bpp = 1;
+        BlockWidth = 128;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7 | 0x4); //set mode 4 128X128X1bpp 2 color
+    }
+    else if (ucMode == HC_MODE5)
+    {
+        bpp = 1;
+        BlockWidth = 128;
+        outpw(REG_LCM_HC_CTRL, inpw(REG_LCM_HC_CTRL) & ~0x7 | 0x5); //set mode 5 128X128X1bpp 1 color and 1 transparent
+    }
+
+    outpw(REG_LCM_HC_WBCTRL, ((bpp * BlockWidth / bpw) << 16) | (bpp * BlockWidth / bpw));
+    outpw(REG_LCM_HC_BADDR, (uint32_t)u32CursorBMPBuff);
+    outpw(REG_LCM_HC_COLOR0, 0x00ff0000);       // RED color
+    outpw(REG_LCM_HC_COLOR1, 0x0000ff00);       // GREEN color
+    outpw(REG_LCM_HC_COLOR2, 0x000000ff);       // BLUE color
+    outpw(REG_LCM_HC_COLOR3, 0x00ffff00);       // YELLOW color
+    outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) | VPOSTB_HC_EN);
+}
+
+/**
+  * @brief Set the position of hardware cursor
+  * @param[in] u32CursorX is X position
+  * @param[in] u32CursorY is Y position
+  * @return none
+  */
+void vpostHCPosCtrl(uint32_t u32CursorX, uint32_t u32CursorY)
+{
+    outpw(REG_LCM_HC_POS, (u32CursorY << 16) | u32CursorX); //set Cursor position
+}
+
+/**
+  * @brief Set OSD overlay condition
+  * @param[in] u8OSDDisplayMatch is display method when mask bit is matched, value could be
+  *                                                         - \ref DISPLAY_VIDEO
+  *                                                         - \ref DISPLAY_OSD
+  *                                                         - \ref DISPLAY_SYNTHESIZED
+  * @param[in] u8OSDDisplayUnMatch is display method when mask bit is unmatched
+  *                                                         - \ref DISPLAY_VIDEO
+  *                                                         - \ref DISPLAY_OSD
+  *                                                         - \ref DISPLAY_SYNTHESIZED
+  * @param[in] u8OSDSynW is synthesis video weighting, based on match condition
+  * @return none
+  */
+void vpostOSDSetOverlay(uint8_t u8OSDDisplayMatch, uint8_t u8OSDDisplayUnMatch, uint8_t u8OSDSynW)
+{
+    /* clear OCR0 and OCR1 */
+    outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) & 0xfffffff0);
+
+    /* match condition */
+    if (u8OSDDisplayMatch != 0)
+    {
+        outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | (u8OSDDisplayMatch << 2));
+    }
+
+    /* unmatch condition */
+    if (u8OSDDisplayUnMatch != 0)
+    {
+        outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | (u8OSDDisplayUnMatch));
+    }
+
+    /* synthesized weight */
+    if (u8OSDDisplayMatch == DISPLAY_SYNTHESIZED || u8OSDDisplayUnMatch == DISPLAY_SYNTHESIZED)
+    {
+        outpw(REG_LCM_OSD_OVERLAY, inpw(REG_LCM_OSD_OVERLAY) | (u8OSDSynW << 4));
+    }
+}
+
+/**
+  * @brief Write MPU command
+  * @param[in] uscmd MPU command code
+  * @return none
+  */
+void vpostMPUWriteAddr(uint16_t uscmd)
+{
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) & ~(1 << 30));     //RS=0
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) & ~(1 << 29));     //w
+
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) | (1 << 5)));           //CMD ON
+    outpw(REG_LCM_MPU_CMD, (inpw(REG_LCM_MPU_CMD) & 0xffff0000 | uscmd));
+    while (inpw(REG_LCM_MPU_CMD) & (1UL << 31));
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) & ~(1 << 5)));          //CMD OFF
+}
+
+/**
+  * @brief Write MPU data
+  * @param[in] usdata MPU data
+  * @return none
+  */
+void vpostMPUWriteData(uint16_t usdata)
+{
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) | (1 << 30));      //RS=1
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) & ~(1 << 29));     //w
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) | (1 << 5)));           //CMD ON
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) & 0xffff0000 | usdata);
+    while (inpw(REG_LCM_MPU_CMD) & (1UL << 31));
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) & ~(1 << 5)));          //CMD OFF
+}
+
+/**
+  * @brief Read MPU data
+  * @param none
+  * @return MPU data
+  */
+uint32_t vpostMPUReadData(void)
+{
+    uint32_t udata;
+
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) | (1 << 30));      //RS=1
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) | (1 << 5)));           //CMD ON
+    outpw(REG_LCM_MPU_CMD, inpw(REG_LCM_MPU_CMD) | (1 << 29));      //r
+    while (inpw(REG_LCM_MPU_CMD) & (1UL << 31));
+    udata = inpw(REG_LCM_MPU_CMD) & 0xffff;
+    outpw(REG_LCM_DCCS, (inpw(REG_LCM_DCCS) & ~(1 << 5)));          //CMD OFF
+
+    return udata;
+}
+
+/*@}*/ /* end of group N9H30_LCD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_LCD_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_pwm.c

@@ -0,0 +1,1117 @@
+/**************************************************************************//**
+ * @file     pwm.c
+ * @brief    N9H30 series PWM driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_pwm.h"
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_PWM_Driver PWM Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+  @{
+*/
+
+//Internal function definition
+/// @cond HIDDEN_SYMBOLS
+
+void pwmISR(PVOID pvParam);
+
+
+static INT pwmInitGPIO(const INT nTimerIdentity, const INT nValue);
+static INT pwmInitTimer(const INT nTimerIdentity);
+static INT pwmStartTimer(const INT nTimerIdentity);
+static INT pwmStopTimer(const INT nTimerIdentity, const INT nMethod);
+// Register operation
+static INT pwmSetCP(const INT nTimerIdentity, const INT nValue);
+static INT pwmSetDZI(const INT nTimerIdentity, const INT nValue);
+static INT pwmSetCSR(const INT nTimerIdentity, const INT nValue);
+static INT pwmSetDZGenerator(const INT nTimerIdentity, const INT nStatus);
+static INT pwmSetTimerState(const INT nTimerIdentity, const INT nStatus);
+static INT pwmSetInverter(const INT nTimerIdentity, const INT nStatus);
+static INT pwmSetMode(const INT nTimerIdentity, const INT nStatus);
+static INT pwmSetCNR(const INT nTimerIdentity, const INT nValue);
+static INT pwmSetCMR(const INT nTimerIdentity, const INT nValue);
+static UINT pwmGetPDR(const INT nTimerIdentity);
+static INT pwmSetPIER(const INT nTimerIdentity, const INT value);
+static INT pwmCleanPIIR(const INT nTimerIdentity);
+
+//Global variable
+static BOOL bPWMIRQFlag = FALSE; //IRQ enable flag, set after PWM IRQ enable
+static BOOL bPWMTimerOpenStatus[PWM_TIMER_NUM]; //timer flag which set after open(for disable IRQ decision)
+static BOOL bPWMTimerStartStatus[PWM_TIMER_NUM]; //timer flag which set after Start count(to avoid incorrectly stop procedure)
+static BOOL bPWMTimerMode[PWM_TIMER_NUM]; //PWM timer toggle/one shot mode
+static BOOL volatile bPWMIntFlag[PWM_TIMER_NUM]; //interrupt flag which set by ISR
+/// @endcond /* HIDDEN_SYMBOLS */
+
+
+/**
+  * @brief The init function of PWM device driver
+  */
+INT pwmInit(void)
+{
+    UINT temp;
+    // Enable PWM clock
+    temp = inpw(REG_CLK_PCLKEN1);
+    temp = temp | 0x8000000;
+    outpw(REG_CLK_PCLKEN1, temp);
+
+    sysInstallISR(IRQ_LEVEL_1, PWM_IRQn, (PVOID)pwmISR);
+    sysSetLocalInterrupt(ENABLE_IRQ);  // Enable CPSR I bit
+
+    return 0;
+}
+
+/**
+  * @brief The exit function of PWM device driver
+  */
+INT pwmExit(void)
+{
+    return 0;
+}
+
+/**
+  * @brief The open function of PWM device driver
+  * @param[in] nTimerIdentity PWM Timer channel identity
+  * @retval Successful PWM successfully opened
+  * @retval pwmTimerBusy PWM timer already open
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+INT pwmOpen(const INT nTimerIdentity)
+{
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    if (bPWMTimerOpenStatus[nTimerIdentity] == TRUE)
+    {
+        return pwmTimerBusy;
+    }
+    if (bPWMIRQFlag == FALSE)
+    {
+
+        sysEnableInterrupt(PWM_IRQn);
+
+        bPWMIRQFlag = TRUE;
+    }
+    bPWMTimerOpenStatus[nTimerIdentity] = TRUE;
+
+    // Set PWM timer default value(CSR->PPR->PCR->CMR->CNR)
+    pwmInitTimer(nTimerIdentity);
+
+    //Enable PIER
+    pwmSetPIER(nTimerIdentity, PWM_ENABLE);
+
+    //Reset PIIR
+    pwmCleanPIIR(nTimerIdentity);
+
+    //Reset PWM timer start count flag
+    bPWMTimerStartStatus[nTimerIdentity] = FALSE;
+
+    return Successful;
+
+}
+
+/**
+  * @brief The close function of PWM device driver
+  * @param[in] nTimerIdentity PWM Timer channel identity
+  * @retval Successful PWM successfully closed
+  * @retval pwmTimerNotOpen PWM timer not open
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+INT pwmClose(const INT nTimerIdentity)
+{
+    INT nLoop;
+    BOOL uAllTimerClose = TRUE;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    if (bPWMTimerOpenStatus[nTimerIdentity] == FALSE)
+    {
+        return pwmTimerNotOpen;
+    }
+    bPWMTimerOpenStatus[nTimerIdentity] = FALSE;
+    //Check if all timer stop, IRQ can be disable
+    for (nLoop = PWM_TIMER_MIN; nLoop < PWM_TIMER_NUM; nLoop++)
+    {
+        if (bPWMTimerOpenStatus[nLoop] == TRUE)
+        {
+            uAllTimerClose = FALSE;
+        }
+    }
+    //All timer stop, disable IRQs
+    if (uAllTimerClose == TRUE)
+    {
+
+        sysDisableInterrupt(PWM_IRQn);
+        bPWMIRQFlag = FALSE;
+    }
+
+    pwmSetPIER(nTimerIdentity, PWM_DISABLE);
+    pwmCleanPIIR(nTimerIdentity);
+
+
+    return Successful;
+
+}
+
+/**
+  * @brief The read function of PWM device driver
+  * @param[in] nTimerIdentity PWM Timer channel identity
+  * @param[out] pucStatusValue The point of typePWMSTATUS
+  * @param[in] uLength The length of typePWMSTATUS
+  * @retval Successful Read PWM value successfully
+  * @retval pwmTimerNotOpen PWM timer not open
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidStructLength Struct length error(struct type error)
+  */
+INT pwmRead(const INT nTimerIdentity, PUCHAR pucStatusValue, const UINT uLength)
+{
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    if (bPWMTimerOpenStatus[nTimerIdentity] == FALSE)
+    {
+        return pwmTimerNotOpen;
+    }
+    if (uLength != sizeof(typePWMSTATUS))
+    {
+        return pwmInvalidStructLength;// Struct length error(struct type error)
+    }
+    if (sizeof(*((typePWMSTATUS *)pucStatusValue)) != sizeof(typePWMSTATUS))
+    {
+        return pwmInvalidStructLength;// Struct length error(struct type error)
+    }
+    ((typePWMSTATUS *)pucStatusValue)->PDR = pwmGetPDR(nTimerIdentity);
+    if (bPWMIntFlag[nTimerIdentity] == TRUE)
+    {
+        bPWMIntFlag[nTimerIdentity] = FALSE;
+        ((typePWMSTATUS *)pucStatusValue)->InterruptFlag = TRUE;
+    }
+    else
+    {
+        ((typePWMSTATUS *)pucStatusValue)->InterruptFlag = FALSE;
+    }
+
+    return Successful;
+
+}
+
+/**
+  * @brief The write function of PWM device driver
+  * @param[in] nTimerIdentity PWM Timer channel identity
+  * @param[in] pucCNRCMRValue The value of CNR and CMR
+  * @param[in] uLength For future usage
+  * @retval Successful Write PWM setting successfully
+  * @retval pwmTimerNotOpen PWM timer not open
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+INT pwmWrite(const INT nTimerIdentity, PUCHAR pucCNRCMRValue, const UINT uLength)
+{
+    typePWMVALUE pwmvalue;
+    INT nStatus;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    if (bPWMTimerOpenStatus[nTimerIdentity] == FALSE)
+    {
+        return pwmTimerNotOpen;
+    }
+    if (uLength != sizeof(typePWMVALUE))
+    {
+        return pwmInvalidStructLength;// Struct length error(struct type error)
+    }
+    pwmvalue.value = ((typePWMVALUE *)pucCNRCMRValue)->value;
+    nStatus = pwmSetCNR(nTimerIdentity, pwmvalue.field.cnr);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+    nStatus = pwmSetCMR(nTimerIdentity, pwmvalue.field.cmr);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+    return Successful;
+
+}
+
+/**
+  * @brief The ioctl function of PWM device driver
+  * @param[in] nTimerIdentity PWM Timer channel identity
+  * @param[in] uCommand Ioctl command which indicates different operation
+  * @param[in] uIndication Not use in PWM
+  * @param[in] uValue The value which use with uCommand
+  * @retval Successful PWM ioctl execute successfully
+  * @retval pwmTimerNotOpen PWM timer not open
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidIoctlCommand Ioctl command error
+  * @retval Others Error according to different uCommand
+  */
+INT pwmIoctl(const INT nTimerIdentity, const UINT uCommand, const UINT uIndication, UINT uValue)
+{
+    INT nStatus;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    if (bPWMTimerOpenStatus[nTimerIdentity] == FALSE)
+    {
+        return pwmTimerNotOpen;
+    }
+    switch (uCommand)
+    {
+    case START_PWMTIMER:
+    {
+        nStatus = pwmStartTimer(nTimerIdentity);
+        break;
+    }
+    case STOP_PWMTIMER:
+    {
+        // default stop method is 2
+        nStatus = pwmStopTimer(nTimerIdentity, PWM_STOP_METHOD2);
+        break;
+    }
+    case SET_CSR:
+    {
+        nStatus = pwmSetCSR(nTimerIdentity, uValue);
+        break;
+    }
+    case SET_CP:
+    {
+        nStatus = pwmSetCP(nTimerIdentity, uValue);
+        break;
+    }
+    case SET_DZI:
+    {
+        nStatus = pwmSetDZI(nTimerIdentity, uValue);
+        break;
+    }
+    case SET_INVERTER:
+    {
+        nStatus = pwmSetInverter(nTimerIdentity, uValue);
+        break;
+    }
+    case SET_MODE:
+    {
+        nStatus = pwmSetMode(nTimerIdentity, uValue);
+        break;
+    }
+    case ENABLE_DZ_GENERATOR:
+    {
+        nStatus = pwmSetDZGenerator(nTimerIdentity, PWM_ENABLE);
+        break;
+    }
+    case DISABLE_DZ_GENERATOR:
+    {
+        nStatus = pwmSetDZGenerator(nTimerIdentity, PWM_DISABLE);
+        break;
+    }
+    case ENABLE_PWMGPIOOUTPUT:
+    {
+        nStatus = pwmInitGPIO(nTimerIdentity, uValue);
+        break;
+    }
+    default:
+    {
+        return pwmInvalidIoctlCommand;
+    }
+    }
+    return nStatus;
+}
+
+
+/// @cond HIDDEN_SYMBOLS
+
+/**
+  * @brief The interrupt service routines of PWM
+  * @param[in] pvParam IRQ Parameter(not use in PWM)
+  */
+VOID pwmISR(PVOID pvParam)
+{
+    INT i;
+
+    UINT32 uRegisterValue = 0;
+    uRegisterValue = inpw(REG_PWM_PIIR);// Get PIIR value
+    for (i = 0; i < PWM_TIMER_NUM ; i++)
+    {
+        if (uRegisterValue & (1 << i))
+        {
+            bPWMIntFlag[i] = 1;
+            outpw(REG_PWM_PIIR, (1 << i));
+        }
+    }
+}
+
+/**
+  * @brief This function set corresponding GPIO as PWM function according to the
+  *        parameter nTimerIdentity
+  * @param[in] nTimerIdentity Timer channel number
+  * @retval Successful PWM init GPIO successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidPin PWM output pin setting error
+  */
+static INT pwmInitGPIO(const INT nTimerIdentity, const INT nValue)
+{
+    UINT temp = 0;
+
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+
+    if (nTimerIdentity == PWM_TIMER0)
+    {
+        if (nValue == PWM0_GPA12)
+        {
+            temp = inpw(REG_SYS_GPA_MFPH);
+            temp = (temp & ~0x000F0000) | 0xD0000;
+            outpw(REG_SYS_GPA_MFPH, temp);
+        }
+        else if (nValue == PWM0_GPB2)
+        {
+            temp = inpw(REG_SYS_GPB_MFPL);
+            temp = (temp & ~0xF00) | 0xD00;
+            outpw(REG_SYS_GPB_MFPL, temp);
+        }
+        else
+            return pwmInvalidPin;
+    }
+    else if (nTimerIdentity == PWM_TIMER1)
+    {
+        if (nValue == PWM1_GPA13)
+        {
+            temp = inpw(REG_SYS_GPA_MFPH);
+            temp = (temp & ~0x00F00000) | 0xD00000;
+            outpw(REG_SYS_GPA_MFPH, temp);
+        }
+        else if (nValue == PWM1_GPB3)
+        {
+            temp = inpw(REG_SYS_GPB_MFPL);
+            temp = (temp & ~0xF000) | 0xD000;
+            outpw(REG_SYS_GPB_MFPL, temp);
+        }
+        else
+            return pwmInvalidPin;
+    }
+    else if (nTimerIdentity == PWM_TIMER2)
+    {
+        if (nValue == PWM2_GPA14)
+        {
+            temp = inpw(REG_SYS_GPA_MFPH);
+            temp = (temp & ~0x0F000000) | 0xD000000;
+            outpw(REG_SYS_GPA_MFPH, temp);
+        }
+        else if (nValue == PWM2_GPH2)
+        {
+            temp = inpw(REG_SYS_GPH_MFPL);
+            temp = (temp & ~0xF00) | 0xD00;
+            outpw(REG_SYS_GPH_MFPL, temp);
+        }
+        else
+            return pwmInvalidPin;
+    }
+    else
+    {
+        if (nValue == PWM3_GPA15)
+        {
+            temp = inpw(REG_SYS_GPA_MFPH);
+            temp = (temp & ~0xF0000000) | 0xD0000000;
+            outpw(REG_SYS_GPA_MFPH, temp);
+        }
+        else if (nValue == PWM3_GPH3)
+        {
+            temp = inpw(REG_SYS_GPH_MFPL);
+            temp = (temp & ~0xF000) | 0xD000;
+            outpw(REG_SYS_GPH_MFPL, temp);
+        }
+        else
+            return pwmInvalidPin;
+    }
+
+    return Successful;
+}
+
+
+/**
+  * @brief This function initiates PWM timer n and set the default setting to CSR,
+  *        PPR, PCR, CNR, CMR
+  * @param[in] nTimerIdentity Timer channel number
+  * @retval Successful PWM init timer successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmInitTimer(const INT nTimerIdentity)
+{
+    typePPR PWMPPR;
+    INT nStatus;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+
+    //Set CSR
+    nStatus = pwmSetCSR(nTimerIdentity, DEFAULT_CSR);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+
+    //Set PPR
+    PWMPPR.value = (UINT)inpw(REG_PWM_PPR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        if (PWMPPR.field.cp0 == 0)
+        {
+            pwmSetCP(nTimerIdentity, DEFAULT_CP);
+        }
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        if (PWMPPR.field.cp0 == 0)
+        {
+            pwmSetCP(nTimerIdentity, DEFAULT_CP);
+        }
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        if (PWMPPR.field.cp1 == 0)
+        {
+            pwmSetCP(nTimerIdentity, DEFAULT_CP);
+        }
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        if (PWMPPR.field.cp1 == 0)
+        {
+            pwmSetCP(nTimerIdentity, DEFAULT_CP);
+        }
+        break;
+    }
+    }
+
+    //Set PCR
+    nStatus = pwmSetMode(nTimerIdentity, DEFAULT_MODE);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+    bPWMTimerMode[nTimerIdentity] = DEFAULT_MODE;
+
+    //Set CMR
+    nStatus = pwmSetCMR(nTimerIdentity, DEFAULT_CMR);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+
+    //Set CNR
+    nStatus = pwmSetCNR(nTimerIdentity, DEFAULT_CNR);
+
+    if (nStatus != Successful)
+    {
+        return nStatus;
+    }
+
+    return Successful;
+
+}
+
+
+/**
+  * @brief This function starts PWM timer according to the parameter
+  * @param[in] nTimerIdentity Timer channel number
+  * @retval Successful PWM start timer successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmStartTimer(const INT nTimerIdentity)
+{
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    pwmSetTimerState(nTimerIdentity, PWM_ENABLE);
+    if (bPWMTimerMode[nTimerIdentity] == PWM_TOGGLE)
+    {
+        bPWMTimerStartStatus[nTimerIdentity] = TRUE;
+    }
+
+    return Successful;
+}
+
+/**
+  * @brief This function stops PWM timer n using method 1, 2, or 3 according to the
+  *        parameter nTimerIdentity and nStatus
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nMethod Stop PWM timer method
+  * @retval Successful PWM stop timer successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidStopMethod Stop method error
+  */
+static INT pwmStopTimer(const INT nTimerIdentity, INT nMethod)
+{
+    typeCNR PWMCNR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        // Timer_num value error
+        return pwmInvalidTimerChannel;
+    }
+    //Can't stop before open PWM timer
+    if (bPWMTimerOpenStatus[nTimerIdentity] == FALSE)
+    {
+        return Successful;
+    }
+    // one shot mode didn't need stop procedure
+    if (bPWMTimerMode[nTimerIdentity] == PWM_ONESHOT)
+    {
+        return Successful;
+    }
+    // Timer stop already, no need to stop again
+    if (bPWMTimerStartStatus[nTimerIdentity] == FALSE)
+    {
+        return Successful;
+    }
+
+    // Set CNR as 0
+    PWMCNR.field.cnr = 0;
+    outpw(REG_PWM_CNR0 + (PWM_OFFSET * nTimerIdentity), PWMCNR.value);
+
+    switch (nMethod)
+    {
+    case PWM_STOP_METHOD1:
+    {
+        while (1)
+        {
+            if (pwmGetPDR(nTimerIdentity) == 0)  // Wait PDR reach to 0
+            {
+                pwmSetTimerState(nTimerIdentity, PWM_DISABLE);// Disable pwm timer
+                bPWMIntFlag[nTimerIdentity] = FALSE;
+                bPWMTimerStartStatus[nTimerIdentity] = FALSE;
+                break;
+            }
+        }
+        break;
+    }
+    case PWM_STOP_METHOD2:
+    {
+        while (1)
+        {
+            if (bPWMIntFlag[nTimerIdentity] == TRUE)  // Wait interrupt happen
+            {
+                pwmSetTimerState(nTimerIdentity, PWM_DISABLE);// Disable pwm timer
+                bPWMIntFlag[nTimerIdentity] = FALSE;
+                bPWMTimerStartStatus[nTimerIdentity] = FALSE;
+                break;
+            }
+        }
+        break;
+    }
+    /*case PWM_STOP_METHOD3:
+    {
+        pwmSetPCRState(nTimerIdentity, PWM_DISABLE);// Disable pwm timer
+        bPWMIntFlag[nTimerIdentity] = FALSE;
+        bPWMTimerStartStatus[nTimerIdentity] = FALSE;
+        break;
+    }*/
+    default:
+    {
+        return pwmInvalidStopMethod;// Stop method value error
+    }
+    }
+
+    return Successful;
+}
+
+/**
+  * @brief This function set CPn value according to the parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue The value which want to set in CSRn
+  * @retval Successful Set CPn successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidCPValue PWM_PPR CPn value out of range
+  */
+static INT pwmSetCP(const INT nTimerIdentity, const INT nValue)
+{
+    typePPR PWMPPR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nValue < CP_MIN || nValue > CP_MAX)
+    {
+        return pwmInvalidCPValue;// CP value error
+    }
+    PWMPPR.value = (UINT)inpw(REG_PWM_PPR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPPR.field.cp0 = nValue;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPPR.field.cp0 = nValue;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPPR.field.cp1 = nValue;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPPR.field.cp1 = nValue;
+        break;
+    }
+    }
+    outpw(REG_PWM_PPR, PWMPPR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function set DZIn value according to the parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue The value which want to set in DZIn
+  * @retval Successful Set DZIn successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidDZIValue PWM_PPR DZIn value out of range
+  */
+static INT pwmSetDZI(const INT nTimerIdentity, const INT nValue)
+{
+    typePPR PWMPPR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nValue < DZI_MIN || nValue > DZI_MAX)
+    {
+        return pwmInvalidDZIValue;// CSR value error
+    }
+    PWMPPR.value = (UINT)inpw(REG_PWM_PPR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPPR.field.dzi0 = nValue;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPPR.field.dzi0 = nValue;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPPR.field.dzi1 = nValue;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPPR.field.dzi1 = nValue;
+        break;
+    }
+    }
+    outpw(REG_PWM_PPR, PWMPPR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function set CSRn value according to the parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue The value which want to set in CSRn
+  * @retval Successful Set CSRn successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmSetCSR(const INT nTimerIdentity, const INT nValue)
+{
+    typeCSR PWMCSR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nValue < CSR_MIN || nValue > CSR_MAX)
+    {
+        return pwmInvalidCSRValue;// CSR value error
+    }
+    PWMCSR.value = (UINT)inpw(REG_PWM_CSR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMCSR.field.csr0 = nValue;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMCSR.field.csr1 = nValue;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMCSR.field.csr2 = nValue;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMCSR.field.csr3 = nValue;
+        break;
+    }
+    }
+    outpw(REG_PWM_CSR, PWMCSR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function enable/disable PWM channel n dead zone function according to the
+  *        parameter nTimerIdentity and nStatus
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nStatus PWMDZG_ENABLE/PWMDZG_DISABLE
+  * @retval Successful Set dead zone successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidDZGStatus PWM Dead-Zone Generator enable/disable status error
+  */
+static INT pwmSetDZGenerator(const INT nTimerIdentity, INT nStatus)
+{
+    typePCR PWMPCR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nStatus != PWMDZG_ENABLE && nStatus != PWMDZG_DISABLE)
+    {
+        return pwmInvalidDZGStatus;// PCR inverter value error
+    }
+    PWMPCR.value = (UINT)inpw(REG_PWM_PCR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPCR.field.grpup0_dzen = nStatus;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPCR.field.grpup0_dzen = nStatus;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPCR.field.grpup1_dzen = nStatus;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPCR.field.grpup1_dzen = nStatus;
+        break;
+    }
+    }
+    outpw(REG_PWM_PCR, PWMPCR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function set PWM channel n enable/disable according to the
+  *        parameter nTimerIdentity and nStatus
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nStatus PWM_ENABLE/PWMDISABLE
+  * @retval Successful Set channel enable/disable successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmSetTimerState(const INT nTimerIdentity, INT nStatus)
+{
+    typePCR PWMPCR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nStatus != PWM_ENABLE && nStatus != PWM_DISABLE)
+    {
+        return pwmInvalidTimerStatus;
+    }
+    PWMPCR.value = (UINT)inpw(REG_PWM_PCR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPCR.field.ch0_en = nStatus;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPCR.field.ch1_en = nStatus;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPCR.field.ch2_en = nStatus;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPCR.field.ch3_en = nStatus;
+        break;
+    }
+    }
+    outpw(REG_PWM_PCR, PWMPCR.value);
+
+    return Successful;
+}
+
+
+/**
+  * @brief This function set PWM channel n inverter on/off according to the
+  *        parameter nTimerIdentity and nStatus
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nStatus PWM_ENABLE/PWM_DISABLE
+  * @retval Successful Set inverter successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidInverterValue Inverter value error
+  */
+static INT pwmSetInverter(const INT nTimerIdentity, INT nStatus)
+{
+    typePCR PWMPCR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nStatus != PWM_INVON && nStatus != PWM_INVOFF)
+    {
+        return pwmInvalidInverterValue;// PCR inverter value error
+    }
+    PWMPCR.value = (UINT)inpw(REG_PWM_PCR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPCR.field.ch0_inverter = nStatus;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPCR.field.ch1_inverter = nStatus;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPCR.field.ch2_inverter = nStatus;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPCR.field.ch3_inverter = nStatus;
+        break;
+    }
+    }
+    outpw(REG_PWM_PCR, PWMPCR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function set PWM channel n toggle/one shot mode according to the
+  *        parameter nTimerIdentity and nStatus
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nStatus PWM_TOGGLE/PWM_ONESHOT
+  * @retval Successful Set operation mode successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidModeStatus Operating mode error
+  */
+static INT pwmSetMode(const INT nTimerIdentity, INT nStatus)
+{
+    typePCR PWMPCR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nStatus != PWM_TOGGLE && nStatus != PWM_ONESHOT)
+    {
+        return pwmInvalidModeStatus;// PCR inverter value error
+    }
+    PWMPCR.value = (UINT)inpw(REG_PWM_PCR);
+    switch (nTimerIdentity)
+    {
+    case PWM_TIMER0:
+    {
+        PWMPCR.field.ch0_mode = nStatus;
+        break;
+    }
+    case PWM_TIMER1:
+    {
+        PWMPCR.field.ch1_mode = nStatus;
+        break;
+    }
+    case PWM_TIMER2:
+    {
+        PWMPCR.field.ch2_mode = nStatus;
+        break;
+    }
+    case PWM_TIMER3:
+    {
+        PWMPCR.field.ch3_mode = nStatus;
+        break;
+    }
+    }
+    outpw(REG_PWM_PCR, PWMPCR.value);
+    bPWMTimerMode[nTimerIdentity] = nStatus;
+
+    return Successful;
+}
+
+
+/**
+  * @brief This function set PWM_CNRn value according to the parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue CNR value
+  * @retval Successful Set CNR successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidCNRValue Invalid CNR value
+  */
+static INT pwmSetCNR(const INT nTimerIdentity, INT nValue)
+{
+    typeCNR PWMCNR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nValue < CNR_MIN || nValue > CNR_MAX)
+    {
+        return pwmInvalidCNRValue;// PCR inverter value error
+    }
+    PWMCNR.field.cnr = nValue;
+    outpw(REG_PWM_CNR0 + (PWM_OFFSET * nTimerIdentity), PWMCNR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function set PWM_CMRn value according to the parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue CMR value
+  * @retval Successful Set CMR successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval pwmInvalidCMRValue Invalid CMR value
+  */
+static INT pwmSetCMR(const INT nTimerIdentity, INT nValue)
+{
+    typeCMR PWMCMR;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    if (nValue < CMR_MIN || nValue > CMR_MAX)
+    {
+        return pwmInvalidCMRValue;// CMR value error
+    }
+    PWMCMR.field.cmr = nValue;
+    outpw(REG_PWM_CMR0 + (PWM_OFFSET * nTimerIdentity), PWMCMR.value);
+
+    return Successful;
+}
+
+/**
+  * @brief This function return the PDR value of PWM timer n
+  * @param[in] nTimerIdentity Timer channel number
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  * @retval Others Current PDR value
+  */
+static UINT pwmGetPDR(const INT nTimerIdentity)
+{
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    else
+    {
+        return (UINT)inpw(REG_PWM_PDR0 + (PWM_OFFSET * nTimerIdentity)); // Return PDR value
+    }
+}
+
+/**
+  * @brief This function set the PIERn bit of PWM timer n as 1 or 0 according to the
+  *        parameter nTimerIdentity and nValue
+  * @param[in] nTimerIdentity Timer channel number
+  * @param[in] nValue PWM_ENABLE/PWM_DISABLE
+  * @retval Successful Set PIER successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmSetPIER(const INT nTimerIdentity, INT nValue)
+{
+    UINT uRegisterValue = 0;;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// Timer_num value error
+    }
+    else
+    {
+        uRegisterValue = (UINT)inpw(REG_PWM_PIER);
+        if (nValue == PWM_ENABLE)
+        {
+            uRegisterValue = uRegisterValue | (1 << nTimerIdentity); // Set PIER
+        }
+        else
+        {
+            uRegisterValue = uRegisterValue & (0 << nTimerIdentity); // Clear PIER
+        }
+        outpw(REG_PWM_PIER, uRegisterValue);// Write value to PIER
+
+        return Successful;
+    }
+}
+
+
+/**
+  * @brief This function clear PIIRn bit according to the parameter nTimerIdentity
+  * @param[in] nTimerIdentity Timer channel number
+  * @retval Successful Clear PIIR successfully
+  * @retval pwmInvalidTimerChannel PWM Timer channel number error
+  */
+static INT pwmCleanPIIR(const INT nTimerIdentity)
+{
+    UINT uRegisterValue = 0;
+    if (nTimerIdentity < PWM_TIMER_MIN || nTimerIdentity > PWM_TIMER_MAX)
+    {
+        return pwmInvalidTimerChannel;// nTimerIdentity value error
+    }
+    uRegisterValue = (UINT)inpw(REG_PWM_PIIR);
+    uRegisterValue = uRegisterValue & ~(1 << nTimerIdentity);
+    outpw(REG_PWM_PIIR, uRegisterValue);
+
+    return Successful;
+}
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group N9H30_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_PWM_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_rtc.c

@@ -0,0 +1,1153 @@
+/**************************************************************************//**
+* @file     RTC.c
+* @brief    N9H30 RTC driver source file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_rtc.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup N9H30_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+static CHAR g_chHourMode = 0;
+static BOOL volatile g_bIsEnableTickInt  = FALSE;
+static BOOL volatile g_bIsEnableAlarmInt = FALSE;
+
+static UINT32 volatile g_u32Reg, g_u32Reg1, g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static UINT32 volatile g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+UINT32 volatile i, Wait;
+
+VOID RTC_Check(void)
+{
+    i = 0;
+
+    Wait = inp32(REG_RTC_INTSTS) & RTC_INTSTS_REGWRBUSY_Msk;
+
+    while (Wait == RTC_INTSTS_REGWRBUSY_Msk)
+    {
+
+        Wait = inp32(REG_RTC_INTSTS) & RTC_INTSTS_REGWRBUSY_Msk;
+
+        i++;
+
+        if (i > RTC_WAIT_COUNT)
+        {
+            break;
+        }
+    }
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+  * @brief      Set 32k Frequency Compensation Data
+  *
+  * @param[in]  i32FrequencyX100    Specify the RTC clock X100, ex: 3277365 means 32773.65.
+  *
+  * @return     E_RTC_ERR_FCR_VALUE   Wrong Compensation VALUE
+  *             E_RTC_SUCCESS         Success
+  *
+  * @details    This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.
+  */
+UINT32 RTC_DoFrequencyCompensation(INT32 i32FrequencyX100)
+{
+    INT32 i32RegInt, i32RegFra;
+    UINT32 u32Reg;
+
+    /* Compute integer and fraction for RTC FCR register */
+    i32RegInt = (i32FrequencyX100 / 100) - RTC_FCR_REFERENCE;
+    i32RegFra = (((i32FrequencyX100 % 100)) * 60) / 100;
+
+    /* Judge Integer part is reasonable */
+    if ((i32RegInt < 0) | (i32RegInt > 15))
+    {
+        return E_RTC_ERR_FCR_VALUE;
+    }
+
+    u32Reg = (uint32_t)((i32RegInt << 8) | i32RegFra);
+
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_FREQADJ, u32Reg);
+    RTC_Check();
+
+    return E_RTC_SUCCESS;
+}
+
+/**
+  * @brief      RTC access register enable
+  *
+  * @param[in]  bEnable    1: Enable access register
+  *                        0: Disable access register
+  *
+  * @retval     E_RTC_ERR_EIO   Time-out error
+  * @retval     E_RTC_SUCCESS   Success
+  *
+  */
+UINT32 RTC_WriteEnable(BOOL bEnable)
+{
+    INT32 volatile i32i;
+
+    RTC_Check();
+
+    if (bEnable)
+    {
+        outp32(REG_RTC_RWEN, RTC_WRITE_KEY);
+        RTC_Check();
+
+        for (i32i = 0 ; i32i < RTC_WAIT_COUNT ; i32i++)
+        {
+            /*-------------------------------------------------------------------------------------------------*/
+            /* check RTC_RWEN[16] to find out RTC write enable                                                  */
+            /*-------------------------------------------------------------------------------------------------*/
+            if (inp32(REG_RTC_RWEN) & 0x10000)
+            {
+                break;
+            }
+        }
+
+        if (i32i == RTC_WAIT_COUNT)
+        {
+            //sysprintf ("\nRTC: 3, set write enable FAILED!\n");
+
+            return E_RTC_ERR_EIO;
+        }
+    }
+    else
+    {
+        for (i32i = 0 ; i32i < RTC_WAIT_COUNT ; i32i++)
+        {
+            if (inp32(REG_RTC_RWEN) == 0)
+            {
+                break;
+            }
+        }
+    }
+
+    return E_RTC_SUCCESS;
+}
+
+/**
+  * @brief      Initial RTC and install ISR
+  * @retval     E_RTC_ERR_EIO   Initial RTC time-out
+  * @retval     E_RTC_SUCCESS   Success
+  *
+  */
+UINT32 RTC_Init(void)
+{
+    INT32 i32i;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* When RTC is power on, write 0xa5eb1357 to RTC_INIR to reset all logic.                              */
+    /*-----------------------------------------------------------------------------------------------------*/
+
+    outp32(REG_RTC_INIT, RTC_INIT_KEY);
+    RTC_Check();
+
+    for (i32i = 0 ; i32i < RTC_WAIT_COUNT ; i32i++)
+    {
+        if (inp32(REG_RTC_INIT) & 0x01)
+        {
+            /* Check RTC_INIR[0] to find out RTC reset signal */
+            break;
+        }
+    }
+
+    if (i32i == RTC_WAIT_COUNT)
+    {
+        return E_RTC_ERR_EIO;
+    }
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Install RTC ISR                                                                                     */
+    /*-----------------------------------------------------------------------------------------------------*/
+
+    outp32(REG_RTC_RWEN, RTC_WRITE_KEY);
+    RTC_Check();
+
+    for (i32i = 0 ; i32i < RTC_WAIT_COUNT ; i32i++)
+    {
+        /*-------------------------------------------------------------------------------------------------*/
+        /* check RTC_RWEN[16] to find out RTC write enable                                                 */
+        /*-------------------------------------------------------------------------------------------------*/
+        if (inp32(REG_RTC_RWEN) & 0x10000)
+        {
+            break;
+        }
+    }
+
+    if (i32i == RTC_WAIT_COUNT)
+    {
+        return E_RTC_ERR_EIO;
+    }
+
+    return E_RTC_SUCCESS;
+}
+
+/**
+  * @brief      Set Current Timer
+  *
+  * @param[in]  *sPt    Specify the time property and current time. It includes:
+  *                  -   u8cClockDisplay: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24
+  *                  -   u8cAmPm: \ref RTC_AM / \ref RTC_PM
+  *                  -   u32cSecond: Second value
+  *                  -   u32cMinute: Minute value
+  *                  -   u32cHour: Hour value
+  *                  -   u32cDayOfWeek: Day of week
+  *                  -   u32cDay: Day value
+  *                  -   u32cMonth: Month value
+  *                  -   u32Year: Year value
+  *                  -   u32AlarmMaskSecond: Mask second alarm
+  *                  -   u32AlarmMaskMinute: Mask minute alarm
+  *                  -   u32AlarmMaskHour: Mask hour alarm
+  *                  -   *pfnAlarmCallBack: Call back function
+  *
+  * @retval     E_RTC_ERR_EIO   Initial RTC time-out
+  * @retval     E_RTC_SUCCESS   Success
+  *
+  */
+UINT32 RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+    UINT32 volatile u32Reg;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* DO BASIC JUDGEMENT TO Check RTC time data value is reasonable or not.                               */
+    /*-----------------------------------------------------------------------------------------------------*/
+    if (((sPt->u32Year - RTC_YEAR2000) > 99) |
+            ((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12)) |
+            ((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31)))
+    {
+        return E_RTC_ERR_CALENDAR_VALUE;
+    }
+
+    if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+    {
+        if ((sPt->u32cHour == 0) || (sPt->u32cHour > 12))
+        {
+            return E_RTC_ERR_TIMESACLE_VALUE ;
+        }
+    }
+    else if (sPt->u8cClockDisplay == RTC_CLOCK_24)
+    {
+        if (sPt->u32cHour > 23)
+        {
+            return E_RTC_ERR_TIMESACLE_VALUE ;
+        }
+    }
+    else
+    {
+        return E_RTC_ERR_TIMESACLE_VALUE ;
+    }
+
+    if ((sPt->u32cMinute > 59) |
+            (sPt->u32cSecond > 59) |
+            (sPt->u32cSecond > 59))
+    {
+        return E_RTC_ERR_TIME_VALUE ;
+    }
+    if (sPt->u32cDayOfWeek > 6)
+    {
+        return E_RTC_ERR_DWR_VALUE ;
+    }
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Second, set RTC time data.                                                                          */
+    /*-----------------------------------------------------------------------------------------------------*/
+    if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+    {
+        g_chHourMode = RTC_CLOCK_12;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_TIMEFMT, RTC_CLOCK_12);
+        RTC_Check();
+
+        /*-------------------------------------------------------------------------------------------------*/
+        /* important, range of 12-hour PM mode is 21 upto 32                                               */
+        /*-------------------------------------------------------------------------------------------------*/
+        if (sPt->u8cAmPm == RTC_PM)
+            sPt->u32cHour += 20;
+    }
+    else                                                                               /* RTC_CLOCK_24 */
+    {
+        g_chHourMode = RTC_CLOCK_24;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_TIMEFMT, RTC_CLOCK_24);
+        RTC_Check();
+    }
+
+
+    g_u32hiHour  = sPt->u32cHour / 10;
+    g_u32loHour  = sPt->u32cHour % 10;
+    g_u32hiMin   = sPt->u32cMinute / 10;
+    g_u32loMin   = sPt->u32cMinute % 10;
+    g_u32hiSec   = sPt->u32cSecond / 10;
+    g_u32loSec   = sPt->u32cSecond % 10;
+    u32Reg     = (g_u32hiHour << 20);
+    u32Reg    |= (g_u32loHour << 16);
+    u32Reg    |= (g_u32hiMin << 12);
+    u32Reg    |= (g_u32loMin << 8);
+    u32Reg    |= (g_u32hiSec << 4);
+    u32Reg    |= g_u32loSec;
+    g_u32Reg = u32Reg;
+
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_TIME, (UINT32)g_u32Reg);
+    RTC_Check();
+
+    if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+    {
+        if (sPt->u8cAmPm == RTC_PM)
+            sPt->u32cHour -= 20;
+    }
+
+    g_u32hiYear  = (sPt->u32Year - RTC_YEAR2000) / 10;
+    g_u32loYear  = (sPt->u32Year - RTC_YEAR2000) % 10;
+    g_u32hiMonth =  sPt->u32cMonth              / 10;
+    g_u32loMonth =  sPt->u32cMonth              % 10;
+    g_u32hiDay   =  sPt->u32cDay                / 10;
+    g_u32loDay   =  sPt->u32cDay                % 10;
+    u32Reg    = (g_u32hiYear << 20);
+    u32Reg    |= (g_u32loYear << 16);
+    u32Reg    |= (g_u32hiMonth << 12);
+    u32Reg    |= (g_u32loMonth << 8);
+    u32Reg    |= (g_u32hiDay << 4);
+    u32Reg    |= g_u32loDay;
+    g_u32Reg = u32Reg;
+
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_CAL, (UINT32)g_u32Reg);
+    RTC_Check();
+
+    RTC_WriteEnable(1);
+    outp32(REG_RTC_WEEKDAY, (UINT32)sPt->u32cDayOfWeek);
+    RTC_Check();
+
+    return E_RTC_SUCCESS;
+}
+
+
+/**
+  * @brief      Read current date/time or alarm date/time from RTC
+  *
+  * @param[in]   eTime  \ref RTC_CURRENT_TIME / \ref RTC_ALARM_TIME
+  * @param[out]  *sPt    Specify the time property and current time. It includes:
+  *                  -   u8cClockDisplay: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24
+  *                  -   u8cAmPm: \ref RTC_AM / \ref RTC_PM
+  *                  -   u32cSecond: Second value
+  *                  -   u32cMinute: Minute value
+  *                  -   u32cHour: Hour value
+  *                  -   u32cDayOfWeek: Day of week
+  *                  -   u32cDay: Day value
+  *                  -   u32cMonth: Month value
+  *                  -   u32Year: Year value
+  *                  -   u32AlarmMaskSecond: Mask second alarm
+  *                  -   u32AlarmMaskMinute: Mask minute alarm
+  *                  -   u32AlarmMaskHour: Mask hour alarm
+  *                  -   *pfnAlarmCallBack: Call back function
+  *
+  * @retval     E_RTC_ERR_ENOTTY   Wrong select time
+  * @retval     E_RTC_SUCCESS   Success
+  *
+  */
+UINT32 RTC_Read(E_RTC_TIME_SELECT eTime, S_RTC_TIME_DATA_T *sPt)
+{
+    UINT32 u32Tmp;
+
+    sPt->u8cClockDisplay = inp32(REG_RTC_TIMEFMT);                               /* 12/24-hour */
+    sPt->u32cDayOfWeek = inp32(REG_RTC_WEEKDAY);                                  /* Day of week */
+
+    switch (eTime)
+    {
+    case RTC_CURRENT_TIME:
+    {
+        g_u32Reg   = inp32(REG_RTC_CAL);
+        g_u32Reg1  = inp32(REG_RTC_TIME);
+        break;
+    }
+    case RTC_ALARM_TIME:
+    {
+        g_u32Reg   = inp32(REG_RTC_CALM);
+        g_u32Reg1  = inp32(REG_RTC_TALM);
+        break;
+    }
+    default:
+    {
+        return E_RTC_ERR_ENOTTY;
+    }
+    }
+
+    g_u32hiYear  = (g_u32Reg & 0xF00000) >> 20;
+    g_u32loYear  = (g_u32Reg & 0xF0000) >> 16;
+    g_u32hiMonth = (g_u32Reg & 0x1000) >> 12;
+    g_u32loMonth = (g_u32Reg & 0xF00) >> 8;
+    g_u32hiDay   = (g_u32Reg & 0x30) >> 4;
+    g_u32loDay   =  g_u32Reg & 0xF;
+
+    u32Tmp = (g_u32hiYear * 10);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year   =   u32Tmp  + RTC_YEAR2000;
+
+    u32Tmp = (g_u32hiMonth * 10);
+    sPt->u32cMonth = u32Tmp + g_u32loMonth;
+
+    u32Tmp = (g_u32hiDay * 10);
+    sPt->u32cDay   =  u32Tmp  + g_u32loDay;
+
+    g_u32hiHour = (g_u32Reg1 & 0x300000) >> 20;
+    g_u32loHour = (g_u32Reg1 & 0xF0000) >> 16;
+    g_u32hiMin  = (g_u32Reg1 & 0x7000) >> 12;
+    g_u32loMin  = (g_u32Reg1 & 0xF00) >> 8;
+    g_u32hiSec  = (g_u32Reg1 & 0x70) >> 4;
+    g_u32loSec  =  g_u32Reg1 & 0xF;
+
+    if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+    {
+        u32Tmp = (g_u32hiHour * 10);
+        u32Tmp += g_u32loHour;
+        sPt->u32cHour = u32Tmp;                                /* AM: 1~12. PM: 21~32. */
+
+        if (eTime == RTC_CURRENT_TIME)
+        {
+            if (sPt->u32cHour >= 21)
+            {
+                sPt->u8cAmPm = RTC_PM;
+                sPt->u32cHour -= 20;
+            }
+            else
+            {
+                sPt->u8cAmPm = RTC_AM;
+            }
+        }
+        else
+        {
+            if (sPt->u32cHour < 12)
+            {
+                if (sPt->u32cHour == 0)
+                    sPt->u32cHour = 12;
+                sPt->u8cAmPm = RTC_AM;
+            }
+            else
+            {
+                sPt->u32cHour -= 12;
+                sPt->u8cAmPm = RTC_PM;
+            }
+        }
+
+        u32Tmp = (g_u32hiMin  * 10);
+        u32Tmp += g_u32loMin;
+        sPt->u32cMinute = u32Tmp;
+
+        u32Tmp = (g_u32hiSec  * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32cSecond = u32Tmp;
+
+    }
+    else
+    {
+        /* RTC_CLOCK_24 */
+        u32Tmp = (g_u32hiHour * 10);
+        u32Tmp += g_u32loHour;
+        sPt->u32cHour   = u32Tmp;
+
+        u32Tmp = (g_u32hiMin  * 10);
+        u32Tmp += g_u32loMin;
+        sPt->u32cMinute = u32Tmp;
+
+        u32Tmp = (g_u32hiSec  * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32cSecond = u32Tmp;
+    }
+
+    return E_RTC_SUCCESS;
+
+}
+
+
+/**
+  * @brief      Write current date/time or alarm date/time from RTC
+  *
+  * @param[in]   eTime  \ref RTC_CURRENT_TIME / \ref RTC_ALARM_TIME
+  * @param[in]  *sPt     Specify the time property and current time. It includes:
+  *                  -   u8cClockDisplay: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24
+  *                  -   u8cAmPm: \ref RTC_AM / \ref RTC_PM
+  *                  -   u32cSecond: Second value
+  *                  -   u32cMinute: Minute value
+  *                  -   u32cHour: Hour value
+  *                  -   u32cDayOfWeek: Day of week
+  *                  -   u32cDay: Day value
+  *                  -   u32cMonth: Month value
+  *                  -   u32Year: Year value
+  *                  -   u32AlarmMaskSecond: Mask second alarm
+  *                  -   u32AlarmMaskMinute: Mask minute alarm
+  *                  -   u32AlarmMaskHour: Mask hour alarm
+  *                  -   *pfnAlarmCallBack: Call back function
+  *
+  * @retval     E_RTC_ERR_ENOTTY            Wrong select time
+  * @retval     E_RTC_ERR_CALENDAR_VALUE    Wrong calender value
+  * @retval     E_RTC_ERR_TIME_VALUE        Wrong time value
+  * @retval     E_RTC_ERR_DWR_VALUE         Wrong day of week value
+  * @retval     E_RTC_SUCCESS               Success
+  *
+  */
+UINT32 RTC_Write(E_RTC_TIME_SELECT eTime, S_RTC_TIME_DATA_T *sPt)
+{
+    UINT32 u32Reg;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Check RTC time data value is reasonable or not.                                                     */
+    /*-----------------------------------------------------------------------------------------------------*/
+    if (((sPt->u32Year - RTC_YEAR2000) > 99) |
+            ((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12)) |
+            ((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31)))
+    {
+        return E_RTC_ERR_CALENDAR_VALUE;
+    }
+
+    if ((sPt->u32Year - RTC_YEAR2000) > 99)
+    {
+        return E_RTC_ERR_CALENDAR_VALUE;
+    }
+
+    if ((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))
+    {
+        return E_RTC_ERR_CALENDAR_VALUE;
+    }
+
+    if ((sPt->u32cDay == 0) || (sPt->u32cDay > 31))
+    {
+        return E_RTC_ERR_CALENDAR_VALUE;
+    }
+
+    if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+    {
+        if ((sPt->u32cHour == 0) || (sPt->u32cHour > 12))
+        {
+            return E_RTC_ERR_TIME_VALUE;
+        }
+    }
+    else if (sPt->u8cClockDisplay == RTC_CLOCK_24)
+    {
+        if (sPt->u32cHour > 23)
+        {
+            return E_RTC_ERR_TIME_VALUE;
+        }
+    }
+    else
+    {
+        return E_RTC_ERR_TIME_VALUE;
+    }
+
+    if (sPt->u32cMinute > 59)
+    {
+        return E_RTC_ERR_TIME_VALUE;
+    }
+
+    if (sPt->u32cSecond > 59)
+    {
+        return E_RTC_ERR_TIME_VALUE;
+    }
+
+    if (sPt->u32cDayOfWeek > 6)
+    {
+        return E_RTC_ERR_DWR_VALUE;
+    }
+
+    switch (eTime)
+    {
+
+    case RTC_CURRENT_TIME:
+    {
+        /*---------------------------------------------------------------------------------------------*/
+        /* Second, set RTC time data.                                                                  */
+        /*---------------------------------------------------------------------------------------------*/
+
+        if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+        {
+            g_chHourMode = RTC_CLOCK_12;
+
+            RTC_WriteEnable(1);
+            outp32(REG_RTC_TIMEFMT, RTC_CLOCK_12);
+            RTC_Check();
+
+            /*-----------------------------------------------------------------------------------------*/
+            /* important, range of 12-hour PM mode is 21 upto 32                                       */
+            /*-----------------------------------------------------------------------------------------*/
+            if (sPt->u8cAmPm == RTC_PM)
+            {
+                sPt->u32cHour += 20;
+            }
+        }
+        else                                                                  /* RTC_CLOCK_24 */
+        {
+            g_chHourMode = RTC_CLOCK_24;
+
+            RTC_WriteEnable(1);
+            outp32(REG_RTC_TIMEFMT, RTC_CLOCK_24);
+            RTC_Check();
+
+        }
+
+        g_u32hiHour  = sPt->u32cHour / 10;
+        g_u32loHour  = sPt->u32cHour % 10;
+        g_u32hiMin   = sPt->u32cMinute / 10;
+        g_u32loMin   = sPt->u32cMinute % 10;
+        g_u32hiSec   = sPt->u32cSecond / 10;
+        g_u32loSec   = sPt->u32cSecond % 10;
+
+        u32Reg = (g_u32hiHour << 20);
+        u32Reg |= (g_u32loHour << 16);
+        u32Reg |= (g_u32hiMin << 12);
+        u32Reg |= (g_u32loMin << 8);
+        u32Reg |= (g_u32hiSec << 4);
+        u32Reg |= g_u32loSec;
+        g_u32Reg = u32Reg;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_TIME, (UINT32)g_u32Reg);
+        RTC_Check();
+
+        g_u32hiYear  = (sPt->u32Year - RTC_YEAR2000) / 10;
+        g_u32loYear  = (sPt->u32Year - RTC_YEAR2000) % 10;
+        g_u32hiMonth = sPt->u32cMonth / 10;
+        g_u32loMonth = sPt->u32cMonth % 10;
+        g_u32hiDay   = sPt->u32cDay / 10;
+        g_u32loDay   = sPt->u32cDay % 10;
+
+        u32Reg = (g_u32hiYear << 20);
+        u32Reg |= (g_u32loYear << 16);
+        u32Reg |= (g_u32hiMonth << 12);
+        u32Reg |= (g_u32loMonth << 8);
+        u32Reg |= (g_u32hiDay << 4);
+        u32Reg |= g_u32loDay;
+        g_u32Reg = u32Reg;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_CAL, (UINT32)g_u32Reg);
+        RTC_Check();
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_WEEKDAY, (UINT32) sPt->u32cDayOfWeek);
+        RTC_Check();
+
+        if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+        {
+            if (sPt->u8cAmPm == RTC_PM)
+            {
+                sPt->u32cHour -= 20;
+            }
+        }
+
+        return E_RTC_SUCCESS;
+
+    }
+    case RTC_ALARM_TIME:
+    {
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, inp32(REG_RTC_PWRCTL) & ~RTC_PWRCTL_ALARM_EN_Msk);
+        RTC_Check();
+
+        /*---------------------------------------------------------------------------------------------*/
+        /* Second, set alarm time data.                                                                */
+        /*---------------------------------------------------------------------------------------------*/
+        g_u32hiYear = (sPt->u32Year - RTC_YEAR2000) / 10;
+        g_u32loYear = (sPt->u32Year - RTC_YEAR2000) % 10;
+        g_u32hiMonth = sPt->u32cMonth / 10;
+        g_u32loMonth = sPt->u32cMonth % 10;
+        g_u32hiDay = sPt->u32cDay / 10;
+        g_u32loDay = sPt->u32cDay % 10;
+
+        //u32Reg = ((sPt->u32AlarmMaskDayOfWeek & 0x1) << 31);
+        u32Reg = ((sPt->u32cDayOfWeek & 0x7) << 24);
+        //u32Reg|= ((sPt->u32AlarmMaskYear & 0x1) << 30);
+        u32Reg |= (g_u32hiYear << 20);
+        u32Reg |= (g_u32loYear << 16);
+        //u32Reg|= ((sPt->u32AlarmMaskMonth & 0x1) << 29);
+        u32Reg |= (g_u32hiMonth << 12);
+        u32Reg |= (g_u32loMonth << 8);
+        //u32Reg|= ((sPt->u32AlarmMaskDay & 0x1) << 28);
+        u32Reg |= (g_u32hiDay << 4);
+        u32Reg |= g_u32loDay;
+
+        g_u32Reg = u32Reg;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_CALM, (UINT32)g_u32Reg);
+        RTC_Check();
+
+
+        if (g_chHourMode == RTC_CLOCK_12)
+        {
+            if (sPt->u8cAmPm == RTC_PM)       /* important, range of 12-hour PM mode is 21 upto 32 */
+            {
+                sPt->u32cHour += 20;
+            }
+        }
+        g_u32hiHour   = sPt->u32cHour / 10;
+        g_u32loHour   = sPt->u32cHour % 10;
+        g_u32hiMin  = sPt->u32cMinute / 10;
+        g_u32loMin  = sPt->u32cMinute % 10;
+        g_u32hiSec  = sPt->u32cSecond / 10;
+        g_u32loSec  = sPt->u32cSecond % 10;
+
+        u32Reg = ((sPt->u32AlarmMaskHour & 0x1) << 30);
+        u32Reg |= (g_u32hiHour << 20);
+        u32Reg |= (g_u32loHour << 16);
+        u32Reg |= ((sPt->u32AlarmMaskMinute & 0x1) << 29);
+        u32Reg |= (g_u32hiMin << 12);
+        u32Reg |= (g_u32loMin << 8);
+        u32Reg |= ((sPt->u32AlarmMaskSecond & 0x1) << 28);
+        u32Reg |= (g_u32hiSec << 4);
+        u32Reg |= g_u32loSec;
+
+        g_u32Reg = u32Reg;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_TALM, (UINT32)g_u32Reg);
+        RTC_Check();
+
+        if (sPt->u8cClockDisplay == RTC_CLOCK_12)
+        {
+            if (sPt->u8cAmPm == RTC_PM)
+            {
+                sPt->u32cHour -= 20;
+            }
+        }
+        /*---------------------------------------------------------------------------------------------*/
+        /* Finally, enable alarm interrupt.                                                            */
+        /*---------------------------------------------------------------------------------------------*/
+
+        RTC_Ioctl(0, RTC_IOC_ENABLE_INT, RTC_ALARM_INT, 0);
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, inp32(REG_RTC_PWRCTL) | RTC_PWRCTL_ALARM_EN_Msk);
+        RTC_Check();
+
+        return E_RTC_SUCCESS;
+    }
+    default:
+    {
+        return E_RTC_ERR_ENOTTY;
+    }
+    }
+
+}
+
+
+/**
+  * @brief      Support some commands for application.
+  *
+  * @param[in]   i32Num     Interface number.   always set 0
+  * @param[in]   eCmd       Command
+  * @param[in]   u32Arg0    Arguments for the command
+  * @param[in]   u32Arg1    Arguments for the command.
+  *
+  * @retval     E_RTC_ERR_ENOTTY            Wrong command or argument
+  * @retval     E_RTC_ERR_ENODEV            Interface number incorrect
+  * @retval     E_RTC_SUCCESS               Success
+  *
+  */
+UINT32 RTC_Ioctl(INT32 i32Num, E_RTC_CMD eCmd, UINT32 u32Arg0, UINT32 u32Arg1)
+{
+    INT32 i32Ret;
+    UINT32 u32Reg;
+    RTC_TICK_T *ptick;
+    UINT32 u32Tmp;
+
+    if (i32Num != 0)
+        return E_RTC_ERR_ENODEV;
+
+    switch (eCmd)
+    {
+
+    case RTC_IOC_IDENTIFY_LEAP_YEAR:
+    {
+        u32Reg = inp32(REG_RTC_LEAPYEAR);
+        if (u32Reg & 0x01)
+        {
+            *(PUINT32)u32Arg0 = RTC_LEAP_YEAR;
+        }
+        else
+        {
+            *(PUINT32)u32Arg0 = 0;
+        }
+        break;
+    }
+    case RTC_IOC_SET_TICK_MODE:
+    {
+        ptick = (RTC_TICK_T *) u32Arg0;
+
+        if (g_bIsEnableTickInt == TRUE)
+        {
+            RTC_Ioctl(0, RTC_IOC_DISABLE_INT, RTC_TICK_INT, 0);
+            g_bIsEnableTickInt = TRUE;
+        }
+
+        if (ptick->ucMode > RTC_TICK_1_128_SEC)                            /*Tick mode 0 to 7 */
+        {
+            return E_RTC_ERR_ENOTTY ;
+        }
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_TICK, ptick->ucMode);
+        RTC_Check();
+
+        /*---------------------------------------------------------------------------------------------*/
+        /* Reset tick interrupt status if program enable tick interrupt before.                        */
+        /*---------------------------------------------------------------------------------------------*/
+        if (g_bIsEnableTickInt == TRUE)
+        {
+
+            RTC_Ioctl(0, RTC_IOC_ENABLE_INT, RTC_TICK_INT, 0);
+
+            return E_RTC_SUCCESS;
+        }
+        break;
+    }
+
+    case RTC_IOC_GET_TICK:
+    {
+        break;
+    }
+
+    case RTC_IOC_RESTORE_TICK:
+    {
+        break;
+    }
+
+    case RTC_IOC_ENABLE_INT:
+    {
+
+        switch ((RTC_INT_SOURCE)u32Arg0)
+        {
+
+        case RTC_TICK_INT:
+        {
+            g_bIsEnableTickInt   = TRUE;
+            u32Tmp = inp32(REG_RTC_INTEN) | RTC_TICK_INT;
+            break;
+        }
+        case RTC_ALARM_INT:
+        {
+            g_bIsEnableAlarmInt  = TRUE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_PWRCTL) | RTC_PWRCTL_ALARM_EN_Msk;
+
+            outp32(REG_RTC_PWRCTL, u32Tmp);
+            outp32(REG_RTC_INTEN, inp32(REG_RTC_INTEN) | RTC_INTEN_ALMIEN_Msk);
+
+            RTC_Check();
+
+            u32Tmp = inp32(REG_RTC_INTEN) | RTC_ALARM_INT;
+
+            break;
+        }
+        case RTC_RELATIVE_ALARM_INT:
+        {
+            g_bIsEnableAlarmInt  = TRUE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_PWRCTL) | RTC_PWRCTL_REL_ALARM_EN_Msk;
+
+            outp32(REG_RTC_PWRCTL, u32Tmp);
+            RTC_Check();
+
+            u32Tmp = inp32(REG_RTC_INTEN) | RTC_RELATIVE_ALARM_INT;
+            break;
+        }
+        case RTC_PSWI_INT:
+        {
+            g_bIsEnableAlarmInt  = TRUE;
+            u32Tmp = inp32(REG_RTC_INTEN) | RTC_PSWI_INT;
+            break;
+        }
+        default:
+        {
+            return E_RTC_ERR_ENOTTY;
+
+        }
+        }
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_INTEN, u32Tmp);
+        RTC_Check();
+
+        break;
+    }
+    case RTC_IOC_DISABLE_INT:
+    {
+
+        switch ((RTC_INT_SOURCE)u32Arg0)
+        {
+        case RTC_TICK_INT:
+        {
+            g_bIsEnableTickInt   = FALSE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_INTEN) & (~RTC_TICK_INT);
+
+            outp32(REG_RTC_INTEN, u32Tmp);
+
+            outp32(REG_RTC_INTSTS, RTC_TICK_INT);
+            RTC_Check();
+
+            break;
+        }
+        case RTC_ALARM_INT:
+        {
+            g_bIsEnableAlarmInt  = FALSE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_INTEN) & (~RTC_ALARM_INT);
+
+            outp32(REG_RTC_INTEN, u32Tmp);
+            RTC_Check();
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_PWRCTL) & ~RTC_PWRCTL_ALARM_EN_Msk;
+
+            outp32(REG_RTC_PWRCTL, u32Tmp);
+            RTC_Check();
+
+            outp32(REG_RTC_INTSTS, RTC_ALARM_INT);
+
+            break;
+        }
+        case RTC_RELATIVE_ALARM_INT:
+        {
+            g_bIsEnableAlarmInt  = FALSE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_INTEN) & (~RTC_RELATIVE_ALARM_INT);
+
+            outp32(REG_RTC_INTEN, u32Tmp);
+            RTC_Check();
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_PWRCTL) & ~RTC_PWRCTL_REL_ALARM_EN_Msk;
+
+            outp32(REG_RTC_PWRCTL, u32Tmp);
+            RTC_Check();
+
+            outp32(REG_RTC_INTSTS, RTC_RELATIVE_ALARM_INT);
+
+            break;
+        }
+        case RTC_PSWI_INT:
+        {
+            g_bIsEnableAlarmInt  = FALSE;
+
+            RTC_WriteEnable(1);
+            u32Tmp = inp32(REG_RTC_INTEN) & (~RTC_PSWI_INT);
+
+            outp32(REG_RTC_INTEN, u32Tmp);
+            RTC_Check();
+
+            outp32(REG_RTC_INTSTS, RTC_PSWI_INT);
+
+            break;
+        }
+
+        case RTC_ALL_INT:
+        {
+            g_bIsEnableTickInt   = FALSE;
+            g_bIsEnableAlarmInt  = FALSE;
+
+            RTC_WriteEnable(1);
+            outp32(REG_RTC_INTEN, 0);
+            outp32(REG_RTC_INTSTS, RTC_ALL_INT);
+            RTC_Check();
+
+            break;
+        }
+        default:
+        {
+            return E_RTC_ERR_ENOTTY;
+        }
+        }
+
+
+        break;
+    }
+
+    case RTC_IOC_SET_FREQUENCY:
+    {
+        i32Ret = RTC_DoFrequencyCompensation(u32Arg0) ;
+        if (i32Ret != 0)
+        {
+            return E_RTC_ERR_ENOTTY;
+        }
+        break;
+    }
+    case RTC_IOC_SET_POWER_ON:
+    {
+        RTC_WriteEnable(1);
+        u32Tmp = inp32(REG_RTC_PWRCTL) | 0x01;
+
+        outp32(REG_RTC_PWRCTL, u32Tmp);
+        RTC_Check();
+
+        while ((inp32(REG_RTC_PWRCTL) & 0x01) != 0x1);
+
+        break;
+    }
+    case RTC_IOC_SET_POWER_OFF:
+    {
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, (inp32(REG_RTC_PWRCTL) & ~0x01) | 2);
+        RTC_Check();
+
+        while (1);
+
+        //break;
+    }
+    case RTC_IOC_SET_POWER_OFF_PERIOD:
+    {
+        if (u32Arg0 < 4) u32Arg0 = 4;
+
+        u32Arg0 = u32Arg0 - 4;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, (inp32(REG_RTC_PWRCTL) & ~0xF000) | ((u32Arg0 & 0xF) << 12));
+        RTC_Check();
+
+        break;
+    }
+    case RTC_IOC_ENABLE_HW_POWEROFF:
+    {
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, (inp32(REG_RTC_PWRCTL) | 0x04));
+        RTC_Check();
+
+        break;
+    }
+    case RTC_IOC_DISABLE_HW_POWEROFF:
+    {
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, (inp32(REG_RTC_PWRCTL) & ~0x04));
+        RTC_Check();
+
+        break;
+    }
+    case RTC_IOC_SET_PSWI_CALLBACK:
+    {
+
+        RTC_Ioctl(0, RTC_IOC_ENABLE_INT, RTC_PSWI_INT, 0);
+
+        break;
+    }
+    case RTC_IOC_GET_POWERKEY_STATUS:
+    {
+        RTC_WriteEnable(1);
+        if (inp32(REG_RTC_PWRCTL) & 0x80)
+            *(PUINT32)u32Arg0 = 1;
+        else
+            *(PUINT32)u32Arg0 = 0;
+
+        break;
+    }
+    case RTC_IOC_SET_RELEATIVE_ALARM:
+    {
+        g_bIsEnableAlarmInt  = TRUE;
+
+        RTC_WriteEnable(1);
+        outp32(REG_RTC_PWRCTL, (inp32(REG_RTC_PWRCTL) & ~0xFFF0010));
+        RTC_Check();
+
+        RTC_WriteEnable(1);
+        u32Tmp = (inp32(REG_RTC_PWRCTL) & ~0xFFF0000) | ((u32Arg0 & 0xFFF) << 16) | RTC_PWRCTL_REL_ALARM_EN_Msk;
+
+        outp32(REG_RTC_PWRCTL, u32Tmp);
+        RTC_Check();
+
+        g_bIsEnableAlarmInt  = TRUE;
+
+        RTC_WriteEnable(1);
+        u32Tmp = inp32(REG_RTC_INTEN) | RTC_RELATIVE_ALARM_INT;
+
+        outp32(REG_RTC_INTEN, u32Tmp);
+        RTC_Check();
+
+        break;
+
+    }
+
+    default:
+    {
+        return E_RTC_ERR_ENOTTY;
+    }
+    }
+
+    return E_RTC_SUCCESS;
+}
+
+/**
+  * @brief      Disable AIC channel of RTC and both tick and alarm interrupt.
+  *
+  * @param[in]  None
+  *
+  * @retval     E_RTC_SUCCESS               Success
+  *
+  */
+UINT32 RTC_Close(void)
+{
+
+    g_bIsEnableTickInt = FALSE;
+
+    sysDisableInterrupt(RTC_IRQn);
+
+
+    RTC_Ioctl(0, RTC_IOC_DISABLE_INT, RTC_ALL_INT, 0);
+
+
+    return E_RTC_SUCCESS;
+}
+
+/**
+  * @brief      Enable RTC clock.
+  *
+  * @param[in]  bEnable  1: Enable \n
+  *                      2: Disable
+  *
+  * @return     None
+  *
+  */
+void RTC_EnableClock(BOOL bEnable)
+{
+    if (bEnable)
+        outp32(REG_CLK_PCLKEN0, inp32(REG_CLK_PCLKEN0) | (1 << 2));
+    else
+        outp32(REG_CLK_PCLKEN0, inp32(REG_CLK_PCLKEN0) & ~(1 << 2));
+
+}
+
+
+
+/*@}*/ /* end of group N9H30_RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_RTC_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_scuart.c

@@ -0,0 +1,246 @@
+/**************************************************************************//**
+ * @file     scuart.c
+ * @brief    N9H30 series Smartcard UART mode (SCUART) driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_scuart.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SCUART_Driver SCUART Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/**
+  * @brief Disable smartcard uart interface.
+  * @param sc Smartcard module number
+  * @return None
+  * @details The function is used to disable smartcard interface UART mode.
+  */
+void SCUART_Close(UINT sc)
+{
+    if (sc == 0)
+    {
+        outpw(REG_SC0_INTEN, 0);
+        outpw(REG_SC0_UARTCTL, 0);
+        outpw(REG_SC0_CTL, 0);
+    }
+    else
+    {
+        outpw(REG_SC1_INTEN, 0);
+        outpw(REG_SC1_UARTCTL, 0);
+        outpw(REG_SC1_CTL, 0);
+    }
+}
+
+/// @cond HIDDEN_SYMBOLS
+/**
+  * @brief This function returns module clock of specified SC interface
+  * @param[in] sc Smartcard module number
+  * @return Module clock of specified SC interface
+  */
+static uint32_t SCUART_GetClock(UINT sc)
+{
+    uint32_t u32Div;
+
+    if (sc == 0)
+        u32Div = ((inpw(REG_CLK_DIVCTL6) >> 24) & 0xF) + 1;
+    else
+        u32Div = ((inpw(REG_CLK_DIVCTL6) >> 28) & 0xF) + 1;
+
+    return 12000000 / u32Div;
+}
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+  * @brief Enable smartcard uart interface.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32baudrate Target baudrate of smartcard module.
+  * @return Actual baudrate of smartcard mode.
+  * @details This function use to enable smartcard module UART mode and set baudrate.
+  * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
+  *       And can use \ref SCUART_SetLineConfig function to update these settings.
+  */
+UINT SCUART_Open(UINT sc, UINT u32baudrate)
+{
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    // Calculate divider for target baudrate
+    u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
+
+    if (sc == 0)
+    {
+        outpw(REG_SC0_CTL, SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk);   // Enable smartcard interface and stop bit = 1
+        outpw(REG_SC0_UARTCTL, SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk); // Enable UART mode, disable parity and 8 bit per character
+        outpw(REG_SC0_ETUCTL, u32Div);
+    }
+    else
+    {
+        outpw(REG_SC1_CTL, SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk);   // Enable smartcard interface and stop bit = 1
+        outpw(REG_SC1_UARTCTL, SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk); // Enable UART mode, disable parity and 8 bit per character
+        outpw(REG_SC1_ETUCTL, u32Div);
+    }
+
+    return (u32Clk / (u32Div + 1));
+}
+
+/**
+  * @brief Read data from smartcard UART interface.
+  * @param[in] sc Smartcard module number
+  * @param[in] pu8RxBuf The buffer to store receive the data.
+  * @param[in] u32ReadBytes Target number of characters to receive.
+  * @return Actual character number reads to buffer.
+  * @details The function is used to read Rx data from RX FIFO.
+  * @note This function does not block and return immediately if there's no data available.
+  */
+UINT SCUART_Read(UINT sc, char *pu8RxBuf, UINT u32ReadBytes)
+{
+    uint32_t u32Count;
+
+    if (sc == 0)
+    {
+        for (u32Count = 0; u32Count < u32ReadBytes; u32Count++)
+        {
+            if (inpw(REG_SC0_STATUS) & SC_STATUS_RXEMPTY_Msk)  // no data available
+            {
+                break;
+            }
+            pu8RxBuf[u32Count] = inpw(REG_SC0_DAT);    // get data from FIFO
+        }
+    }
+    else
+    {
+        for (u32Count = 0; u32Count < u32ReadBytes; u32Count++)
+        {
+            if (inpw(REG_SC1_STATUS) & SC_STATUS_RXEMPTY_Msk)  // no data available
+            {
+                break;
+            }
+            pu8RxBuf[u32Count] = inpw(REG_SC1_DAT);    // get data from FIFO
+        }
+
+    }
+
+    return u32Count;
+}
+
+/**
+  * @brief This function use to config smartcard UART mode line setting.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+  * @param[in] u32DataWidth The data length, could be:
+  *                 - \ref SCUART_CHAR_LEN_5
+  *                 - \ref SCUART_CHAR_LEN_6
+  *                 - \ref SCUART_CHAR_LEN_7
+  *                 - \ref SCUART_CHAR_LEN_8
+  * @param[in] u32Parity The parity setting, could be:
+  *                 - \ref SCUART_PARITY_NONE
+  *                 - \ref SCUART_PARITY_ODD
+  *                 - \ref SCUART_PARITY_EVEN
+  * @param[in] u32StopBits The stop bit length, could be:
+  *                 - \ref SCUART_STOP_BIT_1
+  *                 - \ref SCUART_STOP_BIT_2
+  * @return Actual baudrate of smartcard.
+  * @details Smartcard UART mode is operated in LIN data frame.
+  */
+UINT SCUART_SetLineConfig(UINT sc, UINT u32Baudrate, UINT u32DataWidth, UINT u32Parity, UINT  u32StopBits)
+{
+
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    if (u32Baudrate == 0)   // keep original baudrate setting
+    {
+        u32Div = (sc == 0) ? inpw(REG_SC0_ETUCTL) & 0xFFF : inpw(REG_SC1_ETUCTL) & 0xFFF;
+    }
+    else
+    {
+        // Calculate divider for target baudrate
+        u32Div = (u32Clk + (u32Baudrate >> 1) - 1) / u32Baudrate - 1;
+        if (sc == 0)
+            outpw(REG_SC0_ETUCTL, u32Div);
+        else
+            outpw(REG_SC1_ETUCTL, u32Div);
+    }
+
+    if (sc == 0)
+    {
+        outpw(REG_SC0_CTL, u32StopBits | SC_CTL_SCEN_Msk);  // Set stop bit
+        outpw(REG_SC0_UARTCTL, u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk);   // Set character width and parity
+    }
+    else
+    {
+        outpw(REG_SC1_CTL, u32StopBits | SC_CTL_SCEN_Msk);  // Set stop bit
+        outpw(REG_SC1_UARTCTL, u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk);   // Set character width and parity
+    }
+    return (u32Clk / (u32Div + 1));
+}
+
+/**
+  * @brief This function use to set receive timeout count.
+  * @param[in] sc Smartcard module number
+  * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+  *                   set this value to 0 will disable timeout counter.
+  * @return None
+  * @details The time-out counter resets and starts counting whenever the RX buffer received a
+  *          new data word. Once the counter decrease to 1 and no new data is received or CPU
+  *          does not read any data from FIFO, a receiver time-out interrupt will be generated.
+  */
+void SCUART_SetTimeoutCnt(UINT sc, UINT u32TOC)
+{
+    if (sc == 0)
+        outpw(REG_SC0_RXTOUT, u32TOC);
+    else
+        outpw(REG_SC1_RXTOUT, u32TOC);
+}
+
+
+/**
+  * @brief Write data to smartcard UART interface.
+  * @param[in] sc Smartcard module number
+  * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+  * @param[in] u32WriteBytes Number of data to send.
+  * @return None
+  * @details This function is to write data into transmit FIFO to send data out.
+  * @note This function blocks until all data write into FIFO.
+  */
+void SCUART_Write(UINT sc, char *pu8TxBuf, UINT u32WriteBytes)
+{
+    uint32_t u32Count;
+
+    if (sc == 0)
+    {
+        for (u32Count = 0; u32Count != u32WriteBytes; u32Count++)
+        {
+            while (inpw(REG_SC0_STATUS) & SC_STATUS_TXFULL_Msk); // Wait 'til FIFO not full
+            outpw(REG_SC0_DAT, pu8TxBuf[u32Count]);    // Write 1 byte to FIFO
+        }
+    }
+    else
+    {
+        for (u32Count = 0; u32Count != u32WriteBytes; u32Count++)
+        {
+            while (inpw(REG_SC0_STATUS) & SC_STATUS_TXFULL_Msk); // Wait 'til FIFO not full
+            outpw(REG_SC1_DAT, pu8TxBuf[u32Count]);    // Write 1 byte to FIFO
+        }
+    }
+}
+
+
+/*@}*/ /* end of group N9H30_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SCUART_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_sdh.c

@@ -0,0 +1,1193 @@
+/**************************************************************************//**
+ * @file     sdh.c
+ * @brief    N9H30 SDH driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_sdh.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SDH_Driver SDH Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+#define SDH_BLOCK_SIZE   512ul
+
+/** @cond HIDDEN_SYMBOLS */
+
+/* global variables */
+/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */
+/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */
+/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */
+
+#ifdef __ICCARM__
+    #pragma data_alignment = 32
+    static uint8_t _SDH0_ucSDHCBuffer[512];
+    static uint8_t _SDH1_ucSDHCBuffer[512];
+#else
+    static uint8_t _SDH0_ucSDHCBuffer[512] __attribute__((aligned(32)));
+    static uint8_t _SDH1_ucSDHCBuffer[512] __attribute__((aligned(32)));
+#endif
+
+SDH_INFO_T SD0, SD1;
+
+void SDH_CheckRB(SDH_T *sdh)
+{
+    while (1)
+    {
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+        {
+        }
+        if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk)
+        {
+            break;
+        }
+    }
+}
+
+
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+    volatile uint32_t buf, val = 0ul;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk);
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk)
+    {
+        if (pSD->IsCardInsert == 0ul)
+        {
+            val = SDH_NO_SD_CARD;
+        }
+    }
+    return val;
+}
+
+
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount)
+{
+    volatile uint32_t buf;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
+    sdh->CTL = buf;
+
+    if (ntickCount > 0ul)
+    {
+        while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+        {
+            if (ntickCount-- == 0ul)
+            {
+                sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */
+                return 2ul;
+            }
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    }
+    else
+    {
+        while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+        {
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    }
+
+    if (pSD->R7Flag)
+    {
+        uint32_t tmp0 = 0ul, tmp1 = 0ul;
+        tmp1 = sdh->RESP1 & 0xfful;
+        tmp0 = sdh->RESP0 & 0xful;
+        if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul))
+        {
+            pSD->R7Flag = 0ul;
+            return SDH_CMD8_ERROR;
+        }
+    }
+
+    if (!pSD->R3Flag)
+    {
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk)     /* check CRC7 */
+        {
+            return Successful;
+        }
+        else
+        {
+            return SDH_CRC7_ERROR;
+        }
+    }
+    else
+    {
+        /* ignore CRC error for R3 case */
+        pSD->R3Flag = 0ul;
+        sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+        return Successful;
+    }
+}
+
+
+uint32_t SDH_Swap32(uint32_t val)
+{
+    uint32_t buf;
+
+    buf = val;
+    val <<= 24;
+    val |= (buf << 8) & 0xff0000ul;
+    val |= (buf >> 8) & 0xff00ul;
+    val |= (buf >> 24) & 0xfful;
+    return val;
+}
+
+/* Get 16 bytes CID or CSD */
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[])
+{
+    uint32_t i, buf;
+    uint32_t tmpBuf[5];
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk)
+    {
+        for (i = 0ul; i < 5ul; i++)
+        {
+            tmpBuf[i] = SDH_Swap32(sdh->FB[i]);
+        }
+        for (i = 0ul; i < 4ul; i++)
+        {
+            puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful) << 8) | ((tmpBuf[i + 1ul] & 0xff000000ul) >> 24);
+        }
+    }
+    else
+    {
+        return SDH_CRC7_ERROR;
+    }
+    return Successful;
+}
+
+
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+    volatile uint32_t buf;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) |
+          (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk)
+    {
+        /* check CRC7 */
+        return SDH_CRC7_ERROR;
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk)
+    {
+        /* check CRC16 */
+        return SDH_CRC16_ERROR;
+    }
+    return 0ul;
+}
+
+/* there are 8 bits for divider0, maximum is 256 */
+#define SDH_CLK_DIV0_MAX     256ul
+
+void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz)
+{
+    UINT32 div;
+    uint32_t SDH_ReferenceClock;
+
+    if (sd_clock_khz <= 2000)
+    {
+        SDH_ReferenceClock = 12000;
+        if (sdh == SDH0)
+        {
+            outpw(REG_CLK_DIVCTL9, (inpw(REG_CLK_DIVCTL9) & ~0x18) | (0x0 << 3));   // SD clock from XIN [4:3]
+        }
+        else
+        {
+            //fixme   outpw(REG_CLK_DIVCTL9, (inpw(REG_CLK_DIVCTL9) & ~0x18) | (0x0 << 3));   // SD clock from XIN [4:3]
+        }
+    }
+    else
+    {
+        SDH_ReferenceClock = 300000;
+        if (sdh == SDH0)
+        {
+            outpw(REG_CLK_DIVCTL9, (inpw(REG_CLK_DIVCTL9) & ~0x18) | (0x3 << 3));   // SD clock from UPLL [4:3]
+        }
+        else
+        {
+            //fixme  outpw(REG_CLK_DIVCTL9, (inpw(REG_CLK_DIVCTL9) & ~0x18) | (0x3 << 3));   // SD clock from UPLL [4:3]
+        }
+    }
+    div = (SDH_ReferenceClock / sd_clock_khz) - 1;
+
+    if (div >= SDH_CLK_DIV0_MAX)
+    {
+        div = 0xff;
+    }
+    outpw(REG_CLK_DIVCTL9, (inpw(REG_CLK_DIVCTL9) & ~0xff00) | ((div) << 8));  // SD clock divided by CLKDIV3[SD_N] [15:8]
+}
+
+uint32_t SDH_CardDetection(SDH_T *sdh)
+{
+    uint32_t i, val = TRUE;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+
+    if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk)   /* Card detect pin from GPIO */
+    {
+        if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk)   /* Card remove */
+        {
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            val = FALSE;
+        }
+        else
+        {
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        }
+    }
+    else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk)
+    {
+        sdh->CTL |= SDH_CTL_CLKKEEP_Msk;
+        for (i = 0ul; i < 5000ul; i++)
+        {
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk)   /* Card insert */
+        {
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        }
+        else
+        {
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            val = FALSE;
+        }
+
+        sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk;
+    }
+
+    return val;
+}
+
+uint32_t SDH_Init(SDH_T *sdh)
+{
+    uint32_t volatile i, status;
+    uint32_t resp;
+    uint32_t CIDBuffer[4];
+    uint32_t volatile u32CmdTimeOut;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    /* set the clock to 300KHz */
+    SDH_Set_clock(sdh, 300ul);
+
+    /* power ON 74 clock */
+    sdh->CTL |= SDH_CTL_CLK74OEN_Msk;
+
+    while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk)
+    {
+        if (pSD->IsCardInsert == FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    SDH_SDCommand(sdh, 0ul, 0ul);        /* reset all cards */
+    for (i = 0x1000ul; i > 0ul; i--)
+    {
+    }
+
+    /* initial SDHC */
+    pSD->R7Flag = 1ul;
+    u32CmdTimeOut = 0xFFFFFul;
+
+    i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut);
+    if (i == Successful)
+    {
+        /* SD 2.0 */
+        SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+        pSD->R3Flag = 1ul;
+        SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */
+        resp = sdh->RESP0;
+
+        while ((resp & 0x00800000ul) != 0x00800000ul)        /* check if card is ready */
+        {
+            SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+            pSD->R3Flag = 1ul;
+            SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+            resp = sdh->RESP0;
+        }
+        if ((resp & 0x00400000ul) == 0x00400000ul)
+        {
+            pSD->CardType = SDH_TYPE_SD_HIGH;
+        }
+        else
+        {
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        }
+    }
+    else
+    {
+        /* SD 1.1 */
+        SDH_SDCommand(sdh, 0ul, 0ul);        /* reset all cards */
+        for (i = 0x100ul; i > 0ul; i--)
+        {
+        }
+
+        i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+        if (i == 2ul)     /* MMC memory */
+        {
+
+            SDH_SDCommand(sdh, 0ul, 0ul);        /* reset */
+            for (i = 0x100ul; i > 0ul; i--)
+            {
+            }
+
+            pSD->R3Flag = 1ul;
+
+            if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul)    /* eMMC memory */
+            {
+                resp = sdh->RESP0;
+                while ((resp & 0x00800000ul) != 0x00800000ul)
+                {
+                    /* check if card is ready */
+                    pSD->R3Flag = 1ul;
+
+                    SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut);      /* high voltage */
+                    resp = sdh->RESP0;
+                }
+
+                if ((resp & 0x00400000ul) == 0x00400000ul)
+                {
+                    pSD->CardType = SDH_TYPE_EMMC;
+                }
+                else
+                {
+                    pSD->CardType = SDH_TYPE_MMC;
+                }
+            }
+            else
+            {
+                pSD->CardType = SDH_TYPE_UNKNOWN;
+                return SDH_ERR_DEVICE;
+            }
+        }
+        else if (i == 0ul)     /* SD Memory */
+        {
+            pSD->R3Flag = 1ul;
+            SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+            resp = sdh->RESP0;
+            while ((resp & 0x00800000ul) != 0x00800000ul)        /* check if card is ready */
+            {
+                SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+                pSD->R3Flag = 1ul;
+                SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+                resp = sdh->RESP0;
+            }
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        }
+        else
+        {
+            pSD->CardType = SDH_TYPE_UNKNOWN;
+            return SDH_INIT_ERROR;
+        }
+    }
+
+    if (pSD->CardType != SDH_TYPE_UNKNOWN)
+    {
+        SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer);
+        if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+        {
+            if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful)     /* set RCA */
+            {
+                return status;
+            }
+            pSD->RCA = 0x10000ul;
+        }
+        else
+        {
+            if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful)       /* get RCA */
+            {
+                return status;
+            }
+            else
+            {
+                pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000;
+            }
+        }
+    }
+    return Successful;
+}
+
+
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)
+{
+    uint32_t volatile status = 0ul;
+    uint16_t current_comsumption, busy_status0;
+
+    sdh->DMASA = (uint32_t)pSD->dmabuf;
+    sdh->BLEN = 63ul;
+
+    if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful)
+    {
+        return Fail;
+    }
+
+    current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
+    current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
+    if (!current_comsumption)
+    {
+        return Fail;
+    }
+
+    busy_status0 = (uint16_t)(*(pSD->dmabuf + 28)) << 8;
+    busy_status0 |= (uint16_t)(*(pSD->dmabuf + 29));
+
+    if (!busy_status0)   /* function ready */
+    {
+        sdh->DMASA = (uint32_t)pSD->dmabuf;
+        sdh->BLEN = 63ul;    /* 512 bit */
+
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful)
+        {
+            return Fail;
+        }
+
+        /* function change timing: 8 clocks */
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+        {
+        }
+
+        current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
+        current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
+        if (!current_comsumption)
+        {
+            return Fail;
+        }
+
+        return Successful;
+    }
+    else
+    {
+        return Fail;
+    }
+}
+
+
+uint32_t SDH_SelectCardType(SDH_T *sdh)
+{
+    uint32_t volatile status = 0ul;
+    uint32_t param;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+    {
+        return status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* if SD card set 4bit */
+    if (pSD->CardType == SDH_TYPE_SD_HIGH)
+    {
+        sdh->DMASA = (uint32_t)pSD->dmabuf;
+        sdh->BLEN = 0x07ul;  /* 64 bit */
+        sdh->DMACTL |= SDH_DMACTL_DMARST_Msk;
+        while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2);
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+        {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful)
+        {
+            return status;
+        }
+
+        if ((*pSD->dmabuf & 0xful) == 0x2ul)
+        {
+            status = SDH_SwitchToHighSpeed(sdh, pSD);
+            if (status == Successful)
+            {
+                /* divider */
+                SDH_Set_clock(sdh, SDHC_FREQ);
+            }
+        }
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+        {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful)   /* set bus width */
+        {
+            return status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    }
+    else if (pSD->CardType == SDH_TYPE_SD_LOW)
+    {
+        sdh->DMASA = (uint32_t)pSD->dmabuf;;
+        sdh->BLEN = 0x07ul;
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+        {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful)
+        {
+            return status;
+        }
+
+        /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful)
+        {
+            return status;
+        }
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful)
+        {
+            return status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    }
+    else if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+
+        if (pSD->CardType == SDH_TYPE_MMC)
+        {
+            sdh->CTL &= ~SDH_CTL_DBW_Msk;
+        }
+
+        /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */
+        /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */
+        param = (3ul << 24) | (183ul << 16) | (1ul << 8);
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful)
+        {
+            return status;
+        }
+        SDH_CheckRB(sdh);
+
+        sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
+
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful)
+    {
+        return status;
+    }
+    sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+    {
+    }
+
+    sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;
+
+    return Successful;
+}
+
+void SDH_Get_SD_info(SDH_T *sdh)
+{
+    unsigned int R_LEN, C_Size, MULT, size;
+    uint32_t Buffer[4];
+    //unsigned char *ptr;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer);
+
+    if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        /* for MMC/eMMC card */
+        if ((Buffer[0] & 0xc0000000) == 0xc0000000)
+        {
+            /* CSD_STRUCTURE [127:126] is 3 */
+            /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */
+            SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul);
+
+            //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer );
+            sdh->DMASA = (uint32_t)pSD->dmabuf;;
+            sdh->BLEN = 511ul;  /* read 512 bytes for EXT_CSD */
+
+            if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful)
+            {
+                SDH_SDCommand(sdh, 7ul, 0ul);
+                sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+                while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+                {
+                }
+
+                pSD->totalSectorN = (uint32_t)(*(pSD->dmabuf + 215)) << 24;
+                pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 214)) << 16;
+                pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 213)) << 8;
+                pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 212));
+                pSD->diskSize = pSD->totalSectorN / 2ul;
+            }
+        }
+        else
+        {
+            /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */
+            R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+            C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+            MULT = (Buffer[2] & 0x00038000ul) >> 15;
+            size = (C_Size + 1ul) * (1ul << (MULT + 2ul)) * (1ul << R_LEN);
+
+            pSD->diskSize = size / 1024ul;
+            pSD->totalSectorN = size / 512ul;
+        }
+    }
+    else
+    {
+        if ((Buffer[0] & 0xc0000000) != 0x0ul)
+        {
+            C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16);
+            size = (C_Size + 1ul) * 512ul;  /* Kbytes */
+
+            pSD->diskSize = size;
+            pSD->totalSectorN = size << 1;
+        }
+        else
+        {
+            R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+            C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+            MULT = (Buffer[2] & 0x00038000ul) >> 15;
+            size = (C_Size + 1ul) * (1ul << (MULT + 2ul)) * (1ul << R_LEN);
+
+            pSD->diskSize = size / 1024ul;
+            pSD->totalSectorN = size / 512ul;
+        }
+    }
+    pSD->sectorSize = (int)512;
+//    printf("The size is %d KB\n", pSD->diskSize);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/**
+ *  @brief  This function use to reset SD function and select card detection source and pin.
+ *
+ *  @param[in]  sdh    Select SDH0 or SDH1.
+ *  @param[in]  u32CardDetSrc   Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
+ *
+ *  @return None
+ */
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc)
+{
+    volatile int i;
+    sdh->DMACTL = SDH_DMACTL_DMARST_Msk;
+    while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk)
+    {
+    }
+
+    sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;
+
+    sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk;
+    while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk)
+    {
+    }
+
+    if (sdh == SDH0)
+    {
+        memset(&SD0, 0, sizeof(SDH_INFO_T));
+        SD0.dmabuf = (unsigned char *)((uint32_t)_SDH0_ucSDHCBuffer | 0x80000000);
+    }
+    else if (sdh == SDH1)
+    {
+        memset(&SD1, 0, sizeof(SDH_INFO_T));
+        SD1.dmabuf = (unsigned char *)((uint32_t)_SDH1_ucSDHCBuffer | 0x80000000);
+    }
+    else
+    {
+    }
+
+    sdh->GCTL = SDH_GCTL_SDEN_Msk;
+
+    if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3)
+    {
+        sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk;
+    }
+    else
+    {
+        sdh->INTEN |= SDH_INTEN_CDSRC_Msk;
+    }
+    for (i = 0; i < 0x100; i++);
+    sdh->INTSTS = SDH_INTSTS_CDIF_Msk;
+    sdh->INTEN |= SDH_INTEN_CDIEN_Msk;
+
+    sdh->CTL |= SDH_CTL_CTLRST_Msk;
+    while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk)
+    {
+    }
+}
+
+/**
+ *  @brief  This function use to initial SD card.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return None
+ *
+ *  @details This function is used to initial SD card.
+ *           SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.
+ *           And then switch back to the user's setting.
+ */
+uint32_t SDH_Probe(SDH_T *sdh)
+{
+    uint32_t val;
+
+    sdh->GINTEN = 0ul;
+    sdh->CTL &= ~SDH_CTL_SDNWR_Msk;
+    sdh->CTL |=  0x09ul << SDH_CTL_SDNWR_Pos;   /* set SDNWR = 9 */
+    sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;
+    sdh->CTL |=  0x01ul << SDH_CTL_BLKCNT_Pos;  /* set BLKCNT = 1 */
+    sdh->CTL &= ~SDH_CTL_DBW_Msk;               /* SD 1-bit data bus */
+
+    if (!(SDH_CardDetection(sdh)))
+    {
+        return SDH_NO_SD_CARD;
+    }
+
+    if ((val = SDH_Init(sdh)) != 0ul)
+    {
+        return val;
+    }
+
+    /* divider */
+    if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC))
+    {
+        SDH_Set_clock(sdh, MMC_FREQ);
+    }
+    else
+    {
+        SDH_Set_clock(sdh, SD_FREQ);
+    }
+    SDH_Get_SD_info(sdh);
+
+    if ((val = SDH_SelectCardType(sdh)) != 0ul)
+    {
+        return val;
+    }
+
+    return 0ul;
+}
+
+/**
+ *  @brief  This function use to read data from SD card.
+ *
+ *  @param[in]     sdh           Select SDH0 or SDH1.
+ *  @param[out]    pu8BufAddr    The buffer to receive the data from SD card.
+ *  @param[in]     u32StartSec   The start read sector address.
+ *  @param[in]     u32SecCount   The the read sector number of data
+ *
+ *  @return None
+ */
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile bIsSendCmd = FALSE, buf;
+    uint32_t volatile reg;
+    uint32_t volatile i, loop, status;
+    uint32_t blksize = SDH_BLOCK_SIZE;
+
+    SDH_INFO_T *pSD;
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    if (u32SecCount == 0ul)
+    {
+        return SDH_SELECT_ERROR;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+    {
+        return status;
+    }
+    SDH_CheckRB(sdh);
+
+    sdh->BLEN = blksize - 1ul;       /* the actual byte count is equal to (SDBLEN+1) */
+
+    if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        sdh->CMDARG = u32StartSec;
+    }
+    else
+    {
+        sdh->CMDARG = u32StartSec * blksize;
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+
+    loop = u32SecCount / 255ul;
+    for (i = 0ul; i < loop; i++)
+    {
+        pSD->DataReadyFlag = (uint8_t)FALSE;
+        reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;
+        reg = reg | 0xff0000ul;   /* set BLK_CNT to 255 */
+        if (bIsSendCmd == FALSE)
+        {
+            sdh->CTL = reg | (18ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            bIsSendCmd = TRUE;
+        }
+        else
+        {
+            sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while (!pSD->DataReadyFlag)
+        {
+            if (pSD->DataReadyFlag)
+            {
+                break;
+            }
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk)      /* check CRC7 */
+        {
+            return SDH_CRC7_ERROR;
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk)     /* check CRC16 */
+        {
+            return SDH_CRC16_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255ul;
+    if (loop != 0ul)
+    {
+        pSD->DataReadyFlag = (uint8_t)FALSE;
+        reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);
+        reg = reg & (~SDH_CTL_BLKCNT_Msk);
+        reg |= (loop << 16);    /* setup SDCR_BLKCNT */
+
+        if (bIsSendCmd == FALSE)
+        {
+            sdh->CTL = reg | (18ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            bIsSendCmd = TRUE;
+        }
+        else
+        {
+            sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while (!pSD->DataReadyFlag)
+        {
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk)      /* check CRC7 */
+        {
+            return SDH_CRC7_ERROR;
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk)     /* check CRC16 */
+        {
+            return SDH_CRC16_ERROR;
+        }
+    }
+
+    if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul))      /* stop command */
+    {
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+    {
+    }
+
+    return Successful;
+}
+
+
+/**
+ *  @brief  This function use to write data to SD card.
+ *
+ *  @param[in]    sdh           Select SDH0 or SDH1.
+ *  @param[in]    pu8BufAddr    The buffer to send the data to SD card.
+ *  @param[in]    u32StartSec   The start write sector address.
+ *  @param[in]    u32SecCount   The the write sector number of data.
+ *
+ *  @return   \ref SDH_SELECT_ERROR : u32SecCount is zero. \n
+ *            \ref SDH_NO_SD_CARD : SD card be removed. \n
+ *            \ref SDH_CRC_ERROR : CRC error happen. \n
+ *            \ref SDH_CRC7_ERROR : CRC7 error happen. \n
+ *            \ref Successful : Write data to SD card success.
+ */
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile bIsSendCmd = FALSE;
+    uint32_t volatile reg;
+    uint32_t volatile i, loop, status;
+
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0)
+    {
+        pSD = &SD0;
+    }
+    else
+    {
+        pSD = &SD1;
+    }
+
+    if (u32SecCount == 0ul)
+    {
+        return SDH_SELECT_ERROR;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful)
+    {
+        return status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */
+    sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+    if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        sdh->CMDARG = u32StartSec;
+    }
+    else
+    {
+        sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE;  /* set start address for SD CMD */
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+    loop = u32SecCount / 255ul;   /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */
+    for (i = 0ul; i < loop; i++)
+    {
+        pSD->DataReadyFlag = (uint8_t)FALSE;
+        reg = sdh->CTL & 0xff00c080;
+        reg = reg | 0xff0000ul;   /* set BLK_CNT to 0xFF=255 */
+        if (!bIsSendCmd)
+        {
+            sdh->CTL = reg | (25ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            bIsSendCmd = TRUE;
+        }
+        else
+        {
+            sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while (!pSD->DataReadyFlag)
+        {
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
+        {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255ul;
+    if (loop != 0ul)
+    {
+        pSD->DataReadyFlag = (uint8_t)FALSE;
+        reg = (sdh->CTL & 0xff00c080) | (loop << 16);
+        if (!bIsSendCmd)
+        {
+            sdh->CTL = reg | (25ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            bIsSendCmd = TRUE;
+        }
+        else
+        {
+            sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while (!pSD->DataReadyFlag)
+        {
+            if (pSD->IsCardInsert == FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
+        {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+    }
+    sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+
+    if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul))      /* stop command */
+    {
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
+    {
+    }
+
+    return Successful;
+}
+
+/*@}*/ /* end of group N9H30_SD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SD_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+
+
+
+
+
+
+
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_spi.c

@@ -0,0 +1,336 @@
+/**************************************************************************//**
+* @file     spi.c
+* @brief    N9H30 SPI driver source file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+/* Header files */
+#include <stdio.h>
+#include <string.h>
+
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_spi.h"
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SPI_Driver SPI Driver
+  @{
+*/
+
+/** @addtogroup N9H30_SPI_EXPORTED_CONSTANTS SPI Exported Constants
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+#define spi_out(dev, byte, addr)        outpw((dev)->base + addr, byte)
+#define spi_in(dev, addr)               inpw((dev)->base + addr)
+
+typedef struct
+{
+    uint32_t base;      /* spi bus number */
+    uint8_t openflag;
+    uint8_t intflag;
+} spi_dev;
+
+/// @endcond HIDDEN_SYMBOLS
+/*@}*/ /* end of group N9H30_EMAC_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+static spi_dev spi_device[SPI_NUMBER];
+
+#if 0
+/**
+  * @brief  SPI-0 Interrupt handler
+  * @param None
+  * @return None
+  */
+static void spi0ISR(void)
+{
+    // clear interrupt flag
+    outpw(REG_SPI0_CNTRL, spi_in((spi_dev *)((uint32_t)&spi_device[0]), CNTRL) | 0x1 << 16);
+    spi_device[0].intflag = 1;
+}
+
+/**
+  * @brief  SPI-1 Interrupt handler
+  * @param None
+  * @return None
+  */
+static void spi1ISR(void)
+{
+    // clear interrupt flag
+    outpw(REG_SPI1_CNTRL, spi_in((spi_dev *)((uint32_t)&spi_device[1]), CNTRL) | 0x1 << 16);
+    spi_device[1].intflag = 1;
+}
+#endif
+
+/**
+  * @brief  Set SPI divider
+  * @param[in] dev pointer to spi interface structure
+  * @param[in] speed desire spi speed
+  * @return speed set actually
+  */
+static uint32_t spiSetSpeed(spi_dev *dev, uint32_t speed)
+{
+    uint16_t div = (uint16_t)(SPI_INPUT_CLOCK / (2 * speed)) - 1;
+
+    spi_out(dev, div, DIVIDER);
+    return (SPI_INPUT_CLOCK / (2 * (div + 1)));
+}
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/**
+  * @brief Initialize spi interface and install interrupt callback function
+  * @return always 0.
+  * @retval 0 Success.
+  */
+int32_t  spiInit(int32_t fd)
+{
+#if 0
+    if (fd == 0)
+    {
+        sysInstallISR(IRQ_LEVEL_1, SPI0_IRQn, (PVOID)spi0ISR);
+        sysEnableInterrupt(SPI0_IRQn);
+        memset((void *)&spi_device[0], 0, sizeof(spi_dev));
+    }
+    else
+    {
+        sysInstallISR(IRQ_LEVEL_1, SPI1_IRQn, (PVOID)spi1ISR);
+        sysEnableInterrupt(SPI1_IRQn);
+        memset((void *)&spi_device[1], 0, sizeof(spi_dev));
+    }
+
+    sysSetLocalInterrupt(ENABLE_IRQ);
+#endif
+
+    return (0);
+}
+
+/**
+  * @brief Support some spi driver commands for application.
+  * @param[in] fd is interface number.
+  * @param[in] cmd is command.
+  * @param[in] arg0 is the first argument of command.
+  * @param[in] arg1 is the second argument of command.
+  * @return command status.
+  * @retval 0 Success otherwise fail. Fail value could be
+  *                                    - \ref SPI_ERR_NODEV
+  *                                    - \ref SPI_ERR_IO
+  *                                    - \ref SPI_ERR_ARG
+  */
+int32_t spiIoctl(int32_t fd, uint32_t cmd, uint32_t arg0, uint32_t arg1)
+{
+    spi_dev *dev;
+
+    if (fd != 0 && fd != 1)
+        return (SPI_ERR_NODEV);
+
+    dev = (spi_dev *)((uint32_t)&spi_device[fd]);
+    if (dev->openflag == 0)
+        return (SPI_ERR_IO);
+
+    switch (cmd)
+    {
+    case SPI_IOC_TRIGGER:
+        dev->intflag = 0;
+        spi_out(dev, spi_in(dev, CNTRL) | 0x1, CNTRL);
+        break;
+
+#if 0
+    case SPI_IOC_SET_INTERRUPT:
+        if (arg0 == SPI_ENABLE_INTERRUPT)
+            spi_out(dev, spi_in(dev, CNTRL) | (0x1 << 17), CNTRL);
+        else
+            spi_out(dev, spi_in(dev, CNTRL) & ~(0x1 << 17), CNTRL);
+        break;
+#endif
+
+    case SPI_IOC_SET_SPEED:
+        return spiSetSpeed(dev, (uint32_t)arg0);
+
+    case SPI_IOC_SET_DUAL_QUAD_MODE:
+        if (arg0 == SPI_DISABLE_DUAL_QUAD)
+        {
+            spi_out(dev, (spi_in(dev, CNTRL) & ~(0x3 << 21)), CNTRL);
+            break;
+        }
+
+        if (arg0 == SPI_DUAL_MODE)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~(0x3 << 21)) | (0x1 << 22), CNTRL);
+        else
+            spi_out(dev, (spi_in(dev, CNTRL) & ~(0x3 << 21)) | (0x1 << 21), CNTRL);
+        break;
+
+    case SPI_IOC_SET_DUAL_QUAD_DIR:
+        if (arg0 == SPI_DUAL_QUAD_INPUT)
+            spi_out(dev, spi_in(dev, CNTRL) & ~(0x1 << 20), CNTRL);
+        else
+            spi_out(dev, spi_in(dev, CNTRL) | (0x1 << 20), CNTRL);
+        break;
+
+    case SPI_IOC_SET_LSB_MSB:
+        if (arg0 == SPI_MSB)
+            spi_out(dev, spi_in(dev, CNTRL) & ~(0x1 << 10), CNTRL);
+        else
+            spi_out(dev, spi_in(dev, CNTRL) | (0x1 << 10), CNTRL);
+        break;
+
+    case SPI_IOC_SET_TX_NUM:
+        if (arg0 < 4)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~(0x3 << 8)) | (arg0 << 8), CNTRL);
+        else
+            return SPI_ERR_ARG;
+        break;
+
+    case SPI_IOC_SET_TX_BITLEN:
+        if (arg0 < 32)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~(0x1f << 3)) | (arg0 << 3), CNTRL);
+        else
+            return SPI_ERR_ARG;
+        break;
+
+    case SPI_IOC_SET_MODE:
+        if (arg0 > SPI_MODE_3)
+            return SPI_ERR_ARG;
+
+        if (arg0 == SPI_MODE_0)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~((0x3 << 1) | (1UL << 31))) | (1 << 2), CNTRL);
+        else if (arg0 == SPI_MODE_1)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~((0x3 << 1) | (1UL << 31))) | (1 << 1), CNTRL);
+        else if (arg0 == SPI_MODE_2)
+            spi_out(dev, (spi_in(dev, CNTRL) & ~((0x3 << 1) | (1UL << 31))) | ((1UL << 31) | (1 << 2)), CNTRL);
+        else
+            spi_out(dev, (spi_in(dev, CNTRL) & ~((0x3 << 1) | (1UL << 31))) | ((1UL << 31) | (1 << 1)), CNTRL);
+        break;
+
+    case SPI_IOC_ENABLE_SS:
+        if (arg0 == SPI_SS_SS0)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x3)) | 0x1, SSR);
+        else if (arg0 == SPI_SS_SS1)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x3)) | 0x2, SSR);
+        else if (arg0 == SPI_SS_BOTH)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x3)) | 0x3, SSR);
+        else
+            return SPI_ERR_ARG;
+        break;
+
+    case SPI_IOC_DISABLE_SS:
+        if (arg0 == SPI_SS_SS0)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x1)), SSR);
+        else if (arg0 == SPI_SS_SS1)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x2)), SSR);
+        else if (arg0 == SPI_SS_BOTH)
+            spi_out(dev, (spi_in(dev, SSR) & ~(0x3)), SSR);
+        else
+            return SPI_ERR_ARG;
+        break;
+
+    case SPI_IOC_SET_AUTOSS:
+        if (arg0 == SPI_DISABLE_AUTOSS)
+            spi_out(dev, spi_in(dev, SSR) & ~(0x1 << 3), SSR);
+        else
+            spi_out(dev, spi_in(dev, SSR) | (0x1 << 3), SSR);
+        break;
+
+    case SPI_IOC_SET_SS_ACTIVE_LEVEL:
+        if (arg0 == SPI_SS_ACTIVE_LOW)
+            spi_out(dev, spi_in(dev, SSR) & ~(0x1 << 2), SSR);
+        else
+            spi_out(dev, spi_in(dev, SSR) | (0x1 << 2), SSR);
+    default:
+        break;
+    }
+
+    return 0;
+}
+
+/**
+  * @brief Open spi interface and initialize some variables
+  * @param[in] fd is interface number.
+  * @return always 0
+  * @retval 0 success.
+  */
+int spiOpen(int32_t fd)
+{
+    spi_dev *dev;
+
+    if ((uint32_t)fd >= SPI_NUMBER)
+        return SPI_ERR_NODEV;
+
+    dev = (spi_dev *)((uint32_t)&spi_device[fd]);
+
+    if (dev->openflag != 0)         /* a card slot can open only once */
+        return (SPI_ERR_BUSY);
+
+    memset(dev, 0, sizeof(spi_dev));
+    dev->base = ((uint32_t)fd) ? SPI1_BA : SPI0_BA;
+    dev->openflag = 1;
+    dev->intflag = 0;
+
+    return 0;
+}
+
+/**
+  * @brief Get busy status of spi interface
+  * @param[in] fd is interface number.
+  * @return busy or not
+  * @retval 0 not busy.
+  * @retval 1 busy.
+  */
+uint8_t spiGetBusyStatus(int32_t fd)
+{
+    spi_dev *dev;
+
+    dev = (spi_dev *)((uint32_t)&spi_device[fd]);
+
+    if (spi_in(dev, CNTRL) & (0x1 << 17))
+        return (!dev->intflag);
+    else
+        return ((spi_in(dev, CNTRL) & 0x1) == 0x1 ? 1 : 0);
+}
+
+/**
+  * @brief Read data form spi interface
+  * @param[in] fd is interface number.
+  * @param[in] buff_id is buffer number. If transfer number is 4, application needs read 4 times (buff_id is from 0 to 3) from buffer.
+  * @return data
+  */
+uint32_t spiRead(int32_t fd, uint8_t buff_id)
+{
+    spi_dev *dev;
+
+    dev = (spi_dev *)((uint32_t)&spi_device[fd]);
+    return spi_in(dev, (RX0 + 4 * buff_id));
+}
+
+/**
+  * @brief Write data to spi interface
+  * @param[in] fd is interface number.
+  * @param[in] buff_id is buffer number. If transfer number is 4, application needs write 4 times (buff_id is from 0 to 3) to buffer.
+  * @param[in] data is data to be written.
+  * @return none
+  */
+void spiWrite(int32_t fd, uint8_t buff_id, uint32_t data)
+{
+    spi_dev *dev;
+
+    dev = (spi_dev *)((uint32_t)&spi_device[fd]);
+    spi_out(dev, data, (TX0 + 4 * buff_id));
+}
+
+/*@}*/ /* end of group N9H30_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_SPI_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_sys.c

@@ -0,0 +1,675 @@
+/**************************************************************************//**
+* @file     sys.c
+* @brief    N9H30 SYS driver source file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "N9H30.h"
+#include "nu_sys.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+#define SYS_MIN_INT_SOURCE       1
+#define SYS_MAX_INT_SOURCE       62
+#define SYS_NUM_OF_AICREG        16
+
+/* Global variables */
+BOOL volatile _sys_bIsAICInitial = FALSE;
+
+/* declaration the function prototype */
+extern void SYS_Interrupt_Shell(void);
+
+/* Interrupt Handler Table */
+//typedef void (*sys_pvFunPtr)();   /* function pointer */
+sys_pvFunPtr sysIrqHandlerTable[] = { 0,                /* 0 */
+                                      SYS_Interrupt_Shell,   /* 1 */
+                                      SYS_Interrupt_Shell,   /* 2 */
+                                      SYS_Interrupt_Shell,   /* 3 */
+                                      SYS_Interrupt_Shell,   /* 4 */
+                                      SYS_Interrupt_Shell,   /* 5 */
+                                      SYS_Interrupt_Shell,   /* 6 */
+                                      SYS_Interrupt_Shell,   /* 7 */
+                                      SYS_Interrupt_Shell,   /* 8 */
+                                      SYS_Interrupt_Shell,   /* 9 */
+                                      SYS_Interrupt_Shell,   /* 10 */
+                                      SYS_Interrupt_Shell,   /* 11 */
+                                      SYS_Interrupt_Shell,   /* 12 */
+                                      SYS_Interrupt_Shell,   /* 13 */
+                                      SYS_Interrupt_Shell,   /* 14 */
+                                      SYS_Interrupt_Shell,   /* 15 */
+                                      SYS_Interrupt_Shell,   /* 16 */
+                                      SYS_Interrupt_Shell,   /* 17 */
+                                      SYS_Interrupt_Shell,   /* 18 */
+                                      SYS_Interrupt_Shell,   /* 19 */
+                                      SYS_Interrupt_Shell,   /* 20 */
+                                      SYS_Interrupt_Shell,   /* 21 */
+                                      SYS_Interrupt_Shell,   /* 22 */
+                                      SYS_Interrupt_Shell,   /* 23 */
+                                      SYS_Interrupt_Shell,   /* 24 */
+                                      SYS_Interrupt_Shell,   /* 25 */
+                                      SYS_Interrupt_Shell,   /* 26 */
+                                      SYS_Interrupt_Shell,   /* 27 */
+                                      SYS_Interrupt_Shell,   /* 28 */
+                                      SYS_Interrupt_Shell,   /* 29 */
+                                      SYS_Interrupt_Shell,   /* 30 */
+                                      SYS_Interrupt_Shell,   /* 31 */
+                                      SYS_Interrupt_Shell,   /* 32 */
+                                      SYS_Interrupt_Shell,   /* 33 */
+                                      SYS_Interrupt_Shell,   /* 34 */
+                                      SYS_Interrupt_Shell,   /* 35 */
+                                      SYS_Interrupt_Shell,   /* 36 */
+                                      SYS_Interrupt_Shell,   /* 37 */
+                                      SYS_Interrupt_Shell,   /* 38 */
+                                      SYS_Interrupt_Shell,   /* 39 */
+                                      SYS_Interrupt_Shell,   /* 40 */
+                                      SYS_Interrupt_Shell,   /* 41 */
+                                      SYS_Interrupt_Shell,   /* 42 */
+                                      SYS_Interrupt_Shell,   /* 43 */
+                                      SYS_Interrupt_Shell,   /* 44 */
+                                      SYS_Interrupt_Shell,   /* 45 */
+                                      SYS_Interrupt_Shell,   /* 46 */
+                                      SYS_Interrupt_Shell,   /* 47 */
+                                      SYS_Interrupt_Shell,   /* 48 */
+                                      SYS_Interrupt_Shell,   /* 49 */
+                                      SYS_Interrupt_Shell,   /* 50 */
+                                      SYS_Interrupt_Shell,   /* 51 */
+                                      SYS_Interrupt_Shell,   /* 52 */
+                                      SYS_Interrupt_Shell,   /* 53 */
+                                      SYS_Interrupt_Shell,   /* 54 */
+                                      SYS_Interrupt_Shell,   /* 55 */
+                                      SYS_Interrupt_Shell,   /* 56 */
+                                      SYS_Interrupt_Shell,   /* 57 */
+                                      SYS_Interrupt_Shell,   /* 58 */
+                                      SYS_Interrupt_Shell,   /* 59 */
+                                      SYS_Interrupt_Shell,   /* 60 */
+                                      SYS_Interrupt_Shell    /* 61 */
+                                    };
+
+sys_pvFunPtr sysFiqHandlerTable[] = { 0,
+                                      SYS_Interrupt_Shell,   /* 1 */
+                                      SYS_Interrupt_Shell,   /* 2 */
+                                      SYS_Interrupt_Shell,   /* 3 */
+                                      SYS_Interrupt_Shell,   /* 4 */
+                                      SYS_Interrupt_Shell,   /* 5 */
+                                      SYS_Interrupt_Shell,   /* 6 */
+                                      SYS_Interrupt_Shell,   /* 7 */
+                                      SYS_Interrupt_Shell,   /* 8 */
+                                      SYS_Interrupt_Shell,   /* 9 */
+                                      SYS_Interrupt_Shell,   /* 10 */
+                                      SYS_Interrupt_Shell,   /* 11 */
+                                      SYS_Interrupt_Shell,   /* 12 */
+                                      SYS_Interrupt_Shell,   /* 13 */
+                                      SYS_Interrupt_Shell,   /* 14 */
+                                      SYS_Interrupt_Shell,   /* 15 */
+                                      SYS_Interrupt_Shell,   /* 16 */
+                                      SYS_Interrupt_Shell,   /* 17 */
+                                      SYS_Interrupt_Shell,   /* 18 */
+                                      SYS_Interrupt_Shell,   /* 19 */
+                                      SYS_Interrupt_Shell,   /* 20 */
+                                      SYS_Interrupt_Shell,   /* 21 */
+                                      SYS_Interrupt_Shell,   /* 22 */
+                                      SYS_Interrupt_Shell,   /* 23 */
+                                      SYS_Interrupt_Shell,   /* 24 */
+                                      SYS_Interrupt_Shell,   /* 25 */
+                                      SYS_Interrupt_Shell,   /* 26 */
+                                      SYS_Interrupt_Shell,   /* 27 */
+                                      SYS_Interrupt_Shell,   /* 28 */
+                                      SYS_Interrupt_Shell,   /* 29 */
+                                      SYS_Interrupt_Shell,   /* 30 */
+                                      SYS_Interrupt_Shell,   /* 31 */
+                                      SYS_Interrupt_Shell,   /* 32 */
+                                      SYS_Interrupt_Shell,   /* 33 */
+                                      SYS_Interrupt_Shell,   /* 34 */
+                                      SYS_Interrupt_Shell,   /* 35 */
+                                      SYS_Interrupt_Shell,   /* 36 */
+                                      SYS_Interrupt_Shell,   /* 37 */
+                                      SYS_Interrupt_Shell,   /* 38 */
+                                      SYS_Interrupt_Shell,   /* 39 */
+                                      SYS_Interrupt_Shell,   /* 40 */
+                                      SYS_Interrupt_Shell,   /* 41 */
+                                      SYS_Interrupt_Shell,   /* 42 */
+                                      SYS_Interrupt_Shell,   /* 43 */
+                                      SYS_Interrupt_Shell,   /* 44 */
+                                      SYS_Interrupt_Shell,   /* 45 */
+                                      SYS_Interrupt_Shell,   /* 46 */
+                                      SYS_Interrupt_Shell,   /* 47 */
+                                      SYS_Interrupt_Shell,   /* 48 */
+                                      SYS_Interrupt_Shell,   /* 49 */
+                                      SYS_Interrupt_Shell,   /* 50 */
+                                      SYS_Interrupt_Shell,   /* 51 */
+                                      SYS_Interrupt_Shell,   /* 52 */
+                                      SYS_Interrupt_Shell,   /* 53 */
+                                      SYS_Interrupt_Shell,   /* 54 */
+                                      SYS_Interrupt_Shell,   /* 55 */
+                                      SYS_Interrupt_Shell,   /* 56 */
+                                      SYS_Interrupt_Shell,   /* 57 */
+                                      SYS_Interrupt_Shell,   /* 58 */
+                                      SYS_Interrupt_Shell,   /* 59 */
+                                      SYS_Interrupt_Shell,   /* 60 */
+                                      SYS_Interrupt_Shell    /* 61 */
+                                    };
+
+/* Interrupt Handler */
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+    static void __attribute__((interrupt("IRQ"))) sysIrqHandler(void)
+#else
+    __irq void sysIrqHandler()
+#endif
+{
+    UINT32 volatile _mIPER, _mISNR;
+
+    _mIPER = (inpw(REG_AIC_IPER) >> 2) & 0x3f;
+    _mISNR = inpw(REG_AIC_ISNR);
+    if (_mIPER != 0)
+    {
+        if (_mISNR != 0)
+            (*sysIrqHandlerTable[_mIPER])();
+        outpw(REG_AIC_EOSCR, 1);
+    }
+}
+
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+    static void __attribute__((interrupt("FIQ"))) sysFiqHandler(void)
+#else
+    __irq void sysFiqHandler()
+#endif
+{
+    UINT32 volatile _mIPER, _mISNR;
+
+    _mIPER = (inpw(REG_AIC_IPER) >> 2) & 0x3f;
+    _mISNR = inpw(REG_AIC_ISNR);
+    if (_mIPER != 0)
+    {
+        if (_mISNR != 0)
+            (*sysFiqHandlerTable[_mIPER])();
+        outpw(REG_AIC_EOSCR, 1);
+    }
+}
+
+void SYS_Interrupt_Shell()
+{
+    //sysprintf("ISR not found! ISNR=%d\n", inpw(REG_AIC_ISNR));
+}
+
+void sysInitializeAIC()
+{
+    *(unsigned int volatile *)0x38 = (unsigned int)sysIrqHandler;
+
+    *(unsigned int volatile *)0x3C = (unsigned int)sysFiqHandler;
+}
+/// @endcond HIDDEN_SYMBOLS
+
+
+/* Interrupt library functions */
+/**
+ *  @brief  system AIC - disable interrupt
+ *
+ *  @param[in]  eIntNo  Select interrupt source.  \ref IRQn_Type
+ *
+ *  @return   0
+ */
+INT32 sysDisableInterrupt(IRQn_Type eIntNo)
+{
+    if ((eIntNo > SYS_MAX_INT_SOURCE) || (eIntNo < SYS_MIN_INT_SOURCE))
+        return 1;
+
+    if (eIntNo < 32)
+        outpw(REG_AIC_MDCR, (1 << eIntNo));
+    else
+        outpw(REG_AIC_MDCRH, (1 << (eIntNo - 32)));
+
+    return 0;
+}
+
+
+/**
+ *  @brief  system AIC - enable interrupt
+ *
+ *  @param[in]  eIntNo  Select interrupt source.  \ref IRQn_Type
+ *
+ *  @return   0
+ */
+INT32 sysEnableInterrupt(IRQn_Type eIntNo)
+{
+    if ((eIntNo > SYS_MAX_INT_SOURCE) || (eIntNo < SYS_MIN_INT_SOURCE))
+        return 1;
+
+    if (eIntNo < 32)
+        outpw(REG_AIC_MECR, (1 << eIntNo));
+    else
+        outpw(REG_AIC_MECRH, (1 << (eIntNo - 32)));
+
+    return 0;
+}
+
+
+/**
+ *  @brief  system AIC - install exception handler
+ *
+ *  @param[in]  nExceptType  exception type. ( \ref SYS_SWI / \ref SYS_D_ABORT / \ref SYS_I_ABORT / \ref SYS_UNDEFINE)
+ *  @param[in]  pvNewHandler  own exception handler
+ *
+ *  @return   old handler
+ */
+PVOID sysInstallExceptionHandler(INT32 nExceptType, PVOID pvNewHandler)
+{
+    PVOID _mOldVect = NULL;
+
+    switch (nExceptType)
+    {
+    case SYS_SWI:
+        _mOldVect = *(PVOID volatile *)0x28;
+        *(PVOID volatile *)0x28 = pvNewHandler;
+        break;
+
+    case SYS_D_ABORT:
+        _mOldVect = *(PVOID volatile *)0x30;
+        *(PVOID volatile *)0x30 = pvNewHandler;
+        break;
+
+    case SYS_I_ABORT:
+        _mOldVect = *(PVOID volatile *)0x2C;
+        *(PVOID volatile *)0x2C = pvNewHandler;
+        break;
+
+    case SYS_UNDEFINE:
+        _mOldVect = *(PVOID volatile *)0x24;
+        *(PVOID volatile *)0x24 = pvNewHandler;
+        break;
+
+    default:
+        ;
+    }
+    return _mOldVect;
+}
+
+/**
+ *  @brief  system AIC - install FIQ handler
+ *
+ *  @param[in]  pvNewISR  own fiq handler
+ *
+ *  @return   old handler
+ */
+PVOID sysInstallFiqHandler(PVOID pvNewISR)
+{
+    PVOID _mOldVect;
+
+    _mOldVect = *(PVOID volatile *)0x3C;
+    *(PVOID volatile *)0x3C = pvNewISR;
+    return _mOldVect;
+}
+
+/**
+ *  @brief  system AIC - install IRQ handler
+ *
+ *  @param[in]  pvNewISR  own irq handler
+ *
+ *  @return   old handler
+ */
+PVOID sysInstallIrqHandler(PVOID pvNewISR)
+{
+    PVOID _mOldVect;
+
+    _mOldVect = *(PVOID volatile *)0x38;
+    *(PVOID volatile *)0x38 = pvNewISR;
+    return _mOldVect;
+}
+
+
+/**
+ *  @brief  system AIC - install Own IRQ service routine
+ *
+ *  @param[in]  nIntTypeLevel   Interrupt Level. ( \ref FIQ_LEVEL_0 / \ref IRQ_LEVEL_1 / \ref IRQ_LEVEL_2 / \ref IRQ_LEVEL_3 /
+ *                                                 \ref IRQ_LEVEL_4 / \ref IRQ_LEVEL_5 / \ref IRQ_LEVEL_6 / \ref IRQ_LEVEL_7 )
+ *  @param[in]  eIntNo  Interrupt number. \ref IRQn_Type
+ *  @param[in]  pvNewISR  own irq handler
+ *
+ *  @return   old handler
+ */
+PVOID sysInstallISR(INT32 nIntTypeLevel, IRQn_Type eIntNo, PVOID pvNewISR)
+{
+    PVOID   _mOldVect;
+    UINT32  _mRegAddr/*, _mRegValue*/;
+    INT     shift;
+
+    if (!_sys_bIsAICInitial)
+    {
+        sysInitializeAIC();
+        _sys_bIsAICInitial = TRUE;
+    }
+
+    _mRegAddr = REG_AIC_SCR1 + ((eIntNo / 4) * 4);
+    shift = (eIntNo % 4) * 8;
+    nIntTypeLevel &= 0xff;
+    outpw(_mRegAddr, (inpw(_mRegAddr) & ~(0x07 << shift)) | (nIntTypeLevel << shift));
+
+    if ((nIntTypeLevel & 0x7) == FIQ_LEVEL_0)
+    {
+        _mOldVect = (PVOID) sysFiqHandlerTable[eIntNo];
+        sysFiqHandlerTable[eIntNo] = (sys_pvFunPtr)pvNewISR;
+    }
+    else
+    {
+        _mOldVect = (PVOID) sysIrqHandlerTable[eIntNo];
+        sysIrqHandlerTable[eIntNo] = (sys_pvFunPtr)pvNewISR;
+    }
+    return _mOldVect;
+}
+
+
+INT32 sysSetGlobalInterrupt(INT32 nIntState)
+{
+    switch (nIntState)
+    {
+    case ENABLE_ALL_INTERRUPTS:
+        outpw(REG_AIC_MECR, 0xFFFFFFFF);
+        outpw(REG_AIC_MECRH, 0xFFFFFFFF);
+        break;
+
+    case DISABLE_ALL_INTERRUPTS:
+        outpw(REG_AIC_MDCR, 0xFFFFFFFF);
+        outpw(REG_AIC_MDCRH, 0xFFFFFFFF);
+        break;
+
+    default:
+        ;
+    }
+    return 0;
+}
+
+
+/**
+ *  @brief  system AIC - Change interrupt level
+ *
+ *  @param[in]  eIntNo  Interrupt number. \ref IRQn_Type
+ *  @param[in]  uIntLevel   Interrupt Level. ( \ref FIQ_LEVEL_0 / \ref IRQ_LEVEL_1 / \ref IRQ_LEVEL_2 / \ref IRQ_LEVEL_3 /
+ *                                             \ref IRQ_LEVEL_4 / \ref IRQ_LEVEL_5 / \ref IRQ_LEVEL_6 / \ref IRQ_LEVEL_7 )
+ *
+ *  @return   0
+ */
+INT32 sysSetInterruptPriorityLevel(IRQn_Type eIntNo, UINT32 uIntLevel)
+{
+    UINT32  _mRegAddr;
+    INT     shift;
+
+    if ((eIntNo > SYS_MAX_INT_SOURCE) || (eIntNo < SYS_MIN_INT_SOURCE))
+        return 1;
+
+    _mRegAddr = REG_AIC_SCR1 + ((eIntNo / 4) * 4);
+    shift = (eIntNo % 4) * 8;
+    uIntLevel &= 0x7;
+    outpw(_mRegAddr, (inpw(_mRegAddr) & ~(0x07 << shift)) | (uIntLevel << shift));
+
+    return 0;
+}
+
+
+INT32 sysSetInterruptType(IRQn_Type eIntNo, UINT32 uIntSourceType)
+{
+    UINT32 _mRegAddr;
+    INT     shift;
+
+    if ((eIntNo > SYS_MAX_INT_SOURCE) || (eIntNo < SYS_MIN_INT_SOURCE))
+        return 1;
+
+    _mRegAddr = REG_AIC_SCR1 + ((eIntNo / 4) * 4);
+    shift = (eIntNo % 4) * 8;
+    uIntSourceType &= 0xC0;
+    outpw(_mRegAddr, (inpw(_mRegAddr) & ~(0xC0 << shift)) | (uIntSourceType << shift));
+
+    return 0;
+}
+
+
+/**
+ *  @brief  system AIC - Set CP15 Interrupt Type
+ *
+ *  @param[in]  nIntState   Interrupt state. ( \ref ENABLE_IRQ / \ref ENABLE_FIQ / \ref ENABLE_FIQ_IRQ /
+ *                                             \ref DISABLE_IRQ / \ref DISABLE_FIQ / \ref DISABLE_FIQ_IRQ)
+ *
+ *  @return   0
+ */
+INT32 sysSetLocalInterrupt(INT32 nIntState)
+{
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+
+# else
+    INT32 temp;
+#endif
+
+    switch (nIntState)
+    {
+    case ENABLE_IRQ:
+    case ENABLE_FIQ:
+    case ENABLE_FIQ_IRQ:
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+        asm
+        (
+            "mrs    r0, CPSR  \n"
+            "bic    r0, r0, #0x80  \n"
+            "msr    CPSR_c, r0  \n"
+        );
+#else
+        __asm
+        {
+            MRS    temp, CPSR
+            AND    temp, temp, nIntState
+            MSR    CPSR_c, temp
+        }
+#endif
+        break;
+    case DISABLE_IRQ:
+    case DISABLE_FIQ:
+    case DISABLE_FIQ_IRQ:
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+        asm
+        (
+            "MRS    r0, CPSR  \n"
+            "ORR    r0, r0, #0x80  \n"
+            "MSR    CPSR_c, r0  \n"
+        );
+#else
+        __asm
+        {
+            MRS    temp, CPSR
+            ORR    temp, temp, nIntState
+            MSR    CPSR_c, temp
+        }
+#endif
+        break;
+
+    default:
+        ;
+    }
+    return 0;
+}
+
+UINT32  sysGetInterruptEnableStatus(void)
+{
+    return (inpw(REG_AIC_IMR));
+}
+
+
+UINT32  sysGetInterruptEnableStatusH(void)
+{
+    return (inpw(REG_AIC_IMRH));
+}
+
+/// @cond HIDDEN_SYMBOLS
+BOOL sysGetIBitState()
+{
+    INT32 temp;
+
+#if defined ( __GNUC__ ) && !(__CC_ARM)
+    asm
+    (
+        "MRS %0, CPSR   \n"
+        :"=r"(temp) : :
+    );
+#else
+    __asm
+    {
+        MRS temp, CPSR
+    }
+#endif
+
+    if (temp & 0x80)
+        return FALSE;
+    else
+        return TRUE;
+}
+
+INT32 sysGetPLL(UINT32 reg)
+{
+    UINT32 N, M, P;
+
+    N = ((inpw(reg) & 0x007F) >> 0) + 1;
+    M = ((inpw(reg) & 0x1F80) >> 7) + 1;
+    P = ((inpw(reg) & 0xE000) >> 13) + 1;
+
+    return (12 * N / (M * P)); /* 12MHz HXT */
+}
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ *  @brief  system Timer - install WDT interrupt handler
+ *
+ *  @param[in]  clk   clock source. \ref CLK_Type
+ *
+ *  @return   MHz
+ */
+UINT32 sysGetClock(CLK_Type clk)
+{
+    UINT32 src, divS, divN, reg, div;
+
+    switch (clk)
+    {
+    case SYS_UPLL:
+        return sysGetPLL(REG_CLK_UPLLCON);
+
+    case SYS_APLL:
+        return sysGetPLL(REG_CLK_APLLCON);
+
+    case SYS_SYSTEM:
+    {
+        reg = inpw(REG_CLK_DIVCTL0);
+        switch (reg & 0x18)
+        {
+        case 0x0:
+            src = 12;   /* HXT */
+            break;
+        case 0x10:
+            src = sysGetPLL(REG_CLK_APLLCON);
+            break;
+        case 0x18:
+            src = sysGetPLL(REG_CLK_UPLLCON);
+            break;
+        default:
+            return 0;
+        }
+        divS = (reg & 0x7) + 1;
+        divN = ((reg & 0xf00) >> 8) + 1;
+        return (src / divS / divN);
+    }
+
+    case SYS_HCLK1:
+    {
+        reg = inpw(REG_CLK_DIVCTL0);
+        switch (reg & 0x18)
+        {
+        case 0x0:
+            src = 12;   /* HXT */
+            break;
+        case 0x10:
+            src = sysGetPLL(REG_CLK_APLLCON);
+            break;
+        case 0x18:
+            src = sysGetPLL(REG_CLK_UPLLCON);
+            break;
+        default:
+            return 0;
+        }
+        divS = (reg & 0x7) + 1;
+        divN = ((reg & 0xf00) >> 8) + 1;
+        return (src / divS / divN / 2);
+    }
+
+    case SYS_HCLK234:
+    {
+        reg = inpw(REG_CLK_DIVCTL0);
+        switch (reg & 0x18)
+        {
+        case 0x0:
+            src = 12;   /* HXT */
+            break;
+        case 0x10:
+            src = sysGetPLL(REG_CLK_APLLCON);
+            break;
+        case 0x18:
+            src = sysGetPLL(REG_CLK_UPLLCON);
+            break;
+        default:
+            return 0;
+        }
+        divS = (reg & 0x7) + 1;
+        divN = ((reg & 0xf00) >> 8) + 1;
+        div = ((reg & 0xf00000) >> 20) + 1;
+        return (src / divS / divN / 2 / div);
+    }
+
+    case SYS_PCLK:
+    {
+        reg = inpw(REG_CLK_DIVCTL0);
+        switch (reg & 0x18)
+        {
+        case 0x0:
+            src = 12;   /* HXT */
+            break;
+        case 0x10:
+            src = sysGetPLL(REG_CLK_APLLCON);
+            break;
+        case 0x18:
+            src = sysGetPLL(REG_CLK_UPLLCON);
+            break;
+        default:
+            return 0;
+        }
+        divS = (reg & 0x7) + 1;
+        divN = ((reg & 0xf00) >> 8) + 1;
+        div = ((reg & 0xf000000) >> 24) + 1;
+        return (src / divS / divN / 2 / div);
+    }
+    case SYS_CPU:
+    {
+        reg = inpw(REG_CLK_DIVCTL0);
+        switch (reg & 0x18)
+        {
+        case 0x0:
+            src = 12;   /* HXT */
+            break;
+        case 0x10:
+            src = sysGetPLL(REG_CLK_APLLCON);
+            break;
+        case 0x18:
+            src = sysGetPLL(REG_CLK_UPLLCON);
+            break;
+        default:
+            return 0;
+        }
+        divS = (reg & 0x7) + 1;
+        divN = ((reg & 0xf00) >> 8) + 1;
+        div = ((reg & 0xf0000) >> 16) + 1;
+        return (src / divS / divN / div);
+    }
+
+    default:
+        ;
+    }
+    return 0;
+}
+
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_timer.c

@@ -0,0 +1,146 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @brief    N9H30 series TIMER driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_timer.h"
+
+void TIMER_SET_CMP_VALUE(uint32_t timer, uint32_t u32Cmpr)
+{
+    uint32_t u32TmrCMPROffset;
+
+    u32TmrCMPROffset = REG_TMR0_CMPR + timer * 0x10;
+
+    outpw(u32TmrCMPROffset, u32Cmpr);
+}
+
+void TIMER_SET_OPMODE(uint32_t timer, uint32_t u32OpMode)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, (inpw(u32TmrCSROffset) & ~(0x3UL << 27)) | u32OpMode);
+}
+
+void TIMER_SET_PRESCALE_VALUE(uint32_t timer, uint32_t u32PreScale)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, (inpw(u32TmrCSROffset) & ~(0xFFUL)) | u32PreScale);
+}
+
+uint32_t TIMER_GetModuleClock(uint32_t timer)
+{
+    return 12000000;
+}
+
+void TIMER_Start(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) | TIMER_COUNTER_ENABLE);
+}
+
+void TIMER_Stop(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) & ~TIMER_COUNTER_ENABLE);
+}
+
+void TIMER_ClearCounter(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) | TIMER_COUNTER_RESET);
+}
+
+uint32_t TIMER_GetCounter(uint32_t timer)
+{
+    uint32_t u32TmrDROffset;
+
+    u32TmrDROffset = REG_TMR0_DR + timer * 0x10;
+
+    return inpw(u32TmrDROffset);
+}
+
+uint32_t TIMER_GetCompareData(uint32_t timer)
+{
+    uint32_t u32TmrCMPROffset;
+
+    u32TmrCMPROffset = REG_TMR0_CMPR + timer * 0x10;
+
+    return inpw(u32TmrCMPROffset);
+}
+
+void TIMER_EnableInt(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset,  inpw(u32TmrCSROffset) | TIMER_INTERRUPT_ENABLE);
+}
+
+void TIMER_DisableInt(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset,  inpw(u32TmrCSROffset) & ~TIMER_INTERRUPT_ENABLE);
+}
+
+void TIMER_Close(uint32_t timer)
+{
+    uint32_t u32TmrCSROffset;
+
+    u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
+
+    outpw(u32TmrCSROffset, 0);
+}
+
+uint32_t TIMER_Open(uint32_t timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(timer);
+    uint32_t u32Cmpr = 0, u32Prescale = 0;
+    uint32_t u32TmrOffset = 0;
+
+    // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
+    if (u32Freq > (u32Clk / 2))
+    {
+        u32Cmpr = 2;
+    }
+    else
+    {
+        /* Clock source is only XIN. */
+        u32Cmpr = u32Clk / u32Freq;
+    }
+
+    u32TmrOffset = timer * 0x10;
+
+    TIMER_Close(timer);            /* disable timer */
+    TIMER_DisableInt(timer);       /* clear for safety */
+
+    outpw(REG_TMR0_CMPR + u32TmrOffset,  u32Cmpr);
+    outpw(REG_TMR0_CSR + u32TmrOffset,   u32Mode | u32Prescale);
+
+    return (u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_uart.c

@@ -0,0 +1,2200 @@
+/**************************************************************************//**
+* @file     uart.c
+* @version  V1.00
+* @brief    N9H30 UART driver source file
+*
+* SPDX-License-Identifier: Apache-2.0
+* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#if 0
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_uart.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_UART_Driver UART Driver
+  @{
+*/
+
+/** @addtogroup N9H30_UART_EXPORTED_CONSTANTS UART Exported Constants
+  @{
+*/
+
+/*@}*/ /* end of group N9H30_UART_EXPORTED_CONSTANTS */
+
+/// @cond HIDDEN_SYMBOLS
+
+/*-----------------------------------------*/
+/* marco, type and constant definitions    */
+/*-----------------------------------------*/
+/*
+    Define debug level
+*/
+//#define UART_DEBUG
+//#define UART_FLOWCONTROL_DEBUG
+//#define UART1_DEBUG
+//#define UART2_DEBUG
+
+#ifdef UART_DEBUG
+    #define UDEBUG          sysprintf
+#else
+    #define UDEBUG(...)
+#endif  /* UART_DEBUG */
+
+#ifdef UART_FLOWCONTROL_DEBUG
+    #define FDEBUG          sysprintf
+#else
+    #define FDEBUG(...)
+#endif  /* UART_FLOWCONTROL_DEBUG */
+
+#ifdef UART1_DEBUG
+    #define U1DEBUG         sysprintf
+#else
+    #define U1DEBUG(...)
+#endif  /* UART1_DEBUG */
+
+#ifdef UART2_DEBUG
+    #define U2DEBUG         sysprintf
+#else
+    #define U2DEBUG(...)
+#endif  /* UART1_DEBUG */
+
+/*-----------------------------------------*/
+/* global file scope (static) variables    */
+/*-----------------------------------------*/
+static UART_BUFFER_T UART_DEV[UART_NUM];
+
+static UINT32 UARTTXBUFSIZE[UART_NUM] = {500, 500, 500, 500, 500, 500, 500, 500, 500, 500, 500};  /* UART0~10 Tx buffer size */
+static UINT32 UARTRXBUFSIZE[UART_NUM] = {500, 500, 500, 500, 500, 500, 500, 500, 500, 500, 500};    /* UART0~10 Rx buffer size */
+
+
+/*
+    UART flag declarations.
+*/
+static volatile CHAR _uart_cDSRState0 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState1 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState2 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState3 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState4 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState5 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState6 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState7 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState8 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState9 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cDSRState10 = 0;   /* set 1, state change                         */
+static volatile CHAR _uart_cBIIState_0 = 0;  /* set 1, UART channel 0 break interrupt occur */
+static volatile CHAR _uart_cBIIState_1 = 0;  /* set 1, UART channel 1 break interrupt occur */
+static volatile CHAR _uart_cBIIState_2 = 0;  /* set 1, UART channel 2 break interrupt occur */
+static volatile CHAR _uart_cBIIState_3 = 0;  /* set 1, UART channel 3 break interrupt occur */
+static volatile CHAR _uart_cBIIState_4 = 0;  /* set 1, UART channel 4 break interrupt occur */
+static volatile CHAR _uart_cBIIState_5 = 0;  /* set 1, UART channel 0 break interrupt occur */
+static volatile CHAR _uart_cBIIState_6 = 0;  /* set 1, UART channel 1 break interrupt occur */
+static volatile CHAR _uart_cBIIState_7 = 0;  /* set 1, UART channel 2 break interrupt occur */
+static volatile CHAR _uart_cBIIState_8 = 0;  /* set 1, UART channel 3 break interrupt occur */
+static volatile CHAR _uart_cBIIState_9 = 0;  /* set 1, UART channel 4 break interrupt occur */
+static volatile CHAR _uart_cBIIState_10 = 0;  /* set 1, UART channel 4 break interrupt occur */
+static volatile CHAR _uart_cCTSState0 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState1 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState2 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState3 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState4 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState5 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState6 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState7 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState8 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState9 = 0;    /* set 1, state change                         */
+static volatile CHAR _uart_cCTSState10 = 0;    /* set 1, state change                         */
+
+/*
+    Define flow control flags & parameters.
+*/
+#define HWFLOWCONTROL   1
+#define SWFLOWCONTROL   2
+static volatile CHAR _uart_cFlowControlMode = 0;  /* default no flow control */
+static volatile CHAR _uart_cHWTXStopped = 0;      /* Use for H/W flow control. Set 1, stop TX. Set 0, start TX.   */
+static volatile CHAR _uart_cHWRXStopped = 0;      /* Use for H/W flow control. Set 1, stop RX. Set 0, start RX.   */
+static volatile CHAR _uart_cSWTXStopped = 0;      /* Use for S/W flow control. Set 1, rec Xoff. Set 0, rec Xon.   */
+static volatile CHAR _uart_cSWRXStopped = 0;      /* Use for S/W flow control. Set 1, send Xoff. Set 0, send Xon. */
+//static INT _uart_nMaxRxBuf = 0;                   /* used in uartReceiveChars() */
+//static INT _uart_nMinRxBuf = 0;                   /* used in uartReadRxBuf()    */
+
+
+/*-----------------------------------------*/
+/* prototypes of static functions          */
+/*-----------------------------------------*/
+static UINT32 _uartTxBufGetNextOne(INT nNum, UINT32 uPointer);
+static UINT32 _uartRxBufGetNextOne(INT nNum, UINT32 uPointer);
+static void _uartEnableInterrupt(INT nNum, UINT32 uVal);
+static void _uartDisableInterrupt(INT nNum, UINT32 uVal);
+static void _uartReceiveChars(INT nNum);
+static void _uartTransmitChars(INT nNum);
+static void _uartCheckModemStatus(INT nNum);
+static INT _uartSetBaudRate(INT nNum, UART_T *val);
+static void _uartInstallISR(UINT8 ucNum);
+static BOOL _uartBUFSpaceAlloc(INT nNum);
+static BOOL _uartCheckTxBufSpace(INT nNum, UINT32 uHead, UINT32 uTail, UINT32 uLen);
+static INT32 _uartReadRxBuf(INT nNum, PUINT8 pucBuf, UINT32 uLen);
+static void _uartWriteTxBuf(INT nNum, PUINT8 pucBuf, UINT32 uLen);
+static INT _uartConfigureUART(PVOID pvParam);
+static INT _uartPerformIrDA(INT nNum, UINT32 uCmd, UINT32 uCmd1);
+static INT _uartGetRegisterValue(INT nNum, PVOID pvReg);
+
+
+void RS485_HANDLE(INT nNum)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegALT_CSR;
+
+    uRegISR = inpw(REG_UART0_ISR + (nNum * UARTOFFSET));
+    uRegFSR = inpw(REG_UART0_FSR + (nNum * UARTOFFSET));
+
+    if ((uRegISR & UART_ISR_RLS_IF_Msk) && (uRegISR & UART_ISR_RDA_IF_Msk)) /* RLS INT & RDA INT */ //For RS485 Detect Address
+    {
+        if (uRegFSR & UART_FSR_RS485_ADD_DETF_Msk)  /* ADD_IF, RS485 mode */
+        {
+            _uartReceiveChars(nNum);
+            outpw((REG_UART0_FSR + (nNum * UARTOFFSET)), UART_FSR_RS485_ADD_DETF_Msk); /* clear ADD_IF flag */
+        }
+    }
+    else if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk))     /* Rx Ready or Time-out INT*/
+    {
+        /* Handle received data */
+        _uartReceiveChars(nNum);
+    }
+
+    if (uRegISR & UART_ISR_RLS_IF_Msk)
+    {
+        uRegFSR = inpw(REG_UART0_FSR + (nNum * UARTOFFSET));
+        if (uRegFSR & UART_FSR_BIF_Msk)
+            _uart_cBIIState_0 = 1;
+    }
+}
+
+void uart0ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR;
+
+    uRegISR = inpw(REG_UART0_ISR) & 0xff;
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART0);
+
+    if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+        _uartReceiveChars(UART0);
+
+    if (uRegISR & UART_ISR_RLS_IF_Msk)
+    {
+        uRegFSR = inpw(REG_UART0_FSR);
+        if (uRegFSR & UART_FSR_BIF_Msk)
+            _uart_cBIIState_0 = 1;
+    }
+
+}
+
+void uart1ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART1_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART1_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART1);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART1);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART1);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART1_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState1 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART1);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART1_FSR);
+            U1DEBUG("U1 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_1 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U1 OEI!\n");
+        }
+    }
+}
+
+void uart2ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART2_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART2_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART2);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART2);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART2);
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART2_FSR);
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_2 = 1;
+        }
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART2_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState2 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART2);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART2_FSR);
+            U1DEBUG("U2 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_2 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U2 OEI!\n");
+        }
+    }
+}
+
+void uart3ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART3_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART3_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART3);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART3);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk))
+            _uartReceiveChars(UART3);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART3_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState3 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART3);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART3_FSR);
+            U1DEBUG("U3 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_3 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U3 OEI!\n");
+        }
+    }
+
+}
+
+void uart4ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART4_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART4_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART4);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART4);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART4);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART4_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState4 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART4);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART4_FSR);
+            U1DEBUG("U4 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_4 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U4 OEI!\n");
+        }
+    }
+
+}
+
+void uart5ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART5_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART5_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART5);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART5);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART5);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART5_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState5 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART5);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART5_FSR);
+            U1DEBUG("U5 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_5 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U5 OEI!\n");
+        }
+    }
+
+}
+
+void uart6ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART6_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART6_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART6);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART6);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART6);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART6_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState6 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART6);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART6_FSR);
+            U1DEBUG("U6 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_6 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U6 OEI!\n");
+        }
+    }
+
+}
+
+void uart7ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART7_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART7_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART7);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART7);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART7);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART7_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState7 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART7);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART7_FSR);
+            U1DEBUG("U7 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_7 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U7 OEI!\n");
+        }
+    }
+
+}
+
+void uart8ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART8_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART8_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART8);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART8);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UART8);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART8_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState8 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART8);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART8_FSR);
+            U1DEBUG("U8 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_8 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U8 OEI!\n");
+        }
+    }
+
+}
+
+void uart9ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UART9_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UART9_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UART9);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UART9);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk))  /* Received Data Available interrupt */
+            _uartReceiveChars(UART9);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UART9_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState9 = 1;
+            }
+            else
+                _uartCheckModemStatus(UART9);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UART9_FSR);
+            U1DEBUG("U9 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_9 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U9 OEI!\n");
+        }
+    }
+
+}
+
+void uart10ISR(void)
+{
+    UINT32 volatile uRegISR, uRegFSR, uRegMSR, uRegFUN_SEL;
+
+    uRegISR = inpw(REG_UARTA_ISR) & 0xff;
+    uRegFUN_SEL = inpw(REG_UARTA_FUN_SEL);
+
+    if (uRegISR & UART_ISR_THRE_IF_Msk) /* TX empty interrupt, check LSR 4 kinds of error further */
+        _uartTransmitChars(UARTA);
+
+    if (uRegFUN_SEL == 0x3)
+    {
+        RS485_HANDLE(UARTA);
+    }
+    else
+    {
+        if (uRegISR & (UART_ISR_RDA_IF_Msk | UART_ISR_TOUT_IF_Msk)) /* Received Data Available interrupt */
+            _uartReceiveChars(UARTA);
+
+        if (uRegISR & UART_ISR_MODEM_IF_Msk)
+        {
+            if (_uart_cFlowControlMode == 0)
+            {
+                uRegMSR = inpw(REG_UARTA_MSR);
+
+                if (uRegMSR & 0x01)
+                    _uart_cCTSState10 = 1;
+            }
+            else
+                _uartCheckModemStatus(UARTA);  /* H/W flow control */
+        }
+
+        if (uRegISR & UART_ISR_RLS_IF_Msk)
+        {
+            uRegFSR = inpw(REG_UARTA_FSR);
+            U1DEBUG("U10 Irpt_RLS [0x%x]!\n", uRegFSR);
+
+            if (uRegFSR & UART_FSR_BIF_Msk)
+                _uart_cBIIState_10 = 1;
+
+            if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+                U1DEBUG("U10 OEI!\n");
+        }
+    }
+
+}
+
+static UINT32 _uartTxBufGetNextOne(INT nNum, UINT32 uPointer)
+{
+    if ((uPointer + 1) == UARTTXBUFSIZE[nNum])
+        return (UINT32)NULL;
+    else
+        return (uPointer + 1);
+}
+
+static UINT32 _uartRxBufGetNextOne(INT nNum, UINT32 uPointer)
+{
+    if ((uPointer + 1) == UARTRXBUFSIZE[nNum])
+        return (UINT32)NULL;
+    else
+        return (uPointer + 1);
+}
+
+static void _uartEnableInterrupt(INT nNum, UINT32 uVal)
+{
+    UINT32 uReg = 0;
+
+    uReg = inpw(REG_UART0_IER + (nNum * UARTOFFSET));
+    uReg |= uVal;
+    outpw(REG_UART0_IER + (nNum * UARTOFFSET), uReg);
+}
+
+static void _uartDisableInterrupt(INT nNum, UINT32 uVal)
+{
+    UINT32 uReg = 0;
+
+    if (uVal == DISABLEALLIER)
+        outpw(REG_UART0_IER + (nNum * UARTOFFSET), 0);
+    else
+    {
+        uReg = inpw(REG_UART0_IER + (nNum * UARTOFFSET));
+        uReg &= ~uVal;
+        outpw(REG_UART0_IER + (nNum * UARTOFFSET), uReg);
+    }
+}
+
+static void _uartReceiveChars(INT nNum)
+{
+    //UINT32 volatile uRegLSR, uBuf = 0;
+    UINT32 volatile uRegFSR, uRegALT_CSR, uRegFUN_SEL, uRegFCR, uRegLINSR, uRegISR;
+    UINT32 volatile uBuf = 0;
+    UINT32 volatile uOffset = nNum * UARTOFFSET;
+    INT nMaxCount = 256;
+    UCHAR ucChar;
+
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    //uRegFSR = inpw(REG_UART0_FSR+(nNum * UARTOFFSET));
+    uRegFUN_SEL = inpw(REG_UART0_FUN_SEL + uOffset);
+
+    do
+    {
+        uRegFSR = inpw(REG_UART0_FSR + uOffset);
+        uRegLINSR = inpw(REG_UART0_LIN_SR + uOffset);
+        uRegISR = inpw(REG_UART0_ISR + uOffset);
+        ucChar = inpb(REG_UART0_RBR + uOffset);
+
+        if ((uRegFSR & UART_FSR_RS485_ADD_DETF_Msk) && (uRegFUN_SEL == 0x3))
+        {
+            uRegALT_CSR = inpw(REG_UART0_ALT_CSR + (nNum * UARTOFFSET));
+            uRegFCR = inpw(REG_UART0_FCR + (nNum * UARTOFFSET));
+            if (uRegALT_CSR & UART_ALT_CSR_RS485_NMM_Msk)
+            {
+                if (ucChar == (uRegALT_CSR >> UART_ALT_CSR_ADDR_MATCH_Pos))
+                {
+                    uRegFCR &= ~UART_FCR_RX_DIS_Msk;  /* Enable RS485 RX */
+                    outpw((REG_UART0_FCR + (nNum * UARTOFFSET)), uRegFCR);
+                }
+                else
+                {
+                    uRegFCR |= UART_FCR_RX_DIS_Msk;  /* Disable RS485 RX */
+                    uRegFCR |= UART_FCR_RFR_Msk;  /* Clear data from RX FIFO */
+                    outpw((REG_UART0_FCR + (nNum * UARTOFFSET)), uRegFCR);
+                    break;
+                }
+            }
+        }
+
+
+        uBuf = _uartRxBufGetNextOne(nNum, dev->uUartRxTail);
+        if (uBuf == dev->uUartRxHead)  /* Rx buffer full */
+        {
+            //ucChar = inpb(REG_UART0_RBR+(nNum * UARTOFFSET));
+
+            if (_uart_cHWRXStopped)
+                U1DEBUG("[%d] buf full!\n", nNum);
+
+            break;
+        }
+
+        //ucChar = inpb(REG_UART0_RBR+(nNum * UARTOFFSET));
+
+        dev->pucUartRxBuf[dev->uUartRxTail] = ucChar;
+
+        /* Check LSR for BII, FEI, PEI, OEI */
+        dev->pucUARTFlag[dev->uUartRxTail] = 0;
+
+        if (uRegFSR & UART_FSR_BIF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_BIF_Msk;
+            U1DEBUG("BIF!\n");
+        }
+        else if (uRegFSR & UART_FSR_FEF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_FEF_Msk;
+            U1DEBUG("FEF!\n");
+        }
+        else if (uRegFSR & UART_FSR_PEF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_PEF_Msk;
+            U1DEBUG("PEF!\n");
+        }
+        else if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_RX_OVER_IF_Msk;
+            U1DEBUG("OVER_IF!\n");
+        }
+        else if (uRegFSR & UART_FSR_RS485_ADD_DETF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_RS485_ADD_DETF_Msk;
+            U1DEBUG("RS485_ADD_DET_IF!\n");
+        }
+
+        if (uRegFUN_SEL == 0x1)
+        {
+            if (uRegISR & UART_ISR_LIN_RX_BREAK_IF_Msk)
+            {
+                dev->pucLINFlag[dev->uUartRxTail] = uRegLINSR;
+
+                // Clear ISR and LIN Status
+                outpw(REG_UART0_ISR, UART_ISR_LIN_RX_BREAK_IF_Msk);
+                outpw(REG_UART0_LIN_SR, 0x30F);
+            }
+        }
+
+        dev->uUartRxTail = _uartRxBufGetNextOne(nNum, dev->uUartRxTail);
+
+        /* overrun error is special case, H/W ignore the character */
+        if (uRegFSR & UART_FSR_RX_OVER_IF_Msk)
+        {
+            dev->pucUARTFlag[dev->uUartRxTail] = UART_FSR_RX_OVER_IF_Msk;
+            dev->uUartRxTail = _uartRxBufGetNextOne(nNum, dev->uUartRxTail);
+        }
+
+        uRegFSR = inpw(REG_UART0_FSR + (nNum * UARTOFFSET));
+    }
+    while ((!(uRegFSR & UART_FSR_RX_EMPTY_Msk)) && (nMaxCount-- > 0));
+
+}
+
+static void _uartTransmitChars(INT nNum)
+{
+    UINT32 volatile i;
+
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    if (dev->uUartTxHead != dev->uUartTxTail)  /* buffer is not empty */
+    {
+        for (i = 0; i < 8; i++)
+        {
+            outpw(REG_UART0_THR + (nNum * UARTOFFSET), dev->pucUartTxBuf[dev->uUartTxHead]);
+            dev->uUartTxHead = _uartTxBufGetNextOne(nNum, dev->uUartTxHead);
+
+            if (dev->uUartTxHead == dev->uUartTxTail)  /* buffer empty */
+            {
+                _uartDisableInterrupt(nNum, UART_IER_THRE_IEN_Msk);
+                break;
+            }
+        }
+    }
+}
+
+/*
+    Call by uart1ISR().
+*/
+static void _uartCheckModemStatus(INT nNum)
+{
+    UINT32 volatile uRegMSR;
+    UINT32 uOffset = nNum * UARTOFFSET;
+
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    FDEBUG("\n Modem INT\n");
+    uRegMSR = inpw(REG_UART0_MSR + uOffset);
+    if (_uart_cHWTXStopped)
+    {
+        if (!(uRegMSR & 0x10))  /* CTS high, external signal is low */
+        {
+            _uart_cHWTXStopped = 0;
+            FDEBUG("H/W flow control ...\n");
+
+            /* 2007.11.12 modify, PT23 HHWu */
+            if (dev->uUartTxHead != dev->uUartTxTail)   /* buffer is not empty */
+            {
+                _uartEnableInterrupt(nNum, UART_IER_THRE_IEN_Msk);  /* enable TX empty interrupt */
+                FDEBUG("buf not empty, TX continued\n");
+            }
+        }
+    }
+    else
+    {
+        if (!(uRegMSR & 0x10))    /* CTS low, external signal is high */
+        {
+            _uart_cHWTXStopped = 1;
+            _uartDisableInterrupt(nNum, UART_IER_THRE_IEN_Msk);  /* disable TX empty interrupt */
+            FDEBUG("H/W flow control, TX stopped\n");
+        }
+    }
+}
+
+static INT _uartSetBaudRate(INT nNum, UART_T *val)
+{
+    UINT32 u32Reg;
+    UINT32 uOffset = nNum * UARTOFFSET;
+    UINT32 u32Baud_Div;
+    UINT32 u32Clk = val->uFreq;
+    UINT32 u32baudrate = val->uBaudRate;
+
+    //if (val->uFreq > 200000000)  /* Max frequency 200MHz */
+    //  return -1;
+
+    u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
+
+    if (u32Baud_Div > 0xFFFF)
+        u32Reg = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
+    else
+        u32Reg = (UART_BAUD_MODE2 | u32Baud_Div);
+
+    outpw(REG_UART0_BAUD + uOffset, u32Reg);
+
+    return 0;
+}
+
+static void _uartInstallISR(UINT8 ucNum)
+{
+    UART_BUFFER_T *dev;
+
+    IRQn_Type IRQ;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[ucNum];
+
+    if (ucNum == UART0)
+    {
+        IRQ = UART0_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart0ISR);
+    }
+    else if (ucNum == UART1)
+    {
+        IRQ = UART1_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart1ISR);
+    }
+    else if (ucNum == UART2)
+    {
+        IRQ = UART2_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart2ISR);
+    }
+    else if (ucNum == UART3)
+    {
+        IRQ = UART3_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart3ISR);
+    }
+    else if (ucNum == UART4)
+    {
+        IRQ = UART4_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart4ISR);
+    }
+    else if (ucNum == UART5)
+    {
+        IRQ = UART5_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart5ISR);
+    }
+    else if (ucNum == UART6)
+    {
+        IRQ = UART6_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart6ISR);
+    }
+    else if (ucNum == UART7)
+    {
+        IRQ = UART7_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart7ISR);
+    }
+    else if (ucNum == UART8)
+    {
+        IRQ = UART8_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart8ISR);
+    }
+    else if (ucNum == UART9)
+    {
+        IRQ = UART9_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart9ISR);
+    }
+    else if (ucNum == UARTA)
+    {
+        IRQ = UART10_IRQn;
+        dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)uart10ISR);
+    }
+    else
+    {
+        return;
+    }
+
+    //dev->pvUartVector = sysInstallISR((IRQ_LEVEL_1 | HIGH_LEVEL_SENSITIVE), IRQ, (PVOID)pvNewISR);
+    sysSetLocalInterrupt(ENABLE_IRQ);                            /* enable CPSR I bit */
+    sysEnableInterrupt(IRQ);
+    //DrvUART_EnableInt(TEST_PORT,(DRVUART_RLSINT|DRVUART_THREINT|DRVUART_RDAINT));
+
+
+}
+
+static BOOL _uartBUFSpaceAlloc(INT nNum)
+{
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    /* Memory allocate Tx buffer */
+    dev->pucUartTxBuf = (PUINT8) malloc(UARTTXBUFSIZE[nNum] * sizeof(UINT8));
+    if (dev->pucUartTxBuf == NULL)
+        return FALSE;
+
+    /* Memory allocate Rx buffer */
+    dev->pucUartRxBuf = (PUINT8) malloc(UARTRXBUFSIZE[nNum] * sizeof(UINT8));
+    if (dev->pucUartRxBuf == NULL)
+    {
+        free(dev->pucUartTxBuf);
+        return FALSE;
+    }
+
+    /* Memory allocate Rx character flag */
+    dev->pucUARTFlag = (PINT) malloc(UARTRXBUFSIZE[nNum] * sizeof(INT));
+    if (dev->pucUARTFlag == NULL)
+    {
+        free(dev->pucUartTxBuf);
+        free(dev->pucUartRxBuf);
+        return FALSE;
+    }
+
+    /* initial memory */
+    memset(dev->pucUartTxBuf, 0, UARTTXBUFSIZE[nNum] * sizeof(UINT8));
+    memset(dev->pucUartRxBuf, 0, UARTRXBUFSIZE[nNum] * sizeof(UINT8));
+    memset(dev->pucUARTFlag, 0, UARTRXBUFSIZE[nNum] * sizeof(INT));
+
+    /* inital struct UART_BUFFER_STRUCT, uUartTxHead, uUartTxTail, uUartRxHead, uUartRxTail */
+    dev->uUartTxHead = dev->uUartTxTail = (UINT32)NULL;
+    dev->uUartRxHead = dev->uUartRxTail = (UINT32)NULL;
+
+    return TRUE;
+}
+
+static BOOL _uartCheckTxBufSpace(INT nNum, UINT32 uHead, UINT32 uTail, UINT32 uLen)
+{
+    UINT32 uBuf;
+
+    uBuf = _uartTxBufGetNextOne(nNum, uTail);
+    if (uBuf == uHead)  /* Tx buffer full */
+        return FALSE;
+
+    if (uHead == uTail) /* Tx buffer empty */
+        return TRUE;
+
+    if (uTail > uHead)
+    {
+        if (uLen >= (UARTTXBUFSIZE[nNum] - (uTail - uHead))) /* 2007.10.29 fix pointer bug, PT23 HHWu */
+            return FALSE;  /* Tx buffer space isn't enough */
+        else
+            return TRUE;
+    }
+    else
+    {
+        /* case: uTail < uHead */
+        if (uLen >= (uHead - uTail)) /* 2007.10.29 fix pointer bug, PT23 HHWu */
+            return FALSE;  /* Tx buffer space isn't enough */
+        else
+            return TRUE;
+    }
+
+    //return TRUE;
+}
+
+static INT32 _uartReadRxBuf(INT nNum, PUINT8 pucBuf, UINT32 uLen)
+{
+    UINT32 i;
+    UINT32 uOffset = nNum * UARTOFFSET;
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    if (dev->bIsUseUARTRxInt == TRUE)
+    {
+
+        // disable Rx interrupt ...
+
+        if (dev->uUartRxHead == dev->uUartRxTail)
+            return 0;
+
+        for (i = uLen ; i > 0 ; i--)
+        {
+            *pucBuf++ = dev->pucUartRxBuf[dev->uUartRxHead];
+            dev->uUartRxHead = _uartRxBufGetNextOne(nNum, dev->uUartRxHead);
+
+            if (dev->uUartRxHead == dev->uUartRxTail)
+                break;
+        }
+
+        uLen = uLen - i + 1;
+    }
+    else     /* pooling mode */
+    {
+        for (i = 0 ; i < uLen; i++)
+        {
+            while (!(inpw(REG_UART0_FSR + uOffset) & UART_FSR_RX_EMPTY_Msk));
+            *pucBuf++ = inpb(REG_UART0_RBR + uOffset);
+        }
+    }
+
+    return (uLen);
+}
+
+static void _uartWriteTxBuf(INT nNum, PUINT8 pucBuf, UINT32 uLen)
+{
+    UINT32 i;
+    UINT32 uOffset = nNum * UARTOFFSET;
+    UART_BUFFER_T *dev;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    /* Check interrupt or polling mode first */
+    if (dev->bIsUseUARTTxInt == TRUE)
+    {
+        while (uLen--)
+        {
+            dev->pucUartTxBuf[dev->uUartTxTail] = *pucBuf++;
+            dev->uUartTxTail = _uartTxBufGetNextOne(nNum, dev->uUartTxTail);
+        }
+
+        if (!(inpw(REG_UART0_IER + uOffset) & UART_IER_THRE_IEN_Msk)) /* Enable Tx empty interrupt */
+            _uartEnableInterrupt(nNum, UART_IER_THRE_IEN_Msk);
+    }
+    else     /* pooling mode */
+    {
+        for (i = 0 ; i < uLen ; i++)
+        {
+            /* Wait until the transmitter buffer is empty */
+            while (!(inpw(REG_UART0_FSR + uOffset) & UART_FSR_TE_FLAG_Msk));
+            outpw(REG_UART0_THR + uOffset, *pucBuf++);
+        }
+    }
+}
+
+static INT _uartConfigureUART(PVOID pvParam)
+{
+    INT retval;
+    BOOL bIsMemoryAllocOk;
+    UINT32 u32Reg;
+    UINT32 uOffset;
+    UINT32 uNum = 0;
+
+    UART_T *param = (UART_T *) pvParam;
+
+    uOffset = param->ucUartNo * UARTOFFSET;
+    uNum = param->ucUartNo;
+
+    /* Check UART channel */
+    if (uNum > UARTA)
+        return UART_ERR_CHANNEL_INVALID;
+
+    /* Check the supplied parity */
+    if ((param->ucParity != NU_PARITY_NONE) &&
+            (param->ucParity != NU_PARITY_EVEN) &&
+            (param->ucParity != NU_PARITY_ODD)  &&
+            (param->ucParity != (NU_PARITY_ODD | NU_PARITY_STICK)) &&
+            (param->ucParity != (NU_PARITY_EVEN | NU_PARITY_STICK)))
+        return UART_ERR_PARITY_INVALID;
+
+    /* Check the supplied number of data bits */
+    if ((param->ucDataBits != NU_DATA_BITS_5) &&
+            (param->ucDataBits != NU_DATA_BITS_6) &&
+            (param->ucDataBits != NU_DATA_BITS_7) &&
+            (param->ucDataBits != NU_DATA_BITS_8))
+        return UART_ERR_DATA_BITS_INVALID;
+
+    /* Check the supplied number of stop bits */
+    if ((param->ucStopBits != NU_STOP_BITS_1) &&
+            (param->ucStopBits != NU_STOP_BITS_2))
+        return UART_ERR_STOP_BITS_INVALID;
+
+    /* Check the supplied number of trigger level bytes */
+    if ((param -> ucUartNo == UART1) || (param -> ucUartNo == UART2) || (param -> ucUartNo == UART4) ||
+            (param -> ucUartNo == UART6) || (param -> ucUartNo == UART8) || (param -> ucUartNo == UARTA))
+    {
+        /* UART1,2,4,6,8,A */
+        if ((param->ucRxTriggerLevel != UART_FCR_RFITL_1BYTE)   &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_4BYTES)  &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_8BYTES)  &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_14BYTES) &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_30BYTES) &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_46BYTES) &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_62BYTES))
+            return UART_ERR_TRIGGERLEVEL_INVALID;
+    }
+    else
+    {
+        /* UART0,3,5,7,9 */
+        if ((param->ucRxTriggerLevel != UART_FCR_RFITL_1BYTE)  &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_4BYTES) &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_8BYTES) &&
+                (param->ucRxTriggerLevel != UART_FCR_RFITL_30BYTES))
+            return UART_ERR_TRIGGERLEVEL_INVALID;
+    }
+
+    /* Enable UART clock */
+    if (param->ucUartNo < ALLCHANNEL)
+    {
+        outpw(REG_CLK_PCLKEN0, inpw(REG_CLK_PCLKEN0) | (1 << (16 + param->ucUartNo)));
+    }
+
+    /* Reset TX/RX FIFOs */
+    u32Reg = inpw(REG_UART0_FCR + uOffset);
+    outpw(REG_UART0_FCR + uOffset, (u32Reg | (0x03 << 1)));
+
+    /* Setup baud rate */
+    retval = _uartSetBaudRate(param->ucUartNo, param);
+    if (retval < 0)
+        return UART_ERR_SET_BAUDRATE_FAIL;
+
+    /* Setup parity, data bits, and stop bits */
+    outpw(REG_UART0_LCR + uOffset, (param->ucParity | param->ucDataBits | param->ucStopBits));
+
+    /* Setup Rx time out value */
+    outpw(REG_UART0_TOR + uOffset, 0x80 + 0x20);
+
+    /* Setup FIFO trigger level */
+    outpw(REG_UART0_FCR + uOffset, param->ucRxTriggerLevel);
+
+    /* only exec once unless call uartClose() */
+    if (UART_DEV[param->ucUartNo].bIsUARTInitial == FALSE)
+    {
+        /* Configure GPIO function */
+        //_uartConfigureGPIO(param->ucUartNo);
+
+        /* Allocate Tx, Rx buffer */
+        bIsMemoryAllocOk = _uartBUFSpaceAlloc(param->ucUartNo);
+        if (bIsMemoryAllocOk == FALSE)
+            return UART_ERR_ALLOC_MEMORY_FAIL;
+
+        /* Hook UART interrupt service routine */
+        _uartInstallISR(param->ucUartNo);
+
+        /* Enable Rx interrupt */
+        if (UART_DEV[param->ucUartNo].bIsUseUARTRxInt == TRUE)
+            _uartEnableInterrupt(param->ucUartNo, UART_IER_RDA_IEN_Msk);
+
+    }
+
+    UART_DEV[param->ucUartNo].bIsUARTInitial = TRUE;  /* it's important to set TRUE */
+    return 0;
+}
+
+static INT _uartPerformIrDA(INT nNum, UINT32 uCmd, UINT32 uCmd1)  /* UART2 only */
+{
+    UINT32 uOffset = nNum * UARTOFFSET;
+    UINT32 baud;
+
+    switch (uCmd)
+    {
+    case ENABLEIrDA:
+        //_uart_bIsPerformIrDA = TRUE;
+
+        baud = inpw(REG_UART0_BAUD + uOffset);
+        baud = baud & (0x0000ffff);
+        baud = baud + 2;
+        baud = baud / 16;
+        baud = baud - 2;
+
+        outpw(REG_UART0_BAUD + uOffset, baud);
+
+        if (uCmd1 == IrDA_TX)
+            outpw(REG_UART0_IRCR + uOffset, UART_IRCR_TX_SELECT_Msk);
+        else if (uCmd1 == IrDA_RX)
+            outpw(REG_UART0_IRCR + uOffset, 0x0);
+        else
+            return UART_ERR_IrDA_COMMAND_INVALID;
+
+        outpw(REG_UART0_FUN_SEL + uOffset, 0x2); // Select IrDA mode
+
+        break;
+
+    case DISABLEIrDA:
+        //_uart_bIsPerformIrDA = FALSE;
+        outpw(REG_UART0_IRCR + uOffset, 0x40); /* Set default value, INV_TX set 0, INV_RX set 1 */
+        outpw(REG_UART0_FUN_SEL + uOffset, 0x0); // Select UART mode
+        break;
+
+    default:
+        return UART_ERR_IrDA_COMMAND_INVALID;
+    }
+
+    return 0;
+}
+
+/*
+    Remark:
+    1. LCR & LSR aren't support yet.
+*/
+static INT _uartGetRegisterValue(INT nNum, PVOID pvReg)
+{
+    INT nCnt = 0;
+    UINT32 uOffset = nNum * UARTOFFSET;
+
+    UART_REGISTER_T *reg = (UART_REGISTER_T *) pvReg;
+
+    memset(reg, 0, sizeof(UART_REGISTER_T));
+
+    /* Read IER */
+    reg->uUartReg[nCnt][0] = REG_UART0_IER + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_IER + uOffset);
+
+    /* Read FCR */
+    reg->uUartReg[nCnt][0] = REG_UART0_FCR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_FCR + uOffset);
+
+    /* Read LCR */
+    reg->uUartReg[nCnt][0] = REG_UART0_LCR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_LCR + uOffset);
+
+    /* Read MCR, MSR */
+    reg->uUartReg[nCnt][0] = REG_UART0_MCR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_MCR + uOffset);
+    reg->uUartReg[nCnt][0] = REG_UART0_MSR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_MSR + uOffset);
+
+    /* Read FSR */
+    reg->uUartReg[nCnt][0] = REG_UART0_FSR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_FSR + uOffset);
+
+    /* Read ISR */
+    reg->uUartReg[nCnt][0] = REG_UART0_ISR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_ISR + uOffset);
+
+    /* Read TOR */
+    reg->uUartReg[nCnt][0] = REG_UART0_TOR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_TOR + uOffset);
+
+    /* Read BAUD */
+    reg->uUartReg[nCnt][0] = REG_UART0_BAUD + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_BAUD + uOffset);
+
+    /* Read IRCR */
+    reg->uUartReg[nCnt][0] = REG_UART0_IRCR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_IRCR + uOffset);
+
+    /* Read ALT_CSR */
+    reg->uUartReg[nCnt][0] = REG_UART0_ALT_CSR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_ALT_CSR + uOffset);
+
+    /* Read FUN_SEL */
+    reg->uUartReg[nCnt][0] = REG_UART0_FUN_SEL + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_FUN_SEL + uOffset);
+
+    /* Read LIN_CTL */
+    reg->uUartReg[nCnt][0] = REG_UART0_LIN_CTL + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_LIN_CTL + uOffset);
+
+    /* Read LIN_SR */
+    reg->uUartReg[nCnt][0] = REG_UART0_LIN_SR + uOffset;
+    reg->uUartReg[nCnt++][1] = inpw(REG_UART0_LIN_SR + uOffset);
+
+    return (nCnt);
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup N9H30_UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+  * @brief    The function is used to initial device struct parameters.
+  *
+  * @return   0
+  */
+INT uartInit(void)
+{
+    INT i;
+
+    /* Initial UART_BUFFER_T struct */
+    for (i = 0; i < UART_NUM ; i++)
+        UART_DEV[i].bIsUARTInitial = FALSE;
+
+    for (i = 0; i < UART_NUM ; i++)
+        UART_DEV[i].bIsUseUARTTxInt = TRUE;
+
+    for (i = 0; i < UART_NUM ; i++)
+        UART_DEV[i].bIsUseUARTRxInt = TRUE;
+
+    return 0;
+}
+
+/**
+  * @brief    The function is used to config UART channel.
+  *
+  * @param[in]    uart: UART Port. ( UART0 / UART1 / UART2 / UART3 / UART 4 /UART 5 /
+  *                                 UART6 / UART7 / UART8 / UART9 / UARTA )
+  *
+  * @return   UART_EIO: UART config Fail
+  *           Successful: UART config success
+  */
+INT uartOpen(PVOID uart)
+{
+    INT nValue = 0;
+    UART_T *dev = (UART_T *) uart;
+
+    if ((nValue = _uartConfigureUART(uart)) < 0)
+    {
+        if (nValue != UART_ERR_CHANNEL_INVALID)
+            UART_DEV[dev->ucUartNo].nErrno = nValue;
+
+        return UART_EIO;
+    }
+    else
+        UART_DEV[dev->ucUartNo].nErrno = 0;
+
+    return Successful;
+}
+
+/**
+  * @brief    The function is used to read RX FIFO returned data or RX driver buffer.
+  *
+  * @param[in]    nNum: UART Port. ( UART0 / UART1 / UART2 / UART3 / UART 4 /UART 5 /
+  *                                 UART6 / UART7 / UART8 / UART9 / UARTA )
+  * @param[out]   pucBuf: The buffer to receive.
+  *
+  * @param[in]    uLen: The the read bytes number of data.
+  *
+  * @return   UART_EIO: UART read Fail
+  *           DataLength: Receive byte count
+  */
+INT32 uartRead(INT nNum, PUINT8 pucBuf, UINT32 uLen)
+{
+    UART_BUFFER_T *dev;
+    INT32 DataLength;
+
+    //if((nNum < UART0) || (nNum > UART4))
+    //  return UART_ENODEV;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    /* Check UART initial status */
+    if (dev->bIsUARTInitial == FALSE)
+        return UART_EIO;
+
+    /* Check uLen value */
+    if ((uLen > UARTRXBUFSIZE[nNum]) || (uLen == 0))
+        return UART_EIO;
+
+    DataLength = _uartReadRxBuf(nNum, pucBuf, uLen);
+
+    return (DataLength);
+
+}
+
+
+/**
+  * @brief    The function is used to write data to TX FIFO directly or TX driver buffer.
+  *
+  * @param[in]    nNum: UART channel. ( UART0 / UART1 / UART2 / UART3 / UART 4 /UART 5 /
+  *                                     UART6 / UART7 / UART8 / UART9 / UARTA )
+  * @param[out]   pucBuf: Transmit buffer pointer.
+  *
+  * @param[in]    uLen: Transmit buffer length.
+  *
+  * @return   UART_EIO: UART transmit Fail
+  *           uLen: write length on success
+  */
+INT32 uartWrite(INT nNum, PUINT8 pucBuf, UINT32 uLen)
+{
+    BOOL bIsTxBufEnough;
+
+    UART_BUFFER_T *dev;
+
+    //if((nNum < UART0) || (nNum > UART4))
+    //  return UART_ENODEV;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+    dev->nErrno = 0;
+
+    /* Check UART initial status */
+    if (dev->bIsUARTInitial == FALSE)
+        return UART_EIO;
+
+    /* Check uLen value */
+    if ((uLen > UARTWRITESIZE) || (uLen == 0))
+        return UART_EIO;
+
+    /* Check UART Tx buffer */
+    if (dev->bIsUseUARTTxInt == TRUE)
+    {
+        bIsTxBufEnough = _uartCheckTxBufSpace(nNum, dev->uUartTxHead, dev->uUartTxTail, uLen);
+        if (bIsTxBufEnough == FALSE)
+        {
+            //sysprintf("Tx buf not enough\n");
+            dev->nErrno = UART_ERR_TX_BUF_NOT_ENOUGH;
+            return UART_EIO;
+        }
+    }
+
+    /* Move data to UART Tx buffer then transmit */
+    _uartWriteTxBuf(nNum, pucBuf, uLen);
+
+    return (uLen);
+}
+
+/**
+  * @brief    Support some UART driver commands for application.
+  *
+  * @param[in]    nNum: UART channel. ( UART0 / UART1 / UART2 / UART3 / UART 4 /UART 5 /
+  *                                     UART6 / UART7 / UART8 / UART9 / UARTA )
+  *
+  * @param[in]    uCmd: Command.
+  *
+  * @param[in]    uArg0: Arguments for the command.
+  *
+  * @param[in]    uArg1: Arguments for the command.
+  *
+  * @return   UART_ENODEV: UART channel out of range
+  *           UART_EIO: No activated or argument error or configure UART fail
+  *           Successful: Success
+  */
+INT uartIoctl(INT nNum, UINT32 uCmd, UINT32 uArg0, UINT32 uArg1)
+{
+    INT32 retval;
+    UINT32 uReg;
+    UINT32 uOffset = nNum * UARTOFFSET;
+
+    UART_BUFFER_T *dev;
+
+    if ((nNum < UART0) || (nNum > UARTA))
+        return UART_ENODEV;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    /* Check UART initial status */
+    if (dev->bIsUARTInitial == FALSE)
+    {
+        if ((uCmd != UART_IOC_GETERRNO) &&
+                (uCmd != UART_IOC_GETUARTREGISTERVALUE))
+            return UART_EIO;
+    }
+
+    switch (uCmd)
+    {
+    case UART_IOC_SETTXMODE:
+        if (uArg0 == UARTINTMODE)
+            dev->bIsUseUARTTxInt = TRUE;
+        else if (uArg0 == UARTPOLLMODE)
+            dev->bIsUseUARTTxInt = FALSE;
+        else
+        {
+            dev->nErrno = UART_ERR_OPERATE_MODE_INVALID;
+            return UART_EIO;
+        }
+
+        break;
+
+    case UART_IOC_SETRXMODE:
+        if (uArg0 == UARTINTMODE)
+        {
+            dev->bIsUseUARTRxInt = TRUE;
+            _uartEnableInterrupt(nNum, UART_IER_RDA_IEN_Msk);
+        }
+        else if (uArg0 == UARTPOLLMODE)
+        {
+            dev->bIsUseUARTRxInt = FALSE;
+            _uartDisableInterrupt(nNum, UART_IER_RDA_IEN_Msk);
+        }
+        else
+        {
+            dev->nErrno = UART_ERR_OPERATE_MODE_INVALID;
+            return UART_EIO;
+        }
+
+        break;
+
+    case UART_IOC_GETRECCHARINFO:  // ..... not test yet
+        memcpy((PVOID) uArg0, (PVOID) dev, sizeof(struct UART_BUFFER_STRUCT));
+        break;
+
+    case UART_IOC_SETUARTPARAMETER:  // ..... not test yet
+        if ((retval = _uartConfigureUART((PVOID) uArg0)) < 0)
+        {
+            dev->nErrno = retval;
+            return UART_EIO;
+        }
+
+        break;
+
+    case UART_IOC_PERFORMIrDA:
+
+        if ((retval = _uartPerformIrDA(nNum, uArg0, uArg1)) < 0)
+        {
+            dev->nErrno = retval;
+            return UART_EIO;
+        }
+
+        break;
+
+    case UART_IOC_GETUARTREGISTERVALUE:
+        return (_uartGetRegisterValue(nNum, (PVOID) uArg0));
+    //break;
+
+    case UART_IOC_GETERRNO:
+        *(PUINT32)uArg0 = dev->nErrno;
+        break;
+
+    case UART_IOC_SETMODEMINTERRUPT:
+
+        if (uArg0 == UART_ENABLE_MODEM_INT)
+            _uartEnableInterrupt(nNum, UART_IER_MODEM_IEN_Msk);
+        else if (uArg0 == UART_DISABLE_MODEM_INT)
+            _uartDisableInterrupt(nNum, UART_IER_MODEM_IEN_Msk);
+        else
+            return UART_EIO;
+
+        break;
+
+    case UART_IOC_GETCTSSTATE:
+
+        if (nNum == UART1)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState1;                        /* CTS state */
+            _uart_cCTSState1 = 0;
+        }
+        else if (nNum == UART2)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState2;                        /* CTS state */
+            _uart_cCTSState2 = 0;
+        }
+        else if (nNum == UART3)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState3;                        /* CTS state */
+            _uart_cCTSState3 = 0;
+        }
+        else if (nNum == UART4)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState4;                        /* CTS state */
+            _uart_cCTSState4 = 0;
+        }
+        else if (nNum == UART5)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState5;                        /* CTS state */
+            _uart_cCTSState5 = 0;
+        }
+        else if (nNum == UART6)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState6;                        /* CTS state */
+            _uart_cCTSState6 = 0;
+        }
+        else if (nNum == UART7)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState7;                        /* CTS state */
+            _uart_cCTSState7 = 0;
+        }
+        else if (nNum == UART8)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState8;                        /* CTS state */
+            _uart_cCTSState8 = 0;
+        }
+        else if (nNum == UART9)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState9;                        /* CTS state */
+            _uart_cCTSState9 = 0;
+        }
+        else if (nNum == UARTA)
+        {
+            *(PUINT32)uArg0 = _uart_cCTSState10;                        /* CTS state */
+            _uart_cCTSState10 = 0;
+        }
+
+        *(PUINT32)uArg1 = (inpw(REG_UART0_MSR + uOffset) & (1 << 4)) >> 4; /* get CTS# value */
+
+        break;
+
+    case UART_IOC_SETRTSSIGNAL:
+
+        if (uArg0 == UART_RTS_HIGH)     /* set RTS signal high */
+            outpw(REG_UART0_MCR + uOffset, inpw(REG_UART0_MCR + uOffset) & ~0x02);
+        else if (uArg0 == UART_RTS_LOW) /* set RTS signal low  */
+            outpw(REG_UART0_MCR + uOffset, inpw(REG_UART0_MCR + uOffset) | 0x02);
+        else
+            return UART_EIO;
+
+        break;
+
+    case UART_IOC_SETINTERRUPT:
+        if (uArg0 == 1)      /* enable interrupt  */
+            _uartEnableInterrupt(nNum, uArg1);
+        else if (uArg0 == 0) /* disable interrupt */
+            _uartDisableInterrupt(nNum, uArg1);
+        else
+            return UART_EIO;
+
+        break;
+
+    case UART_IOC_SETBREAKCONTROL:
+        uReg = inpw(REG_UART0_LCR + uOffset);
+        if (uArg0 == 1)      /* set break contorl bit  */
+        {
+            uReg |= UART_LCR_BCB_Msk;
+            outpw(REG_UART0_LCR + uOffset, uReg);
+        }
+        else if (uArg0 == 0)    /* clear break contorl bit */
+        {
+            uReg &= ~UART_LCR_BCB_Msk;
+            outpw(REG_UART0_LCR + uOffset, uReg);
+        }
+        else
+            return UART_EIO;
+
+        break;
+
+    case UART_IOC_GETBIISTATE:
+        switch (nNum)
+        {
+        case UART0:
+            *(PUINT32)uArg0 = _uart_cBIIState_0;
+            break;
+        case UART1:
+            *(PUINT32)uArg0 = _uart_cBIIState_1;
+            break;
+        case UART2:
+            *(PUINT32)uArg0 = _uart_cBIIState_2;
+            break;
+        case UART3:
+            *(PUINT32)uArg0 = _uart_cBIIState_3;
+            break;
+        case UART4:
+            *(PUINT32)uArg0 = _uart_cBIIState_4;
+            break;
+        case UART5:
+            *(PUINT32)uArg0 = _uart_cBIIState_5;
+            break;
+        case UART6:
+            *(PUINT32)uArg0 = _uart_cBIIState_6;
+            break;
+        case UART7:
+            *(PUINT32)uArg0 = _uart_cBIIState_7;
+            break;
+        case UART8:
+            *(PUINT32)uArg0 = _uart_cBIIState_8;
+            break;
+        case UART9:
+            *(PUINT32)uArg0 = _uart_cBIIState_9;
+            break;
+        case UARTA:
+            *(PUINT32)uArg0 = _uart_cBIIState_10;
+            break;
+
+        default:
+            break;
+        }
+        break;
+
+    /* H/W S/W flow control function */
+    case UART_IOC_ENABLEHWFLOWCONTROL:
+
+        /* H/W & S/W are alternative */
+        if (_uart_cFlowControlMode == SWFLOWCONTROL)
+            return UART_EIO;
+
+        _uart_cFlowControlMode = HWFLOWCONTROL;
+
+        /* Implement H/W flow control on TX & RX interrupt mode. */
+        //dev->bIsUseUARTTxInt = TRUE;
+        //dev->bIsUseUARTRxInt = TRUE;
+        _uartEnableInterrupt(nNum, UART_IER_RDA_IEN_Msk);
+
+        /*
+            Set up RTS mechanism.
+            In uartReceiveChars(), if uRecCnt >= _uart_nMaxRxBuf then set RTS high to stop RX.
+            In uartReadRxBuf(), if uRecCnt <= _uart_nMinRxBuf then set RTS low to re-start RX.
+        */
+        //_uart_nMaxRxBuf = (UARTRXBUFSIZE[nNum] * 3) / 4;
+        //_uart_nMinRxBuf = UARTRXBUFSIZE[nNum] / 2;
+        //FDEBUG("max[%d] min[%d]\n", _uart_nMaxRxBuf, _uart_nMinRxBuf);
+
+        /* Set RTS high level trigger */
+        outpw(REG_UART0_MCR + uOffset, (inpw(REG_UART0_MCR + uOffset) | UART_RTS_IS_HIGH_LEV_TRG));
+        /* Set RTS high level trigger */
+        outpw(REG_UART0_MSR + uOffset, (inpw(REG_UART0_MSR + uOffset) | UART_CTS_IS_HIGH_LEV_TRG));
+
+        /* Set Auto CTS/RTS */
+        outpw(REG_UART0_IER + uOffset, inpw(REG_UART0_IER + uOffset) | (0x3 << 12));
+
+        /* Enable MODEM status interrupt */
+        //_uartEnableInterrupt(nNum, UART_IER_MODEM_IEN_Msk);
+
+        /*
+            Maintain H/W flow control flag by read Modem Status Register.
+            If CTS high, stop TX.
+            If CTS low, start TX.
+        */
+        //if( inpw(REG_UART0_MSR+uOffset) & 0x10 )  /* CTS external signal is low  */
+        //  _uart_cHWTXStopped = 0;       /* TX started                  */
+        //else                              /* CTS external signal is high */
+        //  _uart_cHWTXStopped = 1;       /* TX stopped                  */
+
+        /* Set RTS as logic 0, RX re-start */
+        //outpb(REG_UART0_MCR+uOffset, inpb(REG_UART0_MCR+uOffset) | 0x02);  /* set RTS signal low  */
+        //_uart_cHWRXStopped = 0;  // RX started
+        break;
+
+    case UART_IOC_DISABLEHWFLOWCONTROL:
+
+        /* Disable MODEM status interrupt */
+        _uartDisableInterrupt(nNum, UART_IER_MODEM_IEN_Msk);
+        _uart_cFlowControlMode = 0;
+        _uart_cHWTXStopped = 0;
+        _uart_cHWRXStopped = 0;
+        break;
+
+    case UART_IOC_FLUSH_TX_BUFFER:
+        dev->uUartTxTail = 0;
+        dev->uUartTxHead = 0;
+        break;
+
+    case UART_IOC_FLUSH_RX_BUFFER:
+        dev->uUartRxTail = 0;
+        dev->uUartRxHead = 0;
+        break;
+
+    case UART_IOC_SET_RS485_MODE:
+        outpw((REG_UART0_FUN_SEL + uOffset), 0x3);
+        outpw((REG_UART0_MCR + uOffset), 0x0);
+        outpw((REG_UART0_LCR + uOffset), (UART_LCR_SPE_Msk | UART_LCR_EPE_Msk | UART_LCR_PBE_Msk | (0x3 << UART_LCR_WLS_Pos)));
+        outpw((REG_UART0_ALT_CSR + uOffset), uArg0 | (uArg1 << UART_ALT_CSR_ADDR_MATCH_Pos));
+        break;
+
+    case UART_IOC_SEND_RS485_ADDRESS:
+
+        while (!((inpw(REG_UART0_FSR + uOffset)) & UART_FSR_TE_FLAG_Msk));
+        uReg = inpw(REG_UART0_LCR + uOffset);
+        outpw((REG_UART0_LCR + uOffset), (UART_LCR_SPE_Msk | UART_LCR_PBE_Msk | (0x3 << UART_LCR_WLS_Pos)));
+        outpw((REG_UART0_THR + uOffset), uArg0);
+        while (!((inpw(REG_UART0_FSR + uOffset)) & UART_FSR_TE_FLAG_Msk));
+
+        outpw((REG_UART0_LCR + uOffset), uReg);
+
+        break;
+
+    case UART_IOC_SET_RS485_RXOFF:
+        uReg = inpw(REG_UART0_FCR + uOffset);
+        if (uArg0 == 1)
+            uReg |= UART_FCR_RX_DIS_Msk;
+        else
+            uReg &= ~UART_FCR_RX_DIS_Msk;
+
+        outpw((REG_UART0_FCR + uOffset), uReg);
+
+        break;
+
+    case UART_IOC_SET_ALTCTL_REG:
+
+        outpw((REG_UART0_ALT_CSR + uOffset), uArg0);
+
+        break;
+
+    case UART_IOC_GET_ALTCTL_REG:
+
+        *(PUINT32)uArg0 = inpw(REG_UART0_ALT_CSR + uOffset);
+
+        break;
+
+    case UART_IOC_SET_LIN_MODE:
+
+        outpw((REG_UART0_FUN_SEL + uOffset), 0x1); // Select LIN function
+
+        /* Select LIN function setting : Tx enable, Rx enable and break field length */
+        uReg = inpw(REG_UART0_ALT_CSR + uOffset);
+        uReg &= ~(UART_ALT_CSR_LIN_TX_EN_Msk | UART_ALT_CSR_LIN_RX_EN_Msk | UART_ALT_CSR_UA_LIN_BKFL_Msk);
+        uReg |= (uArg0 | (uArg1 << UART_ALT_CSR_UA_LIN_BKFL_Pos));
+        outpw((REG_UART0_ALT_CSR + uOffset), uReg);
+
+        break;
+
+    default:
+        return UART_ENOTTY;
+    }
+
+    return Successful;
+}
+
+/**
+  * @brief    Release memory resource, disable interrupt.
+  *
+  * @param[in]    nNum: UART channel. ( UART0 / UART1 / UART2 / UART3 / UART 4 /UART 5 /
+  *                                     UART6 / UART7 / UART8 / UART9 / UARTA )
+  *
+  * @return   UART_ENODEV: UART channel out of range
+  *           UART_EIO: No activated
+  *           Successful: Success
+  */
+INT32 uartRelease(INT nNum)
+{
+    UART_BUFFER_T *dev;
+
+    if ((nNum < UART0) || (nNum > UARTA))
+        return UART_ENODEV;
+
+    dev = (UART_BUFFER_T *) &UART_DEV[nNum];
+
+    /* Check UART initial status */
+    if (dev->bIsUARTInitial == FALSE)
+        return UART_EIO;
+
+    /* Disable all interrupt of the specific UART */
+    _uartDisableInterrupt(nNum, DISABLEALLIER);
+
+    /* Free memory */
+    free(dev->pucUartTxBuf);
+    free(dev->pucUartRxBuf);
+    free(dev->pucUARTFlag);
+
+    /* Initial parameter */
+    dev->bIsUARTInitial = FALSE;  /* it's important */
+
+    return Successful;
+}
+
+/*@}*/ /* end of group N9H30_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_UART_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+#else
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_uart.h"
+
+/**
+ *    @brief        Open and set UART function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The baudrate of UART module.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T *uart, uint32_t u32baudrate)
+{
+    uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
+    //uint32_t u32ClkTbl[4] = {XIN, LXT, ACLK, UCLK};
+    uint32_t u32ClkTbl[4] = {12000000, 0, 75000000, 150000000};
+    uint32_t u32Baud_Div = 0ul;
+
+    if ((uint32_t)uart == UART0_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART1_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UART2_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 21)) >> 21;
+    }
+    else if ((uint32_t)uart == UART3_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 27)) >> 27;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 29)) >> 29;
+    }
+    else if ((uint32_t)uart == UART4_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART5_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UART6_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 21)) >> 21;
+    }
+    else if ((uint32_t)uart == UART7_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 27)) >> 27;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 29)) >> 29;
+    }
+    else if ((uint32_t)uart == UART8_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART9_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UARTA_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 21)) >> 21;
+    }
+
+    /* Select UART function */
+    uart->FUNCSEL = UART_FUNCSEL_UART;
+
+    /* Set UART line configuration */
+    uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+    /* Set UART Rx and RTS trigger level */
+    uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if (u32UartClkSrcSel == 2ul)  // ACLK
+    {
+        //u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    if (u32UartClkSrcSel == 3ul)  // PCLK
+    {
+        //u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if (u32baudrate != 0ul)
+    {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if (u32Baud_Div > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+        }
+    }
+}
+
+void UART_Close(UART_T *uart)
+{
+    uart->INTEN = 0ul;
+}
+
+/**
+ *    @brief        Set UART line configuration
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The register value of baudrate of UART module.
+ *                                  If u32baudrate = 0, UART baudrate will not change.
+ *    @param[in]    u32data_width   The data length of UART module.
+ *                                  - \ref UART_WORD_LEN_5
+ *                                  - \ref UART_WORD_LEN_6
+ *                                  - \ref UART_WORD_LEN_7
+ *                                  - \ref UART_WORD_LEN_8
+ *    @param[in]    u32parity       The parity setting (none/odd/even/mark/space) of UART module.
+ *                                  - \ref UART_PARITY_NONE
+ *                                  - \ref UART_PARITY_ODD
+ *                                  - \ref UART_PARITY_EVEN
+ *                                  - \ref UART_PARITY_MARK
+ *                                  - \ref UART_PARITY_SPACE
+ *    @param[in]    u32stop_bits    The stop bit length (1/1.5/2 bit) of UART module.
+ *                                  - \ref UART_STOP_BIT_1
+ *                                  - \ref UART_STOP_BIT_1_5
+ *                                  - \ref UART_STOP_BIT_2
+ *
+ *    @return       None
+ *
+ *    @details      This function use to config UART line setting.
+ */
+void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
+{
+    uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
+    //uint32_t u32ClkTbl[4] = {XIN, LXT, ACLK, UCLK};
+    uint32_t u32ClkTbl[4] = {12000000, 32768, 75000000, 150000000};
+    uint32_t u32Baud_Div = 0ul;
+
+
+    if ((uint32_t)uart == UART0_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART1_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UART2_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 21)) >> 21;
+    }
+    else if ((uint32_t)uart == UART3_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL4) & (0x3ul << 27)) >> 27;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL4) & (0x7ul << 29)) >> 29;
+    }
+    else if ((uint32_t)uart == UART4_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART5_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UART6_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 21)) >> 21;
+    }
+    else if ((uint32_t)uart == UART7_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL5) & (0x3ul << 27)) >> 27;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL5) & (0x7ul << 29)) >> 29;
+    }
+    else if ((uint32_t)uart == UART8_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 3)) >> 3;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 5)) >> 5;
+    }
+    else if ((uint32_t)uart == UART9_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 11)) >> 11;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 13)) >> 13;
+    }
+    else if ((uint32_t)uart == UARTA_BA)
+    {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (inp32(REG_CLK_DIVCTL6) & (0x3ul << 19)) >> 19;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (inp32(REG_CLK_DIVCTL6) & (0x7ul << 21)) >> 21;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if (u32UartClkSrcSel == 2ul)  // ACLK
+    {
+        //u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    if (u32UartClkSrcSel == 3ul)  // PCLK
+    {
+        //u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if (u32baudrate != 0ul)
+    {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if (u32Baud_Div > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+        }
+    }
+
+    /* Set UART line configuration */
+    uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+#endif
+
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_usbd.c

@@ -0,0 +1,619 @@
+/**************************************************************************//**
+ * @file     usbd.c
+ * @brief    N9H30 USBD driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_usbd.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_USBD_Driver USBD Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+/*--------------------------------------------------------------------------*/
+/// @cond HIDDEN_SYMBOLS
+
+/*!< Global variables for Control Pipe */
+S_USBD_CMD_T gUsbCmd;
+S_USBD_INFO_T *g_usbd_sInfo;
+
+VENDOR_REQ g_usbd_pfnVendorRequest = 0;
+CLASS_REQ g_usbd_pfnClassRequest = 0;
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = 0;
+uint32_t g_u32EpStallLock = 0;       /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+static uint8_t *g_usbd_CtrlInPointer = 0;
+static uint32_t g_usbd_CtrlMaxPktSize = 64;
+static uint8_t g_usbd_UsbConfig = 0;
+static uint8_t g_usbd_UsbAltInterface = 0;
+static uint8_t g_usbd_EnableTestMode = 0;
+static uint8_t g_usbd_TestSelector = 0;
+
+#ifdef __ICCARM__
+    #pragma data_alignment=4
+    static uint8_t g_usbd_buf[12];
+#else
+    static uint8_t g_usbd_buf[12]  __attribute__((aligned(4)));
+#endif
+
+
+uint8_t volatile g_usbd_Configured = 0;
+uint8_t g_usbd_CtrlZero = 0;
+uint8_t g_usbd_UsbAddr = 0;
+uint8_t g_usbd_ShortPacket = 0;
+uint32_t volatile g_usbd_DmaDone = 0;
+uint32_t g_usbd_CtrlInSize = 0;
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ * @brief       USBD Initial
+ *
+ * @param[in]   param               Descriptor
+ * @param[in]   pfnClassReq         Class Request Callback Function
+ * @param[in]   pfnSetInterface     SetInterface Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to initial USBD.
+ */
+void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+    /* Select Vbus detect pin -> GPH0 */
+    outpw(REG_SYS_GPH_MFPL, (inpw(REG_SYS_GPH_MFPL) & ~0xf) | 0x7);
+    /* Enable USB device clock */
+    outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | 0x80000);
+
+    g_usbd_sInfo = param;
+    g_usbd_pfnClassRequest = pfnClassReq;
+    g_usbd_pfnSetInterface = pfnSetInterface;
+
+    /* get EP0 maximum packet size */
+    g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+    /* Initial USB engine */
+    /* Enable PHY */
+    USBD_ENABLE_PHY();
+    /* wait PHY clock ready */
+    while (1)
+    {
+        USBD->EP[EPA].EPMPS = 0x20;
+        if (USBD->EP[EPA].EPMPS == 0x20)
+            break;
+    }
+    /* Force SE0, and then clear it to connect*/
+    USBD_SET_SE0();
+}
+
+/**
+ * @brief       USBD Start
+ *
+ * @return      None
+ *
+ * @details     This function is used to start transfer
+ */
+void USBD_Start(void)
+{
+    USBD_CLR_SE0();
+}
+
+/**
+ * @brief       Process Setup Packet
+ *
+ * @return      None
+ *
+ * @details     This function is used to process Setup packet.
+ */
+void USBD_ProcessSetupPacket(void)
+{
+    // Setup packet process
+    gUsbCmd.bmRequestType = (uint8_t)(USBD->SETUP1_0 & 0xff);
+    gUsbCmd.bRequest = (int8_t)(USBD->SETUP1_0 >> 8) & 0xff;
+    gUsbCmd.wValue = (uint16_t)USBD->SETUP3_2;
+    gUsbCmd.wIndex = (uint16_t)USBD->SETUP5_4;
+    gUsbCmd.wLength = (uint16_t)USBD->SETUP7_6;
+
+    /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */
+    switch (gUsbCmd.bmRequestType & 0x60)
+    {
+    case REQ_STANDARD:   // Standard
+    {
+        USBD_StandardRequest();
+        break;
+    }
+    case REQ_CLASS:   // Class
+    {
+        if (g_usbd_pfnClassRequest != NULL)
+        {
+            g_usbd_pfnClassRequest();
+        }
+        break;
+    }
+    case REQ_VENDOR:   // Vendor
+    {
+        if (g_usbd_pfnVendorRequest != NULL)
+        {
+            g_usbd_pfnVendorRequest();
+        }
+        break;
+    }
+    default:   // reserved
+    {
+        /* Setup error, stall the device */
+        USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
+        break;
+    }
+    }
+}
+
+/**
+ * @brief       Get Descriptor request
+ *
+ * @return      None
+ *
+ * @details     This function is used to process GetDescriptor request.
+ */
+int USBD_GetDescriptor(void)
+{
+    uint32_t u32Len;
+
+    u32Len = gUsbCmd.wLength;
+    g_usbd_CtrlZero = 0;
+
+    switch ((gUsbCmd.wValue & 0xff00) >> 8)
+    {
+    // Get Device Descriptor
+    case DESC_DEVICE:
+    {
+        u32Len = Minimum(u32Len, LEN_DEVICE);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+        break;
+    }
+    // Get Configuration Descriptor
+    case DESC_CONFIG:
+    {
+        uint32_t u32TotalLen;
+
+        u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+        u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+        u32Len = Minimum(u32Len, u32TotalLen);
+        if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
+            g_usbd_CtrlZero = 1;
+
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+        break;
+    }
+    // Get Qualifier Descriptor
+    case DESC_QUALIFIER:
+    {
+        u32Len = Minimum(u32Len, LEN_QUALIFIER);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8QualDesc, u32Len);
+        break;
+    }
+    // Get Other Speed Descriptor - Full speed
+    case DESC_OTHERSPEED:
+    {
+        uint32_t u32TotalLen;
+
+        u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[3];
+        u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[2] + (u32TotalLen << 8);
+
+        u32Len = Minimum(u32Len, u32TotalLen);
+        if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
+            g_usbd_CtrlZero = 1;
+
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8OtherConfigDesc, u32Len);
+        break;
+    }
+    // Get HID Descriptor
+    case DESC_HID:
+    {
+        u32Len = Minimum(u32Len, LEN_HID);
+        USBD_MemCopy(g_usbd_buf, (uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[LEN_CONFIG + LEN_INTERFACE], u32Len);
+        USBD_PrepareCtrlIn(g_usbd_buf, u32Len);
+        break;
+    }
+    // Get Report Descriptor
+    case DESC_HID_RPT:
+    {
+        if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
+            g_usbd_CtrlZero = 1;
+
+        u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xff]);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xff], u32Len);
+        break;
+    }
+    // Get String Descriptor
+    case DESC_STRING:
+    {
+        // Get String Descriptor
+        if ((gUsbCmd.wValue & 0xff) < 4)
+        {
+            u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xff][0]);
+            if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
+                g_usbd_CtrlZero = 1;
+            USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xff], u32Len);
+        }
+        else
+        {
+            USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
+            return 1;
+        }
+        break;
+    }
+    default:
+        // Not support. Reply STALL.
+        USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
+        return 1;
+    }
+    return 0;
+}
+
+
+/**
+ * @brief       Process USB standard request
+ *
+ * @return      None
+ *
+ * @details     This function is used to process USB Standard Request.
+ */
+void USBD_StandardRequest(void)
+{
+    /* clear global variables for new request */
+    g_usbd_CtrlInPointer = 0;
+    g_usbd_CtrlInSize = 0;
+
+    if (gUsbCmd.bmRequestType & 0x80)   /* request data transfer direction */
+    {
+        // Device to host
+        switch (gUsbCmd.bRequest)
+        {
+        case GET_CONFIGURATION:
+        {
+            // Return current configuration setting
+            USBD_PrepareCtrlIn((uint8_t *)&g_usbd_UsbConfig, 1);
+
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        case GET_DESCRIPTOR:
+        {
+            if (!USBD_GetDescriptor())
+            {
+                USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
+                USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
+            }
+            break;
+        }
+        case GET_INTERFACE:
+        {
+            // Return current interface setting
+            USBD_PrepareCtrlIn((uint8_t *)&g_usbd_UsbAltInterface, 1);
+
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        case GET_STATUS:
+        {
+            // Device
+            if (gUsbCmd.bmRequestType == 0x80)
+            {
+                if (g_usbd_sInfo->gu8ConfigDesc[7] & 0x40)
+                    g_usbd_buf[0] = 1; // Self-Powered
+                else
+                    g_usbd_buf[0] = 0; // bus-Powered
+            }
+            // Interface
+            else if (gUsbCmd.bmRequestType == 0x81)
+                g_usbd_buf[0] = 0;
+            // Endpoint
+            else if (gUsbCmd.bmRequestType == 0x82)
+            {
+                uint8_t ep = gUsbCmd.wIndex & 0xF;
+                g_usbd_buf[0] = USBD_GetStall(ep) ? 1 : 0;
+            }
+            g_usbd_buf[1] = 0;
+            USBD_PrepareCtrlIn(g_usbd_buf, 2);
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        default:
+        {
+            /* Setup error, stall the device */
+            USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
+            break;
+        }
+        }
+    }
+    else
+    {
+        // Host to device
+        switch (gUsbCmd.bRequest)
+        {
+        case CLEAR_FEATURE:
+        {
+            if ((gUsbCmd.wValue & 0xff) == FEATURE_ENDPOINT_HALT)
+            {
+
+                int32_t epNum, i;
+
+                /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+                   a flag: g_u32EpStallLock is added to support it */
+                epNum = gUsbCmd.wIndex & 0xF;
+                for (i = 0; i < USBD_MAX_EP; i++)
+                {
+                    if ((((USBD->EP[i].EPCFG & 0xf0) >> 4) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0))
+                    {
+                        USBD->EP[i].EPRSPCTL = (USBD->EP[i].EPRSPCTL & 0xef) | USB_EP_RSPCTL_TOGGLE;
+                    }
+                }
+            }
+            /* Status stage */
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
+            USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_ADDRESS:
+        {
+            g_usbd_UsbAddr = (uint8_t)gUsbCmd.wValue;
+
+            // DATA IN for end of setup
+            /* Status Stage */
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
+            USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_CONFIGURATION:
+        {
+            g_usbd_UsbConfig = (uint8_t)gUsbCmd.wValue;
+            g_usbd_Configured = 1;
+            // DATA IN for end of setup
+            /* Status stage */
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
+            USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_FEATURE:
+        {
+            if ((gUsbCmd.wValue & 0x3) == 2)    /* TEST_MODE*/
+            {
+                g_usbd_EnableTestMode = 1;
+                g_usbd_TestSelector = gUsbCmd.wIndex >> 8;
+            }
+            /* Status stage */
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
+            USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_INTERFACE:
+        {
+            g_usbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue;
+            if (g_usbd_pfnSetInterface != NULL)
+                g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
+            /* Status stage */
+            USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
+            USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+            USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        default:
+        {
+            /* Setup error, stall the device */
+            USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
+            break;
+        }
+        }
+    }
+}
+
+#define TEST_J                  0x01    /*!< TEST J  \hideinitializer */
+#define TEST_K                  0x02    /*!< TEST K  \hideinitializer */
+#define TEST_SE0_NAK            0x03    /*!< TEST SE0  \hideinitializer */
+#define TEST_PACKET             0x04    /*!< TEST Packet  \hideinitializer */
+#define TEST_FORCE_ENABLE       0x05    /*!< TEST Force enable  \hideinitializer */
+
+
+/**
+ * @brief       Update Device State
+ *
+ * @return      None
+ *
+ * @details     This function is used to update Device state when Setup packet complete
+ */
+void USBD_UpdateDeviceState(void)
+{
+    switch (gUsbCmd.bRequest)
+    {
+    case SET_ADDRESS:
+    {
+        USBD_SET_ADDR(g_usbd_UsbAddr);
+        break;
+    }
+    case SET_CONFIGURATION:
+    {
+        if (g_usbd_UsbConfig == 0)
+        {
+            int volatile i;
+            /* Reset PID DATA0 */
+            for (i = 0; i < USBD_MAX_EP; i++)
+            {
+                if (USBD->EP[i].EPCFG & 0x1)
+                {
+                    USBD->EP[i].EPRSPCTL = USB_EP_RSPCTL_TOGGLE;
+                }
+            }
+        }
+        break;
+    }
+    case SET_FEATURE:
+    {
+        if (gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
+            USBD_SetStall(gUsbCmd.wIndex & 0xF);
+        else if (g_usbd_EnableTestMode)
+        {
+            g_usbd_EnableTestMode = 0;
+            if (g_usbd_TestSelector == TEST_J)
+                USBD->TEST = TEST_J;
+            else if (g_usbd_TestSelector == TEST_K)
+                USBD->TEST = TEST_K;
+            else if (g_usbd_TestSelector == TEST_SE0_NAK)
+                USBD->TEST = TEST_SE0_NAK;
+            else if (g_usbd_TestSelector == TEST_PACKET)
+                USBD->TEST = TEST_PACKET;
+            else if (g_usbd_TestSelector == TEST_FORCE_ENABLE)
+                USBD->TEST = TEST_FORCE_ENABLE;
+        }
+        break;
+    }
+    case CLEAR_FEATURE:
+    {
+        if (gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
+            USBD_ClearStall(gUsbCmd.wIndex & 0xF);
+        break;
+    }
+    default:
+        ;
+    }
+}
+
+
+/**
+ * @brief       Prepare Control IN transaction
+ *
+ * @param[in]   pu8Buf      Control IN data pointer
+ * @param[in]   u32Size     IN transfer size
+ *
+ * @return      None
+ *
+ * @details     This function is used to prepare Control IN transfer
+ */
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    g_usbd_CtrlInPointer = pu8Buf;
+    g_usbd_CtrlInSize = u32Size;
+}
+
+
+
+/**
+ * @brief       Start Control IN transfer
+ *
+ * @return      None
+ *
+ * @details     This function is used to start Control IN
+ */
+void USBD_CtrlIn(void)
+{
+    int volatile i;
+    uint32_t volatile count;
+
+    // Process remained data
+    if (g_usbd_CtrlInSize >= g_usbd_CtrlMaxPktSize)
+    {
+        // Data size > MXPLD
+        for (i = 0; i < (g_usbd_CtrlMaxPktSize >> 2); i++, g_usbd_CtrlInPointer += 4)
+            USBD->cep.CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
+        USBD_START_CEP_IN(g_usbd_CtrlMaxPktSize);
+        g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+    }
+    else
+    {
+        // Data size <= MXPLD
+        for (i = 0; i < (g_usbd_CtrlInSize >> 2); i++, g_usbd_CtrlInPointer += 4)
+            USBD->cep.CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
+
+        count = g_usbd_CtrlInSize % 4;
+        for (i = 0; i < count; i++)
+            USBD->cep.CEPDAT_BYTE = *(uint8_t *)(g_usbd_CtrlInPointer + i);
+
+        USBD_START_CEP_IN(g_usbd_CtrlInSize);
+        g_usbd_CtrlInPointer = 0;
+        g_usbd_CtrlInSize = 0;
+    }
+}
+
+/**
+ * @brief       Start Control OUT transaction
+ *
+ * @param[in]   pu8Buf      Control OUT data pointer
+ * @param[in]   u32Size     OUT transfer size
+ *
+ * @return      None
+ *
+ * @details     This function is used to start Control OUT transfer
+ */
+void USBD_CtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    int volatile i;
+
+    while (1)
+    {
+        if (USBD->CEPINTSTS & USBD_CEPINTSTS_RXPKIF_Msk)
+        {
+            for (i = 0; i < u32Size; i++)
+                *(uint8_t *)(pu8Buf + i) = USBD->cep.CEPDAT_BYTE;
+            USBD->CEPINTSTS = USBD_CEPINTSTS_RXPKIF_Msk;
+            break;
+        }
+    }
+}
+
+/**
+ * @brief       Clear all software flags
+ *
+ * @return      None
+ *
+ * @details     This function is used to clear all software control flag
+ */
+void USBD_SwReset(void)
+{
+    // Reset all variables for protocol
+    g_usbd_UsbAddr = 0;
+    g_usbd_DmaDone = 0;
+    g_usbd_ShortPacket = 0;
+    g_usbd_Configured = 0;
+
+    // Reset USB device address
+    USBD_SET_ADDR(0);
+}
+
+/**
+ * @brief       USBD Set Vendor Request
+ *
+ * @param[in]   pfnVendorReq         Vendor Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+    g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+
+/*@}*/ /* end of group N9H30_USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_USBD_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_wdt.c

@@ -0,0 +1,66 @@
+/**************************************************************************//**
+ * @file     wdt.c
+ * @brief    NUC980 series WDT driver source file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "nu_wdt.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize WDT and start counting
+  *
+  * @param[in]  u32TimeoutInterval  Time-out interval period of WDT module. Valid values are:
+  *                                 - \ref WDT_TIMEOUT_2POW4
+  *                                 - \ref WDT_TIMEOUT_2POW6
+  *                                 - \ref WDT_TIMEOUT_2POW8
+  *                                 - \ref WDT_TIMEOUT_2POW10
+  *                                 - \ref WDT_TIMEOUT_2POW12
+  *                                 - \ref WDT_TIMEOUT_2POW14
+  *                                 - \ref WDT_TIMEOUT_2POW16
+  *                                 - \ref WDT_TIMEOUT_2POW18
+  * @param[in]  u32ResetDelay       Configure WDT time-out reset delay period. Valid values are:
+  *                                 - \ref WDT_RESET_DELAY_1026CLK
+  *                                 - \ref WDT_RESET_DELAY_130CLK
+  *                                 - \ref WDT_RESET_DELAY_18CLK
+  *                                 - \ref WDT_RESET_DELAY_3CLK
+  * @param[in]  u32EnableReset      Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+  * @param[in]  u32EnableWakeup     Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+  *             enable or disable WDT time-out reset system or wake-up system.
+  * @note       Please make sure that Register Write-Protection Function has been disabled before using this function.
+  */
+void WDT_Open(UINT32 u32TimeoutInterval,
+              UINT32 u32ResetDelay,
+              UINT32 u32EnableReset,
+              UINT32 u32EnableWakeup)
+{
+
+    outpw(REG_WDT_ALTCTL, u32ResetDelay);
+    outpw(REG_WDT_CTL, u32TimeoutInterval | 0x80 |
+          (u32EnableReset << 1) |
+          (u32EnableWakeup << 4));
+    return;
+}
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+

bsp/nuvoton/libraries/n9h30/Driver/Source/nu_wwdt.c

@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     wwdt.c
+ * @brief    N9H30 WWDT driver source file
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "nu_wwdt.h"
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+  @{
+*/
+
+/** @addtogroup N9H30_WWDT_Driver WWDT Driver
+  @{
+*/
+
+
+/** @addtogroup N9H30_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+
+/**
+ * @brief This function make WWDT module start counting with different counter period and compared window value
+ * @param[in] u32PreScale  Prescale period for the WWDT counter period. Valid values are:
+ *              - \ref WWDT_PRESCALER_1
+ *              - \ref WWDT_PRESCALER_2
+ *              - \ref WWDT_PRESCALER_4
+ *              - \ref WWDT_PRESCALER_8
+ *              - \ref WWDT_PRESCALER_16
+ *              - \ref WWDT_PRESCALER_32
+ *              - \ref WWDT_PRESCALER_64
+ *              - \ref WWDT_PRESCALER_128
+ *              - \ref WWDT_PRESCALER_192
+ *              - \ref WWDT_PRESCALER_256
+ *              - \ref WWDT_PRESCALER_384
+ *              - \ref WWDT_PRESCALER_512
+ *              - \ref WWDT_PRESCALER_768
+ *              - \ref WWDT_PRESCALER_1024
+ *              - \ref WWDT_PRESCALER_1536
+ *              - \ref WWDT_PRESCALER_2048
+ * @param[in] u32CmpValue Window compared value. Valid values are between 0x0 to 0x3F
+ * @param[in] u32EnableInt Enable WWDT interrupt or not. Valid values are \ref TRUE and \ref FALSE
+ * @return None
+ * @note Application can call this function can only once after boot up
+ */
+void WWDT_Open(UINT u32PreScale, UINT u32CmpValue, UINT u32EnableInt)
+{
+    UINT reg;
+    reg = u32PreScale |
+          (u32CmpValue << 16) |
+          0x1 | // enable
+          (u32EnableInt ? 0x2 : 0);
+    outpw(REG_WWDT_CTL, reg);
+
+    return;
+}
+
+
+
+
+/*@}*/ /* end of group N9H30_WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_WWDT_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

bsp/nuvoton/libraries/n9h30/README.md

@@ -0,0 +1,32 @@
+# N9H30 Series
+
+## Supported drivers
+
+| Peripheral | rt_device_class_type | Device name |
+| ------ | ----  | :------:  |
+| ADC | RT_Device_Class_Miscellaneous (ADC) | ***adc*** |
+| ADC_TOUCH | RT_Device_Class_Touch | ***adc_touch*** |
+| CAN | RT_Device_Class_CAN | ***can[0-1]*** |
+| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| EMAC | RT_Device_Class_NetIf | ***e[0-1]*** |
+| ETIMER | RT_Device_Class_Timer | ***etimer[0-3]*** |
+| ETIMER_CAPTURE | RT_Device_Class_Miscellaneous(inputcapture) | ***etmr[0-3]i0*** |
+| GE2D | N/A | ***N/A*** |
+| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** |
+| I2C | RT_Device_Class_I2CBUS | ***i2c[0-1]*** |
+| I2S | RT_Device_Class_Sound | ***sound0*** |
+| JPEGCODEC | N/A | ***N/A*** |
+| PWM | RT_Device_Class_Miscellaneous (PWM) | ***pwm0*** |
+| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** |
+| RTC | RT_Device_Class_RTC | ***rtc*** |
+| SC (UART function) | RT_Device_Class_Char | ***scuart[0-1]*** |
+| SDH | RT_Device_Class_Block | ***sdh[0-1]*** |
+| SOFTI2C | RT_Device_Class_I2CBUS | ***softi2c[0-1]*** |
+| SYS | N/A | ***N/A*** |
+| SYSTICK | N/A | ***N/A*** |
+| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** |
+| UART | RT_Device_Class_Char | ***uart[0-9]*** |
+| USBD | RT_Device_Class_USBDevice | ***usbd*** |
+| USBHOST | RT_Device_Class_USBHost | ***usbh*** |
+| VPOST | RT_Device_Class_Graphic | ***lcd,osd*** |
+| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** |

bsp/nuvoton/libraries/n9h30/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/nuvoton/libraries/n9h30/UsbHostLib/SConscript

@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+group = []
+if GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_USBH'):
+	src = Glob('*src/*.c') + Glob('src/*.cpp')
+	CPPPATH = [cwd + '/inc']
+	group = DefineGroup('n9h30_usbhostlib', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nuvoton/libraries/n9h30/UsbHostLib/inc/config.h

@@ -0,0 +1,1524 @@
+/**************************************************************************//**
+ * @file     config.h
+ * @version  V1.00
+ * @brief    This header file defines the configuration of USB Host library.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef  _USBH_CONFIG_H_
+#define  _USBH_CONFIG_H_
+
+
+/// @cond HIDDEN_SYMBOLS
+
+#include <rtthread.h>
+#include "N9H30.h"
+#include "nu_sys.h"
+#include "drv_sys.h"
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Hardware settings                                                                    */
+/*----------------------------------------------------------------------------------------*/
+#define HCLK_MHZ               300          /* used for loop-delay. must be larger than
+                                               true HCLK clock MHz                        */
+
+#define NON_CACHE_MASK         (0x80000000)
+
+#define ENABLE_OHCI_IRQ()      rt_hw_interrupt_umask(IRQ_OHCI)
+#define DISABLE_OHCI_IRQ()     rt_hw_interrupt_mask(IRQ_OHCI)
+#define IS_OHCI_IRQ_ENABLED()  ((inpw(REG_AIC_IMR)>>OHCI_IRQn) & 0x1)
+#define ENABLE_EHCI_IRQ()      rt_hw_interrupt_umask(IRQ_EHCI)
+#define DISABLE_EHCI_IRQ()     rt_hw_interrupt_mask(IRQ_EHCI)
+#define IS_EHCI_IRQ_ENABLED()  ((inpw(REG_AIC_IMR)>>EHCI_IRQn) & 0x1)
+
+#define ENABLE_OHCI                         /* Enable OHCI host controller                */
+#define ENABLE_EHCI                         /* Enable EHCI host controller                */
+
+#define EHCI_PORT_CNT          2            /* Number of EHCI roothub ports               */
+#define OHCI_PORT_CNT          2            /* Number of OHCI roothub ports               */
+//#define OHCI_PER_PORT_POWER               /* OHCI root hub per port powered             */
+
+#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling
+                                               OHCI isochronous transfer                  */
+
+#define EHCI_ISO_DELAY         2            /* preserved number of frames while
+                                               scheduling EHCI isochronous transfer       */
+
+#define EHCI_ISO_RCLM_RANGE    32           /* When inspecting activated iTD/siTD,
+                                               unconditionally reclaim iTD/isTD scheduled
+                                               in just elapsed EHCI_ISO_RCLM_RANGE ms.    */
+
+#define MAX_DESC_BUFF_SIZE     4096         /* To hold the configuration descriptor, USB
+                                               core will allocate a buffer with this size
+                                               for each connected device. USB core does
+                                               not release it until device disconnected.  */
+
+/*----------------------------------------------------------------------------------------*/
+/*   Memory allocation settings                                                           */
+/*----------------------------------------------------------------------------------------*/
+
+#define STATIC_MEMORY_ALLOC    0       /* pre-allocate static memory blocks. No dynamic memory aloocation.
+                                          But the maximum number of connected devices and transfers are
+                                          limited.  */
+
+#define MAX_UDEV_DRIVER        8       /*!< Maximum number of registered drivers                      */
+#define MAX_ALT_PER_IFACE      12      /*!< maximum number of alternative interfaces per interface    */
+#define MAX_EP_PER_IFACE       8       /*!< maximum number of endpoints per interface                 */
+#define MAX_HUB_DEVICE         8       /*!< Maximum number of hub devices                             */
+
+/* Host controller hardware transfer descriptors memory pool. ED/TD/ITD of OHCI and QH/QTD of EHCI
+   are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE.
+   May allocate one or more units depend on hardware descriptor type.                                 */
+
+#define MEM_POOL_UNIT_SIZE     128     /*!< A fixed hard coding setting. Do not change it!            */
+#define MEM_POOL_UNIT_NUM      256     /*!< Increase this or heap size if memory allocate failed.     */
+
+/*----------------------------------------------------------------------------------------*/
+/*   Re-defined staff for various compiler                                                */
+/*----------------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+    #define   __inline    inline
+#endif
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Debug settings                                                                       */
+/*----------------------------------------------------------------------------------------*/
+#define ENABLE_ERROR_MSG                    /* enable debug messages                      */
+#define ENABLE_DEBUG_MSG                    /* enable debug messages                      */
+//#define ENABLE_VERBOSE_DEBUG              /* verbos debug messages                      */
+//#define DUMP_DESCRIPTOR                   /* dump descriptors                           */
+
+#ifdef ENABLE_ERROR_MSG
+    #define USB_error            rt_kprintf
+#else
+    #define USB_error(...)
+#endif
+
+#ifdef ENABLE_DEBUG_MSG
+    #define USB_debug            rt_kprintf
+    #ifdef ENABLE_VERBOSE_DEBUG
+        #define USB_vdebug          rt_kprintf
+    #else
+        #define USB_vdebug(...)
+    #endif
+#else
+    #define USB_debug(...)
+    #define USB_vdebug(...)
+#endif
+
+
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#define   __IO    volatile             /*!< Defines 'read / write' permissions */
+
+
+//typedef unsigned int     uint32_t;
+//typedef unsigned short   uint16_t;
+//typedef unsigned char    uint8_t;
+
+
+
+/*---------------------- USB Host Controller -------------------------*/
+/**
+    @addtogroup USBH USB Host Controller(USBH)
+    Memory Mapped Structure for USBH Controller
+@{ */
+
+typedef struct
+{
+
+    /**
+     * @var USBH_T::HcRevision
+     * Offset: 0x00  Host Controller Revision Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |REV       |Revision Number
+     * |        |          |Indicates the Open HCI Specification revision number implemented by the Hardware
+     * |        |          |Host Controller supports 1.1 specification.
+     * |        |          |(X.Y = XYh).
+     * @var USBH_T::HcControl
+     * Offset: 0x04  Host Controller Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CBSR      |Control Bulk Service Ratio
+     * |        |          |This specifies the service ratio between Control and Bulk EDs
+     * |        |          |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
+     * |        |          |The internal count will be retained when crossing the frame boundary
+     * |        |          |In case of reset, HCD is responsible for restoring this
+     * |        |          |Value.
+     * |        |          |00 = Number of Control EDs over Bulk EDs served is 1:1.
+     * |        |          |01 = Number of Control EDs over Bulk EDs served is 2:1.
+     * |        |          |10 = Number of Control EDs over Bulk EDs served is 3:1.
+     * |        |          |11 = Number of Control EDs over Bulk EDs served is 4:1.
+     * |[2]     |PLE       |Periodic List Enable Bit
+     * |        |          |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
+     * |        |          |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+     * |        |          |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
+     * |        |          |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+     * |[3]     |IE        |Isochronous List Enable Bit
+     * |        |          |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
+     * |        |          |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+     * |        |          |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
+     * |[4]     |CLE       |Control List Enable Bit
+     * |        |          |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Control list in the next frame Enabled.
+     * |[5]     |BLE       |Bulk List Enable Bit
+     * |        |          |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Bulk list in the next frame Enabled.
+     * |[7:6]   |HCFS      |Host Controller Functional State
+     * |        |          |This field sets the Host Controller state
+     * |        |          |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
+     * |        |          |States are:
+     * |        |          |00 = USBSUSPEND.
+     * |        |          |01 = USBOPERATIONAL.
+     * |        |          |10 = USBRESUME.
+     * |        |          |11 = USBRESET.
+     * @var USBH_T::HcCommandStatus
+     * Offset: 0x08  Host Controller Command Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HCR       |Host Controller Reset
+     * |        |          |This bit is set to initiate the software reset of Host Controller
+     * |        |          |This bit is cleared by the Host Controller, upon completed of the reset operation.
+     * |        |          |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+     * |        |          |0 = Host Controller is not in software reset state.
+     * |        |          |1 = Host Controller is in software reset state.
+     * |[1]     |CLF       |Control List Filled
+     * |        |          |Set high to indicate there is an active TD on the Control List
+     * |        |          |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Control list.
+     * |        |          |1 = An active TD added or found on the Control list.
+     * |[2]     |BLF       |Bulk List Filled
+     * |        |          |Set high to indicate there is an active TD on the Bulk list
+     * |        |          |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+     * |        |          |1 = An active TD added or found on the Bulk list.
+     * |[17:16] |SOC       |Schedule Overrun Count
+     * |        |          |These bits are incremented on each scheduling overrun error
+     * |        |          |It is initialized to 00b and wraps around at 11b
+     * |        |          |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
+     * @var USBH_T::HcInterruptStatus
+     * Offset: 0x0C  Host Controller Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun
+     * |        |          |Set when the List Processor determines a Schedule Overrun has occurred.
+     * |        |          |0 = Schedule Overrun didn't occur.
+     * |        |          |1 = Schedule Overrun has occurred.
+     * |[1]     |WDH       |Write Back Done Head
+     * |        |          |Set after the Host Controller has written HcDoneHead to HccaDoneHead
+     * |        |          |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+     * |        |          |0 =.Host Controller didn't update HccaDoneHead.
+     * |        |          |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
+     * |[2]     |SF        |Start of Frame
+     * |        |          |Set when the Frame Management functional block signals a 'Start of Frame' event
+     * |        |          |Host Control generates a SOF token at the same time.
+     * |        |          |0 =.Not the start of a frame.
+     * |        |          |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
+     * |[3]     |RD        |Resume Detected
+     * |        |          |Set when Host Controller detects resume signaling on a downstream port.
+     * |        |          |0 = No resume signaling detected on a downstream port.
+     * |        |          |1 = Resume signaling detected on a downstream port.
+     * |[5]     |FNO       |Frame Number Overflow
+     * |        |          |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |        |          |0 = The bit 15 of Frame Number didn't change.
+     * |        |          |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |[6]     |RHSC      |Root Hub Status Change
+     * |        |          |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * |        |          |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
+     * |        |          |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * @var USBH_T::HcInterruptEnable
+     * Offset: 0x10  Host Controller Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Enable Bit
+     * |        |          |This bit is a global interrupt enable
+     * |        |          |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcInterruptDisable
+     * Offset: 0x14  Host Controller Interrupt Disable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Disable Bit
+     * |        |          |Global interrupt disable. Writing '1' to disable all interrupts.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcHCCA
+     * Offset: 0x18  Host Controller Communication Area Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:8]  |HCCA      |Host Controller Communication Area
+     * |        |          |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
+     * @var USBH_T::HcPeriodCurrentED
+     * Offset: 0x1C  Host Controller Period Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |PCED      |Periodic Current ED
+     * |        |          |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+     * @var USBH_T::HcControlHeadED
+     * Offset: 0x20  Host Controller Control Head ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CHED      |Control Head ED
+     * |        |          |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcControlCurrentED
+     * Offset: 0x24  Host Controller Control Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CCED      |Control Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcBulkHeadED
+     * Offset: 0x28  Host Controller Bulk Head ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BHED      |Bulk Head ED
+     * |        |          |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+     * @var USBH_T::HcBulkCurrentED
+     * Offset: 0x2C  Host Controller Bulk Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BCED      |Bulk Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+     * @var USBH_T::HcDoneHead
+     * Offset: 0x30  Host Controller Done Head Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |DH        |Done Head
+     * |        |          |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+     * @var USBH_T::HcFmInterval
+     * Offset: 0x34  Host Controller Frame Interval Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FI        |Frame Interval
+     * |        |          |This field specifies the length of a frame as (bit times - 1)
+     * |        |          |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+     * |[30:16] |FSMPS     |FS Largest Data Packet
+     * |        |          |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+     * |[31]    |FIT       |Frame Interval Toggle
+     * |        |          |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
+     * |        |          |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
+     * |        |          |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
+     * @var USBH_T::HcFmRemaining
+     * Offset: 0x38  Host Controller Frame Remaining Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FR        |Frame Remaining
+     * |        |          |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
+     * |        |          |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
+     * |        |          |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+     * |[31]    |FRT       |Frame Remaining Toggle
+     * |        |          |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
+     * @var USBH_T::HcFmNumber
+     * Offset: 0x3C  Host Controller Frame Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FN        |Frame Number
+     * |        |          |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
+     * |        |          |The count rolls over from 'FFFFh' to '0h.'
+     * @var USBH_T::HcPeriodicStart
+     * Offset: 0x40  Host Controller Periodic Start Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |PS        |Periodic Start
+     * |        |          |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+     * @var USBH_T::HcLSThreshold
+     * Offset: 0x44  Host Controller Low-speed Threshold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |LST       |Low-speed Threshold
+     * |        |          |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
+     * |        |          |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
+     * |        |          |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+     * @var USBH_T::HcRhDescriptorA
+     * Offset: 0x48  Host Controller Root Hub Descriptor A Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |NDP       |Number Downstream Ports
+     * |        |          |USB host control supports two downstream ports and only one port is available in this series of chip.
+     * |[8]     |PSM       |Power Switching Mode
+     * |        |          |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+     * |        |          |0 = Global Switching.
+     * |        |          |1 = Individual Switching.
+     * |[11]    |OCPM      |over Current Protection Mode
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported
+     * |        |          |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
+     * |        |          |0 = Global Over current.
+     * |        |          |1 = Individual Over current.
+     * |[12]    |NOCP      |No over Current Protection
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported.
+     * |        |          |0 = Over current status is reported.
+     * |        |          |1 = Over current status is not reported.
+     * @var USBH_T::HcRhDescriptorB
+     * Offset: 0x4C  Host Controller Root Hub Descriptor B Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:16] |PPCM      |Port Power Control Mask
+     * |        |          |Global power switching
+     * |        |          |This field is only valid if PowerSwitchingMode is set (individual port switching)
+     * |        |          |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
+     * |        |          |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
+     * |        |          |0 = Port power controlled by global power switching.
+     * |        |          |1 = Port power controlled by port power switching.
+     * |        |          |Note: PPCM[15:2] and PPCM[0] are reserved.
+     * @var USBH_T::HcRhStatus
+     * Offset: 0x50  Host Controller Root Hub Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LPS       |Clear Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear global power.
+     * |[1]     |OCI       |over Current Indicator
+     * |        |          |This bit reflects the state of the over current status pin
+     * |        |          |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[15]    |DRWE      |Device Remote Wakeup Enable Bit
+     * |        |          |This bit controls if port's Connect Status Change as a remote wake-up event.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Connect Status Change as a remote wake-up event Disabled.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |[16]    |LPSC      |Set Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set global power.
+     * |[17]    |OCIC      |over Current Indicator Change
+     * |        |          |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = OCI (HcRhStatus[1]) didn't change.
+     * |        |          |1 = OCI (HcRhStatus[1]) change.
+     * |[31]    |CRWE      |Clear Remote Wake-up Enable Bit
+     * |        |          |This bit is use to clear DRWE (HcRhStatus[15]).
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear DRWE (HcRhStatus[15]).
+     * @var USBH_T::HcRhPortStatus[2]
+     * Offset: 0x54  Host Controller Root Hub Port Status
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCS       |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = No device connected.
+     * |        |          |1 = Device connected.
+     * |[1]     |PES       |Port Enable Status
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port Disabled.
+     * |        |          |1 = Port Enabled.
+     * |[2]     |PSS       |Port Suspend Status
+     * |        |          |This bit indicates the port is suspended
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port is not suspended.
+     * |        |          |1 = Port is selectively suspended.
+     * |[3]     |POCI      |Port over Current Indicator (Read) or Clear Port Suspend (Write)
+     * |        |          |This bit reflects the state of the over current status pin dedicated to this port
+     * |        |          |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
+     * |        |          |This bit is also used to initiate the selective result sequence for the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[4]     |PRS       |Port Reset Status
+     * |        |          |This bit reflects the reset state of the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port reset.
+     * |        |          |Read Operation
+     * |        |          |0 = Port reset signal is not active.
+     * |        |          |1 = Port reset signal is active.
+     * |[8]     |PPS       |Port Power Status
+     * |        |          |This bit reflects the power state of the port regardless of the power switching mode.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Port Power Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port power is Disabled.
+     * |        |          |1 = Port power is Enabled.
+     * |[9]     |LSDA      |Low Speed Device Attached (Read) or Clear Port Power (Write)
+     * |        |          |This bit defines the speed (and bud idle) of the attached device
+     * |        |          |It is only valid when CCS (HcRhPortStatus1[0]) is set.
+     * |        |          |This bit is also used to clear port power.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear PPS (HcRhPortStatus1[8]).
+     * |        |          |Read Operation:
+     * |        |          |0 = Full Speed device.
+     * |        |          |1 = Low-speed device.
+     * |[16]    |CSC       |Connect Status Change
+     * |        |          |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
+     * |        |          |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
+     * |[17]    |PESC      |Port Enable Status Change
+     * |        |          |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = PES (HcRhPortStatus1[1]) didn't change.
+     * |        |          |1 = PES (HcRhPortStatus1[1]) changed.
+     * |[18]    |PSSC      |Port Suspend Status Change
+     * |        |          |This bit indicates the completion of the selective resume sequence for the port.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port resume is not completed.
+     * |        |          |1 = Port resume completed.
+     * |[19]    |OCIC      |Port over Current Indicator Change
+     * |        |          |This bit is set when POCI (HcRhPortStatus1[3]) changes.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = POCI (HcRhPortStatus1[3]) didn't change.
+     * |        |          |1 = POCI (HcRhPortStatus1[3]) changes.
+     * |[20]    |PRSC      |Port Reset Status Change
+     * |        |          |This bit indicates that the port reset signal has completed.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port reset is not complete.
+     * |        |          |1 = Port reset is complete.
+     * @var USBH_T::HcPhyControl
+     * Offset: 0x200  Host Controller PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[27]    |STBYEN    |USB Transceiver Standby Enable Bit
+     * |        |          |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+     * |        |          |0 = The USB transceiver would never enter the standby mode.
+     * |        |          |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+     * @var USBH_T::HcMiscControl
+     * Offset: 0x204  Host Controller Miscellaneous Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |ABORT     |AHB Bus ERROR Response
+     * |        |          |This bit indicates there is an ERROR response received in AHB bus.
+     * |        |          |0 = No ERROR response received.
+     * |        |          |1 = ERROR response received.
+     * |[3]     |OCAL      |over Current Active Low
+     * |        |          |This bit controls the polarity of over current flag from external power IC.
+     * |        |          |0 = Over current flag is high active.
+     * |        |          |1 = Over current flag is low active.
+     * |[16]    |DPRT1     |Disable Port 1
+     * |        |          |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
+     * |        |          |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+     * |        |          |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+     * |        |          |0 = The connection between USB host controller and transceiver of port 1 Enabled.
+     * |        |          |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
+     */
+    __I  uint32_t HcRevision;            /*!< [0x0000] Host Controller Revision Register                                */
+    __IO uint32_t HcControl;             /*!< [0x0004] Host Controller Control Register                                 */
+    __IO uint32_t HcCommandStatus;       /*!< [0x0008] Host Controller Command Status Register                          */
+    __IO uint32_t HcInterruptStatus;     /*!< [0x000c] Host Controller Interrupt Status Register                        */
+    __IO uint32_t HcInterruptEnable;     /*!< [0x0010] Host Controller Interrupt Enable Register                        */
+    __IO uint32_t HcInterruptDisable;    /*!< [0x0014] Host Controller Interrupt Disable Register                       */
+    __IO uint32_t HcHCCA;                /*!< [0x0018] Host Controller Communication Area Register                      */
+    __IO uint32_t HcPeriodCurrentED;     /*!< [0x001c] Host Controller Period Current ED Register                       */
+    __IO uint32_t HcControlHeadED;       /*!< [0x0020] Host Controller Control Head ED Register                         */
+    __IO uint32_t HcControlCurrentED;    /*!< [0x0024] Host Controller Control Current ED Register                      */
+    __IO uint32_t HcBulkHeadED;          /*!< [0x0028] Host Controller Bulk Head ED Register                            */
+    __IO uint32_t HcBulkCurrentED;       /*!< [0x002c] Host Controller Bulk Current ED Register                         */
+    __IO uint32_t HcDoneHead;            /*!< [0x0030] Host Controller Done Head Register                               */
+    __IO uint32_t HcFmInterval;          /*!< [0x0034] Host Controller Frame Interval Register                          */
+    __I  uint32_t HcFmRemaining;         /*!< [0x0038] Host Controller Frame Remaining Register                         */
+    __I  uint32_t HcFmNumber;            /*!< [0x003c] Host Controller Frame Number Register                            */
+    __IO uint32_t HcPeriodicStart;       /*!< [0x0040] Host Controller Periodic Start Register                          */
+    __IO uint32_t HcLSThreshold;         /*!< [0x0044] Host Controller Low-speed Threshold Register                     */
+    __IO uint32_t HcRhDescriptorA;       /*!< [0x0048] Host Controller Root Hub Descriptor A Register                   */
+    __IO uint32_t HcRhDescriptorB;       /*!< [0x004c] Host Controller Root Hub Descriptor B Register                   */
+    __IO uint32_t HcRhStatus;            /*!< [0x0050] Host Controller Root Hub Status Register                         */
+    __IO uint32_t HcRhPortStatus[2];     /*!< [0x0054] Host Controller Root Hub Port Status [1]                         */
+    __I  uint32_t RESERVE0[105];
+    __IO uint32_t HcPhyControl;          /*!< [0x0200] Host Controller PHY Control Register                             */
+    __IO uint32_t HcMiscControl;         /*!< [0x0204] Host Controller Miscellaneous Control Register                   */
+
+} USBH_T;
+
+/**
+    @addtogroup USBH_CONST USBH Bit Field Definition
+    Constant Definitions for USBH Controller
+@{ */
+
+#define USBH_HcRevision_REV_Pos          (0)                                               /*!< USBH_T::HcRevision: REV Position       */
+#define USBH_HcRevision_REV_Msk          (0xfful << USBH_HcRevision_REV_Pos)               /*!< USBH_T::HcRevision: REV Mask           */
+
+#define USBH_HcControl_CBSR_Pos          (0)                                               /*!< USBH_T::HcControl: CBSR Position       */
+#define USBH_HcControl_CBSR_Msk          (0x3ul << USBH_HcControl_CBSR_Pos)                /*!< USBH_T::HcControl: CBSR Mask           */
+
+#define USBH_HcControl_PLE_Pos           (2)                                               /*!< USBH_T::HcControl: PLE Position        */
+#define USBH_HcControl_PLE_Msk           (0x1ul << USBH_HcControl_PLE_Pos)                 /*!< USBH_T::HcControl: PLE Mask            */
+
+#define USBH_HcControl_IE_Pos            (3)                                               /*!< USBH_T::HcControl: IE Position         */
+#define USBH_HcControl_IE_Msk            (0x1ul << USBH_HcControl_IE_Pos)                  /*!< USBH_T::HcControl: IE Mask             */
+
+#define USBH_HcControl_CLE_Pos           (4)                                               /*!< USBH_T::HcControl: CLE Position        */
+#define USBH_HcControl_CLE_Msk           (0x1ul << USBH_HcControl_CLE_Pos)                 /*!< USBH_T::HcControl: CLE Mask            */
+
+#define USBH_HcControl_BLE_Pos           (5)                                               /*!< USBH_T::HcControl: BLE Position        */
+#define USBH_HcControl_BLE_Msk           (0x1ul << USBH_HcControl_BLE_Pos)                 /*!< USBH_T::HcControl: BLE Mask            */
+
+#define USBH_HcControl_HCFS_Pos          (6)                                               /*!< USBH_T::HcControl: HCFS Position       */
+#define USBH_HcControl_HCFS_Msk          (0x3ul << USBH_HcControl_HCFS_Pos)                /*!< USBH_T::HcControl: HCFS Mask           */
+
+#define USBH_HcCommandStatus_HCR_Pos     (0)                                               /*!< USBH_T::HcCommandStatus: HCR Position  */
+#define USBH_HcCommandStatus_HCR_Msk     (0x1ul << USBH_HcCommandStatus_HCR_Pos)           /*!< USBH_T::HcCommandStatus: HCR Mask      */
+
+#define USBH_HcCommandStatus_CLF_Pos     (1)                                               /*!< USBH_T::HcCommandStatus: CLF Position  */
+#define USBH_HcCommandStatus_CLF_Msk     (0x1ul << USBH_HcCommandStatus_CLF_Pos)           /*!< USBH_T::HcCommandStatus: CLF Mask      */
+
+#define USBH_HcCommandStatus_BLF_Pos     (2)                                               /*!< USBH_T::HcCommandStatus: BLF Position  */
+#define USBH_HcCommandStatus_BLF_Msk     (0x1ul << USBH_HcCommandStatus_BLF_Pos)           /*!< USBH_T::HcCommandStatus: BLF Mask      */
+
+#define USBH_HcCommandStatus_SOC_Pos     (16)                                              /*!< USBH_T::HcCommandStatus: SOC Position  */
+#define USBH_HcCommandStatus_SOC_Msk     (0x3ul << USBH_HcCommandStatus_SOC_Pos)           /*!< USBH_T::HcCommandStatus: SOC Mask      */
+
+#define USBH_HcInterruptStatus_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptStatus: SO Position */
+#define USBH_HcInterruptStatus_SO_Msk    (0x1ul << USBH_HcInterruptStatus_SO_Pos)          /*!< USBH_T::HcInterruptStatus: SO Mask     */
+
+#define USBH_HcInterruptStatus_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptStatus: WDH Position*/
+#define USBH_HcInterruptStatus_WDH_Msk   (0x1ul << USBH_HcInterruptStatus_WDH_Pos)         /*!< USBH_T::HcInterruptStatus: WDH Mask    */
+
+#define USBH_HcInterruptStatus_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptStatus: SF Position */
+#define USBH_HcInterruptStatus_SF_Msk    (0x1ul << USBH_HcInterruptStatus_SF_Pos)          /*!< USBH_T::HcInterruptStatus: SF Mask     */
+
+#define USBH_HcInterruptStatus_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptStatus: RD Position */
+#define USBH_HcInterruptStatus_RD_Msk    (0x1ul << USBH_HcInterruptStatus_RD_Pos)          /*!< USBH_T::HcInterruptStatus: RD Mask     */
+
+#define USBH_HcInterruptStatus_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptStatus: FNO Position*/
+#define USBH_HcInterruptStatus_FNO_Msk   (0x1ul << USBH_HcInterruptStatus_FNO_Pos)         /*!< USBH_T::HcInterruptStatus: FNO Mask    */
+
+#define USBH_HcInterruptStatus_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptStatus: RHSC Position*/
+#define USBH_HcInterruptStatus_RHSC_Msk  (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)        /*!< USBH_T::HcInterruptStatus: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptEnable: SO Position */
+#define USBH_HcInterruptEnable_SO_Msk    (0x1ul << USBH_HcInterruptEnable_SO_Pos)          /*!< USBH_T::HcInterruptEnable: SO Mask     */
+
+#define USBH_HcInterruptEnable_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptEnable: WDH Position*/
+#define USBH_HcInterruptEnable_WDH_Msk   (0x1ul << USBH_HcInterruptEnable_WDH_Pos)         /*!< USBH_T::HcInterruptEnable: WDH Mask    */
+
+#define USBH_HcInterruptEnable_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptEnable: SF Position */
+#define USBH_HcInterruptEnable_SF_Msk    (0x1ul << USBH_HcInterruptEnable_SF_Pos)          /*!< USBH_T::HcInterruptEnable: SF Mask     */
+
+#define USBH_HcInterruptEnable_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptEnable: RD Position */
+#define USBH_HcInterruptEnable_RD_Msk    (0x1ul << USBH_HcInterruptEnable_RD_Pos)          /*!< USBH_T::HcInterruptEnable: RD Mask     */
+
+#define USBH_HcInterruptEnable_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptEnable: FNO Position*/
+#define USBH_HcInterruptEnable_FNO_Msk   (0x1ul << USBH_HcInterruptEnable_FNO_Pos)         /*!< USBH_T::HcInterruptEnable: FNO Mask    */
+
+#define USBH_HcInterruptEnable_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptEnable: RHSC Position*/
+#define USBH_HcInterruptEnable_RHSC_Msk  (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)        /*!< USBH_T::HcInterruptEnable: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_MIE_Pos   (31)                                              /*!< USBH_T::HcInterruptEnable: MIE Position*/
+#define USBH_HcInterruptEnable_MIE_Msk   (0x1ul << USBH_HcInterruptEnable_MIE_Pos)         /*!< USBH_T::HcInterruptEnable: MIE Mask    */
+
+#define USBH_HcInterruptDisable_SO_Pos   (0)                                               /*!< USBH_T::HcInterruptDisable: SO Position*/
+#define USBH_HcInterruptDisable_SO_Msk   (0x1ul << USBH_HcInterruptDisable_SO_Pos)         /*!< USBH_T::HcInterruptDisable: SO Mask    */
+
+#define USBH_HcInterruptDisable_WDH_Pos  (1)                                               /*!< USBH_T::HcInterruptDisable: WDH Position*/
+#define USBH_HcInterruptDisable_WDH_Msk  (0x1ul << USBH_HcInterruptDisable_WDH_Pos)        /*!< USBH_T::HcInterruptDisable: WDH Mask   */
+
+#define USBH_HcInterruptDisable_SF_Pos   (2)                                               /*!< USBH_T::HcInterruptDisable: SF Position*/
+#define USBH_HcInterruptDisable_SF_Msk   (0x1ul << USBH_HcInterruptDisable_SF_Pos)         /*!< USBH_T::HcInterruptDisable: SF Mask    */
+
+#define USBH_HcInterruptDisable_RD_Pos   (3)                                               /*!< USBH_T::HcInterruptDisable: RD Position*/
+#define USBH_HcInterruptDisable_RD_Msk   (0x1ul << USBH_HcInterruptDisable_RD_Pos)         /*!< USBH_T::HcInterruptDisable: RD Mask    */
+
+#define USBH_HcInterruptDisable_FNO_Pos  (5)                                               /*!< USBH_T::HcInterruptDisable: FNO Position*/
+#define USBH_HcInterruptDisable_FNO_Msk  (0x1ul << USBH_HcInterruptDisable_FNO_Pos)        /*!< USBH_T::HcInterruptDisable: FNO Mask   */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6)                                               /*!< USBH_T::HcInterruptDisable: RHSC Position*/
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)       /*!< USBH_T::HcInterruptDisable: RHSC Mask  */
+
+#define USBH_HcInterruptDisable_MIE_Pos  (31)                                              /*!< USBH_T::HcInterruptDisable: MIE Position*/
+#define USBH_HcInterruptDisable_MIE_Msk  (0x1ul << USBH_HcInterruptDisable_MIE_Pos)        /*!< USBH_T::HcInterruptDisable: MIE Mask   */
+
+#define USBH_HcHCCA_HCCA_Pos             (8)                                               /*!< USBH_T::HcHCCA: HCCA Position          */
+#define USBH_HcHCCA_HCCA_Msk             (0xfffffful << USBH_HcHCCA_HCCA_Pos)              /*!< USBH_T::HcHCCA: HCCA Mask              */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos  (4)                                               /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
+#define USBH_HcPeriodCurrentED_PCED_Msk  (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)  /*!< USBH_T::HcPeriodCurrentED: PCED Mask   */
+
+#define USBH_HcControlHeadED_CHED_Pos    (4)                                               /*!< USBH_T::HcControlHeadED: CHED Position */
+#define USBH_HcControlHeadED_CHED_Msk    (0xffffffful << USBH_HcControlHeadED_CHED_Pos)    /*!< USBH_T::HcControlHeadED: CHED Mask     */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4)                                               /*!< USBH_T::HcControlCurrentED: CCED Position*/
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask  */
+
+#define USBH_HcBulkHeadED_BHED_Pos       (4)                                               /*!< USBH_T::HcBulkHeadED: BHED Position    */
+#define USBH_HcBulkHeadED_BHED_Msk       (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)       /*!< USBH_T::HcBulkHeadED: BHED Mask        */
+
+#define USBH_HcBulkCurrentED_BCED_Pos    (4)                                               /*!< USBH_T::HcBulkCurrentED: BCED Position */
+#define USBH_HcBulkCurrentED_BCED_Msk    (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)    /*!< USBH_T::HcBulkCurrentED: BCED Mask     */
+
+#define USBH_HcDoneHead_DH_Pos           (4)                                               /*!< USBH_T::HcDoneHead: DH Position        */
+#define USBH_HcDoneHead_DH_Msk           (0xffffffful << USBH_HcDoneHead_DH_Pos)           /*!< USBH_T::HcDoneHead: DH Mask            */
+
+#define USBH_HcFmInterval_FI_Pos         (0)                                               /*!< USBH_T::HcFmInterval: FI Position      */
+#define USBH_HcFmInterval_FI_Msk         (0x3ffful << USBH_HcFmInterval_FI_Pos)            /*!< USBH_T::HcFmInterval: FI Mask          */
+
+#define USBH_HcFmInterval_FSMPS_Pos      (16)                                              /*!< USBH_T::HcFmInterval: FSMPS Position   */
+#define USBH_HcFmInterval_FSMPS_Msk      (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)         /*!< USBH_T::HcFmInterval: FSMPS Mask       */
+
+#define USBH_HcFmInterval_FIT_Pos        (31)                                              /*!< USBH_T::HcFmInterval: FIT Position     */
+#define USBH_HcFmInterval_FIT_Msk        (0x1ul << USBH_HcFmInterval_FIT_Pos)              /*!< USBH_T::HcFmInterval: FIT Mask         */
+
+#define USBH_HcFmRemaining_FR_Pos        (0)                                               /*!< USBH_T::HcFmRemaining: FR Position     */
+#define USBH_HcFmRemaining_FR_Msk        (0x3ffful << USBH_HcFmRemaining_FR_Pos)           /*!< USBH_T::HcFmRemaining: FR Mask         */
+
+#define USBH_HcFmRemaining_FRT_Pos       (31)                                              /*!< USBH_T::HcFmRemaining: FRT Position    */
+#define USBH_HcFmRemaining_FRT_Msk       (0x1ul << USBH_HcFmRemaining_FRT_Pos)             /*!< USBH_T::HcFmRemaining: FRT Mask        */
+
+#define USBH_HcFmNumber_FN_Pos           (0)                                               /*!< USBH_T::HcFmNumber: FN Position        */
+#define USBH_HcFmNumber_FN_Msk           (0xfffful << USBH_HcFmNumber_FN_Pos)              /*!< USBH_T::HcFmNumber: FN Mask            */
+
+#define USBH_HcPeriodicStart_PS_Pos      (0)                                               /*!< USBH_T::HcPeriodicStart: PS Position   */
+#define USBH_HcPeriodicStart_PS_Msk      (0x3ffful << USBH_HcPeriodicStart_PS_Pos)         /*!< USBH_T::HcPeriodicStart: PS Mask       */
+
+#define USBH_HcLSThreshold_LST_Pos       (0)                                               /*!< USBH_T::HcLSThreshold: LST Position    */
+#define USBH_HcLSThreshold_LST_Msk       (0xffful << USBH_HcLSThreshold_LST_Pos)           /*!< USBH_T::HcLSThreshold: LST Mask        */
+
+#define USBH_HcRhDescriptorA_NDP_Pos     (0)                                               /*!< USBH_T::HcRhDescriptorA: NDP Position  */
+#define USBH_HcRhDescriptorA_NDP_Msk     (0xfful << USBH_HcRhDescriptorA_NDP_Pos)          /*!< USBH_T::HcRhDescriptorA: NDP Mask      */
+
+#define USBH_HcRhDescriptorA_PSM_Pos     (8)                                               /*!< USBH_T::HcRhDescriptorA: PSM Position  */
+#define USBH_HcRhDescriptorA_PSM_Msk     (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)           /*!< USBH_T::HcRhDescriptorA: PSM Mask      */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos    (11)                                              /*!< USBH_T::HcRhDescriptorA: OCPM Position */
+#define USBH_HcRhDescriptorA_OCPM_Msk    (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)          /*!< USBH_T::HcRhDescriptorA: OCPM Mask     */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos    (12)                                              /*!< USBH_T::HcRhDescriptorA: NOCP Position */
+#define USBH_HcRhDescriptorA_NOCP_Msk    (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)          /*!< USBH_T::HcRhDescriptorA: NOCP Mask     */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos    (16)                                              /*!< USBH_T::HcRhDescriptorB: PPCM Position */
+#define USBH_HcRhDescriptorB_PPCM_Msk    (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)       /*!< USBH_T::HcRhDescriptorB: PPCM Mask     */
+
+#define USBH_HcRhStatus_LPS_Pos          (0)                                               /*!< USBH_T::HcRhStatus: LPS Position       */
+#define USBH_HcRhStatus_LPS_Msk          (0x1ul << USBH_HcRhStatus_LPS_Pos)                /*!< USBH_T::HcRhStatus: LPS Mask           */
+
+#define USBH_HcRhStatus_OCI_Pos          (1)                                               /*!< USBH_T::HcRhStatus: OCI Position       */
+#define USBH_HcRhStatus_OCI_Msk          (0x1ul << USBH_HcRhStatus_OCI_Pos)                /*!< USBH_T::HcRhStatus: OCI Mask           */
+
+#define USBH_HcRhStatus_DRWE_Pos         (15)                                              /*!< USBH_T::HcRhStatus: DRWE Position      */
+#define USBH_HcRhStatus_DRWE_Msk         (0x1ul << USBH_HcRhStatus_DRWE_Pos)               /*!< USBH_T::HcRhStatus: DRWE Mask          */
+
+#define USBH_HcRhStatus_LPSC_Pos         (16)                                              /*!< USBH_T::HcRhStatus: LPSC Position      */
+#define USBH_HcRhStatus_LPSC_Msk         (0x1ul << USBH_HcRhStatus_LPSC_Pos)               /*!< USBH_T::HcRhStatus: LPSC Mask          */
+
+#define USBH_HcRhStatus_OCIC_Pos         (17)                                              /*!< USBH_T::HcRhStatus: OCIC Position      */
+#define USBH_HcRhStatus_OCIC_Msk         (0x1ul << USBH_HcRhStatus_OCIC_Pos)               /*!< USBH_T::HcRhStatus: OCIC Mask          */
+
+#define USBH_HcRhStatus_CRWE_Pos         (31)                                              /*!< USBH_T::HcRhStatus: CRWE Position      */
+#define USBH_HcRhStatus_CRWE_Msk         (0x1ul << USBH_HcRhStatus_CRWE_Pos)               /*!< USBH_T::HcRhStatus: CRWE Mask          */
+
+#define USBH_HcRhPortStatus_CCS_Pos      (0)                                               /*!< USBH_T::HcRhPortStatus1: CCS Position  */
+#define USBH_HcRhPortStatus_CCS_Msk      (0x1ul << USBH_HcRhPortStatus_CCS_Pos)            /*!< USBH_T::HcRhPortStatus1: CCS Mask      */
+
+#define USBH_HcRhPortStatus_PES_Pos      (1)                                               /*!< USBH_T::HcRhPortStatus1: PES Position  */
+#define USBH_HcRhPortStatus_PES_Msk      (0x1ul << USBH_HcRhPortStatus_PES_Pos)            /*!< USBH_T::HcRhPortStatus1: PES Mask      */
+
+#define USBH_HcRhPortStatus_PSS_Pos      (2)                                               /*!< USBH_T::HcRhPortStatus1: PSS Position  */
+#define USBH_HcRhPortStatus_PSS_Msk      (0x1ul << USBH_HcRhPortStatus_PSS_Pos)            /*!< USBH_T::HcRhPortStatus1: PSS Mask      */
+
+#define USBH_HcRhPortStatus_POCI_Pos     (3)                                               /*!< USBH_T::HcRhPortStatus1: POCI Position */
+#define USBH_HcRhPortStatus_POCI_Msk     (0x1ul << USBH_HcRhPortStatus_POCI_Pos)           /*!< USBH_T::HcRhPortStatus1: POCI Mask     */
+
+#define USBH_HcRhPortStatus_PRS_Pos      (4)                                               /*!< USBH_T::HcRhPortStatus1: PRS Position  */
+#define USBH_HcRhPortStatus_PRS_Msk      (0x1ul << USBH_HcRhPortStatus_PRS_Pos)            /*!< USBH_T::HcRhPortStatus1: PRS Mask      */
+
+#define USBH_HcRhPortStatus_PPS_Pos      (8)                                               /*!< USBH_T::HcRhPortStatus1: PPS Position  */
+#define USBH_HcRhPortStatus_PPS_Msk      (0x1ul << USBH_HcRhPortStatus_PPS_Pos)            /*!< USBH_T::HcRhPortStatus1: PPS Mask      */
+
+#define USBH_HcRhPortStatus_LSDA_Pos     (9)                                               /*!< USBH_T::HcRhPortStatus1: LSDA Position */
+#define USBH_HcRhPortStatus_LSDA_Msk     (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)           /*!< USBH_T::HcRhPortStatus1: LSDA Mask     */
+
+#define USBH_HcRhPortStatus_CSC_Pos      (16)                                              /*!< USBH_T::HcRhPortStatus1: CSC Position  */
+#define USBH_HcRhPortStatus_CSC_Msk      (0x1ul << USBH_HcRhPortStatus_CSC_Pos)            /*!< USBH_T::HcRhPortStatus1: CSC Mask      */
+
+#define USBH_HcRhPortStatus_PESC_Pos     (17)                                              /*!< USBH_T::HcRhPortStatus1: PESC Position */
+#define USBH_HcRhPortStatus_PESC_Msk     (0x1ul << USBH_HcRhPortStatus_PESC_Pos)           /*!< USBH_T::HcRhPortStatus1: PESC Mask     */
+
+#define USBH_HcRhPortStatus_PSSC_Pos     (18)                                              /*!< USBH_T::HcRhPortStatus1: PSSC Position */
+#define USBH_HcRhPortStatus_PSSC_Msk     (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)           /*!< USBH_T::HcRhPortStatus1: PSSC Mask     */
+
+#define USBH_HcRhPortStatus_OCIC_Pos     (19)                                              /*!< USBH_T::HcRhPortStatus1: OCIC Position */
+#define USBH_HcRhPortStatus_OCIC_Msk     (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)           /*!< USBH_T::HcRhPortStatus1: OCIC Mask     */
+
+#define USBH_HcRhPortStatus_PRSC_Pos     (20)                                              /*!< USBH_T::HcRhPortStatus1: PRSC Position */
+#define USBH_HcRhPortStatus_PRSC_Msk     (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)           /*!< USBH_T::HcRhPortStatus1: PRSC Mask     */
+
+#define USBH_HcPhyControl_STBYEN_Pos     (27)                                              /*!< USBH_T::HcPhyControl: STBYEN Position  */
+#define USBH_HcPhyControl_STBYEN_Msk     (0x1ul << USBH_HcPhyControl_STBYEN_Pos)           /*!< USBH_T::HcPhyControl: STBYEN Mask      */
+
+#define USBH_HcMiscControl_ABORT_Pos     (1)                                               /*!< USBH_T::HcMiscControl: ABORT Position  */
+#define USBH_HcMiscControl_ABORT_Msk     (0x1ul << USBH_HcMiscControl_ABORT_Pos)           /*!< USBH_T::HcMiscControl: ABORT Mask      */
+
+#define USBH_HcMiscControl_OCAL_Pos      (3)                                               /*!< USBH_T::HcMiscControl: OCAL Position   */
+#define USBH_HcMiscControl_OCAL_Msk      (0x1ul << USBH_HcMiscControl_OCAL_Pos)            /*!< USBH_T::HcMiscControl: OCAL Mask       */
+
+#define USBH_HcMiscControl_DPRT1_Pos     (16)                                              /*!< USBH_T::HcMiscControl: DPRT1 Position  */
+#define USBH_HcMiscControl_DPRT1_Msk     (0x1ul << USBH_HcMiscControl_DPRT1_Pos)           /*!< USBH_T::HcMiscControl: DPRT1 Mask      */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+
+
+/*---------------------- HSUSBH HSUSB Host Controller -------------------------*/
+/**
+    @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH)
+    Memory Mapped Structure for HSUSBH Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var HSUSBH_T::EHCVNR
+     * Offset: 0x00  EHCI Version Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CRLEN     |Capability Registers Length
+     * |        |          |This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
+     * |[31:16] |VERSION   |Host Controller Interface Version Number
+     * |        |          |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
+     * |        |          |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
+     * @var HSUSBH_T::EHCSPR
+     * Offset: 0x04  EHCI Structural Parameters Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |N_PORTS   |Number of Physical Downstream Ports
+     * |        |          |This field specifies the number of physical downstream ports implemented on this host controller
+     * |        |          |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8)
+     * |        |          |Valid values are in the range of 1H to FH.
+     * |        |          |A zero in this field is undefined.
+     * |[4]     |PPC       |Port Power Control
+     * |        |          |This field indicates whether the host controller implementation includes port power control
+     * |        |          |A one in this bit indicates the ports have port power switches
+     * |        |          |A zero in this bit indicates the port do not have port power stitches
+     * |        |          |The value of this field affects the functionality of the Port Power field in each port status and control register.
+     * |[11:8]  |N_PCC     |Number of Ports Per Companion Controller
+     * |        |          |This field indicates the number of ports supported per companion host controller
+     * |        |          |It is used to indicate the port routing configuration to system software.
+     * |        |          |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
+     * |        |          |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
+     * |        |          |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
+     * |        |          |The number in this field must be consistent with N_PORTS and N_CC.
+     * |[15:12] |N_CC      |Number of Companion Controller
+     * |        |          |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
+     * |        |          |A zero in this field indicates there are no companion host controllers
+     * |        |          |Port-ownership hand-off is not supported
+     * |        |          |Only high-speed devices are supported on the host controller root ports.
+     * |        |          |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
+     * |        |          |Port-ownership hand-offs are supported
+     * |        |          |High, Full- and Low-speed devices are supported on the host controller root ports.
+     * @var HSUSBH_T::EHCCPR
+     * Offset: 0x08  EHCI Capability Parameters Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AC64      |64-bit Addressing Capability
+     * |        |          |0 = Data structure using 32-bit address memory pointers.
+     * |[1]     |PFLF      |Programmable Frame List Flag
+     * |        |          |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
+     * |[2]     |ASPC      |Asynchronous Schedule Park Capability
+     * |        |          |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
+     * |[7:4]   |IST       |Isochronous Scheduling Threshold
+     * |        |          |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
+     * |        |          |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
+     * |[15:8]  |EECP      |EHCI Extended Capabilities Pointer (EECP)
+     * |        |          |0 = No extended capabilities are implemented.
+     * @var HSUSBH_T::UCMDR
+     * Offset: 0x20  USB Command Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RUN       |Run/Stop (R/W)
+     * |        |          |When set to a 1, the Host Controller proceeds with execution of the schedule
+     * |        |          |The Host Controller continues execution as long as this bit is set to a 1
+     * |        |          |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
+     * |        |          |The Host Controller must halt within 16 micro-frames after software clears the Run bit
+     * |        |          |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
+     * |        |          |Software must not write a one to this field unless the host controller is in the Halted state (i.e.
+     * |        |          |HCHalted in the USBSTS register is a one)
+     * |        |          |Doing so will yield undefined results.
+     * |        |          |0 = Stop.
+     * |        |          |1 = Run.
+     * |[1]     |HCRST     |Host Controller Reset (HCRESET) (R/W)
+     * |        |          |This control bit is used by software to reset the host controller
+     * |        |          |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
+     * |        |          |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
+     * |        |          |to their initial value
+     * |        |          |Any transaction currently in progress on USB is immediately terminated
+     * |        |          |A USB reset is not driven on downstream ports.
+     * |        |          |All operational registers, including port registers and port state machines are set to their initial values
+     * |        |          |Port ownership reverts to the companion host controller(s), with the side effects
+     * |        |          |Software must reinitialize the host controller in order to return the host controller to an operational state.
+     * |        |          |This bit is set to zero by the Host Controller when the reset process is complete
+     * |        |          |Software cannot terminate the reset process early by writing a zero to this register.
+     * |        |          |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
+     * |        |          |Attempting to reset an actively running host controller will result in undefined behavior.
+     * |[3:2]   |FLSZ      |Frame List Size (R/W or RO)
+     * |        |          |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
+     * |        |          |This field specifies the size of the frame list
+     * |        |          |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
+     * |        |          |Values mean:
+     * |        |          |00 = 1024 elements (4096 bytes) Default value.
+     * |        |          |01 = 512 elements (2048 bytes).
+     * |        |          |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment.
+     * |        |          |11 = Reserved.
+     * |[4]     |PSEN      |Periodic Schedule Enable (R/W)
+     * |        |          |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
+     * |        |          |0 = Do not process the Periodic Schedule.
+     * |        |          |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
+     * |[5]     |ASEN      |Asynchronous Schedule Enable (R/W)
+     * |        |          |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
+     * |        |          |0 = Do not process the Asynchronous Schedule.
+     * |        |          |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
+     * |[6]     |IAAD      |Interrupt on Asynchronous Advance Doorbell (R/W)
+     * |        |          |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
+     * |        |          |Software must write a 1 to this bit to ring the doorbell.
+     * |        |          |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
+     * |        |          |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
+     * |        |          |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
+     * |        |          |Software should not write a one to this bit when the asynchronous schedule is disabled
+     * |        |          |Doing so will yield undefined results.
+     * |[23:16] |ITC       |Interrupt Threshold Control (R/W)
+     * |        |          |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
+     * |        |          |The only valid values are defined below
+     * |        |          |If software writes an invalid value to this register, the results are undefined
+     * |        |          |Value Maximum Interrupt Interval
+     * |        |          |0x00 = Reserved.
+     * |        |          |0x01 = 1 micro-frame.
+     * |        |          |0x02 = 2 micro-frames.
+     * |        |          |0x04 = 4 micro-frames.
+     * |        |          |0x08 = 8 micro-frames (default, equates to 1 ms).
+     * |        |          |0x10 = 16 micro-frames (2 ms).
+     * |        |          |0x20 = 32 micro-frames (4 ms).
+     * |        |          |0x40 = 64 micro-frames (8 ms).
+     * |        |          |Any other value in this register yields undefined results.
+     * |        |          |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
+     * @var HSUSBH_T::USTSR
+     * Offset: 0x24  USB Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBINT    |USB Interrupt (USBINT) (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
+     * |        |          |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
+     * |[1]     |UERRINT   |USB Error Interrupt (USBERRINT) (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
+     * |        |          |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
+     * |[2]     |PCD       |Port Change Detect (R/WC)
+     * |        |          |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
+     * |        |          |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
+     * |        |          |This bit is allowed to be maintained in the Auxiliary power well
+     * |        |          |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
+     * |[3]     |FLR       |Frame List Rollover (R/WC)
+     * |        |          |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
+     * |        |          |The exact value at which the rollover occurs depends on the frame list size
+     * |        |          |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
+     * |        |          |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
+     * |[4]     |HSERR     |Host System Error (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
+     * |[5]     |IAA       |Interrupt on Asynchronous Advance (R/WC)
+     * |        |          |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
+     * |        |          |This status bit indicates the assertion of that interrupt source.
+     * |[12]    |HCHalted  |HCHalted (RO)
+     * |        |          |This bit is a zero whenever the Run/Stop bit is a one
+     * |        |          |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
+     * |        |          |internal error).
+     * |[13]    |RECLA     |Reclamation (RO)
+     * |        |          |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
+     * |[14]    |PSS       |Periodic Schedule Status (RO)
+     * |        |          |The bit reports the current real status of the Periodic Schedule
+     * |        |          |If this bit is a zero then the status of the Periodic Schedule is disabled
+     * |        |          |If this bit is a one then the status of the Periodic Schedule is enabled
+     * |        |          |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
+     * |        |          |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
+     * |[15]    |ASS       |Asynchronous Schedule Status (RO)
+     * |        |          |The bit reports the current real status of the Asynchronous Schedule
+     * |        |          |If this bit is a zero then the status of them Asynchronous Schedule is disabled
+     * |        |          |If this bit is a one then the status of the Asynchronous Schedule is enabled
+     * |        |          |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
+     * |        |          |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
+     * @var HSUSBH_T::UIENR
+     * Offset: 0x28  USB Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBIEN    |USB Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the USBINT bit.
+     * |        |          |0 = USB interrupt Disabled.
+     * |        |          |1 = USB interrupt Enabled.
+     * |[1]     |UERRIEN   |USB Error Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the USBERRINT bit.
+     * |        |          |0 = USB Error interrupt Disabled.
+     * |        |          |1 = USB Error interrupt Enabled.
+     * |[2]     |PCIEN     |Port Change Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Port Change Detect bit.
+     * |        |          |0 = Port Change interrupt Disabled.
+     * |        |          |1 = Port Change interrupt Enabled.
+     * |[3]     |FLREN     |Frame List Rollover Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
+     * |        |          |0 = Frame List Rollover interrupt Disabled.
+     * |        |          |1 = Frame List Rollover interrupt Enabled.
+     * |[4]     |HSERREN   |Host System Error Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Host System Error bit.
+     * |        |          |0 = Host System Error interrupt Disabled.
+     * |        |          |1 = Host System Error interrupt Enabled.
+     * |[5]     |IAAEN     |Interrupt on Asynchronous Advance Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
+     * |        |          |0 = Interrupt on Asynchronous Advance Disabled.
+     * |        |          |1 = Interrupt on Asynchronous Advance Enabled.
+     * @var HSUSBH_T::UFINDR
+     * Offset: 0x2C  USB Frame Index Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FI        |Frame Index
+     * |        |          |The value in this register increment at the end of each time frame (e.g.
+     * |        |          |micro-frame)
+     * |        |          |Bits [N:3] are used for the Frame List current index
+     * |        |          |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
+     * |        |          |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
+     * |        |          |FLSZ (UCMDR[3:2] Number Elements N
+     * |        |          |0x0 1024 12
+     * |        |          |0x1 512 11
+     * |        |          |0x2 256 10
+     * |        |          |0x3 Reserved
+     * @var HSUSBH_T::UPFLBAR
+     * Offset: 0x34  USB Periodic Frame List Base Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:12] |BADDR     |Base Address
+     * |        |          |These bits correspond to memory address signals [31:12], respectively.
+     * @var HSUSBH_T::UCALAR
+     * Offset: 0x38  USB Current Asynchronous List Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:5]  |LPL       |Link Pointer Low (LPL)
+     * |        |          |These bits correspond to memory address signals [31:5], respectively
+     * |        |          |This field may only reference a Queue Head (QH).
+     * @var HSUSBH_T::UASSTR
+     * Offset: 0x3C  USB Asynchronous Schedule Sleep Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |ASSTMR    |Asynchronous Schedule Sleep Timer
+     * |        |          |This field defines the AsyncSchedSleepTime of EHCI spec.
+     * |        |          |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty.
+     * |        |          |The default value of this timer is 12'hBD6
+     * |        |          |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us.
+     * @var HSUSBH_T::UCFGR
+     * Offset: 0x60  USB Configure Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CF        |Configure Flag (CF)
+     * |        |          |Host software sets this bit as the last action in its process of configuring the Host Controller
+     * |        |          |This bit controls the default port-routing control logic
+     * |        |          |Bit values and side-effects are listed below.
+     * |        |          |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
+     * |        |          |1 = Port routing control logic default-routes all ports to this host controller.
+     * @var HSUSBH_T::UPSCR[2]
+     * Offset: 0x64~0x68  USB Port 0~1 Status and Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCS       |Current Connect Status (RO)
+     * |        |          |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No device is present.
+     * |        |          |1 = Device is present on port.
+     * |[1]     |CSC       |Connect Status Change (R/W)
+     * |        |          |Indicates a change has occurred in the port's Current Connect Status
+     * |        |          |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
+     * |        |          |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No change.
+     * |        |          |1 = Change in Current Connect Status.
+     * |[2]     |PE        |Port Enabled/Disabled (R/W)
+     * |        |          |Ports can only be enabled by the host controller as a part of the reset and enable
+     * |        |          |Software cannot enable a port by writing a one to this field
+     * |        |          |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
+     * |        |          |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
+     * |        |          |Note that the bit status does not change until the port state actually changes
+     * |        |          |There may be a delay in disabling or enabling a port due to other host controller and bus events.
+     * |        |          |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port Disabled.
+     * |        |          |1 = Port Enabled.
+     * |[3]     |PEC       |Port Enable/Disable Change (R/WC)
+     * |        |          |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
+     * |        |          |Software clears this bit by writing a 1 to it.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No change.
+     * |        |          |1 = Port enabled/disabled status has changed.
+     * |[4]     |OCA       |Over-current Active (RO)
+     * |        |          |This bit will automatically transition from a one to a zero when the over current condition is removed.
+     * |        |          |0 = This port does not have an over-current condition.
+     * |        |          |1 = This port currently has an over-current condition.
+     * |[5]     |OCC       |Over-current Change (R/WC)
+     * |        |          |1 = This bit gets set to a one when there is a change to Over-current Active
+     * |        |          |Software clears this bit by writing a one to this bit position.
+     * |[6]     |FPR       |Force Port Resume (R/W)
+     * |        |          |This functionality defined for manipulating this bit depends on the value of the Suspend bit
+     * |        |          |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
+     * |        |          |Software sets this bit to a 1 to drive resume signaling
+     * |        |          |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
+     * |        |          |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
+     * |        |          |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
+     * |        |          |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
+     * |        |          |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
+     * |        |          |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
+     * |        |          |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
+     * |        |          |This bit will remain a one until the port has switched to the high-speed idle
+     * |        |          |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No resume (K-state) detected/driven on port.
+     * |        |          |1 = Resume detected/driven on port.
+     * |[7]     |SUSPEND   |Suspend (R/W)
+     * |        |          |Port Enabled Bit and Suspend bit of this register define the port states as follows:
+     * |        |          |Port enable is 0 and suspend is 0 = Disable.
+     * |        |          |Port enable is 0 and suspend is 1 = Disable.
+     * |        |          |Port enable is 1 and suspend is 0 = Enable.
+     * |        |          |Port enable is 1 and suspend is 1 = Suspend.
+     * |        |          |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
+     * |        |          |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
+     * |        |          |In the suspend state, the port is sensitive to resume detection
+     * |        |          |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
+     * |        |          |A write of zero to this bit is ignored by the host controller
+     * |        |          |The host controller will unconditionally set this bit to a zero when:
+     * |        |          |Software sets the Force Port Resume bit to a zero (from a one).
+     * |        |          |Software sets the Port Reset bit to a one (from a zero).
+     * |        |          |If host software sets this bit to a one when the port is not enabled (i.e.
+     * |        |          |Port enabled bit is a zero) the results are undefined.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port not in suspend state.
+     * |        |          |1 = Port in suspend state.
+     * |[8]     |PRST      |Port Reset (R/W)
+     * |        |          |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
+     * |        |          |Software writes a zero to this bit to terminate the bus reset sequence
+     * |        |          |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
+     * |        |          |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
+     * |        |          |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
+     * |        |          |The bit status will not read as a zero until after the reset has completed
+     * |        |          |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g.
+     * |        |          |set the Port Enable bit to a one)
+     * |        |          |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
+     * |        |          |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
+     * |        |          |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
+     * |        |          |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port is not in Reset.
+     * |        |          |1 = Port is in Reset.
+     * |[11:10] |LSTS      |Line Status (RO)
+     * |        |          |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
+     * |        |          |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
+     * |        |          |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
+     * |        |          |The encoding of the bits are:
+     * |        |          |Bits[11:10] USB State Interpretation
+     * |        |          |00 = SE0 Not Low-speed device, perform EHCI reset.
+     * |        |          |01 = K-state Low-speed device, release ownership of port.
+     * |        |          |10 = J-state Not Low-speed device, perform EHCI reset.
+     * |        |          |11 = Undefined Not Low-speed device, perform EHCI reset.
+     * |        |          |This value of this field is undefined if Port Power is zero.
+     * |[12]    |PP        |Port Power (PP)
+     * |        |          |Host controller has port power control switches
+     * |        |          |This bit represents the Current setting of the switch (0 = off, 1 = on)
+     * |        |          |When power is not available on a port (i.e.
+     * |        |          |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
+     * |        |          |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
+     * |[13]    |PO        |Port Owner (R/W)
+     * |        |          |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
+     * |        |          |This bit unconditionally goes to 1 whenever the Configured bit is zero.
+     * |        |          |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
+     * |        |          |Software writes a one to this bit when the attached device is not a high-speed device
+     * |        |          |A one in this bit means that a companion host controller owns and controls the port.
+     * |[19:16] |PTC       |Port Test Control (R/W)
+     * |        |          |When this field is zero, the port is NOT operating in a test mode
+     * |        |          |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
+     * |        |          |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
+     * |        |          |Bits Test Mode
+     * |        |          |0x0 = Test mode not enabled.
+     * |        |          |0x1 = Test J_STATE.
+     * |        |          |0x2 = Test K_STATE.
+     * |        |          |0x3 = Test SE0_NAK.
+     * |        |          |0x4 = Test Packet.
+     * |        |          |0x5 = Test FORCE_ENABLE.
+     * @var HSUSBH_T::USBPCR0
+     * Offset: 0xC4  USB PHY 0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8]     |SUSPEND   |Suspend Assertion
+     * |        |          |This bit controls the suspend mode of USB PHY 0.
+     * |        |          |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+     * |        |          |This bit is 1'b0 in default
+     * |        |          |This means the USB PHY 0 is suspended in default
+     * |        |          |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+     * |        |          |0 = USB PHY 0 was suspended.
+     * |        |          |1 = USB PHY 0 was not suspended.
+     * |[11]    |CLKVALID  |UTMI Clock Valid
+     * |        |          |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready
+     * |        |          |S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
+     * |        |          |0 = UTMI clock is not valid.
+     * |        |          |1 = UTMI clock is valid.
+     * @var HSUSBH_T::USBPCR1
+     * Offset: 0xC8  USB PHY 1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8]     |SUSPEND   |Suspend Assertion
+     * |        |          |This bit controls the suspend mode of USB PHY 1.
+     * |        |          |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+     * |        |          |This bit is 1'b0 in default
+     * |        |          |This means the USB PHY 0 is suspended in default
+     * |        |          |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+     * |        |          |0 = USB PHY 1 was suspended.
+     * |        |          |1 = USB PHY 1 was not suspended.
+     */
+    __I  uint32_t EHCVNR;                /*!< [0x0000] EHCI Version Number Register                                     */
+    __I  uint32_t EHCSPR;                /*!< [0x0004] EHCI Structural Parameters Register                              */
+    __I  uint32_t EHCCPR;                /*!< [0x0008] EHCI Capability Parameters Register                              */
+    __I  uint32_t RESERVE0[5];
+    __IO uint32_t UCMDR;                 /*!< [0x0020] USB Command Register                                             */
+    __IO uint32_t USTSR;                 /*!< [0x0024] USB Status Register                                              */
+    __IO uint32_t UIENR;                 /*!< [0x0028] USB Interrupt Enable Register                                    */
+    __IO uint32_t UFINDR;                /*!< [0x002c] USB Frame Index Register                                         */
+    __I  uint32_t RESERVE1[1];
+    __IO uint32_t UPFLBAR;               /*!< [0x0034] USB Periodic Frame List Base Address Register                    */
+    __IO uint32_t UCALAR;                /*!< [0x0038] USB Current Asynchronous List Address Register                   */
+    __IO uint32_t UASSTR;                /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register                   */
+    __I  uint32_t RESERVE2[8];
+    __IO uint32_t UCFGR;                 /*!< [0x0060] USB Configure Flag Register                                      */
+    __IO uint32_t UPSCR[2];              /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register            */
+    __I  uint32_t RESERVE3[22];
+    __IO uint32_t USBPCR0;               /*!< [0x00c4] USB PHY 0 Control Register                                       */
+    __IO uint32_t USBPCR1;               /*!< [0x00c8] USB PHY 1 Control Register                                       */
+
+} HSUSBH_T;
+
+/**
+    @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
+    Constant Definitions for HSUSBH Controller
+@{ */
+
+#define HSUSBH_EHCVNR_CRLEN_Pos          (0)                                               /*!< HSUSBH_T::EHCVNR: CRLEN Position       */
+#define HSUSBH_EHCVNR_CRLEN_Msk          (0xfful << HSUSBH_EHCVNR_CRLEN_Pos)               /*!< HSUSBH_T::EHCVNR: CRLEN Mask           */
+
+#define HSUSBH_EHCVNR_VERSION_Pos        (16)                                              /*!< HSUSBH_T::EHCVNR: VERSION Position     */
+#define HSUSBH_EHCVNR_VERSION_Msk        (0xfffful << HSUSBH_EHCVNR_VERSION_Pos)           /*!< HSUSBH_T::EHCVNR: VERSION Mask         */
+
+#define HSUSBH_EHCSPR_N_PORTS_Pos        (0)                                               /*!< HSUSBH_T::EHCSPR: N_PORTS Position     */
+#define HSUSBH_EHCSPR_N_PORTS_Msk        (0xful << HSUSBH_EHCSPR_N_PORTS_Pos)              /*!< HSUSBH_T::EHCSPR: N_PORTS Mask         */
+
+#define HSUSBH_EHCSPR_PPC_Pos            (4)                                               /*!< HSUSBH_T::EHCSPR: PPC Position         */
+#define HSUSBH_EHCSPR_PPC_Msk            (0x1ul << HSUSBH_EHCSPR_PPC_Pos)                  /*!< HSUSBH_T::EHCSPR: PPC Mask             */
+
+#define HSUSBH_EHCSPR_N_PCC_Pos          (8)                                               /*!< HSUSBH_T::EHCSPR: N_PCC Position       */
+#define HSUSBH_EHCSPR_N_PCC_Msk          (0xful << HSUSBH_EHCSPR_N_PCC_Pos)                /*!< HSUSBH_T::EHCSPR: N_PCC Mask           */
+
+#define HSUSBH_EHCSPR_N_CC_Pos           (12)                                              /*!< HSUSBH_T::EHCSPR: N_CC Position        */
+#define HSUSBH_EHCSPR_N_CC_Msk           (0xful << HSUSBH_EHCSPR_N_CC_Pos)                 /*!< HSUSBH_T::EHCSPR: N_CC Mask            */
+
+#define HSUSBH_EHCCPR_AC64_Pos           (0)                                               /*!< HSUSBH_T::EHCCPR: AC64 Position        */
+#define HSUSBH_EHCCPR_AC64_Msk           (0x1ul << HSUSBH_EHCCPR_AC64_Pos)                 /*!< HSUSBH_T::EHCCPR: AC64 Mask            */
+
+#define HSUSBH_EHCCPR_PFLF_Pos           (1)                                               /*!< HSUSBH_T::EHCCPR: PFLF Position        */
+#define HSUSBH_EHCCPR_PFLF_Msk           (0x1ul << HSUSBH_EHCCPR_PFLF_Pos)                 /*!< HSUSBH_T::EHCCPR: PFLF Mask            */
+
+#define HSUSBH_EHCCPR_ASPC_Pos           (2)                                               /*!< HSUSBH_T::EHCCPR: ASPC Position        */
+#define HSUSBH_EHCCPR_ASPC_Msk           (0x1ul << HSUSBH_EHCCPR_ASPC_Pos)                 /*!< HSUSBH_T::EHCCPR: ASPC Mask            */
+
+#define HSUSBH_EHCCPR_IST_Pos            (4)                                               /*!< HSUSBH_T::EHCCPR: IST Position         */
+#define HSUSBH_EHCCPR_IST_Msk            (0xful << HSUSBH_EHCCPR_IST_Pos)                  /*!< HSUSBH_T::EHCCPR: IST Mask             */
+
+#define HSUSBH_EHCCPR_EECP_Pos           (8)                                               /*!< HSUSBH_T::EHCCPR: EECP Position        */
+#define HSUSBH_EHCCPR_EECP_Msk           (0xfful << HSUSBH_EHCCPR_EECP_Pos)                /*!< HSUSBH_T::EHCCPR: EECP Mask            */
+
+#define HSUSBH_UCMDR_RUN_Pos             (0)                                               /*!< HSUSBH_T::UCMDR: RUN Position          */
+#define HSUSBH_UCMDR_RUN_Msk             (0x1ul << HSUSBH_UCMDR_RUN_Pos)                   /*!< HSUSBH_T::UCMDR: RUN Mask              */
+
+#define HSUSBH_UCMDR_HCRST_Pos           (1)                                               /*!< HSUSBH_T::UCMDR: HCRST Position        */
+#define HSUSBH_UCMDR_HCRST_Msk           (0x1ul << HSUSBH_UCMDR_HCRST_Pos)                 /*!< HSUSBH_T::UCMDR: HCRST Mask            */
+
+#define HSUSBH_UCMDR_FLSZ_Pos            (2)                                               /*!< HSUSBH_T::UCMDR: FLSZ Position         */
+#define HSUSBH_UCMDR_FLSZ_Msk            (0x3ul << HSUSBH_UCMDR_FLSZ_Pos)                  /*!< HSUSBH_T::UCMDR: FLSZ Mask             */
+
+#define HSUSBH_UCMDR_PSEN_Pos            (4)                                               /*!< HSUSBH_T::UCMDR: PSEN Position         */
+#define HSUSBH_UCMDR_PSEN_Msk            (0x1ul << HSUSBH_UCMDR_PSEN_Pos)                  /*!< HSUSBH_T::UCMDR: PSEN Mask             */
+
+#define HSUSBH_UCMDR_ASEN_Pos            (5)                                               /*!< HSUSBH_T::UCMDR: ASEN Position         */
+#define HSUSBH_UCMDR_ASEN_Msk            (0x1ul << HSUSBH_UCMDR_ASEN_Pos)                  /*!< HSUSBH_T::UCMDR: ASEN Mask             */
+
+#define HSUSBH_UCMDR_IAAD_Pos            (6)                                               /*!< HSUSBH_T::UCMDR: IAAD Position         */
+#define HSUSBH_UCMDR_IAAD_Msk            (0x1ul << HSUSBH_UCMDR_IAAD_Pos)                  /*!< HSUSBH_T::UCMDR: IAAD Mask             */
+
+#define HSUSBH_UCMDR_ITC_Pos             (16)                                              /*!< HSUSBH_T::UCMDR: ITC Position          */
+#define HSUSBH_UCMDR_ITC_Msk             (0xfful << HSUSBH_UCMDR_ITC_Pos)                  /*!< HSUSBH_T::UCMDR: ITC Mask              */
+
+#define HSUSBH_USTSR_USBINT_Pos          (0)                                               /*!< HSUSBH_T::USTSR: USBINT Position       */
+#define HSUSBH_USTSR_USBINT_Msk          (0x1ul << HSUSBH_USTSR_USBINT_Pos)                /*!< HSUSBH_T::USTSR: USBINT Mask           */
+
+#define HSUSBH_USTSR_UERRINT_Pos         (1)                                               /*!< HSUSBH_T::USTSR: UERRINT Position      */
+#define HSUSBH_USTSR_UERRINT_Msk         (0x1ul << HSUSBH_USTSR_UERRINT_Pos)               /*!< HSUSBH_T::USTSR: UERRINT Mask          */
+
+#define HSUSBH_USTSR_PCD_Pos             (2)                                               /*!< HSUSBH_T::USTSR: PCD Position          */
+#define HSUSBH_USTSR_PCD_Msk             (0x1ul << HSUSBH_USTSR_PCD_Pos)                   /*!< HSUSBH_T::USTSR: PCD Mask              */
+
+#define HSUSBH_USTSR_FLR_Pos             (3)                                               /*!< HSUSBH_T::USTSR: FLR Position          */
+#define HSUSBH_USTSR_FLR_Msk             (0x1ul << HSUSBH_USTSR_FLR_Pos)                   /*!< HSUSBH_T::USTSR: FLR Mask              */
+
+#define HSUSBH_USTSR_HSERR_Pos           (4)                                               /*!< HSUSBH_T::USTSR: HSERR Position        */
+#define HSUSBH_USTSR_HSERR_Msk           (0x1ul << HSUSBH_USTSR_HSERR_Pos)                 /*!< HSUSBH_T::USTSR: HSERR Mask            */
+
+#define HSUSBH_USTSR_IAA_Pos             (5)                                               /*!< HSUSBH_T::USTSR: IAA Position          */
+#define HSUSBH_USTSR_IAA_Msk             (0x1ul << HSUSBH_USTSR_IAA_Pos)                   /*!< HSUSBH_T::USTSR: IAA Mask              */
+
+#define HSUSBH_USTSR_HCHalted_Pos        (12)                                              /*!< HSUSBH_T::USTSR: HCHalted Position     */
+#define HSUSBH_USTSR_HCHalted_Msk        (0x1ul << HSUSBH_USTSR_HCHalted_Pos)              /*!< HSUSBH_T::USTSR: HCHalted Mask         */
+
+#define HSUSBH_USTSR_RECLA_Pos           (13)                                              /*!< HSUSBH_T::USTSR: RECLA Position        */
+#define HSUSBH_USTSR_RECLA_Msk           (0x1ul << HSUSBH_USTSR_RECLA_Pos)                 /*!< HSUSBH_T::USTSR: RECLA Mask            */
+
+#define HSUSBH_USTSR_PSS_Pos             (14)                                              /*!< HSUSBH_T::USTSR: PSS Position          */
+#define HSUSBH_USTSR_PSS_Msk             (0x1ul << HSUSBH_USTSR_PSS_Pos)                   /*!< HSUSBH_T::USTSR: PSS Mask              */
+
+#define HSUSBH_USTSR_ASS_Pos             (15)                                              /*!< HSUSBH_T::USTSR: ASS Position          */
+#define HSUSBH_USTSR_ASS_Msk             (0x1ul << HSUSBH_USTSR_ASS_Pos)                   /*!< HSUSBH_T::USTSR: ASS Mask              */
+
+#define HSUSBH_UIENR_USBIEN_Pos          (0)                                               /*!< HSUSBH_T::UIENR: USBIEN Position       */
+#define HSUSBH_UIENR_USBIEN_Msk          (0x1ul << HSUSBH_UIENR_USBIEN_Pos)                /*!< HSUSBH_T::UIENR: USBIEN Mask           */
+
+#define HSUSBH_UIENR_UERRIEN_Pos         (1)                                               /*!< HSUSBH_T::UIENR: UERRIEN Position      */
+#define HSUSBH_UIENR_UERRIEN_Msk         (0x1ul << HSUSBH_UIENR_UERRIEN_Pos)               /*!< HSUSBH_T::UIENR: UERRIEN Mask          */
+
+#define HSUSBH_UIENR_PCIEN_Pos           (2)                                               /*!< HSUSBH_T::UIENR: PCIEN Position        */
+#define HSUSBH_UIENR_PCIEN_Msk           (0x1ul << HSUSBH_UIENR_PCIEN_Pos)                 /*!< HSUSBH_T::UIENR: PCIEN Mask            */
+
+#define HSUSBH_UIENR_FLREN_Pos           (3)                                               /*!< HSUSBH_T::UIENR: FLREN Position        */
+#define HSUSBH_UIENR_FLREN_Msk           (0x1ul << HSUSBH_UIENR_FLREN_Pos)                 /*!< HSUSBH_T::UIENR: FLREN Mask            */
+
+#define HSUSBH_UIENR_HSERREN_Pos         (4)                                               /*!< HSUSBH_T::UIENR: HSERREN Position      */
+#define HSUSBH_UIENR_HSERREN_Msk         (0x1ul << HSUSBH_UIENR_HSERREN_Pos)               /*!< HSUSBH_T::UIENR: HSERREN Mask          */
+
+#define HSUSBH_UIENR_IAAEN_Pos           (5)                                               /*!< HSUSBH_T::UIENR: IAAEN Position        */
+#define HSUSBH_UIENR_IAAEN_Msk           (0x1ul << HSUSBH_UIENR_IAAEN_Pos)                 /*!< HSUSBH_T::UIENR: IAAEN Mask            */
+
+#define HSUSBH_UFINDR_FI_Pos             (0)                                               /*!< HSUSBH_T::UFINDR: FI Position          */
+#define HSUSBH_UFINDR_FI_Msk             (0x3ffful << HSUSBH_UFINDR_FI_Pos)                /*!< HSUSBH_T::UFINDR: FI Mask              */
+
+#define HSUSBH_UPFLBAR_BADDR_Pos         (12)                                              /*!< HSUSBH_T::UPFLBAR: BADDR Position      */
+#define HSUSBH_UPFLBAR_BADDR_Msk         (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos)           /*!< HSUSBH_T::UPFLBAR: BADDR Mask          */
+
+#define HSUSBH_UCALAR_LPL_Pos            (5)                                               /*!< HSUSBH_T::UCALAR: LPL Position         */
+#define HSUSBH_UCALAR_LPL_Msk            (0x7fffffful << HSUSBH_UCALAR_LPL_Pos)            /*!< HSUSBH_T::UCALAR: LPL Mask             */
+
+#define HSUSBH_UASSTR_ASSTMR_Pos         (0)                                               /*!< HSUSBH_T::UASSTR: ASSTMR Position      */
+#define HSUSBH_UASSTR_ASSTMR_Msk         (0xffful << HSUSBH_UASSTR_ASSTMR_Pos)             /*!< HSUSBH_T::UASSTR: ASSTMR Mask          */
+
+#define HSUSBH_UCFGR_CF_Pos              (0)                                               /*!< HSUSBH_T::UCFGR: CF Position           */
+#define HSUSBH_UCFGR_CF_Msk              (0x1ul << HSUSBH_UCFGR_CF_Pos)                    /*!< HSUSBH_T::UCFGR: CF Mask               */
+
+#define HSUSBH_UPSCR_CCS_Pos             (0)                                               /*!< HSUSBH_T::UPSCR[2]: CCS Position       */
+#define HSUSBH_UPSCR_CCS_Msk             (0x1ul << HSUSBH_UPSCR_CCS_Pos)                   /*!< HSUSBH_T::UPSCR[2]: CCS Mask           */
+
+#define HSUSBH_UPSCR_CSC_Pos             (1)                                               /*!< HSUSBH_T::UPSCR[2]: CSC Position       */
+#define HSUSBH_UPSCR_CSC_Msk             (0x1ul << HSUSBH_UPSCR_CSC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: CSC Mask           */
+
+#define HSUSBH_UPSCR_PE_Pos              (2)                                               /*!< HSUSBH_T::UPSCR[2]: PE Position        */
+#define HSUSBH_UPSCR_PE_Msk              (0x1ul << HSUSBH_UPSCR_PE_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PE Mask            */
+
+#define HSUSBH_UPSCR_PEC_Pos             (3)                                               /*!< HSUSBH_T::UPSCR[2]: PEC Position       */
+#define HSUSBH_UPSCR_PEC_Msk             (0x1ul << HSUSBH_UPSCR_PEC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: PEC Mask           */
+
+#define HSUSBH_UPSCR_OCA_Pos             (4)                                               /*!< HSUSBH_T::UPSCR[2]: OCA Position       */
+#define HSUSBH_UPSCR_OCA_Msk             (0x1ul << HSUSBH_UPSCR_OCA_Pos)                   /*!< HSUSBH_T::UPSCR[2]: OCA Mask           */
+
+#define HSUSBH_UPSCR_OCC_Pos             (5)                                               /*!< HSUSBH_T::UPSCR[2]: OCC Position       */
+#define HSUSBH_UPSCR_OCC_Msk             (0x1ul << HSUSBH_UPSCR_OCC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: OCC Mask           */
+
+#define HSUSBH_UPSCR_FPR_Pos             (6)                                               /*!< HSUSBH_T::UPSCR[2]: FPR Position       */
+#define HSUSBH_UPSCR_FPR_Msk             (0x1ul << HSUSBH_UPSCR_FPR_Pos)                   /*!< HSUSBH_T::UPSCR[2]: FPR Mask           */
+
+#define HSUSBH_UPSCR_SUSPEND_Pos         (7)                                               /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position   */
+#define HSUSBH_UPSCR_SUSPEND_Msk         (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos)               /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask       */
+
+#define HSUSBH_UPSCR_PRST_Pos            (8)                                               /*!< HSUSBH_T::UPSCR[2]: PRST Position      */
+#define HSUSBH_UPSCR_PRST_Msk            (0x1ul << HSUSBH_UPSCR_PRST_Pos)                  /*!< HSUSBH_T::UPSCR[2]: PRST Mask          */
+
+#define HSUSBH_UPSCR_LSTS_Pos            (10)                                              /*!< HSUSBH_T::UPSCR[2]: LSTS Position      */
+#define HSUSBH_UPSCR_LSTS_Msk            (0x3ul << HSUSBH_UPSCR_LSTS_Pos)                  /*!< HSUSBH_T::UPSCR[2]: LSTS Mask          */
+
+#define HSUSBH_UPSCR_PP_Pos              (12)                                              /*!< HSUSBH_T::UPSCR[2]: PP Position        */
+#define HSUSBH_UPSCR_PP_Msk              (0x1ul << HSUSBH_UPSCR_PP_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PP Mask            */
+
+#define HSUSBH_UPSCR_PO_Pos              (13)                                              /*!< HSUSBH_T::UPSCR[2]: PO Position        */
+#define HSUSBH_UPSCR_PO_Msk              (0x1ul << HSUSBH_UPSCR_PO_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PO Mask            */
+
+#define HSUSBH_UPSCR_PTC_Pos             (16)                                              /*!< HSUSBH_T::UPSCR[2]: PTC Position       */
+#define HSUSBH_UPSCR_PTC_Msk             (0xful << HSUSBH_UPSCR_PTC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: PTC Mask           */
+
+#define HSUSBH_USBPCR0_SUSPEND_Pos       (8)                                               /*!< HSUSBH_T::USBPCR0: SUSPEND Position    */
+#define HSUSBH_USBPCR0_SUSPEND_Msk       (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos)             /*!< HSUSBH_T::USBPCR0: SUSPEND Mask        */
+
+#define HSUSBH_USBPCR0_CLKVALID_Pos      (11)                                              /*!< HSUSBH_T::USBPCR0: CLKVALID Position   */
+#define HSUSBH_USBPCR0_CLKVALID_Msk      (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos)            /*!< HSUSBH_T::USBPCR0: CLKVALID Mask       */
+
+#define HSUSBH_USBPCR1_SUSPEND_Pos       (8)                                               /*!< HSUSBH_T::USBPCR1: SUSPEND Position    */
+#define HSUSBH_USBPCR1_SUSPEND_Msk       (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos)             /*!< HSUSBH_T::USBPCR1: SUSPEND Mask        */
+
+/**@}*/ /* HSUSBH_CONST */
+/**@}*/ /* end of HSUSBH register group */
+
+#define USBH                 ((USBH_T *)0xB0007000)
+#define HSUSBH               ((HSUSBH_T *)0xB0005000)
+
+
+/// @endcond /*HIDDEN_SYMBOLS*/
+
+#endif  /* _USBH_CONFIG_H_ */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
+

bsp/nuvoton/libraries/n9h30/UsbHostLib/inc/ehci.h

@@ -0,0 +1,279 @@
+/**************************************************************************//**
+ * @file     ehci.h
+ * @version  V1.00
+ * @brief    USB EHCI host controller driver header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_EHCI_H_
+#define _USBH_EHCI_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+struct qh_t;
+struct iso_ep_t;
+struct ep_info_t;
+
+/*----------------------------------------------------------------------------------------*/
+/*  Periodic Frame List Size (256, 512, or 1024)                                          */
+/*----------------------------------------------------------------------------------------*/
+#define FL_SIZE              1024            /* frame list size can be 256, 512, or 1024   */
+#define NUM_IQH              11              /* depends on FL_SIZE, 256:9, 512:10, 1024:11 */
+
+
+/*----------------------------------------------------------------------------------------*/
+/*  Interrupt Threshold Control (1, 2, 4, 6, .. 64)                                       */
+/*----------------------------------------------------------------------------------------*/
+#define UCMDR_INT_THR_CTRL     (0x1<<HSUSBH_UCMDR_ITC_Pos)     /* 1 micro-frames          */
+
+
+/*----------------------------------------------------------------------------------------*/
+/*  Queue Element Transfer Descriptor (qTD)                                               */
+/*----------------------------------------------------------------------------------------*/
+typedef struct qTD_t
+{
+    uint32_t      Next_qTD;                 /* Next qTD Pointer                           */
+    uint32_t      Alt_Next_qTD;             /* Alternate Next qTD Pointer                 */
+    uint32_t      Token;                    /* qTD Token                                  */
+    uint32_t      Bptr[5];                  /* qTD Buffer Page Pointer List               */
+    /*
+     * The following members are used by USB Host libary.
+     */
+    struct utr_t  *utr;                     /* associated UTR                             */
+    uint32_t      xfer_len;                 /* assigned transfer transfer length          */
+    struct qh_t   *qh;                      /* The QH that this qTD belong to.            */
+    struct qTD_t  *next;                    /* link for <qtd_list> of QH                  */
+}  qTD_T;
+
+
+#define QTD_LIST_END              0x1       /* Indicate the terminate of qTD list.        */
+#define QTD_PTR(x)                ((qTD_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ *  Status: qTD Token[7:0]
+ */
+#define QTD_STS_PS_OUT            (0<<0)    /* directs the HC to issue an OUT PID         */
+#define QTD_STS_PS_PING           (1<<0)    /* directs the HC to issue an PING PID        */
+#define QTD_STS_SPLIT_STRAT       (0<<1)    /* directs the HC to issue an Start split     */
+#define QTD_STS_SPLIT_COMPLETE    (1<<1)    /* directs the HC to issue an Complete split  */
+#define QTD_STS_MISS_MF           (1<<2)    /* miss a required complete-split transaction */
+#define QTD_STS_XactErr           (1<<3)    /* Transaction Error occurred                 */
+#define QTD_STS_BABBLE            (1<<4)    /* Babble Detected                            */
+#define QTD_STS_DATA_BUFF_ERR     (1<<5)    /* Data Buffer Error                          */
+#define QTD_STS_HALT              (1<<6)    /* Halted                                     */
+#define QTD_STS_ACTIVE            (1<<7)    /* Active                                     */
+
+/*
+ *  PID: qTD Token[9:8]
+ */
+#define QTD_PID_Msk              (0x3<<8)
+#define QTD_PID_OUT               (0<<8)    /* generates token (E1H)                      */
+#define QTD_PID_IN                (1<<8)    /* generates token (69H)                      */
+#define QTD_PID_SETUP             (2<<8)    /* generates token (2DH)                      */
+
+#define QTD_ERR_COUNTER           (3<<10)   /* Token[11:10]                               */
+#define QTD_IOC                   (1<<15)   /* Token[15] - Interrupt On Complete          */
+#define QTD_TODO_LEN_Pos          16        /* Token[31:16] - Total Bytes to Transfer     */
+#define QTD_TODO_LEN(x)           (((x)>>16) & 0x7FFF)
+#define QTD_DT                    (1UL<<31) /* Token[31] - Data Toggle                    */
+
+/*----------------------------------------------------------------------------------------*/
+/*  Queue Head (QH)                                                                       */
+/*----------------------------------------------------------------------------------------*/
+typedef struct qh_t
+{
+    /* OHCI spec. Endpoint descriptor  */
+    uint32_t    HLink;                      /* Queue Head Horizontal Link Pointer         */
+    uint32_t    Chrst;                      /* Endpoint Characteristics: QH DWord 1       */
+    uint32_t    Cap;                        /* Endpoint Capabilities: QH DWord 2          */
+    uint32_t    Curr_qTD;                   /* Current qTD Pointer                        */
+    /*
+     * The followings are qTD Transfer Overlay
+     */
+    uint32_t    OL_Next_qTD;                /* Next qTD Pointer                           */
+    uint32_t    OL_Alt_Next_qTD;            /* Alternate Next qTD Pointer                 */
+    uint32_t    OL_Token;                   /* qTD Token                                  */
+    uint32_t    OL_Bptr[5];                 /* qTD Buffer Page Pointer List               */
+    /*
+     * The following members are used by USB Host libary.
+     */
+    qTD_T       *qtd_list;                  /* currently linked qTD transfers             */
+    qTD_T       *done_list;                 /* currently linked qTD transfers             */
+    struct qh_t *next;                      /* point to the next QH in remove list        */
+}  QH_T;
+
+/*  HLink[0] T field of "Queue Head Horizontal Link Pointer" */
+#define QH_HLNK_END               0x1
+
+/*
+ *  HLink[2:1] Typ field of "Queue Head Horizontal Link Pointer"
+ */
+#define QH_HLNK_ITD(x)            (((uint32_t)(x) & ~0x1F) | 0x0)
+#define QH_HLNK_QH(x)             (((uint32_t)(x) & ~0x1F) | 0x2)
+#define QH_HLNK_SITD(x)           (((uint32_t)(x) & ~0x1F) | 0x4)
+#define QH_HLNK_FSTN(x)           (((uint32_t)(x) & ~0x1F) | 0x6)
+#define QH_PTR(x)                 ((QH_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ *  Bit fields of "Endpoint Characteristics"
+ */
+#define QH_NAK_RL                 (4L<<28)  /* Chrst[31:28] - NAK Count Reload            */
+#define QH_CTRL_EP_FLAG           (1<<27)   /* Chrst[27] - Control Endpoint Flag          */
+#define QH_RCLM_LIST_HEAD         (1<<15)   /* Chrst[15] - Head of Reclamation List Flag  */
+#define QH_DTC                    (1<<14)   /* Chrst[14] - Data Toggle Control            */
+#define QH_EPS_FULL               (0<<12)   /* Chrst[13:12] - Endpoint Speed (Full)       */
+#define QH_EPS_LOW                (1<<12)   /* Chrst[13:12] - Endpoint Speed (Low)        */
+#define QH_EPS_HIGH               (2<<12)   /* Chrst[13:12] - Endpoint Speed (High)       */
+#define QH_I_NEXT                 (1<<7)    /* Chrst[7] - Inactivate on Next Transaction  */
+
+/*
+ *  Bit fields of "Endpoint Capabilities"
+ */
+#define QH_MULT_Pos               30        /* Cap[31:30] - High-Bandwidth Pipe Multiplier */
+#define QH_HUB_PORT_Pos           23        /* Cap[29:23] - Hub Port Number               */
+#define QH_HUB_ADDR_Pos           16        /* Cap[22:16] - Hub Addr                      */
+#define QH_C_MASK_Msk             0xFF00    /* Cap[15:8]  - uFrame C-mask                 */
+#define QH_S_MASK_Msk             0x00FF    /* Cap[7:0]   - uFrame S-mask                 */
+
+
+/*----------------------------------------------------------------------------------------*/
+/*  Isochronous (High-Speed) Transfer Descriptor (iTD)                                    */
+/*----------------------------------------------------------------------------------------*/
+typedef struct itd_t
+{
+    uint32_t      Next_Link;                /* Next Link Pointer                          */
+    uint32_t      Transaction[8];           /* Transaction Status and Control             */
+    uint32_t      Bptr[7];                  /* Buffer Page Pointer List                   */
+    /*
+     * The following members are used by USB Host libary.
+     */
+    struct iso_ep_t *iso_ep;                /* associated isochronous information block   */
+    struct utr_t  *utr;                     /* associated UTR                             */
+    uint32_t      buff_base;                /* buffer base address                        */
+    uint8_t       fidx;                     /* iTD's first index to UTR iso frames        */
+    uint8_t       trans_mask;               /* mask of activated transactions in iTD      */
+    uint32_t      sched_frnidx;             /* scheduled frame index                      */
+    struct itd_t  *next;                    /* used by software to maintain iTD list      */
+}  iTD_T;
+
+/*
+ *  Next_Link[2:1] Typ field of "Next Schedule Element Pointer"  Typ field
+ */
+#define ITD_HLNK_ITD(x)           (((uint32_t)(x) & ~0x1F) | 0x0)
+#define ITD_HLNK_QH(x)            (((uint32_t)(x) & ~0x1F) | 0x2)
+#define ITD_HLNK_SITD(x)          (((uint32_t)(x) & ~0x1F) | 0x4)
+#define ITD_HLNK_FSTN(x)          (((uint32_t)(x) & ~0x1F) | 0x6)
+#define ITD_PTR(x)                ((iTD_T *)((uint32_t)(x) & ~0x1F))
+
+/*
+ *  Transaction[8]
+ */
+#define ITD_STATUS(x)             (((x)>>28)&0xF)
+#define ITD_STATUS_ACTIVE         (0x80000000UL)      /* Active                           */
+#define ITD_STATUS_BUFF_ERR       (0x40000000UL)      /* Data Buffer Error                */
+#define ITD_STATUS_BABBLE         (0x20000000UL)      /* Babble Detected                  */
+#define ITD_STATUS_XACT_ERR       (0x10000000UL)      /* Transcation Error                */
+
+#define ITD_XLEN_Pos              16
+#define ITD_XFER_LEN(x)           (((x)>>16)&0xFFF)
+#define ITD_IOC                   (1<<15)
+#define ITD_PG_Pos                12
+#define ITD_XFER_OFF_Msk          0xFFF
+
+/*
+ *  Bptr[7]
+ */
+#define ITD_BUFF_PAGE_Pos         12
+/* Bptr[0] */
+#define ITD_EP_NUM_Pos            8
+#define ITD_EP_NUM(itd)           (((itd)->Bptr[0]>>8)&0xF)
+#define ITD_DEV_ADDR_Pos          0
+#define ITD_DEV_ADDR(itd)         ((itd)->Bptr[0]&0x7F)
+/* Bptr[1] */
+#define ITD_DIR_IN                (1<<11)
+#define ITD_DIR_OUT               (0<<11)
+#define ITD_MAX_PKTSZ_Pos         0
+#define ITD_MAX_PKTSZ(itd)        ((itd)->Bptr[1]&0x7FF)
+
+/*----------------------------------------------------------------------------------------*/
+/*  Split Isochronous (Full-Speed) Transfer Descriptor (siTD)                             */
+/*----------------------------------------------------------------------------------------*/
+typedef struct sitd_t
+{
+    uint32_t      Next_Link;                /* Next Link Pointer                          */
+    uint32_t      Chrst;                    /* Endpoint and Transaction Translator Characteristics */
+    uint32_t      Sched;                    /* Micro-frame Schedule Control               */
+    uint32_t      StsCtrl;                  /* siTD Transfer Status and Control           */
+    uint32_t      Bptr[2];                  /* Buffer Page Pointer List                   */
+    uint32_t      BackLink;                 /* siTD Back Link Pointer                     */
+    /*
+     * The following members are used by USB Host libary.
+     */
+    struct iso_ep_t *iso_ep;                /* associated isochronous information block   */
+    struct utr_t  *utr;                     /* associated UTR                             */
+    uint8_t       fidx;                     /* iTD's first index to UTR iso frames        */
+    uint32_t      sched_frnidx;             /* scheduled frame index                      */
+    struct sitd_t *next;                    /* used by software to maintain siTD list     */
+}  siTD_T;
+
+#define SITD_LIST_END              0x1      /* Indicate the terminate of siTD list.       */
+
+#define SITD_XFER_IO_Msk           (1UL<<31)
+#define SITD_XFER_IN               (1UL<<31)
+#define SITD_XFER_OUT              (0UL<<31)
+
+#define SITD_PORT_NUM_Pos          24
+#define SITD_HUB_ADDR_Pos          16
+#define SITD_EP_NUM_Pos            8
+#define SITD_DEV_ADDR_Pos          0
+
+#define SITD_IOC                   (1UL<<31)
+#define SITD_XFER_CNT_Pos          16
+#define SITD_XFER_CNT_Msk          (0x3FF<<SITD_XFER_CNT_Pos)
+
+#define SITD_STATUS(x)             ((x)&0xFC)
+#define SITD_STATUS_ACTIVE         0x80
+#define SITD_STATUS_ERR            0x40
+#define SITD_STATUS_BUFF_ERR       0x20
+#define SITD_BABBLE_DETECTED       0x10
+#define SITD_STATUS_XFER_ERR       0x08
+#define SITD_STATUS_MISSED_MF      0x04
+#define SITD_STATUS_ERROR_MASK     0x78
+
+
+/*
+ *  Next_Link[2:1] Typ field of "Next Schedule Element Pointer"  Typ field
+ */
+#define SITD_HLNK_ITD(x)          (((uint32_t)(x) & ~0x1F) | 0x0)
+#define SITD_HLNK_QH(x)           (((uint32_t)(x) & ~0x1F) | 0x2)
+#define SITD_HLNK_SITD(x)         (((uint32_t)(x) & ~0x1F) | 0x4)
+#define SITD_HLNK_FSTN(x)         (((uint32_t)(x) & ~0x1F) | 0x6)
+#define SITD_PTR(x)               ((siTD_T *)((uint32_t)(x) & ~0x1F))
+
+#define HLINK_IS_TERMINATED(x)    (((uint32_t)(x) & 0x1) ? 1 : 0)
+#define HLINK_IS_SITD(x)          ((((uint32_t)(x) & 0x6) == 0x4) ? 1 : 0)
+
+/*----------------------------------------------------------------------------------------*/
+/*  Isochronous endpoint transfer information block. (Software only)                      */
+/*----------------------------------------------------------------------------------------*/
+typedef struct iso_ep_t
+{
+    struct ep_info_t  *ep;
+    uint32_t      next_frame;               /* frame number of next scheduling            */
+    iTD_T         *itd_list;                /* Reference to a list of installed iTDs      */
+    iTD_T         *itd_done_list;           /* Reference to a list of completed iTDs      */
+    siTD_T        *sitd_list;               /* Reference to a list of installed siTDs     */
+    siTD_T        *sitd_done_list;          /* Reference to a list of completed siTDs     */
+    struct iso_ep_t  *next;                 /* used by software to maintain ISO EP list   */
+} ISO_EP_T;
+
+extern void scan_isochronous_list(void);
+
+/// @endcond
+
+#endif  /* _USBH_EHCI_H_ */
+

bsp/nuvoton/libraries/n9h30/UsbHostLib/inc/hub.h

@@ -0,0 +1,124 @@
+/**************************************************************************//**
+ * @file     hub.h
+ * @version  V1.00
+ * @brief    USB Host hub class driver header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_HUB_H_
+#define _USBH_HUB_H_
+
+
+/// @cond HIDDEN_SYMBOLS
+
+
+/*--------------------------------------------------------------------------*/
+/*   Hub class feature selectors (Table 11-17)                              */
+/*--------------------------------------------------------------------------*/
+#define FS_C_HUB_LOCAL_POWER           0
+#define FS_C_HUB_OVER_CURRENT          1
+
+#define FS_PORT_CONNECTION             0
+#define FS_PORT_ENABLE                 1
+#define FS_PORT_SUSPEND                2
+#define FS_PORT_OVER_CURRENT           3
+#define FS_PORT_RESET                  4
+#define FS_PORT_POWER                  8
+#define FS_C_PORT_CONNECTION           16
+#define FS_C_PORT_ENABLE               17
+#define FS_C_PORT_SUSPEND              18
+#define FS_C_PORT_OVER_CURRENT         19
+#define FS_C_PORT_RESET                20
+
+/*--------------------------------------------------------------------------*/
+/*   Hub/Port staus and change bits                                         */
+/*--------------------------------------------------------------------------*/
+#define HUB_S_LOCAL_POWER              (1UL << 0)
+#define HUB_S_OVERCURRENT              (1UL << 1)
+
+#define HUB_C_LOCAL_POWER              (1UL << 0)
+#define HUB_C_OVERCURRENT              (1UL << 1)
+
+#define PORT_S_CONNECTION              (1UL << 0)
+#define PORT_S_ENABLE                  (1UL << 1)
+#define PORT_S_SUSPEND                 (1UL << 2)
+#define PORT_S_OVERCURRENT             (1UL << 3)
+#define PORT_S_RESET                   (1UL << 4)
+#define PORT_S_PORT_POWER              (1UL << 8)
+#define PORT_S_LOW_SPEED               (1UL << 9)
+#define PORT_S_HIGH_SPEED              (1UL << 10)
+#define PORT_S_TEST                    (1UL << 11)
+#define PORT_S_INDICATOR               (1UL << 12)
+
+#define PORT_C_CONNECTION              (1UL << 0)
+#define PORT_C_ENABLE                  (1UL << 1)
+#define PORT_C_SUSPEND                 (1UL << 2)
+#define PORT_C_OVERCURRENT             (1UL << 3)
+#define PORT_C_RESET                   (1UL << 4)
+
+
+/*--------------------------------------------------------------------------*/
+/*   Hub descriptor                                                         */
+/*--------------------------------------------------------------------------*/
+typedef struct __attribute__((__packed__))
+{
+    uint8_t  bDescLength;
+    uint8_t  bDescriptorType;
+    uint8_t  bNbrPorts;
+    uint16_t wHubCharacteristics;
+    uint8_t  bPwrOn2PwrGood;
+    uint8_t  bHubContrCurrent;
+    uint8_t  bDeviceRemovble;
+    uint8_t  PortPwrCtrlMask[16];
+}
+DESC_HUB_T;
+
+/*
+ *   wHubCharacteristics bit field mask
+ */
+#define HUB_CHAR_LPSM                  0x0003   /* 00b: global port power, 01b: per port power, 1x: reserved */
+#define HUB_CHAR_COMPOUND              0x0004   /* 1: is part of a compond device, 0: is not.       */
+#define HUB_CHAR_OCPM                  0x0018   /* 00b: global over-current protection, 01b: per port, 1x: reserved  */
+#define HUB_CHAR_TTTT                  0x0060   /* TT think time. 00b: 8FS, 01b: 16FS, 10b: 24FS, 11b: 32FS  */
+#define HUB_CHAR_PORTIND               0x0080   /* 1: port indicator (LED) supported, 0: not      */
+
+/* port indicator status selectors */
+#define HUB_LED_AUTO                   0
+#define HUB_LED_AMBER                  1
+#define HUB_LED_GREEN                  2
+#define HUB_LED_OFF                    3
+
+
+/*--------------------------------------------------------------------------*/
+/*   Port reset retry and time-out settings                                 */
+/*--------------------------------------------------------------------------*/
+#define HUB_DEBOUNCE_TIME              800      /* Hub connect/disconnect de-bounce time in ms     */
+#define PORT_RESET_RETRY               3        /* port reset retry times                          */
+#define PORT_RESET_TIME_MS             50       /* port reset time (ms)                            */
+#define PORT_RESET_RETRY_INC_MS        250      /* increased reset time (ms) after reset failed    */
+
+
+#define HUB_STATUS_MAX_BYTE            2        /* maximum number of interrupt-in status bytes     */
+/* 2 can support up to 16 port hubs                */
+/* 4 can support up to 32 port hubs                */
+/* Note!! If modeifed to 4, "uint16_t sc_bitmap"   */
+/*        MUST be changed as "uint32_t sc_bitmap"  */
+typedef struct hub_dev_t
+{
+    IFACE_T    *iface;                 /*!< Interface device of this hub          \hideinitializer */
+    UTR_T      *utr;                   /*!< Interrupt in UTR of this hub          \hideinitializer */
+    // uint8_t    buff[HUB_STATUS_MAX_BYTE];   /*!< Interrupt in buffer              \hideinitializer */
+    uint16_t   sc_bitmap;              /*!< Hub and Port Status Change Bitmap     \hideinitializer */
+    uint8_t    bNbrPorts;              /*!< Number of ports                       \hideinitializer */
+    uint8_t    bPwrOn2PwrGood;         /*!< Hub power on to power good time       \hideinitializer */
+    char       pos_id[MAX_HUB_DEVICE + 1]; /*!< Hub position identifier           \hideinitializer */
+    int (*port_reset)(struct hub_dev_t *hub, int port);       /*!< Port reset function                   \hideinitializer */
+    UDEV_T     *children;              /*!< Child device list.                    \hideinitializer */
+} HUB_DEV_T;
+
+
+/// @endcond
+
+#endif  /* _USBH_HUB_H_ */

bsp/nuvoton/libraries/n9h30/UsbHostLib/inc/ohci.h

@@ -0,0 +1,147 @@
+/**************************************************************************//**
+ * @file     ohci.h
+ * @version  V1.00
+ * @brief    USB OHCI host controller driver header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_OHCI_H_
+#define _USBH_OHCI_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * Host controller functional state.
+ * for HCFS(HcControl[7:6])
+ */
+#define HCFS_RESET                (0UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_RESUME               (1UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_OPER                 (2UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_SUSPEND              (3UL << USBH_HcControl_HCFS_Pos)
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Endpoint descriptor                                                                  */
+/*----------------------------------------------------------------------------------------*/
+typedef struct ed_t
+{
+    /* OHCI spec. Endpoint descriptor  */
+    uint32_t    Info;
+    uint32_t    TailP;
+    uint32_t    HeadP;
+    uint32_t    NextED;
+    /* The following members are used by USB Host libary.   */
+    uint8_t     bInterval;
+    uint16_t    next_sf;          /* for isochronous transfer, recording the next SF      */
+    struct ed_t *next;            /* point to the next ED in remove list                  */
+} ED_T;
+
+#define ED_CTRL_FA_Pos            0         /* Info[6:0]   - Function address             */
+#define ED_CTRL_EN_Pos            7         /* Info[10:7]  - Endpoint number              */
+#define ED_CTRL_DIR_Pos           11        /* Info[12:11] - Direction                    */
+#define ED_CTRL_MPS_Pos           16        /* Info[26:16] - Maximum packet size          */
+
+#define ED_FUNC_ADDR_Msk          (0x7f)
+#define ED_EP_ADDR_Msk            (0xf<<7)
+#define ED_DIR_Msk                (0x3<<11)
+#define ED_SPEED_Msk              (1<<13)
+#define ED_MAX_PK_SIZE_Msk        (0x7ff<<16)
+
+#define ED_DIR_BY_TD              (0<<ED_CTRL_DIR_Pos)
+#define ED_DIR_OUT                (1<<ED_CTRL_DIR_Pos)
+#define ED_DIR_IN                 (2<<ED_CTRL_DIR_Pos)
+#define ED_SPEED_FULL             (0<<13)   /* Info[13] - 0: is full speed device         */
+#define ED_SPEED_LOW              (1<<13)   /* Info[13] - 1: is low speed device          */
+#define ED_SKIP                   (1<<14)   /* Info[14] - 1: HC skip this ED              */
+#define ED_FORMAT_GENERAL         (0<<15)   /* Info[15] - 0: is a general TD              */
+#define ED_FORMAT_ISO             (1<<15)   /* Info[15] - 1: is an isochronous TD         */
+#define ED_HEADP_HALT             (1<<0)    /* HeadP[0] - 1: Halt; 0: Not                 */
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Transfer descriptor                                                                  */
+/*----------------------------------------------------------------------------------------*/
+/* general transfer descriptor  */
+typedef struct td_t
+{
+    uint32_t    Info;
+    uint32_t    CBP;                        /* Current Buffer Pointer                     */
+    uint32_t    NextTD;                     /* Next TD                                    */
+    uint32_t    BE;                         /* Buffer End                                 */
+    uint32_t    PSW[4];                     /* PSW 0~7                                    */
+    /* The following members are used by USB Host libary.   */
+    uint32_t    buff_start;                 /* Buffer Start                               */
+    ED_T        *ed;                        /* The ED that this TD belong to.             */
+    struct utr_t  *utr;                     /* associated UTR                             */
+    struct td_t *next;                      /* point to next TD of the same UTR           */
+} TD_T;
+
+#define TD_ADDR_MASK              0xFFFFFFFC
+
+/* Completion codes */
+enum OCHI_CC_CODE
+{
+    /* mapping of the OHCI CC status to error codes */
+    CC_NOERROR,                             /* No  Error                                  */
+    CC_CRC,                                 /* CRC Error                                  */
+    CC_BITSTUFF,                            /* Bit Stuff                                  */
+    CC_DATA_TOGGLE,                         /* Data Toggle                                */
+    CC_STALL,                               /* Stall                                      */
+    CC_NOTRESPONSE,                         /* DevNotResp                                 */
+    CC_PID_CHECK,                           /* PIDCheck                                   */
+    CC_UNEXPECTED_PID,                      /* UnExpPID                                   */
+    CC_DATA_OVERRUN,                        /* DataOver                                   */
+    CC_DATA_UNDERRUN,                       /* DataUnder                                  */
+    CC_RESERVED1,                           /* reserved                                   */
+    CC_RESERVED2,                           /* reserved                                   */
+    CC_BUFFER_OVERRUN,                      /* BufferOver                                 */
+    CC_BUFFER_UNDERRUN,                     /* BuffUnder                                  */
+    CC_NOT_ACCESS                           /* Not Access                                 */
+};
+
+/* TD control field */
+#define TD_CC                     0xF0000000
+#define TD_CC_GET(td)             ((td >>28) & 0x0F)
+#define TD_CC_SET(td, cc)         (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
+#define TD_T_DATA0                0x02000000
+#define TD_T_DATA1                0x03000000
+#define TD_R                      0x00040000
+#define TD_DP                     0x00180000
+#define TD_DP_IN                  0x00100000
+#define TD_DP_OUT                 0x00080000
+#define MAXPSW                    8
+/* steel TD reserved bits to keep driver data */
+#define TD_TYPE_Msk               (0x3<<16)
+#define TD_TYPE_CTRL              (0x0<<16)
+#define TD_TYPE_BULK              (0x1<<16)
+#define TD_TYPE_INT               (0x2<<16)
+#define TD_TYPE_ISO               (0x3<<16)
+#define TD_CTRL_Msk               (0x7<<15)
+#define TD_CTRL_DATA              (1<<15)
+
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+typedef struct
+{
+    uint32_t   int_table[32];               /* Interrupt ED table                         */
+    uint16_t   frame_no;                    /* current frame number                       */
+    uint16_t   pad1;                        /* set to 0 on each frame_no change           */
+    uint32_t   done_head;                   /* info returned for an interrupt             */
+    uint8_t    reserved_for_hc[116];
+} HCCA_T;
+
+
+/// @endcond
+
+#endif  /* _USBH_OHCI_H_ */