bsp-ft32 (#5652)

.github/workflows/action.yml

@@ -36,6 +36,7 @@ jobs:
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "ft32/ft32f072xb-starter", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32/gd32103c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32/gd32105c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32/gd32105r-start", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/ft32/ft32f072xb-starter/.config

@@ -0,0 +1,669 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
+CONFIG_RT_VER_NUM=0x40100
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# POSIX extension functions
+#
+# CONFIG_PKG_USING_POSIX_GETLINE is not set
+# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
+# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+CONFIG_SOC_FAMILY_FT32=y
+CONFIG_SOC_SERIES_FT32F0=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_FT32F072RB=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART1 is not set
+CONFIG_BSP_USING_UART2=y
+# CONFIG_BSP_USING_CRC is not set
+
+#
+# Board extended module Drivers
+#

bsp/ft32/ft32f072xb-starter/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/ft32/ft32f072xb-starter/Kconfig

@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
+

bsp/ft32/ft32f072xb-starter/README.md

@@ -0,0 +1,54 @@
+# FT32F072xx-StarterKit-32 #
+
+## 1. 简介
+
+[StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx)是辉芒微提供的开发板，使用 Cortex-M0 内核的 FT32F072x8/xB 作为主控制器。提供包括扩展引脚等外设资源。
+
+板载主要资源如下：
+
+| 硬件 | 描述 |
+| -- | -- |
+|CPU| Cortex-M0|
+|主频| 72MHz/96MHz |
+|SRAM| 8KB/24KB |
+|Flash| 64KB/128KB |
+
+- 常用外设
+  - LED：4个，（PB0、PB1、PB2、PB3）
+  - 按键：2个，（兼具唤醒功能，PC11、PC13)
+  - 触摸：2个，（PB10、PB11）
+- 常用接口：插针串口J8
+
+## 2. 编译说明
+
+StarterKit-32板级包支持 MDK5，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本 |
+| -- | -- |
+| MDK5(ARM Compiler 5 and 6) | MDK5.35 | 
+
+## 3. 烧写及执行
+
+下载程序：使用 CMSIS-DAP或者J-link等工具。
+
+### 3.1 配置和仿真
+
+工程已经默认使能了RT-Thread UART驱动、GPIO驱动。若想进一步配置工程请
+使用ENV工具。
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | USART0/1 |
+| GPIO | 支持 |  |
+
+## 5. 联系人信息
+
+维护人：
+
+- [FMD-AE](https://github.com/FmdAE)
+
+## 6. 参考
+
+* [StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx)

bsp/ft32/ft32f072xb-starter/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/ft32/ft32f072xb-starter/SConstruct

@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread_ft32f072.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ft32_library = 'FT32F0xx'
+rtconfig.BSP_LIBRARY_TYPE = ft32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ft32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/ft32/ft32f072xb-starter/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/ft32/ft32f072xb-starter/applications/main.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED2 pin: PA5 */
+#define LED2_PIN    GET_PIN(A, 5)
+
+int main(void)
+{
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED2_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED2_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}

bsp/ft32/ft32f072xb-starter/board/Kconfig

@@ -0,0 +1,52 @@
+menu "Hardware Drivers Config"
+
+config SOC_FT32F072RB
+    bool
+    select SOC_SERIES_FT32F0
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+
+            config BSP_UART1_RX_USING_DMA
+                bool "Enable UART1 RX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default y
+
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                default n
+        endif
+    source "../libraries/Drivers/Kconfig"
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/ft32/ft32f072xb-starter/board/SConscript

@@ -0,0 +1,29 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path =  [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s']
+
+# FT32F072x8 || FT32F072xB
+# You can select chips from the list above
+CPPDEFINES = ['FT32F072xB']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')

bsp/ft32/ft32f072xb-starter/board/board.c

@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+    #include "drv_usart.h"
+#endif /* RT_USING_SERIAL */
+
+#define DBG_TAG    "drv_common"
+#define DBG_LVL    DBG_INFO
+#include <rtdbg.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+__IO uint32_t uwTick;
+static uint32_t _systick_ms = 1;
+
+void IncTick(void)
+{
+    uwTick += _systick_ms;
+}
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+        IncTick();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+uint32_t GetTick(void)
+{
+    if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+        IncTick();
+
+    return uwTick;
+}
+
+void SuspendTick(void)
+{
+}
+
+void ResumeTick(void)
+{
+}
+
+void Delay(__IO uint32_t Delay)
+{
+    if (rt_thread_self())
+    {
+        rt_thread_mdelay(Delay);
+    }
+    else
+    {
+        for (rt_uint32_t count = 0; count < Delay; count++)
+        {
+            rt_hw_us_delay(1000);
+        }
+    }
+}
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * This function will initial FT32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+

bsp/ft32/ft32f072xb-starter/board/board.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <ft32f0xx.h>
+#include "drv_gpio.h"
+#include <rthw.h>
+#include <ft32f0xx_gpio.h>
+#include <ft32f0xx_exti.h>
+#include <ft32f0xx_usart.h>
+#include <ft32f0xx_dma.h>
+#include <ft32f0xx_rcc.h>
+#include <ft32f0xx_syscfg.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FT32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define FT32_FLASH_SIZE             (128 * 1024)
+#define FT32_FLASH_END_ADDRESS      ((uint32_t)(FT32_FLASH_START_ADRESS + FT32_FLASH_SIZE))
+
+/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
+#define FT32_SRAM_SIZE      24
+#define FT32_SRAM_END       (0x20000000 + FT32_SRAM_SIZE * 1024)
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END        FT32_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf

@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds

@@ -0,0 +1,157 @@
+/*
+ * linker script for STM32F10x with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  16k /* 16K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x400;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/ft32/ft32f072xb-starter/project.uvoptx

@@ -0,0 +1,915 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp; *.cc; *.cxx</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>0</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:FT32F072RBATx$CMSIS\Flash\FT32F0xx_128.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Compiler</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
+      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
+      <FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\common\time.c</PathWithFileName>
+      <FilenameWithoutPath>time.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\common\stdlib.c</PathWithFileName>
+      <FilenameWithoutPath>stdlib.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>CPU</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
+      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
+      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m0\cpuport.c</PathWithFileName>
+      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</PathWithFileName>
+      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>DeviceDrivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\waitqueue.c</PathWithFileName>
+      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\workqueue.c</PathWithFileName>
+      <FilenameWithoutPath>workqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\ringbuffer.c</PathWithFileName>
+      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\ipc\ringblk_buf.c</PathWithFileName>
+      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName>
+      <FilenameWithoutPath>pin.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName>
+      <FilenameWithoutPath>serial.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Drivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\arm\startup_ft32f072xb.s</PathWithFileName>
+      <FilenameWithoutPath>startup_ft32f072xb.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>board\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\Drivers\drv_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\Drivers\drv_usart.c</PathWithFileName>
+      <FilenameWithoutPath>drv_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Finsh</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\shell.c</PathWithFileName>
+      <FilenameWithoutPath>shell.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\msh.c</PathWithFileName>
+      <FilenameWithoutPath>msh.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\cmd.c</PathWithFileName>
+      <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Kernel</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\components.c</PathWithFileName>
+      <FilenameWithoutPath>components.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\kservice.c</PathWithFileName>
+      <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>29</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
+      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>30</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\mem.c</PathWithFileName>
+      <FilenameWithoutPath>mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>31</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
+      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>32</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\mempool.c</PathWithFileName>
+      <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>33</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\clock.c</PathWithFileName>
+      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>34</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>35</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\object.c</PathWithFileName>
+      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>36</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\device.c</PathWithFileName>
+      <FilenameWithoutPath>device.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>37</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>38</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\scheduler.c</PathWithFileName>
+      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>39</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\irq.c</PathWithFileName>
+      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Libraries</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>40</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crs.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_crs.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>41</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>42</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_pwr.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_pwr.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>43</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_div.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_div.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>44</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crc.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_crc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>45</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_syscfg.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_syscfg.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>46</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_usart.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>47</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_dma.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>48</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\system_ft32f0xx.c</PathWithFileName>
+      <FilenameWithoutPath>system_ft32f0xx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>49</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_tim.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_tim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>50</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_comp.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_comp.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>51</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_debug.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_debug.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>52</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_rcc.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_rcc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>53</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_exti.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_exti.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>54</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_iwdg.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_iwdg.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>55</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_misc.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_misc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>56</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_opa.c</PathWithFileName>
+      <FilenameWithoutPath>ft32f0xx_opa.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>

bsp/ft32/ft32f072xb-starter/project.uvprojx

@@ -0,0 +1,722 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>FT32F072RBATx</Device>
+          <Vendor>FMD</Vendor>
+          <PackID>FMD.FT32F0xx_DFP.1.0.5</PackID>
+          <PackURL>https://www.fremontmicro.com/upload/tools/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00006000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:FT32F072RBATx$CMSIS\Flash\FT32F0xx_128.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:FT32F072RBATx$Drivers\CMSIS\FT32F0xx\Include\ft32f0xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:FT32F072RBATx$CMSIS\SVD\FT32F0xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x6000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x6000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>FT32F072xB, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\FT32F0xx\CMSIS\FT32F0xx\Include;..\libraries\FT32F0xx\FT32F0xx_Driver\Inc;..\libraries\FT32F0xx\FT32F0xx_Driver\templates\Inc;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Compiler</GroupName>
+          <Files>
+            <File>
+              <FileName>syscalls.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
+            </File>
+            <File>
+              <FileName>syscall_mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
+            </File>
+            <File>
+              <FileName>stdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CPU</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
+            </File>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>startup_ft32f072xb.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\arm\startup_ft32f072xb.s</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\Drivers\drv_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>ft32f0xx_crs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crs.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_div.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_div.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_ft32f0xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\system_ft32f0xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_comp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_comp.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_debug.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_debug.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_iwdg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_iwdg.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ft32f0xx_opa.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_opa.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>project</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>

bsp/ft32/ft32f072xb-starter/rtconfig.h

@@ -0,0 +1,202 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart2"
+#define RT_VER_NUM 0x40100
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M0
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* Network */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* POSIX extension functions */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+#define SOC_FAMILY_FT32
+#define SOC_SERIES_FT32F0
+
+/* Hardware Drivers Config */
+
+#define SOC_FT32F072RB
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART2
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/ft32/ft32f072xb-starter/rtconfig.py

@@ -0,0 +1,185 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M0 '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'armclang':
+    # toolchains
+    CC = 'armclang'
+    CXX = 'armclang'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M0 '
+    CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m0 '
+    CFLAGS += ' -mcpu=cortex-m0 '
+    CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
+    CFLAGS += ' -gdwarf-3 -ffunction-sections '
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
+    LFLAGS += ' --list rt-thread.map '
+    LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
+
+    EXEC_PATH += '/ARM/ARMCLANG/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O1' # armclang recommend
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+        
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M0'
+    AFLAGS += ' --fpu None'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
+

bsp/ft32/ft32f072xb-starter/template.uvprojx

@@ -0,0 +1,396 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>FT32F072RBATx</Device>
+          <Vendor>FMD</Vendor>
+          <PackID>FMD.FT32F0xx_DFP.1.0.5</PackID>
+          <PackURL>https://www.fremontmicro.com/upload/tools/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00006000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:FT32F072RBATx$CMSIS\Flash\FT32F0xx_128.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:FT32F072RBATx$Drivers\CMSIS\FT32F0xx\Include\ft32f0xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:FT32F072RBATx$CMSIS\SVD\FT32F0xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x6000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x6000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group 1</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/ft32/libraries/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- FT32F0xx

bsp/ft32/libraries/Drivers/Kconfig

@@ -0,0 +1,34 @@
+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif
+
+config BSP_USING_CRC
+    bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRC
+    # "Crypto device frame dose not support above 8-bits granularity"
+    depends on (SOC_SERIES_FT32F0)
+    default n 
+

bsp/ft32/libraries/Drivers/SConscript

@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+        src += ['drv_usart.c']
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/ft32/libraries/Drivers/dma_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel2-3 DMA2 channel1-2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
+#define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+
+#if  defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+/* DMA1 channel2-3 DMA2 channel1-2 */
+
+/* DMA1 channel4-7 DMA2 channel3-5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#endif
+/* DMA1 channel4-7 DMA2 channel3-5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/ft32/libraries/Drivers/drv_config.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_FT32F0)
+#include "dma_config.h"
+#include "uart_config.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft32/libraries/Drivers/drv_dma.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __DRV_DMA_H_
+#define __DRV_DMA_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_FT32F0)
+#define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
+#endif
+
+struct dma_config {
+    DMA_INSTANCE_TYPE *Instance;
+    rt_uint32_t dma_rcc;
+    IRQn_Type dma_irq;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_DMA_H_ */

bsp/ft32/libraries/Drivers/drv_gpio.c

@@ -0,0 +1,556 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#include <board.h>
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
+#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
+
+#define PIN_FTPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE +(0x400u * PIN_PORT(pin))))
+#define PIN_FTPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
+
+#if defined(GPIOF)
+    #define __FT32_PORT_MAX 6u
+#elif defined(GPIOE)
+    #define __FT32_PORT_MAX 5u
+#elif defined(GPIOD)
+    #define __FT32_PORT_MAX 4u
+#elif defined(GPIOC)
+    #define __FT32_PORT_MAX 3u
+#elif defined(GPIOB)
+    #define __FT32_PORT_MAX 2u
+#elif defined(GPIOA)
+    #define __FT32_PORT_MAX 1u
+#else
+    #define __FT32_PORT_MAX 0u
+    #error Unsupported FT32 GPIO peripheral.
+#endif
+
+#define PIN_STPORT_MAX __FT32_PORT_MAX
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+#if defined(SOC_SERIES_FT32F0)
+    {GPIO_Pin_0, EXTI0_1_IRQn},
+    {GPIO_Pin_1, EXTI0_1_IRQn},
+    {GPIO_Pin_2, EXTI2_3_IRQn},
+    {GPIO_Pin_3, EXTI2_3_IRQn},
+    {GPIO_Pin_4, EXTI4_15_IRQn},
+    {GPIO_Pin_5, EXTI4_15_IRQn},
+    {GPIO_Pin_6, EXTI4_15_IRQn},
+    {GPIO_Pin_7, EXTI4_15_IRQn},
+    {GPIO_Pin_8, EXTI4_15_IRQn},
+    {GPIO_Pin_9, EXTI4_15_IRQn},
+    {GPIO_Pin_10, EXTI4_15_IRQn},
+    {GPIO_Pin_11, EXTI4_15_IRQn},
+    {GPIO_Pin_12, EXTI4_15_IRQn},
+    {GPIO_Pin_13, EXTI4_15_IRQn},
+    {GPIO_Pin_14, EXTI4_15_IRQn},
+    {GPIO_Pin_15, EXTI4_15_IRQn},
+#endif
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+static rt_base_t ft32_pin_get(const char *name)
+{
+    rt_base_t pin = 0;
+    int hw_port_num, hw_pin_num = 0;
+    int i, name_len;
+
+    name_len = rt_strlen(name);
+
+    if ((name_len < 4) || (name_len >= 6))
+    {
+        return -RT_EINVAL;
+    }
+    if ((name[0] != 'P') || (name[2] != '.'))
+    {
+        return -RT_EINVAL;
+    }
+
+    if ((name[1] >= 'A') && (name[1] <= 'Z'))
+    {
+        hw_port_num = (int)(name[1] - 'A');
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    for (i = 3; i < name_len; i++)
+    {
+        hw_pin_num *= 10;
+        hw_pin_num += name[i] - '0';
+    }
+
+    pin = PIN_NUM(hw_port_num, hw_pin_num);
+
+    return pin;
+}
+
+static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    GPIO_TypeDef *gpio_port;
+    uint16_t gpio_pin;
+
+    if (PIN_PORT(pin) < PIN_STPORT_MAX)
+    {
+        gpio_port = PIN_FTPORT(pin);
+        gpio_pin = PIN_FTPIN(pin);
+
+        GPIO_WriteBit(gpio_port, gpio_pin, (BitAction)value);
+    }
+}
+
+static int ft32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    GPIO_TypeDef *gpio_port;
+    uint16_t gpio_pin;
+    int value = PIN_LOW;
+
+    if (PIN_PORT(pin) < PIN_STPORT_MAX)
+    {
+        gpio_port = PIN_FTPORT(pin);
+        gpio_pin = PIN_FTPIN(pin);
+        value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
+    }
+
+    return value;
+}
+
+static void ft32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.GPIO_Pin = PIN_FTPIN(pin);
+    GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
+    GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+    GPIO_InitStruct.GPIO_Speed = GPIO_Speed_Level_3;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+    }
+
+    GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+static rt_err_t ft32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    irqindex = bit2bitno(PIN_FTPIN(pin));
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t ft32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    irqindex = bit2bitno(PIN_FTPIN(pin));
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static void rt_gpio_deinit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+    uint32_t position = 0x00u;
+    uint32_t iocurrent;
+    uint32_t tmp;
+
+    /* Configure the port pins */
+    while ((GPIO_Pin >> position) != 0x00u)
+    {
+        /* Get current io position */
+        iocurrent = (GPIO_Pin) & (1uL << position);
+
+        if (iocurrent != 0x00u)
+        {
+            /*------------------------- EXTI Mode Configuration --------------------*/
+            /* Clear the External Interrupt or Event for the current IO */
+
+            tmp = SYSCFG->EXTICR[position >> 2u];
+            tmp &= (0x0FuL << (4u * (position & 0x03u)));
+            if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
+            {
+                /* Clear EXTI line configuration */
+                EXTI->IMR &= ~((uint32_t)iocurrent);
+                EXTI->EMR &= ~((uint32_t)iocurrent);
+
+                /* Clear Rising Falling edge configuration */
+                EXTI->RTSR &= ~((uint32_t)iocurrent);
+                EXTI->FTSR &= ~((uint32_t)iocurrent);
+
+                /* Configure the External Interrupt or event for the current IO */
+                tmp = 0x0FuL << (4u * (position & 0x03u));
+                SYSCFG->EXTICR[position >> 2u] &= ~tmp;
+            }
+
+            /*------------------------- GPIO Mode Configuration --------------------*/
+            /* Configure IO Direction in Input Floating Mode */
+            GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
+
+            /* Configure the default Alternate Function in current IO */
+            GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
+
+            /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+            GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
+
+            /* Configure the default value IO Output Type */
+            GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+            /* Configure the default value for IO Speed */
+            GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+
+        }
+
+        position++;
+    }
+
+}
+
+
+static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                    rt_uint32_t enabled)
+{
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+    EXTI_InitTypeDef   EXTI_InitStructure;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(PIN_FTPIN(pin));
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        irqmap = &pin_irq_map[irqindex];
+
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+        SYSCFG_EXTILineConfig(PIN_PORT(pin), PIN_NO(pin));
+
+        GPIO_InitStruct.GPIO_Pin = PIN_FTPIN(pin);
+        GPIO_InitStruct.GPIO_Speed = GPIO_Speed_Level_3;
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN;
+            EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
+            EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+            EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
+            EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
+            EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+            EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+            EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
+            EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+            EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+            break;
+        }
+        GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct);
+        EXTI_Init(&EXTI_InitStructure);
+
+        NVIC_SetPriority(irqmap->irqno, 5);
+        NVIC_EnableIRQ(irqmap->irqno);
+        pin_irq_enable_mask |= irqmap->pinbit;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(PIN_FTPIN(pin));
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        rt_gpio_deinit(PIN_FTPORT(pin), PIN_FTPIN(pin));
+
+        pin_irq_enable_mask &= ~irqmap->pinbit;
+
+
+#if defined(SOC_SERIES_FT32F0)
+        if ((irqmap->pinbit >= GPIO_Pin_0) && (irqmap->pinbit <= GPIO_Pin_1))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_Pin_0 | GPIO_Pin_1)))
+            {
+                NVIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_Pin_2) && (irqmap->pinbit <= GPIO_Pin_3))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_Pin_2 | GPIO_Pin_3)))
+            {
+                NVIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_Pin_4) && (irqmap->pinbit <= GPIO_Pin_15))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                         GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15)))
+            {
+                NVIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else
+        {
+            NVIC_DisableIRQ(irqmap->irqno);
+        }
+
+#endif
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _ft32_pin_ops =
+{
+    ft32_pin_mode,
+    ft32_pin_write,
+    ft32_pin_read,
+    ft32_pin_attach_irq,
+    ft32_pin_dettach_irq,
+    ft32_pin_irq_enable,
+    ft32_pin_get,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+
+void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+
+void GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+    /* EXTI line interrupt detected */
+    if (__GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
+    {
+        __GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+        GPIO_EXTI_Callback(GPIO_Pin);
+    }
+}
+
+#if defined(SOC_SERIES_FT32F0)
+void EXTI0_1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_IRQHandler(GPIO_Pin_0);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_1);
+    rt_interrupt_leave();
+}
+
+void EXTI2_3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_IRQHandler(GPIO_Pin_2);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_3);
+    rt_interrupt_leave();
+}
+void EXTI4_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_IRQHandler(GPIO_Pin_4);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_5);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_6);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_7);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_8);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_9);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_10);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_11);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_12);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_13);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_14);
+    GPIO_EXTI_IRQHandler(GPIO_Pin_15);
+    rt_interrupt_leave();
+}
+#endif
+
+int rt_hw_pin_init(void)
+{
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+    return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL);
+}
+
+#endif /* RT_USING_PIN */

bsp/ft32/libraries/Drivers/drv_gpio.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOF))? 5U : 4U)
+
+#define __GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+#define __GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+#define __FT32_PORT(port)  GPIO##port##_BASE
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__FT32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+

bsp/ft32/libraries/Drivers/drv_log.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

bsp/ft32/libraries/Drivers/drv_usart.c

@@ -0,0 +1,695 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#include "board.h"
+#include "drv_usart.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_SERIAL
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.usart"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2)
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+    static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+};
+
+static struct ft32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+};
+
+static struct ft32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+void UART_MspInit(USART_TypeDef *USARTx)
+{
+    GPIO_InitTypeDef GPIO_InitStruct;
+    if (USARTx == USART1)
+    {
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+
+        /*GPIO INIT*/
+        GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10;
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
+        GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+        GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1);
+        GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1);
+
+        /* USART1 interrupt Init */
+        NVIC_SetPriority(USART1_IRQn, 5);
+        NVIC_EnableIRQ(USART1_IRQn);
+    }
+    else if (USARTx  == USART2)
+    {
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+
+        /*GPIO INIT*/
+        GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
+        GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
+        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+        GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1);
+        GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1);
+
+        /* USART2 interrupt Init */
+        NVIC_SetPriority(USART2_IRQn, 5);
+        NVIC_EnableIRQ(USART2_IRQn);
+    }
+}
+
+static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct ft32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+    uart->Init.USART_BaudRate = cfg->baud_rate;
+    uart->Init.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+
+    switch (cfg->flowcontrol)
+    {
+    case RT_SERIAL_FLOWCONTROL_NONE:
+        uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+        break;
+    case RT_SERIAL_FLOWCONTROL_CTSRTS:
+        uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
+        break;
+    default:
+        uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+        break;
+    }
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
+            uart->Init.USART_WordLength = USART_WordLength_9b;
+        else
+            uart->Init.USART_WordLength = USART_WordLength_8b;
+        break;
+    case DATA_BITS_9:
+        uart->Init.USART_WordLength = USART_WordLength_9b;
+        break;
+    default:
+        uart->Init.USART_WordLength = USART_WordLength_8b;
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart->Init.USART_StopBits = USART_StopBits_1;
+        break;
+    case STOP_BITS_2:
+        uart->Init.USART_StopBits   = USART_StopBits_2;
+        break;
+    default:
+        uart->Init.USART_StopBits   = USART_StopBits_1;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uart->Init.USART_Parity     = USART_Parity_No;
+        break;
+    case PARITY_ODD:
+        uart->Init.USART_Parity     = USART_Parity_Odd;
+        break;
+    case PARITY_EVEN:
+        uart->Init.USART_Parity     = USART_Parity_Even;
+        break;
+    default:
+        uart->Init.USART_Parity     = USART_Parity_No;
+        break;
+    }
+
+#ifdef RT_SERIAL_USING_DMA
+    uart->dma_rx.last_index = 0;
+#endif
+    UART_MspInit(uart->config->Instance);
+    USART_Init(uart->config->Instance, &(uart->Init));
+    USART_Cmd(uart->config->Instance, ENABLE);
+    return RT_EOK;
+}
+
+static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct ft32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* disable interrupt */
+        USART_ITConfig(uart->config->Instance, USART_IT_RXNE, DISABLE);
+
+#ifdef RT_SERIAL_USING_DMA
+        /* disable DMA */
+        if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
+        {
+            NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
+            DMA_DeInit(uart->dma_rx.Instance);
+        }
+        else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
+        {
+            NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
+            DMA_DeInit(uart->dma_rx.Instance);
+        }
+#endif
+        break;
+
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_SetPriority(uart->config->irq_type, 1);
+        NVIC_EnableIRQ(uart->config->irq_type);
+        /* enable interrupt */
+        USART_ITConfig(uart->config->Instance, USART_IT_RXNE, ENABLE);
+        break;
+
+#ifdef RT_SERIAL_USING_DMA
+    case RT_DEVICE_CTRL_CONFIG:
+        ft32_dma_config(serial, ctrl_arg);
+        break;
+#endif
+
+    case RT_DEVICE_CTRL_CLOSE:
+        USART_DeInit(uart->config->Instance);
+        break;
+
+    }
+    return RT_EOK;
+}
+
+rt_uint32_t ft32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
+{
+    rt_uint32_t mask;
+    if (word_length == USART_WordLength_8b)
+    {
+        if (parity == USART_Parity_No)
+        {
+            mask = 0x00FFU ;
+        }
+        else
+        {
+            mask = 0x007FU ;
+        }
+    }
+    else if (word_length == USART_WordLength_9b)
+    {
+        if (parity == USART_Parity_No)
+        {
+            mask = 0x01FFU ;
+        }
+        else
+        {
+            mask = 0x00FFU ;
+        }
+    }
+
+    else if (word_length == USART_WordLength_7b)
+    {
+        if (parity == USART_Parity_No)
+        {
+            mask = 0x007FU ;
+        }
+        else
+        {
+            mask = 0x003FU ;
+        }
+    }
+    else
+    {
+        mask = 0x0000U;
+    }
+    return mask;
+}
+
+static int ft32_putc(struct rt_serial_device *serial, char c)
+{
+    struct ft32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+    UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC);
+#if defined(SOC_SERIES_FT32F0)
+    uart->config->Instance->TDR = c;
+#else
+    uart->config->Instance->DR = c;
+#endif
+    while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET);
+    return 1;
+}
+
+static int ft32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct ft32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    ch = -1;
+    if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET)
+    {
+#if defined(SOC_SERIES_FT32F0)
+        ch = uart->config->Instance->RDR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity);
+#else
+        ch = uart->config->Instance->DR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity);
+#endif
+    }
+    return ch;
+}
+
+static rt_size_t ft32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    if (RT_SERIAL_DMA_TX == direction)
+    {
+        return size;
+    }
+    return 0;
+}
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct ft32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+#ifdef RT_SERIAL_USING_DMA
+    else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET))
+    {
+        level = rt_hw_interrupt_disable();
+        recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(&(uart->dma_rx.Instance));
+        recv_len = recv_total_index - uart->dma_rx.last_index;
+        uart->dma_rx.last_index = recv_total_index;
+        rt_hw_interrupt_enable(level);
+
+        if (recv_len)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+        }
+        USART_ClearFlag(uart->config->Instance, USART_IT_IDLE);
+    }
+    else if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) != RESET))
+    {
+        if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
+        {
+
+        }
+        UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC);
+    }
+#endif
+    else
+    {
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_ORE) != RESET)
+        {
+            USART_ClearFlag(uart->config->Instance, USART_FLAG_ORE);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_NE) != RESET)
+        {
+            USART_ClearFlag(uart->config->Instance, USART_FLAG_NE);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_FE) != RESET)
+        {
+            USART_ClearFlag(uart->config->Instance, USART_FLAG_FE);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_PE) != RESET)
+        {
+            USART_ClearFlag(uart->config->Instance, USART_FLAG_PE);
+        }
+#if !defined(SOC_SERIES_FT32F0)
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_LBD) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_LBD);
+        }
+#endif
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_CTS) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_CTS);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXE) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TXE);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC);
+        }
+        if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_RXNE);
+        }
+    }
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void dma_isr(struct rt_serial_device *serial)
+{
+    struct ft32_uart *uart;
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    if ((DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_TC) != RESET) ||
+            (DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_HT) != RESET))
+    {
+        level = rt_hw_interrupt_disable();
+        recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(uart->dma_rx.Instance);
+        if (recv_total_index == 0)
+        {
+            recv_len = serial->config.bufsz - uart->dma_rx.last_index;
+        }
+        else
+        {
+            recv_len = recv_total_index - uart->dma_rx.last_index;
+        }
+        uart->dma_rx.last_index = recv_total_index;
+        rt_hw_interrupt_enable(level);
+
+        if (recv_len)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+        }
+    }
+}
+#endif
+
+#if defined(BSP_USING_UART1)
+void USART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&(uart_obj[UART1_INDEX].serial));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
+void UART1_DMA_RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_rx.Instance);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
+void UART1_DMA_TX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_tx.Instance);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void USART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&(uart_obj[UART2_INDEX].serial));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
+void UART2_DMA_RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_rx.Instance);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
+void UART2_DMA_TX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_tx.Instance);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
+#endif /* BSP_USING_UART2 */
+
+
+static void ft32_uart_get_dma_config(void)
+{
+#ifdef BSP_USING_UART1
+    uart_obj[UART1_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART1_RX_USING_DMA
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
+    uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
+#endif
+#ifdef BSP_UART1_TX_USING_DMA
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
+    uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART2
+    uart_obj[UART2_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART2_RX_USING_DMA
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
+    uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
+#endif
+#ifdef BSP_UART2_TX_USING_DMA
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
+    uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
+#endif
+#endif
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
+{
+    struct rt_serial_rx_fifo *rx_fifo;
+
+    DMA_InitTypeDef Init;
+    struct dma_config *dma_config;
+    struct ft32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        Init = &uart->dma_rx.Init;
+        dma_config = uart->config->dma_rx;
+    }
+    else /* RT_DEVICE_FLAG_DMA_TX == flag */
+    {
+        Init = &uart->dma_tx.Init;
+        dma_config = uart->config->dma_tx;
+    }
+    LOG_D("%s dma config start", uart->config->name);
+
+    {
+        rt_uint32_t tmpreg = 0x00U;
+#if defined(SOC_SERIES_FT32F0)
+        /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+        SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
+        tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
+#endif
+
+        (void)(tmpreg);   /* To avoid compiler warnings */
+    }
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+    }
+
+    Init.DMA_PeripheralInc   =  DMA_PeripheralInc_Disable;
+    Init.MemInc              = DMA_MemoryInc_Enable;
+    Init.PeriphDataAlignment = DMA_PeripheralDataSize_Byte;
+    Init.MemDataAlignment    = DMA_MemoryDataSize_Byte;
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        Init.Direction           = DMA_DIR_PeripheralSRC;
+        Init.Mode                = DMA_Mode_Circular;
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        Init.Direction           = DMA_DIR_PeripheralDST;
+        Init.Mode                = DMA_Mode_Normal;
+    }
+
+    Init.Priority            = DMA_Priority_Medium;
+    DMA_DeInit(dma_config->Instance);
+    DMA_Init(dma_config->Instance);
+
+    /* enable interrupt */
+    if (flag == RT_DEVICE_FLAG_DMA_RX)
+    {
+        rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+        /* Start DMA transfer */
+        UART_Receive_DMA(uart->config->Instance, rx_fifo->buffer, serial->config.bufsz);
+        CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
+        USART_ITConfig(uart->config->Instance, USART_IT_IDLE, ENABLE);
+    }
+
+    /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
+    NVIC_SetPriority(dma_config->dma_irq, 0, 0);
+    NVIC_EnableIRQ(dma_config->dma_irq);
+
+    NVIC_SetPriority(uart->config->irq_type, 1, 0);
+    NVIC_EnableIRQ(uart->config->irq_type);
+
+    LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
+    LOG_D("%s dma config done", uart->config->name);
+}
+
+static void _dma_tx_complete(struct rt_serial_device *serial)
+{
+    struct ft32_uart *uart;
+    rt_size_t trans_total_index;
+    rt_base_t level;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct ft32_uart, serial);
+
+    level = rt_hw_interrupt_disable();
+    trans_total_index = DMA_GetCurrDataCounter(uart->dma_tx.Instance);
+    rt_hw_interrupt_enable(level);
+
+    if (trans_total_index == 0)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+    }
+}
+
+
+#endif  /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops ft32_uart_ops =
+{
+    .configure = ft32_configure,
+    .control = ft32_control,
+    .putc = ft32_putc,
+    .getc = ft32_getc,
+    .dma_transmit = ft32_dma_transmit
+};
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ft32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    ft32_uart_get_dma_config();
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config = &uart_config[i];
+        uart_obj[i].serial.ops    = &ft32_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX
+                                       | uart_obj[i].uart_dma_flag
+                                       , NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */

bsp/ft32/libraries/Drivers/drv_usart.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022.03.02     FMD-AE       first version
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include "drv_dma.h"
+
+int rt_hw_usart_init(void);
+
+#if defined(SOC_SERIES_FT32F0)
+    #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
+#endif
+
+#if defined(SOC_SERIES_FT32F0)
+    #define UART_INSTANCE_CLEAR_FUNCTION    USART_ClearITPendingBit
+#endif
+
+#define USART_TX_Pin GPIO_PIN_2
+#define USART_TX_GPIO_Port GPIOA
+#define USART_RX_Pin GPIO_PIN_3
+#define USART_RX_GPIO_Port GPIOA
+
+/* ft32 config class */
+struct ft32_uart_config
+{
+    const char *name;
+    USART_TypeDef *Instance;
+    IRQn_Type irq_type;
+    struct dma_config *dma_rx;
+    struct dma_config *dma_tx;
+};
+
+/* ft32 uart dirver class */
+struct ft32_uart
+{
+    USART_InitTypeDef Init;
+    struct ft32_uart_config *config;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_InitTypeDef Init;
+        DMA_Channel_TypeDef   *Instance;
+        rt_size_t last_index;
+    } dma_rx;
+    struct
+    {
+        DMA_InitTypeDef Init;
+        DMA_Channel_TypeDef   *Instance;
+    } dma_tx;
+#endif
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+#endif  /* __DRV_USART_H__ */

bsp/ft32/libraries/Drivers/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-02     FMD-AE       first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0.h

@@ -0,0 +1,702 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.30
+ * @date     17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0plus.h

@@ -0,0 +1,813 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.30
+ * @date     17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmFunc.h

@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.30
+ * @date     17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmInstr.h

@@ -0,0 +1,687 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.30
+ * @date     17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f030x6.h

@@ -0,0 +1,3888 @@
+/**
+  ******************************************************************************
+  * @file               ft32f030x6.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F030X6 devices.
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+
+#ifndef __FT32F030X6_H
+#define __FT32F030X6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#if !defined (FT32F030X6)
+  #define FT32F030X6
+#endif
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.0.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F030X6 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F030X6 do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F030X6 uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+    __IO uint32_t RESERVED[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t USER_RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00-0x03 */
+  __IO uint32_t DATA1_DATA0;       /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x07 */
+  __IO uint32_t WRP1_WRP0;         /*!< FLASH option byte write protection 0,1         Address offset: 0x08-0x0b */
+  __IO uint32_t WRP3_WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+//#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+//#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                             ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                     ((uint32_t)0x00000600) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                       ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                            ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                       ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                             ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x00060000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00180000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                              ((uint32_t)0x00800000) /*!<  */
+
+#define COMP_CSR_PCOMPOUTSEL                     ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                       ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                            ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                      ((uint32_t)0x80000000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F030X6 devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F030X6 devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F030X6 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F030X6 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F030X6 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN     ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000000))        // 2V
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000002))        // 3V
+#define DAC_CTRL_REF_SEL_2  ((uint32_t)(0x00000004))        // 4V
+#define DAC_CTRL_REF_SEL_3  ((uint32_t)(0x00000006))        // VDDA
+
+#define IS_DAC_REF_SEL(SEL) (((SEL) == DAC_CTRL_REF_SEL_0) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_1) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_2) ||\
+                ((SEL) == DAC_CTRL_REF_SEL_3))
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F030X6 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F030X6 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F030X6 devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F030X6 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F030X6 devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F030X6 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x00000FFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+//#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+//#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+//#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+//
+///******************  Bit definition for DMA_RMPCR2 register  ********************/
+//#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+//#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F030X6 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X6 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F030X6 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X6 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F030X6 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F030X6 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+//#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+//#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "FT32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F030X6_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f030x8.h

@@ -0,0 +1,3931 @@
+/**
+  ******************************************************************************
+  * @file               ft32f030x8.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F030X8 devices.
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup ft32f030x8
+  * @{
+  */
+
+#ifndef __FT32F030X8_H
+#define __FT32F030X8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target FT32F0 device used in your
+   application
+  */
+
+#if !defined (FT32F030X8)
+  #define FT32F030X8
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.0.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F030X8 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F030X8 do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F030X8 uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+    __IO uint32_t RESERVED[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t USER_RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00-0x03 */
+  __IO uint32_t DATA1_DATA0;       /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x07 */
+  __IO uint32_t WRP1_WRP0;         /*!< FLASH option byte write protection 0,1         Address offset: 0x08-0x0b */
+  __IO uint32_t WRP3_WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t RESERVED[12];   /*!< Reserved,                                          Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;             /*!< OP0 configuration register                              Address offset: 0x30 */
+}OP0_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+//#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+#define OP0_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+//#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define OP0                 ((OP0_TypeDef *) OP0_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+//#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                             ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                     ((uint32_t)0x00000600) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                       ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                            ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                       ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                             ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x00060000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00180000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                              ((uint32_t)0x00800000) /*!<  */
+
+#define COMP_CSR_PCOMPOUTSEL                     ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                       ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                            ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                      ((uint32_t)0x80000000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F030X8 devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F030X8 devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F030X8 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F030X8 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN     ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000000))        // 2V
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000002))        // 3V
+#define DAC_CTRL_REF_SEL_2  ((uint32_t)(0x00000004))        // 4V
+#define DAC_CTRL_REF_SEL_3  ((uint32_t)(0x00000006))        // VDDA
+
+#define IS_DAC_REF_SEL(SEL) (((SEL) == DAC_CTRL_REF_SEL_0) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_1) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_2) ||\
+                ((SEL) == DAC_CTRL_REF_SEL_3))
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F030X8 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F030X8 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x00000FFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+//#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+//#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+//#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+//
+///******************  Bit definition for DMA_RMPCR2 register  ********************/
+//#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+//#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+#define FLASH_KEY1                                                      FLASH_FKEY1
+#define FLASH_KEY2                                                      FLASH_FKEY2
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F030X8 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F030X8 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+//#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+#define  RCC_CSR_VDDLRSTF                    RCC_CSR_V18PWRRSTF
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+//#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "FT32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F030X8_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f032x6.h

@@ -0,0 +1,3972 @@
+/**
+  ******************************************************************************
+  * @file               ft32f030x8.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F030X8 devices.
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup ft32f030x8
+  * @{
+  */
+
+#ifndef __FT32F030X8_H
+#define __FT32F030X8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target FT32F0 device used in your
+   application
+  */
+
+#if !defined (FT32F030X8)
+  #define FT32F030X8
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.0.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F030X8 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F030X8 do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F030X8 uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+    __IO uint32_t RESERVED[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+/**
+  * @brief OPA
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[12];     /*!< Reserved,                               Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;                  /*!< COMP comparator control and status register, Address offset: 0x30 */
+} OPA_TypeDef;
+
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t USER_RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00-0x03 */
+  __IO uint32_t DATA1_DATA0;       /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x07 */
+  __IO uint32_t WRP1_WRP0;         /*!< FLASH option byte write protection 0,1         Address offset: 0x08-0x0b */
+  __IO uint32_t WRP3_WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t RESERVED[12];   /*!< Reserved,                                          Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;             /*!< OP0 configuration register                              Address offset: 0x30 */
+}OP0_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+//#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+#define OPA_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define OP0_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+//#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define OP0                 ((OP0_TypeDef *) OP0_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+//#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                             ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                     ((uint32_t)0x00000600) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                       ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                            ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                       ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                             ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x00060000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00180000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                              ((uint32_t)0x00800000) /*!<  */
+
+#define COMP_CSR_PCOMPOUTSEL                     ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                       ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                            ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                      ((uint32_t)0x80000000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F030X8 devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F030X8 devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F030X8 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F030X8 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN     ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000000))        // 2V
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000002))        // 3V
+#define DAC_CTRL_REF_SEL_2  ((uint32_t)(0x00000004))        // 4V
+#define DAC_CTRL_REF_SEL_3  ((uint32_t)(0x00000006))        // VDDA
+
+#define IS_DAC_REF_SEL(SEL) (((SEL) == DAC_CTRL_REF_SEL_0) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_1) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_2) ||\
+                ((SEL) == DAC_CTRL_REF_SEL_3))
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F030X8 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F030X8 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           OPA Controller (OPA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for OPA register  ********************/
+#define OPA_OP1_OUT                         ((uint32_t)0x00010000)        /*!< OP1 OUT STATE                                */
+#define OPA_OP1_PSEL                        ((uint32_t)0x00008000)        /*!< OP1 normal phase input selection             */
+#define OPA_OP1_NSEL                        ((uint32_t)0x00006000)        /*!< OP1 inverting terminal input selection       */
+#define OPA_OP1_NSEL_0                      ((uint32_t)0x00002000)        /*!< OP1 inverting terminal input selection BIT0  */
+#define OPA_OP1_NSEL_1                      ((uint32_t)0x00004000)        /*!< OP1 inverting terminal input selection BIT1  */
+#define OPA_OP1_FR                          ((uint32_t)0x00001C00)        /*!< OP1 feedback resistor selection              */
+#define OPA_OP1_FR_0                        ((uint32_t)0x00000400)        /*!< OP1 feedback resistor selection BIT0         */
+#define OPA_OP1_FR_1                        ((uint32_t)0x00000800)        /*!< OP1 feedback resistor selection BIT1         */
+#define OPA_OP1_FR_2                        ((uint32_t)0x00001000)        /*!< OP1 feedback resistor selection BIT2         */
+#define OPA_OP1_FCAPE                       ((uint32_t)0x00000200)        /*!< OP1 compensation capacitor enable BIT        */
+#define OPA_OP1_TM                          ((uint32_t)0x00000100)        /*!< OP1 input misalignment calibration mode      */
+#define OPA_OP1_TODIG                       ((uint32_t)0x00000080)        /*!< OP1 outputs to the register control bit      */
+#define OPA_OP1_TOIO                        ((uint32_t)0x00000040)        /*!< OP1 outputs to the ENABLE bit of PA0         */
+#define OPA_OP1_COF                         ((uint32_t)0x0000003E)        /*!< OP1 input misalignment calibration           */
+#define OPA_OP1_COF_0                       ((uint32_t)0x00000002)        /*!< OP1 input misalignment calibration BIT0      */
+#define OPA_OP1_COF_1                       ((uint32_t)0x00000004)        /*!< OP1 input misalignment calibration BIT1      */
+#define OPA_OP1_COF_2                       ((uint32_t)0x00000008)        /*!< OP1 input misalignment calibration BIT2      */
+#define OPA_OP1_COF_3                       ((uint32_t)0x00000010)        /*!< OP1 input misalignment calibration BIT3      */
+#define OPA_OP1_COF_4                       ((uint32_t)0x00000020)        /*!< OP1 input misalignment calibration BIT4      */
+#define OPA_OP1_ON                          ((uint32_t)0x00000001)        /*!< OP1 enable BIT                               */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x00000FFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+//#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+//#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+//#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+//
+///******************  Bit definition for DMA_RMPCR2 register  ********************/
+//#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+//#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+#define FLASH_KEY1                                                      FLASH_FKEY1
+#define FLASH_KEY2                                                      FLASH_FKEY2
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F030X8 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F030X8 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+//#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+#define  RCC_CSR_VDDLRSTF                    RCC_CSR_V18PWRRSTF
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+//#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "FT32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F030X8_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f032x8.h

@@ -0,0 +1,3973 @@
+/**
+  ******************************************************************************
+  * @file               ft32f030x8.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F030X8 devices.
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup ft32f030x8
+  * @{
+  */
+
+#ifndef __FT32F030X8_H
+#define __FT32F030X8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target FT32F0 device used in your
+   application
+  */
+
+#if !defined (FT32F030X8)
+  #define FT32F030X8
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.0.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F030X8 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F030X8 do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F030X8 uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+    __IO uint32_t RESERVED[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+/**
+  * @brief OPA
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[12];     /*!< Reserved,                               Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;                  /*!< COMP comparator control and status register, Address offset: 0x30 */
+} OPA_TypeDef;
+
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t USER_RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00-0x03 */
+  __IO uint32_t DATA1_DATA0;       /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x07 */
+  __IO uint32_t WRP1_WRP0;         /*!< FLASH option byte write protection 0,1         Address offset: 0x08-0x0b */
+  __IO uint32_t WRP3_WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t RESERVED[12];   /*!< Reserved,                                          Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;             /*!< OP0 configuration register                              Address offset: 0x30 */
+}OP0_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+//#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+#define OPA_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define OP0_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+//#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define OP0                 ((OP0_TypeDef *) OP0_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+//#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                             ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                     ((uint32_t)0x00000600) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                       ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                            ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                       ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                             ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x00060000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00180000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                              ((uint32_t)0x00800000) /*!<  */
+
+#define COMP_CSR_PCOMPOUTSEL                     ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                       ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                            ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                      ((uint32_t)0x80000000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F030X8 devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F030X8 devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F030X8 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F030X8 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN     ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000000))        // 2V
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000002))        // 3V
+#define DAC_CTRL_REF_SEL_2  ((uint32_t)(0x00000004))        // 4V
+#define DAC_CTRL_REF_SEL_3  ((uint32_t)(0x00000006))        // VDDA
+
+#define IS_DAC_REF_SEL(SEL) (((SEL) == DAC_CTRL_REF_SEL_0) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_1) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_2) ||\
+                ((SEL) == DAC_CTRL_REF_SEL_3))
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F030X8 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F030X8 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           OPA Controller (OPA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for OPA register  ********************/
+#define OPA_OP1_OUT                         ((uint32_t)0x00010000)        /*!< OP1 OUT STATE                                */
+#define OPA_OP1_PSEL                        ((uint32_t)0x00008000)        /*!< OP1 normal phase input selection             */
+#define OPA_OP1_NSEL                        ((uint32_t)0x00006000)        /*!< OP1 inverting terminal input selection       */
+#define OPA_OP1_NSEL_0                      ((uint32_t)0x00002000)        /*!< OP1 inverting terminal input selection BIT0  */
+#define OPA_OP1_NSEL_1                      ((uint32_t)0x00004000)        /*!< OP1 inverting terminal input selection BIT1  */
+#define OPA_OP1_FR                          ((uint32_t)0x00001C00)        /*!< OP1 feedback resistor selection              */
+#define OPA_OP1_FR_0                        ((uint32_t)0x00000400)        /*!< OP1 feedback resistor selection BIT0         */
+#define OPA_OP1_FR_1                        ((uint32_t)0x00000800)        /*!< OP1 feedback resistor selection BIT1         */
+#define OPA_OP1_FR_2                        ((uint32_t)0x00001000)        /*!< OP1 feedback resistor selection BIT2         */
+#define OPA_OP1_FCAPE                       ((uint32_t)0x00000200)        /*!< OP1 compensation capacitor enable BIT        */
+#define OPA_OP1_TM                          ((uint32_t)0x00000100)        /*!< OP1 input misalignment calibration mode      */
+#define OPA_OP1_TODIG                       ((uint32_t)0x00000080)        /*!< OP1 outputs to the register control bit      */
+#define OPA_OP1_TOIO                        ((uint32_t)0x00000040)        /*!< OP1 outputs to the ENABLE bit of PA0         */
+#define OPA_OP1_COF                         ((uint32_t)0x0000003E)        /*!< OP1 input misalignment calibration           */
+#define OPA_OP1_COF_0                       ((uint32_t)0x00000002)        /*!< OP1 input misalignment calibration BIT0      */
+#define OPA_OP1_COF_1                       ((uint32_t)0x00000004)        /*!< OP1 input misalignment calibration BIT1      */
+#define OPA_OP1_COF_2                       ((uint32_t)0x00000008)        /*!< OP1 input misalignment calibration BIT2      */
+#define OPA_OP1_COF_3                       ((uint32_t)0x00000010)        /*!< OP1 input misalignment calibration BIT3      */
+#define OPA_OP1_COF_4                       ((uint32_t)0x00000020)        /*!< OP1 input misalignment calibration BIT4      */
+#define OPA_OP1_ON                          ((uint32_t)0x00000001)        /*!< OP1 enable BIT                               */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F030X8 devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F030X8 devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F030X8 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x00000FFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+//#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+//#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+//#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+//
+///******************  Bit definition for DMA_RMPCR2 register  ********************/
+//#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+//#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+#define FLASH_KEY1                                                      FLASH_FKEY1
+#define FLASH_KEY2                                                      FLASH_FKEY2
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F030X8 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F030X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F030X8 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F030X8 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+//#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+#define  RCC_CSR_VDDLRSTF                    RCC_CSR_V18PWRRSTF
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+//#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "FT32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F030X8_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f072x8.h

@@ -0,0 +1,3978 @@
+/**
+  ******************************************************************************
+  * @file               ft32f072x8.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F072X8 devices.
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup ft32f030x8
+  * @{
+  */
+
+#ifndef __FT32F072X8_H
+#define __FT32F072X8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target FT32F0 device used in your
+   application
+  */
+
+#if !defined (FT32F072X8)
+  #define FT32F072X8
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.4.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F072X8 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F072X8 do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F072X8 uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+    __IO uint32_t RESERVED[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+/**
+  * @brief OPA
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[12];     /*!< Reserved,                               Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;                  /*!< COMP comparator control and status register, Address offset: 0x30 */
+} OPA_TypeDef;
+
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+    __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t USER_RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00-0x03 */
+  __IO uint32_t DATA1_DATA0;       /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x07 */
+  __IO uint32_t WRP1_WRP0;         /*!< FLASH option byte write protection 0,1         Address offset: 0x08-0x0b */
+  __IO uint32_t WRP3_WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+//#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define OPA_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+//#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                             ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                     ((uint32_t)0x00000600) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                       ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                            ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                       ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                             ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x00060000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00180000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                              ((uint32_t)0x00800000) /*!<  */
+
+#define COMP_CSR_PCOMPOUTSEL                     ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                       ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                            ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                      ((uint32_t)0x80000000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F072X8 devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F072X8 devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F072X8 devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F072X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F072X8 devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN     ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000000))        // 2V
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000002))        // 3V
+#define DAC_CTRL_REF_SEL_2  ((uint32_t)(0x00000004))        // 4V
+#define DAC_CTRL_REF_SEL_3  ((uint32_t)(0x00000006))        // VDDA
+
+#define IS_DAC_REF_SEL(SEL) (((SEL) == DAC_CTRL_REF_SEL_0) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_1) ||\
+                (((SEL) == DAC_CTRL_REF_SEL_2) ||\
+                ((SEL) == DAC_CTRL_REF_SEL_3))
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F072X8 devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F072X8 devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           OPA Controller (OPA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for OPA register  ********************/
+#define OPA_OP1_OUT                         ((uint32_t)0x00010000)        /*!< OP1 OUT STATE                                */
+#define OPA_OP1_PSEL                        ((uint32_t)0x00008000)        /*!< OP1 normal phase input selection             */
+#define OPA_OP1_NSEL                        ((uint32_t)0x00006000)        /*!< OP1 inverting terminal input selection       */
+#define OPA_OP1_NSEL_0                      ((uint32_t)0x00002000)        /*!< OP1 inverting terminal input selection BIT0  */
+#define OPA_OP1_NSEL_1                      ((uint32_t)0x00004000)        /*!< OP1 inverting terminal input selection BIT1  */
+#define OPA_OP1_FR                          ((uint32_t)0x00001C00)        /*!< OP1 feedback resistor selection              */
+#define OPA_OP1_FR_0                        ((uint32_t)0x00000400)        /*!< OP1 feedback resistor selection BIT0         */
+#define OPA_OP1_FR_1                        ((uint32_t)0x00000800)        /*!< OP1 feedback resistor selection BIT1         */
+#define OPA_OP1_FR_2                        ((uint32_t)0x00001000)        /*!< OP1 feedback resistor selection BIT2         */
+#define OPA_OP1_FCAPE                       ((uint32_t)0x00000200)        /*!< OP1 compensation capacitor enable BIT        */
+#define OPA_OP1_TM                          ((uint32_t)0x00000100)        /*!< OP1 input misalignment calibration mode      */
+#define OPA_OP1_TODIG                       ((uint32_t)0x00000080)        /*!< OP1 outputs to the register control bit      */
+#define OPA_OP1_TOIO                        ((uint32_t)0x00000040)        /*!< OP1 outputs to the ENABLE bit of PA0         */
+#define OPA_OP1_COF                         ((uint32_t)0x0000003E)        /*!< OP1 input misalignment calibration           */
+#define OPA_OP1_COF_0                       ((uint32_t)0x00000002)        /*!< OP1 input misalignment calibration BIT0      */
+#define OPA_OP1_COF_1                       ((uint32_t)0x00000004)        /*!< OP1 input misalignment calibration BIT1      */
+#define OPA_OP1_COF_2                       ((uint32_t)0x00000008)        /*!< OP1 input misalignment calibration BIT2      */
+#define OPA_OP1_COF_3                       ((uint32_t)0x00000010)        /*!< OP1 input misalignment calibration BIT3      */
+#define OPA_OP1_COF_4                       ((uint32_t)0x00000020)        /*!< OP1 input misalignment calibration BIT4      */
+#define OPA_OP1_ON                          ((uint32_t)0x00000001)        /*!< OP1 enable BIT                               */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F072X8 devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F072X8 devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F072X8 devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F072X8 devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x00000FFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************  Bit definition for DMA_RMPCR1 register  ********************/
+//#define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
+//#define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
+//#define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
+//#define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
+//#define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
+//#define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
+//#define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
+//#define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
+//#define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
+//#define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
+//
+///******************  Bit definition for DMA_RMPCR2 register  ********************/
+//#define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
+//#define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
+//#define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
+//#define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
+//#define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
+//#define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
+//#define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F072X8 devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F072X8 devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F072X8 devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F072X8 devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F072X8 devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F072X8 devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+//#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+//#define SYSCFG_CFGR1_PA11_PA12_RMP          ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages*/
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+//#define SYSCFG_CFGR1_TIM16_DMA_RMP2         ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_TIM17_DMA_RMP2         ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for FT32F072X8) */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+//#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for FT32F072X8 devices) */
+//#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for FT32F072X8devices) */
+//#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for FT32F072X8devices) */
+//#define SYSCFG_CFGR1_SPI2_DMA_RMP           ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_USART2_DMA_RMP         ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_USART3_DMA_RMP         ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_I2C1_DMA_RMP           ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_TIM1_DMA_RMP           ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_TIM2_DMA_RMP           ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for FT32F072X8) */
+//#define SYSCFG_CFGR1_TIM3_DMA_RMP           ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for FT32F072X8) */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+//#ifdef USE_STDPERIPH_DRIVER
+//  #include "FT32f0xx_conf.h"
+//#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F072X8_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f072xb.h

@@ -0,0 +1,4207 @@
+/**
+  ******************************************************************************
+  * @file               ft32f072xb.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+  * @details            This file contains all the peripheral register's definitions, bits
+  *                     definitions and memory mapping for FT32F072XB devices.
+  * @version            V1.0.0
+  * @date               2021-11-26
+  *******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup ft32f030xb
+  * @{
+  */
+
+#ifndef __FT32F072XB_H
+#define __FT32F072XB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target FT32F0 device used in your
+   application
+  */
+
+#if !defined (FT32F072XB)
+  #define FT32F072XB
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+   Timeout value
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief FT32F0XX Standard Peripheral Library version number V1.4.0
+   */
+#define __FT32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __FT32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __FT32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0XX_STDPERIPH_VERSION        ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__FT32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief FT32F072XB Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< FT32F072XB do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< FT32F072XB uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  FT32F0 specific Interrupt Numbers ******************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
+  PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
+  DIV_IRQn                    = 29,     /*!< USART2 Interrupt                                              */
+  USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
+}IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "ft32f0xx.h"
+#include "system_ft32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4;       /*!< Reserved,                                                                  0x2C */
+  __IO uint32_t ETCR;         /*!< External trigger Control register,                             Address offset:0x30 */
+  __IO uint32_t RTENR;        /*!< ADC rising edge trigger enable register,                             Address offset:0x34 */
+  __IO uint32_t FTENR;        /*!< ADC falling edge trigger enable register,                             Address offset:0x38 */
+  uint32_t   RESERVED5  ;     /*!< Reserved,                                                                  0x3C */
+  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;                    /*Address offset:0x308 */
+  __IO uint32_t CR2;                    /*Address offset:0x30C */
+  __IO uint32_t ADC_IOSH1DR;            /*Address offset:0x310 */
+  __IO uint32_t ADC_IOSH2DR;            /*Address offset:0x314 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t RESERVED1[7];     /*!< Reserved,                               Address offset: 0x18-0x00 */
+  __IO uint32_t CSR;                     /*!< COMP comparator control and status register, Address offset: 0x1C */
+  __IO uint32_t RESERVED2[3];     /*!< Reserved,                               Address offset: 0x20-0x28 */
+  __IO uint32_t CSR2;                    /*!< COMP comparator control and status register 2, Address offset: 0x2C */
+} COMP_TypeDef;
+/**
+  * @brief OPA
+  */
+typedef struct
+{
+  __IO uint32_t RESERVED1[12];           /*!< Reserved,                               Address offset: 0x2C-0x00 */
+  __IO uint32_t CR;                      /*!< COMP comparator control and status register, Address offset: 0x30 */
+} OPA_TypeDef;
+/**
+  * @brief ONEW
+  */
+typedef struct
+{
+  __IO uint32_t RESERVED1[13];     /*!< Reserved,                               Address offset: 0x30-0x00 */
+  __IO uint32_t CFG;                     /*!< COMP comparator control and status register, Address offset: 0x34 */
+  __IO uint32_t BUF;                     /*!< COMP comparator control and status register, Address offset: 0x38 */
+} ONEW_TypeDef;
+/**
+  * @brief DAC Configuration
+  */
+typedef struct
+{
+  __IO uint32_t RESERVED[8];    /*!< Reserved,                                          Address offset: 0x1C-0x00 */
+  __IO uint32_t CTRL;           /*!< DAC configuration register                              Address offset: 0x20 */
+  __IO uint32_t DATA1;          /*!< DAC1 Input  data                                        Address offset: 0x24 */
+  __IO uint32_t DATA2;          /*!< DAC2 Input  data                                        Address offset: 0x28 */
+}DAC_TypeDef;
+/**
+  * @brief DIV Configuration
+  */
+typedef struct
+{
+  __IO uint32_t RESERVED[32];    /*!< Reserved,                                       Address offset: 0x7C-0x00 */
+  __IO uint32_t DID;           /*!< DID  register                                       Address offset: 0x80 */
+  __IO uint32_t DIS;           /*!< DIS register                                        Address offset: 0x84 */
+  __IO uint32_t QUO;           /*!< QUO register                                        Address offset: 0x88 */
+  __IO uint32_t REM;           /*!< REM register                                        Address offset: 0x8C */
+  __IO uint32_t SC;            /*!< SC register                                         Address offset: 0x90 */
+}DIV_TypeDef;
+/**
+  * @brief LEB Configuration
+  */
+typedef struct
+{
+  __IO uint32_t LEBCR;             /*!< LEBCR  register                                         Address offset: 0x80 */
+  __IO uint32_t FLTCFG1;           /*!< FLTCFG1 register                                        Address offset: 0x84 */
+  __IO uint32_t FLTCFG2;           /*!< FLTCFG2 register                                        Address offset: 0x88 */
+  __IO uint32_t LEBCFG;            /*!< LEBCFG register                                         Address offset: 0x8C */
+  __IO uint32_t LEB1CFG;           /*!< LEB1CFG register                                        Address offset: 0x90 */
+  __IO uint32_t LEB2CFG;           /*!< LEB2CFG register                                        Address offset: 0x90 */
+  __IO uint32_t LEB3CFG;           /*!< LEB3CFG register                                        Address offset: 0x90 */
+  __IO uint32_t LEB1PR;            /*!< LEB1PR register                                         Address offset: 0x90 */
+  __IO uint32_t LEB2PR;            /*!< LEB2PR register                                         Address offset: 0x90 */
+  __IO uint32_t LEB3PR;            /*!< LEB3PR register                                         Address offset: 0x90 */
+}LEB_TypeDef;
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+    __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;               /*!< FLASH option byte Read protection,             Address offset: 0x00-0x01 */
+  __IO uint16_t USER;              /*!< FLASH option byte Read protection,             Address offset: 0x02-0x04 */
+  __IO uint16_t DATA0;             /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04-0x05 */
+  __IO uint16_t DATA1;             /*!< User data byte 0 (stored in FLASH_OBR[31:24]), Address offset: 0x06-0x07 */
+  __IO uint16_t WRP0;              /*!< FLASH option byte write protection 0           Address offset: 0x08-0x09 */
+  __IO uint16_t WRP1;              /*!< FLASH option byte write protection 1           Address offset: 0x0a-0x0b */
+  __IO uint16_t WRP2;              /*!< FLASH option byte write protection 2,          Address offset: 0x0C-0x0d */
+  __IO uint16_t WRP3;              /*!< FLASH option byte write protection 3,          Address offset: 0x0e-0x0f */
+} OB_TypeDef;
+
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint32_t RESERVED3;         /*!< Reserved,                                                                 0x2C */
+  __IO uint32_t LEDM;         /*!< GPIO LEDM register,                                       Address offset: 0x30 */
+}GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
+       uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
+  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief USB
+  */
+typedef struct
+{
+    __IO uint8_t FADDR;      /*!<  function address register,                            Address offset: 0x00 */
+    __IO uint8_t POWER;      /*!<  power management register,                            Address offset: 0x01 */
+    __IO uint8_t INTRIN;     /*!<  interrupt register endpint0 plus IN Endpoit 1 to 7,   Address offset: 0x02 */
+    __IO uint8_t RES1;       /*!<  RES1                                                  Address offset: 0x03 */
+    __IO uint8_t INTROUT;    /*!<  interrupt register for OUT Endpoints 1 to 7,          Address offset: 0x04 */
+    __IO uint8_t RES2;       /*!<  RES2                                                  Address offset: 0x05 */
+    __IO uint8_t INTRUSB;    /*!<  interrupt register for common USB interrrupts,        Address offset: 0x06 */
+    __IO uint8_t INTRINE;    /*!<  inerrupt enable register for INTRIN,                  Address offset: 0x07 */
+    __IO uint8_t RES3;       /*!<  RES3                                                  Address offset: 0x08 */
+    __IO uint8_t INTROUTE;   /*!<  inerrupt enable register for INTROUT,                 Address offset: 0x09 */
+    __IO uint8_t RES4;       /*!<  RES4                                                  Address offset: 0x0A */
+    __IO uint8_t INTRUSBE;   /*!<  inerrupt enable register for INTRUSB,                 Address offset: 0x0B */
+    __IO uint8_t FRAM1;      /*!<  frame number bits 0 to 7,                             Address offset: 0x0C */
+    __IO uint8_t FRAM2;      /*!<  frame number bits 8 to 15,                            Address offset: 0x0D */
+    __IO uint8_t INDEX;      /*!<  selecting then endpoint status and control register , Address offset: 0x0E */
+    __IO uint8_t PDCTRL;     /*!<  pull down pull up control ,                           Address offset: 0x0F */
+    __IO uint8_t INMAXP;     /*!<  Maximum packet size for IN endpoint,                  Address offset: 0x10 */
+    union
+    {
+        __IO uint8_t INCSR0; /*!<  control status register fie endpoint 0,               Address offset: 0x11 */
+        __IO uint8_t INCSR1; /*!<  Control Status register 1 for IN Endpoint,            Address offset: 0x11 */
+    }INCSR;
+    __IO uint8_t INCSR2;     /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    //__IO uint8_t RES;        /*!<  Control Status register 2 for IN Endpoint,            Address offset: 0x12 */
+    __IO uint8_t OUTMAXP;    /*!<  Maximum packet size for OUT endpoint,                 Address offset: 0x13 */
+    __IO uint8_t OUTCSR1;    /*!<  Control Status register 1 for OUT Endpoint,           Address offset: 0x14 */
+    __IO uint8_t OUTCSR2;    /*!<  Control Status register 2 for OUT Endpoint,           Address offset: 0x15 */
+    __IO uint8_t OUTCOUNTER; /*!<  number of bytes in OUT endpoint FIFO ,                Address offset: 0x16 */
+    __IO uint8_t RES5;       /*!<  RES5                                                  Address offset: 0x17 */
+    __IO uint8_t RES6;       /*!<  RES6                                                  Address offset: 0x18 */
+    __IO uint8_t RES7;       /*!<  RES7                                                  Address offset: 0x19 */
+    __IO uint8_t FIFO0;      /*!<  FIFO for Endpoint 0,                                  Address offset: 0x20 */
+    __IO uint8_t RES8;       /*!<  RES8                                                  Address offset: 0x21 */
+    __IO uint8_t RES9;       /*!<  RES9                                                  Address offset: 0x22 */
+    __IO uint8_t RES10;      /*!<  RES10                                                 Address offset: 0x23 */
+    __IO uint8_t FIFO1;      /*!<  FIFO for Endpoint 1,                                  Address offset: 0x24 */
+    __IO uint8_t RES11;      /*!<  RES11                                                 Address offset: 0x25 */
+    __IO uint8_t RES12;      /*!<  RES12                                                 Address offset: 0x26 */
+    __IO uint8_t RES13;      /*!<  RES13                                                 Address offset: 0x27 */
+    __IO uint8_t FIFO2;      /*!<  FIFO for Endpoint 2,                                  Address offset: 0x28 */
+    __IO uint8_t RES14;      /*!<  RES14                                                 Address offset: 0x29 */
+    __IO uint8_t RES15;      /*!<  RES15                                                 Address offset: 0x2A */
+    __IO uint8_t RES16;      /*!<  RES16                                                 Address offset: 0x2B */
+    __IO uint8_t FIFO3;      /*!<  FIFO for Endpoint 3,                                  Address offset: 0x2C */
+    __IO uint8_t RES17;      /*!<  RES17                                                 Address offset: 0x2D */
+    __IO uint8_t RES18;      /*!<  RES18                                                 Address offset: 0x2E */
+    __IO uint8_t RES19;      /*!<  RES19                                                 Address offset: 0x2F */
+    __IO uint8_t FIFO4;      /*!<  FIFO for Endpoint 4,                                  Address offset: 0x30 */
+    __IO uint8_t RES20;      /*!<  RES20                                                 Address offset: 0x31 */
+    __IO uint8_t RES21;      /*!<  RES21                                                 Address offset: 0x32 */
+    __IO uint8_t RES22;      /*!<  RES22                                                 Address offset: 0x33 */
+    __IO uint8_t FIFO5;      /*!<  FIFO for Endpoint 5,                                  Address offset: 0x34 */
+    __IO uint8_t RES23;      /*!<  RES23                                                 Address offset: 0x35 */
+    __IO uint8_t RES24;      /*!<  RES24                                                 Address offset: 0x36 */
+    __IO uint8_t RES25;      /*!<  RES25                                                 Address offset: 0x37 */
+    __IO uint8_t FIFO6;      /*!<  FIFO for Endpoint 6,                                  Address offset: 0x38 */
+    __IO uint8_t RES26;      /*!<  RES26                                                 Address offset: 0x39 */
+    __IO uint8_t RES27;      /*!<  RES27                                                 Address offset: 0x3A */
+    __IO uint8_t RES28;      /*!<  RES28                                                 Address offset: 0x3B */
+    __IO uint8_t FIFO7;      /*!<  FIFO for Endpoint 7,                                  Address offset: 0x3C */
+}USB_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+  __IO uint32_t HSECFG;      /*!< RCC clock configuration register 2,                         Address offset: 0x38 New*/
+  __IO uint32_t CFGR4;      /*!< RCC clock configuration register 3,                          Address offset: 0x3C New*/
+  __IO uint32_t TRIM;        /*!< RCC clock control register 2,                               Address offset: 0x40 New*/
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
+       uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+       uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL   CALR
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
+ // __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+ // uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+ // __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  //uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
+} SPI_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/**
+  * @brief TSC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< TSC configer register                          Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< TSC configuration register,                    Address offset: 0x04 */
+}TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  //uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
+  //__IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  //uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  uint32_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE              (APBPERIPH_BASE + 0x00005C00)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x00010000)
+#define OPA_BASE              (APBPERIPH_BASE + 0x00010000)
+#define OPA2_BASE             (APBPERIPH_BASE + 0x00010010)
+#define ONEW_BASE             (APBPERIPH_BASE + 0x00010000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00010000)
+#define DIV_BASE              (APBPERIPH_BASE + 0x00010000)
+#define LEB_BASE              (APBPERIPH_BASE + 0x0000FC00)
+
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define OPA2                ((OPA_TypeDef *) OPA2_BASE)
+#define ONEW                ((ONEW_TypeDef *) ONEW_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DIV                 ((DIV_TypeDef *) DIV_BASE)
+#define LEB                 ((LEB_TypeDef *) LEB_BASE)
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+#define OPA1                OPA
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
+#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
+#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
+#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL21                   ((uint32_t)0x00200000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL20                   ((uint32_t)0x00100000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL19                   ((uint32_t)0x00080000)        /*!< Channel 19 selection */
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_VREFEN                       ((uint32_t)0x00000002)       /*!< Voltage battery enable */
+#define  ADC_CR2_VREFSEL                      ((uint32_t)0x0000000C)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_0                    ((uint32_t)0x00000004)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREFSEL_1                    ((uint32_t)0x00000008)       /*!< Tempurature sensore enable */
+#define  ADC_CR2_VREF_DECIB                   ((uint32_t)0x00000010)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_AMPEN                  ((uint32_t)0x00000100)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPEN                  ((uint32_t)0x00000200)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SEL                    ((uint32_t)0x00000400)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH1_SMPMOD                 ((uint32_t)0x00000800)       /*!< SMPMOD          */
+#define  ADC_CR2_IOSH2_AMPEN                  ((uint32_t)0x00001000)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH2_SMPEN                  ((uint32_t)0x00002000)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH2_SEL                    ((uint32_t)0x00004000)       /*!< Vrefint enable */
+#define  ADC_CR2_IOSH2_SMPMOD                 ((uint32_t)0x00008000)       /*!< SMPMOD          */
+
+/*******************  Bit definition for ADC_ETCR register  ********************/
+#define  ADC_ETCR_EXTMOD                      ((uint32_t)0x80000000)       /*!< EXTMOD  BIT              */
+#define  ADC_ETCR_TRGDISSMP                   ((uint32_t)0x40000000)       /*!< TRGDISSMP  BIT          */
+#define  ADC_ETCR_EXTDLY                      ((uint32_t)0x000003FF)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_0                    ((uint32_t)0x00000001)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_1                    ((uint32_t)0x00000002)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_2                    ((uint32_t)0x00000004)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_3                    ((uint32_t)0x00000008)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_4                    ((uint32_t)0x00000010)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_5                    ((uint32_t)0x00000020)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_6                    ((uint32_t)0x00000040)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_7                    ((uint32_t)0x00000080)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_8                    ((uint32_t)0x00000100)       /*!< EXTDLY           */
+#define  ADC_ETCR_EXTDLY_9                    ((uint32_t)0x00000200)       /*!< EXTDLY           */
+
+/*******************  Bit definition for ADC_RTENR register  ********************/
+#define  ADC_RTENR_RTEN                       ((uint32_t)0x0007FFFF)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_0                     ((uint32_t)0x00000001)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_1                     ((uint32_t)0x00000002)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_2                     ((uint32_t)0x00000004)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_3                     ((uint32_t)0x00000008)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_4                     ((uint32_t)0x00000010)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_5                     ((uint32_t)0x00000020)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_6                     ((uint32_t)0x00000040)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_7                     ((uint32_t)0x00000080)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_8                     ((uint32_t)0x00000100)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_9                     ((uint32_t)0x00000200)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_10                    ((uint32_t)0x00000400)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_11                    ((uint32_t)0x00000800)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_12                    ((uint32_t)0x00001000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_13                    ((uint32_t)0x00002000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_14                    ((uint32_t)0x00004000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_15                    ((uint32_t)0x00008000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_16                    ((uint32_t)0x00010000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_17                    ((uint32_t)0x00020000)       /*!< RTEN             */
+#define  ADC_RTENR_RTEN_18                    ((uint32_t)0x00040000)       /*!< RTEN             */
+
+/*******************  Bit definition for ADC_FTENR register  ********************/
+#define  ADC_FTENR_FTEN                       ((uint32_t)0x0007FFFF)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_0                     ((uint32_t)0x00000001)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_1                     ((uint32_t)0x00000002)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_2                     ((uint32_t)0x00000004)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_3                     ((uint32_t)0x00000008)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_4                     ((uint32_t)0x00000010)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_5                     ((uint32_t)0x00000020)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_6                     ((uint32_t)0x00000040)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_7                     ((uint32_t)0x00000080)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_8                     ((uint32_t)0x00000100)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_9                     ((uint32_t)0x00000200)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_10                    ((uint32_t)0x00000400)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_11                    ((uint32_t)0x00000800)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_12                    ((uint32_t)0x00001000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_13                    ((uint32_t)0x00002000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_14                    ((uint32_t)0x00004000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_15                    ((uint32_t)0x00008000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_16                    ((uint32_t)0x00010000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_17                    ((uint32_t)0x00020000)       /*!< FTEN             */
+#define  ADC_FTENR_FTEN_18                    ((uint32_t)0x00040000)       /*!< FTEN             */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* NCOMP bits definition */
+#define COMP_CSR_NCOMPEN                     ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_NCOMP_VIP_SEL               ((uint32_t)0x0000000e) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_NCOMP_VIP_SEL_2             ((uint32_t)0x00000008) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_NCOMP_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL                 ((uint32_t)0x00000700) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_0               ((uint32_t)0x00000100) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_1               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_NCOMPOUTSEL_2               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_NCOMP_POL                   ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP1OUT                    ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_NCOMPLOCK                   ((uint32_t)0x00008000) /*!<  */
+
+/* PCOMP bits definition */
+#define COMP_CSR_PCOMPEN                     ((uint32_t)0x00010000) /*!< PCOMP enable */
+#define COMP_CSR_PCOMP_VIP_SEL               ((uint32_t)0x000E0000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_0             ((uint32_t)0x00020000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_1             ((uint32_t)0x00040000) /*!<  */
+#define COMP_CSR_PCOMP_VIP_SEL_2             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL               ((uint32_t)0x00300000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_0             ((uint32_t)0x00080000) /*!<  */
+#define COMP_CSR_PCOMP_VIN_SEL_1             ((uint32_t)0x00100000) /*!<  */
+#define COMP_CSR_WNDWEN                      ((uint32_t)0x00800000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL                 ((uint32_t)0x07000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_0               ((uint32_t)0x01000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_1               ((uint32_t)0x02000000) /*!<  */
+#define COMP_CSR_PCOMPOUTSEL_2               ((uint32_t)0x04000000) /*!<  */
+#define COMP_CSR_PCOMP_POL                   ((uint32_t)0x08000000) /*!<  */
+#define COMP_CSR_COMP2OUT                    ((uint32_t)0x40000000) /*!<  */
+#define COMP_CSR_PCOMP_LOCK                  ((uint32_t)0x80000000) /*!<  */
+/***********************  Bit definition for COMP_CSR2 register  ***************/
+#define COMP_CSR_COMP3EN                     ((uint32_t)0x00000001) /*!< MCOMP enable */
+#define COMP_CSR_COMP3_VIP_SEL               ((uint32_t)0x00000006) /*!<  */
+#define COMP_CSR_COMP3_VIP_SEL_0             ((uint32_t)0x00000002) /*!<  */
+#define COMP_CSR_COMP3_VIP_SEL_1             ((uint32_t)0x00000004) /*!<  */
+#define COMP_CSR_COMP3_VIN_SEL               ((uint32_t)0x00000030) /*!<  */
+#define COMP_CSR_COMP3_VIN_SEL_0             ((uint32_t)0x00000010) /*!<  */
+#define COMP_CSR_COMP3_VIN_SEL_1             ((uint32_t)0x00000020) /*!<  */
+#define COMP_CSR_COMP3OUTSEL                 ((uint32_t)0x00000700) /*!<  */
+#define COMP_CSR_COMP3OUTSEL_0               ((uint32_t)0x00000100) /*!<  */
+#define COMP_CSR_COMP3OUTSEL_1               ((uint32_t)0x00000200) /*!<  */
+#define COMP_CSR_COMP3OUTSEL_2               ((uint32_t)0x00000400) /*!<  */
+#define COMP_CSR_COMP3_POL                   ((uint32_t)0x00000800) /*!<  */
+#define COMP_CSR_COMP3OUT                    ((uint32_t)0x00004000) /*!<  */
+#define COMP_CSR_COMP3LOCK                   ((uint32_t)0x00008000) /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+//#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for FT32F072XB devices)*/
+//#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for FT32F072XB devices) */
+//#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for FT32F072XB devices) */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+//#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for FT32F072XB devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                   (Available only for FT32F072XB devices)                */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
+#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
+#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
+#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
+#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
+#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
+#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
+#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
+#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
+#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
+#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
+#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
+#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
+#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
+#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
+#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
+#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
+#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
+#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
+#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
+#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
+#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
+#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
+#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_EN         ((uint32_t)(0x00000001))
+#define DAC_CTRL_REF_SEL    ((uint32_t)(0x00000006))
+#define DAC_CTRL_REF_SEL_0  ((uint32_t)(0x00000002))        /*!< Bit 0 */
+#define DAC_CTRL_REF_SEL_1  ((uint32_t)(0x00000004))        /*!< Bit 1 */
+#define DAC1_BOE            ((uint32_t)(0x00000008))        // DAC1 Out enable
+#define DAC2_BOE            ((uint32_t)(0x00000010))        // DAC2 Out enable
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+//#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+//
+//#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+//#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+//#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+//#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+//#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+//#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+//#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+//#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+//#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+//#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+//#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+//#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+//#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+//#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+//#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_DESIGNER                              ((uint32_t)0x00000FFE)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_PARTNO                                  ((uint32_t)0x0FFFF000)        /*!< Device Identifier */
+#define  DBGMCU_IDCODE_PARTNO_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_PARTNO_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_PARTNO_2                ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_PARTNO_3                ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_PARTNO_4                ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_PARTNO_5                ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_PARTNO_6                ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_PARTNO_7                ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_PARTNO_8                ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_PARTNO_9                ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_PARTNO_10               ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_PARTNO_11               ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_PARTNO_12               ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_PARTNO_13               ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_PARTNO_14               ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_PARTNO_15               ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+#define  DBGMCU_IDCODE_VERSION                               ((uint32_t)0xF0000000)        /*!< Device Identifier */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+//#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for FT32F072XB devices) */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x20000000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+//#define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for FT32F072XB devices) */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+/******************************************************************************/
+/*                                                                            */
+/*                           DIV Controller (DIV)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DIV_SC register  ********************/
+#define  DIV_SC_DIVBUSY                      ((uint32_t)0x00000001)        /*!< Division running flag   */
+#define  DIV_SC_DIV0ERR                      ((uint32_t)0x00000002)        /*!< Division by 0 error interrupt flag    */
+#define  DIV_SC_DIV0IE                       ((uint32_t)0x00000004)        /*!< Division by 0 error interrupt enable  */
+#define  DIV_SC_DIVOV                        ((uint32_t)0x00000008)        /*!< Overflow interrupt interrupt flag    */
+#define  DIV_SC_DIVOVIE                      ((uint32_t)0x00000010)        /*!< Overflow interrupt enable    */
+#define  DIV_SC_DIV0ERRC                     ((uint32_t)0x00000200)        /*!< Division by 0 interrupt clear   */
+#define  DIV_SC_DIVOVC                       ((uint32_t)0x00000800)        /*!< Overflow interrupt clear    */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           OPA Controller (OPA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for OPA register  ********************/
+#define OPA_OP1_OUT                         ((uint32_t)0x00010000)        /*!< OP1 OUT STATE                                */
+#define OPA_OP1_PSEL                        ((uint32_t)0x00008000)        /*!< OP1 normal phase input selection             */
+#define OPA_OP1_NSEL                        ((uint32_t)0x00006000)        /*!< OP1 inverting terminal input selection       */
+#define OPA_OP1_NSEL_0                      ((uint32_t)0x00002000)        /*!< OP1 inverting terminal input selection BIT0  */
+#define OPA_OP1_NSEL_1                      ((uint32_t)0x00004000)        /*!< OP1 inverting terminal input selection BIT1  */
+#define OPA_OP1_FR                          ((uint32_t)0x00001C00)        /*!< OP1 feedback resistor selection              */
+#define OPA_OP1_FR_0                        ((uint32_t)0x00000400)        /*!< OP1 feedback resistor selection BIT0         */
+#define OPA_OP1_FR_1                        ((uint32_t)0x00000800)        /*!< OP1 feedback resistor selection BIT1         */
+#define OPA_OP1_FR_2                        ((uint32_t)0x00001000)        /*!< OP1 feedback resistor selection BIT2         */
+#define OPA_OP1_FCAPE                       ((uint32_t)0x00000200)        /*!< OP1 compensation capacitor enable BIT        */
+#define OPA_OP1_TM                          ((uint32_t)0x00000100)        /*!< OP1 input misalignment calibration mode      */
+#define OPA_OP1_TODIG                       ((uint32_t)0x00000080)        /*!< OP1 outputs to the register control bit      */
+#define OPA_OP1_TOIO                        ((uint32_t)0x00000040)        /*!< OP1 outputs to the ENABLE bit of PA0         */
+#define OPA_OP1_COF                         ((uint32_t)0x0000003E)        /*!< OP1 input misalignment calibration           */
+#define OPA_OP1_COF_0                       ((uint32_t)0x00000002)        /*!< OP1 input misalignment calibration BIT0      */
+#define OPA_OP1_COF_1                       ((uint32_t)0x00000004)        /*!< OP1 input misalignment calibration BIT1      */
+#define OPA_OP1_COF_2                       ((uint32_t)0x00000008)        /*!< OP1 input misalignment calibration BIT2      */
+#define OPA_OP1_COF_3                       ((uint32_t)0x00000010)        /*!< OP1 input misalignment calibration BIT3      */
+#define OPA_OP1_COF_4                       ((uint32_t)0x00000020)        /*!< OP1 input misalignment calibration BIT4      */
+#define OPA_OP1_ON                          ((uint32_t)0x00000001)        /*!< OP1 enable BIT                               */
+
+#define OPA_OP2_PRMAP                       ((uint32_t)0x00020000)        /*!< OP2                                          */
+#define OPA_OP2_OUT                         ((uint32_t)0x00010000)        /*!< OP2 OUT STATE                                */
+#define OPA_OP2_PSEL                        ((uint32_t)0x00008000)        /*!< OP2 normal phase input selection             */
+#define OPA_OP2_NSEL                        ((uint32_t)0x00006000)        /*!< OP2 inverting terminal input selection       */
+#define OPA_OP2_NSEL_0                      ((uint32_t)0x00002000)        /*!< OP2 inverting terminal input selection BIT0  */
+#define OPA_OP2_NSEL_1                      ((uint32_t)0x00004000)        /*!< OP2 inverting terminal input selection BIT1  */
+#define OPA_OP2_FR                          ((uint32_t)0x00001C00)        /*!< OP2 feedback resistor selection              */
+#define OPA_OP2_FR_0                        ((uint32_t)0x00000400)        /*!< OP2 feedback resistor selection BIT0         */
+#define OPA_OP2_FR_1                        ((uint32_t)0x00000800)        /*!< OP2 feedback resistor selection BIT1         */
+#define OPA_OP2_FR_2                        ((uint32_t)0x00001000)        /*!< OP2 feedback resistor selection BIT2         */
+#define OPA_OP2_FCAPE                       ((uint32_t)0x00000200)        /*!< OP2 compensation capacitor enable BIT        */
+#define OPA_OP2_TM                          ((uint32_t)0x00000100)        /*!< OP2 input misalignment calibration mode      */
+#define OPA_OP2_TODIG                       ((uint32_t)0x00000080)        /*!< OP2 outputs to the register control bit      */
+#define OPA_OP2_TOIO                        ((uint32_t)0x00000040)        /*!< OP2 outputs to the ENABLE bit of PA0         */
+#define OPA_OP2_COF                         ((uint32_t)0x0000003E)        /*!< OP2 input misalignment calibration           */
+#define OPA_OP2_COF_0                       ((uint32_t)0x00000002)        /*!< OP2 input misalignment calibration BIT0      */
+#define OPA_OP2_COF_1                       ((uint32_t)0x00000004)        /*!< OP2 input misalignment calibration BIT1      */
+#define OPA_OP2_COF_2                       ((uint32_t)0x00000008)        /*!< OP2 input misalignment calibration BIT2      */
+#define OPA_OP2_COF_3                       ((uint32_t)0x00000010)        /*!< OP2 input misalignment calibration BIT3      */
+#define OPA_OP2_COF_4                       ((uint32_t)0x00000020)        /*!< OP2 input misalignment calibration BIT4      */
+#define OPA_OP2_ON                          ((uint32_t)0x00000001)        /*!< OP2 enable BIT                               */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+//#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for FT32F072XB devices) */
+//#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for FT32F072XB devices) */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+//#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for FT32F072XB devices) */
+//#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for FT32F072XB devices) */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+#define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
+#define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
+#define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+#define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
+#define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
+#define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+//#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+//#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+//#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+//#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_MAS2K                      ((uint32_t)0x00000008)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
+
+//#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+//#define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+//#define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
+//#define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW*/
+#define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
+#define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP2 register  *********************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for FT32F072XB devices) */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for FT32F072XB devices) */
+
+/******************  Bit definition for OB_WRP3 register  *********************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for FT32F072XB devices) */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for FT32F072XB devices) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+#define GPIO_BRR_BR0               GPIO_BRR_BR_0
+#define GPIO_BRR_BR1               GPIO_BRR_BR_1
+#define GPIO_BRR_BR2               GPIO_BRR_BR_2
+#define GPIO_BRR_BR3               GPIO_BRR_BR_3
+#define GPIO_BRR_BR4               GPIO_BRR_BR_4
+#define GPIO_BRR_BR5               GPIO_BRR_BR_5
+#define GPIO_BRR_BR6               GPIO_BRR_BR_6
+#define GPIO_BRR_BR7               GPIO_BRR_BR_7
+#define GPIO_BRR_BR8               GPIO_BRR_BR_8
+#define GPIO_BRR_BR9               GPIO_BRR_BR_9
+#define GPIO_BRR_BR10              GPIO_BRR_BR_10
+#define GPIO_BRR_BR11              GPIO_BRR_BR_11
+#define GPIO_BRR_BR12              GPIO_BRR_BR_12
+#define GPIO_BRR_BR13              GPIO_BRR_BR_13
+#define GPIO_BRR_BR14              GPIO_BRR_BR_14
+#define GPIO_BRR_BR15              GPIO_BRR_BR_15
+
+/*******************  Bit definition for GPIO_LEDM register  *******************/
+#define GPIOA_LEDM_LEDM8                    ((uint32_t)0x00000100)
+#define GPIOA_LEDM_LEDM9                    ((uint32_t)0x00000200)
+#define GPIOA_LEDM_LEDM10                   ((uint32_t)0x00000400)
+#define GPIOA_LEDM_LEDM13                   ((uint32_t)0x00002000)
+#define GPIOA_LEDM_LEDM14                   ((uint32_t)0x00004000)
+#define GPIOA_LEDM_LEDM15                   ((uint32_t)0x00008000)
+
+
+#define GPIOB_LEDM_LEDM0                    ((uint32_t)0x00000001)
+#define GPIOB_LEDM_LEDM1                    ((uint32_t)0x00000002)
+#define GPIOB_LEDM_LEDM3                    ((uint32_t)0x00000008)
+#define GPIOB_LEDM_LEDM4                    ((uint32_t)0x00000010)
+#define GPIOB_LEDM_LEDM5                    ((uint32_t)0x00000020)
+#define GPIOB_LEDM_LEDM6                    ((uint32_t)0x00000040)
+#define GPIOB_LEDM_LEDM7                    ((uint32_t)0x00000080)
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+//#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+/******************************************************************************/
+/*                                                                            */
+/*                          LEB Control (LEB)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LEB_CR register  ********************/
+#define  LEB1MSK                             ((uint32_t)0x0000001F)     /*!< LEB1 shield bit */
+#define  LEB1MSK_0                           ((uint32_t)0x00000001)     /*!< LEB1 TIM1 BKIN shield bit*/
+#define  LEB1MSK_1                           ((uint32_t)0x00000002)     /*!< LEB1 COMP1 brake shield bit */
+#define  LEB1MSK_2                           ((uint32_t)0x00000004)     /*!< LEB1 COMP2 brake shield bit */
+#define  LEB1MSK_3                           ((uint32_t)0x00000008)     /*!< LEB1 COMP3 brake shield bit */
+#define  LEB1MSK_4                           ((uint32_t)0x00000010)     /*!< LEB1 PVD brake shield bit */
+#define  LEB2MSK                             ((uint32_t)0x00001F00)     /*!< LEB2 shield bit */
+#define  LEB2MSK_0                           ((uint32_t)0x00000100)     /*!< LEB2 TIM1 BKIN shield bit*/
+#define  LEB2MSK_1                           ((uint32_t)0x00000200)     /*!< LEB2 COMP1 brake shield bit */
+#define  LEB2MSK_2                           ((uint32_t)0x00000400)     /*!< LEB2 COMP2 brake shield bit */
+#define  LEB2MSK_3                           ((uint32_t)0x00000800)     /*!< LEB2 COMP3 brake shield bit */
+#define  LEB2MSK_4                           ((uint32_t)0x00001000)     /*!< LEB2 PVD brake shield bit */
+#define  LEB3MSK                             ((uint32_t)0x001F0000)     /*!< LEB3 shield bit */
+#define  LEB3MSK_0                           ((uint32_t)0x00010000)     /*!< LEB3 TIM1 BKIN shield bit*/
+#define  LEB3MSK_1                           ((uint32_t)0x00020000)     /*!< LEB3 COMP1 brake shield bit */
+#define  LEB3MSK_2                           ((uint32_t)0x00040000)     /*!< LEB3 COMP2 brake shield bit */
+#define  LEB3MSK_3                           ((uint32_t)0x00080000)     /*!< LEB3 COMP3 brake shield bit */
+#define  LEB3MSK_4                           ((uint32_t)0x00100000)     /*!< LEB3 PVD brake shield bit */
+/********************  Bit definition for FLT_CFG1 register  ********************/
+#define  IOFLTEN                             ((uint32_t)0x00000001)     /*!< IO filter enable */
+#define  IOFLTSW                             ((uint32_t)0x00000002)     /*!< IO filter clock select */
+#define  IOFLTPS                             ((uint32_t)0x0000003C)     /*!< IO filter clock divide */
+#define  IOFLTPS_0                           ((uint32_t)0x00000004)     /*!< IO filter clock divide bit 0 */
+#define  IOFLTPS_1                           ((uint32_t)0x00000008)     /*!< IO filter clock divide bit 1  */
+#define  IOFLTPS_2                           ((uint32_t)0x00000010)     /*!< IO filter clock divide bit 2  */
+#define  IOFLTPS_3                           ((uint32_t)0x00000020)     /*!< IO filter clock divide bit 3  */
+#define  IOFLTSMP                            ((uint32_t)0x000003C0)     /*!< IO filter vote sampled times  */
+#define  IOFLTSMP_0                          ((uint32_t)0x00000040)     /*!< IO filter vote sampled times bit 0 */
+#define  IOFLTSMP_1                          ((uint32_t)0x00000080)     /*!< IO filter vote sampled times bit 1 */
+#define  IOFLTSMP_2                          ((uint32_t)0x00000100)     /*!< IO filter vote sampled times bit 2 */
+#define  IOFLTSMP_3                          ((uint32_t)0x00000200)     /*!< IO filter vote sampled times bit 3 */
+#define  IOSEL                               ((uint32_t)0x00003000)     /*!< Trigger IO select*/
+#define  IOSEL_0                             ((uint32_t)0x00001000)     /*!< Trigger IO select bit 0 */
+#define  IOSEL_1                             ((uint32_t)0x00002000)     /*!< Trigger IO select bit 1  */
+#define  C1FLTEN                             ((uint32_t)0x00010000)     /*!< COM1 filter enable */
+#define  C1FLTSW                             ((uint32_t)0x00020000)     /*!< COM1 filter clock select */
+#define  C1FLTPS                             ((uint32_t)0x003C0000)     /*!< COM1 filter clock divide */
+#define  C1FLTPS_0                           ((uint32_t)0x00040000)     /*!< COM1 filter clock divide bit 0 */
+#define  C1FLTPS_1                           ((uint32_t)0x00080000)     /*!< COM1 filter clock divide bit 1  */
+#define  C1FLTPS_2                           ((uint32_t)0x00100000)     /*!< COM1 filter clock divide bit 2  */
+#define  C1FLTPS_3                           ((uint32_t)0x00200000)     /*!< COM1 filter clock divide bit 3  */
+#define  C1FLTSMP                            ((uint32_t)0x03C00000)     /*!< COM1 filter vote sampled times  */
+#define  C1FLTSMP_0                          ((uint32_t)0x00400000)     /*!< COM1 filter vote sampled times bit 0 */
+#define  C1FLTSMP_1                          ((uint32_t)0x00800000)     /*!< COM1 filter vote sampled times bit 1 */
+#define  C1FLTSMP_2                          ((uint32_t)0x01000000)     /*!< COM1 filter vote sampled times bit 2 */
+#define  C1FLTSMP_3                          ((uint32_t)0x02000000)     /*!< COM1 filter vote sampled times bit 3 */
+#define  C1OUTM                              ((uint32_t)0x04000000)     /*!< COM1 out mode select*/
+#define  C1OUTSEL                            ((uint32_t)0x08000000)     /*!< COM1 out select */
+/********************  Bit definition for FLT_CFG2 register  ********************/
+#define  C2FLTEN                             ((uint32_t)0x00000001)     /*!< COM2 filter enable */
+#define  C2FLTSW                             ((uint32_t)0x00000002)     /*!< COM2 filter clock select */
+#define  C2FLTPS                             ((uint32_t)0x0000003C)     /*!< COM2 filter clock divide */
+#define  C2FLTPS_0                           ((uint32_t)0x00000004)     /*!< COM2 filter clock divide bit 0 */
+#define  C2FLTPS_1                           ((uint32_t)0x00000008)     /*!< COM2 filter clock divide bit 1  */
+#define  C2FLTPS_2                           ((uint32_t)0x00000010)     /*!< COM2 filter clock divide bit 2  */
+#define  C2FLTPS_3                           ((uint32_t)0x00000020)     /*!< COM2 filter clock divide bit 3  */
+#define  C2FLTSMP                            ((uint32_t)0x000003C0)     /*!< COM2 filter vote sampled times  */
+#define  C2FLTSMP_0                          ((uint32_t)0x00000040)     /*!< COM2 filter vote sampled times bit 0 */
+#define  C2FLTSMP_1                          ((uint32_t)0x00000080)     /*!< COM2 filter vote sampled times bit 1 */
+#define  C2FLTSMP_2                          ((uint32_t)0x00000100)     /*!< COM2 filter vote sampled times bit 2 */
+#define  C2FLTSMP_3                          ((uint32_t)0x00000200)     /*!< COM2 filter vote sampled times bit 3 */
+#define  C2OUTM                              ((uint32_t)0x00000400)     /*!< COM2 out mode select*/
+#define  C2OUTSEL                            ((uint32_t)0x00000800)     /*!< COM2 out select */
+#define  C3FLTEN                             ((uint32_t)0x00010000)     /*!< COM3 filter enable */
+#define  C3FLTSW                             ((uint32_t)0x00020000)     /*!< COM3 filter clock select */
+#define  C3FLTPS                             ((uint32_t)0x003C0000)     /*!< COM3 filter clock divide */
+#define  C3FLTPS_0                           ((uint32_t)0x00040000)     /*!< COM3 filter clock divide bit 0 */
+#define  C3FLTPS_1                           ((uint32_t)0x00080000)     /*!< COM3 filter clock divide bit 1  */
+#define  C3FLTPS_2                           ((uint32_t)0x00100000)     /*!< COM3 filter clock divide bit 2  */
+#define  C3FLTPS_3                           ((uint32_t)0x00200000)     /*!< COM3 filter clock divide bit 3  */
+#define  C3FLTSMP                            ((uint32_t)0x03C00000)     /*!< COM3 filter vote sampled times  */
+#define  C3FLTSMP_0                          ((uint32_t)0x00400000)     /*!< COM3 filter vote sampled times bit 0 */
+#define  C3FLTSMP_1                          ((uint32_t)0x00800000)     /*!< COM3 filter vote sampled times bit 1 */
+#define  C3FLTSMP_2                          ((uint32_t)0x01000000)     /*!< COM3 filter vote sampled times bit 2 */
+#define  C3FLTSMP_3                          ((uint32_t)0x02000000)     /*!< COM3 filter vote sampled times bit 3 */
+#define  C3OUTM                              ((uint32_t)0x04000000)     /*!< COM3 out mode select*/
+#define  C3OUTSEL                            ((uint32_t)0x08000000)     /*!< COM3 out select */
+/********************  Bit definition for LEB_CFG register  ********************/
+#define  IO_LEBRTEN                          ((uint32_t)0x00000001)     /*!< Rising edge trigger LEB enable */
+#define  IO_LEBFTEN                          ((uint32_t)0x00000100)     /*!< Falling  edge trigger LEB enable */
+#define  IO_LEBHEN                           ((uint32_t)0x00010000)     /*!< High level shield COMP enable */
+#define  IO_LEBLEN                           ((uint32_t)0x01000000)     /*!< Low level shield COMP enable */
+/********************  Bit definition for LEB1_CFG register  ********************/
+#define  LEB1RTEN                             ((uint32_t)0x0000007F)     /*!< LEB1 rising  shield enable*/
+#define  LEB1RTEN_0                           ((uint32_t)0x00000001)     /*!< TIM1_OC1 */
+#define  LEB1RTEN_1                           ((uint32_t)0x00000002)     /*!< TIM1_OC2 */
+#define  LEB1RTEN_2                           ((uint32_t)0x00000004)     /*!< TIM1_OC3 */
+#define  LEB1RTEN_3                           ((uint32_t)0x00000008)     /*!< TIM1_OC4 */
+#define  LEB1RTEN_4                           ((uint32_t)0x00000010)     /*!< TIM1_OC1N */
+#define  LEB1RTEN_5                           ((uint32_t)0x00000020)     /*!< TIM1_OC2N */
+#define  LEB1RTEN_6                           ((uint32_t)0x00000040)     /*!< TIM1_OC3N */
+#define  LEB1FTEN                             ((uint32_t)0x00007F00)     /*!< LEB1 falling  shield enable */
+#define  LEB1FTEN_0                           ((uint32_t)0x00000100)     /*!< TIM1_OC1 */
+#define  LEB1FTEN_1                           ((uint32_t)0x00000200)     /*!< TIM1_OC2 */
+#define  LEB1FTEN_2                           ((uint32_t)0x00000400)     /*!< TIM1_OC3 */
+#define  LEB1FTEN_3                           ((uint32_t)0x00000800)     /*!< TIM1_OC4 */
+#define  LEB1FTEN_4                           ((uint32_t)0x00001000)     /*!< TIM1_OC1N */
+#define  LEB1FTEN_5                           ((uint32_t)0x00002000)     /*!< TIM1_OC2N */
+#define  LEB1FTEN_6                           ((uint32_t)0x00004000)     /*!< TIM1_OC3N */
+#define  LEB1HEN                              ((uint32_t)0x007F0000)     /*!< PWM high livel shield enable */
+#define  LEB1HEN_0                            ((uint32_t)0x00010000)     /*!< TIM1_OC1 */
+#define  LEB1HEN_1                            ((uint32_t)0x00020000)     /*!< TIM1_OC2 */
+#define  LEB1HEN_2                            ((uint32_t)0x00040000)     /*!< TIM1_OC3 */
+#define  LEB1HEN_3                            ((uint32_t)0x00080000)     /*!< TIM1_OC4 */
+#define  LEB1HEN_4                            ((uint32_t)0x00100000)     /*!< TIM1_OC1N */
+#define  LEB1HEN_5                            ((uint32_t)0x00200000)     /*!< TIM1_OC2N */
+#define  LEB1HEN_6                            ((uint32_t)0x00400000)     /*!< TIM1_OC3N */
+#define  LEB1LEN                              ((uint32_t)0x7F000000)     /*!< PWM low livel shield enable */
+#define  LEB1LEN_0                            ((uint32_t)0x01000000)     /*!< TIM1_OC1 */
+#define  LEB1LEN_1                            ((uint32_t)0x02000000)     /*!< TIM1_OC2 */
+#define  LEB1LEN_2                            ((uint32_t)0x04000000)     /*!< TIM1_OC3 */
+#define  LEB1LEN_3                            ((uint32_t)0x08000000)     /*!< TIM1_OC4 */
+#define  LEB1LEN_4                            ((uint32_t)0x10000000)     /*!< TIM1_OC1N */
+#define  LEB1LEN_5                            ((uint32_t)0x20000000)     /*!< TIM1_OC2N */
+#define  LEB1LEN_6                            ((uint32_t)0x40000000)     /*!< TIM1_OC3N */
+/********************  Bit definition for LEB2_CFG register  ********************/
+#define  LEB2RTEN                             ((uint32_t)0x0000000F)     /*!< LEB2 rising  shield enable */
+#define  LEB2RTEN_0                           ((uint32_t)0x00000001)     /*!< TIM3_OC1 */
+#define  LEB2RTEN_1                           ((uint32_t)0x00000002)     /*!< TIM3_OC2 */
+#define  LEB2RTEN_2                           ((uint32_t)0x00000004)     /*!< TIM3_OC3 */
+#define  LEB2RTEN_3                           ((uint32_t)0x00000008)     /*!< TIM3_OC4 */
+#define  LEB2FTEN                             ((uint32_t)0x00000F00)     /*!< LEB2 falling  shield enable */
+#define  LEB2FTEN_0                           ((uint32_t)0x00000100)     /*!< TIM3_OC1 */
+#define  LEB2FTEN_1                           ((uint32_t)0x00000200)     /*!< TIM3_OC2 */
+#define  LEB2FTEN_2                           ((uint32_t)0x00000400)     /*!< TIM3_OC3 */
+#define  LEB2FTEN_3                           ((uint32_t)0x00000800)     /*!< TIM3_OC4 */
+#define  LEB2HEN                              ((uint32_t)0x000F0000)     /*!< PWM high livel shield enable */
+#define  LEB2HEN_0                            ((uint32_t)0x00010000)     /*!< TIM3_OC1 */
+#define  LEB2HEN_1                            ((uint32_t)0x00020000)     /*!< TIM3_OC2 */
+#define  LEB2HEN_2                            ((uint32_t)0x00040000)     /*!< TIM3_OC3 */
+#define  LEB2HEN_3                            ((uint32_t)0x00080000)     /*!< TIM3_OC4 */
+#define  LEB2LEN                              ((uint32_t)0x0F000000)     /*!< PWM low livel shield enable */
+#define  LEB2LEN_0                            ((uint32_t)0x01000000)     /*!< TIM3_OC1 */
+#define  LEB2LEN_1                            ((uint32_t)0x02000000)     /*!< TIM3_OC2 */
+#define  LEB2LEN_2                            ((uint32_t)0x04000000)     /*!< TIM3_OC3 */
+#define  LEB2LEN_3                            ((uint32_t)0x08000000)     /*!< TIM3_OC4 */
+/********************  Bit definition for LEB3_CFG register  ********************/
+#define  LEB3RTEN                             ((uint32_t)0x00000007)     /*!< LEB3 rising  shield enable */
+#define  LEB3RTEN_0                           ((uint32_t)0x00000001)     /*!< TIM15_OC1 */
+#define  LEB3RTEN_1                           ((uint32_t)0x00000002)     /*!< TIM15_OC2 */
+#define  LEB3RTEN_2                           ((uint32_t)0x00000004)     /*!< TIM15_OC1N */
+#define  LEB3FTEN                             ((uint32_t)0x00000700)     /*!< LEB3 falling  shield enable */
+#define  LEB3FTEN_0                           ((uint32_t)0x00000100)     /*!< TIM15_OC1 */
+#define  LEB3FTEN_1                           ((uint32_t)0x00000200)     /*!< TIM15_OC2 */
+#define  LEB3FTEN_2                           ((uint32_t)0x00000400)     /*!< TIM15_OC1N */
+#define  LEB3HEN                              ((uint32_t)0x00070000)     /*!< PWM high livel shield enable */
+#define  LEB3HEN_0                            ((uint32_t)0x00010000)     /*!< TIM15_OC1 */
+#define  LEB3HEN_1                            ((uint32_t)0x00020000)     /*!< TIM15_OC2 */
+#define  LEB3HEN_2                            ((uint32_t)0x00040000)     /*!< TIM15_OC1N */
+#define  LEB3LEN                              ((uint32_t)0x07000000)     /*!< PWM low livel shield enable */
+#define  LEB3LEN_0                            ((uint32_t)0x01000000)     /*!< TIM15_OC1 */
+#define  LEB3LEN_1                            ((uint32_t)0x02000000)     /*!< TIM15_OC2 */
+#define  LEB3LEN_2                            ((uint32_t)0x04000000)     /*!< TIM15_OC1N */
+/********************  Bit definition for LEB1_PR register  ********************/
+#define  LEB1_PR                               ((uint32_t)0x000003FF)     /*!< LEB1 Blank period */
+#define  LEB1_PR_0                             ((uint32_t)0x00000001)     /*!< LEB1 Blank period bit 0 */
+#define  LEB1_PR_1                             ((uint32_t)0x00000002)     /*!< LEB1 Blank period bit 1 */
+#define  LEB1_PR_2                             ((uint32_t)0x00000004)     /*!< LEB1 Blank period bit 2 */
+#define  LEB1_PR_3                             ((uint32_t)0x00000008)     /*!< LEB1 Blank period bit 3 */
+#define  LEB1_PR_4                             ((uint32_t)0x00000010)     /*!< LEB1 Blank period bit 4 */
+#define  LEB1_PR_5                             ((uint32_t)0x00000020)     /*!< LEB1 Blank period bit 5 */
+#define  LEB1_PR_6                             ((uint32_t)0x00000040)     /*!< LEB1 Blank period bit 6 */
+#define  LEB1_PR_7                             ((uint32_t)0x00000080)     /*!< LEB1 Blank period bit 7 */
+#define  LEB1_PR_8                             ((uint32_t)0x00000100)     /*!< LEB1 Blank period bit 8 */
+#define  LEB1_PR_9                             ((uint32_t)0x00000200)     /*!< LEB1 Blank period bit 9 */
+/********************  Bit definition for LEB2_PR register  ********************/
+#define  LEB2_PR                               ((uint32_t)0x000003FF)     /*!< LEB2 Blank period */
+#define  LEB2_PR_0                             ((uint32_t)0x00000001)     /*!< LEB2 Blank period bit 0 */
+#define  LEB2_PR_1                             ((uint32_t)0x00000002)     /*!< LEB2 Blank period bit 1 */
+#define  LEB2_PR_2                             ((uint32_t)0x00000004)     /*!< LEB2 Blank period bit 2 */
+#define  LEB2_PR_3                             ((uint32_t)0x00000008)     /*!< LEB2 Blank period bit 3 */
+#define  LEB2_PR_4                             ((uint32_t)0x00000010)     /*!< LEB2 Blank period bit 4 */
+#define  LEB2_PR_5                             ((uint32_t)0x00000020)     /*!< LEB2 Blank period bit 5 */
+#define  LEB2_PR_6                             ((uint32_t)0x00000040)     /*!< LEB2 Blank period bit 6 */
+#define  LEB2_PR_7                             ((uint32_t)0x00000080)     /*!< LEB2 Blank period bit 7 */
+#define  LEB2_PR_8                             ((uint32_t)0x00000100)     /*!< LEB2 Blank period bit 8 */
+#define  LEB2_PR_9                             ((uint32_t)0x00000200)     /*!< LEB2 Blank period bit 9 */
+/********************  Bit definition for LEB3_PR register  ********************/
+#define  LEB3_PR                               ((uint32_t)0x000003FF)     /*!< LEB3 Blank period */
+#define  LEB3_PR_0                             ((uint32_t)0x00000001)     /*!< LEB3 Blank period bit 0 */
+#define  LEB3_PR_1                             ((uint32_t)0x00000002)     /*!< LEB3 Blank period bit 1 */
+#define  LEB3_PR_2                             ((uint32_t)0x00000004)     /*!< LEB3 Blank period bit 2 */
+#define  LEB3_PR_3                             ((uint32_t)0x00000008)     /*!< LEB3 Blank period bit 3 */
+#define  LEB3_PR_4                             ((uint32_t)0x00000010)     /*!< LEB3 Blank period bit 4 */
+#define  LEB3_PR_5                             ((uint32_t)0x00000020)     /*!< LEB3 Blank period bit 5 */
+#define  LEB3_PR_6                             ((uint32_t)0x00000040)     /*!< LEB3 Blank period bit 6 */
+#define  LEB3_PR_7                             ((uint32_t)0x00000080)     /*!< LEB3 Blank period bit 7 */
+#define  LEB3_PR_8                             ((uint32_t)0x00000100)     /*!< LEB3 Blank period bit 8 */
+#define  LEB3_PR_9                             ((uint32_t)0x00000200)     /*!< LEB3 Blank period bit 9 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          One Wire (ONEW)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ONEW_CFG register  ********************/
+#define  ONEW_CFG_PDB                          ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep */
+#define  ONEW_CFG_HWMOD                        ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
+#define  ONEW_CFG_DMAEN                        ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
+#define  ONEW_CFG_DEBEN                        ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
+#define  ONEW_CFG_LSBF                         ((uint32_t)0x00000010)     /*!< Clear Standby Flag */
+#define  ONEW_CFG_PDGE                         ((uint32_t)0x00000020)     /*!< Clear Standby Flag */
+/********************  Bit definition for ONEW_BUF register  ********************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x02E0)     /*!< PLS[3] PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x0200)     /*!< Bit 3 */
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!<       */
+
+/* PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV8                     ((uint16_t)0x0200)     /*!< PVD level 8 */
+#define  PWR_CR_PLS_LEV9                     ((uint16_t)0x0220)     /*!< PVD level 9 */
+#define  PWR_CR_PLS_LEV10                    ((uint16_t)0x0240)     /*!< PVD level 10 */
+#define  PWR_CR_PLS_LEV11                    ((uint16_t)0x0260)     /*!< PVD level 11 */
+#define  PWR_CR_PLS_LEV12                    ((uint16_t)0x0280)     /*!< PVD level 12 */
+#define  PWR_CR_PLS_LEV13                    ((uint16_t)0x02A0)     /*!< PVD level 13 */
+#define  PWR_CR_PLS_LEV14                    ((uint16_t)0x02C0)     /*!< PVD level 14 */
+#define  PWR_CR_PLS_LEV15                    ((uint16_t)0x02E0)     /*!< PVD level 15 */
+
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+//#define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+//#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+//#define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
+//#define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
+//#define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
+//#define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
+//#define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+//#define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+/* SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+/* SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+/* HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+/* PPRE configuration */
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+                                                                                done inside the ADC_CFGR2 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the FT32F072XB devices) */
+#define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
+                                                                                Old PREDIV1 bit definition, maintained for legacy purpose */
+#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
+                                                                                (This bit and configuration is only available for FT32F072XB devices)*/
+#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+/* MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_MCOPRE                     RCC_CFGR_MCO_PRE            /*!< MCO prescaler*/
+#define  RCC_CFGR_MCOPRE_1                   RCC_CFGR_MCO_PRE_1          /*!< MCO is divided by 1*/
+#define  RCC_CFGR_MCOPRE_2                   RCC_CFGR_MCO_PRE_2          /*!< MCO is divided by 2*/
+#define  RCC_CFGR_MCOPRE_4                   RCC_CFGR_MCO_PRE_4          /*!< MCO is divided by 4*/
+#define  RCC_CFGR_MCOPRE_8                   RCC_CFGR_MCO_PRE_8          /*!< MCO is divided by 8*/
+#define  RCC_CFGR_MCOPRE_16                  RCC_CFGR_MCO_PRE_16         /*!< MCO is divided by 16*/
+#define  RCC_CFGR_MCOPRE_32                  RCC_CFGR_MCO_PRE_32         /*!< MCO is divided by 32*/
+#define  RCC_CFGR_MCOPRE_64                  RCC_CFGR_MCO_PRE_64         /*!< MCO is divided by 64*/
+#define  RCC_CFGR_MCOPRE_128                 RCC_CFGR_MCO_PRE_128        /*!< MCO is divided by 128*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */
+
+/*******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+//#define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+//#define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
+//#define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
+//#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+//#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+//#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+//#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
+//#define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
+//#define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
+//#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
+#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+//#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+//#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
+//#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+//#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
+
+#define  RCC_AHBENR_IOPAEN                  RCC_AHBENR_GPIOAEN          /*!< GPIOA clock enable */
+#define  RCC_AHBENR_IOPBEN                  RCC_AHBENR_GPIOBEN          /*!< GPIOB clock enable */
+#define  RCC_AHBENR_IOPCEN                  RCC_AHBENR_GPIOCEN          /*!< GPIOC clock enable */
+#define  RCC_AHBENR_IOPDEN                  RCC_AHBENR_GPIODEN          /*!< GPIOD clock enable */
+
+#define  RCC_AHBENR_IOPFEN                  RCC_AHBENR_GPIOFEN          /*!< GPIOF clock enable */
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
+//#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
+//#define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
+//#define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
+#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+//#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+//#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+//#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
+//#define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
+//#define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+//#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
+#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+//#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+//#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000038)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  RCC_BDCR_LSEDRV_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/* RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCISO                     ((uint32_t)0x00002000)        /*!<  */
+#define  RCC_BDCR_RTCPD                      ((uint32_t)0x00004000)        /*!<   */
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+//#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+
+#define  RCC_AHBRSTR_IOPARST                 RCC_AHBRSTR_GPIOARST
+#define  RCC_AHBRSTR_IOPBRST                 RCC_AHBRSTR_GPIOBRST
+#define  RCC_AHBRSTR_IOPCRST                 RCC_AHBRSTR_GPIOCRST
+#define  RCC_AHBRSTR_IOPDRST                 RCC_AHBRSTR_GPIODRST
+#define  RCC_AHBRSTR_IOPFRST                 RCC_AHBRSTR_GPIOFRST
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/* PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/* Old Bit definition maintained for legacy purpose */
+#define  RCC_CFGR2_PREDIV                  RCC_CFGR2_PREDIV1
+#define  RCC_CFGR2_PREDIV_0                RCC_CFGR2_PREDIV1_0
+#define  RCC_CFGR2_PREDIV_1                RCC_CFGR2_PREDIV1_1
+#define  RCC_CFGR2_PREDIV_2                RCC_CFGR2_PREDIV1_2
+#define  RCC_CFGR2_PREDIV_3                RCC_CFGR2_PREDIV1_3
+
+#define  RCC_CFGR2_PREDIV_DIV1             RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_CFGR2_PREDIV_DIV2             RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_CFGR2_PREDIV_DIV3             RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_CFGR2_PREDIV_DIV4             RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_CFGR2_PREDIV_DIV5             RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_CFGR2_PREDIV_DIV6             RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_CFGR2_PREDIV_DIV7             RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_CFGR2_PREDIV_DIV8             RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_CFGR2_PREDIV_DIV9             RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_CFGR2_PREDIV_DIV10            RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_CFGR2_PREDIV_DIV11            RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_CFGR2_PREDIV_DIV12            RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_CFGR2_PREDIV_DIV13            RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_CFGR2_PREDIV_DIV14            RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_CFGR2_PREDIV_DIV15            RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_CFGR2_PREDIV_DIV16            RCC_CFGR2_PREDIV1_DIV16
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
+//#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
+#define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
+//#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+//#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+//#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+//#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+//#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+#define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
+#define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
+#define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF800000)        /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+
+/********************  Bits definition for RTC_CR register  *******************/
+//#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+//#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+//#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+//#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+//#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+//#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_BKP                           ((uint32_t)0x00040000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+//#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK                           RTC_CR_BKP
+#define RTC_CR_CALSEL                        RTC_CR_COSEL
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+//#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+//#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+//#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+//#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+//#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+//#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALR register  ******************/
+#define RTC_CALR_CALP                         ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP                         RTC_CALR_CALP
+#define RTC_CAL_CALW8                        RTC_CALR_CALW8
+#define RTC_CAL_CALW16                       RTC_CALR_CALW16
+#define RTC_CAL_CALM                         RTC_CALR_CALM
+#define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+//#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
+//#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+#define RTC_TAFCR_TAMP2TRG                                   RTC_TAFCR_TAMP2EDGE
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+//#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+//#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+//#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+//#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+//#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+//#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+//#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+//#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+//#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+//#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+//#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+//#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+//#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+//#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+//#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+//#define SYSCFG_CFGR1_PA11_PA12_RMP          ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages*/
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+//#define SYSCFG_CFGR1_TIM16_DMA_RMP2         ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_TIM17_DMA_RMP2         ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for FT32F072XB) */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C PB9 Fast mode plus */
+//#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for FT32F072XB devices) */
+//#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for FT32F072XBdevices) */
+//#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for FT32F072XBdevices) */
+//#define SYSCFG_CFGR1_SPI2_DMA_RMP           ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_USART2_DMA_RMP         ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_USART3_DMA_RMP         ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_I2C1_DMA_RMP           ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_TIM1_DMA_RMP           ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_TIM2_DMA_RMP           ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for FT32F072XB) */
+//#define SYSCFG_CFGR1_TIM3_DMA_RMP           ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for FT32F072XB) */
+
+
+/* Old bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR1_I2C_FMP_PB6               SYSCFG_CFGR1_I2C_PB6_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB7               SYSCFG_CFGR1_I2C_PB7_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB8               SYSCFG_CFGR1_I2C_PB8_FMP
+#define SYSCFG_CFGR1_I2C_FMP_PB9               SYSCFG_CFGR1_I2C_PB9_FMP
+
+
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+//#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+//#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+//#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+//#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+//#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+//#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+//#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+//#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+//#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+//#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
+//#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+//#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+//#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+//#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+//#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+//#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+
+/* Old Bit definition maintained for legacy purpose */
+
+
+/*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
+//#define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
+//#define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+//#define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+//#define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+//#define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+//#define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
+//#define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+//#define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+//#define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+//#define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+//#define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+//#define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+//#define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+//#define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+//#define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+//#define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+//#define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+//#define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
+//#define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+//#define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+//#define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+//#define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+//#define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+//#define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+//#define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+//#define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
+//#define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+//#define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+//#define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+//#define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+//#define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+//#define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+//#define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+//#define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+//#define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+//#define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
+//#define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+//#define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+//#define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+//#define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+//#define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+//#define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
+//#define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M0                        ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+//#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+#define  USART_CR1_M1                        ((uint32_t)0x10000000)            /*!< End of Block interrupt enable */
+
+#define  USART_CR1_M                         USART_CR1_M0
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+//#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+//#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABRE                      ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMOD                    ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMOD_0                  ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMOD_1                  ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+#define  USART_CR2_ABRMODE                                   USART_CR2_ABRMOD
+#define  USART_CR2_ABRMODE_0                 USART_CR2_ABRMOD_0
+#define  USART_CR2_ABRMODE_1                 USART_CR2_ABRMOD_1
+#define  USART_CR2_ABREN                     USART_CR2_ABRE
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+//#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+//#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+//#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+//#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+//#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+//#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+//#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+//#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+//#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+//#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+//#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+//#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+//#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+//#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+#define  USART_BRR_BRR                       ((uint16_t)0xFFFF)                /*!< Fraction of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+//#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+//#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+//#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+//#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+//#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+//#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+//#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+//#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+//#ifdef USE_STDPERIPH_DRIVER
+//  #include "FT32f0xx_conf.h"
+//#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F072XB_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f0xx.h

@@ -0,0 +1,110 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx.h
+  * @author             FMD AE
+  * @brief              CMSIS FT32F0xx Device Peripheral Access Layer Header File.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+#ifndef __FT32F0xx_H
+#define __FT32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+#if !defined  (FT32F0)
+#define FT32F0
+#endif /* FT32F0 */
+
+
+
+/**
+  * @brief CMSIS Device version number V2.3.3
+  */
+#define __FT32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
+#define __FT32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __FT32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
+#define __FT32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __FT32F0_DEVICE_VERSION        ((__FT32F0_DEVICE_VERSION_MAIN << 24)\
+                                        |(__FT32F0_DEVICE_VERSION_SUB1 << 16)\
+                                        |(__FT32F0_DEVICE_VERSION_SUB2 << 8 )\
+                                        |(__FT32F0_DEVICE_VERSION_RC))
+
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#if defined(FT32F030x6)
+  #include "ft32f030x6.h"
+#elif defined(FT32F030x8)
+  #include "ft32f030x8.h"
+#elif defined (FT32F032x6)
+  #include "ft32f032x6.h"
+#elif defined (FT32F032x8)
+  #include "ft32f032x8.h"
+#elif defined(FT32F072x8)
+  #include "ft32f072x8.h"
+#elif defined(FT32F072xB)
+  #include "ft32f072xb.h"
+#else
+ #error "Please select first the target FT32F0xx device used in your application (in ft32f0xx.h file)"
+#endif
+#include "../../../FT32F0xx_Driver/templates/Inc/ft32f0xx_conf.h"
+
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __FT32F0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/*****************************END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/system_ft32f0xx.h

@@ -0,0 +1,43 @@
+/**
+  ******************************************************************************
+  * @file               system_ft32f0xx.h
+  * @author             FMD AE
+  * @brief              CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
+  * @details
+  * @version            V1.0.0
+  * @date               2021-07-01
+  *******************************************************************************
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_FT32F0xx_H
+#define __SYSTEM_FT32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f030x6.s

@@ -0,0 +1,252 @@
+;/**
+;  ******************************************************************************
+;  * @file    			startup_ft32f030x6.s 
+;  * @author  			FMD AE
+;  * @brief   			FT32F030X6 devices vector table for MDK-ARM toolchain.   	
+;  * @version 			V1.0.0           
+;  * @data		 		2021-07-01
+;  ******************************************************************************
+;  */
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+               	DCD     PVD_VDDIO_IRQHandler           ; PVD_VDDIO 
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_IRQHandler                 ; RCC
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     0                              ; Reserved
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
+                DCD     ADC1_IRQHandler                ; ADC1 
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     0                              ; Reserved
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_IRQHandler                ; TIM6
+                DCD     0                              ; Reserved
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     USB_IRQHandler                 ; USB
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+
+
+
+        LDR     R0, =__initial_sp          ; set stack pointer 
+        MSR     MSP, R0  
+
+;;Check if boot space corresponds to test memory 
+
+        LDR R0,=0x00000004
+        LDR R1, [R0]
+        LSRS R1, R1, #24
+        LDR R2,=0x1F
+        CMP R1, R2
+        
+        BNE ApplicationStart  
+     
+;; SYSCFG clock enable    
+     
+        LDR R0,=0x40021018 
+        LDR R1,=0x00000001
+        STR R1, [R0]
+        
+;; Set CFGR1 register with flash memory remap at address 0
+
+        LDR R0,=0x40010000 
+        LDR R1,=0x00000000
+        STR R1, [R0]
+ApplicationStart        
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_VDDIO_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
+                EXPORT  ADC1_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler 
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT FMD *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f030x8.s

@@ -0,0 +1,252 @@
+;/**
+;  ******************************************************************************
+;  * @file    			startup_ft32f030x8.s 
+;  * @author  			FMD AE
+;  * @brief   			FT32F030X8 devices vector table for MDK-ARM toolchain.   	
+;  * @version 			V1.0.0           
+;  * @data		 		2021-07-01
+;  ******************************************************************************
+;  */
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+               	DCD     PVD_VDDIO_IRQHandler           ; PVD_VDDIO 
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_IRQHandler                 ; RCC
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     0                              ; Reserved
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
+                DCD     ADC1_IRQHandler                ; ADC1 
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     0                              ; Reserved
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_IRQHandler                ; TIM6
+                DCD     0                              ; Reserved
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     USB_IRQHandler                 ; USB
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+
+
+
+        LDR     R0, =__initial_sp          ; set stack pointer 
+        MSR     MSP, R0  
+
+;;Check if boot space corresponds to test memory 
+
+        LDR R0,=0x00000004
+        LDR R1, [R0]
+        LSRS R1, R1, #24
+        LDR R2,=0x1F
+        CMP R1, R2
+        
+        BNE ApplicationStart  
+     
+;; SYSCFG clock enable    
+     
+        LDR R0,=0x40021018 
+        LDR R1,=0x00000001
+        STR R1, [R0]
+        
+;; Set CFGR1 register with flash memory remap at address 0
+
+        LDR R0,=0x40010000 
+        LDR R1,=0x00000000
+        STR R1, [R0]
+ApplicationStart        
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_VDDIO_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
+                EXPORT  ADC1_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler 
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT FMD *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s

@@ -0,0 +1,254 @@
+;/**
+;  ******************************************************************************
+;  * @file    			startup_ft32f072x8.s 
+;  * @author  			FMD AE
+;  * @brief   			FT32F072X8 devices vector table for MDK-ARM toolchain.   	
+;  * @version 			V1.0.0           
+;  * @data		 		2021-07-01
+;  ******************************************************************************
+;  */
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+               	DCD     PVD_VDDIO_IRQHandler           ; PVD_VDDIO 
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_IRQHandler                 ; RCC
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     0                              ; Reserved
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
+                DCD     ADC1_IRQHandler                ; ADC1 
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     0                              ; Reserved
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_IRQHandler                ; TIM6
+                DCD     0                              ; Reserved
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     DIV_IRQHandler                 ; DIV
+                DCD     0                              ; Reserved
+                DCD     USB_IRQHandler                 ; USB
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+
+
+
+        LDR     R0, =__initial_sp          ; set stack pointer 
+        MSR     MSP, R0  
+
+;;Check if boot space corresponds to test memory 
+
+        LDR R0,=0x00000004
+        LDR R1, [R0]
+        LSRS R1, R1, #24
+        LDR R2,=0x1F
+        CMP R1, R2
+        
+        BNE ApplicationStart  
+     
+;; SYSCFG clock enable    
+     
+        LDR R0,=0x40021018 
+        LDR R1,=0x00000001
+        STR R1, [R0]
+        
+;; Set CFGR1 register with flash memory remap at address 0
+
+        LDR R0,=0x40010000 
+        LDR R1,=0x00000000
+        STR R1, [R0]
+ApplicationStart        
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_VDDIO_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
+                EXPORT  ADC1_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+				EXPORT	DIV_IRQHandler				   [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler 
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+DIV_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT FMD *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x6.s

@@ -0,0 +1,258 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f030x6.s
+  * @author    MCD Application Team
+  * @brief     STM32F030x4/STM32F030x6 devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl entry
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler                   /* Window WatchDog              */
+  .word  0                                 /* Reserved                     */
+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */
+  .word  FLASH_IRQHandler                  /* FLASH                        */
+  .word  RCC_IRQHandler                    /* RCC                          */
+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word  0                                 /* Reserved                     */
+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
+  .word  ADC1_IRQHandler                   /* ADC1                         */
+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM3_IRQHandler                   /* TIM3                         */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  TIM14_IRQHandler                  /* TIM14                        */
+  .word  0                                 /* Reserved                     */
+  .word  TIM16_IRQHandler                  /* TIM16                        */
+  .word  TIM17_IRQHandler                  /* TIM17                        */
+  .word  I2C1_IRQHandler                   /* I2C1                         */
+  .word  0                                 /* Reserved                     */
+  .word  SPI1_IRQHandler                   /* SPI1                         */
+  .word  0                                 /* Reserved                     */
+  .word  USART1_IRQHandler                 /* USART1                       */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel4_5_IRQHandler
+  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+  .weak      ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x8.s

@@ -0,0 +1,273 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f030x8.s
+  * @author    MCD Application Team
+  * @brief     STM32F030x8 devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl entry
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler                   /* Window WatchDog              */
+  .word  0                                 /* Reserved                     */
+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */
+  .word  FLASH_IRQHandler                  /* FLASH                        */
+  .word  RCC_IRQHandler                    /* RCC                          */
+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word  0                                 /* Reserved                     */
+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
+  .word  ADC1_IRQHandler                   /* ADC1                         */
+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM3_IRQHandler                   /* TIM3                         */
+  .word  TIM6_IRQHandler                   /* TIM6                         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM14_IRQHandler                  /* TIM14                        */
+  .word  TIM15_IRQHandler                  /* TIM15                        */
+  .word  TIM16_IRQHandler                  /* TIM16                        */
+  .word  TIM17_IRQHandler                  /* TIM17                        */
+  .word  I2C1_IRQHandler                   /* I2C1                         */
+  .word  I2C2_IRQHandler                   /* I2C2                         */
+  .word  SPI1_IRQHandler                   /* SPI1                         */
+  .word  SPI2_IRQHandler                   /* SPI2                         */
+  .word  USART1_IRQHandler                 /* USART1                       */
+  .word  USART2_IRQHandler                 /* USART2                       */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel4_5_IRQHandler
+  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+  .weak      ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak      USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s

@@ -0,0 +1,294 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f072xb.s
+  * @author    MCD Application Team
+  * @brief     STM32F072x8/STM32F072xB devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl entry
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler                   /* Window WatchDog              */
+  .word  PVD_VDDIO2_IRQHandler             /* PVD and VDDIO2 through EXTI Line detect */
+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */
+  .word  FLASH_IRQHandler                  /* FLASH                        */
+  .word  RCC_CRS_IRQHandler                /* RCC and CRS                  */
+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word  TSC_IRQHandler                    /* TSC                          */
+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word  DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
+  .word  ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2         */
+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word  TIM2_IRQHandler                   /* TIM2                         */
+  .word  TIM3_IRQHandler                   /* TIM3                         */
+  .word  TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
+  .word  TIM7_IRQHandler                   /* TIM7                         */
+  .word  TIM14_IRQHandler                  /* TIM14                        */
+  .word  TIM15_IRQHandler                  /* TIM15                        */
+  .word  TIM16_IRQHandler                  /* TIM16                        */
+  .word  TIM17_IRQHandler                  /* TIM17                        */
+  .word  I2C1_IRQHandler                   /* I2C1                         */
+  .word  I2C2_IRQHandler                   /* I2C2                         */
+  .word  SPI1_IRQHandler                   /* SPI1                         */
+  .word  SPI2_IRQHandler                   /* SPI2                         */
+  .word  USART1_IRQHandler                 /* USART1                       */
+  .word  USART2_IRQHandler                 /* USART2                       */
+  .word  USART3_4_IRQHandler               /* USART3 and USART4            */
+  .word  CEC_CAN_IRQHandler                /* CEC and CAN                  */
+  .word  USB_IRQHandler                    /* USB                          */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      PVD_VDDIO2_IRQHandler
+  .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_CRS_IRQHandler
+  .thumb_set RCC_CRS_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      TSC_IRQHandler
+  .thumb_set TSC_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel4_5_6_7_IRQHandler
+  .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
+
+  .weak      ADC1_COMP_IRQHandler
+  .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      TIM6_DAC_IRQHandler
+  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+  .weak      TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak      USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak      USART3_4_IRQHandler
+  .thumb_set USART3_4_IRQHandler,Default_Handler
+
+  .weak      CEC_CAN_IRQHandler
+  .thumb_set CEC_CAN_IRQHandler,Default_Handler
+
+  .weak      USB_IRQHandler
+  .thumb_set USB_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x6_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x08007FFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x8_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f072xb_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x6.s

@@ -0,0 +1,245 @@
+;*******************************************************************************
+;* File Name          : startup_stm32f030x6.s
+;* Author             : MCD Application Team
+;* Description        : STM32F030x4/STM32F030x6 devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address,
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                  ; Reset Handler
+
+        DCD     NMI_Handler                    ; NMI Handler
+        DCD     HardFault_Handler              ; Hard Fault Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     SVC_Handler                    ; SVCall Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     PendSV_Handler                 ; PendSV Handler
+        DCD     SysTick_Handler                ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                ; Window Watchdog
+        DCD     0                              ; Reserved
+        DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+        DCD     FLASH_IRQHandler               ; FLASH
+        DCD     RCC_IRQHandler                 ; RCC
+        DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+        DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+        DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+        DCD     0                              ; Reserved
+        DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+        DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+        DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
+        DCD     ADC1_IRQHandler                ; ADC1 
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+        DCD     0                              ; Reserved
+        DCD     TIM3_IRQHandler                ; TIM3
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     TIM14_IRQHandler               ; TIM14
+        DCD     0                              ; Reserved
+        DCD     TIM16_IRQHandler               ; TIM16
+        DCD     TIM17_IRQHandler               ; TIM17
+        DCD     I2C1_IRQHandler                ; I2C1
+        DCD     0                              ; Reserved
+        DCD     SPI1_IRQHandler                ; SPI1
+        DCD     0                              ; Reserved
+        DCD     USART1_IRQHandler              ; USART1
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+
+        PUBWEAK EXTI4_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+        B EXTI4_15_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+        B DMA1_Channel2_3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_IRQHandler
+        B DMA1_Channel4_5_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x8.s

@@ -0,0 +1,274 @@
+;*******************************************************************************
+;* File Name          : startup_stm32f030x8.s
+;* Author             : MCD Application Team
+;* Description        : STM32F030x8 devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address,
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                  ; Reset Handler
+
+        DCD     NMI_Handler                    ; NMI Handler
+        DCD     HardFault_Handler              ; Hard Fault Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     SVC_Handler                    ; SVCall Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     PendSV_Handler                 ; PendSV Handler
+        DCD     SysTick_Handler                ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                ; Window Watchdog
+        DCD     0                              ; Reserved
+        DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+        DCD     FLASH_IRQHandler               ; FLASH
+        DCD     RCC_IRQHandler                 ; RCC
+        DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+        DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+        DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+        DCD     0                              ; Reserved
+        DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+        DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+        DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
+        DCD     ADC1_IRQHandler                ; ADC1 
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+        DCD     0                              ; Reserved
+        DCD     TIM3_IRQHandler                ; TIM3
+        DCD     TIM6_IRQHandler                ; TIM6
+        DCD     0                              ; Reserved
+        DCD     TIM14_IRQHandler               ; TIM14
+        DCD     TIM15_IRQHandler               ; TIM15
+        DCD     TIM16_IRQHandler               ; TIM16
+        DCD     TIM17_IRQHandler               ; TIM17
+        DCD     I2C1_IRQHandler                ; I2C1
+        DCD     I2C2_IRQHandler                ; I2C2
+        DCD     SPI1_IRQHandler                ; SPI1
+        DCD     SPI2_IRQHandler                ; SPI2
+        DCD     USART1_IRQHandler              ; USART1
+        DCD     USART2_IRQHandler              ; USART2
+
+
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+
+        PUBWEAK EXTI4_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+        B EXTI4_15_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+        B DMA1_Channel2_3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_IRQHandler
+        B DMA1_Channel4_5_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s

@@ -0,0 +1,308 @@
+;*******************************************************************************
+;* File Name          : startup_stm32f072xb.s
+;* Author             : MCD Application Team
+;* Description        : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address,
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                  ; Reset Handler
+
+        DCD     NMI_Handler                    ; NMI Handler
+        DCD     HardFault_Handler              ; Hard Fault Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     SVC_Handler                    ; SVCall Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     PendSV_Handler                 ; PendSV Handler
+        DCD     SysTick_Handler                ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                ; Window Watchdog
+        DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
+        DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+        DCD     FLASH_IRQHandler               ; FLASH
+        DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+        DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+        DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+        DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+        DCD     TSC_IRQHandler                 ; TSC
+        DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+        DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+        DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4 to Channel 7
+        DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                ; TIM2
+        DCD     TIM3_IRQHandler                ; TIM3
+        DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+        DCD     TIM7_IRQHandler                ; TIM7
+        DCD     TIM14_IRQHandler               ; TIM14
+        DCD     TIM15_IRQHandler               ; TIM15
+        DCD     TIM16_IRQHandler               ; TIM16
+        DCD     TIM17_IRQHandler               ; TIM17
+        DCD     I2C1_IRQHandler                ; I2C1
+        DCD     I2C2_IRQHandler                ; I2C2
+        DCD     SPI1_IRQHandler                ; SPI1
+        DCD     SPI2_IRQHandler                ; SPI2
+        DCD     USART1_IRQHandler              ; USART1
+        DCD     USART2_IRQHandler              ; USART2
+        DCD     USART3_4_IRQHandler            ; USART3 and USART4
+        DCD     CEC_CAN_IRQHandler             ; CEC and CAN
+        DCD     USB_IRQHandler                 ; USB
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_VDDIO2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_VDDIO2_IRQHandler
+        B PVD_VDDIO2_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_CRS_IRQHandler
+        B RCC_CRS_IRQHandler
+
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+
+        PUBWEAK EXTI4_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+        B EXTI4_15_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+        B DMA1_Channel2_3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_6_7_IRQHandler
+        B DMA1_Channel4_5_6_7_IRQHandler
+
+        PUBWEAK ADC1_COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_COMP_IRQHandler
+        B ADC1_COMP_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+        
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_4_IRQHandler
+        B USART3_4_IRQHandler
+
+        PUBWEAK CEC_CAN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_CAN_IRQHandler
+        B CEC_CAN_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/system_ft32f0xx.c

@@ -0,0 +1,755 @@
+/**
+  ******************************************************************************
+  * @file               system_ft32f0xx.h
+  * @author             FMD AE
+  * @brief              CMSIS FT32F0xx Device Peripheral Access Layer Header File.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup FT32f0xx_system
+  * @{
+  */
+
+/** @addtogroup FT32f0xx_System_Private_Includes
+  * @{
+  */
+
+#include "FT32f0xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup FT32f0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FT32F0xx_System_Private_Defines
+  * @{
+  */
+
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+// #define SYSCLK_FREQ_24MHz  24000000
+// #define SYSCLK_FREQ_36MHz  36000000
+// #define SYSCLK_FREQ_48MHz  48000000
+// #define SYSCLK_FREQ_56MHz  56000000
+ #define SYSCLK_FREQ_72MHz  72000000
+// #define SYSCLK_FREQ_96MHz  96000000
+/**
+  * @}
+  */
+
+/** @addtogroup FT32f0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FT32f0xx_System_Private_Variables
+  * @{
+  */
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz
+#ifdef FT32F072xB
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /*!< System Clock Frequency (Core Clock) */
+#endif
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup FT32f0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup FT32f0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in FT32f0xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in FT32f0xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+      }
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+#ifdef FT32F072xB
+  SetSysClockTo96();
+#endif
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000000);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSE)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000000);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000001);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000001);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#elif defined SYSCLK_FREQ_96MHz
+/**
+  * @brief  Sets System clock frequency to 96MHz and configure HCLK, PCLK
+  *         prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+    StartUpCounter++;
+  } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
+    HSIStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSIStatus = (uint32_t)0x00;
+  }
+
+  if (HSIStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002);
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_adc.h

@@ -0,0 +1,592 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_adc.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the ADC firmware
+  *                     library
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_ADC_H
+#define __FT32F0XX_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  ADC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t ADC_Resolution;                  /*!< Selects the resolution of the conversion.
+                                                 This parameter can be a value of @ref ADC_Resolution */
+
+  FunctionalState ADC_ContinuousConvMode;   /*!< Specifies whether the conversion is performed in
+                                                 Continuous or Single mode.
+                                                 This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConvEdge;        /*!< Selects the external trigger Edge and enables the
+                                                 trigger of a regular group. This parameter can be a value
+                                                 of @ref ADC_external_trigger_edge_conversion */
+
+  uint32_t ADC_ExternalTrigConv;            /*!< Defines the external trigger used to start the analog
+                                                 to digital conversion of regular channels. This parameter
+                                                 can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
+
+  uint32_t ADC_DataAlign;                   /*!< Specifies whether the ADC data alignment is left or right.
+                                                 This parameter can be a value of @ref ADC_data_align */
+
+  uint32_t  ADC_ScanDirection;              /*!< Specifies in which direction the channels will be scanned
+                                                 in the sequence.
+                                                 This parameter can be a value of @ref ADC_Scan_Direction */
+}ADC_InitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+#define IS_ADC_ALL_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
+
+/** @defgroup ADC_JitterOff
+  * @{
+  */
+/* These defines are obsolete and maintained for legacy purpose only. They are replaced  by the ADC_ClockMode */
+#define ADC_JitterOff_PCLKDiv2                    ADC_CFGR2_JITOFFDIV2
+#define ADC_JitterOff_PCLKDiv4                    ADC_CFGR2_JITOFFDIV4
+
+#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_ClockMode
+  * @{
+  */
+#define ADC_ClockMode_AsynClk                  ((uint32_t)0x00000000)   /*!< ADC Asynchronous clock mode */
+#define ADC_ClockMode_SynClkDiv2               ADC_CFGR2_CKMODE_0   /*!<  Synchronous clock mode divided by 2 */
+#define ADC_ClockMode_SynClkDiv4               ADC_CFGR2_CKMODE_1   /*!<  Synchronous clock mode divided by 4 */
+#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
+                                        ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
+                                        ((CLOCK) == ADC_ClockMode_SynClkDiv4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Resolution
+  * @{
+  */
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ADC_CFGR1_RES_0
+#define ADC_Resolution_8b                          ADC_CFGR1_RES_1
+#define ADC_Resolution_6b                          ADC_CFGR1_RES
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_edge_conversion
+  * @{
+  */
+#define ADC_ExternalTrigConvEdge_None              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising            ADC_CFGR1_EXTEN_0
+#define ADC_ExternalTrigConvEdge_Falling           ADC_CFGR1_EXTEN_1
+#define ADC_ExternalTrigConvEdge_RisingFalling     ADC_CFGR1_EXTEN
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_channels_conversion
+  * @{
+  */
+
+/* TIM1 */
+#define ADC_ExternalTrigConv_T1_TRGO               ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC4                ADC_CFGR1_EXTSEL_0
+
+/* TIM2 */
+#define ADC_ExternalTrigConv_T2_TRGO               ADC_CFGR1_EXTSEL_1
+
+/* TIM3 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
+
+/* TIM15 */
+#define ADC_ExternalTrigConv_T15_TRGO              ADC_CFGR1_EXTSEL_2
+
+#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
+                                         ((CONV) == ADC_ExternalTrigConv_T1_CC4)   || \
+                                         ((CONV) == ADC_ExternalTrigConv_T2_TRGO)  || \
+                                         ((CONV) == ADC_ExternalTrigConv_T3_TRGO)  || \
+                                         ((CONV) == ADC_ExternalTrigConv_T15_TRGO))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ADC_CFGR1_ALIGN
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_Direction
+  * @{
+  */
+
+#define ADC_ScanDirection_Upward                   ((uint32_t)0x00000000)
+#define ADC_ScanDirection_Backward                 ADC_CFGR1_SCANDIR
+
+#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
+                                          ((DIRECTION) == ADC_ScanDirection_Backward))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_DMA_Mode
+  * @{
+  */
+
+#define ADC_DMAMode_OneShot                        ((uint32_t)0x00000000)
+#define ADC_DMAMode_Circular                       ADC_CFGR1_DMACFG
+
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
+                               ((MODE) == ADC_DMAMode_Circular))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_Channel_0                 ((uint32_t)0x00000000)
+#define ADC_AnalogWatchdog_Channel_1                 ((uint32_t)0x04000000)
+#define ADC_AnalogWatchdog_Channel_2                 ((uint32_t)0x08000000)
+#define ADC_AnalogWatchdog_Channel_3                 ((uint32_t)0x0C000000)
+#define ADC_AnalogWatchdog_Channel_4                 ((uint32_t)0x10000000)
+#define ADC_AnalogWatchdog_Channel_5                 ((uint32_t)0x14000000)
+#define ADC_AnalogWatchdog_Channel_6                 ((uint32_t)0x18000000)
+#define ADC_AnalogWatchdog_Channel_7                 ((uint32_t)0x1C000000)
+#define ADC_AnalogWatchdog_Channel_8                 ((uint32_t)0x20000000)
+#define ADC_AnalogWatchdog_Channel_9                 ((uint32_t)0x24000000)
+#define ADC_AnalogWatchdog_Channel_10                ((uint32_t)0x28000000)
+#define ADC_AnalogWatchdog_Channel_11                ((uint32_t)0x2C000000)
+#define ADC_AnalogWatchdog_Channel_12                ((uint32_t)0x30000000)
+#define ADC_AnalogWatchdog_Channel_13                ((uint32_t)0x34000000)
+#define ADC_AnalogWatchdog_Channel_14                ((uint32_t)0x38000000)
+#define ADC_AnalogWatchdog_Channel_15                ((uint32_t)0x3C000000)
+#define ADC_AnalogWatchdog_Channel_16                ((uint32_t)0x40000000)
+#define ADC_AnalogWatchdog_Channel_17                ((uint32_t)0x44000000)
+#define ADC_AnalogWatchdog_Channel_18                ((uint32_t)0x48000000)
+
+
+#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_8)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_9)  || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
+                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_times
+  * @{
+  */
+
+#define ADC_SampleTime_1_5Cycles                     ((uint32_t)0x00000000)
+#define ADC_SampleTime_7_5Cycles                     ((uint32_t)0x00000001)
+#define ADC_SampleTime_13_5Cycles                    ((uint32_t)0x00000002)
+#define ADC_SampleTime_28_5Cycles                    ((uint32_t)0x00000003)
+#define ADC_SampleTime_41_5Cycles                    ((uint32_t)0x00000004)
+#define ADC_SampleTime_55_5Cycles                    ((uint32_t)0x00000005)
+#define ADC_SampleTime_71_5Cycles                    ((uint32_t)0x00000006)
+#define ADC_SampleTime_239_5Cycles                   ((uint32_t)0x00000007)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_7_5Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_13_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_28_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_41_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_55_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_71_5Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_239_5Cycles))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels
+  * @{
+  */
+
+#define ADC_Channel_0                              ADC_CHSELR_CHSEL0
+#define ADC_Channel_1                              ADC_CHSELR_CHSEL1
+#define ADC_Channel_2                              ADC_CHSELR_CHSEL2
+#define ADC_Channel_3                              ADC_CHSELR_CHSEL3
+#define ADC_Channel_4                              ADC_CHSELR_CHSEL4
+#define ADC_Channel_5                              ADC_CHSELR_CHSEL5
+#define ADC_Channel_6                              ADC_CHSELR_CHSEL6
+#define ADC_Channel_7                              ADC_CHSELR_CHSEL7
+#define ADC_Channel_8                              ADC_CHSELR_CHSEL8
+#define ADC_Channel_9                              ADC_CHSELR_CHSEL9
+#define ADC_Channel_10                             ADC_CHSELR_CHSEL10
+#define ADC_Channel_11                             ADC_CHSELR_CHSEL11
+#define ADC_Channel_12                             ADC_CHSELR_CHSEL12
+#define ADC_Channel_13                             ADC_CHSELR_CHSEL13
+#define ADC_Channel_14                             ADC_CHSELR_CHSEL14
+#define ADC_Channel_15                             ADC_CHSELR_CHSEL15
+#define ADC_Channel_16                             ADC_CHSELR_CHSEL16
+#define ADC_Channel_17                             ADC_CHSELR_CHSEL17
+#define ADC_Channel_18                             ADC_CHSELR_CHSEL18
+#define ADC_Channel_19                             ADC_CHSELR_CHSEL19
+#define ADC_Channel_20                             ADC_CHSELR_CHSEL20
+#define ADC_Channel_21                             ADC_CHSELR_CHSEL21
+
+#define ADC_Channel_TempSensor                     ((uint32_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                        ((uint32_t)ADC_Channel_17)
+#if defined (FT32F072xB)
+    #define ADC_Channel_OP1                            ((uint32_t)ADC_Channel_18)
+    #define ADC_Channel_OP2                            ((uint32_t)ADC_Channel_19)
+    #define ADC_Channel_IOSH1                          ((uint32_t)ADC_Channel_20)
+    #define ADC_Channel_IOSH2                          ((uint32_t)ADC_Channel_21)
+
+    #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFC00000) == (uint32_t)RESET))
+
+#else
+    #define ADC_Channel_IOSH                          ((uint32_t)ADC_Channel_18)
+    #define ADC_Channel_OP                            ((uint32_t)ADC_Channel_19)
+
+    #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF00000) == (uint32_t)RESET))
+
+#endif
+
+
+
+#if defined (FT32F072xB)
+    /**
+      * @}ADC_IOSH1_SMPSEL
+      */
+    #define ADC_IOSH1_SMPSEL_PB1                        ((uint32_t)0x00000000)
+    #define ADC_IOSH1_SMPSEL_OP1OUT                     ((uint32_t)0x00000400)
+
+    #define ADC_IOSH2_SMPSEL_PB0                        ((uint32_t)0x00000000)
+    #define ADC_IOSH2_SMPSEL_OP2OUT                     ((uint32_t)0x00004000)
+
+    #define IS_ADC_SMPSEL(SEL)                      (   ((SEL) == ADC_IOSH2_SMPSEL_PB1) || \
+                                                        ((SEL) == ADC_IOSH2_SMPSEL_OP1OUT) || \
+                                                        ((SEL) == ADC_IOSH1_SMPSEL_OP2OUT) )
+    /**
+      * @}IS_ADC_SMPEN
+      */
+    #define ADC_IOSH1_SMPEN                  ((uint32_t)0x00000200)
+    #define ADC_IOSH2_SMPEN                  ((uint32_t)0x00002000)
+
+    #define IS_ADC_SMPEN(SMPEN)                     (   ((SMPEN) == ADC_IOSH1_SMPEN) || \
+                                                        ((SMPEN) == ADC_IOSH2_SMPEN) )
+    /**
+      * @}IS_ADC_SMPMOD
+      */
+    #define IS_ADC_SMPMOD(SMPMOD)           (   ((SMPMOD) == ADC_CR2_IOSH1_SMPMOD) || \
+                                                ((SMPMOD) == ADC_CR2_IOSH2_SMPMOD) )
+
+    #define ADC_SMP_SOFTWARE_MODE           ((uint32_t)0x00000000)
+    #define ADC_SMP_HARDWARE_MODE           ((uint32_t)0x00000001)
+
+    #define IS_ADC_MODE(MODE)               (   ((MODE) == ADC_SMP_SOFTWARE_MODE) || \
+                                                ((MODE) == ADC_SMP_HARDWARE_MODE) )
+
+    /**
+      * @}IS_ADC_AMPEN
+      */
+    #define ADC_IOSH1_AMPEN                  ((uint32_t)0x00000100)
+    #define ADC_IOSH2_AMPEN                  ((uint32_t)0x00001000)
+
+    #define IS_ADC_AMPEN(AMPEN)                     (   ((AMPEN) == ADC_IOSH1_AMPEN) || \
+                                                        ((AMPEN) == ADC_IOSH2_AMPEN) )
+    /**
+      * @}IS_ADC_EXTDLY
+      */
+    #define IS_ADC_EXTDLY(EXTDLY)               (  ((EXTDLY) >=0 ) && ((EXTDLY) <= 0x000003FF))
+
+    /**
+      * @}IS_ADC_RTEN
+      */
+    #define IS_ADC_RTEN(RTEN)               (   ((RTEN) == ADC_RTENR_RTEN) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_0) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_1) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_2) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_3) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_4) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_5) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_6) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_7) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_8) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_9) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_10) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_11) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_12) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_13) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_14) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_15) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_16) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_17) || \
+                                                ((RTEN) == ADC_RTENR_RTEN_18)   )
+
+    /**
+      * @}IS_ADC_FTEN
+      */
+    #define IS_ADC_FTEN(FTEN)               (   ((FTEN) == ADC_FTENR_FTEN) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_0) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_1) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_2) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_3) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_4) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_5) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_6) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_7) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_8) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_9) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_10) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_11) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_12) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_13) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_14) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_15) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_16) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_17) || \
+                                                ((FTEN) == ADC_FTENR_FTEN_18))
+
+#else
+    /**
+      * @}IS_ADC_AMPEN
+      */
+    #define ADC_IOSH1_AMPEN                  ((uint32_t)0x00000100)
+    #define ADC_IOSH_AMPEN                  ADC_IOSH1_AMPEN
+
+    #define IS_ADC_AMPEN(AMPEN)                     (   ((AMPEN) == ADC_IOSH1_AMPEN))
+
+    /**
+      * @}IS_ADC_SMPEN
+      */
+    #define ADC_IOSH1_SMPEN                  ((uint32_t)0x00000200)
+    #define ADC_IOSH_SMPEN                  ADC_IOSH1_SMPEN
+
+    #define IS_ADC_SMPEN(SMPEN)                     (   ((SMPEN) == ADC_IOSH1_SMPEN) )
+
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition
+  * @{
+  */
+
+#define ADC_IT_ADRDY                               ADC_IER_ADRDYIE
+#define ADC_IT_EOSMP                               ADC_IER_EOSMPIE
+#define ADC_IT_EOC                                 ADC_IER_EOCIE
+#define ADC_IT_EOSEQ                               ADC_IER_EOSEQIE
+#define ADC_IT_OVR                                 ADC_IER_OVRIE
+#define ADC_IT_AWD                                 ADC_IER_AWDIE
+
+#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
+                           ((IT) == ADC_IT_EOC)   || ((IT) == ADC_IT_EOSEQ) || \
+                           ((IT) == ADC_IT_OVR)   || ((IT) == ADC_IT_AWD))
+
+#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition
+  * @{
+  */
+
+#define ADC_FLAG_ADRDY                             ADC_ISR_ADRDY
+#define ADC_FLAG_EOSMP                             ADC_ISR_EOSMP
+#define ADC_FLAG_EOC                               ADC_ISR_EOC
+#define ADC_FLAG_EOSEQ                             ADC_ISR_EOSEQ
+#define ADC_FLAG_OVR                               ADC_ISR_OVR
+#define ADC_FLAG_AWD                               ADC_ISR_AWD
+
+#define ADC_FLAG_ADEN                              ((uint32_t)0x01000001)
+#define ADC_FLAG_ADDIS                             ((uint32_t)0x01000002)
+#define ADC_FLAG_ADSTART                           ((uint32_t)0x01000004)
+#define ADC_FLAG_ADSTP                             ((uint32_t)0x01000010)
+#define ADC_FLAG_ADCAL                             ((uint32_t)0x81000000)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY)   || ((FLAG) == ADC_FLAG_EOSMP) || \
+                               ((FLAG) == ADC_FLAG_EOC)     || ((FLAG) == ADC_FLAG_EOSEQ) || \
+                               ((FLAG) == ADC_FLAG_AWD)     || ((FLAG) == ADC_FLAG_OVR)   || \
+                               ((FLAG) == ADC_FLAG_ADEN)    || ((FLAG) == ADC_FLAG_ADDIS) || \
+                               ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
+                               ((FLAG) == ADC_FLAG_ADCAL))
+
+
+
+
+
+#define ADC_Vrefsel_0_625V                                  ((uint32_t)0x00000002)
+#define ADC_Vrefsel_1_5V                                    ((uint32_t)0x00000006)
+#define ADC_Vrefsel_2_5V                                    ((uint32_t)0x0000000A)
+#define ADC_Vrefsel_VDDA                                    ((uint32_t)(~(uint32_t)0x0000000E))
+#define IS_ADC_Vrefsel(Vref)    (   (   (Vref) == ADC_Vrefsel_0_625V)   || \
+                                    (   (Vref) == ADC_Vrefsel_1_5V  )   || \
+                                    (   (Vref) == ADC_Vrefsel_2_5V  )   || \
+                                    (   (Vref) == ADC_Vrefsel_VDDA  )   )
+
+#define ADC_VrefEN                                      ((uint32_t)0x00000002)
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+/* This Function is obsolete and maintained for legacy purpose only.
+   ADC_ClockModeConfig() function should be used instead */
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
+
+/* Power saving functions *****************************************************/
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Temperature Sensor , Vrefint and Vbat management function ... ******************/
+void ADC_TempSensorCmd(FunctionalState NewState);
+void ADC_VrefintCmd(FunctionalState NewState);
+void ADC_VbatCmd(FunctionalState NewState);
+void ADC_VrefDecibCmd(FunctionalState NewState);
+void ADC_IoshSmpCmd(uint32_t SmpEn, FunctionalState NewState);
+void ADC_IoshAmpCmd(uint32_t AmpEn, FunctionalState NewState);
+
+/* Channels Configuration functions *******************************************/
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
+void ADC_StopOfConversion(ADC_TypeDef* ADCx);
+void ADC_StartOfConversion(ADC_TypeDef* ADCx);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+#if defined (FT32F072xB)
+void ADC_IoshSmpSel(uint32_t Ioshx, uint32_t SmpSel);
+void ADC_IoshSmpMod(uint32_t SmpModBit, uint32_t Mode);
+void ADC_ExtModeCmd(FunctionalState NewState);
+void ADC_TrgdDisSmpCmd(FunctionalState NewState);
+void ADC_ExtDlyConfig(uint32_t ExtDly);
+void ADC_RtenCmd(uint32_t Rtenx, FunctionalState NewState);
+void ADC_FtenCmd(uint32_t Ftenx, FunctionalState NewState);
+
+#endif
+
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+void ADC_VrefselConfig(uint32_t ADC_Vrefsel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__ft32F0XX_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_comp.h

@@ -0,0 +1,255 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_comp.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the COMP firmware
+  *                     library
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_COMP_H
+#define __FT32F0XX_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  COMP Init structure definition
+  */
+
+typedef struct
+{
+
+  uint32_t COMP_VipSel;                     /*!< Select the positive input of the comparator.
+                                          This parameter can be a value of @ref COMP_VipSel */
+
+  uint32_t COMP_VinSel;             /*!< Select the negative input of the comparator.
+                                          This parameter can be a value of @ref COMP_VinSel */
+
+  uint32_t COMP_OutputSel;          /*!< Selects The output selection of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputSel */
+
+  uint32_t COMP_Pol;                        /*!< Select the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_Pol */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define NCOMP_Selection_COMP                    ((uint32_t)0x00000000) /*!< NCOMP Selection */
+#define PCOMP_Selection_COMP                    ((uint32_t)0x00000010) /*!< PCOMP Selection */
+#define COMP_Selection_COMP3                    ((uint32_t)0x00000001) /*!< PCOMP Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == NCOMP_Selection_COMP) || \
+                                    ((PERIPH) == PCOMP_Selection_COMP))
+
+
+#define COMP_Selection_COMP1                    NCOMP_Selection_COMP
+#define COMP_Selection_COMP2                    PCOMP_Selection_COMP
+/**
+  * @}
+  */
+
+/** @defgroup COMP_VipSel
+  * @{
+  */
+
+#define NCOMP_VIP_SEL_1WIRE             ((uint32_t)0x00000000)
+#define NCOMP_VIP_SEL_PAD_PA1           ((uint32_t)0x00000002)
+#define NCOMP_VIP_SEL_PAD_PA4           ((uint32_t)0x00000004)
+#define NCOMP_VIP_SEL_PAD_PA13          ((uint32_t)0x00000006)
+#define NCOMP_VIP_SEL_PAD_PB12          ((uint32_t)0x00000008)
+
+#define PCOMP_VIP_SEL_PAD_PA3           ((uint32_t)0x00000000)
+#define PCOMP_VIP_SEL_PAD_PA4           ((uint32_t)0x00020000)
+#define PCOMP_VIP_SEL_PAD_PA13          ((uint32_t)0x00040000)
+#define PCOMP_VIP_SEL_PAD_PB12          ((uint32_t)0x00060000)
+
+#define COMP3_VIP_SEL_PAD_PF5           ((uint32_t)0x00000000)
+#define COMP3_VIP_SEL_PAD_PB12          ((uint32_t)0x00000002)
+#define COMP3_VIP_SEL_PAD_PA13          ((uint32_t)0x00000004)
+#define COMP3_VIP_SEL_PAD_PA4           ((uint32_t)0x00000006)
+
+#define IS_COMP_VIP_SEL(INPUT)  (((INPUT) == NCOMP_VIP_SEL_1WIRE) || \
+                                        ((INPUT) == NCOMP_VIP_SEL_PAD_PA1)  || \
+                                        ((INPUT) == NCOMP_VIP_SEL_PAD_PA4)  || \
+                                        ((INPUT) == NCOMP_VIP_SEL_PAD_PA13) || \
+                                        ((INPUT) == NCOMP_VIP_SEL_PAD_PB12) || \
+                                        ((INPUT) == PCOMP_VIP_SEL_PAD_PA3)  || \
+                                        ((INPUT) == PCOMP_VIP_SEL_PAD_PA4)  || \
+                                        ((INPUT) == PCOMP_VIP_SEL_PAD_PA13) || \
+                                        ((INPUT) == PCOMP_VIP_SEL_PAD_PB12)  )
+/**
+  * @}
+  */
+
+/** @defgroup COMP_VinSel
+  * @{
+  */
+
+#define NCOMP_VIN_SEL_DAC1_OUT                  ((uint32_t)0x00000000)
+#define NCOMP_VIN_SEL_PAD_PA0                   ((uint32_t)0x00000010)
+#define NCOMP_VIN_SEL_PAD_PA4                   ((uint32_t)0x00000020)
+#define NCOMP_VIN_SEL_PAD_PA5                   ((uint32_t)0x00000030)
+
+#define PCOMP_VIN_SEL_DAC2_OUT                  ((uint32_t)0x00000000)
+#define PCOMP_VIN_SEL_PAD_PA2                   ((uint32_t)0x00080000)
+#define PCOMP_VIN_SEL_PAD_PA4                   ((uint32_t)0x00100000)
+#define PCOMP_VIN_SEL_PAD_PA5                   ((uint32_t)0x00180000)
+
+#define COMP3_VIN_SEL_PAD_PF4                   ((uint32_t)0x00000000)
+#define COMP3_VIN_SEL_DAC2_OUT                  ((uint32_t)0x00000010)
+#define COMP3_VIN_SEL_PAD_PA4                   ((uint32_t)0x00000020)
+#define COMP3_VIN_SEL_PAD_PA5                   ((uint32_t)0x00000030)
+
+#define IS_COMP_VINSEL(INPUT) (((INPUT) == NCOMP_VIN_SEL_DAC1_OUT) || \
+                                ((INPUT) == NCOMP_VIN_SEL_PAD_PA0) || \
+                                ((INPUT) == NCOMP_VIN_SEL_PAD_PA4) || \
+                                ((INPUT) == NCOMP_VIN_SEL_PAD_PA5) || \
+                                ((INPUT) == PCOMP_VIN_SEL_DAC2_OUT)|| \
+                                ((INPUT) == PCOMP_VIN_SEL_PAD_PA2) || \
+                                ((INPUT) == PCOMP_VIN_SEL_PAD_PA4) || \
+                                ((INPUT) == PCOMP_VIN_SEL_PAD_PA5) )
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputSel
+  * @{
+  */
+
+#define COMP_OUTPUT_NO_SELECTION                    ((uint32_t)0x00000000)
+#define NCOMP_OUTPUT_SEL_TIM1_CAPTURE1              ((uint32_t)0x00000200)
+#define NCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR            ((uint32_t)0x00000300)
+#define NCOMP_OUTPUT_SEL_TIM3_CAPTURE1              ((uint32_t)0x00000600)
+#define NCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR            ((uint32_t)0x00000700)
+
+#define PCOMP_OUTPUT_SEL_TIM1_BREAK                 ((uint32_t)0x01000000)
+#define PCOMP_OUTPUT_SEL_TIM1_CAPTURE1              ((uint32_t)0x02000000)
+#define PCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR            ((uint32_t)0x03000000)
+#define PCOMP_OUTPUT_SEL_TIM3_CAPTURE1              ((uint32_t)0x06000000)
+#define PCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR            ((uint32_t)0x07000000)
+
+#define COMP3_OUTPUT_SEL_TIM1_CAPTURE1              ((uint32_t)0x00000200)
+#define COMP3_OUTPUT_SEL_TIM1_OCREFCLEAR            ((uint32_t)0x00000300)
+#define COMP3_OUTPUT_SEL_TIM3_CAPTURE1              ((uint32_t)0x00000600)
+#define COMP3_OUTPUT_SEL_TIM3_OCREFCLEAR            ((uint32_t)0x00000700)
+
+#define IS_COMP_OUTPUT_SEL(SEL) (   ((SEL) == NCOMP_OUTPUT_SEL_TIM1_CAPTURE1)   || \
+                                    ((SEL) == NCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR) ||\
+                                    ((SEL) == NCOMP_OUTPUT_SEL_TIM3_CAPTURE1)   ||\
+                                    ((SEL) == NCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR) ||\
+                                    ((SEL) == PCOMP_OUTPUT_SEL_TIM1_BREAK)      ||\
+                                    ((SEL) == PCOMP_OUTPUT_SEL_TIM1_CAPTURE1)   ||\
+                                    ((SEL) == PCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR) ||\
+                                    ((SEL) == PCOMP_OUTPUT_SEL_TIM3_CAPTURE1)   ||\
+                                    ((SEL) == PCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR) ||\
+                                    ((SEL) == COMP_OUTPUT_NO_SELECTION)         )
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Pol
+  * @{
+  */
+
+#define NCOMP_POL_NOT_INVERT                ((uint32_t)0x00000000)
+#define NCOMP_POL_INVERT                    ((uint32_t)0x00000800)
+
+#define PCOMP_POL_NOT_INVERT                ((uint32_t)0x00000000)
+#define PCOMP_POL_INVERT                    ((uint32_t)0x08000000)
+
+#define COMP3_POL_NOT_INVERT                ((uint32_t)0x00000000)
+#define COMP3_POL_INVERT                    ((uint32_t)0x00000800)
+
+#define IS_COMP_POL(POL)                 (  ((POL) == NCOMP_POL_NOT_INVERT) || \
+                                            ((POL) == NCOMP_POL_INVERT)     || \
+                                            ((POL) == PCOMP_POL_NOT_INVERT) || \
+                                            ((POL) == PCOMP_POL_INVERT)     )
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel
+  * @{
+  */
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High                   COMP_CSR_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+
+#define IS_COMP_OUTPUT_LEVEL(LEVEL)         (((LEVEL) == COMP_CSR_COMP1OUT) || \
+                                             ((LEVEL) == COMP_CSR_COMP2OUT))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_COMP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crc.h

@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_crc.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the CRC firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_CRC_H
+#define __FT32F0XX_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_ReverseInputData
+  * @{
+  */
+#define CRC_ReverseInputData_No             ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
+#define CRC_ReverseInputData_8bits          CRC_CR_REV_IN_0        /*!< Reverse operation of Input Data on 8 bits */
+#define CRC_ReverseInputData_16bits         CRC_CR_REV_IN_1        /*!< Reverse operation of Input Data on 16 bits */
+#define CRC_ReverseInputData_32bits         CRC_CR_REV_IN          /*!< Reverse operation of Input Data on 32 bits */
+
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No)     || \
+                                         ((DATA) == CRC_ReverseInputData_8bits)  || \
+                                         ((DATA) == CRC_ReverseInputData_16bits) || \
+                                         ((DATA) == CRC_ReverseInputData_32bits))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_PolynomialSize
+  * @brief    Only applicable for FT32F042 and FT32F072 devices
+  * @{
+  */
+#define CRC_PolSize_7                       CRC_CR_POLSIZE        /*!< 7-bit polynomial for CRC calculation */
+#define CRC_PolSize_8                       CRC_CR_POLSIZE_1      /*!< 8-bit polynomial for CRC calculation */
+#define CRC_PolSize_16                      CRC_CR_POLSIZE_0      /*!< 16-bit polynomial for CRC calculation */
+#define CRC_PolSize_32                      ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
+
+#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7)  || \
+                               ((SIZE) == CRC_PolSize_8)  || \
+                               ((SIZE) == CRC_PolSize_16) || \
+                               ((SIZE) == CRC_PolSize_32))
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRC computation unit **********************************/
+void CRC_DeInit(void);
+void CRC_ResetDR(void);
+//void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for FT32F042 and FT32F072 devices */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);
+void CRC_SetInitRegister(uint32_t CRC_InitValue);
+void CRC_SetPolynomial(uint32_t CRC_Pol);
+
+/* CRC computation ************************************************************/
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+/* Independent register (IDR) access (write/read) *****************************/
+void CRC_SetIDRegister(uint8_t CRC_IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_CRC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crs.h

@@ -0,0 +1,163 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_crs.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the CRS firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_CRS_H
+#define __FT32F0XX_CRS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup CRS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRS_Interrupt_Sources
+  * @{
+  */
+#define CRS_IT_SYNCOK             CRS_ISR_SYNCOKF    /*!< SYNC event OK */
+#define CRS_IT_SYNCWARN           CRS_ISR_SYNCWARNF  /*!< SYNC warning */
+#define CRS_IT_ERR                CRS_ISR_ERRF       /*!< error */
+#define CRS_IT_ESYNC              CRS_ISR_ESYNCF     /*!< Expected SYNC */
+#define CRS_IT_TRIMOVF            CRS_ISR_TRIMOVF    /*!< Trimming overflow or underflow */
+#define CRS_IT_SYNCERR            CRS_ISR_SYNCERR    /*!< SYNC error */
+#define CRS_IT_SYNCMISS           CRS_ISR_SYNCMISS    /*!< SYNC missed*/
+
+#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+                       ((IT) == CRS_IT_ERR)  || ((IT) == CRS_IT_ESYNC))
+
+#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+                           ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
+                           ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
+                           ((IT) == CRS_IT_SYNCMISS))
+
+#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_Flags
+  * @{
+  */
+#define CRS_FLAG_SYNCOK             CRS_ISR_SYNCOKF    /*!< SYNC event OK */
+#define CRS_FLAG_SYNCWARN           CRS_ISR_SYNCWARNF  /*!< SYNC warning */
+#define CRS_FLAG_ERR                CRS_ISR_ERRF       /*!< error */
+#define CRS_FLAG_ESYNC              CRS_ISR_ESYNCF     /*!< Expected SYNC */
+#define CRS_FLAG_TRIMOVF            CRS_ISR_TRIMOVF    /*!< Trimming overflow or underflow */
+#define CRS_FLAG_SYNCERR            CRS_ISR_SYNCERR    /*!< SYNC error */
+#define CRS_FLAG_SYNCMISS           CRS_ISR_SYNCMISS    /*!< SYNC missed*/
+
+#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
+                           ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
+                           ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
+                           ((FLAG) == CRS_FLAG_SYNCMISS))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_Synchro_Source
+  * @{
+  */
+#define CRS_SYNCSource_GPIO       ((uint32_t)0x00)        /*!< Synchro Signal soucre GPIO */
+#define CRS_SYNCSource_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define CRS_SYNCSource_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF */
+
+#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
+                                    ((SOURCE) == CRS_SYNCSource_LSE) ||\
+                                    ((SOURCE) == CRS_SYNCSource_USB))
+/**
+  * @}
+  */
+
+/** @defgroup CRS_SynchroDivider
+  * @{
+  */
+#define CRS_SYNC_Div1        ((uint32_t)0x00)                          /*!< Synchro Signal not divided */
+#define CRS_SYNC_Div2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define CRS_SYNC_Div4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define CRS_SYNC_Div8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define CRS_SYNC_Div16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define CRS_SYNC_Div32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define CRS_SYNC_Div64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define CRS_SYNC_Div128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+
+#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2)   ||\
+                              ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8)   || \
+                              ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
+                              ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
+/**
+  * @}
+  */
+
+/** @defgroup CRS_SynchroPolarity
+  * @{
+  */
+#define CRS_SYNCPolarity_Rising       ((uint32_t)0x00)      /*!< Synchro Active on rising edge */
+#define CRS_SYNCPolarity_Falling      CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+
+#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
+                                    ((POLARITY) == CRS_SYNCPolarity_Falling))
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRS **********************************/
+void CRS_DeInit(void);
+void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
+void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
+void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
+void CRS_SoftwareSynchronizationGenerate(void);
+void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
+void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
+void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
+void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
+void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
+uint32_t CRS_GetReloadValue(void);
+uint32_t CRS_GetHSI48CalibrationValue(void);
+uint32_t CRS_GetFrequencyErrorValue(void);
+uint32_t CRS_GetFrequencyErrorDirection(void);
+
+/* Interrupts and flags management functions **********************************/
+void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
+FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
+void CRS_ClearFlag(uint32_t CRS_FLAG);
+ITStatus CRS_GetITStatus(uint32_t CRS_IT);
+void CRS_ClearITPendingBit(uint32_t CRS_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_CRS_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dac.h

@@ -0,0 +1,43 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_dac.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the DAC firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+#ifndef __FT32F0XX_DAC_H
+#define __FT32F0XX_DAC_H
+
+
+#include "ft32f0xx.h"
+
+
+
+/**
+    *   @Parama DAC_CTRL
+    */
+
+#define DAC_DATA_RESET          ((uint32_t)(0x0000007f))
+
+#define DAC_CTRL_READ               (uint8_t)(0x20)
+#define DAC_DATA1_READ          (uint8_t)(0x24)
+#define DAC_DATA2_READ          (uint8_t)(0x28)
+
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0x7F)
+
+
+/**
+    *   @Parama DAC1_DATA
+    */
+void DAC_Ref_Config(uint32_t    DAC_RefSel);
+void Bsp_DAC_Config(void);
+uint8_t DAC_Read_Reg(uint8_t DAC_Register);
+void DAC_Cmd(FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint8_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint8_t Data);
+
+#endif

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_debug.h

@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_debug.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the DBGMCU firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_DBGMCU_H
+#define __FT32F0XX_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup DBGMCU
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define DBGMCU_STOP                  DBGMCU_CR_DBG_STOP
+#define DBGMCU_STANDBY               DBGMCU_CR_DBG_STANDBY
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP
+#define DBGMCU_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP
+#define DBGMCU_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP
+#define DBGMCU_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP
+#define DBGMCU_TIM14_STOP            DBGMCU_APB1_FZ_DBG_TIM14_STOP
+#define DBGMCU_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP
+#define DBGMCU_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP
+#define DBGMCU_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
+#define DBGMCU_CAN1_STOP             DBGMCU_APB1_FZ_DBG_CAN1_STOP
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             DBGMCU_APB2_FZ_DBG_TIM1_STOP
+#define DBGMCU_TIM15_STOP            DBGMCU_APB2_FZ_DBG_TIM15_STOP
+#define DBGMCU_TIM16_STOP            DBGMCU_APB2_FZ_DBG_TIM16_STOP
+#define DBGMCU_TIM17_STOP            DBGMCU_APB2_FZ_DBG_TIM17_STOP
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_DBGMCU_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_div.h

@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file               FT32f0xx_div.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the dividor firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data               2021-12-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_DIV_H
+#define __FT32F0XX_DIV_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+#include <stdint.h>
+/** @addtogroup DIV
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  DIV Status
+  */
+typedef enum
+{
+    DIV_COMPLETE  = 0,
+    DIV_ERROR_DIV0ERR,
+    DIV_ERROR_DIV0V,
+}DIV_Status;
+
+/**
+  * @brief  Dividor Data structure definition
+  */
+typedef struct
+{
+    uint32_t DIV_quotient;          /*!< Selects The feedback resister of the OPA. */
+    uint32_t DIV_remainder;          /*!< Selects The compensate cap of the OPA.*/
+}DIV_ResultTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DIV_interrupts_definition
+  * @{
+  */
+
+#define DIV_IT_DIV0ERR                              DIV_SC_DIV0IE
+#define DIV_IT_DIVOV                                DIV_SC_DIVOVIE
+#define IS_DIV_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFFEB) == (uint32_t)RESET))
+
+#define IS_DIV_GET_IT(IT) (((IT) == DIV_IT_DIV0ERR) || ((IT) == DIV_IT_DIVOV))
+
+#define IS_DIV_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFFEB0) == (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup DIV_flags_definition
+  * @{
+  */
+
+#define DIV_FLAG_BUSY                               DIV_SC_DIVBUSY
+#define DIV_FLAG_DIV0ERR                            DIV_SC_DIV0ERR
+#define DIV_FLAG_DIVOV                              DIV_SC_DIVOV
+
+#define IS_DIV_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFFFF5) == (uint32_t)RESET))
+
+#define IS_DIV_GET_FLAG(FLAG) (((FLAG) == DIV_FLAG_BUSY)   || ((FLAG) == DIV_FLAG_DIV0ERR) || ((FLAG) == DIV_FLAG_DIV0ERR))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* DIV Calculating functions *****************************************/
+DIV_Status DivS32ByS16(DIV_ResultTypeDef* pResult,int32_t divedent,int16_t dividor);
+
+/* Interrupts and flags management functions **********************************/
+void DIV_ITConfig(uint32_t DIV_IT, FunctionalState NewState);
+FlagStatus DIV_GetFlagStatus(uint32_t DIV_FLAG);
+void DIV_ClearFlag(uint32_t DIV_FLAG);
+ITStatus DIV_GetITStatus(uint32_t DIV_IT);
+void DIV_ClearITPendingBit(uint32_t DIV_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_DIV_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dma.h

@@ -0,0 +1,783 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_dma.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the DMA firmware
+  *               library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_DMA_H
+#define __FT32F0XX_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup DMA
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  DMA Init structures definition
+  */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction     */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel.
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction     */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode     */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size        */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size            */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level              */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory            */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+  * @{
+  */
+
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST              DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+                         ((DIR) == DMA_DIR_PeripheralDST))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode
+  * @{
+  */
+
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable           DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+                                            ((STATE) == DMA_PeripheralInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode
+  * @{
+  */
+
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable               DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+                                        ((STATE) == DMA_MemoryInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode
+  * @{
+  */
+
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define DMA_Mode_Circular                  DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              DMA_CCR_PL
+#define DMA_Priority_High                  DMA_CCR_PL_1
+#define DMA_Priority_Medium                DMA_CCR_PL_0
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory
+  * @{
+  */
+
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Remap_Config
+  * @{
+  */
+#define DMAx_CHANNEL1_RMP                                     0x00000000
+#define DMAx_CHANNEL2_RMP                                     0x10000000
+#define DMAx_CHANNEL3_RMP                                     0x20000000
+#define DMAx_CHANNEL4_RMP                                     0x30000000
+#define DMAx_CHANNEL5_RMP                                     0x40000000
+#define DMAx_CHANNEL6_RMP                                     0x50000000
+#define DMAx_CHANNEL7_RMP                                     0x60000000
+
+
+#define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \
+                               ((LIST) == DMA2))
+
+/****************** DMA1 remap bit field definition********************/
+/* DMA1 - Channel 1 */
+#define DMA1_CH1_DEFAULT      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH1_ADC          (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC)       /*!< Remap ADC on DMA1 Channel 1*/
+#define DMA1_CH1_TIM17_CH1    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define DMA1_CH1_TIM17_UP     (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 1 */
+#define DMA1_CH1_USART1_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART2_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART3_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART4_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART5_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART6_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART7_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define DMA1_CH1_USART8_RX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
+/* DMA1 - Channel 2 */
+#define DMA1_CH2_DEFAULT      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH2_ADC          (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC)       /*!< Remap ADC on DMA1 channel 2 */
+#define DMA1_CH2_I2C1_TX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define DMA1_CH2_SPI1_RX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX)   /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define DMA1_CH2_TIM1_CH1     (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define DMA1_CH2_TIM17_CH1    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define DMA1_CH2_TIM17_UP     (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 2 */
+#define DMA1_CH2_USART1_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART2_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART3_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART4_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART5_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART6_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART7_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define DMA1_CH2_USART8_TX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
+/* DMA1 - Channel 3 */
+#define DMA1_CH3_DEFAULT      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMAx */
+#define DMA1_CH3_TIM6_UP      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA1 channel 3 */
+#define DMA1_CH3_DAC_CH1      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1)   /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#define DMA1_CH3_I2C1_RX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define DMA1_CH3_SPI1_TX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX)   /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define DMA1_CH3_TIM1_CH2     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#define DMA1_CH3_TIM2_CH2     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#define DMA1_CH3_TIM16_CH1    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define DMA1_CH3_TIM16_UP     (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 3 */
+#define DMA1_CH3_USART1_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART2_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART3_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART4_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART5_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART6_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART7_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define DMA1_CH3_USART8_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
+/* DMA1 - Channel 4 */
+#define DMA1_CH4_DEFAULT      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH4_TIM7_UP      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA1 channel 4 */
+#define DMA1_CH4_DAC_CH2      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2)   /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#define DMA1_CH4_I2C2_TX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX)   /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define DMA1_CH4_SPI2_RX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#define DMA1_CH4_TIM2_CH4     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#define DMA1_CH4_TIM3_CH1     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define DMA1_CH4_TIM3_TRIG    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define DMA1_CH4_TIM16_CH1    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define DMA1_CH4_TIM16_UP     (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 4 */
+#define DMA1_CH4_USART1_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART2_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART3_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART4_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART5_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART6_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART7_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define DMA1_CH4_USART8_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
+/* DMA1 - Channel 5 */
+#define DMA1_CH5_DEFAULT      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH5_I2C2_RX      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX)   /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define DMA1_CH5_SPI2_TX      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX)   /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define DMA1_CH5_TIM1_CH3     (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define DMA1_CH5_USART1_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART2_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART3_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART4_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART5_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART6_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART7_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define DMA1_CH5_USART8_RX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
+/* DMA1 - Channel 6 */
+#define DMA1_CH6_DEFAULT      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH6_I2C1_TX      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define DMA1_CH6_SPI2_RX      (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define DMA1_CH6_TIM1_CH1     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM1_CH2     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define DMA1_CH6_TIM1_CH3     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define DMA1_CH6_TIM3_CH1     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM3_TRIG    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define DMA1_CH6_TIM16_CH1    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define DMA1_CH6_TIM16_UP     (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 6 */
+#define DMA1_CH6_USART1_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART2_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART3_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART4_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART5_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART6_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART7_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define DMA1_CH6_USART8_RX    (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
+/* DMA1 - Channel 7 */
+#define DMA1_CH7_DEFAULT      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT)       /*!< Default remap position for DMA1 */
+#define DMA1_CH7_I2C1_RX      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define DMA1_CH7_SPI2_TX      (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX)   /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define DMA1_CH7_TIM2_CH2     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define DMA1_CH7_TIM2_CH4     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define DMA1_CH7_TIM17_CH1    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define DMA1_CH7_TIM17_UP     (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 7 */
+#define DMA1_CH7_USART1_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART2_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART3_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART4_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART5_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART6_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART7_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define DMA1_CH7_USART8_TX    (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
+
+#define IS_DMA1_REMAP(REMAP)  ((REMAP == DMA1_CH1_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH1_ADC)       ||\
+                                    (REMAP == DMA1_CH1_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH1_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH1_USART1_RX) ||\
+                                    (REMAP == DMA1_CH1_USART2_RX) ||\
+                                    (REMAP == DMA1_CH1_USART3_RX) ||\
+                                    (REMAP == DMA1_CH1_USART4_RX) ||\
+                                    (REMAP == DMA1_CH1_USART5_RX) ||\
+                                    (REMAP == DMA1_CH1_USART6_RX) ||\
+                                    (REMAP == DMA1_CH1_USART7_RX) ||\
+                                    (REMAP == DMA1_CH1_USART8_RX) ||\
+                                    (REMAP == DMA1_CH2_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH2_ADC)       ||\
+                                    (REMAP == DMA1_CH2_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH2_SPI1_RX)   ||\
+                                    (REMAP == DMA1_CH2_TIM1_CH1)  ||\
+                                    (REMAP == DMA1_CH2_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH2_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH2_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH2_USART1_TX) ||\
+                                    (REMAP == DMA1_CH2_USART2_TX) ||\
+                                    (REMAP == DMA1_CH2_USART3_TX) ||\
+                                    (REMAP == DMA1_CH2_USART4_TX) ||\
+                                    (REMAP == DMA1_CH2_USART5_TX) ||\
+                                    (REMAP == DMA1_CH2_USART6_TX) ||\
+                                    (REMAP == DMA1_CH2_USART7_TX) ||\
+                                    (REMAP == DMA1_CH2_USART8_TX) ||\
+                                    (REMAP == DMA1_CH3_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH3_TIM6_UP)   ||\
+                                    (REMAP == DMA1_CH3_DAC_CH1)   ||\
+                                    (REMAP == DMA1_CH3_I2C1_RX)   ||\
+                                    (REMAP == DMA1_CH3_SPI1_TX)   ||\
+                                    (REMAP == DMA1_CH3_TIM1_CH2)  ||\
+                                    (REMAP == DMA1_CH3_TIM2_CH2)  ||\
+                                    (REMAP == DMA1_CH3_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH3_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH3_USART1_RX) ||\
+                                    (REMAP == DMA1_CH3_USART2_RX) ||\
+                                    (REMAP == DMA1_CH3_USART3_RX) ||\
+                                    (REMAP == DMA1_CH3_USART4_RX) ||\
+                                    (REMAP == DMA1_CH3_USART5_RX) ||\
+                                    (REMAP == DMA1_CH3_USART6_RX) ||\
+                                    (REMAP == DMA1_CH3_USART7_RX) ||\
+                                    (REMAP == DMA1_CH3_USART8_RX) ||\
+                                    (REMAP == DMA1_CH4_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH4_TIM7_UP)   ||\
+                                    (REMAP == DMA1_CH4_DAC_CH2)   ||\
+                                    (REMAP == DMA1_CH4_I2C2_TX)   ||\
+                                    (REMAP == DMA1_CH4_SPI2_RX)   ||\
+                                    (REMAP == DMA1_CH4_TIM2_CH4)  ||\
+                                    (REMAP == DMA1_CH4_TIM3_CH1)  ||\
+                                    (REMAP == DMA1_CH4_TIM3_TRIG) ||\
+                                    (REMAP == DMA1_CH4_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH4_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH4_USART1_TX) ||\
+                                    (REMAP == DMA1_CH4_USART2_TX) ||\
+                                    (REMAP == DMA1_CH4_USART3_TX) ||\
+                                    (REMAP == DMA1_CH4_USART4_TX) ||\
+                                    (REMAP == DMA1_CH4_USART5_TX) ||\
+                                    (REMAP == DMA1_CH4_USART6_TX) ||\
+                                    (REMAP == DMA1_CH4_USART7_TX) ||\
+                                    (REMAP == DMA1_CH4_USART8_TX) ||\
+                                    (REMAP == DMA1_CH5_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH5_I2C2_RX)   ||\
+                                    (REMAP == DMA1_CH5_SPI2_TX)   ||\
+                                    (REMAP == DMA1_CH5_TIM1_CH3)  ||\
+                                    (REMAP == DMA1_CH5_USART1_RX) ||\
+                                    (REMAP == DMA1_CH5_USART2_RX) ||\
+                                    (REMAP == DMA1_CH5_USART3_RX) ||\
+                                    (REMAP == DMA1_CH5_USART4_RX) ||\
+                                    (REMAP == DMA1_CH5_USART5_RX) ||\
+                                    (REMAP == DMA1_CH5_USART6_RX) ||\
+                                    (REMAP == DMA1_CH5_USART7_RX) ||\
+                                    (REMAP == DMA1_CH5_USART8_RX) ||\
+                                    (REMAP == DMA1_CH6_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH6_I2C1_TX)   ||\
+                                    (REMAP == DMA1_CH6_SPI2_RX)   ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH1)  ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH2)  ||\
+                                    (REMAP == DMA1_CH6_TIM1_CH3)  ||\
+                                    (REMAP == DMA1_CH6_TIM3_CH1)  ||\
+                                    (REMAP == DMA1_CH6_TIM3_TRIG) ||\
+                                    (REMAP == DMA1_CH6_TIM16_CH1) ||\
+                                    (REMAP == DMA1_CH6_TIM16_UP)  ||\
+                                    (REMAP == DMA1_CH6_USART1_RX) ||\
+                                    (REMAP == DMA1_CH6_USART2_RX) ||\
+                                    (REMAP == DMA1_CH6_USART3_RX) ||\
+                                    (REMAP == DMA1_CH6_USART4_RX) ||\
+                                    (REMAP == DMA1_CH6_USART5_RX) ||\
+                                    (REMAP == DMA1_CH6_USART6_RX) ||\
+                                    (REMAP == DMA1_CH6_USART7_RX) ||\
+                                    (REMAP == DMA1_CH6_USART8_RX) ||\
+                                    (REMAP == DMA1_CH7_DEFAULT)   ||\
+                                    (REMAP == DMA1_CH7_I2C1_RX)   ||\
+                                    (REMAP == DMA1_CH7_SPI2_TX)   ||\
+                                    (REMAP == DMA1_CH7_TIM2_CH2)  ||\
+                                    (REMAP == DMA1_CH7_TIM2_CH4)  ||\
+                                    (REMAP == DMA1_CH7_TIM17_CH1) ||\
+                                    (REMAP == DMA1_CH7_TIM17_UP)  ||\
+                                    (REMAP == DMA1_CH7_USART1_TX) ||\
+                                    (REMAP == DMA1_CH7_USART2_TX) ||\
+                                    (REMAP == DMA1_CH7_USART3_TX) ||\
+                                    (REMAP == DMA1_CH7_USART4_TX) ||\
+                                    (REMAP == DMA1_CH7_USART5_TX) ||\
+                                    (REMAP == DMA1_CH7_USART6_TX) ||\
+                                    (REMAP == DMA1_CH7_USART7_TX) ||\
+                                    (REMAP == DMA1_CH7_USART8_TX))
+
+/****************** DMA2 remap bit field definition********************/
+/* DMA2 - Channel 1 */
+#define DMA2_CH1_DEFAULT      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */
+#define DMA2_CH1_I2C2_TX      (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX)   /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define DMA2_CH1_USART1_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART2_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART3_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART4_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART5_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART6_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART7_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define DMA2_CH1_USART8_TX    (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
+/* DMA2 - Channel 2 */
+#define DMA2_CH2_DEFAULT      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */
+#define DMA2_CH2_I2C2_RX      (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX)   /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART1_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART2_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART3_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART4_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART5_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART6_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART7_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define DMA2_CH2_USART8_RX    (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
+/* DMA2 - Channel 3 */
+#define DMA2_CH3_DEFAULT      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */
+#define DMA2_CH3_TIM6_UP      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA2 channel 3 */
+#define DMA2_CH3_DAC_CH1      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1)   /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define DMA2_CH3_SPI1_RX      (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX)   /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART1_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART2_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART3_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART4_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART5_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART6_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART7_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define DMA2_CH3_USART8_RX    (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
+/* DMA2 - Channel 4 */
+#define DMA2_CH4_DEFAULT      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */
+#define DMA2_CH4_TIM7_UP      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA2 channel 4 */
+#define DMA2_CH4_DAC_CH2      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2)   /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define DMA2_CH4_SPI1_TX      (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX)   /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART1_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART2_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART3_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART4_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART5_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART6_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART7_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define DMA2_CH4_USART8_TX    (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
+/* DMA2 - Channel 5 */
+#define DMA2_CH5_DEFAULT      (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT)       /*!< Default remap position for DMA2 */
+#define DMA2_CH5_ADC          (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC)       /*!< Remap ADC on DMA2 channel 5 */
+#define DMA2_CH5_USART1_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART2_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART3_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART4_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART5_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART6_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART7_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define DMA2_CH5_USART8_TX    (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+#define IS_DMA2_REMAP(REMAP)  ((REMAP == DMA2_CH1_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH1_I2C2_TX)   ||\
+                                    (REMAP == DMA2_CH1_USART1_TX) ||\
+                                    (REMAP == DMA2_CH1_USART2_TX) ||\
+                                    (REMAP == DMA2_CH1_USART3_TX) ||\
+                                    (REMAP == DMA2_CH1_USART4_TX) ||\
+                                    (REMAP == DMA2_CH1_USART5_TX) ||\
+                                    (REMAP == DMA2_CH1_USART6_TX) ||\
+                                    (REMAP == DMA2_CH1_USART7_TX) ||\
+                                    (REMAP == DMA2_CH1_USART8_TX) ||\
+                                    (REMAP == DMA2_CH2_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH2_I2C2_RX)   ||\
+                                    (REMAP == DMA2_CH2_USART1_RX) ||\
+                                    (REMAP == DMA2_CH2_USART2_RX) ||\
+                                    (REMAP == DMA2_CH2_USART3_RX) ||\
+                                    (REMAP == DMA2_CH2_USART4_RX) ||\
+                                    (REMAP == DMA2_CH2_USART5_RX) ||\
+                                    (REMAP == DMA2_CH2_USART6_RX) ||\
+                                    (REMAP == DMA2_CH2_USART7_RX) ||\
+                                    (REMAP == DMA2_CH2_USART8_RX) ||\
+                                    (REMAP == DMA2_CH3_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH3_TIM6_UP)   ||\
+                                    (REMAP == DMA2_CH3_DAC_CH1)   ||\
+                                    (REMAP == DMA2_CH3_SPI1_RX)   ||\
+                                    (REMAP == DMA2_CH3_USART1_RX) ||\
+                                    (REMAP == DMA2_CH3_USART2_RX) ||\
+                                    (REMAP == DMA2_CH3_USART3_RX) ||\
+                                    (REMAP == DMA2_CH3_USART4_RX) ||\
+                                    (REMAP == DMA2_CH3_USART5_RX) ||\
+                                    (REMAP == DMA2_CH3_USART6_RX) ||\
+                                    (REMAP == DMA2_CH3_USART7_RX) ||\
+                                    (REMAP == DMA2_CH3_USART8_RX) ||\
+                                    (REMAP == DMA2_CH4_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH4_TIM7_UP)   ||\
+                                    (REMAP == DMA2_CH4_DAC_CH2)   ||\
+                                    (REMAP == DMA2_CH4_SPI1_TX)   ||\
+                                    (REMAP == DMA2_CH4_USART1_TX) ||\
+                                    (REMAP == DMA2_CH4_USART2_TX) ||\
+                                    (REMAP == DMA2_CH4_USART3_TX) ||\
+                                    (REMAP == DMA2_CH4_USART4_TX) ||\
+                                    (REMAP == DMA2_CH4_USART5_TX) ||\
+                                    (REMAP == DMA2_CH4_USART6_TX) ||\
+                                    (REMAP == DMA2_CH4_USART7_TX) ||\
+                                    (REMAP == DMA2_CH4_USART8_TX) ||\
+                                    (REMAP == DMA2_CH5_DEFAULT)   ||\
+                                    (REMAP == DMA2_CH5_ADC)       ||\
+                                    (REMAP == DMA2_CH5_USART1_TX) ||\
+                                    (REMAP == DMA2_CH5_USART2_TX) ||\
+                                    (REMAP == DMA2_CH5_USART3_TX) ||\
+                                    (REMAP == DMA2_CH5_USART4_TX) ||\
+                                    (REMAP == DMA2_CH5_USART5_TX) ||\
+                                    (REMAP == DMA2_CH5_USART6_TX) ||\
+                                    (REMAP == DMA2_CH5_USART7_TX) ||\
+                                    (REMAP == DMA2_CH5_USART8_TX ))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition
+  * @{
+  */
+
+#define DMA_IT_TC                          DMA_CCR_TCIE
+#define DMA_IT_HT                          DMA_CCR_HTIE
+#define DMA_IT_TE                          DMA_CCR_TEIE
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        DMA_ISR_GIF1
+#define DMA1_IT_TC1                        DMA_ISR_TCIF1
+#define DMA1_IT_HT1                        DMA_ISR_HTIF1
+#define DMA1_IT_TE1                        DMA_ISR_TEIF1
+#define DMA1_IT_GL2                        DMA_ISR_GIF2
+#define DMA1_IT_TC2                        DMA_ISR_TCIF2
+#define DMA1_IT_HT2                        DMA_ISR_HTIF2
+#define DMA1_IT_TE2                        DMA_ISR_TEIF2
+#define DMA1_IT_GL3                        DMA_ISR_GIF3
+#define DMA1_IT_TC3                        DMA_ISR_TCIF3
+#define DMA1_IT_HT3                        DMA_ISR_HTIF3
+#define DMA1_IT_TE3                        DMA_ISR_TEIF3
+#define DMA1_IT_GL4                        DMA_ISR_GIF4
+#define DMA1_IT_TC4                        DMA_ISR_TCIF4
+#define DMA1_IT_HT4                        DMA_ISR_HTIF4
+#define DMA1_IT_TE4                        DMA_ISR_TEIF4
+#define DMA1_IT_GL5                        DMA_ISR_GIF5
+#define DMA1_IT_TC5                        DMA_ISR_TCIF5
+#define DMA1_IT_HT5                        DMA_ISR_HTIF5
+#define DMA1_IT_TE5                        DMA_ISR_TEIF5
+#define DMA1_IT_GL6                        DMA_ISR_GIF6
+#define DMA1_IT_TC6                        DMA_ISR_TCIF6
+#define DMA1_IT_HT6                        DMA_ISR_HTIF6
+#define DMA1_IT_TE6                        DMA_ISR_TEIF6
+#define DMA1_IT_GL7                        DMA_ISR_GIF7
+#define DMA1_IT_TC7                        DMA_ISR_TCIF7
+#define DMA1_IT_HT7                        DMA_ISR_HTIF7
+#define DMA1_IT_TE7                        DMA_ISR_TEIF7
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition
+  * @{
+  */
+#define DMA1_FLAG_GL1                      DMA_ISR_GIF1
+#define DMA1_FLAG_TC1                      DMA_ISR_TCIF1
+#define DMA1_FLAG_HT1                      DMA_ISR_HTIF1
+#define DMA1_FLAG_TE1                      DMA_ISR_TEIF1
+#define DMA1_FLAG_GL2                      DMA_ISR_GIF2
+#define DMA1_FLAG_TC2                      DMA_ISR_TCIF2
+#define DMA1_FLAG_HT2                      DMA_ISR_HTIF2
+#define DMA1_FLAG_TE2                      DMA_ISR_TEIF2
+#define DMA1_FLAG_GL3                      DMA_ISR_GIF3
+#define DMA1_FLAG_TC3                      DMA_ISR_TCIF3
+#define DMA1_FLAG_HT3                      DMA_ISR_HTIF3
+#define DMA1_FLAG_TE3                      DMA_ISR_TEIF3
+#define DMA1_FLAG_GL4                      DMA_ISR_GIF4
+#define DMA1_FLAG_TC4                      DMA_ISR_TCIF4
+#define DMA1_FLAG_HT4                      DMA_ISR_HTIF4
+#define DMA1_FLAG_TE4                      DMA_ISR_TEIF4
+#define DMA1_FLAG_GL5                      DMA_ISR_GIF5
+#define DMA1_FLAG_TC5                      DMA_ISR_TCIF5
+#define DMA1_FLAG_HT5                      DMA_ISR_HTIF5
+#define DMA1_FLAG_TE5                      DMA_ISR_TEIF5
+#define DMA1_FLAG_GL6                      DMA_ISR_GIF6
+#define DMA1_FLAG_TC6                      DMA_ISR_TCIF6
+#define DMA1_FLAG_HT6                      DMA_ISR_HTIF6
+#define DMA1_FLAG_TE6                      DMA_ISR_TEIF6
+#define DMA1_FLAG_GL7                      DMA_ISR_GIF7
+#define DMA1_FLAG_TC7                      DMA_ISR_TCIF7
+#define DMA1_FLAG_HT7                      DMA_ISR_HTIF7
+#define DMA1_FLAG_TE7                      DMA_ISR_TEIF7
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions******************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_exti.h

@@ -0,0 +1,186 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_exti.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the EXTI
+  *               firmware library
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_EXTI_H
+#define __FT32F0XX_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup EXTI
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  EXTI mode enumeration
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+  * @brief  EXTI Trigger enumeration
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+  * @brief  EXTI Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+/** @defgroup EXTI_Lines
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0  */
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1  */
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2  */
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3  */
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4  */
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5  */
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6  */
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7  */
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8  */
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9  */
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 */
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< Internal interrupt line 17
+                                                      Connected to the RTC Alarm
+                                                      event */
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< Internal interrupt line 18
+                                                      Connected to the USB
+                                                      event*/
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< Internal interrupt line 19
+                                                      Connected to the RTC Tamper
+                                                      and Time Stamp events */
+#define EXTI_Line20      ((uint32_t)0x00100000)   /*!< Internal interrupt line 20
+                                                      Connected to the RTC wakeup
+                                                      event */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< Internal interrupt line 21
+                                                      Connected to the Comparator 1
+                                                      event */
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< Internal interrupt line 22
+                                                      Connected to the Comparator 2
+                                                      event*/
+#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< Internal interrupt line 23
+                                                      Connected to the I2C1 wakeup
+                                                      event*/
+#define EXTI_Line25      ((uint32_t)0x02000000)  /*!< Internal interrupt line 25
+                                                      Connected to the USART1 wakeup
+                                                      event */
+#define EXTI_Line26      ((uint32_t)0x04000000)  /*!< Internal interrupt line 26
+                                                      Connected to the USART2 wakeup
+                                                      event*/
+#define EXTI_Line27      ((uint32_t)0x08000000)  /*!< Internal interrupt line 27
+                                                      Connected to the CEC wakeup
+                                                      event */
+#define EXTI_Line31      ((uint32_t)0x80000000)  /*!< Internal interrupt line 31
+                                                      Connected to the VDD USB monitor
+                                                      event */
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \
+                                ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \
+                                ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_flash.h

@@ -0,0 +1,389 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_flash.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the FLASH
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_FLASH_H
+#define __FT32F0XX_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  FLASH Status
+  */
+typedef enum
+{
+  FLASH_BUSY = 1,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Latency
+  * @{
+  */
+#define FLASH_Latency_0                 ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                 ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                 ((uint32_t)0x00000002)
+#define FLASH_Latency_3                 ((uint32_t)0x00000003)
+#define FLASH_Latency_4                 ((uint32_t)0x00000004)
+#define FLASH_Latency_5                 ((uint32_t)0x00000005)
+#define FLASH_Latency_6                 ((uint32_t)0x00000006)
+#define FLASH_Latency_7                 ((uint32_t)0x00000007)
+#define FLASH_Latency_8                 ((uint32_t)0x00000008)
+#define FLASH_Latency_9                 ((uint32_t)0x00000009)
+#define FLASH_Latency_10                ((uint32_t)0x0000000a)
+#define FLASH_Latency_11                ((uint32_t)0x0000000b)
+#define FLASH_Latency_12                ((uint32_t)0x0000000c)
+#define FLASH_Latency_13                ((uint32_t)0x0000000d)
+#define FLASH_Latency_14                ((uint32_t)0x0000000e)
+#define FLASH_Latency_15                ((uint32_t)0x0000000f)
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                    ((LATENCY) == FLASH_Latency_2 ) || \
+                                    ((LATENCY) == FLASH_Latency_3 ) || \
+                                    ((LATENCY) == FLASH_Latency_4 ) || \
+                                    ((LATENCY) == FLASH_Latency_5 ) || \
+                                    ((LATENCY) == FLASH_Latency_6 ) || \
+                                    ((LATENCY) == FLASH_Latency_7 ) || \
+                                    ((LATENCY) == FLASH_Latency_8 ) || \
+                                    ((LATENCY) == FLASH_Latency_9 ) || \
+                                    ((LATENCY) == FLASH_Latency_10) || \
+                                    ((LATENCY) == FLASH_Latency_11) || \
+                                    ((LATENCY) == FLASH_Latency_12) || \
+                                    ((LATENCY) == FLASH_Latency_13) || \
+                                    ((LATENCY) == FLASH_Latency_14) || \
+                                    ((LATENCY) == FLASH_Latency_15))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupts
+  * @{
+  */
+
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE  /*!< End of programming interrupt source */
+#define FLASH_IT_ERR                   FLASH_CR_ERRIE  /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Address
+  * @{
+  */
+
+#if defined(FT32F030X8)  /*64K devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
+#elif defined (FT32F072xB)  /*128K devices */
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_DATA_ADDRESS
+  * @{
+  */
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Write_Protection
+  * @{
+  */
+
+#define OB_WRP_Pages0to7               ((uint32_t)0x00000001) /* Write protection of page 0     to  7     */
+#define OB_WRP_Pages8to15              ((uint32_t)0x00000002) /* Write protection of page 8     to  15    */
+#define OB_WRP_Pages16to23             ((uint32_t)0x00000004) /* Write protection of page 16    to  23    */
+#define OB_WRP_Pages24to31             ((uint32_t)0x00000008) /* Write protection of page 24    to  31    */
+#define OB_WRP_Pages32to39             ((uint32_t)0x00000010) /* Write protection of page 32    to  39    */
+#define OB_WRP_Pages40to47             ((uint32_t)0x00000020) /* Write protection of page 40    to  47    */
+#define OB_WRP_Pages48to55             ((uint32_t)0x00000040) /* Write protection of page 48    to  55    */
+#define OB_WRP_Pages56to63             ((uint32_t)0x00000080) /* Write protection of page 56    to  63    */
+#define OB_WRP_Pages64to71             ((uint32_t)0x00000100) /* Write protection of page 64    to  71    */
+#define OB_WRP_Pages72to79             ((uint32_t)0x00000200) /* Write protection of page 72    to  79    */
+#define OB_WRP_Pages80to87             ((uint32_t)0x00000400) /* Write protection of page 80    to  87    */
+#define OB_WRP_Pages88to95             ((uint32_t)0x00000800) /* Write protection of page 88    to  95    */
+#define OB_WRP_Pages96to103            ((uint32_t)0x00001000) /* Write protection of page 96    to  103   */
+#define OB_WRP_Pages104to111           ((uint32_t)0x00002000) /* Write protection of page 104   to  111   */
+#define OB_WRP_Pages112to119           ((uint32_t)0x00004000) /* Write protection of page 112   to  119   */
+#define OB_WRP_Pages120to127           ((uint32_t)0x00008000) /* Write protection of page 120   to  127   */
+
+#define OB_WRP_AllPages                ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection
+  * @{
+  */
+
+/**
+  * @brief  FLASH_Read Protection Level
+  */
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+                                                it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog
+  * @{
+  */
+#if defined (FT32F072xB)
+    #define OB_IWDG_SW                     ((uint8_t)0x01)  /*!< Software IWDG selected */
+    #define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#else
+    #define OB_IWDG_SW                     ((uint8_t)0x00)  /*!< Software IWDG selected */
+    #define OB_IWDG_HW                     ((uint8_t)0x01)  /*!< Hardware IWDG selected */
+#endif
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_BOOT1
+  * @{
+  */
+
+#define OB_BOOT1_RESET                 ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET                   ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
+  * @{
+  */
+
+#define OB_VDDA_ANALOG_ON              ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF             ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
+  * @{
+  */
+
+#define OB_SRAM_PARITY_SET              ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET            ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags
+  * @{
+  */
+
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY     /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR               FLASH_SR_PGERR   /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP     /*!< FLASH End of Programming flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Timeout_definition
+  * @{
+  */
+#define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x000B0000)
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Legacy
+  * @{
+  */
+#define FLASH_WRProt_Pages0to7         OB_WRP_Pages0to7
+#define FLASH_WRProt_Pages8to15        OB_WRP_Pages8to15
+#define FLASH_WRProt_Pages16to23       OB_WRP_Pages16to23
+#define FLASH_WRProt_Pages24to31       OB_WRP_Pages24to31
+#define FLASH_WRProt_Pages32to39       OB_WRP_Pages32to39
+#define FLASH_WRProt_Pages40to47       OB_WRP_Pages40to47
+#define FLASH_WRProt_Pages48to55       OB_WRP_Pages48to55
+#define FLASH_WRProt_Pages56to63       OB_WRP_Pages56to63
+#define FLASH_WRProt_Pages64to71       OB_WRP_Pages64to71
+#define FLASH_WRProt_Pages72to79       OB_WRP_Pages72to79
+#define FLASH_WRProt_Pages80to87       OB_WRP_Pages80to87
+#define FLASH_WRProt_Pages88to95       OB_WRP_Pages88to95
+#define FLASH_WRProt_Pages96to103      OB_WRP_Pages96to103
+#define FLASH_WRProt_Pages104to111     OB_WRP_Pages104to111
+#define FLASH_WRProt_Pages112to119     OB_WRP_Pages112to119
+#define FLASH_WRProt_Pages120to127     OB_WRP_Pages120to127
+
+
+#define FLASH_WRProt_AllPages          OB_WRP_AllPages
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/**
+  * @brief  FLASH memory functions that can be executed from FLASH.
+  */
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+#if defined(FT32F072xB)
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+#endif
+
+/* FLASH Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+#if defined(FT32F072xB)
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+#else
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint32_t Data);
+#endif
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* FLASH Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/** @defgroup FLASH_Legacy
+  * @{
+  */
+#define FLASH_EraseOptionBytes               FLASH_OB_Erase
+#define FLASH_EnableWriteProtection          FLASH_OB_EnableWRP
+#define FLASH_UserOptionByteConfig           FLASH_OB_UserConfig
+#define FLASH_ProgramOption4ByteData         FLASH_OB_ProgramData
+#define FLASH_GetUserOptionByte              FLASH_OB_GetUser
+#define FLASH_GetWriteProtectionOptionByte   FLASH_OB_GetWRP
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_FLASH_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_gpio.h

@@ -0,0 +1,370 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_gpio.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the GPIO
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F030X8_GPIO_H
+#define __FT32F030X8_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+
+/** @addtogroup GPIO
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                     ((PERIPH) == GPIOB))
+
+/** @defgroup Configuration_Mode_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode              */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode             */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+  * @}
+  */
+
+/** @defgroup Output_type_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+  * @}
+  */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_Speed_Level_1  = 0x00, /*!< I/O output speed: Low 2 MHz */
+  GPIO_Speed_Level_2  = 0x01, /*!< I/O output speed: Medium 10 MHz */
+  GPIO_Speed_Level_3  = 0x03  /*!< I/O output speed: High 50 MHz */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+                              ((SPEED) == GPIO_Speed_Level_3))
+/**
+  * @}
+  */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+/**
+  * @}
+  */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+  * @{
+  */
+typedef enum
+{
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+  * @}
+  */
+
+/**
+  * @brief  GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef   */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef  */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef  */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef   */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define
+  * @{
+  */
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected    */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected    */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected    */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected    */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected    */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected    */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected    */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected    */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected    */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected    */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected   */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected   */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected   */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected   */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected   */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected   */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources
+  * @{
+  */
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternate_function_selection_define
+  * @{
+  */
+
+/**
+  * @brief  AF 0 selection
+  */
+#define GPIO_AF_0            ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
+                                                MCO, SWDAT, SWCLK, TIM14, BOOT,
+                                                USART1, CEC, IR_OUT, SPI2, TS, TIM3,
+                                                USART4, CAN, TIM3, USART2, USART3,
+                                                CRS, TIM16, TIM1 */
+/**
+  * @brief  AF 1 selection
+  */
+#define GPIO_AF_1            ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
+                                                EVENTOUT, I2C1, I2C2, TIM15, SPI2,
+                                                USART3, TS, SPI1 */
+/**
+  * @brief  AF 2 selection
+  */
+#define GPIO_AF_2            ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
+                                                USB */
+/**
+  * @brief  AF 3 selection
+  */
+#define GPIO_AF_3            ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
+
+/**
+  * @brief  AF 4 selection
+  */
+#define GPIO_AF_4            ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
+                                                I2C1 */
+
+/**
+  * @brief  AF 5 selection
+  */
+#define GPIO_AF_5            ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2,
+                                                MCO, I2C1, USB */
+
+/**
+  * @brief  AF 6 selection
+  */
+#define GPIO_AF_6            ((uint8_t)0x06) /* EVENTOUT */
+/**
+  * @brief  AF 7 selection
+  */
+#define GPIO_AF_7            ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
+                          ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
+                          ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
+                          ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Speed_Legacy
+  * @{
+  */
+
+#define GPIO_Speed_2MHz  GPIO_Speed_Level_1   /*!< I/O output speed: Low 2 MHz  */
+#define GPIO_Speed_10MHz GPIO_Speed_Level_2   /*!< I/O output speed: Medium 10 MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3   /*!< I/O output speed: High 50 MHz */
+
+/** @defgroup GPIO_LEDM Only Use in GPIOA and GPIOB
+  * @}
+  */
+#define GPIO_LEDM_0         ((uint32_t)(0x00000001))
+#define GPIO_LEDM_1         ((uint32_t)(0x00000002))
+#define GPIO_LEDM_3         ((uint32_t)(0x00000008))
+#define GPIO_LEDM_4         ((uint32_t)(0x00000010))
+#define GPIO_LEDM_5         ((uint32_t)(0x00000020))
+#define GPIO_LEDM_6         ((uint32_t)(0x00000040))
+#define GPIO_LEDM_7         ((uint32_t)(0x00000080))
+
+#define GPIO_LEDM_8         ((uint32_t)(0x00000100))
+#define GPIO_LEDM_9         ((uint32_t)(0x00000200))
+#define GPIO_LEDM_10        ((uint32_t)(0x00000400))
+#define GPIO_LEDM_13        ((uint32_t)(0x00002000))
+#define GPIO_LEDM_14        ((uint32_t)(0x00004000))
+#define GPIO_LEDM_15        ((uint32_t)(0x00008000))
+
+
+#define IS_GPIO_LEDM(LEDM)      (((LEDM) == GPIO_LEDM_0) ||\
+                                                                ((LEDM) == GPIO_LEDM_1) ||\
+                                                                ((LEDM) == GPIO_LEDM_3) ||\
+                                                                ((LEDM) == GPIO_LEDM_4) ||\
+                                                                ((LEDM) == GPIO_LEDM_5) ||\
+                                                                ((LEDM) == GPIO_LEDM_6) ||\
+                                                                ((LEDM) == GPIO_LEDM_7) ||\
+                                                                ((LEDM) == GPIO_LEDM_8) ||\
+                                                                ((LEDM) == GPIO_LEDM_9) ||\
+                                                                ((LEDM) == GPIO_LEDM_10) ||\
+                                                                ((LEDM) == GPIO_LEDM_13) ||\
+                                                                ((LEDM) == GPIO_LEDM_14) ||\
+                                                                ((LEDM) == GPIO_LEDM_15))
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+/*GPIO LED*/
+void GPIO_LedmConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_LEDMx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_i2c.h

@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_i2c.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the I2C firmware
+  *                     library
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_I2C_H
+#define __FT32F0XX_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  I2C Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t I2C_Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                         This parameter must be set by referring to I2C_Timing_Config_Tool*/
+
+  uint32_t I2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                         This parameter can be a value of @ref I2C_Analog_Filter*/
+
+  uint32_t I2C_DigitalFilter;       /*!< Configures the digital noise filter.
+                                         This parameter can be a number between 0x00 and 0x0F*/
+
+  uint32_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode*/
+
+  uint32_t I2C_OwnAddress1;         /*!< Specifies the device own address 1.
+                                         This parameter can be a 7-bit or 10-bit address*/
+
+  uint32_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement*/
+
+  uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address*/
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2))
+
+#define IS_I2C_1_PERIPH(PERIPH)         ((PERIPH) == I2C1)
+
+/** @defgroup I2C_Analog_Filter
+  * @{
+  */
+
+#define I2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable        I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_AnalogFilter_Enable) || \
+                                         ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Digital_Filter
+  * @{
+  */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_mode
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice            I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost              I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2C) || \
+                                         ((MODE) == I2C_Mode_SMBusDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint32_t)0x00000000)
+#define I2C_Ack_Disable                 I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK)                 (((ACK) == I2C_Ack_Enable) || \
+                                         ((ACK) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit   I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction
+  * @{
+  */
+
+#define I2C_Direction_Transmitter       ((uint16_t)0x0000)
+#define I2C_Direction_Receiver          ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                         ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DMA_transfer_requests
+  * @{
+  */
+
+#define I2C_DMAReq_Tx                   I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx                   I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_slave_address
+  * @{
+  */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_own_address2
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address2_mask
+  * @{
+  */
+
+#define I2C_OA2_NoMask                  ((uint8_t)0x00)
+#define I2C_OA2_Mask01                  ((uint8_t)0x01)
+#define I2C_OA2_Mask02                  ((uint8_t)0x02)
+#define I2C_OA2_Mask03                  ((uint8_t)0x03)
+#define I2C_OA2_Mask04                  ((uint8_t)0x04)
+#define I2C_OA2_Mask05                  ((uint8_t)0x05)
+#define I2C_OA2_Mask06                  ((uint8_t)0x06)
+#define I2C_OA2_Mask07                  ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NoMask) || \
+                                         ((MASK) == I2C_OA2_Mask01) || \
+                                         ((MASK) == I2C_OA2_Mask02) || \
+                                         ((MASK) == I2C_OA2_Mask03) || \
+                                         ((MASK) == I2C_OA2_Mask04) || \
+                                         ((MASK) == I2C_OA2_Mask05) || \
+                                         ((MASK) == I2C_OA2_Mask06) || \
+                                         ((MASK) == I2C_OA2_Mask07))
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_timeout
+  * @{
+  */
+
+#define IS_I2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_registers
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR            ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR           ((uint8_t)0x14)
+#define I2C_Register_ISR                ((uint8_t)0x18)
+#define I2C_Register_ICR                ((uint8_t)0x1C)
+#define I2C_Register_PECR               ((uint8_t)0x20)
+#define I2C_Register_RXDR               ((uint8_t)0x24)
+#define I2C_Register_TXDR               ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CR1) || \
+                                         ((REGISTER) == I2C_Register_CR2) || \
+                                         ((REGISTER) == I2C_Register_OAR1) || \
+                                         ((REGISTER) == I2C_Register_OAR2) || \
+                                         ((REGISTER) == I2C_Register_TIMINGR) || \
+                                         ((REGISTER) == I2C_Register_TIMEOUTR) || \
+                                         ((REGISTER) == I2C_Register_ISR) || \
+                                         ((REGISTER) == I2C_Register_ICR) || \
+                                         ((REGISTER) == I2C_Register_PECR) || \
+                                         ((REGISTER) == I2C_Register_RXDR) || \
+                                         ((REGISTER) == I2C_Register_TXDR))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition
+  * @{
+  */
+
+#define  I2C_FLAG_TXE                   I2C_ISR_TXE
+#define  I2C_FLAG_TXIS                  I2C_ISR_TXIS
+#define  I2C_FLAG_RXNE                  I2C_ISR_RXNE
+#define  I2C_FLAG_ADDR                  I2C_ISR_ADDR
+#define  I2C_FLAG_NACKF                 I2C_ISR_NACKF
+#define  I2C_FLAG_STOPF                 I2C_ISR_STOPF
+#define  I2C_FLAG_TC                    I2C_ISR_TC
+#define  I2C_FLAG_TCR                   I2C_ISR_TCR
+#define  I2C_FLAG_BERR                  I2C_ISR_BERR
+#define  I2C_FLAG_ARLO                  I2C_ISR_ARLO
+#define  I2C_FLAG_OVR                   I2C_ISR_OVR
+#define  I2C_FLAG_PECERR                I2C_ISR_PECERR
+#define  I2C_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
+#define  I2C_FLAG_ALERT                 I2C_ISR_ALERT
+#define  I2C_FLAG_BUSY                  I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+                                         ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+                                         ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+                                         ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+                                         ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+                                         ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+                                         ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+                                         ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define  I2C_IT_TXIS                    I2C_ISR_TXIS
+#define  I2C_IT_RXNE                    I2C_ISR_RXNE
+#define  I2C_IT_ADDR                    I2C_ISR_ADDR
+#define  I2C_IT_NACKF                   I2C_ISR_NACKF
+#define  I2C_IT_STOPF                   I2C_ISR_STOPF
+#define  I2C_IT_TC                      I2C_ISR_TC
+#define  I2C_IT_TCR                     I2C_ISR_TCR
+#define  I2C_IT_BERR                    I2C_ISR_BERR
+#define  I2C_IT_ARLO                    I2C_ISR_ARLO
+#define  I2C_IT_OVR                     I2C_ISR_OVR
+#define  I2C_IT_PECERR                  I2C_ISR_PECERR
+#define  I2C_IT_TIMEOUT                 I2C_ISR_TIMEOUT
+#define  I2C_IT_ALERT                   I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+
+#define IS_I2C_GET_IT(IT)               (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+                                         ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+                                         ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+                                         ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+                                         ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+                                         ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+                                         ((IT) == I2C_IT_ALERT))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ReloadEndMode_definition
+  * @{
+  */
+
+#define  I2C_Reload_Mode                I2C_CR2_RELOAD
+#define  I2C_AutoEnd_Mode               I2C_CR2_AUTOEND
+#define  I2C_SoftEnd_Mode               ((uint32_t)0x00000000)
+
+
+#define IS_RELOAD_END_MODE(MODE)        (((MODE) == I2C_Reload_Mode) || \
+                                         ((MODE) == I2C_AutoEnd_Mode) || \
+                                         ((MODE) == I2C_SoftEnd_Mode))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_StartStopMode_definition
+  * @{
+  */
+
+#define  I2C_No_StartStop                 ((uint32_t)0x00000000)
+#define  I2C_Generate_Stop                I2C_CR2_STOP
+#define  I2C_Generate_Start_Read          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_Generate_Start_Write         I2C_CR2_START
+
+
+#define IS_START_STOP_MODE(MODE)        (((MODE) == I2C_Generate_Stop) || \
+                                         ((MODE) == I2C_Generate_Start_Read) || \
+                                         ((MODE) == I2C_Generate_Start_Write) || \
+                                         ((MODE) == I2C_No_StartStop))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/*  SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_I2C_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_iwdg.h

@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_iwdg.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the IWDG
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F030X8_IWDG_H
+#define __FT32F030X8_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               IWDG_SR_PVU
+#define IWDG_FLAG_RVU               IWDG_SR_RVU
+#define IWDG_FLAG_WVU               IWDG_SR_WVU
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)  || \
+                            ((FLAG) == IWDG_FLAG_WVU))
+
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_misc.h

@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_misc.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the miscellaneous
+  *                     firmware library functions (add-on to CMSIS functions).
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_MISC_H
+#define __FT32F0XX_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  NVIC Init Structure definition
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;             /*!< Specifies the IRQ channel to be enabled or disabled.
+                                            This parameter can be a value of @ref IRQn_Type
+                                            (For the complete FT32 Devices IRQ Channels list,
+                                            please refer to ft32f0xx.h file) */
+
+  uint8_t NVIC_IRQChannelPriority;     /*!< Specifies the priority level for the IRQ channel specified
+                                            in NVIC_IRQChannel. This parameter can be a value
+                                            between 0 and 3.  */
+
+  FunctionalState NVIC_IRQChannelCmd;  /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                            will be enabled or disabled.
+                                            This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+  *
+@verbatim
+
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_System_Low_Power
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group
+  * @{
+  */
+#define IS_NVIC_PRIORITY(PRIORITY)  ((PRIORITY) < 0x04)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_opa.h

@@ -0,0 +1,232 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_opa.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the OPA firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_OPA_H
+#define __FT32F0XX_OPA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+
+/** @addtogroup OPA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  OPA Init structure definition
+  */
+
+typedef struct
+{
+
+  uint32_t OPA_OP0PSel;     /*!< Select the positive input of the OPA.
+                                          This parameter can be a value of @ref OPA_OP0PSel */
+
+  uint32_t OPA_OP0NSel;             /*!< Select the negative input of the OPA.
+                                          This parameter can be a value of @ref OPA_OP0NSel */
+
+  uint32_t OPA_OP0FR;          /*!< Selects The feedback resister of the OPA.
+                                          This parameter can be a value of @ref OPA_OP0FR */
+
+  uint32_t OPA_OP0FCAPE;   /*!< Selects The compensate cap of the OPA.
+                                          This parameter can be a value of @ref OPA_OP0FCAPE */
+
+ uint32_t OPA_OPTODIG;  /*!< Selects The output to REG of the OPA.
+                                          This parameter can be a value of @ref OPA_OPTODIG */
+
+ uint32_t OPA_OPTOIO;   /*!< Selects The output to PA0 of the OPA.
+                                          This parameter can be a value of @ref OPA_OPTOIO */
+
+}OPA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/**
+  * @}
+  */
+/** @defgroup OPA_Exported_Constants
+  * @{
+  */
+#define IS_OPA_ALL_PERIPH(PERIPH) (((PERIPH) == OPA) || ((PERIPH) == OPA2))
+
+/** @defgroup OPA_OP0PSel
+  * @{
+  */
+
+#define OPA_VIP_SEL_PA1         ((uint32_t)0x00000000)
+#define OPA_VIP_SEL_GND         ((uint32_t)0x00008000)
+
+#define OPA1_VIP_SEL_PA1        OPA_VIP_SEL_PA1
+#define OPA1_VIP_SEL_GND        OPA_VIP_SEL_GND
+
+#define OPA2_VIP_SEL_PA3        ((uint32_t)0x00000000)
+#define OPA2_VIP_SEL_PA4        ((uint32_t)0x00020000)
+#define OPA2_VIP_SEL_GND        ((uint32_t)0x00008000)
+
+#define IS_OPA_VIP_SEL(INPUT)   (  ((INPUT) == OPA_VIP_SEL_PA1)     || \
+                                    ((INPUT) == OPA2_VIP_SEL_PA4)   || \
+                                    ((INPUT) == OPA_VIP_SEL_GND) )
+
+/**
+  * @}
+  */
+
+/** @defgroup OPA_OP0NSel
+  * @{
+  */
+#define OPA_VIN_SEL_GND         ((uint32_t)0x00000000)
+#define OPA_VIN_SEL_PA2         ((uint32_t)0x00002000)
+#define OPA_VIN_SEL_R4K_PA2     ((uint32_t)0x00004000)
+#define OPA_VIN_SEL_R4K_GND     ((uint32_t)0x00006000)
+
+#define OPA2_VIN_SEL_GND            ((uint32_t)0x00000000)
+#define OPA2_VIN_SEL_PF4            ((uint32_t)0x00002000)
+#define OPA2_VIN_SEL_R4K_PF4        ((uint32_t)0x00004000)
+#define OPA2_VIN_SEL_R4K_GND        ((uint32_t)0x00006000)
+
+#define IS_OPA_VIN_SEL(INPUT)   ( ((INPUT) == OPA_VIN_SEL_GND)      || \
+                                  ((INPUT) == OPA_VIN_SEL_PA2)      || \
+                                  ((INPUT) == OPA_VIN_SEL_R4K_PA2)  || \
+                                  ((INPUT) == OPA_VIN_SEL_R4K_GND) )
+
+/**
+  * @}
+  */
+
+/** @defgroup OPA_OP0FR
+  * @{
+  */
+
+#define OPA_FR_SEL_NORES        ((uint32_t)0x00000000)
+#define OPA_FR_SEL_40K          ((uint32_t)0x00001000)
+#define OPA_FR_SEL_80K          ((uint32_t)0x00001400)
+#define OPA_FR_SEL_160K         ((uint32_t)0x00001800)
+#define OPA_FR_SEL_320K         ((uint32_t)0x00001C00)
+
+#define OPA2_FR_SEL_NORES       ((uint32_t)0x00000000)
+#define OPA2_FR_SEL_40K         ((uint32_t)0x00001000)
+#define OPA2_FR_SEL_80K         ((uint32_t)0x00001400)
+#define OPA2_FR_SEL_160K        ((uint32_t)0x00001800)
+#define OPA2_FR_SEL_320K        ((uint32_t)0x00001C00)
+
+#define IS_OPA_FR_SEL(INPUT)    (   ((INPUT) == OPA_FR_SEL_NORES)   || \
+                                        ((INPUT) == OPA_FR_SEL_40K)     || \
+                                        ((INPUT) == OPA_FR_SEL_80K)     || \
+                                        ((INPUT) == OPA_FR_SEL_160K)    || \
+                                        ((INPUT) == OPA_FR_SEL_320K)    )
+
+/**
+  * @}
+  */
+
+/** @defgroup OPA_OP0FCAPE
+  * @{
+  */
+
+#define OPA_FCAP_SEL_EN             ((uint32_t)0x00000000)
+#define OPA_FCAP_SEL_DIS            ((uint32_t)0x00000200)
+
+#define OPA2_FCAP_SEL_EN            ((uint32_t)0x00000000)
+#define OPA2_FCAP_SEL_DIS           ((uint32_t)0x00000200)
+
+#define IS_OPA_FCAP_SEL(INPUT)  (((INPUT) == OPA_FCAP_SEL_EN) || \
+                                             ((INPUT) == OPA_FCAP_SEL_DIS))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup OPA_OPTODIG
+  * @{
+  */
+
+#define OPA_ODIG_SEL_DIS            ((uint32_t)0x00000000)
+#define OPA_ODIG_SEL_EN             ((uint32_t)0x00000080)
+
+#define OPA2_ODIG_SEL_DIS           ((uint32_t)0x00000000)
+#define OPA2_ODIG_SEL_EN            ((uint32_t)0x00000080)
+
+#define IS_OPA_ODIG_SEL(INPUT)      (((INPUT) == OPA_ODIG_SEL_DIS) || \
+                                             ((INPUT) == OPA_ODIG_SEL_EN))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup OPA_OPTOIO
+  * @{
+  */
+
+#define OPA_OIO_SEL_DIS         ((uint32_t)0x00000000)
+#define OPA_OIO_SEL_EN          ((uint32_t)0x00000040)
+
+#define OPA2_OIO_SEL_DIS        ((uint32_t)0x00000000)
+#define OPA2_OIO_SEL_EN         ((uint32_t)0x00000040)
+
+#define IS_OPA_OIO_SEL(INPUT)               (((INPUT) == OPA_OIO_SEL_DIS) || \
+                                             ((INPUT) == OPA_OIO_SEL_EN))
+
+
+#define OPA_OutputLevel_High                   ((uint32_t)0x00010000)
+#define OPA_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+
+#define IS_OPA_OUTPUT_LEVEL(LEVEL)          (   ((LEVEL) == OPA_OutputLevel_High) || \
+                                                ((LEVEL) == OPA_OutputLevel_Low))
+
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the OPA configuration to the default reset state ****/
+void OPA_DeInit(OPA_TypeDef* OPAx);
+
+/* Initialization and Configuration functions *********************************/
+void OPA_Init(OPA_TypeDef* OPAx, OPA_InitTypeDef* OPA_InitStruct);
+void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
+void OPA_Cmd(OPA_TypeDef* OPAx, FunctionalState NewState);
+uint32_t OPA_GetOutputLevel(OPA_TypeDef* OPAx, uint32_t OPA_OutLevel);
+uint8_t OPA_Cali(OPA_TypeDef* OPAx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_OPA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_pwr.h

@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_pwr.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the PWR firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_PWR_H
+#define __FT32F0XX_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level
+  * @brief
+  * @{
+  */
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
+#define PWR_PVDLevel_8                  PWR_CR_PLS_LEV8
+#define PWR_PVDLevel_9                  PWR_CR_PLS_LEV9
+#define PWR_PVDLevel_10                 PWR_CR_PLS_LEV10
+#define PWR_PVDLevel_11                 PWR_CR_PLS_LEV11
+#define PWR_PVDLevel_12                 PWR_CR_PLS_LEV12
+#define PWR_PVDLevel_13                 PWR_CR_PLS_LEV13
+#define PWR_PVDLevel_14                 PWR_CR_PLS_LEV14
+#define PWR_PVDLevel_15                 PWR_CR_PLS_LEV15
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)|| \
+                                 ((LEVEL) == PWR_PVDLevel_8) || ((LEVEL) == PWR_PVDLevel_9)|| \
+                                 ((LEVEL) == PWR_PVDLevel_10) || ((LEVEL) == PWR_PVDLevel_11)|| \
+                                 ((LEVEL) == PWR_PVDLevel_12) || ((LEVEL) == PWR_PVDLevel_13)|| \
+                                 ((LEVEL) == PWR_PVDLevel_14) || ((LEVEL) == PWR_PVDLevel_15))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_WakeUp_Pins
+  * @{
+  */
+
+#define PWR_WakeUpPin_1                 PWR_CSR_EWUP1
+#define PWR_WakeUpPin_2                 PWR_CSR_EWUP2
+#define PWR_WakeUpPin_3                 PWR_CSR_EWUP3
+#define PWR_WakeUpPin_4                 PWR_CSR_EWUP4
+#define PWR_WakeUpPin_5                 PWR_CSR_EWUP5
+#define PWR_WakeUpPin_6                 PWR_CSR_EWUP6
+#define PWR_WakeUpPin_7                 PWR_CSR_EWUP7
+#define PWR_WakeUpPin_8                 PWR_CSR_EWUP8
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
+                                ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
+                                ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
+                                ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define PWR_STOPEntry_SLEEPONEXIT       ((uint8_t)0x03)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
+                                  ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rcc.h

@@ -0,0 +1,597 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_rcc.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the RCC
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_RCC_H
+#define __FT32F0XX_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK_Frequency;
+  uint32_t ADCCLK_Frequency;
+  uint32_t CECCLK_Frequency;
+  uint32_t I2C1CLK_Frequency;
+  uint32_t USART1CLK_Frequency;
+  uint32_t USART2CLK_Frequency;
+  uint32_t USART3CLK_Frequency;
+  uint32_t USBCLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RCC_HSE_configuration
+  * @{
+  */
+
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source
+  * @{
+  */
+
+#define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
+#define RCC_PLLSource_HSE                RCC_CFGR_PLLSRC_HSE_PREDIV
+#define RCC_PLLSource_HSI48              RCC_CFGR_PLLSRC_HSI48_PREDIV
+#define RCC_PLLSource_HSI                RCC_CFGR_PLLSRC_HSI_PREDIV
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_HSI48)    || \
+                                   ((SOURCE) == RCC_PLLSource_HSI)      || \
+                                   ((SOURCE) == RCC_PLLSource_HSE)      || \
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Multiplication_Factor
+  * @{
+  */
+
+#define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                             ((MUL) == RCC_PLLMul_16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PREDIV1_division_factor
+  * @{
+  */
+#define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source
+  * @{
+  */
+
+#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSource_HSI48           RCC_CFGR_SW_HSI48
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSI48) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB_Clock_Source
+  * @{
+  */
+
+#define RCC_HCLK_Div1                    RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_Div2                    RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_Div4                    RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_Div8                    RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_Div16                   RCC_CFGR_PPRE_DIV16
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_ADC_clock_source
+  * @{
+  */
+/* These defines are obsolete and kept for legacy purpose only.
+Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
+#define RCC_ADCCLK_HSI14                 ((uint32_t)0x00000000)
+#define RCC_ADCCLK_PCLK_Div2             ((uint32_t)0x01000000)
+#define RCC_ADCCLK_PCLK_Div4             ((uint32_t)0x01004000)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
+                               ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_I2C_clock_source
+  * @{
+  */
+
+#define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_USB_clock_source
+  * @brief
+  * @{
+  */
+
+#define RCC_USBCLK_HSI48                 ((uint32_t)0x00000000)
+#define RCC_USBCLK_PLLCLK                RCC_CFGR3_USBSW
+
+#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_USART_clock_source
+  * @{
+  */
+
+#define RCC_USART1CLK_PCLK                  ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK                ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE                   ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI                   ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK                  ((uint32_t)0x20000000)
+#define RCC_USART2CLK_SYSCLK                ((uint32_t)0x20010000)
+#define RCC_USART2CLK_LSE                   ((uint32_t)0x20020000)
+#define RCC_USART2CLK_HSI                   ((uint32_t)0x20030000)
+
+#define RCC_USART3CLK_PCLK                  ((uint32_t)0x30000000)
+#define RCC_USART3CLK_SYSCLK                ((uint32_t)0x30040000)
+#define RCC_USART3CLK_LSE                   ((uint32_t)0x30080000)
+#define RCC_USART3CLK_HSI                   ((uint32_t)0x300C0000)
+
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART1CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART1CLK_HSI)    || \
+                                   ((USARTCLK) == RCC_USART2CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART2CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART2CLK_HSI)|| \
+                                   ((USARTCLK) == RCC_USART3CLK_PCLK)   || \
+                                   ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART3CLK_LSE)    || \
+                                   ((USARTCLK) == RCC_USART3CLK_HSI))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt_Source
+  * @{
+  */
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_HSI14RDY                  ((uint8_t)0x20)
+#define RCC_IT_HSI48RDY                  ((uint8_t)0x40)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
+                           ((IT) == RCC_IT_CSS)    || ((IT) == RCC_IT_HSI48RDY))
+
+#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Configuration
+  * @{
+  */
+
+#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_LSE_ON                       RCC_BDCR_LSEON
+#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+
+#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Drive_Configuration
+  * @{
+  */
+
+#define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+                                 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Peripherals
+  * @{
+  */
+
+#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
+#define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
+#define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripherals
+  * @{
+  */
+
+#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_USART6            RCC_APB2ENR_USART6EN
+#define RCC_APB2Periph_USART7            RCC_APB2ENR_USART7EN
+#define RCC_APB2Periph_USART8            RCC_APB2ENR_USART8EN
+#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
+#define RCC_APB2Periph_TIM1              RCC_APB2ENR_TIM1EN
+#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_DBGMCU            RCC_APB2ENR_DBGMCUEN
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Peripherals
+  * @{
+  */
+
+#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
+#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
+#define RCC_APB1Periph_TIM14             RCC_APB1ENR_TIM14EN
+#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
+#define RCC_APB1Periph_USART4            RCC_APB1ENR_USART4EN
+#define RCC_APB1Periph_USART5            RCC_APB1ENR_USART5EN
+#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
+#define RCC_APB1Periph_CAN               RCC_APB1ENR_CANEN
+#define RCC_APB1Periph_CRS               RCC_APB1ENR_CRSEN
+#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN
+#define RCC_APB1Periph_CEC               RCC_APB1ENR_CECEN
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Clock_Source
+  * @{
+  */
+
+#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
+#define RCC_MCOSource_HSI14              ((uint8_t)0x01)
+#define RCC_MCOSource_LSI                ((uint8_t)0x02)
+#define RCC_MCOSource_LSE                ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
+#define RCC_MCOSource_HSI                ((uint8_t)0x05)
+#define RCC_MCOSource_HSE                ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
+#define RCC_MCOSource_HSI48              ((uint8_t)0x08)
+#define RCC_MCOSource_PLLCLK             ((uint8_t)0x87)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14)      || \
+                                   ((SOURCE) == RCC_MCOSource_SYSCLK)  || ((SOURCE) == RCC_MCOSource_HSI)        || \
+                                   ((SOURCE) == RCC_MCOSource_HSE)     || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
+                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_HSI48)      || \
+                                   ((SOURCE) == RCC_MCOSource_PLLCLK)  || ((SOURCE) == RCC_MCOSource_LSE))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOPrescaler
+  * @{
+  */
+#if !defined (FT32F051)
+#define RCC_MCOPrescaler_1            RCC_CFGR_MCO_PRE_1
+#define RCC_MCOPrescaler_2            RCC_CFGR_MCO_PRE_2
+#define RCC_MCOPrescaler_4            RCC_CFGR_MCO_PRE_4
+#define RCC_MCOPrescaler_8            RCC_CFGR_MCO_PRE_8
+#define RCC_MCOPrescaler_16           RCC_CFGR_MCO_PRE_16
+#define RCC_MCOPrescaler_32           RCC_CFGR_MCO_PRE_32
+#define RCC_MCOPrescaler_64           RCC_CFGR_MCO_PRE_64
+#define RCC_MCOPrescaler_128          RCC_CFGR_MCO_PRE_128
+
+#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_8)  || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_16) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_32) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_64) || \
+                                         ((PRESCALER) == RCC_MCOPrescaler_128))
+#endif /* FT32F051 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag
+  * @{
+  */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
+#define RCC_FLAG_V18PWRRSTF              ((uint8_t)0x57)
+#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
+#define RCC_FLAG_HSI14RDY                ((uint8_t)0x61)
+#define RCC_FLAG_HSI48RDY                ((uint8_t)0x71)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)  || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)  || ((FLAG) == RCC_FLAG_OBLRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)  || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)  || ((FLAG) == RCC_FLAG_IWDGRST) || \
+                           ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
+                           ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \
+                           ((FLAG) == RCC_FLAG_V18PWRRSTF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
+void RCC_HSI14Cmd(FunctionalState NewState);
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_HSI48Cmd(FunctionalState NewState);
+uint32_t RCC_GetHSI48CalibrationValue(void);
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+#ifdef FT32F051
+void RCC_MCOConfig(uint8_t RCC_MCOSource);
+#else
+void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
+#endif /* FT32F051 */
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLKConfig(uint32_t RCC_HCLK);
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
+                                               For proper ADC clock selection, refer to
+                                               ADC_ClockModeConfig() in the ADC driver */
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_RCC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rtc.h

@@ -0,0 +1,747 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_rtc.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the RTC firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_RTC_H
+#define __FT32F0XX_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  RTC Init structures definition
+  */
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x1FFF */
+}RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month.
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     This parameter must be set to a value in the 1-31 range
+                                     if the Alarm Date is selected.
+                                     This parameter can be a value of @ref RTC_WeekDay_Definitions
+                                     if the Alarm WeekDay is selected. */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+
+/** @defgroup RTC_Hour_Formats
+  * @{
+  */
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Asynchronous_Predivider
+  * @{
+  */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+  * @{
+  */
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Time_Definitions
+  * @{
+  */
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AM_PM_Definitions
+  * @{
+  */
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Year_Date_Definitions
+  * @{
+  */
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Month_Date_Definitions
+  * @{
+  */
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_WeekDay_Definitions
+  * @{
+  */
+
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
+#define RTC_Weekday_Saturday           ((uint8_t)0x6)
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+  * @{
+  */
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+  * @{
+  */
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarms_Definitions
+  * @{
+  */
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define IS_RTC_ALARM(ALARM)      ((ALARM) == RTC_Alarm_A)
+#define IS_RTC_CMD_ALARM(ALARM)  (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
+  * @{
+  */
+#define RTC_AlarmSubSecondMask_All         ((uint8_t)0x00) /*!< All Alarm SS fields are masked.
+                                                                There is no comparison on sub seconds
+                                                                for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm
+                                                                comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm
+                                                                comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm
+                                                                comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm
+                                                                comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm
+                                                                comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm
+                                                                comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm
+                                                                comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm
+                                                                comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm
+                                                                comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm
+                                                                comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm
+                                                                comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm
+                                                                comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm
+                                                                comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm
+                                                                comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match
+                                                                to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions
+  * @{
+  */
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_selection_Definitions
+  * @{
+  */
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA)  || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+  * @{
+  */
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Calib_Output_selection_Definitions
+  * @{
+  */
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000)
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Smooth_calib_period_Definitions
+  * @{
+  */
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
+  * @{
+  */
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added
+                                                                during a X -second window = Y - CALM[8:0].
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
+  * @{
+  */
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+  * @{
+  */
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
+                                        ((SAVING) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Trigger_Definitions
+  * @{
+  */
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+  * @{
+  */
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+  * @{
+  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192  ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096  ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048  ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024  ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                      with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+  * @{
+  */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+  * @{
+  */
+#define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
+                                                 input tamper 1 */
+#define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
+                                                 input tamper 2 */
+#define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
+                                                 input tamper 3*/
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+  * @{
+  */
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+  * @{
+  */
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions
+  * @{
+  */
+#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
+#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
+#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
+#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
+#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
+#define RTC_FLAG_TSF                      RTC_ISR_TSF
+#define RTC_FLAG_WUTF                     RTC_ISR_WUTF
+#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
+#define RTC_FLAG_INITF                    RTC_ISR_INITF
+#define RTC_FLAG_RSF                      RTC_ISR_RSF
+#define RTC_FLAG_INITS                    RTC_ISR_INITS
+#define RTC_FLAG_SHPF                     RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
+#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
+
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF)  || ((FLAG) == RTC_FLAG_TSF)     || \
+                               ((FLAG) == RTC_FLAG_WUTF)   || ((FLAG) == RTC_FLAG_ALRAWF)  || \
+                               ((FLAG) == RTC_FLAG_ALRAF)  || ((FLAG) == RTC_FLAG_INITF)   || \
+                               ((FLAG) == RTC_FLAG_RSF)    || ((FLAG) == RTC_FLAG_WUTWF)   || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F)  || \
+                               ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                               ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Interrupts_Definitions
+  * @{
+  */
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_ALRA)  || \
+                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT)   || \
+                           ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3))
+
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A) configuration functions  **********************************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions ********************************/
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_RTC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_spi.h

@@ -0,0 +1,540 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_spi.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the SPI
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_SPI_H
+#define __FT32F0XX_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  SPI Init structure definition
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2))
+
+#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
+
+/** @defgroup SPI_data_direction
+  * @{
+  */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_DataSize_4b                 ((uint16_t)0x0300)
+#define SPI_DataSize_5b                 ((uint16_t)0x0400)
+#define SPI_DataSize_6b                 ((uint16_t)0x0500)
+#define SPI_DataSize_7b                 ((uint16_t)0x0600)
+#define SPI_DataSize_8b                 ((uint16_t)0x0700)
+#define SPI_DataSize_9b                 ((uint16_t)0x0800)
+#define SPI_DataSize_10b                ((uint16_t)0x0900)
+#define SPI_DataSize_11b                ((uint16_t)0x0A00)
+#define SPI_DataSize_12b                ((uint16_t)0x0B00)
+#define SPI_DataSize_13b                ((uint16_t)0x0C00)
+#define SPI_DataSize_14b                ((uint16_t)0x0D00)
+#define SPI_DataSize_15b                ((uint16_t)0x0E00)
+#define SPI_DataSize_16b                ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+                                 ((SIZE) == SPI_DataSize_5b) || \
+                                 ((SIZE) == SPI_DataSize_6b) || \
+                                 ((SIZE) == SPI_DataSize_7b) || \
+                                 ((SIZE) == SPI_DataSize_8b) || \
+                                 ((SIZE) == SPI_DataSize_9b) || \
+                                 ((SIZE) == SPI_DataSize_10b) || \
+                                 ((SIZE) == SPI_DataSize_11b) || \
+                                 ((SIZE) == SPI_DataSize_12b) || \
+                                 ((SIZE) == SPI_DataSize_13b) || \
+                                 ((SIZE) == SPI_DataSize_14b) || \
+                                 ((SIZE) == SPI_DataSize_15b) || \
+                                 ((SIZE) == SPI_DataSize_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length
+  * @{
+  */
+
+#define SPI_CRCLength_8b                ((uint16_t)0x0000)
+#define SPI_CRCLength_16b               SPI_CR1_CRCL
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+                                   ((LENGTH) == SPI_CRCLength_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   SPI_CR1_CPOL
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  SPI_CR1_CPHA
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management
+  * @{
+  */
+
+#define SPI_NSS_Soft                    SPI_CR1_SSM
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Mode
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Standard
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Data_Format
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           SPI_I2SPR_MCKOE
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Clock_Polarity
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   SPI_I2SCFGR_CKPOL
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold
+  * @{
+  */
+
+#define SPI_RxFIFOThreshold_HF          ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF          SPI_CR2_FRXTH
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+                                             ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               SPI_CR2_TXDMAEN
+#define SPI_I2S_DMAReq_Rx               SPI_CR2_RXDMAEN
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_last_DMA_transfers
+  * @{
+  */
+
+#define SPI_LastDMATransfer_TxEvenRxEven   ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven    ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd    ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd     ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+  * @}
+  */
+/** @defgroup SPI_NSS_internal_software_management
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         SPI_CR1_SSI
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_transmission_fifo_status_level
+  * @{
+  */
+
+#define SPI_TransmissionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull    ((uint16_t)0x0800)
+#define SPI_TransmissionFIFOStatus_HalfFull        ((uint16_t)0x1000)
+#define SPI_TransmissionFIFOStatus_Full            ((uint16_t)0x1800)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_reception_fifo_status_level
+  * @{
+  */
+#define SPI_ReceptionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull    ((uint16_t)0x0200)
+#define SPI_ReceptionFIFOStatus_HalfFull        ((uint16_t)0x0400)
+#define SPI_ReceptionFIFOStatus_Full            ((uint16_t)0x0600)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_I2S_flags_definition
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               SPI_SR_RXNE
+#define SPI_I2S_FLAG_TXE                SPI_SR_TXE
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
+#define SPI_FLAG_MODF                   SPI_SR_MODF
+#define SPI_I2S_FLAG_OVR                SPI_SR_OVR
+#define SPI_I2S_FLAG_BSY                SPI_SR_BSY
+#define SPI_I2S_FLAG_FRE                SPI_SR_FRE
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+                                   ((FLAG) == I2S_FLAG_UDR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_syscfg.h

@@ -0,0 +1,276 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_syscfg.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the SYSCFG firmware
+  *                     library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/*!< Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_SYSCFG_H
+#define __FT32F0XX_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup SYSCFG
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_EXTI_Port_Sources
+  * @{
+  */
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources
+  * @{
+  */
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Memory_Remap_Config
+  * @{
+  */
+#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DMA_Remap_Config
+  * @{
+  */
+#define SYSCFG_DMARemap_TIM3        SYSCFG_CFGR1_TIM3_DMA_RMP      /* Remap TIM3 DMA requests from channel4 to channel6*/
+#define SYSCFG_DMARemap_TIM2        SYSCFG_CFGR1_TIM2_DMA_RMP      /* Remap TIM2 DMA requests from channel3/4 to channel7*/
+#define SYSCFG_DMARemap_TIM1        SYSCFG_CFGR1_TIM1_DMA_RMP      /* Remap TIM1 DMA requests from channel2/3/4 to channel6*/
+#define SYSCFG_DMARemap_I2C1        SYSCFG_CFGR1_I2C1_DMA_RMP      /* Remap I2C1 DMA requests from channel3/2 to channel7/6*/
+#define SYSCFG_DMARemap_USART3      SYSCFG_CFGR1_USART3_DMA_RMP    /* Remap USART3 DMA requests from channel6/7 to channel3/2*/
+#define SYSCFG_DMARemap_USART2      SYSCFG_CFGR1_USART2_DMA_RMP    /* Remap USART2 DMA requests from channel4/5 to channel6/7*/
+#define SYSCFG_DMARemap_SPI2        SYSCFG_CFGR1_SPI2_DMA_RMP      /* Remap SPI2 DMA requests from channel4/5 to channel6/7*/
+#define SYSCFG_DMARemap_TIM17_2     SYSCFG_CFGR1_TIM17_DMA_RMP2    /* Remap TIM17 DMA requests from channel1/2 to channel7*/
+#define SYSCFG_DMARemap_TIM16_2     SYSCFG_CFGR1_TIM16_DMA_RMP2    /* Remap TIM16 DMA requests from channel3/4 to channel6*/
+#define SYSCFG_DMARemap_TIM17       SYSCFG_CFGR1_TIM17_DMA_RMP     /* Remap TIM17 DMA requests from channel1 to channel2*/
+#define SYSCFG_DMARemap_TIM16       SYSCFG_CFGR1_TIM16_DMA_RMP     /* Remap TIM16 DMA requests from channel3 to channel4*/
+#define SYSCFG_DMARemap_USART1Rx    SYSCFG_CFGR1_USART1RX_DMA_RMP  /* Remap USART1 Rx DMA requests from channel3 to channel5*/
+#define SYSCFG_DMARemap_USART1Tx    SYSCFG_CFGR1_USART1TX_DMA_RMP  /* Remap USART1 Tx DMA requests from channel2 to channel4*/
+#define SYSCFG_DMARemap_ADC1        SYSCFG_CFGR1_ADC_DMA_RMP       /* Remap ADC1 DMA requests from channel1 to channel2*/
+
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM16) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
+                                    ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
+                                    ((REMAP) == SYSCFG_DMARemap_ADC1))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config
+  * @{
+  */
+#define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1      SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7*/
+#define SYSCFG_I2CFastModePlus_I2C2      SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins*/
+#define SYSCFG_I2CFastModePlus_PA9       SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9*/
+#define SYSCFG_I2CFastModePlus_PA10      SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10*/
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB7)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB8)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PA9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PA10))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Lock_Config
+  * @{
+  */
+#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK       /*!< Connects the PVD event to the Break Input of TIM1 */
+#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
+                                       ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_ISR_WRAPPER
+  * @{
+  */
+#define SYSCFG_ITLINE0                           ((uint32_t) 0x00000000)
+#define SYSCFG_ITLINE1                           ((uint32_t) 0x00000001)
+#define SYSCFG_ITLINE2                           ((uint32_t) 0x00000002)
+#define SYSCFG_ITLINE3                           ((uint32_t) 0x00000003)
+#define SYSCFG_ITLINE4                           ((uint32_t) 0x00000004)
+#define SYSCFG_ITLINE5                           ((uint32_t) 0x00000005)
+#define SYSCFG_ITLINE6                           ((uint32_t) 0x00000006)
+#define SYSCFG_ITLINE7                           ((uint32_t) 0x00000007)
+#define SYSCFG_ITLINE8                           ((uint32_t) 0x00000008)
+#define SYSCFG_ITLINE9                           ((uint32_t) 0x00000009)
+#define SYSCFG_ITLINE10                          ((uint32_t) 0x0000000A)
+#define SYSCFG_ITLINE11                          ((uint32_t) 0x0000000B)
+#define SYSCFG_ITLINE12                          ((uint32_t) 0x0000000C)
+#define SYSCFG_ITLINE13                          ((uint32_t) 0x0000000D)
+#define SYSCFG_ITLINE14                          ((uint32_t) 0x0000000E)
+#define SYSCFG_ITLINE15                          ((uint32_t) 0x0000000F)
+#define SYSCFG_ITLINE16                          ((uint32_t) 0x00000010)
+#define SYSCFG_ITLINE17                          ((uint32_t) 0x00000011)
+#define SYSCFG_ITLINE18                          ((uint32_t) 0x00000012)
+#define SYSCFG_ITLINE19                          ((uint32_t) 0x00000013)
+#define SYSCFG_ITLINE20                          ((uint32_t) 0x00000014)
+#define SYSCFG_ITLINE21                          ((uint32_t) 0x00000015)
+#define SYSCFG_ITLINE22                          ((uint32_t) 0x00000016)
+#define SYSCFG_ITLINE23                          ((uint32_t) 0x00000017)
+#define SYSCFG_ITLINE24                          ((uint32_t) 0x00000018)
+#define SYSCFG_ITLINE25                          ((uint32_t) 0x00000019)
+#define SYSCFG_ITLINE26                          ((uint32_t) 0x0000001A)
+#define SYSCFG_ITLINE27                          ((uint32_t) 0x0000001B)
+#define SYSCFG_ITLINE28                          ((uint32_t) 0x0000001C)
+#define SYSCFG_ITLINE29                          ((uint32_t) 0x0000001D)
+#define SYSCFG_ITLINE30                          ((uint32_t) 0x0000001E)
+#define SYSCFG_ITLINE31                          ((uint32_t) 0x0000001F)
+
+/**
+  * @}
+  */
+/** @defgroup IRDA_ENV_SEL
+  * @{
+  */
+#define SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1)    /* Timer16 is selected as IRDA Modulation envelope source */
+#define SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IRDA_ENV_SEL_0)  /* USART1 is selected as IRDA Modulation envelope source.*/
+#define SYSCFG_IRDA_ENV_SEL_USART2    (SYSCFG_CFGR1_IRDA_ENV_SEL_1)  /* USART2 is selected as IRDA Modulation envelope source.*/
+
+#define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16)      || \
+                                 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1)     || \
+                                 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_SYSCFG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_tim.h

@@ -0,0 +1,1167 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_tim.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the TIM
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_TIM_H
+#define __FT32F0XX_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  TIM Time Base Init structure definition
+  * @note   This sturcture is used with all TIMx.
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF.
+                                       @note This parameter is valid only for TIM1. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Init structure definition
+  */
+
+typedef struct
+{
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                   @note This parameter is valid only for TIM1. */
+
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                   This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
+                                   for TIM2) */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM1. */
+} TIM_OCInitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Init structure definition
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+  * @brief  TIM_BDTR structure definition
+  * @note   This sturcture is used only with TIM1.
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_Lock_level */
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Init structure definition
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup TIM_Exported_constants
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM14)|| \
+                                   ((PERIPH) == TIM15)|| \
+                                   ((PERIPH) == TIM16)|| \
+                                   ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 */
+#define IS_TIM_LIST1_PERIPH(PERIPH)  ((PERIPH) == TIM1)
+
+/* LIST2: TIM 1, 15, 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST3: TIM 1, 2 and 3 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3))
+
+/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM14) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST6: TIM 1, 2, 3 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM15))
+
+/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
+#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM14))
+
+/* LIST8: TIM 1, 2, 3 and 14 */
+#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM14))
+
+/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
+#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM15))
+
+/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
+#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM6) || \
+                                     ((PERIPH) == TIM7) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST1: TIM 11 */
+#define IS_TIM_LIST11_PERIPH(PERIPH)  ((PERIPH) == TIM14)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||    \
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Division_CKD
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+  * @{
+  */
+
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_state
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_state
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Capture_Compare_state
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Capture_Compare_N_state
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Lock_level
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_interrupt_sources
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR) || \
+                               ((BASE) == TIM_DMABase_OR))
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_DMA_Burst_Length
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_External_Trigger_Polarity
+  * @{
+  */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Forced_Action
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_Event_Source
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Source
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Output_Source
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flags
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_External_Trigger_Filter
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OCReferenceClear
+  * @{
+  */
+#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Remap
+  * @{
+  */
+#define TIM14_GPIO                      ((uint16_t)0x0000)
+#define TIM14_RTC_CLK                   ((uint16_t)0x0001)
+#define TIM14_HSEDiv32                  ((uint16_t)0x0002)
+#define TIM14_MCO                       ((uint16_t)0x0003)
+
+#define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM14_GPIO)|| \
+                                  ((TIM_REMAP) == TIM14_RTC_CLK) || \
+                                  ((TIM_REMAP) == TIM14_HSEDiv32) || \
+                                  ((TIM_REMAP) == TIM14_MCO))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Legacy
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Advanced-control timers (TIM1) specific features*******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__FT32F0XX_TIM_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_usart.h

@@ -0,0 +1,539 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_usart.h
+  * @author             FMD AE
+  * @brief              This file contains all the functions prototypes for the USART
+  *                     firmware library.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F0XX_USART_H
+#define __FT32F0XX_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+
+/** @addtogroup USART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+
+
+/**
+  * @brief  USART Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+  uint32_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint32_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint32_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/**
+  * @brief  USART Clock Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t USART_Clock;             /*!< Specifies whether the USART clock is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Clock */
+
+  uint32_t USART_CPOL;              /*!< Specifies the steady state of the serial clock.
+                                         This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint32_t USART_CPHA;              /*!< Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint32_t USART_LastBit;           /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                         data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                         This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+/** @defgroup USART_Word_Length
+  * @{
+  */
+
+#define USART_WordLength_8b                  ((uint32_t)0x00000000)
+#define USART_WordLength_9b                  USART_CR1_M /* should be ((uint32_t)0x00001000) */
+#define USART_WordLength_7b                  ((uint32_t)0x10001000)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b) || \
+                                      ((LENGTH) == USART_WordLength_7b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Stop_Bits
+  * @{
+  */
+
+#define USART_StopBits_1                     ((uint32_t)0x00000000)
+#define USART_StopBits_2                     USART_CR2_STOP_1
+#define USART_StopBits_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity
+  * @{
+  */
+
+#define USART_Parity_No                      ((uint32_t)0x00000000)
+#define USART_Parity_Even                    USART_CR1_PCE
+#define USART_Parity_Odd                     (USART_CR1_PCE | USART_CR1_PS)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode
+  * @{
+  */
+
+#define USART_Mode_Rx                        USART_CR1_RE
+#define USART_Mode_Tx                        USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+                              ((MODE) != (uint32_t)0x00))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Hardware_Flow_Control
+  * @{
+  */
+
+#define USART_HardwareFlowControl_None       ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS        USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS        USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS    (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock
+  * @{
+  */
+
+#define USART_Clock_Disable                  ((uint32_t)0x00000000)
+#define USART_Clock_Enable                   USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity
+  * @{
+  */
+
+#define USART_CPOL_Low                       ((uint32_t)0x00000000)
+#define USART_CPOL_High                      USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge                     USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint32_t)0x00000000)
+#define USART_LastBit_Enable                 USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      USART_CR3_DMAT
+#define USART_DMAReq_Rx                      USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+                                  ((DMAREQ) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Recception_Error
+  * @{
+  */
+
+#define USART_DMAOnError_Enable              ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable             USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+                                       ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark             USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                          ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Address_Detection
+  * @{
+  */
+
+#define USART_AddressLength_4b               ((uint32_t)0x00000000)
+#define USART_AddressLength_7b               USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+                                             ((ADDRESS) == USART_AddressLength_7b))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              USART_CR3_IRLP
+#define USART_IrDAMode_Normal                ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DE_Polarity
+  * @{
+  */
+
+#define USART_DEPolarity_High                ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low                 USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+                                        ((POLARITY) == USART_DEPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Inversion_Pins
+  * @{
+  */
+
+#define USART_InvPin_Tx                      USART_CR2_TXINV
+#define USART_InvPin_Rx                      USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+                                       ((PIN) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_AutoBaudRate_Mode
+  * @{
+  */
+
+#define USART_AutoBaudRate_StartBit          ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge       USART_CR2_ABRMODE_0
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+                                          ((MODE) == USART_AutoBaudRate_FallingEdge))
+/**
+  * @}
+  */
+
+/** @defgroup USART_OVR_DETECTION
+  * @{
+  */
+
+#define USART_OVRDetection_Enable            ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable           USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+                                    ((OVR) == USART_OVRDetection_Disable))
+/**
+  * @}
+  */
+/** @defgroup USART_Request
+  * @{
+  */
+
+#define USART_Request_ABRRQ                  USART_RQR_ABRRQ
+#define USART_Request_SBKRQ                  USART_RQR_SBKRQ
+#define USART_Request_MMRQ                   USART_RQR_MMRQ
+#define USART_Request_RXFRQ                  USART_RQR_RXFRQ
+#define USART_Request_TXFRQ                  USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+                                   ((REQUEST) == USART_Request_RXFRQ) || \
+                                   ((REQUEST) == USART_Request_MMRQ) || \
+                                   ((REQUEST) == USART_Request_SBKRQ) || \
+                                   ((REQUEST) == USART_Request_ABRRQ))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags
+  * @{
+  */
+#define USART_FLAG_REACK                     USART_ISR_REACK
+#define USART_FLAG_TEACK                     USART_ISR_TEACK
+#define USART_FLAG_WU                        USART_ISR_WUF
+#define USART_FLAG_RWU                       USART_ISR_RWU
+#define USART_FLAG_SBK                       USART_ISR_SBKF
+#define USART_FLAG_CM                        USART_ISR_CMF
+#define USART_FLAG_BUSY                      USART_ISR_BUSY
+#define USART_FLAG_ABRF                      USART_ISR_ABRF
+#define USART_FLAG_ABRE                      USART_ISR_ABRE
+#define USART_FLAG_EOB                       USART_ISR_EOBF
+#define USART_FLAG_RTO                       USART_ISR_RTOF
+#define USART_FLAG_nCTSS                     USART_ISR_CTS
+#define USART_FLAG_CTS                       USART_ISR_CTSIF
+#define USART_FLAG_LBD                       USART_ISR_LBD
+#define USART_FLAG_TXE                       USART_ISR_TXE
+#define USART_FLAG_TC                        USART_ISR_TC
+#define USART_FLAG_RXNE                      USART_ISR_RXNE
+#define USART_FLAG_IDLE                      USART_ISR_IDLE
+#define USART_FLAG_ORE                       USART_ISR_ORE
+#define USART_FLAG_NE                        USART_ISR_NE
+#define USART_FLAG_FE                        USART_ISR_FE
+#define USART_FLAG_PE                        USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                             ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+                             ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+                             ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+                             ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+                             ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+                             ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+                                   ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+                                   ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                                   ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+                                   ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+                                   ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition
+  * @brief USART Interrupt definition
+  * USART_IT possible values
+  * Elements values convention: 0xZZZZYYXX
+  *   XX: Position of the corresponding Interrupt
+  *   YY: Register index
+  *   ZZZZ: Flag position
+  * @{
+  */
+
+#define USART_IT_WU                          ((uint32_t)0x00140316)
+#define USART_IT_CM                          ((uint32_t)0x0011010E)
+#define USART_IT_EOB                         ((uint32_t)0x000C011B)
+#define USART_IT_RTO                         ((uint32_t)0x000B011A)
+#define USART_IT_PE                          ((uint32_t)0x00000108)
+#define USART_IT_TXE                         ((uint32_t)0x00070107)
+#define USART_IT_TC                          ((uint32_t)0x00060106)
+#define USART_IT_RXNE                        ((uint32_t)0x00050105)
+#define USART_IT_IDLE                        ((uint32_t)0x00040104)
+#define USART_IT_LBD                         ((uint32_t)0x00080206)
+#define USART_IT_CTS                         ((uint32_t)0x0009030A)
+#define USART_IT_ERR                         ((uint32_t)0x00000300)
+#define USART_IT_ORE                         ((uint32_t)0x00030300)
+#define USART_IT_NE                          ((uint32_t)0x00020300)
+#define USART_IT_FE                          ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+                                ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                                ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+                             ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                             ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+                               ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+                               ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+                               ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                               ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Global_definition
+  * @{
+  */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F0XX_USART_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_wwdg.h

@@ -0,0 +1,91 @@
+/**
+  ******************************************************************************
+  * @file    ft32f030x8_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    2020-06-22
+  * @brief   This file contains all the functions prototypes for the WWDG
+  *          firmware library.
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT32F030X8_WWDG_H
+#define __FT32F030X8_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx.h"
+
+/** @addtogroup FT32F030X8_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Prescaler
+  * @{
+  */
+
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the WWDG configuration to the default reset state ****/
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FT32F030X8_WWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_adc.c

@@ -0,0 +1,1265 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_adc.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Analog to Digital Convertor (ADC) peripheral:
+  *                 + Initialization and Configuration
+  *                 + Power saving
+  *                 + Analog Watchdog configuration
+  *                 + Temperature Sensor, Vrefint (Internal Reference Voltage) and
+  *                   Vbat (Voltage battery) management
+  *                 + ADC Channels Configuration
+  *                 + ADC Channels DMA Configuration
+  *                 + Interrupts and flags management.
+  * @version            V1.0.0
+  * @data                   2021-07-01
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_adc.h"
+#include "ft32f0xx_rcc.h"
+
+
+
+/* ADC CFGR mask */
+#define CFGR1_CLEAR_MASK           ((uint32_t)0xFFFFD203)
+
+/* Calibration time out */
+#define CALIBRATION_TIMEOUT        ((uint32_t)0x0000F000)
+
+/**
+  * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  if(ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @note   This function is used to configure the global features of the ADC (
+  *         Resolution, Data Alignment, continuous mode activation, External
+  *         trigger source and edge, Sequence Scan Direction).
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+  assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection));
+
+  /* Get the ADCx CFGR value */
+  tmpreg = ADCx->CFGR1;
+
+  /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
+  tmpreg &= CFGR1_CLEAR_MASK;
+
+  /*---------------------------- ADCx CFGR Configuration ---------------------*/
+
+  /* Set RES[1:0] bits according to ADC_Resolution value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
+  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set SCANDIR bit according to ADC_ScanDirection value */
+
+  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
+             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
+             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
+
+  /* Write to ADCx CFGR */
+  ADCx->CFGR1 = tmpreg;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @note   This function is used to initialize the global features of the ADC (
+  *         Resolution, Data Alignment, continuous mode activation, External
+  *         trigger source and edge, Sequence Scan Direction).
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Resolution member */
+  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+
+   /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+  /* Initialize the ADC_ExternalTrigConvEdge member */
+  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
+
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+  /* Initialize the ADC_ScanDirection member */
+  ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADEN bit to Enable the ADC peripheral */
+    ADCx->CR |= (uint32_t)ADC_CR_ADEN;
+  }
+  else
+  {
+    /* Set the ADDIS to Disable the ADC peripheral */
+    ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
+  }
+}
+
+/**
+  * @brief  Configure the ADC to either be clocked by the asynchronous clock(which is
+  *         independent, the dedicated 14MHz clock) or the synchronous clock derived from
+  *         the APB clock of the ADC bus interface divided by 2 or 4
+  * @note   This function can be called only when ADC is disabled.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_ClockMode: This parameter can be :
+  *            @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock
+  *            @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2
+  *            @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4
+  * @retval None
+  */
+void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode));
+
+    /* Configure the ADC Clock mode according to ADC_ClockMode */
+    ADCx->CFGR2 = (uint32_t)ADC_ClockMode;
+
+}
+
+/**
+  * @brief  Enables or disables the jitter when the ADC is clocked by PCLK div2
+  *         or div4
+  * @note   This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig()
+  *         function should be used instead.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_JitterOff: This parameter can be :
+  *            @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2
+  *            @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4
+  * @param  NewState: new state of the ADCx jitter.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Disable Jitter */
+    ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
+  }
+  else
+  {
+    /* Enable Jitter */
+    ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables the ADC Power Off.
+  * @note   ADC power-on and power-off can be managed by hardware to cut the
+  *         consumption when the ADC is not converting.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @note   The ADC can be powered down:
+  *         - During the Auto delay phase:  The ADC is powered on again at the end
+  *           of the delay (until the previous data is read from the ADC data register).
+  *         - During the ADC is waiting for a trigger event: The ADC is powered up
+  *           at the next trigger event (when the conversion is started).
+  * @param  NewState: new state of the ADCx power Off.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Automatic Power-Off */
+    ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
+  }
+  else
+  {
+    /* Disable the ADC Automatic Power-Off */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Wait conversion mode.
+  * @note   When the CPU clock is not fast enough to manage the data rate, a
+  *         Hardware delay can be introduced between ADC conversions to reduce
+  *         this data rate.
+  * @note   The Hardware delay is inserted after each conversions and until the
+  *         previous data is read from the ADC data register
+  * @note   This is a way to automatically adapt the speed of the ADC to the speed
+  *         of the system which will read the data.
+  * @note   Any hardware triggers wich occur while a conversion is on going or
+  *         while the automatic Delay is applied are ignored
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx Auto-Delay.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Automatic Delayed conversion */
+    ADCx->CFGR1 |= ADC_CFGR1_WAIT;
+  }
+  else
+  {
+    /* Disable the ADC Automatic Delayed conversion */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the analog watchdog
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx Analog Watchdog.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Analog Watchdog */
+    ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
+  }
+  else
+  {
+    /* Disable the ADC Analog Watchdog */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
+  }
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *          This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *          This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+
+  /* Set the ADCx high and low threshold */
+  ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
+
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected
+  *            @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected
+  *            @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected
+  *            @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected
+  *            @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected
+  *            @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected
+  *            @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected
+  *            @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected
+  *            @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected
+  *            @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected
+  *            @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected
+  *            @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected
+  *            @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected
+  *            @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected
+  *            @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected
+  *            @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected
+  *            @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected
+  *            @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected
+  *            @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected
+  * @note   The channel selected on the AWDCH must be also set into the CHSELR
+  *         register
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CFGR1;
+
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= ~ADC_CFGR1_AWDCH;
+
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_AnalogWatchdog_Channel;
+
+  /* Store the new register value */
+  ADCx->CFGR1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADC Analog Watchdog Single Channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC Analog Watchdog Single Channel */
+    ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
+  }
+  else
+  {
+    /* Disable the ADC Analog Watchdog Single Channel */
+    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the temperature sensor channel.
+  * @param  NewState: new state of the temperature sensor input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
+  }
+  else
+  {
+    /* Disable the temperature sensor channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Vrefint channel.
+  * @param  NewState: new state of the Vref input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Vrefint channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
+  }
+  else
+  {
+    /* Disable the Vrefint channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Vbat channel.
+  * @note   This feature is not applicable for FT32F030 devices.
+  * @param  NewState: new state of the Vbat input channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VbatCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Vbat channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
+  }
+  else
+  {
+    /* Disable the Vbat channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures for the selected ADC and its sampling time.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure.
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected,
+  *            @arg ADC_Channel_11: ADC Channel11 selected,
+  *            @arg ADC_Channel_12: ADC Channel12 selected,
+  *            @arg ADC_Channel_13: ADC Channel13 selected,
+  *            @arg ADC_Channel_14: ADC Channel14 selected,
+  *            @arg ADC_Channel_15: ADC Channel15 selected,
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  *            @arg ADC_Channel_18: ADC Channel18 selected,
+  *            @arg ADC_Channel_19: ADC Channel19 selected,
+  *            @arg ADC_Channel_20: ADC Channel20 selected,
+  *            @arg ADC_Channel_21: ADC Channel21 selected,
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles
+  *            @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles
+  *            @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles
+  *            @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles
+  *            @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles
+  *            @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles
+  *            @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
+  *            @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
+  * @retval None
+  */
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* Configure the ADC Channel */
+  ADCx->CHSELR |= (uint32_t)ADC_Channel;
+
+  /* Clear the Sampling time Selection bits */
+  tmpreg &= ~ADC_SMPR1_SMPR;
+
+  /* Set the ADC Sampling Time register */
+  tmpreg |= (uint32_t)ADC_SampleTime;
+
+  /* Configure the ADC Sample time register */
+  ADCx->SMPR = tmpreg ;
+}
+
+/**
+  * @brief  Enable the Continuous mode for the selected ADCx channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the Continuous mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   It is not possible to have both discontinuous mode and continuous mode
+  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
+  *         as if continuous mode was disabled
+  * @retval None
+  */
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Continuous mode*/
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
+  }
+  else
+  {
+    /* Disable the Continuous mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
+  }
+}
+
+/**
+  * @brief  Enable the discontinuous mode for the selected ADC channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the discontinuous mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   It is not possible to have both discontinuous mode and continuous mode
+  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
+  *         as if continuous mode was disabled
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+  {
+    /* Enable the Discontinuous mode */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
+  }
+  else
+  {
+    /* Disable the Discontinuous mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
+  }
+}
+
+/**
+  * @brief  Enable the Overrun mode for the selected ADC channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the Overrun mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+  {
+    /* Enable the Overrun mode */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
+  }
+  else
+  {
+    /* Disable the Overrun mode */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
+  }
+}
+
+/**
+  * @brief  Active the Calibration operation for the selected ADC.
+  * @note   The Calibration can be initiated only when ADC is still in the
+  *         reset configuration (ADEN must be equal to 0).
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval ADC Calibration factor
+  */
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
+{
+  uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Set the ADC calibartion */
+  ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
+
+  /* Wait until no ADC calibration is completed */
+  do
+  {
+    calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
+    calibrationcounter++;
+  } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
+
+  if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
+  {
+    /*Get the calibration factor from the ADC data register */
+    tmpreg = ADCx->DR;
+  }
+  else
+  {
+    /* Error factor */
+    tmpreg = 0x00000000;
+  }
+  return tmpreg;
+}
+
+/**
+  * @brief  Stop the on going conversions for the selected ADC.
+  * @note   When ADSTP is set, any on going conversion is aborted, and the ADC
+  *         data register is not updated with current conversion.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_StopOfConversion(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
+}
+
+/**
+  * @brief  Start Conversion for the selected ADC channels.
+  * @note   In continuous mode, ADSTART is not cleared by hardware with the
+  *         assertion of EOSEQ because the sequence is automatic relaunched
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_StartOfConversion(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for ADC channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_DMARequestMode: the ADC channel to configure.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_DMAMode_OneShot: DMA One Shot Mode
+  *            @arg ADC_DMAMode_Circular: DMA Circular Mode
+  *  @retval None
+  */
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
+  ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @param  NewState: new state of the specified ADC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_CONFIG_IT(ADC_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->IER |= ADC_IT;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->IER &= (~(uint32_t)ADC_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_OVR: Overrun flag
+  *            @arg ADC_FLAG_EOSEQ: End of Sequence flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_EOSMP: End of sampling flag
+  *            @arg ADC_FLAG_ADRDY: ADC Ready flag
+  *            @arg ADC_FLAG_ADEN: ADC enable flag
+  *            @arg ADC_FLAG_ADDIS: ADC disable flag
+  *            @arg ADC_FLAG_ADSTART: ADC start flag
+  *            @arg ADC_FLAG_ADSTP: ADC stop flag
+  *            @arg ADC_FLAG_ADCAL: ADC Calibration flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  if((uint32_t)(ADC_FLAG & 0x01000000))
+  {
+    tmpreg = ADCx->CR & 0xFEFFFFFF;
+  }
+  else
+  {
+    tmpreg = ADCx->ISR;
+  }
+
+  /* Check the status of the specified ADC flag */
+  if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_ADRDY: ADC Ready flag
+  *            @arg ADC_FLAG_EOSMP: End of sampling flag
+  *            @arg ADC_FLAG_EOSEQ: End of Sequence flag
+  *            @arg ADC_FLAG_OVR: Overrun flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->ISR = (uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral
+  * @param  ADC_IT: specifies the ADC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (uint32_t)(ADCx->IER & ADC_IT);
+
+  /* Check the status of the specified ADC interrupt */
+  if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_ADRDY: ADC ready interrupt
+  *            @arg ADC_IT_EOSMP: End of sampling interrupt
+  *            @arg ADC_IT_EOC: End of conversion interrupt
+  *            @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
+  *            @arg ADC_IT_OVR: overrun interrupt
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_CLEAR_IT(ADC_IT));
+
+    /* Clear the selected ADC interrupt pending bits */
+    ADCx->ISR = (uint32_t)ADC_IT;
+}
+
+
+/**
+  * @brief  select the ADC VREF.
+  * @param  ADC_Vrefsel: The sVREF value to be set for the ADC.
+             This parameter can be one of the following values:
+  *            @arg ADC_Vrefsel_0_625V: VREF 0.625V selected
+  *            @arg ADC_Vrefsel_1_5V:   VREF 1.5V selected
+  *            @arg ADC_Vrefsel_2_5V:   VREF 2.5V selected
+  *            @arg ADC_Vrefsel_VDDA:   VREF VDDA selected
+  * @retval None
+  */
+void ADC_VrefselConfig(uint32_t ADC_Vrefsel)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_ADC_Vrefsel(ADC_Vrefsel));
+
+    /* Read CR2 register */
+    tmpreg = ADC->CR2;
+
+    /* Clear the Vref Selection bits */
+    tmpreg &= ~((uint32_t)0x0000000E) ;
+
+    /* Set the ADC Vref register */
+    tmpreg |= (uint32_t)ADC_Vrefsel;
+
+    /* Configure the ADC Vref register */
+    ADC->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enable Reference voltage halved.
+  * @param  NewState: new state of the reference voltage halved.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_VrefDecibCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the Discontinuous mode */
+        ADC->CR2 |= (uint32_t)ADC_CR2_VREF_DECIB;
+    }
+    else
+    {
+        /* Disable the Discontinuous mode */
+        ADC->CR2 &= (uint32_t)(~ADC_CR2_VREF_DECIB);
+    }
+}
+
+/**
+  * @brief  Sampling hold circuit sampling enable or disable.
+  * @param  SmpEn:
+  *         @arg    ADC_IOSH1_SMPEN
+  *         @arg    ADC_IOSH2_SMPEN
+  * @param  NewState: new state of SMP.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_IoshSmpCmd(uint32_t SmpEn, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_SMPEN(SmpEn));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC->CR2 |= SmpEn;
+    }
+    else
+    {
+        ADC->CR2 &= ~SmpEn;
+    }
+}
+
+/**
+  * @brief  The hold enable bit of the sample-hold circuit.
+  * @param  SmpEn:
+  *         @arg    ADC_IOSH1_AMPEN
+  *         @arg    ADC_IOSH2_AMPEN
+  * @param  NewState: new state of AMP.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_IoshAmpCmd(uint32_t AmpEn, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_AMPEN(AmpEn));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC->CR2 |= AmpEn;
+    }
+    else
+    {
+        ADC->CR2 &= ~AmpEn;
+    }
+}
+
+/**
+  * @brief  Input source selection.
+  * @param  Ioshx:
+  *         @arg    ADC_CR2_IOSH1_SEL
+  *         @arg    ADC_CR2_IOSH2_SEL
+  * @param  SmpSel:
+  *         if Ioshx is ADC_CR2_IOSH1_SEL,the SmpSel can be
+  *         @arg    ADC_IOSH1_SMPSEL_PB1
+  *         @arg    ADC_IOSH1_SMPSEL_OP1OUT
+  *         if Ioshx is ADC_CR2_IOSH2_SEL,the SmpSel can be
+  *         @arg    ADC_IOSH2_SMPSEL_PB0
+  *         @arg    ADC_IOSH2_SMPSEL_OP2OUT
+  * @note   None
+  * @retval None
+  */
+#if defined (FT32F072xB)
+void ADC_IoshSmpSel(uint32_t Ioshx, uint32_t SmpSel)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_IOSH(Ioshx));
+    assert_param(IS_ADC_SMPSEL(SmpSel));
+
+    /* Read CR2 register */
+    tmpreg = ADC->CR2;
+
+    if (Ioshx != ADC_CR2_IOSH1_SEL)
+    {
+        /* IOSH2 */
+        tmpreg &= ~ADC_CR2_IOSH2_SEL;
+    }
+    else
+    {
+        /* IOSH1 */
+        tmpreg &= ~ADC_CR2_IOSH1_SEL;
+    }
+
+    tmpreg |= SmpSel;
+
+    /* Config CR2 register */
+    ADC->CR2 = tmpreg;
+}
+/**
+  * @brief  The hold enable bit of the sample-hold circuit.
+  * @param  SmpModBit:
+  *         @arg    ADC_CR2_IOSH1_SMPMOD
+  *         @arg    ADC_CR2_IOSH2_SMPMOD
+  * @param  Mode:
+  *         @arg    ADC_SMP_SOFTWARE_MODE
+  *         @arg    ADC_SMP_HARDWARE_MODE
+  * @note   None
+  * @retval None
+  */
+void ADC_IoshSmpMod(uint32_t SmpModBit, uint32_t Mode)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_SMPMOD(SmpModBit));
+    assert_param(IS_ADC_MODE(Mode));
+
+    /* Read CR2 register */
+    tmpreg = ADC->CR2;
+
+    if (Mode != ADC_SMP_SOFTWARE_MODE)
+    {
+        /* Hardware mode */
+        if (SmpModBit != ADC_CR2_IOSH1_SMPMOD)
+        {
+            /* IOSH2 */
+            tmpreg |= ADC_CR2_IOSH2_SMPMOD | ADC_CR2_IOSH2_AMPEN;
+        }
+        else
+        {
+            /* IOSH1 */
+            tmpreg |= ADC_CR2_IOSH1_SMPMOD | ADC_CR2_IOSH1_AMPEN;
+        }
+    }
+    else
+    {
+        /* Software mode */
+        if (SmpModBit != ADC_CR2_IOSH1_SMPMOD)
+        {
+            /* IOSH2 */
+            tmpreg &= ~ADC_CR2_IOSH2_AMPEN;
+            tmpreg |= ADC_CR2_IOSH2_SMPMOD | ADC_CR2_IOSH2_SMPEN;
+        }
+        else
+        {
+            /* IOSH1 */
+            tmpreg &= ~ADC_CR2_IOSH1_AMPEN;
+            tmpreg |= ADC_CR2_IOSH1_SMPMOD | ADC_CR2_IOSH1_SMPEN;
+        }
+    }
+
+    /* Config CR2 register */
+    ADC->CR2 = tmpreg;
+}
+/**
+  * @brief  External hardware trigger mode config.
+  * @param  NewState: new state of .
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_ExtModeCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC1->ETCR |= ADC_ETCR_EXTMOD;
+    }
+    else
+    {
+        ADC1->ETCR &= ~ADC_ETCR_EXTMOD;
+    }
+}
+
+/**
+  * @brief  Stop sampling configuration after triggering.
+  * @param  NewState: new state of .
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_TrgdDisSmpCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC1->ETCR |= ADC_ETCR_TRGDISSMP;
+    }
+    else
+    {
+        ADC1->ETCR &= ~ADC_ETCR_TRGDISSMP;
+    }
+}
+/**
+  * @brief  The delay time of The external hardware triggers.
+  * @param  ExtDly: 0~1023.
+  * @note   None
+  * @retval None
+  */
+void ADC_ExtDlyConfig(uint32_t ExtDly)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_EXTDLY(ExtDly));
+
+    /* Read ETCR register */
+    tmpreg = ADC1->ETCR;
+
+    /* Clear EXTDLY */
+    tmpreg &= ~ADC_ETCR_EXTDLY;
+
+    /* Config EXTDLY */
+    tmpreg |= ExtDly;
+
+    /* Config ETCR */
+    ADC1->ETCR = tmpreg;
+}
+
+/**
+  * @brief  Rising edge triggering config.
+  * @param  Rtenx:This parameter can be :
+  *         ADC_RTENR_RTEN or ADC_RTENR_RTEN_0  ~ ADC_RTENR_RTEN_18
+  * @param  NewState: new state of .
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_RtenCmd(uint32_t Rtenx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_RTEN(Rtenx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC1->RTENR |= Rtenx;
+    }
+    else
+    {
+        ADC1->RTENR &= ~Rtenx;
+    }
+}
+
+/**
+  * @brief  Falling edge triggering config.
+  * @param  Ftenx:This parameter can be :
+  *         ADC_FTENR_RTEN or ADC_FTENR_RTEN_0  ~ ADC_FTENR_RTEN_18
+  * @param  NewState: new state of .
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   None
+  * @retval None
+  */
+void ADC_FtenCmd(uint32_t Ftenx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_FTEN(Ftenx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADC1->FTENR |= Ftenx;
+    }
+    else
+    {
+        ADC1->FTENR &= ~Ftenx;
+    }
+}
+
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_comp.c

@@ -0,0 +1,309 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_comp.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the comparators (COMP1 and COMP2) peripheral:
+  *                      + Comparators configuration
+  *                      + Window mode control
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_comp.h"
+
+#define COMP_CSR_CLEAR_MASK              ((uint32_t)0x00003FFE)
+
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  None
+  * @retval None
+  */
+void COMP_DeInit(void)
+{
+    COMP->CSR = ((uint32_t)0x00000000);    /*!< Set COMP_CSR register to reset value */
+
+    #if defined(FT32F072xB)
+        COMP->CSR2 = ((uint32_t)0x00000000);
+    #endif
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  *            @arg COMP_Selection_COMP3: COMP3 selected
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
+  *         the configuration information for the specified COMP peripheral.
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+    assert_param(IS_COMP_VIP_SEL(COMP_InitStruct->COMP_VipSel));
+    assert_param(IS_COMP_VINSEL(COMP_InitStruct->COMP_VinSel));
+    assert_param(IS_COMP_OUTPUT_SEL(COMP_InitStruct->COMP_OutputSel));
+    assert_param(IS_COMP_POL(COMP_InitStruct->COMP_Pol));
+
+    if (COMP_Selection != COMP_Selection_COMP3)
+    {
+        /*!< Get the COMP_CSR register value */
+        tmpreg = COMP->CSR;
+
+        /*!< Clear the bits */
+        tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
+
+        /*!< Configure COMP: COMP_VipSel, COMP_VinSel, COMP_OutputSel value and COMP_Pol */
+        tmpreg |= (uint32_t)((COMP_InitStruct->COMP_VipSel | COMP_InitStruct->COMP_VinSel|
+                           COMP_InitStruct->COMP_OutputSel | COMP_InitStruct->COMP_Pol));
+
+        /*!< Write to COMP_CSR register */
+        COMP->CSR = tmpreg;
+    }
+    else
+    {
+        #if defined(FT32F072xB)
+            /*!< Get the COMP_CSR register value */
+            tmpreg = COMP->CSR2;
+
+            /*!< Clear the bits */
+            tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK);
+
+            /*!< Configure COMP: COMP_VipSel, COMP_VinSel, COMP_OutputSel value and COMP_Pol */
+            tmpreg |= (uint32_t)((COMP_InitStruct->COMP_VipSel | COMP_InitStruct->COMP_VinSel|
+                                    COMP_InitStruct->COMP_OutputSel | COMP_InitStruct->COMP_Pol));
+
+            /*!< Write to COMP_CSR2 register */
+            COMP->CSR2 = tmpreg;
+        #endif
+    }
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
+{
+    #if defined(FT32F072xB)
+        COMP_InitStruct->COMP_VipSel = 0;
+        COMP_InitStruct->COMP_VinSel = 0;
+        COMP_InitStruct->COMP_OutputSel = 0;
+        COMP_InitStruct->COMP_Pol = 0;
+    #else
+        COMP_InitStruct->COMP_VipSel = NCOMP_VIP_SEL_PAD_PA1;
+        COMP_InitStruct->COMP_VinSel = NCOMP_VIN_SEL_PAD_PA0 | PCOMP_VIN_SEL_PAD_PA2;
+        COMP_InitStruct->COMP_OutputSel = 0;
+        COMP_InitStruct->COMP_Pol = 0;
+    #endif
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  *            @arg COMP_Selection_COMP3: COMP3 selected
+  * @param  NewState: new state of the COMP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the
+  *         output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if(COMP_Selection != COMP_Selection_COMP3)
+    {
+        if (NewState != DISABLE)
+        {
+            /* Enable the selected COMP peripheral */
+            COMP->CSR |= (uint32_t) (1<<COMP_Selection);
+        }
+        else
+        {
+            /* Disable the selected COMP peripheral  */
+            COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
+        }
+    }
+    else
+    {
+        #if defined(FT32F072xB)
+            if (NewState != DISABLE)
+            {
+                /* Enable the selected COMP peripheral */
+                COMP->CSR2 |= (uint32_t) (1);
+            }
+            else
+            {
+                /* Disable the selected COMP peripheral  */
+                COMP->CSR2 &= (uint32_t)(~((uint32_t)1));
+            }
+        #endif
+
+    }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator.
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  *            @arg COMP_Selection_COMP3: COMP3 selected
+  * @retval Returns the selected comparator output level: low or high.
+  *
+  */
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
+{
+    uint32_t compout = 0x0;
+
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+    if(COMP_Selection != COMP_Selection_COMP3)
+    {
+        /* Check if selected comparator output is high */
+        if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
+        {
+            compout = COMP_OutputLevel_High;
+        }
+        else
+        {
+            compout = COMP_OutputLevel_Low;
+        }
+    }
+    else
+    {
+        #if defined(FT32F072xB)
+            /* Check if selected comparator output is high */
+            if ( (COMP->CSR2 & COMP_CSR_COMP3OUT) != 0)
+            {
+                compout = COMP_OutputLevel_High;
+            }
+            else
+            {
+                compout = COMP_OutputLevel_Low;
+            }
+        #endif
+    }
+
+    /* Return the comparator output level */
+    return (uint32_t)(compout);
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the window mode.
+  * @note   In window mode, COMP1 and COMP2 non inverting inputs are connected
+  *         together and only COMP1 non inverting input (PA1) can be used.
+  * @param  NewState: new state of the window mode.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
+  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: selects the comparator to be locked
+  *          This parameter can be a value of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 configuration is locked.
+  *            @arg COMP_Selection_COMP2: COMP2 configuration is locked.
+  *            @arg COMP_Selection_COMP3: COMP3 configuration is locked.
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+    if(COMP_Selection != COMP_Selection_COMP3)
+    {
+        /* Set the lock bit corresponding to selected comparator */
+        COMP->CSR |= (uint32_t) (COMP_CSR_NCOMPLOCK<<COMP_Selection);
+    }
+    else
+    {
+        #if defined(FT32F072xB)
+            /* Set the lock bit corresponding to selected comparator */
+            COMP->CSR2 |= (uint32_t) (COMP_CSR_COMP3LOCK);
+        #endif
+    }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crc.c

@@ -0,0 +1,261 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_crc.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of CRC computation unit peripheral:
+  *                 + Configuration of the CRC computation unit
+  *                 + CRC computation of one/many 32-bit data
+  *               + CRC Independent register (IDR) access
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_crc.h"
+
+/**
+  * @brief  Deinitializes CRC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CRC_DeInit(void)
+{
+  /* Set DR register to reset value */
+  CRC->DR = 0xFFFFFFFF;
+
+  /* Reset IDR register */
+  CRC->IDR = 0x00;
+
+  /* Set INIT register to reset value */
+  CRC->INIT = 0xFFFFFFFF;
+
+  /* Reset the CRC calculation unit */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Resets the CRC calculation unit and sets INIT register content in DR register.
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR |= CRC_CR_RESET;
+}
+
+/**
+  * @brief  Selects the polynomial size. This function is only applicable for
+  *         FT32F072 devices.
+  * @param  CRC_PolSize: Specifies the polynomial size.
+  *         This parameter can be:
+  *          @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
+  * @retval None
+  */
+//void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
+//{
+//  uint32_t tmpcr = 0;
+
+//  /* Check the parameter */
+//  assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
+
+//  /* Get CR register value */
+//  tmpcr = CRC->CR;
+
+//  /* Reset POL_SIZE bits */
+//  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
+//  /* Set the polynomial size */
+//  tmpcr |= (uint32_t)CRC_PolSize;
+
+//  /* Write to CR register */
+//  CRC->CR = (uint32_t)tmpcr;
+//}
+
+/**
+  * @brief  Selects the reverse operation to be performed on input data.
+  * @param  CRC_ReverseInputData: Specifies the reverse operation on input data.
+  *          This parameter can be:
+  *            @arg CRC_ReverseInputData_No: No reverse operation is performed
+  *            @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
+  *            @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
+  *            @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
+  * @retval None
+  */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
+{
+  uint32_t tmpcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
+
+  /* Get CR register value */
+  tmpcr = CRC->CR;
+
+  /* Reset REV_IN bits */
+  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
+  /* Set the reverse operation */
+  tmpcr |= (uint32_t)CRC_ReverseInputData;
+
+  /* Write to CR register */
+  CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+  * @brief  Enables or disable the reverse operation on output data.
+  *         The reverse operation on output data is performed on 32-bit.
+  * @param  NewState: new state of the reverse operation on output data.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRC_ReverseOutputDataCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable reverse operation on output data */
+    CRC->CR |= CRC_CR_REV_OUT;
+  }
+  else
+  {
+    /* Disable reverse operation on output data */
+    CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
+  }
+}
+
+/**
+  * @brief  Initializes the INIT register.
+  * @note   After resetting CRC calculation unit, CRC_InitValue is stored in DR register
+  * @param  CRC_InitValue: Programmable initial CRC value
+  * @retval None
+  */
+void CRC_SetInitRegister(uint32_t CRC_InitValue)
+{
+  CRC->INIT = CRC_InitValue;
+}
+
+/**
+  * @brief  Initializes the polynomail coefficients. This function is only
+  *         applicable for FT32F072 devices.
+  * @param  CRC_Pol: Polynomial to be used for CRC calculation.
+  * @retval None
+  */
+void CRC_SetPolynomial(uint32_t CRC_Pol)
+{
+ // CRC->POL = CRC_Pol;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  CRC_Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t CRC_Data)
+{
+  CRC->DR = CRC_Data;
+
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 16-bit CRC of a given 16-bit data.
+  * @param  CRC_Data: data half-word(16-bit) to compute its CRC
+  * @retval 16-bit CRC
+  */
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
+{
+  *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
+
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 8-bit CRC of a given 8-bit data.
+  * @param  CRC_Data: 8-bit data to compute its CRC
+  * @retval 8-bit CRC
+  */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
+{
+  *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
+
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Stores an 8-bit data in the Independent Data(ID) register.
+  * @param  CRC_IDValue: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t CRC_IDValue)
+{
+  CRC->IDR = CRC_IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (uint8_t)(CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crs.c

@@ -0,0 +1,401 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_crs.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of CRS peripheral :
+  *                 + Configuration of the CRS peripheral
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_crs.h"
+#include "ft32f0xx_rcc.h"
+
+
+/** @defgroup CRS
+  * @brief CRS driver modules
+  * @{
+  */
+
+/* CRS Flag Mask */
+#define FLAG_MASK                 ((uint32_t)0x700)
+
+
+/**
+  * @brief  Deinitializes CRS peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CRS_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI48 RC.
+  * @note   This function can be called only when the AUTOTRIMEN bit is reset.
+  * @param  CRS_HSI48CalibrationValue:
+  * @retval None
+  */
+void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue)
+{
+  /* Clear TRIM[5:0] bits */
+  CRS->CR &= ~CRS_CR_TRIM;
+
+  /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */
+  CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8);
+
+}
+
+/**
+  * @brief  Enables or disables the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @param  NewState: new state of the frequency error counter.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_FrequencyErrorCounterCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+        CRS->CR |= CRS_CR_CEN;
+  }
+  else
+  {
+        CRS->CR &= ~CRS_CR_CEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the automatic hardware adjustement of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @param  NewState: new state of the automatic trimming.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_AutomaticCalibrationCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    CRS->CR |= CRS_CR_AUTOTRIMEN;
+  }
+else
+  {
+    CRS->CR &= ~CRS_CR_AUTOTRIMEN;
+  }
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @param  None
+  * @retval None
+  */
+void CRS_SoftwareSynchronizationGenerate(void)
+{
+  CRS->CR |= CRS_CR_SWSYNC;
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI48 RC.
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_ReloadValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and .
+  * @retval None
+  */
+void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue)
+{
+
+  /* Clear RELOAD[15:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_RELOAD;
+
+  /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */
+  CRS->CFGR |= (uint32_t)CRS_ReloadValue;
+
+}
+
+/**
+  * @brief
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_ErrorLimitValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and .
+  * @retval None
+  */
+void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue)
+{
+  /* Clear FELIM[7:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_FELIM;
+
+  /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */
+  CRS->CFGR |= (uint32_t)(CRS_ErrorLimitValue <<16);
+}
+
+/**
+  * @brief
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Prescaler: specifies the HSI calibration trimming value.
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNC_Div1:
+  *            @arg CRS_SYNC_Div2:
+  *            @arg CRS_SYNC_Div4:
+  *            @arg CRS_SYNC_Div8:
+  *            @arg CRS_SYNC_Div16:
+  *            @arg CRS_SYNC_Div32:
+  *            @arg CRS_SYNC_Div64:
+  *            @arg CRS_SYNC_Div128:
+  * @retval None
+  */
+void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler));
+
+  /* Clear SYNCDIV[2:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_SYNCDIV;
+
+  /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */
+  CRS->CFGR |= CRS_Prescaler;
+}
+
+/**
+  * @brief
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Source: .
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNCSource_GPIO:
+  *            @arg CRS_SYNCSource_LSE:
+  *            @arg CRS_SYNCSource_USB:
+  * @retval None
+  */
+void CRS_SynchronizationSourceConfig(uint32_t CRS_Source)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_SOURCE(CRS_Source));
+
+  /* Clear SYNCSRC[1:0] bits */
+  CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  CRS->CFGR |= CRS_Source;
+}
+
+/**
+  * @brief
+  * @note   This function can be called only when the CEN bit is reset.
+  * @param  CRS_Polarity: .
+  *          This parameter can be one of the following values:
+  *            @arg CRS_SYNCPolarity_Rising:
+  *            @arg CRS_SYNCPolarity_Falling:
+  * @retval None
+  */
+void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity));
+
+  /* Clear SYNCSPOL bit */
+  CRS->CFGR &= ~CRS_CFGR_SYNCPOL;
+
+  /* Set the SYNCSPOL bits according to CRS_Polarity value */
+  CRS->CFGR |= CRS_Polarity;
+}
+
+/**
+  * @brief  Returns the Relaod value.
+  * @param  None
+  * @retval The reload value
+  */
+uint32_t CRS_GetReloadValue(void)
+{
+  return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Returns the HSI48 Calibration value.
+  * @param  None
+  * @retval The reload value
+  */
+uint32_t CRS_GetHSI48CalibrationValue(void)
+{
+  return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8);
+}
+
+/**
+  * @brief  Returns the frequency error capture.
+  * @param  None
+  * @retval The frequency error capture value
+  */
+uint32_t CRS_GetFrequencyErrorValue(void)
+{
+  return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP));
+}
+
+/**
+  * @brief  Returns the frequency error direction.
+  * @param  None
+  * @retval The frequency error direction. The returned value can be one
+  *         of the following values:
+  *           - 0x00: Up counting
+  *           - 0x8000: Down counting
+  */
+uint32_t CRS_GetFrequencyErrorDirection(void)
+{
+  return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR));
+}
+
+
+/**
+  * @brief  Enables or disables the specified CRS interrupts.
+  * @param  CRS_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg CRS_IT_SYNCOK:
+  *              @arg CRS_IT_SYNCWARN:
+  *              @arg CRS_IT_ERR:
+  *              @arg CRS_IT_ESYNC:
+  * @param  NewState: new state of the specified CRS interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_IT(CRS_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    CRS->CR |= CRS_IT;
+  }
+  else
+  {
+    CRS->CR &= ~CRS_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRS flag is set or not.
+  * @param  CRS_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_FLAG_SYNCOK:
+  *              @arg CRS_FLAG_SYNCWARN:
+  *              @arg CRS_FLAG_ERR:
+  *              @arg CRS_FLAG_ESYNC:
+  *              @arg CRS_FLAG_TRIMOVF:
+  *              @arg CRS_FLAG_SYNCERR:
+  *              @arg CRS_FLAG_SYNCMISS:
+  * @retval The new state of CRS_FLAG (SET or RESET).
+  */
+FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_FLAG(CRS_FLAG));
+
+  return ((FlagStatus)(CRS->ISR & CRS_FLAG));
+}
+
+/**
+  * @brief  Clears the CRS specified FLAG.
+  * @param  CRS_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_FLAG_SYNCOK:
+  *              @arg CRS_FLAG_SYNCWARN:
+  *              @arg CRS_FLAG_ERR:
+  *              @arg CRS_FLAG_ESYNC:
+  *              @arg CRS_FLAG_TRIMOVF:
+  *              @arg CRS_FLAG_SYNCERR:
+  *              @arg CRS_FLAG_SYNCMISS:
+  * @retval None
+  */
+void CRS_ClearFlag(uint32_t CRS_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_FLAG(CRS_FLAG));
+
+  if ((CRS_FLAG & FLAG_MASK)!= 0)
+  {
+    CRS->ICR |= CRS_ICR_ERRC;
+  }
+  else
+  {
+    CRS->ICR |= CRS_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRS IT pending bit is set or not.
+  * @param  CRS_IT: specifies the IT pending bit to check.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_IT_SYNCOK:
+  *              @arg CRS_IT_SYNCWARN:
+  *              @arg CRS_IT_ERR:
+  *              @arg CRS_IT_ESYNC:
+  *              @arg CRS_IT_TRIMOVF:
+  *              @arg CRS_IT_SYNCERR:
+  *              @arg CRS_IT_SYNCMISS:
+  * @retval The new state of CRS_IT (SET or RESET).
+  */
+ITStatus CRS_GetITStatus(uint32_t CRS_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_GET_IT(CRS_IT));
+
+  return ((ITStatus)(CRS->ISR & CRS_IT));
+}
+
+/**
+  * @brief  Clears the CRS specified IT pending bi.
+  * @param  CRS_FLAG: specifies the IT pending bi to clear.
+  *          This parameter can be one of the following values:
+  *              @arg CRS_IT_SYNCOK:
+  *              @arg CRS_IT_SYNCWARN:
+  *              @arg CRS_IT_ERR:
+  *              @arg CRS_IT_ESYNC:
+  *              @arg CRS_IT_TRIMOVF:
+  *              @arg CRS_IT_SYNCERR:
+  *              @arg CRS_IT_SYNCMISS:
+  * @retval None
+  */
+void CRS_ClearITPendingBit(uint32_t CRS_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CRS_CLEAR_IT(CRS_IT));
+
+  if ((CRS_IT & FLAG_MASK)!= 0)
+  {
+    CRS->ICR |= CRS_ICR_ERRC;
+  }
+  else
+  {
+    CRS->ICR |= CRS_IT;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dac.c

@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_dac.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of DAC peripheral
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_dac.h"
+
+/**
+    *
+    */
+void DAC_Ref_Config(uint32_t    DAC_RefSel)
+{
+    uint32_t tmpreg = 0;
+
+    assert_param(IS_DAC_REF_SEL(DAC_RefSel));
+
+    tmpreg = DAC->CTRL;
+    tmpreg &= ~DAC_CTRL_REF_SEL;
+    tmpreg |= DAC_RefSel;
+
+    DAC->CTRL |= tmpreg;
+}
+/**
+    *   @Parame
+    */
+void DAC_Cmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTRL |= DAC_CTRL_EN;
+    }
+    else
+    {
+        DAC->CTRL &= ~DAC_CTRL_EN;
+    }
+}
+
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: no use.
+  * @param  Data: Data to be loaded in the selected data DAC1DATA register. 7BIT
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_DATA(Data));
+
+  DAC->DATA1 = (uint32_t)Data;
+}
+
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_DATA(Data));
+
+  DAC->DATA2 = (uint32_t)Data;
+}
+
+
+
+/**
+    *   @Parame
+    *
+    */
+uint8_t DAC_Read_Reg(uint8_t DAC_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DAC_Register;
+
+  /* Return the selected register value */
+  return (uint8_t)(*(__IO uint32_t *) tmp);
+}

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_debug.c

@@ -0,0 +1,152 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_debug.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Debug MCU (DBGMCU) peripheral:
+  *                 + Device and Revision ID management
+  *                 + Peripherals Configuration
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_debug.h"
+
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+  *             @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+  *             @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped
+  *                                   when Core is halted.
+  *             @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *             @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+  *             @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
+  *                                             when Core is halted
+  *             @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted
+  * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *          This parameter can be any combination of the following values:
+  *             @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+  *             @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
+  * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_div.c

@@ -0,0 +1,228 @@
+/**
+  ******************************************************************************
+  * @file               FT32f0xx_div.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the dividor peripheral
+  *                     applicable only on FT32F072xB devices:
+  *                     + Comparators configuration
+  *                     + Window mode control
+  * @version            V1.0.0
+  * @data               2021-12-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_div.h"
+
+/**
+  * @brief  Enable or disable the OPA peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPA_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg NOPA_Selection_OPA: OPA1 selected
+  *            @arg POPA_Selection_OPA: OPA2 selected
+  * @param  NewState: new state of the OPA peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the
+  *         output level is low.
+  * @retval None
+  */
+DIV_Status DivS32ByS16(DIV_ResultTypeDef* pResult,int32_t divedent,int16_t dividor)
+{
+    DIV_Status status = DIV_COMPLETE;
+    DIV->DID = divedent;
+    DIV->DIS = dividor;
+    while(DIV_GetFlagStatus(DIV_FLAG_BUSY) == SET);
+    if(DIV_GetFlagStatus(DIV_FLAG_DIV0ERR) == SET)
+    {
+        status = DIV_ERROR_DIV0ERR;
+    }
+    else if(DIV_GetFlagStatus(DIV_FLAG_DIVOV) == SET)
+    {
+        status = DIV_ERROR_DIV0V;
+    }
+    else
+    {
+        pResult -> DIV_quotient = DIV-> QUO;
+        pResult -> DIV_remainder = DIV-> REM;
+    }
+    return status;
+}
+
+/** @defgroup DIV Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions.
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the DIV Interrupts
+         and get the status and clear flags and Interrupts pending bits.
+
+  *** Flags for DIV status ***
+  ======================================================
+    [..]
+        (+)Flags :
+           (##) DIV_FLAG_DIV0ERR : This flag is set after the ADC has been enabled (bit ADEN=1)
+               and when the ADC reaches a state where it is ready to accept conversion requests
+           (##) DIV_FLAG_DIVOV : This flag is set by software to enable the ADC.
+                The DIV will be effectively ready to operate once the ADRDY flag has been set.
+           (##) DIV_FLAG_BUSY : This flag is cleared once the ADC is effectively
+                disabled.
+        (+)Interrupts
+           (##) DIV_IT_DIV0ERR : specifies the interrupt source for ADC ready event.
+           (##) DIV_IT_DIVOV :   specifies the interrupt source for ADC ready event.
+
+    [..] The user should identify which mode will be used in his application to
+         manage the ADC controller events: Polling mode or Interrupt mode.
+
+    [..] In the Polling Mode it is advised to use the following functions:
+         (+) DIV_GetFlagStatus() : to check if flags events occur.
+         (+) DIV_ClearFlag()     : to clear the flags events.
+
+    [..] In the Interrupt Mode it is advised to use the following functions:
+         (+) DIV_ITConfig()       : to enable or disable the interrupt source.
+         (+) DIV_GetITStatus()    : to check if Interrupt occurs.
+         (+) DIV_ClearITPendingBit() : to clear the Interrupt pending Bit
+             (corresponding Flag).
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables or disables the specified DIV interrupts.
+  * @param  DIV_IT: specifies the DIV interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg DIV_IT_DIV0ERR: Divide By Zero Exception
+  *            @arg DIV_IT_DIVOV: Overflow interrupt
+  * @param  NewState: new state of the specified DIV interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DIV_ITConfig(uint32_t DIV_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_DIV_CONFIG_IT(DIV_IT));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected DIV interrupts */
+        DIV->SC |= DIV_IT;
+    }
+    else
+    {
+        /* Disable the selected DIV interrupts */
+        DIV->SC &= (~(uint32_t)DIV_IT);
+    }
+}
+
+/**
+  * @brief  Checks whether the specified DIV flag is set or not.
+  * @param  DIV_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DIV_FLAG_DIV0ERR: Divide By Zero Exception flag
+  *            @arg DIV_FLAG_DIVOV: Overflow flag
+  *            @arg DIV_FLAG_BUSY: Busy flag
+  * @retval The new state of DIV_FLAG (SET or RESET).
+  */
+FlagStatus DIV_GetFlagStatus(uint32_t DIV_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_DIV_GET_FLAG(DIV_FLAG));
+
+    /* Check the status of the specified DIV flag */
+    if ((DIV->SC & DIV_FLAG) != (uint32_t)RESET)
+    {
+        /* DIV_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DIV_FLAG is reset */
+        bitstatus = RESET;
+    }
+    /* Return the DIV_FLAG status */
+    return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DIV's pending flags.
+  * @param  DIV_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DIV_FLAG_DIV0ERRC: Divide By Zero Exception flag
+  *            @arg DIV_FLAG_DIVOVC: Overflow flag
+  * @retval None
+  */
+void DIV_ClearFlag(uint32_t DIV_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_DIV_CLEAR_FLAG(DIV_FLAG));
+    /* Clear the selected DIV flags */
+    DIV->SC |= (uint32_t)(DIV_FLAG<<8);
+}
+
+/**
+  * @brief  Checks whether the specified DIV interrupt has occurred or not.
+  * @param  DIV_IT: specifies the DIV interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DIV_IT_DIV0ERR: Divide By Zero Exception
+  *            @arg DIV_IT_DIVOV: Overflow interrupt
+  * @retval The new state of DIV_IT (SET or RESET).
+  */
+ITStatus DIV_GetITStatus(uint32_t DIV_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    /* Check the parameters */
+    assert_param(IS_DIV_GET_IT(DIV_IT));
+
+    /* Get the DIV_IT enable bit status */
+    enablestatus = (uint32_t)((DIV->SC>>1) & DIV_IT);
+
+    /* Check the status of the specified DIV interrupt */
+    if (((uint32_t)(DIV->SC & DIV_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        /* DIV_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DIV_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the DIV_IT status */
+    return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DIV's interrupt pending bits.
+  * @param  DIV: where x can be 1 to select the DIV1 peripheral.
+  * @param  DIV_IT: specifies the DIV interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg DIV_IT_DIV0ERR: Divide By Zero Exception
+  *            @arg DIV_IT_DIVOV: Overflow interrupt
+  * @retval None
+  */
+void DIV_ClearITPendingBit(uint32_t DIV_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_DIV_CLEAR_IT(DIV_IT));
+
+    /* Clear the selected DIV interrupt pending bits */
+    DIV->SC |= (uint32_t)(DIV_IT<<8);
+}
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/
+

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dma.c

@@ -0,0 +1,649 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_dma.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Direct Memory Access controller (DMA):
+  *                 + Initialization and Configuration
+  *                 + Data Counter
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_dma.h"
+
+
+/** @defgroup DMA
+  * @brief DMA driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask        ((uint32_t)0x10000000) /* DMA2 FLAG mask */
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks:*/
+#define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+
+
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and
+  *         x can be 1 to 7 for DMA1 to select the DMA Channel.
+  * @note
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CCR  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->CNDTR = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPAR  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMAR = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+  }
+//  else if (DMAy_Channelx == DMA1_Channel6)
+//  {
+//    /* Reset interrupt pending bits for DMA1 Channel6 */
+//    DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+//  }
+//  else if (DMAy_Channelx == DMA1_Channel7)
+//  {
+//    /* Reset interrupt pending bits for DMA1 Channel7 */
+//    DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+//  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified parameters
+  *         in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @note
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CCR;
+
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CCR_CLEAR_MASK;
+
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CCR |= DMA_CCR_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+  }
+}
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+  *         for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *         or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask
+  *            @arg DMA_IT_HT: Half transfer interrupt mask
+  *            @arg DMA_IT_TE: Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMA_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag
+  * @note   The Global flag (DMAy_FLAG_GLx) is set whenever any of the ot
+  *         relative to the same channel is set (Transfer Complete, Half-transfer
+  *         Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
+  *         DMAy_FLAG_TEx).
+  *
+  * @retval The new state of DMA_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+        ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMA_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag
+  *
+  * @note   Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+  *         relative to the same channel (Transfer Complete, Half-transfer Complete and
+  *         Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+  *
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+        ;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->IFCR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMA_IT: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt
+  *            @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt
+  *            @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt
+  *            @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt
+  *            @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt
+  *            @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt
+  *            @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt
+  *            @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt
+  *            @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt
+  *            @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt
+  *            @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt
+  *            @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt
+  *            @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt
+  *            @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt
+  *            @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt
+  *            @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt
+  *            @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt
+  *            @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt
+  *            @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt
+  *            @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt
+  *            @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt
+  * @note   The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
+  *         interrupts relative to the same channel is set (Transfer Complete,
+  *         Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
+  *         DMAy_IT_HTx or DMAy_IT_TEx).
+  *
+  * @retval The new state of DMA_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+        ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+  {
+    /* DMAy_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMAy_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt
+  * @note   Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
+  *         interrupts relative to the same channel (Transfer Complete, Half-transfer
+  *         Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
+  *         DMAy_IT_TEx).
+  *
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+        ;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->IFCR = DMAy_IT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_exti.c

@@ -0,0 +1,223 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_exti.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the EXTI peripheral:
+  *                 + Initialization and Configuration
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_exti.h"
+
+
+
+/** @defgroup EXTI
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE     ((uint32_t)0x00000)        /* No interrupt selected */
+
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x0F940000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x006BFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
+  *         contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+    /* Select the trigger for the selected interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->SWIER |= EXTI_Line;
+}
+
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be (0..27).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+   FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be (0..27).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..27).
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_flash.c

@@ -0,0 +1,1601 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_flash.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the FLASH peripheral:
+  *                 - FLASH Interface configuration
+  *                 - FLASH Memory Programming
+  *                 - Option Bytes Programming
+  *                 - Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_flash.h"
+
+/**
+  * @brief  Sets the code latency value.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *          This parameter can be one of the following values:
+  *             @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  *             @arg FLASH_Latency_1: FLASH One Latency cycle
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+    /* Read the ACR register */
+    tmpreg = FLASH->ACR;
+
+    /* Sets the Latency value */
+    tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+    tmpreg |= FLASH_Latency;
+
+    /* Write the ACR register */
+    FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param  NewState: new state of the FLASH prefetch buffer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if(NewState != DISABLE)
+    {
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+    }
+    else
+    {
+        FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
+    }
+}
+
+/**
+  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+  * @param  None
+  * @retval FLASH Prefetch Buffer Status (SET or RESET).
+  */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+    return bitstatus;
+}
+
+
+/**
+  * @brief  Unlocks the FLASH control register and program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+    if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+    {
+        /* Unlocking the program memory access */
+        FLASH->KEYR = FLASH_FKEY1;
+        FLASH->KEYR = FLASH_FKEY2;
+    }
+}
+
+/**
+  * @brief  Locks the Program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+    /* Set the LOCK Bit to lock the FLASH control register and program memory access */
+    FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+  * @brief  Erases a specified page in program memory.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Page_Address: The page address in program memory to be erased.
+  * @note   A Page is erased in the Program memory only if the address to load
+  *         is the start address of a page (multiple of 512 bytes,in FT32F072XB is 1024 bytes).
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+
+    FLASH_PrefetchBufferCmd(DISABLE);
+  __ASM("ISB");
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to erase the page */
+    FLASH->CR |= FLASH_CR_PER;
+    FLASH->AR  = Page_Address;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* Disable the PER Bit */
+    FLASH->CR &= ~FLASH_CR_PER;
+  }
+
+  FLASH_PrefetchBufferCmd(ENABLE);
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH pages.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    FLASH_PrefetchBufferCmd(DISABLE);
+    __ASM("ISB");
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* if the previous operation is completed, proceed to erase all pages */
+         FLASH->CR |= FLASH_CR_MER;
+         FLASH->CR |= FLASH_CR_STRT;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        /* Disable the MER Bit */
+        FLASH->CR &= ~FLASH_CR_MER;
+    }
+
+    FLASH_PrefetchBufferCmd(ENABLE);
+
+    /* Return the Erase Status */
+    return status;
+}
+
+#if defined(FT32F072xB)
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  FLASH_PrefetchBufferCmd(DISABLE);
+  __ASM("ISB");
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new first
+    half word */
+    FLASH->CR |= FLASH_CR_PG;
+
+    *(__IO uint16_t*)Address = (uint16_t)Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the previous operation is completed, proceed to program the new second
+      half word */
+      tmp = Address + 2;
+
+      *(__IO uint16_t*) tmp = Data >> 16;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+  }
+
+  FLASH_PrefetchBufferCmd(ENABLE);
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  FLASH_PrefetchBufferCmd(DISABLE);
+  __ASM("ISB");
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new data */
+    FLASH->CR |= FLASH_CR_PG;
+
+    *(__IO uint16_t*)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* Disable the PG Bit */
+    FLASH->CR &= ~FLASH_CR_PG;
+  }
+
+  FLASH_PrefetchBufferCmd(ENABLE);
+
+  /* Return the Program Status */
+  return status;
+}
+#else
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access (recommended
+  *         to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  FLASH_PrefetchBufferCmd(DISABLE);
+  __ASM("ISB");
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new first word */
+    FLASH->CR |= FLASH_CR_PG;
+
+    *(__IO uint32_t*)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* Disable the PG Bit */
+    FLASH->CR &= ~FLASH_CR_PG;
+  }
+
+  FLASH_PrefetchBufferCmd(ENABLE);
+
+  /* Return the Program Status */
+  return status;
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Unlocks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
+  {
+    /* Unlocking the option bytes block access */
+    FLASH->OPTKEYR = FLASH_OPTKEY1;
+    FLASH->OPTKEYR = FLASH_OPTKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Lock(void)
+{
+    /* Set the OPTWREN Bit to lock the option bytes block access */
+    FLASH->CR &= ~FLASH_CR_OPTWRE;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Launch(void)
+{
+    /* Set the OBL_Launch bit to launch the option byte loading */
+    FLASH->CR |= FLASH_CR_OBL_LAUNCH;
+}
+
+#if defined(FT32F072xB)
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @note   This functions erases all option bytes except the Read protection (RDP).
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_Erase(void)
+{
+    uint16_t rdptmp = OB_RDP_Level_0;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Get the actual read protection Option Byte value */
+    if(FLASH_OB_GetRDP() != RESET)
+    {
+        rdptmp = 0x0;
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* If the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CR |= FLASH_CR_OPTER;
+        FLASH->CR |= FLASH_CR_STRT;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status == FLASH_COMPLETE)
+        {
+            /* If the erase operation is completed, disable the OPTER Bit */
+            FLASH->CR &= ~FLASH_CR_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            /* Restore the last read protection Option Byte value */
+            OB->RDP = (uint16_t)rdptmp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                FLASH->CR &= ~FLASH_CR_OPTER;
+            }
+        }
+    }
+    /* Return the erase status */
+    return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_WRP: specifies the address of the pages to be write protected.
+  *          This parameter can be:
+  *             @arg OB_WRP_Pages0to7..OB_WRP_Pages120to127
+  *             @arg OB_WRP_AllPages
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+
+  OB_WRP = (uint32_t)(~OB_WRP);
+  WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
+  WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0);
+  WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ;
+  WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    if(WRP0_Data != 0xFF)
+    {
+      OB->WRP0 = WRP0_Data;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+    {
+      OB->WRP1 = WRP1_Data;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+    {
+      OB->WRP2 = WRP2_Data;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
+    {
+      OB->WRP3 = WRP3_Data;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the write protection operation Status */
+  return status;
+}
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  FLASH_ReadProtection_Level: specifies the read protection level.
+  *          This parameter can be:
+  *             @arg OB_RDP_Level_0: No protection
+  *             @arg OB_RDP_Level_1: Read protection of the memory
+  *             @arg
+  * @note   When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_OB_RDP(OB_RDP));
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CR |= FLASH_CR_OPTER;
+        FLASH->CR |= FLASH_CR_STRT;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status == FLASH_COMPLETE)
+        {
+            /* If the erase operation is completed, disable the OPTER Bit */
+            FLASH->CR &= ~FLASH_CR_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->RDP = OB_RDP;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CR &= ~FLASH_CR_OPTER;
+            }
+        }
+    }
+    /* Return the protection operation Status */
+    return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_IWDG: Selects the WDG mode
+  *          This parameter can be one of the following values:
+  *             @arg OB_IWDG_SW: Software WDG selected
+  *             @arg OB_IWDG_HW: Hardware WDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *             @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *             @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+    assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+    assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+
+        OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* If the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT1 option bit.
+  * @param  OB_BOOT1: Set or Reset the BOOT1 option bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_BOOT1_RESET: BOOT1 option bit reset
+  *             @arg OB_BOOT1_SET: BOOT1 option bit set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+
+        OB->USER = OB_BOOT1 | 0xEF;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* If the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+  * @brief  Sets or resets the analogue monitoring on VDDA Power source.
+  * @param  OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+  *          This parameter can be one of the following values:
+  *             @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+  *             @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+  * @retval None
+  */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+
+        OB->USER =  OB_VDDA_ANALOG | 0xDF;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+  * @brief  Sets or resets the SRAM parity.
+  * @param  OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_SRAM_PARITY_SET: Set SRAM parity.
+  *             @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
+  * @retval None
+  */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+
+        OB->USER =  OB_SRAM_Parity | 0xBF;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
+  *         BOOT1 and VDDA ANALOG monitoring.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_USER: Selects all user option bytes
+  *          This parameter is a combination of the following values:
+  *             @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+  *             @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+  *             @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+  *             @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+  *             @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
+  *             @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET
+  *             @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set
+  *             @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* If the erase operation is completed, disable the OPTER Bit */
+        FLASH->CR &= ~FLASH_CR_OPTER;
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+
+        OB->USER = OB_USER;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* If the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+    /* Return the Option Byte program Status */
+    return status;
+
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  *          This parameter can be 0x1FFFF804.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* Enables the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG;
+    *(__IO uint16_t*)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+#else
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @note   This functions erases all option bytes except the Read protection (RDP).
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_Erase(void)
+{
+  uint32_t rdptmp = 0;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Get the actual read protection Option Byte value */
+  if(FLASH_OB_GetRDP() != RESET)
+  {
+    rdptmp = 0x0000 | 0xff00;               //��������1
+  }
+    else
+    {
+        rdptmp = OB_RDP_Level_0 | 0x5500;   //��������0
+    }
+
+    /*Get iwdg value */
+//  if ((uint8_t)(FLASH->OBR & (FLASH_OBR_IWDG_SW)) != RESET)
+//  {
+//      rdptmp |= 0x0f0000 | 0xf0000000;//HW iwdg
+//  }
+//  else
+    {
+        rdptmp |= 0x0e0000 | 0xf1000000;//sw iwdg
+    }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to erase the option bytes */
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+
+      /* Restore the last read protection Option Byte value */
+      OB->USER_RDP = rdptmp;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else
+    {
+      if (status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+  }
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_WRP: specifies the address of the pages to be write protected.
+  *          This parameter can be:
+  *             @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
+  *             @arg OB_WRP_AllPages
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+    uint8_t WRP0_Data = 0xFF,WRP1_Data = 0xFF,WRP2_Data = 0xFF,WRP3_Data = 0xFF;
+    uint8_t nWRP0_Data = 0,nWRP1_Data = 0,nWRP2_Data = 0,nWRP3_Data = 0;
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+
+  OB_WRP = (uint32_t)(~OB_WRP);
+  WRP0_Data = (uint8_t)(OB_WRP & OB_WRP0_WRP0);
+    nWRP0_Data = ~WRP0_Data;
+
+  WRP1_Data = (uint8_t)((OB_WRP >> 8) & OB_WRP0_WRP0);
+    nWRP1_Data = ~WRP1_Data;
+
+  WRP2_Data = (uint8_t)((OB_WRP >> 16) & OB_WRP0_WRP0);
+    nWRP2_Data = ~WRP2_Data;
+
+  WRP3_Data = (uint8_t)((OB_WRP >> 24) & OB_WRP0_WRP0);
+  nWRP3_Data = ~WRP3_Data;
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+   if((WRP0_Data != 0xFF) ||(WRP1_Data != 0xFF))
+    {
+      OB->WRP1_WRP0 = (WRP0_Data) | (nWRP0_Data<<8) | (WRP1_Data<<16) | (nWRP1_Data<<24);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+   if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+    {
+      OB->WRP3_WRP2  = (WRP2_Data) | (nWRP2_Data<<8) | (WRP3_Data<<16) | (nWRP3_Data<<24);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the write protection operation Status */
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  FLASH_ReadProtection_Level: specifies the read protection level.
+  *          This parameter can be:
+  *             @arg OB_RDP_Level_0: No protection
+  *             @arg OB_RDP_Level_1: Read protection of the memory
+  *             @arg
+  * @note   When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  uint32_t ob_user_rdp = 0;
+    uint16_t ob_rdp_nrdp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP(OB_RDP));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user_rdp = OB->USER_RDP & 0xffff0000;
+    ob_rdp_nrdp = OB_RDP;
+    OB_RDP = ~OB_RDP;
+    ob_rdp_nrdp |= OB_RDP<<8;
+  ob_user_rdp |= ob_rdp_nrdp;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+
+      OB->USER_RDP = ob_user_rdp;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTER Bit */
+        FLASH->CR &= ~FLASH_CR_OPTER;
+      }
+    }
+  }
+  /* Return the protection operation Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_IWDG: Selects the WDG mode
+  *          This parameter can be one of the following values:
+  *             @arg OB_IWDG_SW: Software WDG selected
+  *             @arg OB_IWDG_HW: Hardware WDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *             @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *          This parameter can be one of the following values:
+  *             @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *             @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+    uint32_t ob_user_rdp = 0;
+    uint8_t ob_user = 0,ob_nuser = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user = OB->USER_RDP >>16 & 0xF8;//Clear
+    ob_user |= OB_IWDG | OB_STOP | OB_STDBY;
+    ob_nuser = ~ob_user;
+
+    ob_user_rdp = (OB->USER_RDP &0x0000ffff) |  ob_user<<16 | ob_nuser<<24;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->USER_RDP = ob_user_rdp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* If the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+    }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT1 option bit.
+  * @param  OB_BOOT1: Set or Reset the BOOT1 option bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_BOOT1_RESET: BOOT1 option bit reset
+  *             @arg OB_BOOT1_SET: BOOT1 option bit set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+    uint32_t ob_user_rdp = 0;
+    uint8_t ob_user =0,ob_nuser = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user = OB->USER_RDP >>16 & 0xef;//Clear
+    ob_user |= OB_BOOT1;
+    ob_nuser = ~ob_user;
+  ob_user_rdp = (OB->USER_RDP &0x0000ffff) |  ob_user<<16 | ob_nuser<<24;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->USER_RDP = ob_user_rdp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* If the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+    }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the analogue monitoring on VDDA Power source.
+  * @param  OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+  *          This parameter can be one of the following values:
+  *             @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+  *             @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+  * @retval None
+  */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+    uint32_t ob_user_rdp = 0;
+    uint8_t ob_user = 0,ob_nuser = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user = OB->USER_RDP >>16 & 0xdf;//Clear
+    ob_user |= OB_VDDA_ANALOG;
+    ob_nuser = ~ob_user;
+  ob_user_rdp = (OB->USER_RDP &0x0000ffff) |  ob_user<<16 | ob_nuser<<24;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->USER_RDP = ob_user_rdp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+    }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the SRAM parity.
+  * @param  OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
+  *          This parameter can be one of the following values:
+  *             @arg OB_SRAM_PARITY_SET: Set SRAM parity.
+  *             @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
+  * @retval None
+  */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+    uint32_t ob_user_rdp = 0;
+    uint8_t ob_user = 0,ob_nuser = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user = OB->USER_RDP >>16 & 0xbf;//Clear
+    ob_user |= OB_SRAM_Parity;
+    ob_nuser = ~ob_user;
+  ob_user_rdp = (OB->USER_RDP &0x0000ffff) |  ob_user<<16 | ob_nuser<<24;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->USER_RDP = ob_user_rdp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+    }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
+  *         BOOT1 and VDDA ANALOG monitoring.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  OB_USER: Selects all user option bytes
+  *          This parameter is a combination of the following values:
+  *             @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+  *             @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+  *             @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+  *             @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+  *             @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
+  *             @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET
+  *             @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set
+  *             @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+    uint32_t ob_user_rdp = 0;
+    uint8_t ob_user = 0,ob_nuser = 0;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    ob_user = OB->USER_RDP >>16 & 0x00;//Clear
+    ob_user |= OB_USER;
+    ob_nuser = ~ob_user;
+  ob_user_rdp = (OB->USER_RDP &0x0000ffff) |  ob_user<<16 | ob_nuser<<24;
+
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= FLASH_CR_OPTPG;
+
+            OB->USER_RDP = ob_user_rdp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                /* If the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= ~FLASH_CR_OPTPG;
+            }
+        }
+    }
+  /* Return the Option Byte program Status */
+  return status;
+
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option
+  *         bytes (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  *          This parameter can be 0x1FFFF804.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Enables the Option Bytes Programming operation */
+        FLASH->CR |= FLASH_CR_OPTPG;
+        *(__IO uint32_t*)Address = Data;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+        if(status != FLASH_TIMEOUT)
+        {
+            /* If the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= ~FLASH_CR_OPTPG;
+        }
+    }
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+#endif
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval The FLASH User Option Bytes .
+  */
+uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return (uint8_t)(FLASH->OBR >> 8);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value
+  */
+uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+
+  if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
+  {
+    readstatus = SET;
+  }
+  else
+  {
+    readstatus = RESET;
+  }
+  return readstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or
+  *         disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+  *             @arg FLASH_IT_ERR: FLASH Error Interrupt
+  * @retval None
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status FLASHstatus = FLASH_COMPLETE;
+
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+  {
+    FLASHstatus = FLASH_BUSY;
+  }
+  else
+  {
+    if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+    {
+      FLASHstatus = FLASH_ERROR_WRP;
+    }
+    else
+    {
+      if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
+      {
+        FLASHstatus = FLASH_ERROR_PROGRAM;
+      }
+      else
+      {
+        FLASHstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the FLASH Status */
+  return FLASHstatus;
+}
+
+
+/**
+  * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY,
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check for the FLASH Status */
+  status = FLASH_GetStatus();
+
+  /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetStatus();
+    Timeout--;
+  }
+
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_gpio.c

@@ -0,0 +1,423 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_gpio.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the GPIO peripheral:
+  *                 + Initialization and Configuration functions
+  *                 + GPIO Read and Write functions
+  *                 + GPIO Alternate functions configuration functions
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_gpio.h"
+#include "ft32f0xx_rcc.h"
+
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset
+  *         values.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if(GPIOx == GPIOA)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+  }
+  else if(GPIOx == GPIOB)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+  }
+  else if(GPIOx == GPIOC)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+  }
+  else if(GPIOx == GPIOD)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+  }
+//  else if(GPIOx == GPIOE)
+//  {
+//    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+//    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+//  }
+  else
+  {
+    if(GPIOx == GPIOF)
+    {
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /*-------------------------- Configure the port pins -----------------------*/
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration */
+        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      /* Pull-up Pull down resistor configuration */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next device reset.
+  * @param  GPIOx: where x can be (A or B) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+
+  * @param  GPIO_Pin: specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval The input port pin value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enumeration values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *          This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE
+  *          and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF.
+  * @param  GPIO_AF: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following value:
+  *            @arg GPIO_AF_0:  WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK,
+  *                             TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4,
+  *                             CAN, USART2, CRS, TIM16, TIM1, TS, USART8
+  *            @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1,
+  *                            I2C2, TIM15, SPI2, USART3, TS, SPI1, USART7, USART8
+  *                            USART5, USART4, USART6, I2C1
+  *            @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB, USART6, USART5,
+  *                            USART8, USART7, USART6
+  *            @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT
+  *            @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN, I2C1, USART5
+  *            @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2, USART6, MCO
+  *            @arg GPIO_AF_6: EVENTOUT
+  *            @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT
+  * @note   The pin should already been configured in Alternate Function mode(AF)
+  *         using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  * @note   Refer to the Alternate function mapping table in the device datasheet
+  *         for the detailed mapping of the system and peripherals'alternate
+  *         function I/O pins.
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+    *   @param  GPIOx:GPIOA,GPIOB
+    *                   GPIO_LEDMx:
+    *                                       GPIO_LEDM_0
+    *                           GPIO_LEDM_1
+    *                           GPIO_LEDM_3
+    *                           GPIO_LEDM_4
+    *                           GPIO_LEDM_5
+    *                           GPIO_LEDM_6
+    *                           GPIO_LEDM_7
+    *                           GPIO_LEDM_8
+    *                           GPIO_LEDM_9
+    *                           GPIO_LEDM_10
+    *                           GPIO_LEDM_13
+    *                           GPIO_LEDM_14
+    *                           GPIO_LEDM_15
+    */
+void GPIO_LedmConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_LEDMx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+    assert_param(IS_GPIO_LEDM(GPIO_LEDMx));
+
+    GPIOx->LEDM |= (uint16_t)GPIO_LEDMx;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_i2c.c

@@ -0,0 +1,1256 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_i2c.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Inter-Integrated circuit (I2C):
+  *                 + Initialization and Configuration
+  *                 + Communications handling
+  *                 + SMBUS management
+  *                 + I2C registers management
+  *                 + Data transfers management
+  *                 + DMA transfers management
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_i2c.h"
+#include "ft32f0xx_rcc.h"
+
+
+
+#define CR1_CLEAR_MASK          ((uint32_t)0x00CFE0FF)  /*<! I2C CR1 clear register Mask */
+#define CR2_CLEAR_MASK          ((uint32_t)0x07FF7FFF)  /*<! I2C CR2 clear register Mask */
+#define TIMING_CLEAR_MASK       ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
+#define ERROR_IT_MASK           ((uint32_t)0x00003F00)  /*<! I2C Error interrupt register Mask */
+#define TC_IT_MASK              ((uint32_t)0x000000C0)  /*<! I2C TC interrupt register Mask */
+
+
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
+  assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+  /* Disable I2Cx Peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear I2Cx CR1 register */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: analog and digital filter */
+  /* Set ANFOFF bit according to I2C_AnalogFilter value */
+  /* Set DFN bits according to I2C_DigitalFilter value */
+  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+  /*---------------------------- I2Cx TIMING Configuration -------------------*/
+  /* Configure I2Cx: Timing */
+  /* Set TIMINGR bits according to I2C_Timing */
+  /* Write to I2Cx TIMING */
+  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+  /* Enable I2Cx Peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Clear tmpreg local variable */
+  tmpreg = 0;
+  /* Clear OAR1 register */
+  I2Cx->OAR1 = (uint32_t)tmpreg;
+  /* Clear OAR2 register */
+  I2Cx->OAR2 = (uint32_t)tmpreg;
+  /* Configure I2Cx: Own Address1 and acknowledged address */
+  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+  /* Set OA1 bits according to I2C_OwnAddress1 value */
+  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+                      (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+  /* Write to I2Cx OAR1 */
+  I2Cx->OAR1 = tmpreg;
+  /* Enable Own Address1 acknowledgement */
+  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+  /*---------------------------- I2Cx MODE Configuration ---------------------*/
+  /* Configure I2Cx: mode */
+  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+  tmpreg = I2C_InitStruct->I2C_Mode;
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 |= tmpreg;
+
+  /*---------------------------- I2Cx ACK Configuration ----------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear I2Cx CR2 register */
+  tmpreg &= CR2_CLEAR_MASK;
+  /* Configure I2Cx: acknowledgement */
+  /* Set NACK bit according to I2C_Ack value */
+  tmpreg |= I2C_InitStruct->I2C_Ack;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+  /*---------------- Reset I2C init structure parameters values --------------*/
+  /* Initialize the I2C_Timing member */
+  I2C_InitStruct->I2C_Timing = 0;
+  /* Initialize the I2C_AnalogFilter member */
+  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  /* Initialize the I2C_DigitalFilter member */
+  I2C_InitStruct->I2C_DigitalFilter = 0;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Disable peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /* Perform a dummy read to delay the disable of peripheral for minimum
+     3 APB clock cycles to perform the software reset functionality */
+  *(__IO uint32_t *)(uint32_t)I2Cx;
+
+  /* Enable peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ERRI: Error interrupt mask
+  *            @arg I2C_IT_TCI: Transfer Complete interrupt mask
+  *            @arg I2C_IT_STOPI: Stop Detection interrupt mask
+  *            @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+  *            @arg I2C_IT_ADDRI: Address Match interrupt mask
+  *            @arg I2C_IT_RXI: RX interrupt mask
+  *            @arg I2C_IT_TXI: TX interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR1 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable clock stretching */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
+  }
+  else
+  {
+    /* Disable clock stretching  */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C own address 2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C own address 2.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable own address 2 */
+    I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+  }
+  else
+  {
+    /* Disable own address 2 */
+    I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+  }
+}
+
+/**
+  * @brief  Configures the I2C slave own address 2 and mask.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Mask: specifies own address 2 mask to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_OA2_NoMask: no mask.
+  *            @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+  *            @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+  * @retval None
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_OWN_ADDRESS2(Address));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0]  */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+            (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the I2C general call mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C general call mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable general call mode */
+    I2Cx->CR1 |= I2C_CR1_GCEN;
+  }
+  else
+  {
+    /* Disable general call mode */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C slave byte control.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C slave byte control.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable slave byte control */
+    I2Cx->CR1 |= I2C_CR1_SBC;
+  }
+  else
+  {
+    /* Disable slave byte control */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+  }
+}
+
+/**
+  * @brief  Configures the slave address to be transmitted after start generation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx SADD bit [9:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the I2C 10-bit addressing mode for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit addressing mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit addressing mode */
+    I2Cx->CR2 |= I2C_CR2_ADD10;
+  }
+  else
+  {
+    /* Disable 10-bit addressing mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  Enables or disables the I2C automatic end mode (stop condition is
+  *         automatically sent when nbytes data are transferred).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C automatic end mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has effect if Reload mode is disabled.
+  * @retval None
+  */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto end mode */
+    I2Cx->CR2 |= I2C_CR2_AUTOEND;
+  }
+  else
+  {
+    /* Disable Auto end mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C nbytes reload mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the nbytes reload mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto Reload mode */
+    I2Cx->CR2 |= I2C_CR2_RELOAD;
+  }
+  else
+  {
+    /* Disable Auto Reload mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+  }
+}
+
+/**
+  * @brief  Configures the number of bytes to be transmitted/received.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  * @retval None
+  */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx Nbytes bit [7:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+  /* Set I2Cx Nbytes */
+  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the type of transfer request for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Direction: specifies the transfer request direction to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Direction_Transmitter: Master request a write transfer
+  *            @arg I2C_Direction_Receiver: Master request a read transfer
+  * @retval None
+  */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction == I2C_Direction_Transmitter)
+  {
+    /* Request a write Transfer */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+  }
+  else
+  {
+    /* Request a read Transfer */
+    I2Cx->CR2 |= I2C_CR2_RD_WRN;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR2 |= I2C_CR2_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR2 |= I2C_CR2_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C 10-bit header only mode with read direction.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit header only mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This mode can be used only when switching from master transmitter mode
+  *         to master receiver mode.
+  * @retval None
+  */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit header only mode */
+    I2Cx->CR2 |= I2C_CR2_HEAD10R;
+  }
+  else
+  {
+    /* Disable 10-bit header only mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+  }
+}
+
+/**
+  * @brief  Generates I2C communication Acknowledge.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the Acknowledge.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable ACK generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
+  }
+  else
+  {
+    /* Enable NACK generation */
+    I2Cx->CR2 |= I2C_CR2_NACK;
+  }
+}
+
+/**
+  * @brief  Returns the I2C slave matched address .
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the slave matched address .
+  */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+  * @brief  Returns the I2C slave received request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received request.
+  */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+  uint32_t tmpreg = 0;
+  uint16_t direction = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Return the slave matched address in the SR1 register */
+  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+
+  /* If write transfer is requested */
+  if (tmpreg == 0)
+  {
+    /* write transfer is requested */
+    direction = I2C_Direction_Transmitter;
+  }
+  else
+  {
+    /* Read transfer is requested */
+    direction = I2C_Direction_Receiver;
+  }
+  return direction;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  *          This parameter must be a value between 0 and 255.
+  * @param  ReloadEndMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Reload_Mode: Enable Reload mode .
+  *            @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+  *            @arg I2C_SoftEnd_Mode: Enable Software end mode.
+  * @param  StartStopMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_No_StartStop: Don't Generate stop and start condition.
+  *            @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+  *            @arg I2C_Generate_Start_Read: Generate Restart for read request.
+  *            @arg I2C_Generate_Start_Write: Generate Restart for write request.
+  * @retval None
+  */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+  assert_param(IS_START_STOP_MODE(StartStopMode));
+
+  /* Get the CR2 register value */
+  tmpreg = I2Cx->CR2;
+
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+            (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+
+  /* update CR2 register */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables I2C SMBus alert.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx SMBus alert.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable SMBus alert */
+    I2Cx->CR1 |= I2C_CR1_ALERTEN;
+  }
+  else
+  {
+    /* Disable SMBus alert */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Clock Timeout (SCL Timeout detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
+  }
+  else
+  {
+    /* Disable Clock Timeout */
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Extended clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
+  }
+  else
+  {
+    /* Disable Clock Timeout */
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
+  *         high detection).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Idle clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
+  }
+  else
+  {
+    /* Disable Clock Timeout */
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
+  }
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
+  *         idle SCL and SDA high when TIDLE = 1).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutA to be programmed.
+  * @retval None
+  */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTA bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+  /* Set I2Cx TIMEOUTA */
+  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutB to be programmed.
+  * @retval None
+  */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTB bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+  /* Set I2Cx TIMEOUTB */
+  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables I2C PEC calculation.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_PECEN;
+  }
+  else
+  {
+    /* Disable PEC calculation */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C PEC transmission/reception request.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC transmission/reception request */
+    I2Cx->CR2 |= I2C_CR2_PECBYTE;
+  }
+  else
+  {
+    /* Disable PEC transmission/reception request */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
+  }
+}
+
+/**
+  * @brief  Returns the I2C PEC.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @retval The value of the PEC .
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_1_PERIPH(I2Cx));
+
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+  * @}
+  */
+
+
+
+  /**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Register: specifies the register to read.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Register_CR1: CR1 register.
+  *            @arg I2C_Register_CR2: CR2 register.
+  *            @arg I2C_Register_OAR1: OAR1 register.
+  *            @arg I2C_Register_OAR2: OAR2 register.
+  *            @arg I2C_Register_TIMINGR: TIMING register.
+  *            @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+  *            @arg I2C_Register_ISR: ISR register.
+  *            @arg I2C_Register_ICR: ICR register.
+  *            @arg I2C_Register_PECR: PECR register.
+  *            @arg I2C_Register_RXDR: RXDR register.
+  *            @arg I2C_Register_TXDR: TXDR register.
+  * @retval The value of the read register.
+  */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t)I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Write in the DR register the data to be sent */
+  I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->RXDR;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables the I2C DMA interface.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_DMAReq_Tx: Tx DMA transfer request
+  *            @arg I2C_DMAReq_Rx: Rx DMA transfer request
+  * @param  NewState: new state of the selected I2C DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR1 |= I2C_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+  }
+}
+/**
+  * @}
+  */
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_FLAG_TXE: Transmit data register empty
+  *            @arg I2C_FLAG_TXIS: Transmit interrupt status
+  *            @arg I2C_FLAG_RXNE: Receive data register not empty
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_TC: Transfer complete (master mode)
+  *            @arg I2C_FLAG_TCR: Transfer complete reload
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  *            @arg I2C_FLAG_BUSY: Bus busy
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t tmpreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+
+  /* Get flag status */
+  tmpreg &= I2C_FLAG;
+
+  if(tmpreg != 0)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_TXIS: Transmit interrupt status
+  *            @arg I2C_IT_RXNE: Receive data register not empty
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_TC: Transfer complete (master mode)
+  *            @arg I2C_IT_TCR: Transfer complete reload
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t tmpreg = 0;
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  /* If Error interrupt */
+  if ((uint32_t)(I2C_IT & ERROR_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+  }
+  /* If TC interrupt */
+  else if ((uint32_t)(I2C_IT & TC_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+  }
+  else
+  {
+    enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+  }
+
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+
+  /* Get flag status */
+  tmpreg &= I2C_IT;
+
+  /* Check the status of the specified I2C flag */
+  if((tmpreg != RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_iwdg.c

@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_iwdg.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Independent watchdog (IWDG) peripheral:
+  *                 + Prescaler and Counter configuration
+  *                 + IWDG activation
+  *                 + Flag management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_iwdg.h"
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *          This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+
+/**
+  * @brief  Sets the IWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  * @retval None
+  */
+void IWDG_SetWindowValue(uint16_t WindowValue)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
+  IWDG->WINR = WindowValue;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function
+ *
+@verbatim
+ ==============================================================================
+                          ##### IWDG activation function #####
+ ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
+  *            @arg IWDG_FLAG_WVU: Counter Window Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_misc.c

@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_misc.c
+  * @author             FMD AE
+  * @brief              This file provides all the miscellaneous firmware functions (add-on
+  *                     to CMSIS functions).
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_misc.h"
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));
+
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/
+    tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
+    tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
+    tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));
+
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
+
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *          This parameter can be one of the following values:
+  *            @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *            @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *            @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *            @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *            @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_opa.c

@@ -0,0 +1,360 @@
+/**
+  ******************************************************************************
+  * @file    			ft32f0xx_opa.c
+  * @author  			FMD AE
+  * @brief   			This file provides firmware functions to manage the following 
+  *          			functionalities of the comparators (OPA1 and OPA2) peripheral
+  *          			applicable only on FT32F030 devices: 
+  *           		+ Comparators configuration
+  *           		+ Window mode control
+  * @version 			V1.0.0           
+  * @data		 			2021-07-01
+	******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_comp.h"
+#include "ft32f0xx_opa.h"
+
+/* CSR register Mask */
+#define OPA_CR_CLEAR_MASK              ((uint32_t)0x0003FFC1)
+
+/* Clear PRMAP BIT*/
+#define	OPA_OP2_CLEAR_PRMAP				((uint32_t)0x00020000)         
+
+/**
+  * @brief  Deinitializes OPA peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the OPA configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAx: the selected comparator. 
+  *         This parameter can be one of the following values:
+  *         @arg OPA:  OPA1 selected
+  *         @arg OPA2: OPA2 selected
+  * @retval None
+  */
+void OPA_DeInit(OPA_TypeDef* OPAx)
+{
+    /* Check the parameters */
+    assert_param(IS_OPA_ALL_PERIPH(OPAx)); 
+	
+    OPAx->CR = ((uint32_t)0x00000000);    /*!< Set OPA_CSR register to reset value */
+}
+
+/**
+  * @brief  Initializes the OPA peripheral according to the specified parameters
+  *         in OPA_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   To correctly run this function, the OPA_Cali() function must be called before.       
+  * @param  OPAx: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg OPA:  OPA1 selected
+  *            @arg OPA2: OPA2 selected
+  * @param  OPA_InitStruct: pointer to an OPA_InitTypeDef structure that contains 
+  *         the configuration information for the specified OPA peripheral.
+  * @retval None
+  */
+void OPA_Init(OPA_TypeDef* OPAx, OPA_InitTypeDef* OPA_InitStruct)
+{
+	uint32_t tmpreg = 0;
+
+	/* Check the parameters */
+	assert_param(IS_OPA_VIP_SEL(OPA_InitStruct->OPA_OP0PSel));
+	assert_param(IS_OPA_VIN_SEL(OPA_InitStruct->OPA_OP0NSel));
+	assert_param(IS_OPA_FR_SEL(OPA_InitStruct->OPA_OP0FR));
+	assert_param(IS_OPA_FCAP_SEL(OPA_InitStruct->OPA_OP0FCAPE));
+	assert_param(IS_OPA_ODIG_SEL(OPA_InitStruct->OPA_OPTODIG));
+	assert_param(IS_OPA_OIO_SEL(OPA_InitStruct->OPA_OPTOIO));
+
+	/*!< Get the OPA_CR register value */
+	tmpreg = OPAx->CR;
+
+	/*!< Clear the bits */ 
+	tmpreg &= (uint32_t) ~(OPA_CR_CLEAR_MASK);
+
+	/*!< Configure OPA: OPA_VipSel, OPA_VinSel, OPA_OutputSel value and OPA_Pol */
+	tmpreg |= (uint32_t)((OPA_InitStruct->OPA_OP0PSel | OPA_InitStruct->OPA_OP0NSel|
+					   OPA_InitStruct->OPA_OP0FR | OPA_InitStruct->OPA_OP0FCAPE | OPA_InitStruct->OPA_OPTODIG |OPA_InitStruct->OPA_OPTOIO));
+
+	/*!< Write to OPA_CR register */
+	OPAx->CR = tmpreg;  
+}
+
+/**
+  * @brief  Fills each OPA_InitStruct member with its default value.
+  * @param  OPA_InitStruct: pointer to an OPA_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct)
+{
+	OPA_InitStruct->OPA_OP0PSel = 0x00000000;
+	OPA_InitStruct->OPA_OP0NSel = 0x00002000;
+	OPA_InitStruct->OPA_OP0FR = 0x00000000;
+	OPA_InitStruct->OPA_OP0FCAPE = 0x00000000;
+	OPA_InitStruct->OPA_OPTODIG = 0x00000080;
+	OPA_InitStruct->OPA_OPTOIO = 0x00000040;
+}
+
+/**
+  * @brief  Enable or disable the OPA peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAx: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg OPA: OPA1 selected
+  *            @arg OPA2: OPA2 selected
+  * @param  NewState: new state of the OPA peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with 
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the 
+  *         output level is low.
+  * @retval None
+  */
+void OPA_Cmd(OPA_TypeDef* OPAx, FunctionalState NewState)
+{
+	/* Check the parameters */
+	assert_param(IS_OPA_ALL_PERIPH(OPAx));
+	assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+	if (NewState != DISABLE)
+	{
+		/* Enable the selected OPA peripheral */
+		OPAx->CR |= OPA_OP1_ON;
+	}
+	else
+	{
+		/* Disable the selected OPA peripheral  */
+		OPAx->CR &= ~OPA_OP1_ON;
+	}
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  OPAx: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg OPA:  OPA1 selected
+  *            @arg OPA2: OPA2 selected  
+  * @param  OPA_OutLevel:  
+  *          This parameter can be one of the following values:
+  *            @arg OPA_OutputLevel_High
+  *            @arg OPA_OutputLevel_Low   
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t OPA_GetOutputLevel(OPA_TypeDef* OPAx, uint32_t OPA_OutLevel)
+{
+	uint32_t compout = 0x0;
+
+	/* Check the parameters */
+	assert_param(IS_OPA_ALL_PERIPH(OPAx));
+	assert_param(IS_OPA_OUTPUT_LEVEL(OPA_OutLevel));
+
+	/* Check if selected comparator output is high */
+	if ((OPAx->CR & OPA_OutLevel) != 0)
+	{
+		compout = OPA_OutLevel;
+	}
+	else
+	{
+		compout = OPA_OutputLevel_Low;
+	}
+
+	/* Return the comparator output level */
+	return (uint32_t)(compout);
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @param  OPAx: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg OPA:  OPA1 selected
+  *            @arg OPA2: OPA2 selected 
+  * @retval Returns:	0：fail		others：The calibration value 
+  *       
+  */
+uint8_t OPA_Cali(OPA_TypeDef* OPAx)
+{
+	uint32_t    opadelay;
+	uint32_t    outstate;
+	uint8_t  	CalDA, CalDB;
+	uint32_t	opatmp32;
+	uint32_t	delay_time = 0x1fff;
+	
+	/* Check the parameters */
+	assert_param(IS_OPA_ALL_PERIPH(OPAx));
+  
+	/* Enable the selected OPA peripheral */
+	OPAx->CR |= OPA_OP1_ON;
+
+	/* Enable OP0TM */
+	OPAx->CR |= OPA_OP1_TM;
+
+	/* OP0NSEL = 00   ,  SET TO GND */
+	OPAx->CR &= ~OPA_OP1_NSEL;
+
+	/* OP0PSEL = 1   ,  SET TO GND */
+	OPAx->CR |= OPA_OP1_PSEL;
+
+	/* OP0FCAPE = 0 */
+	OPAx->CR &= ~OPA_OP1_FCAPE;
+
+	/* OPTODIG = 1 */
+	OPAx->CR |= OPA_OP1_TODIG;
+
+	/* OP0FR = 000 */
+	OPAx->CR &= ~OPA_OP1_FR;
+
+	if (OPAx == OPA)
+	{
+		/* PA2 TO FLOAT */
+		GPIOA ->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint32_t)2 * 2));	
+	}
+	else
+	{
+		/* Clear PRMAP */
+		OPAx->CR &= (~OPA_OP2_CLEAR_PRMAP);
+		
+		/* PF4 TO FLOAT */
+		GPIOF ->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint32_t)4 * 2));			
+	}
+
+	#if defined (FT32F072xB)
+		/* OP0COF = 00000 */
+		OPAx->CR &= ~OPA_OP1_COF;
+		CalDA = 0;
+		opadelay = delay_time;
+		while(opadelay--);			
+		outstate = OPAx->CR;		// save
+		
+		for(;;)
+		{
+			CalDA++;
+			if(CalDA >= 0x1F) 
+			return 0;				//fail
+		
+			opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+			OPAx->CR = opatmp32 | (CalDA << 1);
+			opadelay = delay_time;
+			while(opadelay--);
+			
+			if( (outstate ^ OPAx->CR) & OPA_OP1_OUT) 
+			break;
+		}
+
+		OPAx->CR |= OPA_OP1_COF;		//0x1F
+		CalDB = 0x1F;
+		opadelay = delay_time;
+		while(opadelay--);		
+		outstate = OPAx->CR;		// save
+		
+		for(;;)
+		{
+			if(0 == CalDB) 
+			return 0;
+		
+			CalDB--;
+			opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+			OPAx->CR = opatmp32 | (CalDB << 1);
+			opadelay = delay_time;
+			while(opadelay--);
+			
+			if( (outstate ^ OPAx->CR) & OPA_OP1_OUT ) 
+			break;
+		}
+
+		CalDA+= CalDB;
+		CalDA/= 2;
+		opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+		OPAx->CR = opatmp32 | (CalDA << 1);	
+	#else
+		/* OP0COF = 10000 */
+		OPAx->CR &= ~OPA_OP1_COF;
+		OPAx->CR |= OPA_OP1_COF_4;
+		CalDA = 0;
+		opadelay = delay_time;
+		while(opadelay--);
+		outstate = OPAx->CR;		// save
+		
+		for(;;)
+		{
+			CalDA++;
+			if(CalDA >= 0x0F) 
+			return 0;
+		
+			opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+			OPAx->CR = opatmp32 | (CalDA << 1);
+			opadelay = delay_time;
+			while(opadelay--);
+			
+			if((outstate^OPAx->CR) & OPA_OP1_OUT) 
+			break;
+		}
+		
+		OPAx->CR &= ~OPA_OP1_COF;		
+		OPAx->CR |= OPA_OP1_COF_0 | OPA_OP1_COF_1 | OPA_OP1_COF_2 | OPA_OP1_COF_3;	//0x0F
+		CalDB = 0x0F;
+		opadelay = delay_time;
+		while(opadelay--);		
+		outstate = OPAx->CR;		// save
+
+		for(;;)
+		{
+			if(0 == CalDB) 
+			return 0;
+		
+			CalDB--;
+			opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+			OPAx->CR = opatmp32 | (CalDB << 1);
+			opadelay = delay_time;
+			while(opadelay--);
+			
+			if( (outstate^OPAx->CR) & OPA_OP1_OUT ) 
+			break;
+		}
+
+		CalDA+= CalDB;
+		CalDA/= 2;
+		opatmp32 = OPAx->CR & (~OPA_OP1_COF);
+		OPAx->CR = opatmp32 | (CalDA << 1);			
+	#endif
+
+	return CalDA;
+}
+
+
+
+
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_pwr.c

@@ -0,0 +1,366 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_pwr.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Power Controller (PWR) peripheral:
+  *                 + Backup Domain Access
+  *                 + PVD configuration
+  *                 + WakeUp pins configuration
+  *                 + Low Power modes configuration
+  *                 + Flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_pwr.h"
+#include "ft32f0xx_rcc.h"
+
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFD1F)
+
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the Backup domain registers.
+  * @note   If the HSE divided by 32 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the Backup domain registers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Backup Domain Access */
+    PWR->CR |= PWR_CR_DBP;
+  }
+  else
+  {
+    /* Disable the Backup Domain Access */
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *             @arg PWR_PVDLevel_0
+  *             @arg PWR_PVDLevel_1
+  *             @arg PWR_PVDLevel_2
+  *             @arg PWR_PVDLevel_3
+  *             @arg PWR_PVDLevel_4
+  *             @arg PWR_PVDLevel_5
+  *             @arg PWR_PVDLevel_6
+  *             @arg PWR_PVDLevel_7
+  *             @arg PWR_PVDLevel_8
+  *             @arg PWR_PVDLevel_9
+  *             @arg PWR_PVDLevel_10
+  *             @arg PWR_PVDLevel_11
+  *             @arg PWR_PVDLevel_12
+  *             @arg PWR_PVDLevel_13
+  *             @arg PWR_PVDLevel_14
+  *             @arg PWR_PVDLevel_15
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+
+  tmpreg = PWR->CR;
+
+  /* Clear PLS[7:5] bits  PLS3*/
+  tmpreg &= CR_PLS_MASK;
+
+  /* Set PLS[7:5] and PLS3 bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PVD */
+    PWR->CR |= PWR_CR_PVDE;
+  }
+  else
+  {
+    /* Disable the PVD */
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
+  *          This parameter can be one of the following values
+  *             @arg PWR_WakeUpPin_1
+  *             @arg PWR_WakeUpPin_2
+  *             @arg PWR_WakeUpPin_3
+  *             @arg PWR_WakeUpPin_4
+  *             @arg PWR_WakeUpPin_5
+  *             @arg PWR_WakeUpPin_6
+  *             @arg PWR_WakeUpPin_7
+  *             @arg PWR_WakeUpPin_8
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the EWUPx pin */
+    PWR->CSR |= PWR_WakeUpPin;
+  }
+  else
+  {
+    /* Disable the EWUPx pin */
+    PWR->CSR &= ~PWR_WakeUpPin;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional
+  *         startup delay is incurred when waking up from Stop mode.
+  *         By keeping the internal regulator ON during Stop mode, the consumption
+  *         is higher although the startup time is reduced.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *             @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *             @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+                @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+
+  /* Store the new value */
+  PWR->CR = tmpreg;
+
+  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
+    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  }
+  else if (PWR_STOPEntry == PWR_STOPEntry_WFE)
+  {
+    /* Request Wait For Event */
+    __WFE();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
+    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  }
+  else
+  {
+    /* Set SLEEP on exit bit of Cortex-M0 System Control Register */
+    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+  }
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available)
+  *          - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
+  *             time-stamp, RTC Alarm out, or RTC clock calibration out.
+  *          - WKUP pin 1 (PA0) if enabled.
+  * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+
+  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
+  *                  event was received from the WKUP pin or from the RTC alarm
+  *                  (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
+  *             @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the
+  *                  system was resumed from StandBy mode.
+  *             @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
+  *                  is enabled by the PWR_PVDCmd() function.
+  *             @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag.
+  *                  This flag indicates the state of the internal voltage
+  *                  reference, VREFINT.
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_FLAG_WU: Wake Up flag
+  *             @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rcc.c

@@ -0,0 +1,1509 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_rcc.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Reset and clock control (RCC) peripheral:
+  *                     + Internal/external clocks, PLL, CSS and MCO configuration
+  *                     + System, AHB and APB busses clocks configuration
+  *                 + Peripheral clocks configuration
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_rcc.h"
+
+
+/* ---------------------- RCC registers mask -------------------------------- */
+/* RCC Flag Mask */
+#define FLAG_MASK                 ((uint8_t)0x1F)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS          ((uint32_t)0x40021002)
+
+/* CFGR register byte 3 (Bits[31:23]) base address */
+#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x40021007)
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define CIR_BYTE1_ADDRESS         ((uint32_t)0x40021009)
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002100A)
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  * @note      HSI ON and used as system clock source
+  * @note      HSI14, HSE and PLL OFF
+  * @note      AHB, APB prescaler set to 1.
+  * @note      CSS and MCO OFF
+  * @note      All interrupts disabled
+  * @note   However, this function doesn't modify the configuration of the
+  * @note      Peripheral clocks
+  * @note      LSI, LSE and RTC clocks
+  * @param  None
+  * @retval None
+  */
+void RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function resets the CSSON bit, so if the Clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
+  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
+
+  /* Set the new HSE configuration -------------------------------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
+
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @note   This function waits on HSERDY flag to be set and return SUCCESS if
+  *         this flag is set, otherwise returns ERROR if the timeout is reached
+  *         and this flag is not set. The timeout value is defined by the constant
+  *         HSE_STARTUP_TIMEOUT in ft32f0xx.h file. You can tailor it depending
+  *         on the HSE crystal used in your application.
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: HSE oscillator is stable and ready to use
+  *          - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+
+  /* Wait till HSE is ready and if timeout is reached exit */
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  *         Refer to the Application Note AN4067 for more details on how to
+  *         calibrate the HSI.
+  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
+
+  tmpreg = RCC->CR;
+
+  /* Clear HSITRIM[4:0] bits */
+  tmpreg &= ~RCC_CR_HSITRIM;
+
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   After enabling the HSI, the application software should wait on
+  *         HSIRDY flag to be set indicating that HSI clock is stable and can
+  *         be used to clock the PLL and/or system clock.
+  * @note   HSI can not be stopped if it is used directly or through the PLL
+  *         as system clock. In this case, you have to select another source
+  *         of the system clock then stop the HSI.
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_HSION;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_HSION;
+  }
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator for ADC (HSI14)
+  *         calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  *         Refer to the Application Note AN4067  for more details on how to
+  *         calibrate the HSI14.
+  * @param  HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
+  *          This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
+
+  tmpreg = RCC->CR2;
+
+  /* Clear HSI14TRIM[4:0] bits */
+  tmpreg &= ~RCC_CR2_HSI14TRIM;
+
+  /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
+  tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator for ADC (HSI14).
+  * @note   After enabling the HSI14, the application software should wait on
+  *         HSIRDY flag to be set indicating that HSI clock is stable and can
+  *         be used to clock the ADC.
+  * @note   The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI14.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_HSI14Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 |= RCC_CR2_HSI14ON;
+  }
+  else
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI14ON;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator request from ADC.
+  * @param  NewState: new state of the HSI14 ADC request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI14DIS;
+  }
+  else
+  {
+    RCC->CR2 |= RCC_CR2_HSI14DIS;
+  }
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @note   As the LSE is in the Backup domain and write access is denied to this
+  *         domain after reset, you have to enable write access using
+  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
+  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_LSEConfig(uint32_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEON);
+
+  /* Reset LSEBYP bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+
+  /* Configure LSE */
+  RCC->BDCR |= RCC_LSE;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE) drive capability.
+  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
+  * @retval None
+  */
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
+
+  /* Clear LSEDRV[1:0] bits */
+  RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
+
+  /* Set the LSE Drive */
+  RCC->BDCR |= RCC_LSEDrive;
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @param  NewState: new state of the LSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CSR |= RCC_CSR_LSION;
+  }
+  else
+  {
+    RCC->CSR &= ~RCC_CSR_LSION;
+  }
+}
+
+/**
+  * @brief  Configures the PLL clock source and multiplication factor.
+  * @note   This function must be used only when the PLL is disabled.
+  *
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
+  *            @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+  *            @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source,
+  *            @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry
+  * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+  *         PLL source).
+  *
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
+  *          This parameter can be RCC_PLLMul_x where x:[2,16]
+  *
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+  /* Clear PLL Source [16] and Multiplier [21:18] bits */
+  RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
+
+  /* Set the PLL Source and Multiplier */
+  RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
+}
+
+/**
+  * @brief  Enables or disables the PLL.
+  * @note   After enabling the PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The PLL can not be disabled if it is used as system clock source
+  * @note   The PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the PLL.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_PLLON;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_PLLON;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator for USB (HSI48).
+  * @note   After enabling the HSI48, the application software should wait on
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI48.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSI48Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR2 |= RCC_CR2_HSI48ON;
+  }
+  else
+  {
+    RCC->CR2 &= ~RCC_CR2_HSI48ON;
+  }
+}
+
+/**
+  * @brief  Configures the PREDIV1 division factor.
+  * @note   This function must be used only when the PLL is disabled.
+  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+  *          This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+  * @retval None
+  */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PREDIV1[3:0] bits */
+  tmpreg &= ~(RCC_CFGR2_PREDIV1);
+  /* Set the PREDIV1 division factor */
+  tmpreg |= RCC_PREDIV1_Div;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
+  * @param  NewState: new state of the Clock Security System.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->CR |= RCC_CR_CSSON;
+  }
+  else
+  {
+    RCC->CR &= ~RCC_CR_CSSON;
+  }
+}
+/**
+  * @brief  Selects the clock source to output on MCO pin (PA8) and the corresponding
+  *         prescsaler.
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOSource_NoClock: No clock selected.
+  *            @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+  *            @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+  *            @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+  *            @arg RCC_MCOSource_SYSCLK: System clock selected.
+  *            @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+  *            @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+  *            @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+  *            @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+  *            @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+  * @param  RCC_MCOPrescaler: specifies the prescaler on MCO pin.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
+  *            @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
+  *            @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
+  *            @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
+  *            @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
+  *            @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
+  *            @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
+  *            @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
+  * @retval None
+  */
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+  assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
+
+  /* Get CFGR value */
+  tmpreg = RCC->CFGR;
+  /* Clear MCOPRE[2:0] bits */
+  tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+  /* Set the RCC_MCOSource and RCC_MCOPrescaler */
+  tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use RCC_GetSYSCLKSource() function to know which clock is
+  *         currently used as system clock source.
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
+  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSI48:  HSI48 selected as system clock source
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear SW[1:0] bits */
+  tmpreg &= ~RCC_CFGR_SW;
+
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following values:
+  *           - 0x00: HSI used as system clock
+  *           - 0x04: HSE used as system clock
+  *           - 0x08: PLL used as system clock
+  *           - 0x0C: HSI48 used as system clock
+  */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+  *         the system clock (SYSCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
+  *            @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
+  *            @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
+  *            @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
+  *            @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
+  *            @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
+  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear HPRE[3:0] bits */
+  tmpreg &= ~RCC_CFGR_HPRE;
+
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+  tmpreg |= RCC_SYSCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the APB clock (PCLK).
+  * @param  RCC_HCLK: defines the APB clock divider. This clock is derived from
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HCLK_Div1: APB clock = HCLK
+  *            @arg RCC_HCLK_Div2: APB clock = HCLK/2
+  *            @arg RCC_HCLK_Div4: APB clock = HCLK/4
+  *            @arg RCC_HCLK_Div8: APB clock = HCLK/8
+  *            @arg RCC_HCLK_Div16: APB clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLKConfig(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PPRE[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE;
+
+  /* Set PPRE[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADC clock (ADCCLK).
+  * @note   This function is obsolete.
+  *         For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
+  * @param  RCC_ADCCLK: defines the ADC clock source. This clock is derived
+  *         from the HSI14 or APB clock (PCLK).
+  *          This parameter can be one of the following values:
+  *             @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
+  *             @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
+  *             @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
+  * @retval None
+  */
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
+
+  /* Clear ADCPRE bit */
+  RCC->CFGR &= ~RCC_CFGR_ADCPRE;
+  /* Set ADCPRE bits according to RCC_PCLK value */
+  RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
+
+  /* Clear ADCSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
+  /* Set ADCSW bits according to RCC_ADCCLK value */
+  RCC->CFGR3 |= RCC_ADCCLK >> 16;
+}
+
+/**
+  * @brief  Configures the CEC clock (CECCLK).
+  * @param  RCC_CECCLK: defines the CEC clock source. This clock is derived
+  *         from the HSI or LSE clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
+  *             @arg RCC_CECCLK_LSE: CEC clock = LSE
+  * @retval None
+  */
+
+
+/**
+  * @brief  Configures the I2C1 clock (I2C1CLK).
+  * @param  RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
+  *             @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
+  * @retval None
+  */
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
+
+  /* Clear I2CSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
+  /* Set I2CSW bits according to RCC_I2CCLK value */
+  RCC->CFGR3 |= RCC_I2CCLK;
+}
+
+/**
+  * @brief  Configures the USART1 clock (USART1CLK).
+  * @param  RCC_USARTCLK: defines the USART clock source. This clock is derived
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
+  *             @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
+  *             @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
+  *             @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
+  *             @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK)
+  *             @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock
+  *             @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock
+  *             @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock
+  *             @arg RCC_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK)
+  *             @arg RCC_USART3CLK_SYSCLK: USART3 clock = System Clock
+  *             @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock
+  *             @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock
+  * @retval None
+  */
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
+
+  /* Get USART index */
+  tmp = (RCC_USARTCLK >> 28);
+
+  /* Clear USARTSW[1:0] bit */
+  if (tmp == (uint32_t)0x00000001)
+  {
+    /* Clear USART1SW[1:0] bit */
+    RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
+  }
+//  else if (tmp == (uint32_t)0x00000002)
+//  {
+//    /* Clear USART2SW[1:0] bit */
+//    RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
+//  }
+//  else
+//  {
+//    /* Clear USART3SW[1:0] bit */
+//    RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
+//  }
+
+  /* Set USARTxSW bits according to RCC_USARTCLK value */
+  RCC->CFGR3 |= RCC_USARTCLK;
+}
+
+/**
+  * @brief  Configures the USB clock (USBCLK).
+  * @param  RCC_USBCLK: defines the USB clock source. This clock is derived
+  *         from the HSI48 or system clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USBCLK_HSI48: USB clock = HSI48
+  *             @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
+  * @retval None
+  */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_USBCLK(RCC_USBCLK));
+
+  /* Clear USBSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
+  /* Set USBSW bits according to RCC_USBCLK value */
+  RCC->CFGR3 |= RCC_USBCLK;
+}
+
+/**
+  * @brief  Returns the frequencies of the System, AHB and APB busses clocks.
+  * @note    The frequency returned by this function is not the real frequency
+  *           in the chip. It is calculated based on the predefined constant and
+  *           the source selected by RCC_SYSCLKConfig():
+  *
+  * @note     If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
+  *
+  * @note     If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
+  *
+  * @note     If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *
+  * @note     If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
+  *
+  * @note     (*) HSI_VALUE is a constant defined in ft32f0xx.h file (default value
+  *               8 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
+  *
+  * @note     (**) HSE_VALUE is a constant defined in ft32f0xx.h file (default value
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                return wrong result.
+  *
+  * @note     (***) HSI48_VALUE is a constant defined in ft32f0xx.h file (default value
+  *                 48 MHz) but the real value may vary depending on the variations
+  *                 in voltage and temperature.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+  *         the clocks frequencies.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  * @note   Each time SYSCLK, HCLK and/or PCLK clock changes, this function
+  *         must be called to update the structure's field. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  *
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        pllclk = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        pllclk = (HSE_VALUE / prediv1factor) * pllmull;
+      }
+      RCC_Clocks->SYSCLK_Frequency = pllclk;
+      break;
+    case 0x0C:  /* HSI48 used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
+      break;
+    default: /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp];
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+  /* Get PCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE;
+  tmp = tmp >> 8;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK clock frequency */
+  RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+  /* ADCCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
+  {
+    /* ADC Clock is HSI14 Osc. */
+    RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
+  }
+  else
+  {
+    if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
+    {
+      /* ADC Clock is derived from PCLK/2 */
+      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
+    }
+    else
+    {
+      /* ADC Clock is derived from PCLK/4 */
+      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
+    }
+
+  }
+
+  /* CECCLK clock frequency */
+
+
+  /* I2C1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
+  {
+    /* I2C1 Clock is HSI Osc. */
+    RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
+  }
+  else
+  {
+    /* I2C1 Clock is System Clock */
+    RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+
+  /* USART1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
+  {
+    /* USART1 Clock is PCLK */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
+  {
+    /* USART1 Clock is System Clock */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
+  {
+    /* USART1 Clock is LSE Osc. */
+    RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
+  {
+    /* USART1 Clock is HSI Osc. */
+    RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
+  }
+
+  /* USART2CLK clock frequency */
+  RCC_Clocks->USART2CLK_Frequency=RCC_Clocks->PCLK_Frequency;
+    /* USART2CLK clock frequency */
+//  if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
+//  {
+//    /* USART Clock is PCLK */
+//    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
+//  }
+//  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
+//  {
+//    /* USART Clock is System Clock */
+//    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+//  }
+//  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
+//  {
+//    /* USART Clock is LSE Osc. */
+//    RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
+//  }
+//  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
+//  {
+//    /* USART Clock is HSI Osc. */
+//    RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
+//  }
+
+
+  /* USART3CLK clock frequency */
+
+  /* USBCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
+  {
+    /* USB Clock is HSI48 */
+    RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
+  }
+  else
+  {
+    /* USB Clock is PLL clock */
+    RCC_Clocks->USBCLK_Frequency = pllclk;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the RTC
+  *         is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
+  *
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+  *            @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
+  *
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  *
+  * @note   The maximum input clock frequency for RTC is 2MHz (when using HSE as
+  *         RTC clock source).
+  *
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+  /* Select the RTC clock source */
+  RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock source was selected
+  *         using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+  else
+  {
+    RCC->BDCR &= ~RCC_BDCR_RTCEN;
+  }
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @param  NewState: new state of the Backup domain reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->BDCR |= RCC_BDCR_BDRST;
+  }
+  else
+  {
+    RCC->BDCR &= ~RCC_BDCR_BDRST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA: GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB: GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC: GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD: GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE: GPIOE clock
+  *             @arg RCC_AHBPeriph_GPIOF: GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:    TS clock
+  *             @arg RCC_AHBPeriph_CRC:   CRC clock
+  *             @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
+  *             @arg RCC_AHBPeriph_SRAM:  SRAM clock
+  *             @arg RCC_AHBPeriph_DMA1:  DMA1 clock
+  *             @arg RCC_AHBPeriph_DMA2:  DMA2 clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *             @arg RCC_APB2Periph_USART6: USART6 clock
+  *             @arg RCC_APB2Periph_USART7: USART7 clock
+  *             @arg RCC_APB2Periph_USART8: USART8 clock
+  *             @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *             @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *             @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *             @arg RCC_APB2Periph_USART1: USART1 clock
+  *             @arg RCC_APB2Periph_TIM15:  TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:  TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:  TIM17 clock
+  *             @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:   TIM2 clock
+  *           @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *           @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:   TIM7 clock
+  *           @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *           @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *           @arg RCC_APB1Periph_USART2: USART2 clock
+  *           @arg RCC_APB1Periph_USART3: USART3 clock
+  *           @arg RCC_APB1Periph_USART4: USART4 clock
+  *           @arg RCC_APB1Periph_USART5: USART5 clock
+  *           @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *           @arg RCC_APB1Periph_USB:    USB clock
+  *           @arg RCC_APB1Periph_CAN:    CAN clock
+  *           @arg RCC_APB1Periph_CRS:    CRS clock
+  *           @arg RCC_APB1Periph_PWR:    PWR clock
+  *           @arg RCC_APB1Periph_DAC:    DAC clock
+  *           @arg RCC_APB1Periph_CEC:    CEC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB peripheral reset.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA: GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB: GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC: GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD: GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE: GPIOE clock
+  *             @arg RCC_AHBPeriph_GPIOF: GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:    TS clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRSTR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *             @arg RCC_APB2Periph_USART6: USART6 clock
+  *             @arg RCC_APB2Periph_USART7: USART7 clock
+  *             @arg RCC_APB2Periph_USART8: USART8 clock
+  *             @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *             @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *             @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *             @arg RCC_APB2Periph_USART1: USART1 clock
+  *             @arg RCC_APB2Periph_TIM15:  TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:  TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:  TIM17 clock
+  *             @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:   TIM2 clock
+  *           @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *           @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:   TIM7 clock
+  *           @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *           @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *           @arg RCC_APB1Periph_USART2: USART2 clock
+  *           @arg RCC_APB1Periph_USART3: USART3 clock
+  *           @arg RCC_APB1Periph_USART4: USART4 clock
+  *           @arg RCC_APB1Periph_USART5: USART5 clock
+  *           @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *           @arg RCC_APB1Periph_USB:    USB clock
+  *           @arg RCC_APB1Periph_CAN:    CAN clock
+  *           @arg RCC_APB1Periph_CRS:    CRS clock
+  *           @arg RCC_APB1Periph_PWR:    PWR clock
+  *           @arg RCC_APB1Periph_DAC:    DAC clock
+  *           @arg RCC_APB1Periph_CEC:    CEC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
+  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
+  *         automatically generated. The NMI will be executed indefinitely, and
+  *         since NMI has higher priority than any other IRQ (and main program)
+  *         the application will be stacked in the NMI ISR unless the CSS interrupt
+  *         pending bit is cleared.
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *              @arg RCC_IT_LSERDY: LSE ready interrupt
+  *              @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *              @arg RCC_IT_HSERDY: HSE ready interrupt
+  *              @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *              @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *              @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  * @param  NewState: new state of the specified RCC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_IT(RCC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *             @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *             @arg RCC_FLAG_PLLRDY: PLL clock ready
+  *             @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *             @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *             @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
+  *             @arg RCC_FLAG_PINRST: Pin reset
+  *             @arg RCC_FLAG_V18PWRRSTF:  V1.8 power domain reset
+  *             @arg RCC_FLAG_PORRST: POR/PDR reset
+  *             @arg RCC_FLAG_SFTRST: Software reset
+  *             @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *             @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *             @arg RCC_FLAG_LPWRRST: Low Power reset
+  *             @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
+  *             @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  * @retval The new state of RCC_FLAG (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+
+  if (tmp == 0)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 1)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else if (tmp == 2)          /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+  else                        /* The flag to check is in CR2 register */
+  {
+    statusreg = RCC->CR2;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_MASK;
+
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
+  *         RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+  *         RCC_FLAG_LPWRRST.
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RMVF bit to clear the reset flags */
+  RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *             @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of RCC_IT (SET or RESET).
+  */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_GET_IT(RCC_IT));
+
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/

bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rtc.c

@@ -0,0 +1,1902 @@
+/**
+  ******************************************************************************
+  * @file               ft32f0xx_rtc.c
+  * @author             FMD AE
+  * @brief              This file provides firmware functions to manage the following
+  *                     functionalities of the Real-Time Clock (RTC) peripheral:
+  *                 + Initialization
+  *                 + Calendar (Time and Date) configuration
+  *                 + Alarms (Alarm A) configuration
+  *                 + Daylight Saving configuration
+  *                 + Output pin Configuration
+  *                 + Digital Calibration configuration
+  *                 + TimeStamp configuration
+  *                 + Tampers configuration
+  *                 + Backup Data Registers configuration
+  *                 + Output Type Config configuration
+  *                 + Shift control synchronisation
+  *                 + Interrupts and flags management
+  * @version            V1.0.0
+  * @data                   2021-07-01
+    ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft32f0xx_rtc.h"
+
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
+                                            RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \
+                                            RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00004000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
+
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  ErrorStatus status = ERROR;
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR        = (uint32_t)0x00000000;
+    RTC->DR        = (uint32_t)0x00002101;
+    RTC->CR        &= (uint32_t)0x00000000;
+    RTC->PRER      = (uint32_t)0x007F00FF;
+    RTC->ALRMAR    = (uint32_t)0x00000000;
+    RTC->SHIFTR    = (uint32_t)0x00000000;
+    RTC->CALR       = (uint32_t)0x00000000;
+    RTC->ALRMASSR  = (uint32_t)0x00000000;
+
+    /* Reset ISR register and exit initialization mode */
+    RTC->ISR = (uint32_t)0x00000000;
+
+    /* Reset Tamper and alternate functions configuration register */
+    RTC->TAFCR = 0x00000000;
+
+    /* Wait till the RTC RSF flag is set */
+    if (RTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in
+  *         initialization mode only.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8],
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.
+  * @param  NewState: new state of the write protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = SUCCESS;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts
+  *         counting after 4 RTCCLK cycles.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+    /*when BypassShadow is enable,this bit should wait to clear zero.edit:2020.5.23*/
+    while((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+        ;
+    }
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
+  {
+    /* Bypass shadow mode */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+
+    /* Clear RSF flag */
+    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+
+    /* Wait the registers to be synchronised */
+    do
+    {
+      synchrostatus = RTC->ISR & RTC_ISR_RSF;
+      synchrocounter++;
+    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+    if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }
+
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xFF;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    }
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    }
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
+  }
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0;
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
+  *                        contain the returned current time configuration.
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
+
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
+  }
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
+  *                        contain the returned current date configuration.
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
+  *                          contains the alarm configuration parameters.
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    }
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    }
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+    }
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
+  }
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  RTC->ALRMAR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
+  *                          contains the output alarm configuration values.
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+
+  /* Get the RTC_ALRMAR register */
+  tmpreg = (uint32_t)(RTC->ALRMAR);
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  NewState: new state of the specified alarm.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;
+  }
+  else
+  {
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.
+  * @note   This function is performed only when the Alarm is disabled.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *          This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
+  *                                             There is no comparison on sub seconds for Alarm.
+  *            @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
+  *                                                Only SS[0] is compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
+  *                                                Only SS[1:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
+  *                                                Only SS[2:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
+  *                                                Only SS[3:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
+  *                                                Only SS[4:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
+  *                                                Only SS[5:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
+  *                                                Only SS[6:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
+  *                                                Only SS[7:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
+  *                                                Only SS[8:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                                 Only SS[9:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                                 Only SS[10:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                                 Only SS[11:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                                 Only SS[12:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
+  *                                              Only SS[13:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));
+
+  /* Configure the AlarmA SubSecond register */
+  RTC->ALRMASSR = tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+
+  /* Get the RTC_ALRMAR register */
+  tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *            @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit
+  *                             in CR register to store the operation.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Output_Disable: No output selected
+  *            @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+  *            @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal.
+  *          This parameter can be one of the following:
+  *            @arg RTC_OutputPolarity_High: The output pin is high when the
+  *                                          ALRAF is high (depending on OSEL)
+  *            @arg RTC_OutputPolarity_Low: The output pin is low when the
+  *                                         ALRAF is high (depending on OSEL)
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  {
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput: Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *            @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
+  *            @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *          This parameter can be can be one of the following values:
+  *            @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
+  *            @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
+  *            @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
+  *            @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+  *         activated.
+  *          This parameter can be one of the following:
+  *            @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
+  *                                           edge of the related pin.
+  *            @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
+  *                                            falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+    /*��Edge�ĸ��û�д�λ�Ķ���*/
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
+  *                             contains the TimeStamp time values.
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
+  *                             contains the TimeStamp date values.
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+  *                            stimulates tamper event.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
+  }
+  else
+  {
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;
+  }
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *            @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+  *                                           samples at the active level
+  *            @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+  *                                           samples at the active level
+  *            @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+  *                                           samples at the active level
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 32768
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 16384
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 8192
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 4096
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 2048
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 1024
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 512
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 256
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register
+  *         is reset.
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures the RTC Output Pin mode.
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
+  *                                    Open Drain mode.
+  *            @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in
+  *                                    Push Pull mode.
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register
+  * @param  RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
+  *          This parameter can be one of the following values :
+  *            @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
+  *            @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS:  Time Stamp interrupt mask
+  *            @arg RTC_IT_WUT:  WakeUp Timer interrupt mask
+  *            @arg RTC_IT_ALRA:  Alarm A interrupt mask
+  *            @arg RTC_IT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified RTC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FLAG_RECALPF: RECALPF event flag
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_INITF: Initialization mode flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *            @arg RTC_FLAG_INITS: Registers Configured flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT FMD *****END OF FILE****/