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@@ -9,6 +9,7 @@
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* 2024-04-23 Zeidan fix bugs, test on STM32F429IGTx
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* 2024-12-10 zzk597 add support for STM32F1 series
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* 2024-06-23 wdfk-prog Add blocking modes and distinguish POLL,INT,DMA modes
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+ * 2024-06-23 wdfk-prog Distinguish STM32 I2C timing semantics by IP generation
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*/
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#include "drv_hard_i2c.h"
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@@ -19,6 +20,18 @@
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#define LOG_TAG "drv.i2c.hw"
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#include <drv_log.h>
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+/*
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+ * Default timing values follow the IP generation split declared in
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+ * drv_hard_i2c.h:
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+ * - legacy IP (F1/F4): timing is the bus speed in Hz
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+ * - TIMINGR IP (F7/H7): timing is the raw I2C_TIMINGR value
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+ */
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+#if defined(STM32_I2C_TIMINGR_IP)
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+#define DEFAULT_I2C_TIMING_VALUE 0x307075B1U // 100K
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+#else
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+#define DEFAULT_I2C_TIMING_VALUE (100*1000U) //HZ
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+#endif
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+
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/* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */
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#define DMA_TRANS_MIN_LEN 2
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@@ -56,6 +69,16 @@ static struct stm32_i2c_config i2c_config[] =
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static struct stm32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0};
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+static void stm32_i2c_apply_default_config(struct stm32_i2c_config *cfg)
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+{
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+ RT_ASSERT(cfg != RT_NULL);
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+
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+ if (cfg->timing == 0U)
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+ {
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+ cfg->timing = DEFAULT_I2C_TIMING_VALUE;
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+ }
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+}
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+
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static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv)
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{
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RT_ASSERT(i2c_drv != RT_NULL);
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@@ -64,14 +87,16 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv)
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struct stm32_i2c_config *cfg = i2c_drv->config;
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rt_memset(i2c_handle, 0, sizeof(I2C_HandleTypeDef));
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+ stm32_i2c_apply_default_config(cfg);
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+
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i2c_handle->Instance = cfg->Instance;
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-#if defined(SOC_SERIES_STM32H7)
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+#if defined(STM32_I2C_TIMINGR_IP)
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i2c_handle->Init.Timing = cfg->timing;
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i2c_handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK;
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#else
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- i2c_handle->Init.ClockSpeed = 100000;
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+ i2c_handle->Init.ClockSpeed = cfg->timing;
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i2c_handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
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-#endif /* defined(SOC_SERIES_STM32H7) */
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+#endif /* defined(STM32_I2C_TIMINGR_IP) */
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i2c_handle->Init.OwnAddress1 = 0;
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i2c_handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
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i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
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@@ -87,7 +112,7 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv)
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{
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return -RT_EFAULT;
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}
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-#if defined(SOC_SERIES_STM32H7)
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+#if defined(STM32_I2C_TIMINGR_IP)
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/* Configure Analogue filter */
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if (HAL_I2CEx_ConfigAnalogFilter(i2c_handle, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
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{
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@@ -99,7 +124,7 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv)
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{
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return -RT_EFAULT;
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}
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-#endif /* defined(SOC_SERIES_STM32H7) */
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+#endif /* defined(STM32_I2C_TIMINGR_IP) */
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#if defined(BSP_I2C_RX_USING_DMA)
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/* I2C2 DMA Init */
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if (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX)
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@@ -325,6 +350,10 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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+ /* timeout = data_time + dev_addr_time + reserve_time */
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+#define TIMEOUT_FREQ_KHZ(freq) (((freq) / 1000U) ? ((freq) / 1000U) : 1U)
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+#define TIMEOUT_CALC(msg) (((msg)->len * 8U) / TIMEOUT_FREQ_KHZ(bus->config.usage_freq) + 1U + 5U)
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+
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rt_uint32_t i = 0;
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rt_int32_t ret = 0;
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struct rt_i2c_msg *msg = RT_NULL;
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@@ -348,13 +377,6 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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completion = &i2c_obj->completion;
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#endif /* defined(BSP_I2C_USING_IRQ) */
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LOG_D("xfer start %d megs", num);
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-
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- rt_uint32_t freq_khz = bus->config.usage_freq / 1000;
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- if (freq_khz == 0)
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- {
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- freq_khz = 1;
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- }
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-
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for (i = 0; i < num; i++)
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{
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rt_bool_t need_wait = RT_FALSE;
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@@ -363,10 +385,11 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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next_msg = is_last ? RT_NULL : &msgs[i + 1];
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mode = stm32_i2c_get_xfer_mode(i, msg, next_msg, is_last);
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LOG_D("xfer msgs[%d] addr=0x%2x buf=0x%x len= 0x%x flags= 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags);
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-
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- // timeout= data_time + dev_addr_time + reserve_time
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- timeout = (msg->len * 8) / freq_khz + 1 + 5;
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-
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+#if defined(STM32_I2C_TIMINGR_IP)
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+ timeout = bus->timeout ? bus->timeout : 100U;
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+#else
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+ timeout = TIMEOUT_CALC(msg);
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+#endif
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if (msg->flags & RT_I2C_RD)
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{
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LOG_D("xfer rec msgs[%d] hal mode = %s", i, stm32_i2c_mode_name(mode));
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@@ -421,38 +444,78 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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out:
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ret = i;
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/*
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- * On STM32H7, STOPI only enables STOP-event interrupt handling.
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+ * On TIMINGR-based STM32 I2C IPs (currently F7/H7 in this driver),
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+ * STOPI only enables STOP-event interrupt handling.
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* It does not actively generate a STOP condition on the bus.
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*
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- * For non-H7 STM32 series, the legacy HAL error handler already
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- * generates a STOP condition on AF in master/memory modes, so
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- * this driver does not manually issue another STOP in the AF path.
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+ * For legacy STM32 I2C IPs, the HAL error handler already generates a
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+ * STOP condition on AF in master/memory modes, so this driver does not
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+ * manually issue another STOP in the AF path.
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*/
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if (handle->ErrorCode & HAL_I2C_ERROR_AF)
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{
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LOG_W("I2C[%s] NACK Error", bus->parent.parent.name);
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-#if defined(SOC_SERIES_STM32H7)
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+#if defined(STM32_I2C_TIMINGR_IP)
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handle->Instance->CR1 |= I2C_IT_STOPI;
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-#endif /* defined(SOC_SERIES_STM32H7) */
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+#endif /* defined(STM32_I2C_TIMINGR_IP) */
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}
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if (handle->ErrorCode & HAL_I2C_ERROR_BERR)
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{
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LOG_W("I2C[%s] BUS Error", bus->parent.parent.name);
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-#if defined(SOC_SERIES_STM32H7)
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+#if defined(STM32_I2C_TIMINGR_IP)
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handle->Instance->CR1 |= I2C_IT_STOPI;
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#else
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handle->Instance->CR1 |= I2C_CR1_STOP;
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-#endif /* defined(SOC_SERIES_STM32H7) */
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+#endif /* defined(STM32_I2C_TIMINGR_IP) */
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}
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return ret;
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+#undef TIMEOUT_FREQ_KHZ
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+#undef TIMEOUT_CALC
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+}
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+
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+rt_err_t stm_i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args)
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+{
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+ struct stm32_i2c *i2c_obj;
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+ RT_ASSERT(bus != RT_NULL);
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+
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+ i2c_obj = rt_container_of(bus, struct stm32_i2c, i2c_bus);
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+ RT_ASSERT(i2c_obj != RT_NULL);
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+
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+ switch (cmd)
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+ {
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+ case BSP_I2C_CTRL_SET_TIMING:
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+ {
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+ if (args == RT_NULL)
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+ {
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+ return -RT_EINVAL;
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+ }
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+
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+ rt_uint32_t timing = *(rt_uint32_t *)args;
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+ if(timing <= 0)
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+ {
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+ return -RT_ERROR;
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+ }
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+
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+ i2c_obj->i2c_bus.config.usage_freq = i2c_obj->config->timing = timing;
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+ return stm32_i2c_configure(&i2c_obj->i2c_bus);
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+ break;
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+ }
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+ default:
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+ {
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+ break;
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+ }
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+ }
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+ return -RT_EINVAL;
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}
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static const struct rt_i2c_bus_device_ops stm32_i2c_ops =
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{
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.master_xfer = stm32_i2c_master_xfer,
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- RT_NULL,
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- RT_NULL,
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+#if defined(STM32_I2C_LEGACY_IP)
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+ .i2c_bus_control = stm_i2c_bus_control,
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+#endif
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+ .slave_xfer = RT_NULL,
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};
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int RT_hw_i2c_bus_init(void)
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@@ -465,6 +528,12 @@ int RT_hw_i2c_bus_init(void)
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i2c_objs[i].i2c_bus.ops = &stm32_i2c_ops;
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i2c_objs[i].config = &i2c_config[i];
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i2c_objs[i].i2c_bus.timeout = i2c_config[i].timeout;
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+ stm32_i2c_apply_default_config(&i2c_config[i]);
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+#if defined(STM32_I2C_LEGACY_IP)
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+ i2c_objs[i].i2c_bus.config.max_hz = i2c_config[i].timing;
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+ i2c_objs[i].i2c_bus.config.usage_freq = i2c_config[i].timing;
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+#endif
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+
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#ifdef BSP_I2C_USING_DMA
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if ((i2c_objs[i].i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX))
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{
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@@ -525,7 +594,7 @@ int RT_hw_i2c_bus_init(void)
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i2c_objs[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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i2c_objs[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
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i2c_objs[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
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-#endif
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+#endif /* SOC_SERIES_STM32U5 */
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
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i2c_objs[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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@@ -685,7 +754,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
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#endif /* I2C4 */
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: "unknown",
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hi2c->ErrorCode);
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-#if defined(SOC_SERIES_STM32H7)
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+#if defined(STM32_I2C_TIMINGR_IP)
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/* Send stop signal to prevent bus lock-up */
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if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
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{
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@@ -697,7 +766,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
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LOG_W("I2C BUS Error now stoped");
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hi2c->Instance->CR1 |= I2C_IT_STOPI;
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}
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-#endif /* defined(SOC_SERIES_STM32H7) */
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+#endif /* defined(STM32_I2C_TIMINGR_IP) */
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}
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#ifdef BSP_USING_HARD_I2C1
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wdfk-prog