[bsp][yichip] add yc3122-pos (#7526)

Co-authored-by: supperthomas <78900636@qq.com>

.github/workflows/action.yml

@@ -63,6 +63,7 @@ jobs:
                 - "at32/at32f425-start"
                 - "at32/at32f435-start"
                 - "at32/at32f437-start"
+                - "yichip/yc3122-pos"
                 - "hc32/ev_hc32f4a0_lqfp176"
                 - "hc32/ev_hc32f460_lqfp100_v2"
                 - "hc32l196"

bsp/yichip/yc3122-pos/.config

@@ -0,0 +1,998 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_RT_USING_HW_ATOMIC is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_MTD_NOR=y
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_BITOPS is not set
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+CONFIG_RT_SFUD_USING_SFDP=y
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+# CONFIG_RT_SFUD_USING_QSPI is not set
+CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
+# CONFIG_RT_DEBUG_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_YC3122=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_INTER_FLASH is not set

bsp/yichip/yc3122-pos/Kconfig

@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_YC3122
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "drivers/Kconfig"

bsp/yichip/yc3122-pos/Libraries/.ignore_format.yml

@@ -0,0 +1,9 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- CMSIS
+- core
+- sdk
+- startup

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/YC3122.svd

@@ -0,0 +1,11215 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.0" xmlns:xs="http://www.yichip.com/" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+	<name>YC3122</name>
+	<version>1.0</version>
+	<series>ARMCM0</series>
+	<description>ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 80MHz, etc.</description>
+	<licenseText>YC is supplying the software is provided for YC3122 microprocessor.</licenseText>
+	<cpu>
+		<name>CM0</name>
+		<revision>r1p0</revision>
+		<endian>little</endian>
+		<mpuPresent>false</mpuPresent>
+		<fpuPresent>false</fpuPresent>
+		<nvicPrioBits>8</nvicPrioBits>
+		<vendorSystickConfig>false</vendorSystickConfig>
+	</cpu>
+	<addressUnitBits>8</addressUnitBits>
+	<width>32</width>
+	<size>32</size>
+	<access>read-write</access>
+	<resetValue>0x00000000</resetValue>
+	<resetMask>0xFFFFFFFF</resetMask>
+	<peripherals>
+		<!--MCU-->
+		<peripheral>
+			<name>MMCU</name>
+			<version>1.0</version>
+			<description>MMCU</description>
+			<groupName>MMCU</groupName>
+			<baseAddress>0xd0000</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x110</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<interrupt>
+				<name>USB</name>
+				<value>0</value>
+			</interrupt>
+			<interrupt>
+				<name>I2C0</name>
+				<value>1</value>
+			</interrupt>
+			<interrupt>
+				<name>I2C1</name>
+				<value>2</value>
+			</interrupt>
+			<interrupt>
+				<name>QSPI</name>
+				<value>3</value>
+			</interrupt>
+			<interrupt>
+				<name>SPI0</name>
+				<value>4</value>
+			</interrupt>
+			<interrupt>
+				<name>SPI1</name>
+				<value>5</value>
+			</interrupt>
+			<interrupt>
+				<name>HSPI</name>
+				<value>6</value>
+			</interrupt>
+			<interrupt>
+				<name>SEC</name>
+				<value>7</value>
+			</interrupt>
+			<interrupt>
+				<name>UART0</name>
+				<value>8</value>
+			</interrupt>
+			<interrupt>
+				<name>UART1</name>
+				<value>9</value>
+			</interrupt>
+			<interrupt>
+				<name>UART2</name>
+				<value>10</value>
+			</interrupt>
+			<interrupt>
+				<name>UART3</name>
+				<value>11</value>
+			</interrupt>
+			<interrupt>
+				<name>MEMCP</name>
+				<value>12</value>
+			</interrupt>
+			<interrupt>
+				<name>SCI0</name>
+				<value>13</value>
+			</interrupt>
+			<interrupt>
+				<name>SCI1</name>
+				<value>14</value>
+			</interrupt>
+			<interrupt>
+				<name>MSR</name>
+				<value>15</value>
+			</interrupt>
+			<interrupt>
+				<name>GPIO</name>
+				<value>16</value>
+			</interrupt>
+			<interrupt>
+				<name>TMRG0</name>
+				<value>17</value>
+			</interrupt>
+			<interrupt>
+				<name>TMRG1</name>
+				<value>18</value>
+			</interrupt>
+			<interrupt>
+				<name>SDIO</name>
+				<value>19</value>
+			</interrupt>
+			<interrupt>
+				<name>PSARM</name>
+				<value>20</value>
+			</interrupt>
+			<interrupt>
+				<name>RSA</name>
+				<value>21</value>
+			</interrupt>
+			<interrupt>
+				<name>SM4</name>
+				<value>22</value>
+			</interrupt>
+			<interrupt>
+				<name>TRNG</name>
+				<value>23</value>
+			</interrupt>
+			<interrupt>
+				<name>WDT</name>
+				<value>24</value>
+			</interrupt>
+			<interrupt>
+				<name>DCMI</name>
+				<value>25</value>
+			</interrupt>
+			<interrupt>
+				<name>ADC</name>
+				<value>26</value>
+			</interrupt>
+			<interrupt>
+				<name>RTC</name>
+				<value>27</value>
+			</interrupt>
+			<interrupt>
+				<name>RSVD1</name>
+				<value>28</value>
+			</interrupt>
+			<interrupt>
+				<name>POWER</name>
+				<value>29</value>
+			</interrupt>
+			<interrupt>
+				<name>SOFTWARE</name>
+				<value>30</value>
+			</interrupt>
+			<interrupt>
+				<name>RISCV</name>
+				<value>31</value>
+			</interrupt>
+			<registers>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>BITBAND_CFG</name>
+							<description>bitband 每一BIT对应的地址长度(0x2\n0000对应的地址是0x800000)\n0: RAM每一BIT对应的地址长度是8-bit\n1: RAM每一BIT对应的地址长度是32-bit</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SCSCLK_EN</name>
+							<description>m0 scsclk的使能</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FCLK_EN</name>
+							<description>m0 fclk的使能</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DCLK_EN</name>
+							<description>m0 dclk的使能</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>WFI_EN</name>
+							<description>m0 WFI的使能</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LTSLEEP</name>
+							<description>写1 M0,进入浅睡眠模式\n注意:此BIT写1后必须要有6个以上的NOP指令,否则退\n出浅睡眠时可能会出错</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LTSLEEP_EN</name>
+							<description>使能 lightsleep</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--WKUP_SRC-->
+				<register>
+					<name>WKUP_SRC</name>
+					<description>* WKUP_SRC *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>唤醒中断源设置: 每1bit对应0~31号中断</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ERROR_STATUS-->
+				<register>
+					<name>ERROR_STATUS</name>
+					<description>* ERROR_STATUS *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ERR_CLR</name>
+							<description>写1会清除所有的CPU ERROR状态</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DMA_MPU</name>
+							<description>当这1bit置1,代表DMA MPU错误</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>MPU_ROM</name>
+							<description>当这1bit置1,代表rom区域非法访问</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RCODE_CRC</name>
+							<description>当这1bit置1,代表RV代码读取CRC校验错误</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RV_ACCESS</name>
+							<description>当这1bit置1,代表risc-v访问不存在的地\n址空间</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RV_MPU</name>
+							<description>当这1bit置1,代表RV MPU错误</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RAM_NOEXE</name>
+							<description>当这1bit置1,代表M0 RAM执行代码错误</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>MPU</name>
+							<description>当这1bit置1,代表M0 MPU错误</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>MEM</name>
+							<description>当这1bit置1,代表ROM或RAM奇偶校验错误</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>CODE_CRC</name>
+							<description>当这1bit置1,代表M0的代码 CRC校验错误</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--IRQ_ADDR0-->
+				<register>
+					<name>IRQ_ADDR0</name>
+					<description>* IRQ_ADDR0 *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>M0的中断起始地址</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CURR_CLK-->
+				<register>
+					<name>CURR_CLK</name>
+					<description>* CURR_CLK *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>MS_CLK</name>
+							<description>DELAY_MS所需时钟(单位CLK)</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>US_CLK</name>
+							<description>DELAY_US所需时钟(单位CLK)</description>
+							<bitRange>[31:20]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RV_CTRL-->
+				<register>
+					<name>RV_CTRL</name>
+					<description>* RV_CTRL *</description>
+					<addressOffset>0x100</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SLP_STATUS</name>
+							<description>RV睡眠状态\n1:睡眠\n0:没有睡眠</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RST_STATUS</name>
+							<description>RV复位状态\n1:复位\n0:没有复位</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>FS_LOCK</name>
+							<description>RV独立睡眠配置锁定\n1: 锁定 FS_LOCK和FS_EN</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FS_EN</name>
+							<description>RV独立睡眠配置\n0xa: M0和RV独立睡眠\nothers: M0睡眠会强制RV一起睡眠</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESET</name>
+							<description>RV复位使能\n0x0a: enable risc-v\nothers: reset riscv</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLK_EN</name>
+							<description>RV 时钟使能\n0x0a: 使能 risc-v clock\nothers: 失能 risc-v clock</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RV_IRQ-->
+				<register>
+					<name>RV_IRQ</name>
+					<description>* RV_IRQ *</description>
+					<addressOffset>0x104</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TRIG</name>
+							<description>写‘1’会触发m0_to_rv中断,中断pend\ning寄存器和wakeup enable配置在riscv\n寄存器中\n必须写0清除,否则会导致一直触发</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IRQ</name>
+							<description>rv_to_m0中断状态位,使能之前必须先清除一\n下该标志位,否则上次中断状态会直接触发中断</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>rv_to_m0中断使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SW_IRQ-->
+				<register>
+					<name>SW_IRQ</name>
+					<description>* SW_IRQ *</description>
+					<addressOffset>0x108</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CODE</name>
+							<description>用户软件自己可以操作的8BIT</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TRIG</name>
+							<description>软件写1会触发软件中断</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>M0软件中断使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BIN_IRQ-->
+				<register>
+					<name>BIN_IRQ</name>
+					<description>* BIN_IRQ *</description>
+					<addressOffset>0x10c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ONED_IE</name>
+							<description>一维码二值化中断使能</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>QR_IE</name>
+							<description>二维码二值化中断使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--MPU-->
+		<peripheral>
+			<name>MMPU</name>
+			<version>1.0</version>
+			<description>MMPU</description>
+			<groupName>MMPU</groupName>
+			<baseAddress>0xd8080</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x80</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL_ID-->
+				<register>
+					<name>CTRL_ID</name>
+					<description>* CTRL_ID *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>MPU ID</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>MPU使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL_FSR-->
+				<register>
+					<name>CTRL_FSR</name>
+					<description>* CTRL_FSR *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[4:2] fault region\n[1:0] fault  status</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL_FAR-->
+				<register>
+					<name>CTRL_FAR</name>
+					<description>* CTRL_FAR *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>fault address</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PROTECTION-->
+				<register>
+					<name>PROTECTION</name>
+					<description>* PROTECTION *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>16</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>protection15：0\n00：no access\n01：private only\n10：private + user read only\n11：Full Access</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--USER_START-->
+				<register>
+					<name>USER_START</name>
+					<description>* USER_START *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>用户程序起始地址</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE0-->
+				<register>
+					<name>REGION_BASE0</name>
+					<description>* REGION_BASE0 *</description>
+					<addressOffset>0x40</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE1-->
+				<register>
+					<name>REGION_BASE1</name>
+					<description>* REGION_BASE1 *</description>
+					<addressOffset>0x44</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE2-->
+				<register>
+					<name>REGION_BASE2</name>
+					<description>* REGION_BASE2 *</description>
+					<addressOffset>0x48</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE3-->
+				<register>
+					<name>REGION_BASE3</name>
+					<description>* REGION_BASE3 *</description>
+					<addressOffset>0x4c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE4-->
+				<register>
+					<name>REGION_BASE4</name>
+					<description>* REGION_BASE4 *</description>
+					<addressOffset>0x50</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE5-->
+				<register>
+					<name>REGION_BASE5</name>
+					<description>* REGION_BASE5 *</description>
+					<addressOffset>0x54</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE6-->
+				<register>
+					<name>REGION_BASE6</name>
+					<description>* REGION_BASE6 *</description>
+					<addressOffset>0x58</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_BASE7-->
+				<register>
+					<name>REGION_BASE7</name>
+					<description>* REGION_BASE7 *</description>
+					<addressOffset>0x5c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[0]regionx_enable [20:6]\n  BASEx_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT0-->
+				<register>
+					<name>REGION_LIMIT0</name>
+					<description>* REGION_LIMIT0 *</description>
+					<addressOffset>0x60</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT0_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT1-->
+				<register>
+					<name>REGION_LIMIT1</name>
+					<description>* REGION_LIMIT1 *</description>
+					<addressOffset>0x64</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT1_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT2-->
+				<register>
+					<name>REGION_LIMIT2</name>
+					<description>* REGION_LIMIT2 *</description>
+					<addressOffset>0x68</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT2_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT3-->
+				<register>
+					<name>REGION_LIMIT3</name>
+					<description>* REGION_LIMIT3 *</description>
+					<addressOffset>0x6c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT3_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT4-->
+				<register>
+					<name>REGION_LIMIT4</name>
+					<description>* REGION_LIMIT4 *</description>
+					<addressOffset>0x70</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT4_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT5-->
+				<register>
+					<name>REGION_LIMIT5</name>
+					<description>* REGION_LIMIT5 *</description>
+					<addressOffset>0x74</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT5_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT6-->
+				<register>
+					<name>REGION_LIMIT6</name>
+					<description>* REGION_LIMIT6 *</description>
+					<addressOffset>0x78</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT6_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REGION_LIMIT7-->
+				<register>
+					<name>REGION_LIMIT7</name>
+					<description>* REGION_LIMIT7 *</description>
+					<addressOffset>0x7c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>[20:6] LIMIT7_REG</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--HSPI-->
+		<peripheral>
+			<name>MHSPI</name>
+			<version>1.0</version>
+			<description>MHSPI</description>
+			<groupName>MHSPI</groupName>
+			<baseAddress>0xd8400</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x34</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>FIRST_BIT</name>
+							<description> 帧格式位\n0：先发送MSB;\n1：先发送LSB\n注：y_to_rgb_mode为1时,先进行y转rgb操\n作,再按配置比特顺序进行发送</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>Y2RGB</name>
+							<description>buff内容转RGB565控制位\n0：无操作;\n1：buffer内容为8-bit灰度，实际发送时会自动转\n换为16-bit RGB565发送。</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_PHASE</name>
+							<description>控制接收相位调整值位,按bit采样位偏移N个cl\nk个 个数\n0-7: 采样时间延后(rx_adj_clk + 1)*\nHspi_clk不得大于clk_div。\n</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLK_DIV</name>
+							<description>HSPI预分频位\n0-7：分频值为(clk_div + 1)*2。</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TRX_DLY</name>
+							<description>发送和接收保护间隔位\n0-7：软件增加Hspi_clk*(trx_dly+1)\n*4个周期时长。</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIFO_CTRL</name>
+							<description>FIFO软件控制权限使能位\n0: 软件无法操作FIFO,仅运行DMA自动操作\n1: 软件可以操作FIFO,不使用DMA时,可以直接使用\nFIFO进行收发</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>NCS_DLY</name>
+							<description>NCS提前拉低和滞后拉高的延时位\n0-7：spi_clk*(ncs_dly+1)。</description>
+							<bitRange>[10:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXD_EN</name>
+							<description>接收相位调整使能开关\n0：失能相位调整;\n1：使能相位调整。</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RTX_SEQ</name>
+							<description>收发序列控制位\n0：收发同时进行，长度为tx_len;\n1：先进行tx_len次发送, 再进行rx_len次接收\n（rx_len为0时跳过接收）</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CPHA</name>
+							<description>时钟相位\n0：空闲状态时，SCK保持低电平；\n1：空闲状态时，SCK保持高电平；</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CPOL</name>
+							<description>时钟极性位\n0：失能相位调整\n1：使能相位调整</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>START</name>
+							<description>HSPI启动位，自动开启DMA_START\n0：无动作\n1：硬件启动一次HSPI收发</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>START_SEL</name>
+							<description>DCMI多行中断选择\n0: DCMI DMA0\n1: DCMI DMA1</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>START_EN</name>
+							<description>DCMI多行中断启动spi使能\n0: 禁止硬件启动spi\n1: 允许硬件启动spi</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>接收相位调整使能开关\n0：失能HSPI\n1：使能HSPI</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--FIFO-->
+				<register>
+					<name>FIFO</name>
+					<description>* FIFO *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RX_DATA</name>
+							<description>读取RX_FIFO数据\n0-7：写寄存器时，直接将此字节写入Rx_FIFO，\n读取此寄存器时，表示Rx_FIFO当前值;</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TX_DATA</name>
+							<description>读取Tx_FIFO数据\n0-7：写寄存器时，直接将此字节写入Tx_FIFO，\n读取此寄存器时，表示Tx_FIFO当前值;</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AUTO_RST</name>
+							<description>fifo自动复位\n0: do not effect\n1: 每次传输完成后,自动复位一下fifo</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_FULL</name>
+							<description>RXFIFO状态位\n0：非满;\n1：满。</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_EMPTY</name>
+							<description>RXFIFO状态位\n0：非空;\n1：空。</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_RPTR_INC</name>
+							<description>读取RXFIFO字节位，写1, RX_DATA读\n地址加1\n0：无操作；\n1：读取FIFO中一个字节</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RST</name>
+							<description>软件复位FIFO\n0: do not effect\n1: reset fifo</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TX_FULL</name>
+							<description> TXFIFO状态位\n0：非满;\n1：满。</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_EMPTY</name>
+							<description>TXFIFO状态位\n0：非空;\n1：空。</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_RPTR_INC</name>
+							<description>读取TXFIFO字节位，写1, TX_DATA读\n地址加1\n0：无操作；\n1：读取FIFO中一个字节；</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA-->
+				<register>
+					<name>DMA</name>
+					<description>* DMA *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PINGPANG_EN</name>
+							<description>SPI发送数据时,DMA从内存中乒乓buffer\n取数\n0: disable pingpang\n1: enable pingpang,tx_saddr~\ntx_saddr+tx_len和tx_saddr+tx_\nlen ~ tx_saddr+tx_len*2</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_PTR_INC</name>
+							<description>RXFIFO状态位\n0：rx_addr自增;\n1：rx_addr不自增。</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TX_PTR_INC</name>
+							<description>TXFIFO状态位\n0：tx_addr自增\n1：tx_addr不自增。</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>START</name>
+							<description>启动DMA传输位，同AUTO_START搭配使用\n0：无操作；\n1：启动一次dma传输任务</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AUTO_START</name>
+							<description>DMA自动传输位\n0：dma不会自动启动，必须手动通过dma_start_\nman启动;\n1：spi_start自动启动dma，无须手动启动dma\n。</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>DMA控制位\n0：失能DMA;\n1：使能DMA。</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IRQ-->
+				<register>
+					<name>IRQ</name>
+					<description>* IRQ *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SOQ_EN</name>
+							<description>检测START信号丢失使能位\n0: 失能；\n1: 使能。</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFO_EN</name>
+							<description>接收FIFO溢出控制位\n0: 失能接收FIFO未溢出;\n1: 使能接收FIFO溢出;</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFH_EN</name>
+							<description>接收FIFO高水准线控制位\n0: 失能高于低水准线;\n1: 使能高于水准线。</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFO_EN</name>
+							<description>发送FIFO溢出控制位\n0: 失能发送FIFO未溢出;\n1: 使能发送FIFO溢出。</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFL_EN</name>
+							<description>发送FIFO低水准线控制位\n0: 失能低于低水准线；\n1: 使能低于低水准线。</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DMA_EN</name>
+							<description>DMA发送完成控制位\n0: 失能DMA发送;\n1: 使能DMA发送。</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOQ_MIS</name>
+							<description>丢失一次HSPI任务状态位\n0: 未错过任务；\n1: 出错，错过一次任务。</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFO_MIS</name>
+							<description>接收FIFO溢出状态位\n0: 接收FIFO未溢出设定字节个数;\n1: 接收FIFO溢出设定字节个数。</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFH_MIS</name>
+							<description>接收FIFO高水准线状态位\n0: 不高于低水准线;\n1: 高于水准线。</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFO_MIS</name>
+							<description>发送FIFO溢出状态位\n0: 发送FIFO未溢出设定字节个数;\n1: 发送FIFO溢出设定字节个数。</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFL_MIS</name>
+							<description>发送FIFO低水准线状态位\n0: 不低于低水准线；\n1: 低于低水准线。</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DMA_MIS</name>
+							<description>DMA传输状态位\n0: DMA发送未完成;\n1: DMA发送完成。</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOQ_RIS</name>
+							<description>HSPI start信号来临时，上次传输还未完成\n， \n此时会错过一个HSPI任务，出现错误。\n0: 未错过任务；\n1: 出错，错过一次任务</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFO_RIS</name>
+							<description>接收FIFO溢出标志位\n0: 接收FIFO未溢出设定字节个数;\n1: 接收FIFO溢出设定字节个数。</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RXFH_RIS</name>
+							<description>接收FIFO高水准线标志位\n0: 不高于低水准线;\n1: 高于水准线。</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFO_RIS</name>
+							<description>发送FIFO溢出标志位\n0: 发送FIFO未溢出设定字节个数;\n1: 发送FIFO溢出设定字节个数。</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TXFL_RIS</name>
+							<description>发送FIFO低水准线标志位\n0: 不低于低水准线；\n1: 低于低水准线；</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DMA_RIS</name>
+							<description>DMA发送完成标志位\n0: DMA发送未完成；\n1: DMA完成一次传输发送；</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_TX_SADDR-->
+				<register>
+					<name>DMA_TX_SADDR</name>
+					<description>* DMA_TX_SADDR *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>存放发送数据起始地址，必须四字节对齐。</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_RX_SADDR-->
+				<register>
+					<name>DMA_RX_SADDR</name>
+					<description>* DMA_RX_SADDR *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收数据的起始地址，必须四字节对齐</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_TX_LEN-->
+				<register>
+					<name>DMA_TX_LEN</name>
+					<description>* DMA_TX_LEN *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>HSPI发送数据字节长度，配置为0时，表示仅接收</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_RX_LEN-->
+				<register>
+					<name>DMA_RX_LEN</name>
+					<description>* DMA_RX_LEN *</description>
+					<addressOffset>0x1c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>HSPI接收数据字节长度，配置为0时，表示仅发送</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_TX_ADDR-->
+				<register>
+					<name>DMA_TX_ADDR</name>
+					<description>* DMA_TX_ADDR *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>存放当前发送数据的地址。</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--DMA_RX_ADDR-->
+				<register>
+					<name>DMA_RX_ADDR</name>
+					<description>* DMA_RX_ADDR *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>存放当前接收数据的地址。</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--FIFO_CTRL-->
+				<register>
+					<name>FIFO_CTRL</name>
+					<description>* FIFO_CTRL *</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TX_ITEMS</name>
+							<description>读取RX_FIFO的数据个数。</description>
+							<bitRange>[28:24]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_ITEMS</name>
+							<description>读取Tx_FIFO的数据个数。</description>
+							<bitRange>[20:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_WATERLEVEL</name>
+							<description>接收FIFO高水线，\n接收FIFO数据大于等于此长度，并且水线值不为0时，\n触发rx_fifo_hi中断。</description>
+							<bitRange>[12:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_WATERLEVEL</name>
+							<description>发送FIFO低水线，\n发送FIFO数据小于等于此长度，并且水线值不为0时，\n触发tx_fifo_lo中断。</description>
+							<bitRange>[4:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--WDT-->
+		<peripheral>
+			<name>MWDT</name>
+			<version>1.0</version>
+			<description>MWDT</description>
+			<groupName>MWDT</groupName>
+			<baseAddress>0xf0000</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x10</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CONFIG-->
+				<register>
+					<name>CONFIG</name>
+					<description>* CONFIG *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>OFF_LOCK</name>
+							<description>wdt_off_lock\n1: wdt_off不起作用\n0: wdt_off起作用</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>OFF</name>
+							<description>关闭wdt\nwdt_off_lock为0,并且wdt_on为0时,设\n置wdt_off为1,再设置wdt_off为0,可关闭w\ndt</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLK_DIV</name>
+							<description>hclk预分频,最大16分频,实际使用的时钟频率\n是clk/(wdt_clk_div+1)</description>
+							<bitRange>[10:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>0 :WDT功能关闭. 1: WDT 功能打开.</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MODE</name>
+							<description>0 :复位 1:中断</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RELOAD</name>
+							<description>WDT计数时长为(2^(wdt_preset-1\n))个hclk_div时钟周期</description>
+							<bitRange>[4:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CNT-->
+				<register>
+					<name>CNT</name>
+					<description>* CNT *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CNT</name>
+							<description>WDT CNT</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- KICK -->
+				<register>
+					<name>IRQ_STATUS</name>
+					<description>WDT IRQ STATUS</description>
+					<addressOffset>0x08</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- WDT: KICK Register -->
+						<field>
+							<name>STATE</name>
+							<description>WDT IRQ STATUS</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<register>
+					<name>KICK</name>
+					<description>WDT KICK, 必须写 0x5937</description>
+					<alternateRegister>IRQ_STATUS</alternateRegister>
+					<addressOffset>0x08</addressOffset>
+					<fields>
+						<!-- WDT: KICK Register -->
+						<field>
+							<name>VALUE</name>
+							<description>WDT KICK,必须写 0x5937</description>
+							<bitRange>[31:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLEAR-->
+				<register>
+					<name>CLEAR</name>
+					<description>* CLEAR *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CLEAR</name>
+							<description>向这个寄存器中写1清除WDT 中断</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--SCI0-->
+		<peripheral>
+			<name>MSCI0</name>
+			<version>1.0</version>
+			<description>MSCI0</description>
+			<groupName>MSCI0</groupName>
+			<baseAddress>0xf0400</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x90</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--MODE-->
+				<register>
+					<name>MODE</name>
+					<description>* MODE *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EDC_EN</name>
+							<description>EDC错误检测使能          \n0: 失能 \n1: 使能</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MST_EN</name>
+							<description>主机模式使能   \n0: 失能 \n1: 使能</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLK_SEL</name>
+							<description>CLK时钟源控制位(PWM0~PWM7)</description>
+							<bitRange>[14:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_EN</name>
+							<description>CWT计时器使能        \n0: 失能\n1: 使能</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BGT_EN</name>
+							<description>块保护时间使能         \n0: 失能 \n1: 使能</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>SCI7816使能     \n0: 失能 \n1: 使能</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RET_EN</name>
+							<description>重传使能位\n0:失能\n1:使能</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RET_TIME</name>
+							<description>重传次数</description>
+							<bitRange>[7:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ETU_NUM</name>
+							<description>ETU个数控制位</description>
+							<bitRange>[4:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>OD</name>
+							<description>OD控制位\n0: 开漏模式 \n1: 推挽模式(default)</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CODE_DRT</name>
+							<description>编码选择控制位\n0:正向编码 \n1:反向编码</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TPS</name>
+							<description>模式控制位\n0:T=0 \n1:T=1</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TS_TEST</name>
+							<description>检测TS字节\n0:不起作用\n1:接收到数据为03时校验位电平取反</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_CL</name>
+							<description>发送FIFO内容清除控制位\n0:不起作用\n1:清除FIFO内数据</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_CL</name>
+							<description>接收FIFO内容清除控制位\n0:不起作用\n1:清除FIFO内数据</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS-->
+				<register>
+					<name>STATUS</name>
+					<description>* STATUS *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CHK_BIT</name>
+							<description>检验位状态\n0:检验位正确  \n1:检验位错误</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_OT</name>
+							<description>CWT超时状态位\n0:没超时 \n1:超时 (参考:SCI7816_CWT寄存器说明）</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BGT_OT</name>
+							<description>BGT超时状态位\n0:没超时 \n1:超时 (参考:SCI7816_BGT寄存器说明）</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RET_CHK</name>
+							<description>重传奇偶校验检测状态位\n0: 奇偶校验正确 \n1: 奇偶校验错误（在重传功能开启时,只有在发送达到重传\n次数时仍有错误发生,此位才被置位）</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_F</name>
+							<description>发送缓冲器满状态位\n0: 发送缓冲器不满 \n1: 发送缓冲器满</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_N</name>
+							<description>发送缓冲器空状态位\n0: 发送缓冲器空 \n1: 发送缓冲器中不空</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PRT_CHK</name>
+							<description>奇偶校验状态位\n0: 奇偶校验正确 \n1: 奇偶校验错误</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_F</name>
+							<description>接收缓冲器满状态位\n0:接收缓冲器不满 \n1:接收缓冲器满</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_N</name>
+							<description>接收缓冲器空状态位\n0:接收缓冲器空 \n1:接收缓冲器中不空</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--INT_IO-->
+				<register>
+					<name>INT_IO</name>
+					<description>* INT_IO *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>T_FNS</name>
+							<description>发送完成标志位\n0:没发送完成\n1:已发送完成</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_FNS</name>
+							<description>接收完成标志位\n0:没接收完成\n1:已接收完成</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DATA-->
+				<register>
+					<name>DATA</name>
+					<description>* DATA *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>在发送或接收模式下分别充当发送或接收buffer\n角色</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ETU-->
+				<register>
+					<name>ETU</name>
+					<description>* ETU *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>配置SCI7816通讯速率</description>
+							<bitRange>[12:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BGT-->
+				<register>
+					<name>BGT</name>
+					<description>* BGT *</description>
+					<addressOffset>0x2c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>配置SCI7816块反向发送时间间隔,max 6\n3</description>
+							<bitRange>[5:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CWT-->
+				<register>
+					<name>CWT</name>
+					<description>* CWT *</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CWT_SRT</name>
+							<description>CWT计时开始\n0:CWT未开始计时\n1:CWT计时立即生效</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_TMR</name>
+							<description>配置SCI7816CWT定时值,发送字节完成,接\n收起始时启动计时</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--EDC-->
+				<register>
+					<name>EDC</name>
+					<description>* EDC *</description>
+					<addressOffset>0x34</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>保存 LRC 计算结果</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IS-->
+				<register>
+					<name>IS</name>
+					<description>* IS *</description>
+					<addressOffset>0x60</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>R_SRT</name>
+							<description>接收到毛刺信号,会触发此中断,仅rx_en使能时\n会触发\nbwt期间,bwt会自动恢复重启,可以触发超时\ncwt期间,毛刺到来会重置cwt计数器,wt超时时间会变\n长</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_FLG</name>
+							<description>cwt标志, 写 '1' 清除 IS 和 IES</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_FNS</name>
+							<description>接收完成</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_FNS</name>
+							<description>发送完成</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHTCUT</name>
+							<description>tbd</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_OVF</name>
+							<description>主机写入 发送FIFO 时 发送FIFO 满,T\nFIFO_OVF 溢出中断\n接收时,主机读 FIFO 下溢可能会导致此中断断言</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_OVF</name>
+							<description>设备接收字节时 接收FIFO 满,RFIFO_O\nVF 溢出中断</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_LA</name>
+							<description>T_ITEMS &lt;= TL_WTL\n发生中断后,应首先填充T_ITEMS至水线以上,或改变水\n线,才能清除中断\nTL_WTL为0时,不触发此中断</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_HA</name>
+							<description>R_ITEMS &lt;= RH_WTL\n发生中断后,应首先读取rx_fifo至水线以下,或改变水\n线,才能清除中断\nRH_WTL为0时,不触发此中断</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_ERR</name>
+							<description>发送错误,T0 重试次数超过配置,T1 从未触发\n此错误</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_DONE</name>
+							<description>成功传输 FIFO 中的最后一个字节</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BWT_TO</name>
+							<description>接收 BWT 定时器超时中断</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_TO</name>
+							<description>接收 CWT 定时器超时中断</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_ERR</name>
+							<description>接收错误中断,T0 重试次数超过配置,T1 奇偶\n校验错误</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_DONE</name>
+							<description>成功接收到1个字节</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IE-->
+				<register>
+					<name>IE</name>
+					<description>* IE *</description>
+					<addressOffset>0x64</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>R_SRT</name>
+							<description>使能 R_SRT 中断控制位</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_FLG</name>
+							<description>使能 CWT_FLG 中断控制位</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_FNS</name>
+							<description>使能 R_FNS 中断控制位</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_FNS</name>
+							<description>使能 T_FNS 中断控制位</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHTCUT</name>
+							<description>使能 SHTCUT 中断控制位</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_OVF</name>
+							<description>使能 TFIFO_OVF 中断控制位</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_OVF</name>
+							<description>使能 RFIFO_OVF 中断控制位</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_LA</name>
+							<description>使能 TFIFO_LA 中断控制位</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_HA</name>
+							<description>使能 RFIFO_HA 中断控制位</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_ERR</name>
+							<description>使能 T_ERR 中断控制位</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_DONE</name>
+							<description>使能 T_DONE 中断控制位</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BWT_TO</name>
+							<description>使能 BWT_TO 中断控制位</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_TO</name>
+							<description>使能 CWT_TO 中断控制位</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_ERR</name>
+							<description>使能 R_ERR 中断控制位</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_DONE</name>
+							<description>使能 R_DONE 中断控制位</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IES-->
+				<register>
+					<name>IES</name>
+					<description>* IES *</description>
+					<addressOffset>0x68</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>R_SRT</name>
+							<description>使能 R_SRT 中断状态控制位</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_FLG</name>
+							<description>使能 CWT_FLG 中断状态控制位</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_FNS</name>
+							<description>使能 R_FNS 中断状态控制位</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_FNS</name>
+							<description>使能 T_FNS 中断状态控制位</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHTCUT</name>
+							<description>使能 SHTCUT 中断状态控制位</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_OVF</name>
+							<description>使能 TFIFO_OVF 中断状态控制位</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_OVF</name>
+							<description>使能 RFIFO_OVF 中断状态控制位</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TFIFO_LA</name>
+							<description>使能 TFIFO_LA 中断状态控制位</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RFIFO_HA</name>
+							<description>使能 RFIFO_HA 中断状态控制位</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_ERR</name>
+							<description>使能 T_ERR 中断状态控制位</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T_DONE</name>
+							<description>使能 T_DONE 中断状态控制位</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BWT_TO</name>
+							<description>使能 BWT_TO 中断状态控制位</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_TO</name>
+							<description>使能 CWT_TO 中断状态控制位</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_ERR</name>
+							<description>使能 R_ERR 中断状态控制位</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>R_DONE</name>
+							<description>使能 R_DONE 中断状态控制位</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL2-->
+				<register>
+					<name>CTRL2</name>
+					<description>* CTRL2 *</description>
+					<addressOffset>0x6c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>BWT_RNG</name>
+							<description>接收 BWT 定时器运行状态</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>BWTA_ST</name>
+							<description>接收 BWT 自动停止使能控制位\n0:接收 BWT 定时器不会自动停止\n1:当发送”BWTA_ST”位时,接收 BWT 定时器将\n自动停止</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BWTA_SRT</name>
+							<description>接收 BWT 自动启动使能控制位\n0:接收 BWT 定时器不会自动启动\n1:当发送”BWTA_SRT”位时,接收 BWT 定时器\n将自动启动</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BWT_RLD</name>
+							<description>写”1”接收 BWT 重新装载,始终读回”0”</description>
+							<bitRange>[27:27]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>BWT_SRT</name>
+							<description>写”1”接收 BWT 开始,始终读回”0”</description>
+							<bitRange>[26:26]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>BWT_ST</name>
+							<description>写”1”接收 BWT 停止,始终读回”0”</description>
+							<bitRange>[25:25]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>BWT_EN</name>
+							<description>接收 BWT 使能控制位\n0:接收 BWT 定时器失能\n1:接收 BWT 定时器使能</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_RNG</name>
+							<description>接收 CWT 定时器运行状态</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>CWTA_SRT</name>
+							<description>接收 CWT 自动启动使能控制位\n0:接收 CWT 定时器不会自动启动\n1:当发送”CWTA_SRT”位时,接收 CWT 定时器\n将自动启动</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWT_RLD</name>
+							<description>写”1”接收 CWT 重新装载,始终读回”0”</description>
+							<bitRange>[19:19]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>CWT_SRT</name>
+							<description>写”1”接收 CWT 开始,始终读回”0”</description>
+							<bitRange>[18:18]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>CWT_ST</name>
+							<description>写”1”接收 CWT 停止,始终读回”0”</description>
+							<bitRange>[17:17]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>CWT_EN</name>
+							<description>接收 CWT 定时器使能控制位\n0:接收 CWT 定时器失能\n1:接收 CWT 定时器使能</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWTC_DSA</name>
+							<description>清除 CWT 计数器控制位\n0:使用发送开始位或接收开始位清除 CWT 计数器\n1:不清除 CWT 计数器</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CWTS_SL</name>
+							<description>CWT开始选择控制位\n0:接收缓冲器等待或者发送字节结束\n1:接收起始位或发送起始位</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BGTS_SL</name>
+							<description>BGT开始选择控制位\n0:接收开始\n1:接收启动位,更可重新定位</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FST_FLG</name>
+							<description>发送第一个字节标志位\n0:不传输第一个字节\n1:下面的字节是要传送的第一个字节</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>FST_W</name>
+							<description>发送第一个字节等待块保护时间\n0:第一个字节发送不考虑 BGT_FLG\n1:当发送第一个字节时,等待 BGT_FLG 置”1”</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FST_RF</name>
+							<description>写1将刷新 FST_FLG 置1</description>
+							<bitRange>[9:9]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>FST_EN</name>
+							<description>使能发送第一个字节控制位\n0:第一个字节传输失能\n1:第一个字节发送开始或当 BGT_FLG 置&quot;1&quot;</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_EN</name>
+							<description>使能接收数据控制位\n0:失能\n1:使能</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TX_EN</name>
+							<description>使能发送数据控制位\n0:失能\n1:使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CWT_TO-->
+				<register>
+					<name>CWT_TO</name>
+					<description>* CWT_TO *</description>
+					<addressOffset>0x70</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 CWT 超时预设值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CWT_RLD-->
+				<register>
+					<name>CWT_RLD</name>
+					<description>* CWT_RLD *</description>
+					<addressOffset>0x74</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 CWT 重新加载值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CWT_CNT-->
+				<register>
+					<name>CWT_CNT</name>
+					<description>* CWT_CNT *</description>
+					<addressOffset>0x78</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 CWT 当前计数值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS_FSM-->
+				<register>
+					<name>STATUS_FSM</name>
+					<description>* STATUS_FSM *</description>
+					<addressOffset>0x7c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RX_WAIT</name>
+							<description>RX_WAIT_STATE</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_ERR_GAD</name>
+							<description>RX_ERROR_GUARD_STATE</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_GARD</name>
+							<description>RX_GUARD_STATE</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_ERR</name>
+							<description>RX_ERROR_STATE</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_PRT_CHK</name>
+							<description>RX_PARITY_CHECK_STATE</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_PRT</name>
+							<description>RX_PARITY_STATE</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_DTA</name>
+							<description>RX_DATA_STATE</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_STR</name>
+							<description>RX_START_STATE</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_RDY</name>
+							<description>RX_READY_STATE</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RX_IDLE</name>
+							<description>RX_IDLE_STATE</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_GAD</name>
+							<description>TX_GUARD_STATE</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_ERR_GAD</name>
+							<description>TX_ERROR_GUARD_STATE</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_ERR_DET</name>
+							<description>TX_ERROR_DETECT_STATE</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_INT_GAD</name>
+							<description>TX_INT_GUARD_STATE</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_PRT</name>
+							<description>TX_PARITY_STATE</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_DTA</name>
+							<description>TX_DATA_STATE</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_LD_DTA</name>
+							<description>TX_LOAD_DATA_STATE</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_STR</name>
+							<description>TX_START_STATE</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TX_IDLE</name>
+							<description>TX_IDLE_STATE</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--BWT_TO-->
+				<register>
+					<name>BWT_TO</name>
+					<description>* BWT_TO *</description>
+					<addressOffset>0x80</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 BWT 超时预设值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BWT_RLD-->
+				<register>
+					<name>BWT_RLD</name>
+					<description>* BWT_RLD *</description>
+					<addressOffset>0x84</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 BWT 重装载值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BWT_CNT-->
+				<register>
+					<name>BWT_CNT</name>
+					<description>* BWT_CNT *</description>
+					<addressOffset>0x88</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>接收 BWT 当前计数值</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--FIFO_CTRL-->
+				<register>
+					<name>FIFO_CTRL</name>
+					<description>* FIFO_CTRL *</description>
+					<addressOffset>0x8c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>R_ITEMS</name>
+							<description>接收 FIFO 字节数</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T_ITEMS</name>
+							<description>发送 FIFO 字节数</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RH_WTL</name>
+							<description>FIFO_ITEMS &gt;= RH_WTL 时,触\n发 RFIFO_HA 中断\n注意:RH_WTL 为0时,不触发中断</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TL_WTL</name>
+							<description>T_ITEMS &lt;= TL_WTL 时,触发 T\nFIFO_LA 中断\n注意：TL_WTL 为0时,不触发中断</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- SCI1 -->
+		<peripheral derivedFrom="MSCI0">
+			<name>MSCI1</name>
+			<baseAddress>0xf0800</baseAddress>
+		</peripheral>
+		<!-- Timer -->
+		<peripheral>
+			<name>MTIM</name>
+			<version>1.0</version>
+			<description>32 TIMER</description>
+			<groupName>TIMER</groupName>
+			<baseAddress>0xf0c00</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x78</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- Timer PWM0_PCNT -->
+				<register>
+					<dim>18</dim>
+					<dimIncrement>4</dimIncrement>
+					<name>PERIOD[%s]</name>
+					<description>period Register</description>
+					<addressOffset>0x00</addressOffset>
+					<access>read-write</access>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- Timer period -->
+						<field>
+							<name>period</name>
+							<description>period</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- Timer CTRL register -->
+				<register>
+					<name>CTRL1</name>
+					<description>pwm Control Register(0~7)</description>
+					<addressOffset>0x48</addressOffset>
+					<size>32</size>
+					<access>read-write</access>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- ENABLE: Enable timer0 -->
+						<field>
+							<name>PWM0EN</name>
+							<description>Enable or disable TIMER</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM0FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM0MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM0REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer1 -->
+						<field>
+							<name>PWM1EN</name>
+							<description>Enable or disable TIMER1</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM1FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM1MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM1REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer2 -->
+						<field>
+							<name>PWM2EN</name>
+							<description>Enable or disable TIMER2</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM2FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM2MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM2REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer3 -->
+						<field>
+							<name>PWM3EN</name>
+							<description>Enable or disable TIMER3</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM3FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM3MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM3REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer4 -->
+						<field>
+							<name>PWM4EN</name>
+							<description>Enable or disable TIMER4</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM4FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM4MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM4REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer5 -->
+						<field>
+							<name>PWM5EN</name>
+							<description>Enable or disable TIMER5</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM5FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PW5MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM5REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer6 -->
+						<field>
+							<name>PWM6EN</name>
+							<description>Enable or disable TIMER6</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM6FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM6MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM6REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ENABLE: Enable timer7 -->
+						<field>
+							<name>PWM7EN</name>
+							<description>Enable or disable TIMER7</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM7FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM7MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM7REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- Timer ctrl1 register -->
+				<register>
+					<name>CTRL2</name>
+					<description>pwm Control Register(8)</description>
+					<addressOffset>0x4c</addressOffset>
+					<size>32</size>
+					<access>read-write</access>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- ENABLE: Enable timer8 -->
+						<field>
+							<name>PWM8EN</name>
+							<description>Enable or disable TIMER</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LEVEL: high or low -->
+						<field>
+							<name>PWM8FIR</name>
+							<description>TIMER initial level</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE: PWM or TIMER -->
+						<field>
+							<name>PWM8MD</name>
+							<description>TIMER mode</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RELOAD: AUTO RELOAD -->
+						<field>
+							<name>PWM8REL</name>
+							<description>TIMER AUTO RELOAD</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- IT_EN: Enable interrupt -->
+						<field>
+							<name>IRQ_EN</name>
+							<description>The timer crresponds to the interrupt enable control bit</description>
+							<bitRange>[12:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- IT_CLR: clear irq -->
+						<field>
+							<name>IRQ_CLR</name>
+							<description>Clear interrupt control bits</description>
+							<bitRange>[21:13]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- Timer cnt -->
+				<register>
+					<dim>9</dim>
+					<dimIncrement>4</dimIncrement>
+					<size>32</size>
+					<name>CNT[%s]</name>
+					<addressOffset>0x50</addressOffset>
+					<access>read-only</access>
+					<fields>
+						<!-- Timer cnt -->
+						<field>
+							<name>cnt</name>
+							<description>cnt</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- PWM IRQ status register -->
+				<register>
+					<name>IRQ_NUM</name>
+					<description>pwm IRQ status Register</description>
+					<addressOffset>0x74</addressOffset>
+					<size>32</size>
+					<access>read-write</access>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- PWM_IRQ_PEND register -->
+						<field>
+							<name>PWM_IRQ_PEND</name>
+							<description>PWM_IRQ status</description>
+							<bitRange>[8:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--CRC-->
+		<peripheral>
+			<name>MCRC</name>
+			<version>1.0</version>
+			<description>MCRC</description>
+			<groupName>MCRC</groupName>
+			<baseAddress>0xf8204</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x7e</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--RESULT-->
+				<register>
+					<name>RESULT</name>
+					<description>* RESULT *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>存放CRC运算的初值及结果</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--MASK-->
+				<register>
+					<name>MASK</name>
+					<description>* MASK *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>计算掩码,不影响CRC最终运算结果</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DATA-->
+				<register>
+					<name>DATA</name>
+					<description>* DATA *</description>
+					<addressOffset>0x7c</addressOffset>
+					<size>16</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>存放参与CRC运算的数据</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--RCC-->
+		<peripheral>
+			<name>MRCC</name>
+			<version>1.0</version>
+			<description>MRCC</description>
+			<groupName>MRCC</groupName>
+			<baseAddress>0xf8400</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x2c</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--HCLK_CTRL-->
+				<register>
+					<name>HCLK_CTRL</name>
+					<description>* HCLK_CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>UART_SEL</name>
+							<description>UART时钟clk_uart选择。\n0: rc192m分频后生成的48M时钟\n1: pll_hsi_48m,切换PLL频率会抖动\n2: pll_hse_48m,切换PLL频率会抖动</description>
+							<bitRange>[15:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>USB_SEL</name>
+							<description>USB时钟clk_usb选择。\n0: rc192m分频后生成的48M时钟\n1: pll_hsi_48m,切换PLL频率会抖动\n2: pll_hse_48m,切换PLL频率会抖动</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PCLK_CTRL-->
+				<register>
+					<name>PCLK_CTRL</name>
+					<description>* PCLK_CTRL *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>DIV_EN</name>
+							<description>PCLK分频使能</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEL</name>
+							<description>PCLK使用的分频值选择\n0: 1分频\n1: 2分频\n2: 4分频\n3: 8分频</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RSA_CLK-->
+				<register>
+					<name>RSA_CLK</name>
+					<description>* RSA_CLK *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CLK_CFG</name>
+							<description>每16个clk_rsa中,前n个可以强制为0,此\n寄存器用于选择n值,从这里输出的时钟最终给到RSA模块1\n : 每16个clk_rsa中,前3个周期强制为0\n2, 4, 5 :每16个clk_rsa中,前2个周期强\n制为0\n3 : 每16个clk_rsa中,第一个强制为0\n6, 7 :clk_rsa输入等于输出\nOthers : 每16个clk_rsa中,前7个周期强\n制为0</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLK_EN-->
+				<register>
+					<name>CLK_EN</name>
+					<description>* CLK_EN *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RC48M</name>
+							<description>RC48M数字模块时钟开关</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RV_REG</name>
+							<description>RV_REG数字模块时钟开关</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RV_SYS</name>
+							<description>RV_SYS数字模块时钟开关</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MPU_DMA</name>
+							<description>MPU_DMA数字模块时钟开关</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MEMCP</name>
+							<description>MEMCP数字模块时钟开关</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHGPUMP</name>
+							<description>CHGPUMP数字模块时钟开关</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SD</name>
+							<description>SD数字模块时钟开关</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DCMI</name>
+							<description>DCMI数字模块时钟开关</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DAC</name>
+							<description>DAC数字模块时钟开关</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI</name>
+							<description>HSPI数字模块时钟开关</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM</name>
+							<description>PSRAM数字模块时钟开关</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MSR_ADC</name>
+							<description>7811_ADC数字模块时钟开关</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MSR</name>
+							<description>7811数字模块时钟开关</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UART</name>
+							<description>UART数字模块时钟开关</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SM4</name>
+							<description>SM4数字模块时钟开关</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SCI1</name>
+							<description>SCI1数字模块时钟开关</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SCI0</name>
+							<description>SCI0数字模块时钟开关</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO</name>
+							<description>GPIO数字模块时钟开关</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AES</name>
+							<description>AES数字模块时钟开关</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RSA</name>
+							<description>RSA数字模块时钟开关</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DES</name>
+							<description>DES数字模块时钟开关</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SPI</name>
+							<description>SPI数字模块时钟开关</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>USB</name>
+							<description>USB数字模块时钟开关</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>WDT</name>
+							<description>WDT数字模块时钟开关</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PWM</name>
+							<description>PWM数字模块时钟开关</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CRC</name>
+							<description>CRC数字模块时钟开关</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHA</name>
+							<description>SHA数字模块时钟开关</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>QSPI</name>
+							<description>qspi数字模块时钟开关</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RNG</name>
+							<description>rng数字模块时钟开关</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--MCU_CLK-->
+				<register>
+					<name>MCU_CLK</name>
+					<description>* MCU_CLK *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RAND_MASK</name>
+							<description>DIV_HI和DIV_LO会加上(随机数&amp; RA\nND_MASK)</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DIV_HI</name>
+							<description>输入给MCU的时钟的低电平持续时间 = (DIV\n_HI +1)个clk</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DIV_LO</name>
+							<description>输入给MCU的时钟的低电平持续时间 = (DIV\n_LO+1)个clk</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RAND_EN</name>
+							<description>为1则使能MCU时钟随机功能</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DIV_SEL</name>
+							<description>MCU时钟分频选择\n0：选择非分频时钟作为 clk_mcu\n1：选择分频时钟作为clk_mcu\n注意：当从'1'变为'0'时,应先设置div_sel为'\n0',延迟至少两个周期,然后清除div_en,不要同时清\n除这两位。当从'0'变为'1'时,应先设置div_en为\n'1',延迟至少两个周期,然后设置</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DIV_EN</name>
+							<description>为1则使能MCU时钟分频</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RC_32K</name>
+							<description>为1则使能内部RC32K（LSI）为系统时钟,同\n时屏蔽其他所有的设置</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEL</name>
+							<description>MCU时钟来源选择\n0: rc192m\n1: pll_192M\n2: pll_256M\n3: pll_48M,</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PER1_CLK-->
+				<register>
+					<name>PER1_CLK</name>
+					<description>* PER1_CLK *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>QSPI_DIV_HI</name>
+							<description>输入给QSPI的时钟的低电平持续时间 = (QS\nPI_DIV_HI+1)个clk</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>QSPI_DIV_LO</name>
+							<description>输入给QSPI的时钟的低电平持续时间 = (QS\nPI_DIV_LO+1)个clk</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>QSPI_SEL</name>
+							<description>QSPI总线时钟来源选择\n0: CLK_MCU\n1: RC192M\n2: pll_192M\n3: pll_48M</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_DIV_HI</name>
+							<description>输入给AHB的时钟的高电平持续时间 = (AHB\n_DIV_HI +1)个clk</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_DIV_LO</name>
+							<description>输入给AHB的时钟的低电平持续时间 = (AHB\n_DIV_LO+1)个clk</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_RAND_MASK</name>
+							<description>AHB_DIV_HI和AHB_DIV_LO会加上\n(随机数&amp;AHB_RAND_MASK)</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_RAND_EN</name>
+							<description>为1则使能AHB总线时钟随机功能</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_SEL</name>
+							<description>AHB总线时钟来源选择\n0: CLK_MCU\n1: RC192M\n2: pll_192M\n3: pll_48M</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PER2_CLK-->
+				<register>
+					<name>PER2_CLK</name>
+					<description>* PER2_CLK *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>HSPI_DIV_HI</name>
+							<description>输入给HSPI的时钟的高电平持续时间 = (HS\nPI_DIV_HI +1)个clk</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI_DIV_LO</name>
+							<description>输入给HSPI的时钟的低电平持续时间 = (HS\nPI_DIV_LO+1)个clk</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI_DIV_EN</name>
+							<description>为1则使能HSPI时钟分频</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI_DIV_SEL</name>
+							<description>HSPI时钟分频选择\n0：选择非分频时钟作为 clk_hspi\n1：选择分频时钟作为 clk_hspi</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI_PLL_SEL</name>
+							<description>HSPI时钟来源选择\n0: pll_hsi\n1: pll_hse</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HSPI_SEL</name>
+							<description>PSRAM总线时钟来源选择\n0: CLK_MCU\n1: RC192M\n2: pll_192M\n3: pll_256M</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_DIV_HI</name>
+							<description>输入给PSRAM的时钟的高电平持续时间 = (P\nSRAM_DIV_HI +1)个clk</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_DIV_LO</name>
+							<description>输入给PSRAM的时钟的低电平持续时间 = (P\nSRAM_DIV_LO+1)个clk</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_DIV_EN</name>
+							<description>为1则使能PSRAM时钟分频</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_DIV_SEL</name>
+							<description>PSRAM时钟分频选择\n0：选择非分频时钟作为 clk_psram\n1：选择分频时钟作为clk_psram</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_PLL_SEL</name>
+							<description>PSRAM时钟来源选择\n0: pll_hsi\n1: pll_hse</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PSRAM_SEL</name>
+							<description>PSRAM总线时钟来源选择\n0: CLK_MCU\n1: RC192M\n2: pll_192M\n3: pll_256M</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PER3_CLK-->
+				<register>
+					<name>PER3_CLK</name>
+					<description>* PER3_CLK *</description>
+					<addressOffset>0x1c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>GPIO1_DIV_HI</name>
+							<description>GPIO奇数脚输出的时钟的高电平持续时间 = (\nGPIO1_DIV_HI+1)个clk</description>
+							<bitRange>[31:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO1_DIV_LO</name>
+							<description>GPIO奇数脚输出的时钟的低电平持续时间 = (\nGPIO1_DIV_LO+1)个clk</description>
+							<bitRange>[29:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO1_EN</name>
+							<description>GPIO奇数脚时钟输出使能</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO1_SEL</name>
+							<description>GPIO奇数脚时钟输出,需要把奇数的GPIO配置\n成 55:GPIO_CLK_OUT\n0: clk_rc48m\n1: clk_pll_hsi_48m\n2: clk_pll_hse_48m</description>
+							<bitRange>[25:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO0_DIV_HI</name>
+							<description>GPIO偶数脚输出的时钟的高电平持续时间 = (\nGPIO0_DIV_HI+1)个clk</description>
+							<bitRange>[23:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO0_DIV_LO</name>
+							<description>GPIO偶数脚输出的时钟的低电平持续时间 = (\nGPIO0_DIV_LO+1)个clk</description>
+							<bitRange>[21:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO0_EN</name>
+							<description>GPIO偶数脚时钟输出使能</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>GPIO0_SEL</name>
+							<description>GPIO偶数脚时钟输出,需要把偶数的GPIO配置\n成 55:GPIO_CLK_OUT\n0: clk_rc48m\n1: clk_pll_hsi_48m\n2: clk_pll_hse_48m</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ADAC_DIV_HI</name>
+							<description>输入给ADAC的时钟的高电平持续时间 = (AD\nAC_DIV_HI +1)个clk</description>
+							<bitRange>[15:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ADAC_DIV_LO</name>
+							<description>输入给ADAC的时钟的低电平持续时间 = (AD\nAC_DIV_LO+1)个clk</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ADAC_EN</name>
+							<description>ADAC时钟分频使能来源选择\n0：选择非分频时钟作为 clk_adac\n1：选择分频时钟作为clk_adac</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ADAC_SEL</name>
+							<description>ADAC时钟来源选择\n0: rc48m\n1: pll_hsi_48m\n2: pll_hse_48m</description>
+							<bitRange>[9:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICE_DIV_HI</name>
+							<description>输入给ICE的时钟的高电平持续时间 = (ICE\n_DIV_HI +1)个clk</description>
+							<bitRange>[7:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICE_DIV_LO</name>
+							<description>输入给ICE的时钟的低电平持续时间 = (ICE\n_DIV_LO+1)个clk</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICE_EN</name>
+							<description>ICE时钟分频使能来源选择\n0：选择非分频时钟作为 clk_ice\n1：选择分频时钟作为clk_ice</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICE_SEL</name>
+							<description>ICE时钟来源选择\n0: rc48m\n1: pll_hsi_48m\n2: pll_hse_48m</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLK_PLL_SEL-->
+				<register>
+					<name>CLK_PLL_SEL</name>
+					<description>* CLK_PLL_SEL *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RSA_PLL_SEL</name>
+							<description>RSA的时钟来源选择\n0x5: PLL_HSE\nOthers:PLL_HSI</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MCU_PLL_SEL</name>
+							<description>MCU的时钟来源选择\n0x5: PLL_HSE\nOthers:PLL_HSI</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>QSPI_PLL_SEL</name>
+							<description>QSPI的时钟来源选择\n0x5: PLL_HSE\nOthers:PLL_HSI</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AHB_PLL_SEL</name>
+							<description>AHB的时钟来源选择\n0x5: PLL_HSE\nOthers:PLL_HSI</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PLL_SEL_LOCK</name>
+							<description>为1后锁定AHB,QSPI,MCU,RSA的时钟\n选择,且无法解锁。</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--OSC32K_CALI-->
+				<register>
+					<name>OSC32K_CALI</name>
+					<description>* OSC32K_CALI *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TIME</name>
+							<description>校准持续时长,校准时间长度为(2^cali_ti\nme)个 OSC32K 周期</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DONE</name>
+							<description>校准完成信号\n校准开始后,此信号会变成'0',校准完成后,此信号会变为\n'1'</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>START</name>
+							<description>校准启动信号\n写'1'后,延迟1us,再写'0',上升沿触发校准开始</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CNT</name>
+							<description>time所表示的时间长度内,48M时钟计数值\n注意：校准时钟源使用的是clk_gpio1_sel选择的\n48M时钟</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLK_RSA-->
+				<register>
+					<name>CLK_RSA</name>
+					<description>* CLK_RSA *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>DIV_HI</name>
+							<description>输入给RSA的时钟的高电平持续时间 = (DIV\n_HI+1)个clk</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DIV_LO</name>
+							<description>输入给RSA的时钟的低电平持续时间 = (DIV\n_LO+1)个clk</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RAND_MASK</name>
+							<description>DIV_HI和DIV_LO会加上(随机数&amp; RA\nND_MASK)</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RAND_EN</name>
+							<description>RSA时钟随机使能\n0:失能RSA时钟随机\n1:使能RSA时钟随机</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEL</name>
+							<description>RSA时钟来源选择\n0: cpu\n1: rc192m\n2: pll_out_norm, (192M)\n3: pll_out_max, (256M)</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--SYSCTRL-->
+		<peripheral>
+			<name>MSYSCTRL</name>
+			<version>1.0</version>
+			<description>MSYSCTRL</description>
+			<groupName>MSYSCTRL</groupName>
+			<baseAddress>0xf8520</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x48</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CHGR_EVENT_IRQ-->
+				<register>
+					<name>CHGR_EVENT_IRQ</name>
+					<description>* CHGR_EVENT_IRQ *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EVENT1_EN</name>
+							<description>chgr_event[11:10]事件检测使能,\n使能中断前必须先使能这一比特,power_key一直使能\n,无法更改</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EVENT0_EN</name>
+							<description>chgr_event[9:0]事件检测使能,使能\n中断前必须先使能这一比特</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>chgr中断使能总开关</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PWK</name>
+							<description>power key irq</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_OV</name>
+							<description>ad_lpm_vbat_ov_flag</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DET_AON</name>
+							<description>ad_lpm_chgr_in_det_aon</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CC_OV_CV</name>
+							<description>ad_lpm_chgr_cc_ov_cv</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CC</name>
+							<description>ad_lpm_chgr_dppm_ov_cc</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CV</name>
+							<description>ad_lpm_chgr_dppm_ov_cv</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PGOOD</name>
+							<description>ad_lpm_chgr_pgood</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UVLO_OK_AON</name>
+							<description>ad_lpm_chgr_uvlo_ok_aon</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESET</name>
+							<description>ad_lpm_chgr_reset</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICHG</name>
+							<description>ad_lpm_chgr_state_ichg</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IND</name>
+							<description>ad_lpm_chgr_state_ind</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RCH_EN</name>
+							<description>ad_lpm_chgr_state_rch_en</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_LV</name>
+							<description>ad_lpm_chgr_state_vbat_l\nv</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CHGR_EVENT_ICTRL-->
+				<register>
+					<name>CHGR_EVENT_ICTRL</name>
+					<description>* CHGR_EVENT_ICTRL *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PWK_IT</name>
+							<description>power_key</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_OV_IT</name>
+							<description>ad_lpm_vbat_ov_flag</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DET_AON_IT</name>
+							<description>ad_lpm_chgr_in_det_aon</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CC_OV_CV_IT</name>
+							<description>ad_lpm_chgr_cc_ov_cv</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CC_IT</name>
+							<description>ad_lpm_chgr_dppm_ov_cc</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CV_IT</name>
+							<description>ad_lpm_chgr_dppm_ov_cv</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>PGOOD_IT</name>
+							<description>ad_lpm_chgr_pgood</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UVLO_OK_AON_IT</name>
+							<description>ad_lpm_chgr_uvlo_ok_aon</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RESET_IT</name>
+							<description>ad_lpm_chgr_reset</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICHG_IT</name>
+							<description>ad_lpm_chgr_state_ichg</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>IND_IT</name>
+							<description>ad_lpm_chgr_state_ind</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RCH_EN_IT</name>
+							<description>ad_lpm_chgr_state_rch_en</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBAT_LV_IT</name>
+							<description>ad_lpm_chgr_state_vbat_l\nv 中断类型\n0: 低电平 \n1: 高电平</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PWK_IE</name>
+							<description>power_key</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_OV_IE</name>
+							<description>ad_lpm_vbat_ov_flag</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DET_AON_IE</name>
+							<description>ad_lpm_chgr_in_det_aon</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CC_OV_CV_IE</name>
+							<description>ad_lpm_chgr_cc_ov_cv</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CC_IE</name>
+							<description>ad_lpm_chgr_dppm_ov_cc</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CV_IE</name>
+							<description>ad_lpm_chgr_dppm_ov_cv</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>PGOOD_IE</name>
+							<description>ad_lpm_chgr_pgood</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UVLO_OK_AON_IE</name>
+							<description>ad_lpm_chgr_uvlo_ok_aon</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RESET_IE</name>
+							<description>ad_lpm_chgr_reset</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICHG_IE</name>
+							<description>ad_lpm_chgr_state_ichg</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>IND_IE</name>
+							<description>ad_lpm_chgr_state_ind</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RCH_EN_IE</name>
+							<description>ad_lpm_chgr_state_rch_en</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBAT_LV_IE</name>
+							<description>ad_lpm_chgr_state_vbat_l\nv 中断使能\n0: 禁止\n1: 使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RNG_CTRL-->
+				<register>
+					<name>RNG_CTRL</name>
+					<description>* RNG_CTRL *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+				</register>
+				<!--RNG_DATA0-->
+				<register>
+					<name>RNG_DATA0</name>
+					<description>* RNG_DATA0 *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>访问此寄存器可以获得随机数</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RNG_DATA1-->
+				<register>
+					<name>RNG_DATA1</name>
+					<description>* RNG_DATA1 *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>访问此寄存器可以获得随机数</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RNG_DATA2-->
+				<register>
+					<name>RNG_DATA2</name>
+					<description>* RNG_DATA2 *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>访问此寄存器可以获得随机数</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RNG_DATA3-->
+				<register>
+					<name>RNG_DATA3</name>
+					<description>* RNG_DATA3 *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>访问此寄存器可以获得随机数</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--rom_switch-->
+				<register>
+					<name>rom_switch</name>
+					<description>* rom_switch *</description>
+					<addressOffset>0x1c</addressOffset>
+					<size>8</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ALARM_EN</name>
+							<description>报警使能\n1：使能报警\n0：失能报警</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SRAM_NEXE</name>
+							<description>RAM不能跑程序,写0无效(产品阶段固定为1)</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOCK_ANA</name>
+							<description>锁定模拟寄存器</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOCK_OTP</name>
+							<description>lock_otp \n写1锁定寄存器 sfr_otphid_addr / sf\nr_otpuser_addr</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DEBUG_EN</name>
+							<description>使能DEBUG功能(产品阶段固定为0)\n0: 失能debug功能;\n1: 使能debug功能</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOCK_SEC</name>
+							<description>loc_sec</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ROM_SW</name>
+							<description>写1后置位,写0无效,模块复位后,恢复到0。(产\n品阶段固定为1)\n锁定的寄存器：\nALARM_EN\nBTM_EN\ngpio_ICE\ngpio_SWDAT\nsfr_ramkey_sel\nsfr_medcon_wr\nQAES regs</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LPM_BUSY_CFG-->
+				<register>
+					<name>LPM_BUSY_CFG</name>
+					<description>* LPM_BUSY_CFG *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>AON_STATE</name>
+							<description>0: lpm/rtc register acce\nss finish\n1: lpm/rtc register access o\nngoing</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>LPM_STATE</name>
+							<description>0: lpm access finish\n1: lpm access ongoing</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>RTC_STATE</name>
+							<description>0: rtc access finish\n1: rtc access ongoing</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>LPM_EN</name>
+							<description>0: 总线访问LPM时,不等待LPM完成直接返回\n,软件查询STATE标志确定是否访问完成\n1: 总线访问LPM时,等待LPM访问完成才释放总线,软\n件无须查询STATE标志</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RTC_EN</name>
+							<description>0: 总线访问RTC时,不等待RTC完成直接返回\n,软件查询STATE标志确定是否访问完成\n1: 总线访问RTC时,等待LPM访问完成才释放总线,软\n件无须查询STATE标志</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LPM_RDATA-->
+				<register>
+					<name>LPM_RDATA</name>
+					<description>* LPM_RDATA *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RDATA</name>
+							<description>lpm access read data</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--RTC_RDATA-->
+				<register>
+					<name>RTC_RDATA</name>
+					<description>* RTC_RDATA *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RDATA</name>
+							<description>rtc access read data</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--AON_RDATA-->
+				<register>
+					<name>AON_RDATA</name>
+					<description>* AON_RDATA *</description>
+					<addressOffset>0x2c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RDATA</name>
+							<description>lpm/rtc access read data\n, the last read value of lpm\n or rtc</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--pwk_state-->
+				<register>
+					<name>pwk_state</name>
+					<description>* pwk_state *</description>
+					<addressOffset>0x40</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>STATE</name>
+							<description>POWER_KEY按键状态</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--VIO_IRQ-->
+				<register>
+					<name>VIO_IRQ</name>
+					<description>* VIO_IRQ *</description>
+					<addressOffset>0x44</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VIO1_STATUS</name>
+							<description>vio1 pgood状态\n1: vio1 电源电压正常\n0: vio1电源电压低于设定值</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VIO0_STATUS</name>
+							<description>vio pgood状态\n1: vio 电源电压正常\n0: vio电源电压低于设定值</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VIO1_IRQ</name>
+							<description>vio1 pgood irq 状态\n1: vio1 电压低于配置值,vio1_pgood由高\n变为低</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VIO0_IRQ</name>
+							<description>vio pgood irq 状态\n1: vio 电压低于配置值,vio_pgood由高变为\n低</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IRQ_STATE</name>
+							<description>vio pgood 中断总状态\n1: vio0或vio1其中之一电压低于配置值</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VIO1_EN</name>
+							<description>vio1 pgood 中断开关</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VIO0_EN</name>
+							<description>vio0 pgood 中断开关</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>vio 中断总开关</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--RSTGEN-->
+		<peripheral>
+			<name>MRSTGEN</name>
+			<version>1.0</version>
+			<description>MRSTGEN</description>
+			<groupName>MRSTGEN</groupName>
+			<baseAddress>0xf8574</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0xc</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--RST_EN-->
+				<register>
+					<name>RST_EN</name>
+					<description>* RST_EN *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>GPIO_SEL</name>
+							<description>复位GPIO选择\n0: ice_rst/m0_dbg_rst复位外设时,不\n复位GPIO\n1: ice_rst/m0_dbg_rst复位外设时,复\n位GPIO</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TS_U</name>
+							<description>1: 使能低温自检复位功能</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TS_O</name>
+							<description>1: 使能高温自检复位功能</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_U</name>
+							<description>1: 使能纽扣电池3.3v输出低压自检复位功能</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_O</name>
+							<description>1: 使能纽扣电池3.3v输出高压自检复位功能</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DVDD_U</name>
+							<description>1: 使能纽扣电池1.2v输出低压自检复位功能</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_U</name>
+							<description>1: 使能锂电池3.3v输出低压自检复位功能</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_O</name>
+							<description>1: 使能锂电池3.3v输出高压自检复位功能</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VDDSEC_U</name>
+							<description>1: 使能安全域电源1.2v输出低压自检复位功能</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>WDT</name>
+							<description>1: 使能看门狗复位功能</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOFT</name>
+							<description>1: 使能软件复位功能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RST_TYPE-->
+				<register>
+					<name>RST_TYPE</name>
+					<description>* RST_TYPE *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TS_U</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TS_O</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_U</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_O</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DVDD_U</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_U</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_O</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VDDSEC_U</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>WDT</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOFT</name>
+							<description>软件可读写,若对应的复位信号触发,则硬件自动置1\n,清0需由软件完成。</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RESET-->
+				<register>
+					<name>RESET</name>
+					<description>* RESET *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RESET</name>
+							<description>复位使能:\n写入 &quot;0x55&quot; ,触发软件复位,sw_rst\n写入 &quot;0x50&quot; ,触发软件复位,ic_rst\n写入 &quot;0xAB“ ,触发sci复位,rst_sci\n写入 &quot;0xAE“ ,触发sci2复位,rst_sci_\n2\n写入 &quot;0xC3&quot; ,触发7811复位,rst_7811</description>
+							<bitRange>[7:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--SECURE-->
+		<peripheral>
+			<name>MSECURE</name>
+			<version>1.0</version>
+			<description>MSECURE</description>
+			<groupName>MSECURE</groupName>
+			<baseAddress>0xf85c0</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x1c</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>THRESHOLD</name>
+							<description>sensor检测警报持续时间门限,大于此门限发出\n警报,否则不报警。\n时间门限值: (2^sensor_delay)*hclk</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEC_EN</name>
+							<description>1: sensor检测使能。\n[7]: 低温自检,ad_ts_uth/uthb\n[6]: 高温自检,ad_ts_oth/othb\n[5]: 纽扣电池3.3v输出低压自检,ad_vbat_\nuvh/uvhb\n[4]: 纽扣电池3.3v输出高压自检,ad_vbat_\novh/ovhb\n[3]: 纽扣电池1.2v输出低压自检,ad_dvddl\npm_uvh/uvhb\n[2]: 锂电池3.3v输出低压自检,ad_vsec_u\nv/uvb\n[1]: 锂电池3.3v输出高压自检,ad_vsec_o\nv/ovb\n[0]: 安全域电源1.2v输出低压自检,ad_vdds\nec_uv/uvb</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--result-->
+				<register>
+					<name>result</name>
+					<description>* result *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TS_UTHB</name>
+							<description>低温自检电路结果输出</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TS_UTH</name>
+							<description>低温自检电路结果输出</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TS_OTHB</name>
+							<description>高温自检电路结果输出</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TS_OTH</name>
+							<description>高温自检电路结果输出</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBUT_UVHB</name>
+							<description>纽扣电池3.3v输出低压自检电路结果输出</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBUT_UVH</name>
+							<description>纽扣电池3.3v输出低压自检电路结果输出</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBUT_OVHB</name>
+							<description>纽扣电池3.3v输出高压自检电路结果输出</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VBUT_OVH</name>
+							<description>纽扣电池3.3v输出高压自检电路结果输出</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DVDDLPM_UVHB</name>
+							<description>纽扣电池1.2v输出低压自检电路结果输出</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>DVDDLPM_UVH</name>
+							<description>纽扣电池1.2v输出低压自检电路结果输出</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VSEC_UHVB</name>
+							<description>锂电池3.3v输出低压自检电路结果输出</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VSEC_UVH</name>
+							<description>锂电池3.3v输出低压自检电路结果输出</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VSEC_OVHB</name>
+							<description>锂电池3.3v输出高压自检电路结果输出</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VSEC_OVH</name>
+							<description>锂电池3.3v输出高压自检电路结果输出</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VDDSEC_UHVB</name>
+							<description>安全域电源1.2v输出低压自检电路结果输出</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>VDDSEC_UVH</name>
+							<description>安全域电源1.2v输出低压自检电路结果输出</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>STATE</name>
+							<description>1: 对应检测项报警。\n[8]: 低温自检警报\n[7]: 高温自检警报\n[6]: 纽扣电池3.3v输出低压自检警报\n[5]: 纽扣电池3.3v输出高压自检警报\n[4]: 纽扣电池1.2v输出低压自检警报\n[3]: 锂电池3.3v输出低压自检警报\n[2]: 锂电池3.3v输出高压自检警报\n[1]: 安全域电源1.2v输出低压自检警报</description>
+							<bitRange>[8:1]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--RTC_IE-->
+				<register>
+					<name>RTC_IE</name>
+					<description>* RTC_IE *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LSE_IRQ</name>
+							<description>rtc_lse_irq flag, 仅指中断标志\n,清除需要使用RTC_LSE寄存器</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>LSI_IRQ</name>
+							<description>rtc_lsi_irq flag, 仅指中断标志\n,清除需要使用RTC_LSI寄存器</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>LSE_IE</name>
+							<description>1: enable rtc_lse irq</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LSI_IE</name>
+							<description>1: enable rtc_lsi irq</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IE-->
+				<register>
+					<name>IE</name>
+					<description>* IE *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LPM_IRQ</name>
+							<description>lpm security irq status</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>CORE_IE</name>
+							<description>CORE SEC中断开关\n1: enable core security even\nt interrupt</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>SEC中断总开关\nboth lpm security events and\n core security events will t\nrigger secure_irq</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SENSOR_CTRL-->
+				<register>
+					<name>SENSOR_CTRL</name>
+					<description>* SENSOR_CTRL *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VDDSEC_SEL</name>
+							<description>threshold voltage select\nion(sim tt 50deg, voltage fr\nom low to high): \n0000: 867mV\n0001: 887mV\n0010: 907mV\n0011: 927mV\n0100: 947mV\n0101: 967mV\n0110: 987mV\n0111: 1005mV\n1000: 1025mV\n1001: 1045mV\n1010: 1065mV\n1011: 1085mV\n1100: 1105mV\n1101: 1125mV\n1110: 1145mV\n1111: 1165mV</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_H_SEL</name>
+							<description>threshold voltage select\nion(sim tt 50deg, voltage fr\nom low to high):\n0000: 3.369\n0001: 3.419\n0010: 3.469\n0011: 3.522\n0100: 3.576\n0101: 3.631\n0110: 3.688\n0111: 3.748\n1000: 3.809\n1001: 3.872\n1010: 3.937\n1011: 4.005\n1100: 4.074\n1101: 4.147\n1110: 4.222\n1111: 4.299</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_L_SEL</name>
+							<description>threshold voltage select\nion(sim tt 50deg, voltage fr\nom low to high):\n0000: 1.938\n0001: 1.971\n0010: 2.005\n0011: 2.040\n0100: 2.076\n0101: 2.113\n0110: 2.152\n0111: 2.193\n1000: 2.235\n1001: 2.278\n1010: 2.324\n1011: 2.371\n1100: 2.420\n1101: 2.471\n1110: 2.525\n1111: 2.580</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VDDSEC_EN</name>
+							<description>0x5, disable sensor, els\ne enable  sensor</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VSEC_EN</name>
+							<description>0x5, disable sensor, els\ne enable sensor</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- GPIO -->
+		<peripheral>
+			<name>MGPIO</name>
+			<version>1.0</version>
+			<description>8 GPIO</description>
+			<groupName>MGPIO</groupName>
+			<baseAddress>0xf8700</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0xe1</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- GPIO_CTRL -->
+				<register>
+					<dim>80</dim>
+					<dimIncrement>1</dimIncrement>
+					<name>CTRL[%s]</name>
+					<addressOffset>0x00</addressOffset>
+					<size>8</size>
+					<fields>
+						<!-- FUN -->
+						<field>
+							<name>FUNC</name>
+							<description>GPIO function</description>
+							<bitRange>[5:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MODE -->
+						<field>
+							<name>MODE</name>
+							<description>GPIO mode</description>
+							<bitRange>[7:6]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_EN -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>INTR[%s]</name>
+					<addressOffset>0x80</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_LEVEL -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>IRQ_LEVEL[%s]</name>
+					<addressOffset>0x90</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_RISE -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>IRQ_RISE[%s]</name>
+					<addressOffset>0xa0</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_FALL -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>IRQ_FALL[%s]</name>
+					<addressOffset>0xB0</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_STATUS -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>IRQ_STATUS[%s]</name>
+					<addressOffset>0xc0</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IRQ_NUM -->
+				<register>
+					<name>IRQ_NUM</name>
+					<description>GPIO_IRQ_INDEX register</description>
+					<addressOffset>0xcf</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- GPIO_IRQ_INDEX -->
+						<field>
+							<name> INDEX</name>
+							<description>GPIO_IRQ_INDEX</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- IN_LEVEL -->
+				<register>
+					<dim>5</dim>
+					<dimIncrement>2</dimIncrement>
+					<name>IN_LEVEL[%s]</name>
+					<addressOffset>0xd0</addressOffset>
+					<size>16</size>
+					<fields>
+						<field>
+							<name>PIN0</name>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN1</name>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN2</name>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN3</name>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN4</name>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN5</name>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN6</name>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN7</name>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN8</name>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN9</name>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN10</name>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN11</name>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN12</name>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN13</name>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN14</name>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PIN15</name>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- OD_CTRL -->
+				<register>
+					<name>OD_CTRL</name>
+					<description>GPIO_OD register</description>
+					<addressOffset>0xe0</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- GPIO_OD -->
+						<field>
+							<name>PA10</name>
+							<description>GPIO_OD</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PB6</name>
+							<description>GPIO_OD</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PC1</name>
+							<description>GPIO_OD</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PC8</name>
+							<description>GPIO_OD</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PD0</name>
+							<description>GPIO_OD</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PD12</name>
+							<description>GPIO_OD</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PE12</name>
+							<description>GPIO_OD</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PE6</name>
+							<description>GPIO_OD</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- DMA -->
+		<peripheral>
+			<name>MDMA</name>
+			<version>1.0</version>
+			<description>32 DMA</description>
+			<baseAddress>0xf8800</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x1c</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- DMA_SRC_ADDR -->
+				<register>
+					<name>SRC_ADDR</name>
+					<description>DMA_SRC_ADDR register</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_SRC_ADDR -->
+						<field>
+							<name>VAL</name>
+							<description>source address</description>
+							<bitRange>[31:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_DEST_ADDR -->
+				<register>
+					<name>DEST_ADDR</name>
+					<description>DMA_DEST_ADDR register</description>
+					<addressOffset>0x04</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_DEST_ADDR -->
+						<field>
+							<name>VAL</name>
+							<description>dest address</description>
+							<bitRange>[31:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_LEN_LOW -->
+				<register>
+					<name>LEN_LOW</name>
+					<description>DMA_LEN_LOW register</description>
+					<addressOffset>0x08</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_RX_LEN_LOW -->
+						<field>
+							<name>RX_LEN_L</name>
+							<description>buff len</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DMA_TX_LEN_LOW -->
+						<field>
+							<name>TX_LEN_L</name>
+							<description>buff len</description>
+							<bitRange>[31:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_CFG_LEN_HIGH -->
+				<register>
+					<name>CTRL</name>
+					<description>DMA control register</description>
+					<addressOffset>0x0c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- LOOPBACK_MODE -->
+						<field>
+							<name>LOOPBACK</name>
+							<description>loop back mode</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- INT_MODE -->
+						<field>
+							<name>INT_MODE</name>
+							<description>enable interrupt</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- R_ADDR_LOCK -->
+						<field>
+							<name>RADDR_LOCK</name>
+							<description>lock read addr</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- W_ADDR_LOCK -->
+						<field>
+							<name>WADDR_LOCK</name>
+							<description>lock write addr</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DMA_RX_LEN_HIGH -->
+						<field>
+							<name>RX_LEN_H</name>
+							<description>rx len</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DMA_TX_LEN_HIGH -->
+						<field>
+							<name>TX_LEN_H</name>
+							<description>tx len</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DMA_PP_BUF -->
+						<field>
+							<name>PP_BUF</name>
+							<description>flag slave/dcmi</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RESET_BIT -->
+						<field>
+							<name>RESET</name>
+							<description>init write 0,write 1</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- CLEAR_INT -->
+						<field>
+							<name>CLEAR_INT</name>
+							<description>clear DMA int</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- START_BIT -->
+						<field>
+							<name>START</name>
+							<description>enable DMA</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_STATUS -->
+				<register>
+					<name>STATUS</name>
+					<description>DMA status</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_STATUS -->
+						<field>
+							<name>DONE</name>
+							<description>DMA status</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_RPTR -->
+				<register>
+					<name>RPTR</name>
+					<description>Sends the current address of the BUF read pointer</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_RPTR -->
+						<field>
+							<name>VAL</name>
+							<description>Sends the current address of the BUF read pointer</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- DMA_WPRT -->
+				<register>
+					<name>WPRT</name>
+					<description>received the current address of the BUF read pointer</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- DMA_WPRT -->
+						<field>
+							<name>VAL</name>
+							<description>receiced the current address of the BUF read pointer</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- DMA_QSPI -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_QSPI</name>
+			<version>1.0</version>
+			<description>QSPI</description>
+			<alternatePeripheral>MDMA</alternatePeripheral>
+			<baseAddress>0xf8800</baseAddress>
+		</peripheral>
+		<!-- DMA_SPI0 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_SPI0</name>
+			<baseAddress>0xf8900</baseAddress>
+		</peripheral>
+		<!-- DMA_SPI1 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_SPI1</name>
+			<baseAddress>0xf8a00</baseAddress>
+		</peripheral>
+		<!-- DMA_UART0 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_UART0</name>
+			<baseAddress>0xf8b00</baseAddress>
+		</peripheral>
+		<!-- DMA_UART1 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_UART1</name>
+			<baseAddress>0xf8c00</baseAddress>
+		</peripheral>
+		<!-- DMA_UART2 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_UART2</name>
+			<baseAddress>0xf8d00</baseAddress>
+		</peripheral>
+		<!-- DMA_UART3 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_UART3</name>
+			<baseAddress>0xf8e00</baseAddress>
+		</peripheral>
+		<!-- DMA_7811 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_7811</name>
+			<baseAddress>0xf8f00</baseAddress>
+		</peripheral>
+		<!-- DMA_MEMCP -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_MEMCP</name>
+			<baseAddress>0xf9000</baseAddress>
+		</peripheral>
+		<!-- DMA_IIC0 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_IIC0</name>
+			<baseAddress>0xf9100</baseAddress>
+		</peripheral>
+		<!-- DMA_IIC1 -->
+		<peripheral derivedFrom="MDMA">
+			<name>MDMA_IIC1</name>
+			<baseAddress>0xf9200</baseAddress>
+		</peripheral>
+		<!--SPI-->
+		<peripheral>
+			<name>MSPI</name>
+			<version>1.0</version>
+			<description>MSPI</description>
+			<groupName>MSPI</groupName>
+			<baseAddress>0xf891c</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x4</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>WAIT_DMA</name>
+							<description>0: ignore dma status\n1: 等待dma 完全写入ram ,再开始接收下1 by\nte</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIRST_BIT</name>
+							<description>1: 先发送lsb\n0:先发送MSB</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_PHASE</name>
+							<description>0: normal receive sample\n point\n1: receive sample point dela\ny one clock of ahb_bus</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SCK_DIR</name>
+							<description>ncs 与 sck 输入输出选择\n0: 输出(master mode)\n1: 输入(slave mode)</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AUTO_START</name>
+							<description>1: spi dma可以被dcmi多行中断自动启\n动</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RW_DELAY</name>
+							<description>反向间隔（value*16个clock）</description>
+							<bitRange>[14:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DCMI_EN</name>
+							<description>0: 8-bit spi mode\n1: 8-bit byte y extended to \n16-bit rgb565</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESET</name>
+							<description>spi_reset</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CPOL</name>
+							<description>CPOL （空闲状态时钟电平） 1: High \n 0: Low</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CPHA</name>
+							<description>CPHA  1: 偶数边沿采样  0: 奇数边沿\n采样</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MODE</name>
+							<description>0: Master Mode  1：Slave \nMode</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLK_DIV</name>
+							<description>SPICLK 分频系数 (1&lt;&lt;CTRL[2:0\n])</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- SPI0 -->
+		<peripheral derivedFrom="MSPI">
+			<name>MSPI0</name>
+			<baseAddress>0xf891c</baseAddress>
+			<alternatePeripheral>MSPI</alternatePeripheral>
+		</peripheral>
+		<!-- SPI1 -->
+		<peripheral derivedFrom="MSPI">
+			<name>MSPI1</name>
+			<baseAddress>0xf8a1c</baseAddress>
+		</peripheral>
+		<!--UART-->
+		<peripheral>
+			<name>MUART</name>
+			<version>1.0</version>
+			<description>MUART</description>
+			<groupName>MUART</groupName>
+			<baseAddress>0xf8b1c</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x10</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>8</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RESET_BAUD</name>
+							<description> UART重置波特率位\n0：无操作\n1：必须先配置好波特率，置位1后 波特率才能生效。\n</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>HDX_EN</name>
+							<description>UART全双工/双工模式控制位\n0：全双工\n1：半双工\n</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SMART_CARD</name>
+							<description>UART 智能卡模式控制位\n0：关闭智能卡\n1：开启智能卡模式</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FLOW_CTRL</name>
+							<description>UART 模块流控控制位\n0：无流控模式\n1：有流控模式\n</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>STOP_BITS</name>
+							<description>UART 停止位\n0：1bit停止位\n1：2bit停止位\n</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DATA_BITS</name>
+							<description>UART 校验使能位\n0：无校验位,仅发送8bit数据\n1：有校验位,发送9bit数据。\n</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PARITY</name>
+							<description>UART 校验位\n0：Parity_Even(偶校验)\n1：Parity_Odd(奇校验)\n</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_EN</name>
+							<description>UART 使能位\n0：失能Rx功能\n1：使能Rx功能\n</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RX_INT_LEN-->
+				<register>
+					<name>RX_INT_LEN</name>
+					<description>* RX_INT_LEN *</description>
+					<addressOffset>0x1</addressOffset>
+					<size>8</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>控制串口接收中断长度，为0不触发中断</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BAUD-->
+				<register>
+					<name>BAUD</name>
+					<description>* BAUD *</description>
+					<addressOffset>0x2</addressOffset>
+					<size>16</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TX_INT_EN</name>
+							<description>发送中断使能位 0：失能tx中断  1：使能tx\n中断</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>BAUD_RATE</name>
+							<description>配置波特率 (波特率=时钟/寄存器的值)</description>
+							<bitRange>[14:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TIMEOUT_INT-->
+				<register>
+					<name>TIMEOUT_INT</name>
+					<description>* TIMEOUT_INT *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>16</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>0：不启用。当收到数据后开始计时，超时未收到下一\n个字节则触发中断，接收超时中断时间值（48*value）\n。</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RX_DATA-->
+				<register>
+					<name>RX_DATA</name>
+					<description>* RX_DATA *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>8</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>读取UART的数据</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS-->
+				<register>
+					<name>STATUS</name>
+					<description>* STATUS *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RX_ITEMS_L</name>
+							<description>当前RX BUF中的数据个数低16位</description>
+							<bitRange>[31:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_ITEMS_H</name>
+							<description>当前RX BUF中的数据个数高4位</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_NEAR_FULL</name>
+							<description>0:rx buf 数据未接近满  1:rx bu\nf 数据接近满</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_FULL</name>
+							<description>0:rx buf 未满  1:rx buf 满</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_EMPTY</name>
+							<description>0:rx buf 非空  1:rx buf 为空</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- UART0 -->
+		<peripheral derivedFrom="MUART">
+			<name>MUART0</name>
+			<baseAddress>0xf8b1c</baseAddress>
+			<alternatePeripheral>MUART</alternatePeripheral>
+		</peripheral>
+		<!-- UART1 -->
+		<peripheral derivedFrom="MUART">
+			<name>MUART1</name>
+			<baseAddress>0xf8c1c</baseAddress>
+		</peripheral>
+		<!-- UART2 -->
+		<peripheral derivedFrom="MUART">
+			<name>MUART2</name>
+			<baseAddress>0xf8d1c</baseAddress>
+		</peripheral>
+		<!-- UART3 -->
+		<peripheral derivedFrom="MUART">
+			<name>MUART3</name>
+			<baseAddress>0xf8e1c</baseAddress>
+		</peripheral>
+		<!-- ISO7811 -->
+		<!--IIC-->
+		<peripheral>
+			<name>MIIC</name>
+			<version>1.0</version>
+			<description>MIIC</description>
+			<groupName>MIIC</groupName>
+			<baseAddress>0xf911c</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x8</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL1-->
+				<register>
+					<name>CTRL1</name>
+					<description>* CTRL1 *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SCLL</name>
+							<description>scll    scl低电平时间</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SCLH</name>
+							<description>sclh   scl高电平时间</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>STSU</name>
+							<description>stsu   起始位建立时间</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>STHD</name>
+							<description>sthd  起始位保持时间</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL2-->
+				<register>
+					<name>CTRL2</name>
+					<description>* CTRL2 *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SOSU</name>
+							<description>sosu  停止位建立时间</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DTSU</name>
+							<description>dtsu  数据位的建立时间</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DTHD</name>
+							<description>dthd  数据位的保持时间</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESTART</name>
+							<description>restart     注意！！！这一bit是控\n制I2C协议中restart时序的,而不是复位I2C寄存\n器；在写从设备的时候置0,在读从设备的时候要置1</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- IIC0 -->
+		<peripheral derivedFrom="MIIC">
+			<name>MI2C0</name>
+			<baseAddress>0xf911c</baseAddress>
+			<alternatePeripheral>MIIC</alternatePeripheral>
+		</peripheral>
+		<!-- IIC1 -->
+		<peripheral derivedFrom="MIIC">
+			<name>MI2C1</name>
+			<baseAddress>0xf921c</baseAddress>
+		</peripheral>
+		<!--LPM-->
+		<peripheral>
+			<name>MLPM</name>
+			<version>1.0</version>
+			<description>MLPM</description>
+			<groupName>MLPM</groupName>
+			<baseAddress>0xfa800</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x328</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- LDO_POR -->
+				<register>
+					<name>LDO_POR</name>
+					<description>analog register</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0xF004D040</resetValue>
+					<fields>
+						<!-- RG_LPM_LDO_LPM_VSEL -->
+						<field>
+							<name>RG_LPM_LDO_LPM_VSEL</name>
+							<description>digital aon ldo vout sel</description>
+							<bitRange>[4:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_LDO_LPM_0P33VDD_BYPB -->
+						<field>
+							<name>RG_LPM_LDO_LPM_0P33VDD_BYPB</name>
+							<description>LPM 0.33vdd ldo bypass to gnd enable control, low active</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_HVLDO_OCP_EN -->
+						<field>
+							<name>RG_LPM_HVLDO_OCP_EN</name>
+							<description>HVLDO over current protection enable</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_POR_DEGLITCH_OPT -->
+						<field>
+							<name>RG_LPM_POR_DEGLITCH_OPT</name>
+							<description>Vcoin POR deglitch optimization control, high active</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_VSEC_POR_DEGLITCH_OPT -->
+						<field>
+							<name>RG_LPM_VSEC_POR_DEGLITCH_OPT</name>
+							<description>Vlion POR deglitch optimization control, high active</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_LDO_SEC_VTRIM -->
+						<field>
+							<name>RG_LPM_LDO_SEC_VTRIM</name>
+							<description>Security main LDO output voltage control</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_OSC192M_VC -->
+						<field>
+							<name>RG_LPM_OSC192M_VC</name>
+							<description>RC OSC 192MHz frequency control</description>
+							<bitRange>[24:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_LDO_SEC_EN -->
+						<field>
+							<name>RG_LPM_LDO_SEC_EN</name>
+							<description>Security main LDO enable</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_LDO_OSC192M_EN -->
+						<field>
+							<name>RG_LPM_LDO_OSC192M_EN</name>
+							<description>RC OSC 192MHz LDO enable</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_OSC192M_RSTN -->
+						<field>
+							<name>RG_LPM_OSC192M_RSTN</name>
+							<description>RC OSC 192MHz resetn</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_OSC192M_EN -->
+						<field>
+							<name>RG_LPM_OSC192M_EN</name>
+							<description>RC OSC 192MHz enable</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- OSC_XTAL -->
+				<register>
+					<name>OSC_XTAL</name>
+					<description>analog register</description>
+					<addressOffset>0x04</addressOffset>
+					<size>32</size>
+					<resetValue>0x2F0</resetValue>
+					<fields>
+						<!-- OSC_XTAL_REF_MODE_EN -->
+						<field>
+							<name>OSC_XTAL_REF_MODE_EN</name>
+							<description>mode cfg</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_IB_OBUF -->
+						<field>
+							<name>OSC_XTAL_IB_OBUF</name>
+							<description>xtal output buffer bias current ctrl</description>
+							<bitRange>[2:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_IB_CTRL -->
+						<field>
+							<name>OSC_XTAL_IB_CTRL</name>
+							<description>xtal core bias current ctrl</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_CTRIM -->
+						<field>
+							<name>OSC_XTAL_CTRIM</name>
+							<description>xtal cap bank selection</description>
+							<bitRange>[12:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_EN_REG -->
+						<field>
+							<name>OSC_XTAL_EN_REG</name>
+							<description>xtal regulator enable, high active</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_EN -->
+						<field>
+							<name>OSC_XTAL_EN</name>
+							<description>xtal core enable, high active</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OSC_XTAL_DIV2_EN -->
+						<field>
+							<name>OSC_XTAL_DIV2_EN</name>
+							<description>xtal to clkpll ref freq div2 enable, high active</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- XO32K -->
+				<register>
+					<name>XO32K</name>
+					<description>XO32K control</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x58945</resetValue>
+					<fields>
+						<!-- RG_LPM_XO32K_RG_XTAL_CGM_ISEL -->
+						<field>
+							<name>RG_LPM_XO32K_RG_XTAL_CGM_ISEL</name>
+							<description>xo32k constant-gm current selection</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_RDC_SEL -->
+						<field>
+							<name>RG_LPM_XO32K_RDC_SEL</name>
+							<description>xo32k gm gate-drain dc res type selection</description>
+							<bitRange>[4:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_ITUNE -->
+						<field>
+							<name>RG_LPM_XO32K_ITUNE</name>
+							<description>xo32k gm current selection</description>
+							<bitRange>[9:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_GMP_BYPASS -->
+						<field>
+							<name>RG_LPM_XO32K_GMP_BYPASS</name>
+							<description>xo32k gm pmos bypass, high active. when xo32k mode</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_DISCONNECT -->
+						<field>
+							<name>RG_LPM_XO32K_DISCONNECT</name>
+							<description>disconnect xo32k analog circuit from gpio pad, high active</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_VREF_TUNE -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_VREF_TUNE</name>
+							<description>xo32k comp voltage selection when vrefn from vgen, control bits higher</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_VN_SEL -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_VN_SEL</name>
+							<description>xo32k hysteresis comp negative input signal selection</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_VGEN_EN -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_VGEN_EN</name>
+							<description>xo32k comp vrefn voltage gen circuit enable, high active</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_TH_SEL -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_TH_SEL</name>
+							<description>xo32k hysteresis comp threshold voltage selection, control bits higher, vth higher</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_ISEL -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_ISEL</name>
+							<description>xo32k hysteresis comp current selection</description>
+							<bitRange>[19:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_XO32K_COMP_IB_LARGE -->
+						<field>
+							<name>RG_LPM_XO32K_COMP_IB_LARGE</name>
+							<description>xo32k hysteresis comp and current-starved invter bais current enlarge control, high active</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_LPM_XO32K_EN -->
+						<field>
+							<name>DA_LPM_XO32K_EN</name>
+							<description>xo32k enable, high active</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- CHGR_CTRL -->
+				<register>
+					<name>CHGR_CTRL</name>
+					<description>CHGR control register</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- RG_LPM_CHGR_TERMC -->
+						<field>
+							<name>RG_LPM_CHGR_TERMC</name>
+							<description>Charging termination current control</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_TCC -->
+						<field>
+							<name>RG_LPM_CHGR_TCC</name>
+							<description>analog register</description>
+							<bitRange>[3:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_SHUTDOWN_SW -->
+						<field>
+							<name>RG_LPM_CHGR_SHUTDOWN_SW</name>
+							<description>Force off charger pass transistor</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_SHUTDOWN_CORE -->
+						<field>
+							<name>RG_LPM_CHGR_SHUTDOWN_CORE</name>
+							<description>Force off charger CC/CV loop</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_SHUTDOWN_BIAS -->
+						<field>
+							<name>RG_LPM_CHGR_SHUTDOWN_BIAS</name>
+							<description>Force off charger bias</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_RCHC -->
+						<field>
+							<name>RG_LPM_CHGR_RCHC</name>
+							<description>Battery voltage threshold adjustments for re-charging in 53mV/steps</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_INSC_ENB -->
+						<field>
+							<name>RG_LPM_CHGR_INSC_ENB</name>
+							<description>Charger input sink current enable. Used to wake up charger case and to be turned off upon the end of charging process</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_ICHG_SET -->
+						<field>
+							<name>RG_LPM_CHGR_ICHG_SET</name>
+							<description>Charging current control in CC phase</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_FORCE_CV -->
+						<field>
+							<name>RG_LPM_CHGR_FORCE_CV</name>
+							<description>Charger CV mode force enable</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_FORCE_CORE_ON -->
+						<field>
+							<name>RG_LPM_CHGR_FORCE_CORE_ON</name>
+							<description>Force on charger CC/CV loop when charger is in standby mode</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_FORCE_CC -->
+						<field>
+							<name>RG_LPM_CHGR_FORCE_CC</name>
+							<description>Charger CC mode force enable</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_CVC -->
+						<field>
+							<name>RG_LPM_CHGR_CVC</name>
+							<description>analog register</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_LPM_CHGR_RLIMIT_ENB -->
+						<field>
+							<name>RG_LPM_CHGR_RLIMIT_ENB</name>
+							<description>analog register</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--GPIO_WKEN_W0-->
+				<register>
+					<name>GPIO_WKEN_W0</name>
+					<description>* GPIO_WKEN_W0 *</description>
+					<addressOffset>0x200</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LOW</name>
+							<description>gpio[31:0] 深度睡眠唤醒使能</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--GPIO_WKEN_W1-->
+				<register>
+					<name>GPIO_WKEN_W1</name>
+					<description>* GPIO_WKEN_W1 *</description>
+					<addressOffset>0x204</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>MID</name>
+							<description>gpio[63:32] 深度睡眠唤醒使能</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--GPIO_WKEN_W2-->
+				<register>
+					<name>GPIO_WKEN_W2</name>
+					<description>* GPIO_WKEN_W2 *</description>
+					<addressOffset>0x208</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>HIGH</name>
+							<description>gpio[79:64] 深度睡眠唤醒使能</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--GPIO_WK_LEVEL-->
+				<register>
+					<name>GPIO_WK_LEVEL</name>
+					<description>* GPIO_WK_LEVEL *</description>
+					<addressOffset>0x210</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LEVEL</name>
+							<description>GPIO唤醒电平设置\n0: GPIO高电平唤醒深度睡眠\n1: GPIO低电平唤醒深度睡眠</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--GPIO_LATCH-->
+				<register>
+					<name>GPIO_LATCH</name>
+					<description>* GPIO_LATCH *</description>
+					<addressOffset>0x214</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LATCH</name>
+							<description>nan</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--DEEP_SLEEP-->
+				<register>
+					<name>DEEP_SLEEP</name>
+					<description>* DEEP_SLEEP *</description>
+					<addressOffset>0x220</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EN</name>
+							<description>写0x5a会进入深度睡眠</description>
+							<bitRange>[7:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--WAKEUP_CTRL-->
+				<register>
+					<name>WAKEUP_CTRL</name>
+					<description>* WAKEUP_CTRL *</description>
+					<addressOffset>0x224</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RTC_LSE</name>
+							<description>1: 使能LSE定时唤醒深度睡眠</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RTC_LSI</name>
+							<description>1:使能LSI定时唤醒深度睡眠</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEC_EN</name>
+							<description>1: 使能安全事件唤醒深度睡眠</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--WAIT_LDO_CTRL-->
+				<register>
+					<name>WAIT_LDO_CTRL</name>
+					<description>* WAIT_LDO_CTRL *</description>
+					<addressOffset>0x228</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CNT</name>
+							<description>core_ldo打开后,等待cnt个osc32k\n周期后,开始启动系统,首次上电默认值为32ms\ndeep_sleep时,可通过合理设置此延迟值,减少系统\n退出deep_sleep时间</description>
+							<bitRange>[9:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--WKUP_HVLDO_CTRL-->
+				<register>
+					<name>WKUP_HVLDO_CTRL</name>
+					<description>* WKUP_HVLDO_CTRL *</description>
+					<addressOffset>0x22c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PWK_OFF_DISABLE</name>
+							<description>power key off disable\n0xaa: 禁用power key 关闭系统功能\nothers: 使能power 关闭系统功能</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHGR_IN_TURN_ON</name>
+							<description>chgr_in事件打开系统使能\n0xaa: 关闭chgr_in事件打开系统功能\nothers: 打开chgr_in事件打开系统功能</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIRST</name>
+							<description>1: 深度睡眠唤醒时,先打开HVLDO,再进行上\n电过程</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--RTC_LSE_CTRL-->
+				<register>
+					<name>RTC_LSE_CTRL</name>
+					<description>* RTC_LSE_CTRL *</description>
+					<addressOffset>0x230</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SEL</name>
+							<description>RTC_LSE的时钟选择\n0: 用LSI作为RTC_LSE的时钟\n1:用LSEZ作为RTC_LSE的时钟</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>使能 RTC LSE的时钟</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CHGR_EVENT_EN-->
+				<register>
+					<name>CHGR_EVENT_EN</name>
+					<description>* CHGR_EVENT_EN *</description>
+					<addressOffset>0x240</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EVENT1</name>
+							<description>1: 使能CHGR_WKUP[11:10]充电标\n志位检测和唤醒,使能后需要延时1ms再配置CHGR_WK\nUP_HI_EN[11:10]/CHGR_WKUP_LO\n_EN[11:10]</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EVENT0</name>
+							<description>1: 使能CHGR_WKUP[9:0]充电标志位\n检测和唤醒,使能后需要延时1ms再配置CHGR_WKUP\n_HI_EN[9:0]/CHGR_WKUP_LO_EN[\n9:0]</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CHGR_WKUP_HI_EN-->
+				<register>
+					<name>CHGR_WKUP_HI_EN</name>
+					<description>* CHGR_WKUP_HI_EN *</description>
+					<addressOffset>0x244</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PWK</name>
+							<description>power_key</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_OV</name>
+							<description>ad_lpm_vbat_ov_flag</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DET_AON</name>
+							<description>ad_lpm_chgr_in_det_aon</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CC_OV_CV</name>
+							<description>ad_lpm_chgr_cc_ov_cv</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CC</name>
+							<description>ad_lpm_chgr_dppm_ov_cc</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CV</name>
+							<description>ad_lpm_chgr_dppm_ov_cv</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PGOOD</name>
+							<description>ad_lpm_chgr_pgood</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UVLO_OK_AON</name>
+							<description>ad_lpm_chgr_uvlo_ok_aon</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESET</name>
+							<description>ad_lpm_chgr_reset</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICHG</name>
+							<description>ad_lpm_chgr_state_ichg</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IND</name>
+							<description>ad_lpm_chgr_state_ind</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RCH_EN</name>
+							<description>ad_lpm_chgr_state_rch_en</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_LV</name>
+							<description>ad_lpm_chgr_state_vbat_l\nv</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CHGR_WKUP_LO_EN-->
+				<register>
+					<name>CHGR_WKUP_LO_EN</name>
+					<description>* CHGR_WKUP_LO_EN *</description>
+					<addressOffset>0x248</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PWK</name>
+							<description>power_key</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_OV</name>
+							<description>ad_lpm_vbat_ov_flag</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DET_AON</name>
+							<description>ad_lpm_chgr_in_det_aon</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CC_OV_CV</name>
+							<description>ad_lpm_chgr_cc_ov_cv</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CC</name>
+							<description>ad_lpm_chgr_dppm_ov_cc</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DPPM_OV_CV</name>
+							<description>ad_lpm_chgr_dppm_ov_cv</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PGOOD</name>
+							<description>ad_lpm_chgr_pgood</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UVLO_OK_AON</name>
+							<description>ad_lpm_chgr_uvlo_ok_aon</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RESET</name>
+							<description>ad_lpm_chgr_reset</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ICHG</name>
+							<description>ad_lpm_chgr_state_ichg</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IND</name>
+							<description>ad_lpm_chgr_state_ind</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RCH_EN</name>
+							<description>ad_lpm_chgr_state_rch_en</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBAT_LV</name>
+							<description>ad_lpm_chgr_state_vbat_l\nv</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--PWK_CTRL-->
+				<register>
+					<name>PWK_CTRL</name>
+					<description>* PWK_CTRL *</description>
+					<addressOffset>0x260</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LDO_EN</name>
+							<description>写1 打开HVLDO</description>
+							<bitRange>[17:17]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>LDO_OFF</name>
+							<description>写1 关闭HVLDO</description>
+							<bitRange>[16:16]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>OFF_TIME</name>
+							<description>power_key按下多长时间关闭系统配置\n00: 4s\n01: 5s\n10: 6s\n11: 7s</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ON_TIME</name>
+							<description>power key 按下多长时间唤醒系统配置\n00: 128ms\n01: 384ms\n10: 640ms\n11: 896ms</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LDO_EXEN_CTRL-->
+				<register>
+					<name>LDO_EXEN_CTRL</name>
+					<description>* LDO_EXEN_CTRL *</description>
+					<addressOffset>0x264</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>GPIO</name>
+							<description>0xaa: gpio 模式,pu/pd/ie/o\n/oen受寄存器控制\nothers: ldo_exen模式,pu/pd/ie始\n终为0,oen为0允许输出,o输出hvldo_en信号</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IN</name>
+							<description>ldo_exen input value</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>0: disable input\n1: enable input</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PU</name>
+							<description>1: enable pull-up</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PD</name>
+							<description>1: enable pull-down</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>OUT</name>
+							<description>nan</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>OEN</name>
+							<description>0: enable output\n1: disable output</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLK_CTRL-->
+				<register>
+					<name>CLK_CTRL</name>
+					<description>* CLK_CTRL *</description>
+					<addressOffset>0x280</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EN</name>
+							<description>1: 使能寄存器时钟</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ACCESS_CODE-->
+				<register>
+					<name>ACCESS_CODE</name>
+					<description>* ACCESS_CODE *</description>
+					<addressOffset>0x2a0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ACCESS_CODE</name>
+							<description>按照顺序写入&quot;0x55-&gt;0xaa-&gt;0x17&quot;\n 来设置或者清除 &quot;access_en&quot;</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ACCESS_EN-->
+				<register>
+					<name>ACCESS_EN</name>
+					<description>* ACCESS_EN *</description>
+					<addressOffset>0x2a4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ACCESS_EN</name>
+							<description>这1bit 只能在ACCESS_CODE设置后写\n入\n1: 打开LPM寄存器写入权限\n0: 关闭LPM寄存器写入权限\n注：每次退出深度睡眠后,access_code和acce\nss_en会自动清0,必须重新使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BAKEUP_REG0-->
+				<register>
+					<name>BAKEUP_REG0</name>
+					<description>* BAKEUP_REG0 *</description>
+					<addressOffset>0x300</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>REG</name>
+							<description>复位值是0x5555_5555</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BAKEUP_REG1-->
+				<register>
+					<name>BAKEUP_REG1</name>
+					<description>* BAKEUP_REG1 *</description>
+					<addressOffset>0x304</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>REG</name>
+							<description>复位值是0xaaaa_aaaa</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BAKEUP_REG2-->
+				<register>
+					<name>BAKEUP_REG2</name>
+					<description>* BAKEUP_REG2 *</description>
+					<addressOffset>0x320</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>REG</name>
+							<description>无复位功能寄存器</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BAKEUP_REG3-->
+				<register>
+					<name>BAKEUP_REG3</name>
+					<description>* BAKEUP_REG3 *</description>
+					<addressOffset>0x324</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>REG</name>
+							<description>无复位功能寄存器</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--BPK-->
+		<peripheral>
+			<name>MBPK</name>
+			<version>1.0</version>
+			<description>MBPK</description>
+			<groupName>MBPK</groupName>
+			<baseAddress>0xfac00</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x94</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- KEY-->
+				<register>
+					<dim>32</dim>
+					<dimIncrement>4</dimIncrement>
+					<name>KEY[%s]</name>
+					<description>key</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+				</register>
+				<!--RST-->
+				<register>
+					<name>RST</name>
+					<description>* RST *</description>
+					<addressOffset>0x80</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RESET</name>
+							<description>写1会复位KEY,BPK的配置,SENSOR的配\n置。</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--CLR-->
+				<register>
+					<name>CLR</name>
+					<description>* CLR *</description>
+					<addressOffset>0x84</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CLR</name>
+							<description>每一bit控制256-bit 的KEY清除 , \n写“1”将清除相应的区域</description>
+							<bitRange>[3:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--LR-->
+				<register>
+					<name>LR</name>
+					<description>* LR *</description>
+					<addressOffset>0x88</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LOCK_READ</name>
+							<description>每一bit控制256-bit 的KEY的锁定 ,\n 写“1”将锁定读取相应的区域</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LW-->
+				<register>
+					<name>LW</name>
+					<description>* LW *</description>
+					<addressOffset>0x8c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LOCK_WRITE</name>
+							<description>每一bit控制256-bit 的KEY的锁定 ,\n 写“1”将锁定写入相应的区域</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LOCK-->
+				<register>
+					<name>LOCK</name>
+					<description>* LOCK *</description>
+					<addressOffset>0x90</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RESET_LOCK</name>
+							<description>1:锁定RESET寄存器</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLR_LOCK</name>
+							<description>1:锁定CLR寄存器</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LKR_LOCK</name>
+							<description>1:锁定LOCK_READ寄存器</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LKW_LOCK</name>
+							<description>1:锁定LOCK_WRITE寄存器</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOCK_SELF</name>
+							<description>1:锁定LOCK寄存器本身(通常用于配置好其他的\n锁定过后,且无法解锁)</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--SEC-->
+		<peripheral>
+			<name>MSEC</name>
+			<version>1.0</version>
+			<description>MSEC</description>
+			<groupName>MSEC</groupName>
+			<baseAddress>0xfae00</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0xc8</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--LC-->
+				<register>
+					<name>LC</name>
+					<description>* LC *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>仅支持比特置1操作,不支持清0回退\n0x01: 上电非安全状态\n其他值：用户自定义</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--LOCK-->
+				<register>
+					<name>LOCK</name>
+					<description>* LOCK *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SHIELD</name>
+							<description>1:锁定SHIELD_EN/SHIELD_CTR\nL寄存器</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SENSOR</name>
+							<description>1:锁定SENSOR_EN/SENSOR_CTR\nL/SENSOR_THRES寄存器</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TAMPER</name>
+							<description>1:锁定TAMP_EN/TAMP_CTRL/TA\nMP_STA_CTRL/TAMP_DYN_CTRL寄存器</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ACTION</name>
+							<description>1:锁定 ALERT_ACTION寄存器</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOCK_SELF</name>
+							<description>1:锁定LOCK寄存器本身(通常用于配置好其他的\n锁定过后,且无法解锁)</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ALERT_FILT-->
+				<register>
+					<name>ALERT_FILT</name>
+					<description>* ALERT_FILT *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CNT_CLR</name>
+							<description>写1 清除CNT寄存器的是值</description>
+							<bitRange>[16:16]</bitRange>
+							<access>write-only</access>
+						</field>
+						<field>
+							<name>THOLD</name>
+							<description>当THOLD的配置大于等于CNT的值的时候会触发\n ALERT_ACTION</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CNT</name>
+							<description>当TAMPER/SENSOR/SHIELD的报警\n发生时cnt寄存器会加1</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--ALERT_ACTION-->
+				<register>
+					<name>ALERT_ACTION</name>
+					<description>* ALERT_ACTION *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RESET_SYSTEM</name>
+							<description>当ALERT_ACTION发生时,除了该寄存器配\n置成0x5能失能复位系统动作,其他配置都会导致复位系统</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CLEAR_KEY</name>
+							<description>当ALERT_ACTION发生时,除了该寄存器配\n置成0x5能失能清除秘钥动作,其他配置都会导致清除秘钥</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SOFT_ATTACK_EN-->
+				<register>
+					<name>SOFT_ATTACK_EN</name>
+					<description>* SOFT_ATTACK_EN *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EN</name>
+							<description>置‘1’后无法清0\n1: 使能soft_attack功能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SOFT_ATTACK_LOCK-->
+				<register>
+					<name>SOFT_ATTACK_LOCK</name>
+					<description>* SOFT_ATTACK_LOCK *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LOCK</name>
+							<description>软件攻击锁定\n0: 解锁 soft attack\n1: 锁定 soft attack\n注：写此寄存器可置1和清0,写其他任意寄存器,此寄存器会\n置1</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SOFT_ATTACK-->
+				<register>
+					<name>SOFT_ATTACK</name>
+					<description>* SOFT_ATTACK *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TYPE</name>
+							<description>soft_attack位检测到1时,锁存写数据的\n比特7到4</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TRIGGER</name>
+							<description>写1触发软件攻击\n注：必须先写soft_attack_lock为0,再写此\n寄存器,中间不能插入其他寄存器读写操作</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--IE-->
+				<register>
+					<name>IE</name>
+					<description>* IE *</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>KEY_CLEAR</name>
+							<description>1:使能清除秘钥触发中断</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOFT_ATTACK</name>
+							<description>1:使能soft attact触发中断</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHIELD</name>
+							<description>1:使能SHIELD触发中断</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SENSOR</name>
+							<description>1:使能SENSOR触发中断</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TAMPER</name>
+							<description>1:使能TAMPER触发中断</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IRQ-->
+				<register>
+					<name>IRQ</name>
+					<description>* IRQ *</description>
+					<addressOffset>0x34</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>KEY_CLEAR</name>
+							<description>写‘1’清除KEY_CLEAR中断状态</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOFT_ATTACK</name>
+							<description>写‘1’清除SOFT_ATTACK中断状态</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SHIELD</name>
+							<description>写‘1’清除SHIELD中断状态</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SENSOR</name>
+							<description>写‘1’清除SENSOR中断状态</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TAMPER</name>
+							<description>写‘1’清除TAMPER中断状态</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS-->
+				<register>
+					<name>STATUS</name>
+					<description>* STATUS *</description>
+					<addressOffset>0x38</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>KEY_CLEAR</name>
+							<description>清除秘钥中断状态</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>SOFT_ATTACK</name>
+							<description>软件攻击中断状态</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>SHIELD_ALARM</name>
+							<description>SHIELD中断状态</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>SENSOR_ALARM</name>
+							<description>SENSOR中断状态</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TAMP_ALARM</name>
+							<description>TAMPER中断状态,每1BIT代表一个TAMP\nER触发中断</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--TAMP_EN-->
+				<register>
+					<name>TAMP_EN</name>
+					<description>* TAMP_EN *</description>
+					<addressOffset>0x40</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name> TAMP_7</name>
+							<description>TAMPER7 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_6</name>
+							<description>TAMPER6 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_5</name>
+							<description>TAMPER5 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_4</name>
+							<description>TAMPER4 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_3</name>
+							<description>TAMPER3 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_2</name>
+							<description>TAMPER2 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_1</name>
+							<description>TAMPER1 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> TAMP_0</name>
+							<description>TAMPER0 使能\n0x5:使能\nOthers:使能</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TAMP_CTRL-->
+				<register>
+					<name>TAMP_CTRL</name>
+					<description>* TAMP_CTRL *</description>
+					<addressOffset>0x44</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PU_EN</name>
+							<description>TAMPER IO上拉使能(每1BIT对应控制一\n个 TAMPER IO)\n动态模式:需要把输入脚上拉或下拉\n静态模式:把对应IO上拉,PULL_AUTO为1时,自动\n在静态检测期间使能上拉,其他时间禁止上拉,以减少功耗\n注：Tamper IO 上电默认开启上拉,每个IO上拉或\n下拉只能选择一个</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PD_EN</name>
+							<description>TAMPER IO下拉使能(每1BIT对应控制一\n个 TAMPER IO)\n动态模式:需要把输入脚上拉或下拉\n静态模式:把对应IO下拉,PULL_AUTO为1时,自动\n在静态检测期间使能下拉,其他时间禁止下拉,以减少功耗</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>TAMPER IO使能\n动态模式,输入管脚需要使能IE,输出管脚不需要\n静态模式,所有管脚均需要使能IE,PULL_AUTO为1\n时,自动在静态检测期间使能IE,其他时间禁止IE,以减少\n功耗</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>MODE</name>
+							<description>TAMPER IO模式(每1BIT控制两个IO,\n按顺序对应IO0~7)\n0:静态模式\n1:动态模式</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TAMP_STA_CTRL-->
+				<register>
+					<name>TAMP_STA_CTRL</name>
+					<description>* TAMP_STA_CTRL *</description>
+					<addressOffset>0x48</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ALERT_LEVEL</name>
+							<description>分别对应8个引脚的静态报警电平\n0: 低电平报警\n1: 高电平报警</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHK_DLY</name>
+							<description>静态上下拉开启后,延迟多长时间后进行检测\n0: 1ms\n1: 4ms\n2: 8ms\n3: 16ms</description>
+							<bitRange>[23:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHK_GAP</name>
+							<description>静态检测间隔\n0: 1ms\n1: 2ms\n2: 4ms\n3: 8ms</description>
+							<bitRange>[21:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name> PULL_AUTO</name>
+							<description>0: 静态上下拉由软件控制\n1: 静态上下拉只在配置工作期间有效,由硬件自动控制</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PROT_MODE</name>
+							<description>静态报警触发后,保护模式选择\n0: 引脚处于高阻状态\n1: 引脚自动上下拉（取决于外部电平）</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PROT_EN</name>
+							<description>静态报警触发后,IO是否启动自动保护\n0: 不开启 ,继续进行检测\n1: 开启 ,停止检测,进入保护模式,保护模式由PROT\n_MODE确定</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FILT_WIN</name>
+							<description>静态检测窗口报警过滤选择\n0: 一个窗口检测到报警即为报警\n1: 连续两个窗口检测到报警即为报警\n2: 连续三个窗口检测到报警即为报警\n3: 连续四个窗口检测到报警即为报警</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHK_WIN</name>
+							<description>窗口内采样过滤选择\n0: 窗口内进行一次采样,一次采样成功即触发窗口报警\n1: 窗口内进行两次采样,连续两次采样成功即触发窗口报警\n2: 窗口内进行三次采样,连续三次采样成功即触发窗口报警\n3: 窗口内进行四次采样,连续四次采样成功即触发窗口报警</description>
+							<bitRange>[3:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PERIOD</name>
+							<description>静态检测周期\n0: 32ms\n1: 125ms\n2: 500ms\n3: 0.9999s</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TAMP_DYN_CTRL-->
+				<register>
+					<name>TAMP_DYN_CTRL</name>
+					<description>* TAMP_DYN_CTRL *</description>
+					<addressOffset>0x4c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PROT_MODE</name>
+							<description>动态报警触发后,保护模式选择\n0: 引脚处于高阻状态\n1: 引脚自动上下拉（取决于外部电平）</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PROT_EN</name>
+							<description>动态报警触发后,IO是否启动自动保护\n0: 不开启 \n1: 开启 ,保护模式由PROT_MODE确定</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>CHK_WIN</name>
+							<description>窗口内采样过滤选择\n0: 窗口内进行一次采样,一次采样成功即触发窗口报警\n1: 窗口内进行两次采样,连续两次采样成功即触发窗口报警\n2: 窗口内进行三次采样,连续三次采样成功即触发窗口报警\n3: 窗口内进行四次采样,连续四次采样成功即触发窗口报警</description>
+							<bitRange>[3:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PERIOD</name>
+							<description>动态检测周期\n0: 32ms\n1: 125ms\n2: 500ms\n3: 0.9999s</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TAMP_IO_STATUS-->
+				<register>
+					<name>TAMP_IO_STATUS</name>
+					<description>* TAMP_IO_STATUS *</description>
+					<addressOffset>0x50</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PU</name>
+							<description>IO上拉状态</description>
+							<bitRange>[31:24]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>PD</name>
+							<description>IO下拉状态</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>OEN</name>
+							<description>IO使能状态</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>IE</name>
+							<description>IO IE状态</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--SENSOR_EN-->
+				<register>
+					<name>SENSOR_EN</name>
+					<description>* SENSOR_EN *</description>
+					<addressOffset>0x80</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>
+TEMP_EN</name>
+							<description>温度传感器使能:\n0x5:失能\nOthers:使能</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_3_3_EN</name>
+							<description>纽扣电池3.3V输入电压传感器使能:\n0x5:失能\nOthers:使能</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_1_2_EN</name>
+							<description>纽扣电池1.2V输出电压传感器使能:\n0x5:失能\nOthers:使能</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SENSOR_CTRL-->
+				<register>
+					<name>SENSOR_CTRL</name>
+					<description>* SENSOR_CTRL *</description>
+					<addressOffset>0x84</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CHK_EN</name>
+							<description>传感器检测使能\n[4]: 低温检测使能\n[3]: 高温检测使能\n[2]: 纽扣电池3.3v输出低压检测使能\n[1]: 纽扣电池3.3v输出高压检测使能\n[0]: 纽扣电池1.2v输出低压检测使能</description>
+							<bitRange>[28:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DELAY</name>
+							<description>警报持续时间门限,大于门限的信号,将触发报警。用\n于滤除毛刺,防止虚警。\n00: 1*(1/32k)=31.25us\n01: 8*(1/32k)=250us\n10: 32*(1/32k)=1ms\n11: 128*(1/32k)=4ms\n注：这个时间必须小于sensor_duration时间</description>
+							<bitRange>[19:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DUR</name>
+							<description>Sensor检测时间长度。\n00: always on\n01: 2ms\n10: 8ms\n11: 16ms</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SENSOR_THRES-->
+				<register>
+					<name>SENSOR_THRES</name>
+					<description>* SENSOR_THRES *</description>
+					<addressOffset>0x88</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TS_OTC</name>
+							<description>高温报警温度设置\n0:  85\n1:  90\n2:  95\n3:  100\n4:  105</description>
+							<bitRange>[22:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TS_UTC</name>
+							<description>低温报警温度设置\n0: -40\n1: -35\n2: -30\n3: -25\n4: -20</description>
+							<bitRange>[18:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_H</name>
+							<description>纽扣电池3.3V输入电压高报警设置\n0000: 3.471\n0001: 3.577\n0010: 3.690\n0011: 3.810\n0100: 3.938\n0101: 4.076\n0110: 4.223\n0111: 4.381\n1000: 4.552\n1001: 4.736\n1010: 4.936\n1011: 5.154\n1100: 5.392\n1101: 5.653\n1110: 5.926\n1111: 6.115</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>VBUT_L</name>
+							<description>纽扣电池3.3V输入电压低报警设置\n0000: 1.938\n0001: 1.971\n0010: 2.005\n0011: 2.040\n0100: 2.076\n0101: 2.113\n0110: 2.152\n0111: 2.193\n1000: 2.235\n1001: 2.278\n1010: 2.324\n1011: 2.371\n1100: 2.420\n1101: 2.471\n1110: 2.525\n1111: 2.580</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DVDDLPM_L</name>
+							<description>纽扣电池1.2V输出电压低报警设置\n报警值等于 0.83+DVDDLPM_L*0.02</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SHIELD_EN-->
+				<register>
+					<name>SHIELD_EN</name>
+					<description>* SHIELD_EN *</description>
+					<addressOffset>0xc0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EN_7</name>
+							<description>SHIELD 7使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_6</name>
+							<description>SHIELD 6使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_5</name>
+							<description>SHIELD 5使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_4</name>
+							<description>SHIELD 4使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_3</name>
+							<description>SHIELD 3使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_2</name>
+							<description>SHIELD 2使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_1</name>
+							<description>SHIELD 1使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN_0</name>
+							<description>SHIELD 0使能\n0x5 :失能\nOthers: 使能</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SHIELD_CTRL-->
+				<register>
+					<name>SHIELD_CTRL</name>
+					<description>* SHIELD_CTRL *</description>
+					<addressOffset>0xc4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>CHK_WIN</name>
+							<description>窗口内采样过滤选择\n0: 窗口内进行一次采样,一次采样成功即触发窗口报警\n1: 窗口内进行两次采样,连续两次采样成功即触发窗口报警\n2: 窗口内进行三次采样,连续三次采样成功即触发窗口报警\n3: 窗口内进行四次采样,连续四次采样成功即触发窗口报警</description>
+							<bitRange>[9:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PERIOD</name>
+							<description>Shield工作周期\n0: 32ms\n1: 125ms\n2: 500ms\n3: 0.9999s</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--RTC-->
+		<peripheral>
+			<name>MRTC</name>
+			<version>1.0</version>
+			<description>MRTC</description>
+			<groupName>MRTC</groupName>
+			<baseAddress>0xfaf00</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x18</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--EN-->
+				<register>
+					<name>EN</name>
+					<description>* EN *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>1: 使能RTC  0:失能RTC</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SEC_CNT-->
+				<register>
+					<name>SEC_CNT</name>
+					<description>* SEC_CNT *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>设置一秒校准值</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IE-->
+				<register>
+					<name>IE</name>
+					<description>* IE *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ALARM</name>
+							<description>1: 允许闹钟中断 0:禁止闹钟中断</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEC</name>
+							<description>1: 允许秒中断 0:禁止秒中断</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--IRQ_STATUS-->
+				<register>
+					<name>IRQ_STATUS</name>
+					<description>* IRQ_STATUS *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ALARM</name>
+							<description>1: 闹钟中断,clk_alm_ie为0时也会置\n位,但不会触发中断</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SEC</name>
+							<description>1: 秒中断,scnd_ie为0时也会置位,但不\n会触发中断</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--ALARM-->
+				<register>
+					<name>ALARM</name>
+					<description>* ALARM *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>IRQPREVAL</name>
+							<description>闹钟中断预设值</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TIME-->
+				<register>
+					<name>TIME</name>
+					<description>* TIME *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>读操作读取当前RTC计数器值\n写操作改写当前RTC计数器值,仅支持32-bit操作</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- RTC_LSI -->
+		<peripheral derivedFrom="MRTC">
+			<name>MRTCLSI</name>
+			<baseAddress>0xfaf00</baseAddress>
+			<alternatePeripheral>MRTC</alternatePeripheral>
+		</peripheral>
+		<!-- RTC_LSE -->
+		<peripheral derivedFrom="MRTC">
+			<name>MRTCLSE</name>
+			<baseAddress>0xfb000</baseAddress>
+		</peripheral>
+		<!--ADC-->
+		<peripheral>
+			<name>MADC</name>
+			<version>1.0</version>
+			<description>MADC</description>
+			<groupName>MADC</groupName>
+			<baseAddress>0xfbb00</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x50</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--CTRL1-->
+				<register>
+					<name>CTRL1</name>
+					<description>* CTRL1 *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>SAMP_EDGE</name>
+							<description>ADC采样边沿选择\n0:下降沿采样\n1: 上升沿采样</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>AWD_EN</name>
+							<description>ADC看门狗使能,ADC采样值超过看门狗门限时会\n触发ADC看门狗中断\n0::失能\n1::使能</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>adc模块数字开关\n0: 失能ADC模块\n1: 使能ADC模块</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL2-->
+				<register>
+					<name>CTRL2</name>
+					<description>* CTRL2 *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TRIG_EN</name>
+							<description>定时器溢出触发ADC采样(仅适用于单次采样模式)\n0:失能\n1:使能</description>
+							<bitRange>[24:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SAMP_MODE</name>
+							<description>采样模式\n0:单次采样模式\n1:连续采样模式</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SGL_START</name>
+							<description>软件写'1',启动一次ADC采(仅在SAMP_M\nODE为0时生效)</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--IE-->
+				<register>
+					<name>IE</name>
+					<description>* IE *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>AWD</name>
+							<description>ADC看门狗中断使能\n0:失能\n1.使能</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIFO_FULL</name>
+							<description>FIFO数据溢出中断使能\n0:失能\n1.使能</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIFO_OVER</name>
+							<description>FIFO数据超过FIFO_LIMIT中断使能\n0:失能\n1.使能</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DONE</name>
+							<description>采样结束中断使能\n0:失能\n1.使能</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS-->
+				<register>
+					<name>STATUS</name>
+					<description>* STATUS *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>AWD</name>
+							<description>ADC看门狗中断状态,写1清除中断</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIFO_FULL</name>
+							<description>FIFO数据溢出中断状态,写1清除中断</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>FIFO_OVER</name>
+							<description>FIFO数据超过FIFO_LIMIT中断状态,写\n1清除中断</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>DONE</name>
+							<description>采样结束中断状态,写1清除中断</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--FIFO_CTRL-->
+				<register>
+					<name>FIFO_CTRL</name>
+					<description>* FIFO_CTRL *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>EN</name>
+							<description>ADC FIFO使能\n1:ADC数据有效转换值会写入FIFO\n0:ADC数据有效转换值不会写入FIFO</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RST</name>
+							<description>ADC FIFO复位</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ITEMS</name>
+							<description>FIFO中的有效数据量</description>
+							<bitRange>[12:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>LIMIT</name>
+							<description>当LIMIT&gt;0,且ITEMS&gt;=LIMIT时触\n发FIFO_OVER中断</description>
+							<bitRange>[4:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--FIFO-->
+				<register>
+					<name>FIFO</name>
+					<description>* FIFO *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>DATA</name>
+							<description>使用FIFO时的ADC取数寄存器(未使能电压转换\n功能时,读到的为原始AD值;使能电压转换功能时,读到的为\n电压值的二进制补码,单位为mv)</description>
+							<bitRange>[12:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--DATA-->
+				<register>
+					<name>DATA</name>
+					<description>* DATA *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>不使用FIFO时的ADC取数寄存器(未使能电压转\n换功能时,读到的为原始AD值;使能电压转换功能时,读到的\n为电压值的二进制补码,单位为mv)</description>
+							<bitRange>[12:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--AWD-->
+				<register>
+					<name>AWD</name>
+					<description>* AWD *</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>HIGH_LIMIT</name>
+							<description>ADC看门狗的高阈值(使能电压转换时,需同时启用\n负电压归零功能才能使用ADC看门狗功能)</description>
+							<bitRange>[28:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>LOW_LIMIT</name>
+							<description>ADC看门狗的低阈值(使能电压转换时,需同时启用\n负电压归零功能才能使用ADC看门狗功能)</description>
+							<bitRange>[12:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REF_AD-->
+				<register>
+					<name>REF_AD</name>
+					<description>* REF_AD *</description>
+					<addressOffset>0x40</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>基准电压AD值</description>
+							<bitRange>[9:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--REF_VOL-->
+				<register>
+					<name>REF_VOL</name>
+					<description>* REF_VOL *</description>
+					<addressOffset>0x44</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>基准电压(mV)</description>
+							<bitRange>[12:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--SLOPE-->
+				<register>
+					<name>SLOPE</name>
+					<description>* SLOPE *</description>
+					<addressOffset>0x48</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>VAL</name>
+							<description>电压转换斜率((vol_high-vol_low\n)/(vol_high_ref-vol_low_ref)\n)*64计算得到的10-bit整数值</description>
+							<bitRange>[9:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CONVERT_CTRL-->
+				<register>
+					<name>CONVERT_CTRL</name>
+					<description>* CONVERT_CTRL *</description>
+					<addressOffset>0x4c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>NEG_ZERO</name>
+							<description>负电压归零控制(写1时,负电压以0V输出)</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>EN</name>
+							<description>电压转换功能开关\n1: 使能电压转换\n0: 失能电压转换(输出原始ADC采样值)</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!--ISO7811-->
+		<peripheral>
+			<name>MISO7811</name>
+			<version>1.0</version>
+			<description>MISO7811</description>
+			<groupName>MISO7811</groupName>
+			<baseAddress>0xf8f00</baseAddress>
+			<alternatePeripheral>MDMA_7811</alternatePeripheral>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x60</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!--BASE_ADDR_T1-->
+				<register>
+					<name>BASE_ADDR_T1</name>
+					<description>* BASE_ADDR_T1 *</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_BASE_ADDR</name>
+							<description>Character write base add\nress for track 1</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BASE_ADDR_T2-->
+				<register>
+					<name>BASE_ADDR_T2</name>
+					<description>* BASE_ADDR_T2 *</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_BASE_ADDR</name>
+							<description>Character write base add\nress for track 2</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--BASE_ADDR_T3-->
+				<register>
+					<name>BASE_ADDR_T3</name>
+					<description>* BASE_ADDR_T3 *</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_BASE_ADDR</name>
+							<description>Character write base add\nress for track 3</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--CTRL-->
+				<register>
+					<name>CTRL</name>
+					<description>* CTRL *</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>T3_BUFFULL_CLR_IRQ</name>
+							<description>Clear 7811 track 3 buffe\nr full interrupt</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_BUFFULL_IRQ_EN</name>
+							<description>7811 track 3 buffer full\n interrupt enable</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_BUFFULL_CLR_IRQ</name>
+							<description>Clear 7811 track 2 buffe\nr full interrupt</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_BUFFULL_IRQ_EN</name>
+							<description>7811 track 2 buffer full\n interrupt enable</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_BUFFULL_CLR_IRQ</name>
+							<description>Clear 7811 track 1 buffe\nr full interrupt</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_BUFFULL_IRQ_EN</name>
+							<description>7811 track 1 buffer full\n interrupt enable</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_CHANNEL_SEL</name>
+							<description>Channel select signal fo\nr track 3</description>
+							<bitRange>[25:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_CHANNEL_SEL</name>
+							<description>Channel select signal fo\nr track 2</description>
+							<bitRange>[23:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_CHANNEL_SEL</name>
+							<description>Channel select signal fo\nr track 1</description>
+							<bitRange>[21:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_DC_CALC_WIN</name>
+							<description>DC calculation window co\nnfiguration for track 3</description>
+							<bitRange>[19:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_DC_CANCEL_EN</name>
+							<description>Enable DC cancellation f\nor track 3</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_DC_CALC_WIN</name>
+							<description>DC calculation window co\nnfiguration for track 2</description>
+							<bitRange>[16:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_DC_CANCEL_EN</name>
+							<description>Enable DC cancellation f\nor track 2</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_DC_CALC_WIN</name>
+							<description>DC calculation window co\nnfiguration for track 1</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_DC_CANCEL_EN</name>
+							<description>Enable DC cancellation f\nor track 1</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TIMER_CLR_IRQ</name>
+							<description>Clear 7811 timer interru\npt</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TIMER_IRQ_EN</name>
+							<description>7811 timer interrupt ena\nble</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>TIMER_EN</name>
+							<description>Timer enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SOFT_RESET</name>
+							<description>soft reset for AHB bus c\nontrol</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_CLR_IRQ</name>
+							<description>Clear 7811 track 3 inter\nrupt</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T3_IRQ_EN</name>
+							<description>7811  track 3 interrupt \nenable</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_CLR_IRQ</name>
+							<description>Clear 7811 track 2 inter\nrupt</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T2_IRQ_EN</name>
+							<description>7811  track 2 interrupt \nenable</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_CLR_IRQ</name>
+							<description>Clear 7811 track 1 inter\nrupt</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>T1_IRQ_EN</name>
+							<description>7811  track 1 interrupt \nenable</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RX_EN</name>
+							<description>7811 decoder enable</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T1_PEAK_VALUE_CFG-->
+				<register>
+					<name>T1_PEAK_VALUE_CFG</name>
+					<description>* T1_PEAK_VALUE_CFG *</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>THLD_RATIO</name>
+							<description>Peak value threshold rat\nio</description>
+							<bitRange>[16:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ALPHA</name>
+							<description>Coefficient for peak val\nue update IIR filter</description>
+							<bitRange>[12:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[8:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T1_PEAK_WIDTH_CFG-->
+				<register>
+					<name>T1_PEAK_WIDTH_CFG</name>
+					<description>* T1_PEAK_WIDTH_CFG *</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>UPDATA_RATIO4</name>
+							<description>Pulse width update ratio\n4</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UPDATA_RATIO3</name>
+							<description>Pulse width update ratio\n3</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UPDATA_RATIO2</name>
+							<description>Pulse width update ratio\n2</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>UPDATA_RATIO1</name>
+							<description>Pulse width update ratio\n1</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[14:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T1_PULSE_WIDTH_CFG-->
+				<register>
+					<name>T1_PULSE_WIDTH_CFG</name>
+					<description>* T1_PULSE_WIDTH_CFG *</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PEAK_SEL_RATIO2</name>
+							<description>Pulse width thld ratio2 \nfor peak select</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PEAK_SEL_RATIO1</name>
+							<description>Pulse width thld ratio1 \nfor peak select</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_BETA</name>
+							<description>Coefficient for pulse wi\ndth threshold IIR filter</description>
+							<bitRange>[21:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_MAX</name>
+							<description>Maximum pulse width valu\ne</description>
+							<bitRange>[17:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SYNC_ZERO_WIN</name>
+							<description>Synchronized zero judgem\nent window</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T1_DECODE_CFG-->
+				<register>
+					<name>T1_DECODE_CFG</name>
+					<description>* T1_DECODE_CFG *</description>
+					<addressOffset>0x1c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RATIO8</name>
+							<description>Pulse width threshold8 f\nor decode</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO7</name>
+							<description>Pulse width threshold7 f\nor decode</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO6</name>
+							<description>Pulse width threshold6 f\nor decode</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO5</name>
+							<description>Pulse width threshold5 f\nor decode</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO4</name>
+							<description>Pulse width threshold4 f\nor decode</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO3</name>
+							<description>Pulse width threshold3 f\nor decode</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO2</name>
+							<description>Pulse width threshold2 f\nor decode</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO1</name>
+							<description>Pulse width threshold1 f\nor decode</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T2_PEAK_VALUE_CFG-->
+				<register>
+					<name>T2_PEAK_VALUE_CFG</name>
+					<description>* T2_PEAK_VALUE_CFG *</description>
+					<addressOffset>0x20</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>THLD_RATIO</name>
+							<description>Peak value threshold rat\nio</description>
+							<bitRange>[16:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ALPHA</name>
+							<description>Coefficient for peak val\nue update IIR filter</description>
+							<bitRange>[12:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[8:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T2_PEAK_WIDTH_CFG-->
+				<register>
+					<name>T2_PEAK_WIDTH_CFG</name>
+					<description>* T2_PEAK_WIDTH_CFG *</description>
+					<addressOffset>0x24</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PULSE_WID_RATIO4</name>
+							<description>Pulse width update ratio\n4</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO3</name>
+							<description>Pulse width update ratio\n3</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO2</name>
+							<description>Pulse width update ratio\n2</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO1</name>
+							<description>Pulse width update ratio\n1</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[14:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T2_PULSE_WIDTH_CFG-->
+				<register>
+					<name>T2_PULSE_WIDTH_CFG</name>
+					<description>* T2_PULSE_WIDTH_CFG *</description>
+					<addressOffset>0x28</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PEAK_SEL_RATIO2</name>
+							<description>Pulse width thld ratio2 \nfor peak select</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PEAK_SEL_RATIO1</name>
+							<description>Pulse width thld ratio1 \nfor peak select</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_BETA</name>
+							<description>Coefficient for pulse wi\ndth threshold IIR filter</description>
+							<bitRange>[21:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_MAX</name>
+							<description>Maximum pulse width valu\ne</description>
+							<bitRange>[17:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SYNC_ZERO_WIN</name>
+							<description>Synchronized zero judgem\nent window</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T2_DECODE_CFG-->
+				<register>
+					<name>T2_DECODE_CFG</name>
+					<description>* T2_DECODE_CFG *</description>
+					<addressOffset>0x2c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RATIO8</name>
+							<description>Pulse width threshold8 f\nor decode</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO7</name>
+							<description>Pulse width threshold7 f\nor decode</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO6</name>
+							<description>Pulse width threshold6 f\nor decode</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO5</name>
+							<description>Pulse width threshold5 f\nor decode</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO4</name>
+							<description>Pulse width threshold4 f\nor decode</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO3</name>
+							<description>Pulse width threshold3 f\nor decode</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO2</name>
+							<description>Pulse width threshold2 f\nor decode</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO1</name>
+							<description>Pulse width threshold1 f\nor decode</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T3_PEAK_VALUE_CFG-->
+				<register>
+					<name>T3_PEAK_VALUE_CFG</name>
+					<description>* T3_PEAK_VALUE_CFG *</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>THLD_RATIO</name>
+							<description>Peak value threshold rat\nio</description>
+							<bitRange>[16:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>ALPHA</name>
+							<description>Coefficient for peak val\nue update IIR filter</description>
+							<bitRange>[12:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[8:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T3_PEAK_WIDTH_CFG-->
+				<register>
+					<name>T3_PEAK_WIDTH_CFG</name>
+					<description>* T3_PEAK_WIDTH_CFG *</description>
+					<addressOffset>0x34</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PULSE_WID_RATIO4</name>
+							<description>Pulse width update ratio\n4</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO3</name>
+							<description>Pulse width update ratio\n3</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO2</name>
+							<description>Pulse width update ratio\n2</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_RATIO1</name>
+							<description>Pulse width update ratio\n1</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>THLD_INIT</name>
+							<description>Initial peak value thres\nhold</description>
+							<bitRange>[14:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T3_PULSE_WIDTH_CFG-->
+				<register>
+					<name>T3_PULSE_WIDTH_CFG</name>
+					<description>* T3_PULSE_WIDTH_CFG *</description>
+					<addressOffset>0x38</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>PEAK_SEL_RATIO2</name>
+							<description>Pulse width thld ratio2 \nfor peak select</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PEAK_SEL_RATIO1</name>
+							<description>Pulse width thld ratio1 \nfor peak select</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_BETA</name>
+							<description>Coefficient for pulse wi\ndth threshold IIR filter</description>
+							<bitRange>[21:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>PULSE_WID_MAX</name>
+							<description>Maximum pulse width valu\ne</description>
+							<bitRange>[17:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>SYNC_ZERO_WIN</name>
+							<description>Synchronized zero judgem\nent window</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--T3_DECODE_CFG-->
+				<register>
+					<name>T3_DECODE_CFG</name>
+					<description>* T3_DECODE_CFG *</description>
+					<addressOffset>0x3c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>RATIO8</name>
+							<description>Pulse width threshold8 f\nor decode</description>
+							<bitRange>[31:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO7</name>
+							<description>Pulse width threshold7 f\nor decode</description>
+							<bitRange>[27:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO6</name>
+							<description>Pulse width threshold6 f\nor decode</description>
+							<bitRange>[23:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO5</name>
+							<description>Pulse width threshold5 f\nor decode</description>
+							<bitRange>[19:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO4</name>
+							<description>Pulse width threshold4 f\nor decode</description>
+							<bitRange>[15:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO3</name>
+							<description>Pulse width threshold3 f\nor decode</description>
+							<bitRange>[11:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO2</name>
+							<description>Pulse width threshold2 f\nor decode</description>
+							<bitRange>[7:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<field>
+							<name>RATIO1</name>
+							<description>Pulse width threshold1 f\nor decode</description>
+							<bitRange>[3:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--STATUS-->
+				<register>
+					<name>STATUS</name>
+					<description>* STATUS *</description>
+					<addressOffset>0x40</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>T3_FIFO_WR_ERR</name>
+							<description>Track 3 fifo write error</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T2_FIFO_WR_ERR</name>
+							<description>Track 2 fifo write error</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T1_FIFO_WR_ERR</name>
+							<description>Track 1 fifo write error</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T3_RX_DONE</name>
+							<description>7811 decoder rx done sig\nnal for track3</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T2_RX_DONE</name>
+							<description>7811 decoder rx done sig\nnal for track2</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T1_RX_DONE</name>
+							<description>7811 decoder rx done sig\nnal for track1</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T3_BUF_FULL</name>
+							<description>Track 3 buffer full</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T2_BUF_FULL</name>
+							<description>Track 2 buffer full</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T1_BUF_FULL</name>
+							<description>Track 1 buffer full</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TIMER_MEET</name>
+							<description>Timer meet limit</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T3_WR_DONE</name>
+							<description>Shared memory write done\n signal for track3</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T2_WR_DONE</name>
+							<description>Shared memory write done\n signal for track2</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>T1_WR_DONE</name>
+							<description>Shared memory write done\n signal for track1</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--CHAR_NUM-->
+				<register>
+					<name>CHAR_NUM</name>
+					<description>* CHAR_NUM *</description>
+					<addressOffset>0x44</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TRACK3</name>
+							<description>Track 3 character number</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK2</name>
+							<description>Track 2 character number</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK1</name>
+							<description>Track 1 character number</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--INTERFER_CHAR_NUM-->
+				<register>
+					<name>INTERFER_CHAR_NUM</name>
+					<description>* INTERFER_CHAR_NUM *</description>
+					<addressOffset>0x48</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TRACK3</name>
+							<description>Track 3 interference cha\nracter number</description>
+							<bitRange>[23:16]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK2</name>
+							<description>Track 2 interference cha\nracter number</description>
+							<bitRange>[15:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK1</name>
+							<description>Track 1 interference cha\nracter number</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--DC_EST-->
+				<register>
+					<name>DC_EST</name>
+					<description>* DC_EST *</description>
+					<addressOffset>0x4c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>TRACK3</name>
+							<description>Track 3 dc value for dco\nc</description>
+							<bitRange>[29:20]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK2</name>
+							<description>Track 2 dc value for dco\nc</description>
+							<bitRange>[19:10]</bitRange>
+							<access>read-only</access>
+						</field>
+						<field>
+							<name>TRACK1</name>
+							<description>Track 1 dc value for dco\nc</description>
+							<bitRange>[9:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!--END_ADDR_T1-->
+				<register>
+					<name>END_ADDR_T1</name>
+					<description>* END_ADDR_T1 *</description>
+					<addressOffset>0x50</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_END_ADDR</name>
+							<description>Character write end addr\ness for track 1</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--END_ADDR_T2-->
+				<register>
+					<name>END_ADDR_T2</name>
+					<description>* END_ADDR_T2 *</description>
+					<addressOffset>0x54</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_END_ADDR</name>
+							<description>Character write end addr\ness for track 2</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--END_ADDR_T3-->
+				<register>
+					<name>END_ADDR_T3</name>
+					<description>* END_ADDR_T3 *</description>
+					<addressOffset>0x58</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>ISO_END_ADDR</name>
+							<description>Character write end addr\ness for track 3</description>
+							<bitRange>[19:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!--TIMER_LIMIT-->
+				<register>
+					<name>TIMER_LIMIT</name>
+					<description>* TIMER_LIMIT *</description>
+					<addressOffset>0x5c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<field>
+							<name>LIMIT</name>
+							<description>Timer limit for interrup\nt</description>
+							<bitRange>[31:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ANA_LDO_CLK -->
+		<peripheral>
+			<name>ANA_LDO_CLK</name>
+			<version>1.0</version>
+			<description>32 ANA_LDO_CLK</description>
+			<groupName>ANA_LDO_CLK</groupName>
+			<baseAddress>0xfb200</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x4</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- LDO_CTRL -->
+				<register>
+					<name>LDO_CTRL</name>
+					<description>LDO control</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0x35494</resetValue>
+					<fields>
+						<!-- OTP_LDO_VSEL -->
+						<field>
+							<name>OTP_LDO_VSEL</name>
+							<description>OTP ldo25 voitage selction</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- OTP_LDO_EN -->
+						<field>
+							<name>OTP_LDO_EN</name>
+							<description>OTP ldo25 enable</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_CARD_VSEL -->
+						<field>
+							<name>LDO_CARD_VSEL</name>
+							<description>7816 LDO output voltage select</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_CARD_EN -->
+						<field>
+							<name>LDO_CARD_EN</name>
+							<description>7816 LDO enable</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_CARD_OCP_EN -->
+						<field>
+							<name>LDO_CARD_OCP_EN</name>
+							<description>7816 LDO over-current protection</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_CARD_VTRIM -->
+						<field>
+							<name>LDO_CARD_VTRIM</name>
+							<description>7816 LDO output voltage trim</description>
+							<bitRange>[10:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_CARD_0P33VDD -->
+						<field>
+							<name>LDO_CARD_0P33VDD</name>
+							<description>7816 sink LDO for GPIO floating ground pull down</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_BBPLLVCO_VSEL -->
+						<field>
+							<name>LDO_BBPLLVCO_VSEL</name>
+							<description>bbpll vco ldo output voltage select</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_BBPLL_VSEL -->
+						<field>
+							<name>LDO_BBPLL_VSEL</name>
+							<description>bbpll ldo output voltage select</description>
+							<bitRange>[15:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_IBLOAD_SEL -->
+						<field>
+							<name>LDO_IBLOAD_SEL</name>
+							<description>bbpll bleed current sel</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_HVSEL -->
+						<field>
+							<name>LDO_HVSEL</name>
+							<description>bbpll ldo high voltage sel</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_EN_BBPLL2 -->
+						<field>
+							<name>LDO_EN_BBPLL2</name>
+							<description>bbpll2 ldo enable</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- LDO_EN_BBPLL1 -->
+						<field>
+							<name>LDO_EN_BBPLL1</name>
+							<description>bbpll1 ldo enable</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ANA_BBPLL -->
+		<peripheral>
+			<name>ANA_BBPLL</name>
+			<version>1.0</version>
+			<description>32 ANA_BBPLL</description>
+			<groupName>ANA_BBPLL</groupName>
+			<baseAddress>0xfb210</baseAddress>
+			<addressBlock>
+				<offset>0x00</offset>
+				<size>0x1c</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- BBPLL1_CTRL0 -->
+				<register>
+					<name>BBPLL1_CTRL0</name>
+					<description>BBPLL1 control</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x80102</resetValue>
+					<fields>
+						<!-- BBPLL1_CP_IBSEL -->
+						<field>
+							<name>BBPLL1_CP_IBSEL</name>
+							<description>lcp sel</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_CLKGEN_CK48M_WIDTH -->
+						<field>
+							<name>BBPLL1_CLKGEN_CK48M_WIDTH</name>
+							<description>pulse width select</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_CLKGEN_CK48M_SEL -->
+						<field>
+							<name>BBPLL1_CLKGEN_CK48M_SEL</name>
+							<description>Pulse width select mode enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_CLKGEN_CK48M_DIVN -->
+						<field>
+							<name>BBPLL1_CLKGEN_CK48M_DIVN</name>
+							<description>div_ratio of 48MHz</description>
+							<bitRange>[22:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL1_CTRL1 -->
+				<register>
+					<name>BBPLL1_CTRL1</name>
+					<description>BBPLL1 control</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- BBPLL1_DIVR_FRAC -->
+						<field>
+							<name>BBPLL1_DIVR_FRAC</name>
+							<description>divr of pll</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL1_CTRL2 -->
+				<register>
+					<name>BBPLL1_CTRL2</name>
+					<description>BBPLL1 control</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0xA0052</resetValue>
+					<fields>
+						<!-- BBPLL1_VCO_IBSEL -->
+						<field>
+							<name>BBPLL1_VCO_IBSEL</name>
+							<description>Bias current select of vco</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_RSTN -->
+						<field>
+							<name>BBPLL1_RSTN</name>
+							<description>Reset signal of pll</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_LOOPDIV_WIDTH -->
+						<field>
+							<name>BBPLL1_LOOPDIV_WIDTH</name>
+							<description>Pulse width select</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_LOOPDIV_SEL -->
+						<field>
+							<name>BBPLL1_LOOPDIV_SEL</name>
+							<description>Pulse width select mode enable</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_FREFDIV2_SEL -->
+						<field>
+							<name>BBPLL1_FREFDIV2_SEL</name>
+							<description>Reference clk div sel</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_VCO -->
+						<field>
+							<name>BBPLL1_EN_VCO</name>
+							<description>VCO enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_PFDCP -->
+						<field>
+							<name>BBPLL1_EN_PFDCP</name>
+							<description>pfd and chargepump enable</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_LOOPDIV -->
+						<field>
+							<name>BBPLL1_EN_LOOPDIV</name>
+							<description>loopdivider enable</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_CLKGEN_CK48M_DIV2 -->
+						<field>
+							<name>BBPLL1_EN_CLKGEN_CK48M_DIV2</name>
+							<description>48M div2 enable</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_CLKGEN_256M -->
+						<field>
+							<name>BBPLL1_EN_CLKGEN_256M</name>
+							<description>256M clk_gen enable</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_CLKGEN_192M -->
+						<field>
+							<name>BBPLL1_EN_CLKGEN_192M</name>
+							<description>192M clk_gen enable</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_CLKGEN_48M -->
+						<field>
+							<name>BBPLL1_EN_CLKGEN_48M</name>
+							<description>48M clk_gen enable</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_EN_CLKGEN -->
+						<field>
+							<name>BBPLL1_EN_CLKGEN</name>
+							<description>clk_gen enable</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_DIVR_INT -->
+						<field>
+							<name>BBPLL1_DIVR_INT</name>
+							<description>divr of pll</description>
+							<bitRange>[21:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL2_CTRL0 -->
+				<register>
+					<name>BBPLL2_CTRL0</name>
+					<description>BBPLL2 control</description>
+					<addressOffset>0xc</addressOffset>
+					<size>32</size>
+					<resetValue>0x80102</resetValue>
+					<fields>
+						<!-- BBPLL2_CP_IBSEL -->
+						<field>
+							<name>BBPLL2_CP_IBSEL</name>
+							<description>lcp sel</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_CLKGEN_CK48M_WIDTH -->
+						<field>
+							<name>BBPLL2_CLKGEN_CK48M_WIDTH</name>
+							<description>pulse width select</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_CLKGEN_CK48M_SEL -->
+						<field>
+							<name>BBPLL2_CLKGEN_CK48M_SEL</name>
+							<description>Pulse width select mode enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_CLKGEN_CK48M_DIVN -->
+						<field>
+							<name>BBPLL2_CLKGEN_CK48M_DIVN</name>
+							<description>div_ratio of 48MHz</description>
+							<bitRange>[22:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL2_CTRL1 -->
+				<register>
+					<name>BBPLL2_CTRL1</name>
+					<description>BBPLL2 control</description>
+					<addressOffset>0x10</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- BBPLL2_DIVR_FRAC -->
+						<field>
+							<name>BBPLL2_DIVR_FRAC</name>
+							<description>divr of pll</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL2_CTRL2 -->
+				<register>
+					<name>BBPLL2_CTRL2</name>
+					<description>BBPLL2 control</description>
+					<addressOffset>0x14</addressOffset>
+					<size>32</size>
+					<resetValue>0xA0050</resetValue>
+					<fields>
+						<!-- BBPLL2_VCO_IBSEL -->
+						<field>
+							<name>BBPLL2_VCO_IBSEL</name>
+							<description>Bias current select of vco</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_RSTN -->
+						<field>
+							<name>BBPLL2_RSTN</name>
+							<description>Reset signal of pll</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_LOOPDIV_WIDTH -->
+						<field>
+							<name>BBPLL2_LOOPDIV_WIDTH</name>
+							<description>Pulse width select</description>
+							<bitRange>[5:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_LOOPDIV_SEL -->
+						<field>
+							<name>BBPLL2_LOOPDIV_SEL</name>
+							<description>Pulse width select mode enable</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_FREFDIV2_SEL -->
+						<field>
+							<name>BBPLL2_FREFDIV2_SEL</name>
+							<description>Reference clk div sel</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_VCO -->
+						<field>
+							<name>BBPLL2_EN_VCO</name>
+							<description>VCO enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_PFDCP -->
+						<field>
+							<name>BBPLL2_EN_PFDCP</name>
+							<description>pfd and chargepump enable</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_LOOPDIV -->
+						<field>
+							<name>BBPLL2_EN_LOOPDIV</name>
+							<description>loopdivider enable</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_CLKGEN_CK48M_DIV2 -->
+						<field>
+							<name>BBPLL2_EN_CLKGEN_CK48M_DIV2</name>
+							<description>48M div2 enable</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_CLKGEN_256M -->
+						<field>
+							<name>BBPLL2_EN_CLKGEN_256M</name>
+							<description>256M clk_gen enable</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_CLKGEN_192M -->
+						<field>
+							<name>BBPLL2_EN_CLKGEN_192M</name>
+							<description>192M clk_gen enable</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_CLKGEN_48M -->
+						<field>
+							<name>BBPLL2_EN_CLKGEN_48M</name>
+							<description>48M clk_gen enable</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_EN_CLKGEN -->
+						<field>
+							<name>BBPLL2_EN_CLKGEN</name>
+							<description>clk_gen enable</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_DIVR_INT -->
+						<field>
+							<name>BBPLL2_DIVR_INT</name>
+							<description>divr of pll</description>
+							<bitRange>[21:16]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- BBPLL_CTRL -->
+				<register>
+					<name>BBPLL_CTRL</name>
+					<description>BBPLL control</description>
+					<addressOffset>0x18</addressOffset>
+					<size>32</size>
+					<resetValue>0x400100</resetValue>
+					<fields>
+						<!-- BBPLL_TST_SEL -->
+						<field>
+							<name>BBPLL_TST_SEL</name>
+							<description>pll test select</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_TST_EN_VCTRL -->
+						<field>
+							<name>BBPLL_TST_EN_VCTRL</name>
+							<description>vctrl test enable</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_TST_EN_CK -->
+						<field>
+							<name>BBPLL_TST_EN_CK</name>
+							<description>clk test enable</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_TST_EN -->
+						<field>
+							<name>BBPLL_TST_EN</name>
+							<description>pll test enable</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_TST_CKSEL -->
+						<field>
+							<name>BBPLL_TST_CKSEL</name>
+							<description>clk test select</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_PFD_TONSEL -->
+						<field>
+							<name>BBPLL_PFD_TONSEL</name>
+							<description>pfd ton select</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_PFD_PWERES_SEL -->
+						<field>
+							<name>BBPLL_PFD_PWERES_SEL</name>
+							<description>Power Res select</description>
+							<bitRange>[9:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_DSM_ORDER_SEL -->
+						<field>
+							<name>BBPLL_DSM_ORDER_SEL</name>
+							<description>DSM mesh order select</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_DSM_DITHEREN -->
+						<field>
+							<name>BBPLL_DSM_DITHEREN</name>
+							<description>DSM dither enable</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_PFD_FREF_PHSEL -->
+						<field>
+							<name>BBPLL2_PFD_FREF_PHSEL</name>
+							<description>fref phase select</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_PFD_FDIV_PHSEL -->
+						<field>
+							<name>BBPLL2_PFD_FDIV_PHSEL</name>
+							<description>fdiv phase select</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_DSM_CKSEL -->
+						<field>
+							<name>BBPLL2_DSM_CKSEL</name>
+							<description>DSM clk select</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL2_DSM_CK_PHSEL -->
+						<field>
+							<name>BBPLL2_DSM_CK_PHSEL</name>
+							<description>DSM clk phase select</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_PFD_FREF_PHSEL -->
+						<field>
+							<name>BBPLL1_PFD_FREF_PHSEL</name>
+							<description>fref phase select</description>
+							<bitRange>[16:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_PFD_FDIV_PHSEL -->
+						<field>
+							<name>BBPLL1_PFD_FDIV_PHSEL</name>
+							<description>fdiv phase select</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_DSM_CKSEL -->
+						<field>
+							<name>BBPLL1_DSM_CKSEL</name>
+							<description>DSM clk select</description>
+							<bitRange>[18:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL1_DSM_CK_PHSEL -->
+						<field>
+							<name>BBPLL1_DSM_CK_PHSEL</name>
+							<description>DSM clk phase select</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- BBPLL_CKIN_SEL -->
+						<field>
+							<name>BBPLL_CKIN_SEL</name>
+							<description>PLL clk input select</description>
+							<bitRange>[21:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_BBPLL_CLKGEN_PWERES_SEL -->
+						<field>
+							<name>RG_BBPLL_CLKGEN_PWERES_SEL</name>
+							<description>Power Res select</description>
+							<bitRange>[23:22]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ANA_MCR -->
+		<peripheral>
+			<name>ANA_MCR</name>
+			<version>1.0</version>
+			<description>32 ANA_MCR</description>
+			<groupName>ANA_MCR</groupName>
+			<baseAddress>0xfb230</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0xc</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- MCR_CTRL0 -->
+				<register>
+					<name>CTRL0</name>
+					<description>MCR control</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0x9494c200</resetValue>
+					<fields>
+						<!-- ADC_CLK_EN -->
+						<field>
+							<name>ADC_CLK_EN</name>
+							<description>MCR ADC clock enable</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_EN -->
+						<field>
+							<name>ADC_EN</name>
+							<description>MCR ADC enable</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_EN_BIASGEN -->
+						<field>
+							<name>ADC_EN_BIASGEN</name>
+							<description>MCR ADC reference voltage enable</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ADC_EN_CONSTGM -->
+						<field>
+							<name>ADC_EN_CONSTGM</name>
+							<description>MCR ADC constant Gm bias enable</description>
+							<bitRange>[12:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ADC_EN_REG -->
+						<field>
+							<name>ADC_EN_REG</name>
+							<description>MCR ADC regulator enable</description>
+							<bitRange>[13:13]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ADC_CLKSEL -->
+						<field>
+							<name>ADC_CLKSEL</name>
+							<description>MCR ADC clock select</description>
+							<bitRange>[15:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_DCOC_PGA0 -->
+						<field>
+							<name>DCOC_PGA0</name>
+							<description>MCR CH0 PGA DCOC DAC input</description>
+							<bitRange>[21:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_REFBUF_VREF -->
+						<field>
+							<name>ADC_REFBUF_VREF</name>
+							<description>MCR ADC differential reference voltage control</description>
+							<bitRange>[23:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DCOC_PGA1 -->
+						<field>
+							<name>DCOC_PGA1</name>
+							<description>MCR CH1 PGA DCOC DAC input</description>
+							<bitRange>[29:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_REGA_VCTRL -->
+						<field>
+							<name>ADC_REGA_VCTRL</name>
+							<description>MCR ADC analog regulator output voltage control</description>
+							<bitRange>[31:30]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- MCR_CTRL1 -->
+				<register>
+					<name>CTRL1</name>
+					<description>MCR control</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x3156780</resetValue>
+					<fields>
+						<!-- MCR_DCOC_PGA2 -->
+						<field>
+							<name>DCOC_PGA2</name>
+							<description>MCR CH2 PGA DCOC DAC input</description>
+							<bitRange>[5:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_REGD_VCTRL -->
+						<field>
+							<name>ADC_REGD_VCTRL</name>
+							<description>MCR ADC digital regulator output voltage control</description>
+							<bitRange>[7:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_IBC_REFBUF -->
+						<field>
+							<name>ADC_IBC_REFBUF</name>
+							<description>MCR ADC differential reference voltage buffer bias current control</description>
+							<bitRange>[10:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_IBC_REFBUF2 -->
+						<field>
+							<name>ADC_IBC_REFBUF2</name>
+							<description>MCR ADC bias voltage buffer bias current control</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_ADC_VCTRL_BIASGEN -->
+						<field>
+							<name>ADC_VCTRL_BIASGEN</name>
+							<description>MCR ADC bias voltage control</description>
+							<bitRange>[14:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA0_EN -->
+						<field>
+							<name>PGA0_EN</name>
+							<description>MCR CH0 PGA enable</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_CSEL -->
+						<field>
+							<name>PGA_CSEL</name>
+							<description>MCR lowpass cap selection cap</description>
+							<bitRange>[18:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA1_EN -->
+						<field>
+							<name>PGA1_EN</name>
+							<description>MCR CH1 PGA enable</description>
+							<bitRange>[19:19]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_IOUTSEL -->
+						<field>
+							<name>PGA_IOUTSEL</name>
+							<description>MCR PAG output current enhance</description>
+							<bitRange>[22:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA2_EN -->
+						<field>
+							<name>PGA2_EN</name>
+							<description>MCR CH2 PGA enable</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_R1SEL -->
+						<field>
+							<name>PGA_R1SEL</name>
+							<description>pag input resistor selection</description>
+							<bitRange>[26:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_VCM_GEN_EN -->
+						<field>
+							<name>PGA_VCM_GEN_EN</name>
+							<description>MCR PGA input common mode buffer enable</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_CM_EN -->
+						<field>
+							<name>PGA_CM_EN</name>
+							<description>MCR PGA input common mode feedback enable</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- MCR_CTRL2 -->
+				<register>
+					<name>CTRL2</name>
+					<description>MCR control</description>
+					<addressOffset>0x8</addressOffset>
+					<size>32</size>
+					<resetValue>0xc630000</resetValue>
+					<fields>
+						<!-- MCR_PGA_RES_BYPASS -->
+						<field>
+							<name>PGA_RES_BYPASS</name>
+							<description>MCR control</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MCR_PGA_LDO_EN -->
+						<field>
+							<name>PGA_LDO_EN</name>
+							<description>MCR PGA LDO enable</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr adc test channel sel -->
+						<field>
+							<name>ADC_CHANNEL_SEL</name>
+							<description>mcr adc test channel sel</description>
+							<bitRange>[13:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr adc test channel enable -->
+						<field>
+							<name>ADC_CHANNEL_EN</name>
+							<description>mcr adc test channel enable</description>
+							<bitRange>[14:14]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr adc test out enable -->
+						<field>
+							<name>ADC_OUT_EN</name>
+							<description>MCR adc input connect to test pad enable</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr pga0 gc -->
+						<field>
+							<name>PGA0_GC</name>
+							<description>MCR CH0 PGA gain control</description>
+							<bitRange>[20:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr pga1 gc -->
+						<field>
+							<name>PGA1_GC</name>
+							<description>MCR CH1 PGA gain control</description>
+							<bitRange>[25:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mcr pga2 gc -->
+						<field>
+							<name>PGA2_GC</name>
+							<description>MCR CH2 PGA gain control</description>
+							<bitRange>[30:26]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ADC_ANALOG -->
+		<peripheral>
+			<name>ADC_ANALOG</name>
+			<version>1.0</version>
+			<description>32 ADC_ANALOG</description>
+			<groupName>ADC_ANALOG</groupName>
+			<baseAddress>0xfb240</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x8</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- ADC_CTRL0 -->
+				<register>
+					<name>ADC_CTRL0</name>
+					<description>ADC_CTRL0</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0X8830</resetValue>
+					<fields>
+						<!-- MISC_SARADC_EN_REG -->
+						<field>
+							<name>MISC_SARADC_EN_REG</name>
+							<description>GPADC regulator enable. 0: off; 1: on</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_EN_CONSTGM -->
+						<field>
+							<name>MISC_SARADC_EN_CONSTGM</name>
+							<description>GPADC constant Gm bias enable. 0: off; 1: on</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_EN_BIASGEN -->
+						<field>
+							<name>MISC_SARADC_EN_BIASGEN</name>
+							<description>GPADC reference voltage enable. 0: off; 1: on</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_EN -->
+						<field>
+							<name>MISC_SARADC_EN</name>
+							<description>GPADC enable. 0: off; 1: on</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_GBG_FASTSETTLING -->
+						<field>
+							<name>MISC_GBG_FASTSETTLING</name>
+							<description>The global bandgap fast settling enable</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_GBG_EN -->
+						<field>
+							<name>MISC_GBG_EN</name>
+							<description>The global bandgap enable</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- ADC_CTRL1 -->
+				<register>
+					<name>ADC_CTRL1</name>
+					<description>ADC_CTRL1</description>
+					<addressOffset>0x04</addressOffset>
+					<size>32</size>
+					<resetValue>0xF7F0A86</resetValue>
+					<fields>
+						<!-- MISC_SARADC_VCTRL_BIASGEN -->
+						<field>
+							<name>MISC_SARADC_VCTRL_BIASGEN</name>
+							<description>GPADC bias voltage control 425mV+25mV*misc_saradc_vctrl_biasgen</description>
+							<bitRange>[2:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_SEL_CH_S -->
+						<field>
+							<name>MISC_SARADC_SEL_CH_S</name>
+							<description>GPADC channel select</description>
+							<bitRange>[5:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_REGD_VCTRL -->
+						<field>
+							<name>MISC_SARADC_REGD_VCTRL</name>
+							<description>GPADC digital regulator output voltage control. 0: 1.0V; 1: 1.1V; 2: 1.2V; 3: 1.3V</description>
+							<bitRange>[7:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_REGA_VCTRL -->
+						<field>
+							<name>MISC_SARADC_REGA_VCTRL</name>
+							<description>GPADC analog regulator output voltage control. 0: 1.0V; 1: 1.1V; 2: 1.2V; 3: 1.3V</description>
+							<bitRange>[9:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_REFBUF_VREF_CTRL -->
+						<field>
+							<name>MISC_SARADC_REFBUF_VREF_CTRL</name>
+							<description>GPADC differential reference voltage control.</description>
+							<bitRange>[11:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_MODE -->
+						<field>
+							<name>MISC_SARADC_MODE</name>
+							<description>0=gpio,1=gpio diff,2=hvin,3=vinlpm,4=temperature</description>
+							<bitRange>[14:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBUF_GC -->
+						<field>
+							<name>MISC_SARADC_IBUF_GC</name>
+							<description>GPADC full scale control</description>
+							<bitRange>[16:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBUF_EN_RC -->
+						<field>
+							<name>MISC_SARADC_IBUF_EN_RC</name>
+							<description>GPADC input buffer feedback capacitor enable</description>
+							<bitRange>[17:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBUF_BW -->
+						<field>
+							<name>MISC_SARADC_IBUF_BW</name>
+							<description>GPADC input buffer bandwidth control</description>
+							<bitRange>[19:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- SINGLE_START -->
+						<field>
+							<name>MISC_SARADC_IBC_REFBUF</name>
+							<description>GPADC differential reference voltage buffer bias current control</description>
+							<bitRange>[22:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBC_REFBUF2 -->
+						<field>
+							<name>MISC_SARADC_IBC_REFBUF2</name>
+							<description>GPADC bias voltage buffer bias current control</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBC_IBUF -->
+						<field>
+							<name>MISC_SARADC_IBC_IBUF</name>
+							<description>GPAADC input buffer bias control</description>
+							<bitRange>[26:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- MISC_SARADC_IBC_CMBUF -->
+						<field>
+							<name>MISC_SARADC_IBC_CMBUF</name>
+							<description>GPADC biasgen buffer bias current control</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ANA_RNG -->
+		<peripheral>
+			<name>ANA_RNG</name>
+			<version>1.0</version>
+			<description>32 ANA_RNG</description>
+			<groupName>ANA_RNG</groupName>
+			<baseAddress>0xfb260</baseAddress>
+			<addressBlock>
+				<offset>0x00</offset>
+				<size>0x8</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- RNG_CTRL0 -->
+				<register>
+					<name>RNG_CTRL0</name>
+					<description>RNG control</description>
+					<addressOffset>0x0</addressOffset>
+					<size>32</size>
+					<resetValue>0x80000</resetValue>
+					<fields>
+						<!-- RG_NCS_I_SET -->
+						<field>
+							<name>RG_NCS_I_SET</name>
+							<description>NCS current setting</description>
+							<bitRange>[19:17]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_NCS_EN -->
+						<field>
+							<name>DA_NCS_EN</name>
+							<description>NCS enable</description>
+							<bitRange>[20:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_NCS_RESETN -->
+						<field>
+							<name>DA_NCS_RESETN</name>
+							<description>NCS reset</description>
+							<bitRange>[21:21]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_LDO_TRNG_EN -->
+						<field>
+							<name>DA_LDO_TRNG_EN</name>
+							<description>Security TRNG LDO enable.</description>
+							<bitRange>[22:22]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_BIAS_EN -->
+						<field>
+							<name>DA_TRNG_BIAS_EN</name>
+							<description>TRNG bias enable signal, high active</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGA_OSCJ_EN -->
+						<field>
+							<name>DA_TRNG_TRNGA_OSCJ_EN</name>
+							<description>TRNGA LFOSC enable signal,high active</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGB_OSCJ_EN -->
+						<field>
+							<name>DA_TRNG_TRNGB_OSCJ_EN</name>
+							<description>TRNGB LFOSC enable signal,high active</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGC_OSCJ_EN -->
+						<field>
+							<name>DA_TRNG_TRNGC_OSCJ_EN</name>
+							<description>TRNGC LFOSC enable signal,high active</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGD_OSCJ_EN -->
+						<field>
+							<name>DA_TRNG_TRNGD_OSCJ_EN</name>
+							<description>TRNGD LFOSC enable signal,high active</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOA_EN -->
+						<field>
+							<name>DA_TRNG_TRNGOA_EN</name>
+							<description>TRNGA HFOSC enable signal,high active</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOB_EN -->
+						<field>
+							<name>DA_TRNG_TRNGOB_EN</name>
+							<description>TRNGB HFOSC enable signal,high active</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOC_EN -->
+						<field>
+							<name>DA_TRNG_TRNGOC_EN</name>
+							<description>TRNGC HFOSC enable signal,high active</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOD_EN -->
+						<field>
+							<name>DA_TRNG_TRNGOD_EN</name>
+							<description>TRNGD HFOSC enable signal,high active</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- RNG_CTRL1 -->
+				<register>
+					<name>RNG_CTRL1</name>
+					<description>RNG control</description>
+					<addressOffset>0x4</addressOffset>
+					<size>32</size>
+					<resetValue>0x45454545</resetValue>
+					<fields>
+						<!-- RG_TRNG_TRNGA_ON_JITTER -->
+						<field>
+							<name>RG_TRNG_TRNGA_ON_JITTER</name>
+							<description>TRNGA LFOSC jitter control signal</description>
+							<bitRange>[1:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGA_OSCJ_TRIM -->
+						<field>
+							<name>RG_TRNG_TRNGA_OSCJ_TRIM</name>
+							<description>TRNGA LFOSC frequency control signal</description>
+							<bitRange>[3:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGA_OSCJ_VREF -->
+						<field>
+							<name>RG_TRNG_TRNGA_OSCJ_VREF</name>
+							<description>TRNGA LFOSC vref control signal</description>
+							<bitRange>[6:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOA_CLR -->
+						<field>
+							<name>DA_TRNG_TRNGOA_CLR</name>
+							<description>TRNGA sample DFF output clear signal,low active</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGB_ON_JITTER -->
+						<field>
+							<name>RG_TRNG_TRNGB_ON_JITTER</name>
+							<description>TRNGB LFOSC jitter control signal</description>
+							<bitRange>[9:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGB_OSCJ_TRIM -->
+						<field>
+							<name>RG_TRNG_TRNGB_OSCJ_TRIM</name>
+							<description>TRNGB LFOSC frequency control signal</description>
+							<bitRange>[11:10]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGB_OSCJ_VREF -->
+						<field>
+							<name>RG_TRNG_TRNGB_OSCJ_VREF</name>
+							<description>TRNGB LFOSC vref control signal</description>
+							<bitRange>[14:12]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOB_CLR -->
+						<field>
+							<name>DA_TRNG_TRNGOB_CLR</name>
+							<description>TRNGB sample DFF output clear signal,low active</description>
+							<bitRange>[15:15]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGC_ON_JITTER -->
+						<field>
+							<name>RG_TRNG_TRNGC_ON_JITTER</name>
+							<description>TRNGC LFOSC jitter control signal</description>
+							<bitRange>[17:16]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGC_OSCJ_TRIM -->
+						<field>
+							<name>RG_TRNG_TRNGC_OSCJ_TRIM</name>
+							<description>TRNGC LFOSC frequency control signal</description>
+							<bitRange>[19:18]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGC_OSCJ_VREF -->
+						<field>
+							<name>RG_TRNG_TRNGC_OSCJ_VREF</name>
+							<description>TRNGC LFOSC vref control signal</description>
+							<bitRange>[22:20]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOC_CLR -->
+						<field>
+							<name>DA_TRNG_TRNGOC_CLR</name>
+							<description>TRNGC sample DFF output clear signal,low active</description>
+							<bitRange>[23:23]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGD_ON_JITTER -->
+						<field>
+							<name>RG_TRNG_TRNGD_ON_JITTER</name>
+							<description>TRNGD LFOSC jitter control signal</description>
+							<bitRange>[25:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGD_OSCJ_TRIM -->
+						<field>
+							<name>RG_TRNG_TRNGD_OSCJ_TRIM</name>
+							<description>TRNGD LFOSC frequency control signal</description>
+							<bitRange>[27:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RG_TRNG_TRNGD_OSCJ_VREF -->
+						<field>
+							<name>RG_TRNG_TRNGD_OSCJ_VREF</name>
+							<description>TRNGD LFOSC vref control signal</description>
+							<bitRange>[30:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- DA_TRNG_TRNGOD_CLR -->
+						<field>
+							<name>DA_TRNG_TRNGOD_CLR</name>
+							<description>TRNGD sample DFF output clear signal,low active</description>
+							<bitRange>[31:31]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- ANA_CHGR -->
+		<peripheral>
+			<name>ANA_CHGR</name>
+			<version>1.0</version>
+			<description>32 ANA</description>
+			<groupName>ANA_CHGR</groupName>
+			<baseAddress>0xfb270</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x4</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- CHGR STATE -->
+				<register>
+					<name>STATE</name>
+					<description>CHGR state</description>
+					<addressOffset>0x00</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- CHGR_STATE_VBAT_LV -->
+						<field>
+							<name>CHGR_STATE_VBAT_LV</name>
+							<description>CHGR_STATE_VBAT_LV</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_STAT_RCH_EN -->
+						<field>
+							<name>CHGR_STATE_RCH_EN</name>
+							<description>CHGR_STAT_RCH_EN</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_STATE_IND -->
+						<field>
+							<name>CHGR_STATE_IND</name>
+							<description>CHGR_STATE_IND</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_STATE_ICHG -->
+						<field>
+							<name>CHGR_STATE_ICHG</name>
+							<description>CHGR_STATE_ICHG</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_RESET -->
+						<field>
+							<name>CHGR_RESET</name>
+							<description>CHGR_RESET</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_UVLO_OK_AON -->
+						<field>
+							<name>CHGR_UVLO_OK_AON</name>
+							<description>CHGR_UVLO_OK_AON</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_PGOOD -->
+						<field>
+							<name>CHGR_PGOOD</name>
+							<description>CHGR_PGOOD</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_DPPM_OV_CV -->
+						<field>
+							<name>CHGR_DPPM_OV_CV</name>
+							<description>CHGR_DPPM_OV_CC</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_DPPM_OV_CC -->
+						<field>
+							<name>CHGR_DPPM_OV_CC</name>
+							<description>CHGR_DPPM_OV_CC</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_CC_OV_CV -->
+						<field>
+							<name>CHGR_CC_OV_CV</name>
+							<description>CHGR_CC_OV_CV</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- CHGR_IN_DET_AON -->
+						<field>
+							<name>CHGR_IN_DET_AON</name>
+							<description>CHGR_IN_DET_AON</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- VBAT_OV_FLAG -->
+						<field>
+							<name>VBAT_OV_FLAG</name>
+							<description>VBAT_OV_FLAG</description>
+							<bitRange>[11:11]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+		<!-- USB -->
+		<peripheral>
+			<name>USB</name>
+			<version>1.0</version>
+			<description>32 USB</description>
+			<groupName>USB</groupName>
+			<baseAddress>0xfb400</baseAddress>
+			<addressBlock>
+				<offset>0</offset>
+				<size>0x3A</size>
+				<usage>registers</usage>
+			</addressBlock>
+			<registers>
+				<!-- USB_CONFIG -->
+				<register>
+					<name>USB_CONFIG</name>
+					<description>USB_CONFIG</description>
+					<addressOffset>0x00</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- enable_iso[0] -->
+						<field>
+							<name>enable_iso[0]</name>
+							<description>enable ISO for endpoint 2 OUT</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- enable_iso[1] -->
+						<field>
+							<name>enable_iso[1]</name>
+							<description>1:enable ISO for endpoint 2 IN</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- bias -->
+						<field>
+							<name>bias</name>
+							<description>USB pad bias control</description>
+							<bitRange>[3:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- usb_en -->
+						<field>
+							<name>usb_en</name>
+							<description>enable usb function</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- dev_speed -->
+						<field>
+							<name>dev_speed</name>
+							<description>enable usb function</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- dev_resume -->
+						<field>
+							<name>dev_resume</name>
+							<description>resume device</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- epc_rmtwkupfeat -->
+						<field>
+							<name>epc_rmtwkupfeat</name>
+							<description>endpoint wakeup enable</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_INT_MASK -->
+				<register>
+					<name>USB_INT_MASK</name>
+					<description>USB_INT_MASK</description>
+					<addressOffset>0x01</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- setup_irq_mask -->
+						<field>
+							<name>setup_irq_mask</name>
+							<description>setup interrupt mask</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- suspend_irq_mask -->
+						<field>
+							<name>suspend_irq_mask</name>
+							<description>suspend interrupt mask</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- NAK_irq_mask -->
+						<field>
+							<name>NAK_irq_mask</name>
+							<description>NAK interrupt mask</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- reset_irq_mask -->
+						<field>
+							<name>reset_irq_mask</name>
+							<description>reset interrupt mask</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ACK_irq_mask -->
+						<field>
+							<name>ACK_irq_mask</name>
+							<description>ACK interrupt mask</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RXready_irq_mask -->
+						<field>
+							<name>RXready_irq_mask</name>
+							<description>RXready interrupt mask</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RXfull_irq_mask -->
+						<field>
+							<name>RXfull_irq_mask</name>
+							<description>RXfull interrupt mask</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- txdone0_irq_mask -->
+						<field>
+							<name>txdone0_irq_mask</name>
+							<description>txdone0 interrupt mask</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_DRV -->
+				<register>
+					<name>USB_DRV</name>
+					<description>USB_DRV</description>
+					<addressOffset>0x02</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- txdone1_irq_mask -->
+						<field>
+							<name>txdone1_irq_mask</name>
+							<description>txdone1 interrupt mask</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- txdone2_irq_mask -->
+						<field>
+							<name>txdone2_irq_mask</name>
+							<description>txdone2 interrupt mask</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- txdone3_irq_mask -->
+						<field>
+							<name>txdone3_irq_mask</name>
+							<description>txdone3 interrupt mask</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- usb_drv-->
+						<field>
+							<name>usb_drv</name>
+							<description>usb_drv</description>
+							<bitRange>[4:3]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_ADDR -->
+				<register>
+					<name>USB_ADDR</name>
+					<description>USB_ADDR</description>
+					<addressOffset>0x03</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- dev_addr -->
+						<field>
+							<name>dev_addr</name>
+							<description>device address</description>
+							<bitRange>[6:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- bcst_noack -->
+						<field>
+							<name>bcst_noack</name>
+							<description>disable broadcast(address 0) packet receive</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_RX_SADDR -->
+				<register>
+					<name>USB_RX_SADDR</name>
+					<description>USB_RX_SADDR</description>
+					<addressOffset>0x04</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- rx_startaddr -->
+						<field>
+							<name>rx_startaddr</name>
+							<description>rx_start address</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_RX_BUFLEN -->
+				<register>
+					<name>USB_RX_BUFLEN</name>
+					<description>USB_RX_BUFLEN</description>
+					<addressOffset>0x07</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- rx_buflen -->
+						<field>
+							<name>rx_buflen</name>
+							<description>rx_buflen</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TX_SADDR0 -->
+				<register>
+					<name>USB_TX_SADDR0</name>
+					<description>USB_TX_SADDR0</description>
+					<addressOffset>0x0a</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- tx_saddr0 -->
+						<field>
+							<name>tx_saddr0</name>
+							<description>tx_saddress0</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TX_SADDR1 -->
+				<register>
+					<name>USB_TX_SADDR1</name>
+					<description>USB_TX_SADDR1</description>
+					<addressOffset>0x0d</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- tx_saddr1 -->
+						<field>
+							<name>tx_saddr1</name>
+							<description>tx_saddress1</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TX_SADDR2 -->
+				<register>
+					<name>USB_TX_SADDR2</name>
+					<description>USB_TX_SADDR2</description>
+					<addressOffset>0x10</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- tx_saddr2 -->
+						<field>
+							<name>tx_saddr2</name>
+							<description>tx_saddress2</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TX_SADDR3 -->
+				<register>
+					<name>USB_TX_SADDR3</name>
+					<description>USB_TX_SADDR3</description>
+					<addressOffset>0x13</addressOffset>
+					<size>24</size>
+					<resetValue>0x000000</resetValue>
+					<fields>
+						<!-- tx_saddr3 -->
+						<field>
+							<name>tx_saddr3</name>
+							<description>tx_saddress3</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_HMODE -->
+				<register>
+					<name>USB_HMODE</name>
+					<description>USB_HMODE</description>
+					<addressOffset>0x16</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- usb_hmode -->
+						<field>
+							<name>usb_hmode</name>
+							<description>usb host mode</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- reset_device -->
+						<field>
+							<name>reset_device</name>
+							<description>usb reset device</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- dma_enable -->
+						<field>
+							<name>dma_enable</name>
+							<description>usb dma enable</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- mram_select -->
+						<field>
+							<name>mram_select</name>
+							<description>mram select</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- sof_enable -->
+						<field>
+							<name>sof_enable</name>
+							<description>sof enable</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- sof_window -->
+						<field>
+							<name>sof_window</name>
+							<description>sof window</description>
+							<bitRange>[7:5]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_RX_RPTR -->
+				<register>
+					<name>USB_RX_RPTR</name>
+					<description>USB_RX_RPTR</description>
+					<addressOffset>0x1c</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- usb_rx_rptr -->
+						<field>
+							<name>usb_rx_rptr</name>
+							<description>USB RX DMA read pointer</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TRIG -->
+				<register>
+					<name>USB_TRIG</name>
+					<description>USB_TRIG</description>
+					<addressOffset>0x20</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- ep0_trig -->
+						<field>
+							<name>ep0_trig</name>
+							<description>send endpoint 0 data in fifo</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_trig -->
+						<field>
+							<name>ep1_trig</name>
+							<description>send endpoint 1 data in fifo</description>
+							<bitRange>[1:1]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_trig -->
+						<field>
+							<name>ep2_trig</name>
+							<description>send endpoint 2 data in fifo</description>
+							<bitRange>[2:2]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_trig -->
+						<field>
+							<name>ep3_trig</name>
+							<description>send endpoint 3 data in fifo</description>
+							<bitRange>[3:3]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep0_send_zero -->
+						<field>
+							<name>ep0_send_zero</name>
+							<description>endpoint 0 reply zero length packet to host</description>
+							<bitRange>[4:4]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_send_zero -->
+						<field>
+							<name>ep1_send_zero</name>
+							<description>endpoint 1 reply zero length packet to host</description>
+							<bitRange>[5:5]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_send_zero -->
+						<field>
+							<name>ep2_send_zero</name>
+							<description>endpoint 2 reply zero length packet to host</description>
+							<bitRange>[6:6]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_send_zero -->
+						<field>
+							<name>ep3_send_zero</name>
+							<description>endpoint 3 reply zero length packet to host</description>
+							<bitRange>[7:7]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_STALL -->
+				<register>
+					<name>USB_STALL</name>
+					<description>USB_STALL</description>
+					<addressOffset>0x21</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- ep0_stall -->
+						<field>
+							<name>ep0_stall</name>
+							<description>set endpoint 0 to stall</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_in_stall -->
+						<field>
+							<name>ep1_in_stall</name>
+							<description>set endpoint 1 in to stall</description>
+							<bitRange>[1:1]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_out_stall -->
+						<field>
+							<name>ep1_out_stall</name>
+							<description>set endpoint 1 out to stall</description>
+							<bitRange>[2:2]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_in_stall -->
+						<field>
+							<name>ep2_in_stall</name>
+							<description>set endpoint 2 in to stall</description>
+							<bitRange>[3:3]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_out_stall -->
+						<field>
+							<name>ep2_out_stall</name>
+							<description>set endpoint 2 out to stall</description>
+							<bitRange>[4:4]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_in_stall -->
+						<field>
+							<name>ep3_in_stall</name>
+							<description>set endpoint 3 in to stall</description>
+							<bitRange>[5:5]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_out_stall -->
+						<field>
+							<name>ep3_out_stall</name>
+							<description>set endpoint 3 out to stall</description>
+							<bitRange>[6:6]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- host_mode_start -->
+						<field>
+							<name>host_mode_start</name>
+							<description>host mode start</description>
+							<bitRange>[7:7]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TOGGLE -->
+				<register>
+					<name>USB_TOGGLE</name>
+					<description>USB_TOGGLE</description>
+					<addressOffset>0x22</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- ep0_toggle -->
+						<field>
+							<name>ep0_toggle</name>
+							<description>endpoint 0 to data0</description>
+							<bitRange>[0:0]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_in_toggle -->
+						<field>
+							<name>ep1_in_toggle</name>
+							<description>endpoint 1 in to data0</description>
+							<bitRange>[1:1]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep1_out_toggle -->
+						<field>
+							<name>ep1_out_toggle</name>
+							<description>endpoint 1 out to data0</description>
+							<bitRange>[2:2]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_in_toggle -->
+						<field>
+							<name>ep2_in_toggle</name>
+							<description>endpoint 2 in to data0</description>
+							<bitRange>[3:3]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep2_out_toggle -->
+						<field>
+							<name>ep2_out_toggle</name>
+							<description>endpoint 2 out to data0</description>
+							<bitRange>[4:4]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_in_toggle -->
+						<field>
+							<name>ep3_in_toggle</name>
+							<description>endpoint 3 in to data0</description>
+							<bitRange>[5:5]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- ep3_out_toggle -->
+						<field>
+							<name>ep3_out_toggle</name>
+							<description>endpoint 3 out to data0</description>
+							<bitRange>[6:6]</bitRange>
+							<access>write-only</access>
+						</field>
+						<!-- reset -->
+						<field>
+							<name>reset</name>
+							<description>reset udc and pll and rxcnt</description>
+							<bitRange>[7:7]</bitRange>
+							<access>write-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_RX_WPTR -->
+				<register>
+					<name>USB_RX_WPTR</name>
+					<description>USB_RX_WPTR</description>
+					<addressOffset>0x30</addressOffset>
+					<size>32</size>
+					<resetValue>0x00000000</resetValue>
+					<fields>
+						<!-- usb_rx_wptr -->
+						<field>
+							<name>usb_rx_wptr</name>
+							<description>USB RX DMA write pointer</description>
+							<bitRange>[23:0]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- ep0_stall_state -->
+						<field>
+							<name>ep0_stall_state</name>
+							<description>endpoint 0 stall state</description>
+							<bitRange>[24:24]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep1_in_stall_state -->
+						<field>
+							<name>ep1_in_stall_state</name>
+							<description>endpoint 1 in stall state</description>
+							<bitRange>[25:25]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep1_out_stall_state -->
+						<field>
+							<name>ep1_out_stall_state</name>
+							<description>endpoint 1 out stall state</description>
+							<bitRange>[26:26]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep2_in_stall_state -->
+						<field>
+							<name>ep2_in_stall_state</name>
+							<description>endpoint 2 in stall state</description>
+							<bitRange>[27:27]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep2_out_stall_state -->
+						<field>
+							<name>ep2_out_stall_state</name>
+							<description>endpoint 2 out stall state</description>
+							<bitRange>[28:28]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep3_in_stall_state -->
+						<field>
+							<name>ep3_in_stall_state</name>
+							<description>endpoint 3 in stall state</description>
+							<bitRange>[29:29]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ep3_out_stall_state -->
+						<field>
+							<name>ep3_out_stall_state</name>
+							<description>endpoint 3 out stall state</description>
+							<bitRange>[30:30]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_STATUS -->
+				<register>
+					<name>USB_STATUS</name>
+					<description>USB_STATUS</description>
+					<addressOffset>0x34</addressOffset>
+					<size>16</size>
+					<resetValue>0x0000</resetValue>
+					<fields>
+						<!-- setup_state -->
+						<field>
+							<name>setup_state</name>
+							<description>usb setup state</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- suspend_state -->
+						<field>
+							<name>suspend_state</name>
+							<description>usb suspend state</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- NAK_state -->
+						<field>
+							<name>NAK_state</name>
+							<description>usb NAK state</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- reset_state -->
+						<field>
+							<name>reset_state</name>
+							<description>usb reset state</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- ACK_state -->
+						<field>
+							<name>ACK_state</name>
+							<description>usb ACK state</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RX_ready_state -->
+						<field>
+							<name>RX_ready_state</name>
+							<description>usb RX ready state</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- RX_full_state -->
+						<field>
+							<name>RX_full_state</name>
+							<description>usb RX full state</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- tx_done0_state -->
+						<field>
+							<name>tx_done0_state</name>
+							<description>usb tx done0 state</description>
+							<bitRange>[7:7]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- tx_done1_state -->
+						<field>
+							<name>tx_done1_state</name>
+							<description>usb tx done1 state</description>
+							<bitRange>[8:8]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- tx_done2_state -->
+						<field>
+							<name>tx_done2_state</name>
+							<description>usb tx done2 state</description>
+							<bitRange>[9:9]</bitRange>
+							<access>read-write</access>
+						</field>
+						<!-- tx_done3_state -->
+						<field>
+							<name>tx_done3_state</name>
+							<description>usb tx done3 state</description>
+							<bitRange>[10:10]</bitRange>
+							<access>read-write</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_TX_BUSY -->
+				<register>
+					<name>USB_TX_BUSY</name>
+					<description>USB_TX_BUSY</description>
+					<addressOffset>0x36</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- ep0_in_busy -->
+						<field>
+							<name>ep0_in_busy</name>
+							<description>endpoint 0 in fifo busy state</description>
+							<bitRange>[0:0]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- ep1_in_busy -->
+						<field>
+							<name>ep1_in_busy</name>
+							<description>endpoint 1 in fifo busy state</description>
+							<bitRange>[1:1]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- ep2_in_busy -->
+						<field>
+							<name>ep2_in_busy</name>
+							<description>endpoint 2 in fifo busy state</description>
+							<bitRange>[2:2]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- ep3_in_busy -->
+						<field>
+							<name>ep3_in_busy</name>
+							<description>endpoint 3 in fifo busy state</description>
+							<bitRange>[3:3]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- usb_DN_state -->
+						<field>
+							<name>usb_DN_state</name>
+							<description>usb DN state</description>
+							<bitRange>[4:4]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- usb_DP_state -->
+						<field>
+							<name>usb_DP_state</name>
+							<description>usb DP state</description>
+							<bitRange>[5:5]</bitRange>
+							<access>read-only</access>
+						</field>
+						<!-- RX_empty_state -->
+						<field>
+							<name>RX_empty_state</name>
+							<description>usb RX empty state</description>
+							<bitRange>[6:6]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_RXCNT -->
+				<register>
+					<name>USB_RXCNT</name>
+					<description>USB_RXCNT</description>
+					<addressOffset>0x37</addressOffset>
+					<size>8</size>
+					<resetValue>0x00</resetValue>
+					<fields>
+						<!-- usb_rxcnt -->
+						<field>
+							<name>usb_rxcnt</name>
+							<description>usb rx count</description>
+							<bitRange>[7:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+				<!-- USB_SOF -->
+				<register>
+					<name>USB_SOF</name>
+					<description>USB_SOF</description>
+					<addressOffset>0x38</addressOffset>
+					<size>16</size>
+					<resetValue>0x0000</resetValue>
+					<fields>
+						<!-- usb_sofcnt -->
+						<field>
+							<name>usb_sof_cnt</name>
+							<description>usb sof count</description>
+							<bitRange>[15:0]</bitRange>
+							<access>read-only</access>
+						</field>
+					</fields>
+				</register>
+			</registers>
+		</peripheral>
+	</peripherals>
+</device>

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/system_yc3122.h

@@ -0,0 +1,79 @@
+/**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+    All rights reserved.
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    - Redistributions of source code must retain the above copyright
+        notice, this list of conditions and the following disclaimer.
+    - Redistributions in binary form must reproduce the above copyright
+        notice, this list of conditions and the following disclaimer in the
+        documentation and/or other materials provided with the distribution.
+    - Neither the name of ARM nor the names of its contributors may be used
+        to endorse or promote products derived from this software without
+        specific prior written permission.
+    *
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+    POSSIBILITY OF SUCH DAMAGE.
+    ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_YC3122_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_YC3122_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "yc3122.h"
+#include "type.h"
+#include "rom_api.h"
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/yc3122.h

@@ -0,0 +1,5342 @@
+/******************************************************************************
+ * @file     yc3122.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ *           YC3122
+ * @version  V1.00
+ * @date     15. July 2021
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+    All rights reserved.
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    - Redistributions of source code must retain the above copyright
+        notice, this list ofC conditions and the following disclaimer.
+    - Redistributions in binary form must reproduce the above copyright
+        notice, this list of conditions and the following disclaimer in the
+        documentation and/or other materials provided with the distribution.
+    - Neither the name of ARM nor the names of its contributors may be used
+        to endorse or promote products derived from this software without
+        specific prior written permission.
+    *
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+    POSSIBILITY OF SUCH DAMAGE.
+    ---------------------------------------------------------------------------*/
+
+/** @addtogroup
+  * @{
+  */
+
+/** @addtogroup YC3122
+  * @{
+  */
+
+#ifndef __YC3122_H__
+#define __YC3122_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+  /** @addtogroup Configuration_of_CMSIS
+   * @{
+   */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+typedef enum IRQn
+{
+    /******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+    Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+    NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+    HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+    SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+    PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+    SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+    /******  Device Specific Interrupt Numbers ********************************************************/
+    USB_IRQn                  = 0,
+    I2C0_IRQn                 = 1,
+    I2C1_IRQn                 = 2,
+    QSPI_IRQn                 = 3,
+    SPI0_IRQn                 = 4,
+    SPI1_IRQn                 = 5,
+    HSPI_IRQn                 = 6,
+    SEC_IRQn                  = 7,
+    UART0_IRQn                = 8,
+    UART1_IRQn                = 9,
+    UART2_IRQn                = 10,
+    UART3_IRQn                = 11,
+    MEMCP_IRQn                = 12,
+    SCI0_IRQn                 = 13,
+    SCI1_IRQn                 = 14,
+    MSR_IRQn                  = 15,
+    GPIO_IRQn                 = 16,
+    TMRG0_IRQn                = 17,
+    TMRG1_IRQn                = 18,
+    SDIO_IRQn                 = 19,
+    PSARM_IRQn                = 20,
+    RSA_IRQn                  = 21,
+    SM4_IRQn                  = 22,
+    TRNG_IRQn                 = 23,
+    WDT_IRQn                  = 24,
+    DCMI_IRQn                 = 25,
+    ADC_IRQn                  = 26,
+    RTC_IRQn                  = 27,
+    RSVD1_IRQn                = 28,
+    POWER_IRQn                = 29,
+    SOFTWARE_IRQn             = 30,
+    RISCV_IRQn                = 31
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+#define __CM0_REV                 0x0000U    /*!< Core Revision r0p0                             */
+#define __NVIC_PRIO_BITS          2U         /*!< Number of 2 Bits used for Priority Levels      */
+#define __Vendor_SysTickConfig    0U         /*!< Set to 1 if different SysTick Config is used   */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+#if defined(__USE_YC_M0__)
+#include "core_cm0.h"                       /* Cortex-M# processor and core peripherals          */
+#elif defined(__USE_YC_RISC_V__)
+#include "core_rv_31xx.h"
+#endif
+
+#include "system_yc3122.h"                  /* <Device> System  include file                     */
+
+
+#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __IM   __I
+#endif
+#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __OM   __O
+#endif
+#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
+#define __IOM  __IO
+#endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if defined (__CC_ARM)
+#pragma push
+#pragma anon_unions
+#elif defined (__ICCARM__)
+#pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wc11-extensions"
+#pragma clang diagnostic ignored "-Wreserved-id-macro"
+#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+#pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#else
+#warning Not supported compiler type
+#endif
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+#include <stdint.h>
+#include <string.h>
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+#define BIT0        (0x00000001U)
+#define BIT1        (0x00000002U)
+#define BIT2        (0x00000004U)
+#define BIT3        (0x00000008U)
+#define BIT4        (0x00000010U)
+#define BIT5        (0x00000020U)
+#define BIT6        (0x00000040U)
+#define BIT7        (0x00000080U)
+#define BIT8        (0x00000100U)
+#define BIT9        (0x00000200U)
+#define BIT10       (0x00000400U)
+#define BIT11       (0x00000800U)
+#define BIT12       (0x00001000U)
+#define BIT13       (0x00002000U)
+#define BIT14       (0x00004000U)
+#define BIT15       (0x00008000U)
+#define BIT16       (0x00010000U)
+#define BIT17       (0x00020000U)
+#define BIT18       (0x00040000U)
+#define BIT19       (0x00080000U)
+#define BIT20       (0x00100000U)
+#define BIT21       (0x00200000U)
+#define BIT22       (0x00400000U)
+#define BIT23       (0x00800000U)
+#define BIT24       (0x01000000U)
+#define BIT25       (0x02000000U)
+#define BIT26       (0x04000000U)
+#define BIT27       (0x08000000U)
+#define BIT28       (0x10000000U)
+#define BIT29       (0x20000000U)
+#define BIT30       (0x40000000U)
+#define BIT31       (0x80000000U)
+
+#define BIT(n)      (1UL << (n))
+
+
+/*Todo: DMA MPU*/
+
+#define MPU_DMA_REGION_LEN      4
+typedef struct
+{
+    __IO uint32_t REGION_SADDR      :25;
+    __IO uint32_t REGION_SADDR_RSVD :7 ;
+    __IO uint32_t REGION_EADDR      :25;
+    __IO uint32_t REGION_EADDR_RSVD :7 ;
+} REGION_ADDR_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t MPU_DMA_CTRL          :1 ;
+    __I  uint32_t MPU_DMA_CTRL_RSVD     :31;
+
+    __IO uint32_t REGION0_RW_ENABLE     :2 ;
+    __IO uint32_t REGION1_RW_ENABLE     :2 ;
+    __IO uint32_t REGION2_RW_ENABLE     :2 ;
+    __IO uint32_t REGION3_RW_ENABLE     :2 ;
+    __I  uint32_t MPU_DMA_PROT_RSVD     :24;
+    __IO uint32_t MPU_DMA0_FAULT        :2 ;   /* !< MEMCP                               */
+    __IO uint32_t MPU_DMA1_FAULT        :2 ;   /* !< USB/QSPI/DAC/SDIO/I2C/SPI/UART/7811 */
+    __IO uint32_t MPU_DMA2_FAULT        :2 ;   /* !< DCMI_DMA0                           */
+    __IO uint32_t MPU_DMA3_FAULT        :2 ;   /* !< DCMI_DMA1                           */
+    __IO uint32_t MPU_DMA4_FAULT        :2 ;   /* !< DCMI_DMA2                           */
+    __IO uint32_t MPU_DMA5_FAULT        :2 ;   /* !< PSRAM                               */
+    __IO uint32_t MPU_DMA6_FAULT        :2 ;   /* !< HSPI                                */
+    __IO uint32_t MPU_DMA7_FAULT        :2 ;   /* !< QR_BINARIZE                         */
+    __IO uint32_t MPU_DMA8_FAULT        :2 ;   /* !< QSORT                               */
+    __IO uint32_t MPU_DMA9_FAULT        :2 ;   /* !< CANNY_BINARIZE                      */
+    __IO uint32_t MPU_DMA10_FAULT       :2 ;   /* !< FAST_BINRIZE                        */
+    __I  uint32_t MPU_DMA_FAULT_RSVD    :10;
+    __I  uint32_t MPU_DMA_RSVD1[5]         ;
+
+    REGION_ADDR_TypeDef REGION_ADDRS[MPU_DMA_REGION_LEN];
+    __I  uint32_t MPU_DMA_RSVD2[16]        ;
+    __I  uint32_t DMA_FAULT_ADDR        :25;
+    __I  uint32_t DMA_FAULT_ADDR_RSVD   :7 ;
+} MPU_DMA_TypeDef;  /*132byte*/
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MMCU                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MMCU (MMCU)
+  */
+
+typedef struct {                                /*!< (@ 0x000D0000) MMCU Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL *                                                   */
+
+    struct {
+      __OM  uint32_t LTSLEEP_EN : 1;            /*!< [0..0] 使能 lightsleep                                                  */
+      __IOM uint32_t LTSLEEP    : 1;            /*!< [1..1] 写1 M0,进入浅睡眠模式
+                                                     注意:此BIT写1后必须要有6个以上的NOP指令,否则退
+                                                     出浅睡眠时可能会出错                                            */
+      __IOM uint32_t WFI_EN     : 1;            /*!< [2..2] m0 WFI的使能                                                    */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t DCLK_EN    : 1;            /*!< [4..4] m0 dclk的使能                                                   */
+      __IOM uint32_t FCLK_EN    : 1;            /*!< [5..5] m0 fclk的使能                                                   */
+      __IOM uint32_t SCSCLK_EN  : 1;            /*!< [6..6] m0 scsclk的使能                                                 */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BITBAND_CFG : 1;           /*!< [8..8] bitband 每一BIT对应的地址长度(0x2
+                                                     0000对应的地址是0x800000)
+                                                     0: RAM每一BIT对应的地址长度是8-bit
+                                                     1: RAM每一BIT对应的地址长度是32-bit                             */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * WKUP_SRC *                                               */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 唤醒中断源设置: 每1bit对应0~31号中断                 */
+    } bit;
+  } WKUP_SRC;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * ERROR_STATUS *                                           */
+
+    struct {
+      __IM  uint32_t CODE_CRC   : 1;            /*!< [0..0] 当这1bit置1,代表M0的代码 CRC校验错误                   */
+      __IM  uint32_t MEM        : 1;            /*!< [1..1] 当这1bit置1,代表ROM或RAM奇偶校验错误                   */
+      __IM  uint32_t MPU        : 1;            /*!< [2..2] 当这1bit置1,代表M0 MPU错误                                  */
+      __IM  uint32_t RAM_NOEXE  : 1;            /*!< [3..3] 当这1bit置1,代表M0 RAM执行代码错误                      */
+      __IM  uint32_t RV_MPU     : 1;            /*!< [4..4] 当这1bit置1,代表RV MPU错误                                  */
+      __IM  uint32_t RV_ACCESS  : 1;            /*!< [5..5] 当这1bit置1,代表risc-v访问不存在的地
+                                                     址空间                                                                 */
+      __IM  uint32_t RCODE_CRC  : 1;            /*!< [6..6] 当这1bit置1,代表RV代码读取CRC校验错误                 */
+      __IM  uint32_t MPU_ROM    : 1;            /*!< [7..7] 当这1bit置1,代表rom区域非法访问                         */
+      __IM  uint32_t DMA_MPU    : 1;            /*!< [8..8] 当这1bit置1,代表DMA MPU错误                                 */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t ERR_CLR    : 1;            /*!< [16..16] 写1会清除所有的CPU ERROR状态                            */
+    } bit;
+  } ERROR_STATUS;
+  __IM  uint32_t  RESERVED[5];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * IRQ_ADDR0 *                                              */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] M0的中断起始地址                                           */
+    } bit;
+  } IRQ_ADDR0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * CURR_CLK *                                               */
+
+    struct {
+      __IOM uint32_t MS_CLK     : 20;           /*!< [19..0] DELAY_MS所需时钟(单位CLK)                                   */
+      __IOM uint32_t US_CLK     : 12;           /*!< [31..20] DELAY_US所需时钟(单位CLK)                                  */
+    } bit;
+  } CURR_CLK;
+  __IM  uint32_t  RESERVED1[54];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000100) * RV_CTRL *                                                */
+
+    struct {
+      __IOM uint32_t CLK_EN     : 4;            /*!< [3..0] RV 时钟使能
+                                                     0x0a: 使能 risc-v clock
+                                                     others: 失能 risc-v clock                                               */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t RESET      : 4;            /*!< [11..8] RV复位使能
+                                                     0x0a: enable risc-v
+                                                     others: reset riscv                                                       */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t FS_EN      : 4;            /*!< [19..16] RV独立睡眠配置
+                                                     0xa: M0和RV独立睡眠
+                                                     others: M0睡眠会强制RV一起睡眠                                   */
+      __IOM uint32_t FS_LOCK    : 1;            /*!< [20..20] RV独立睡眠配置锁定
+                                                     1: 锁定 FS_LOCK和FS_EN                                                 */
+      __IM  uint32_t            : 3;
+      __IM  uint32_t RST_STATUS : 1;            /*!< [24..24] RV复位状态
+                                                     1:复位
+                                                     0:没有复位                                                            */
+      __IM  uint32_t SLP_STATUS : 1;            /*!< [25..25] RV睡眠状态
+                                                     1:睡眠
+                                                     0:没有睡眠                                                            */
+    } bit;
+  } RV_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000104) * RV_IRQ *                                                 */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] rv_to_m0中断使能                                               */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t IRQ        : 1;            /*!< [8..8] rv_to_m0中断状态位,使能之前必须先清除一
+                                                     下该标志位,否则上次中断状态会直接触发中断             */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t TRIG       : 1;            /*!< [16..16] 写‘1’会触发m0_to_rv中断,中断pend
+                                                     ing寄存器和wakeup enable配置在riscv
+                                                     寄存器中
+                                                     必须写0清除,否则会导致一直触发                              */
+    } bit;
+  } RV_IRQ;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000108) * SW_IRQ *                                                 */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] M0软件中断使能                                               */
+      __IOM uint32_t TRIG       : 1;            /*!< [1..1] 软件写1会触发软件中断                                    */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t CODE       : 8;            /*!< [15..8] 用户软件自己可以操作的8BIT                             */
+    } bit;
+  } SW_IRQ;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000010C) * BIN_IRQ *                                                */
+
+    struct {
+      __IOM uint32_t QR_IE      : 1;            /*!< [0..0] 二维码二值化中断使能                                     */
+      __IOM uint32_t ONED_IE    : 1;            /*!< [1..1] 一维码二值化中断使能                                     */
+    } bit;
+  } BIN_IRQ;
+} MMCU_Type;                                    /*!< Size = 272 (0x110)                                                        */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MMPU                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MMPU (MMPU)
+  */
+
+typedef struct {                                /*!< (@ 0x000D8080) MMPU Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL_ID *                                                */
+
+    struct {
+      __IM  uint32_t VAL        : 32;           /*!< [31..0] MPU ID                                                            */
+    } bit;
+  } CTRL_ID;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t VAL        : 1;            /*!< [0..0] MPU使能                                                          */
+    } bit;
+  } CTRL;
+  __IM  uint32_t  RESERVED;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * CTRL_FSR *                                               */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [4:2] fault region
+                                                     [1:0] fault status                                                        */
+    } bit;
+  } CTRL_FSR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * CTRL_FAR *                                               */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] fault address                                                     */
+    } bit;
+  } CTRL_FAR;
+
+  union {
+    __IOM uint16_t reg;                         /*!< (@ 0x00000014) * PROTECTION *                                             */
+
+    struct {
+      __IOM uint16_t VAL        : 16;           /*!< [15..0] protection15：0
+                                                     00：no access
+                                                     01：private only
+                                                     10：private + user read only
+                                                     11：Full Access                                                          */
+    } bit;
+  } PROTECTION;
+  __IM  uint16_t  RESERVED1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * USER_START *                                             */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 用户程序起始地址                                          */
+    } bit;
+  } USER_START;
+  __IM  uint32_t  RESERVED2[9];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) * REGION_BASE0 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000044) * REGION_BASE1 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) * REGION_BASE2 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) * REGION_BASE3 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000050) * REGION_BASE4 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE4;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000054) * REGION_BASE5 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE5;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000058) * REGION_BASE6 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE6;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) * REGION_BASE7 *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [0]regionx_enable [20:6]
+                                                     BASEx_REG                                                                 */
+    } bit;
+  } REGION_BASE7;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000060) * REGION_LIMIT0 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT0_REG                                                 */
+    } bit;
+  } REGION_LIMIT0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000064) * REGION_LIMIT1 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT1_REG                                                 */
+    } bit;
+  } REGION_LIMIT1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000068) * REGION_LIMIT2 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT2_REG                                                 */
+    } bit;
+  } REGION_LIMIT2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000006C) * REGION_LIMIT3 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT3_REG                                                 */
+    } bit;
+  } REGION_LIMIT3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000070) * REGION_LIMIT4 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT4_REG                                                 */
+    } bit;
+  } REGION_LIMIT4;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000074) * REGION_LIMIT5 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT5_REG                                                 */
+    } bit;
+  } REGION_LIMIT5;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000078) * REGION_LIMIT6 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT6_REG                                                 */
+    } bit;
+  } REGION_LIMIT6;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000007C) * REGION_LIMIT7 *                                          */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] [20:6] LIMIT7_REG                                                 */
+    } bit;
+  } REGION_LIMIT7;
+} MMPU_Type;                                    /*!< Size = 128 (0x80)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           DCMI                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 DCMI (DCMI)
+  */
+
+typedef struct {                                /*!< (@ 0x000D8200) DCMI Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) DCMI_CR Control Register                                   */
+
+    struct {
+      __IOM uint32_t CAPTURE    : 1;            /*!< [0..0] CAPTURE enable                                                     */
+      __IOM uint32_t CM         : 1;            /*!< [1..1] CAPTURE_MODE                                                       */
+      __IOM uint32_t CROP       : 1;            /*!< [2..2] crop feature                                                       */
+      __IOM uint32_t JPEG       : 1;            /*!< [3..3] JPEG format                                                        */
+      __IOM uint32_t ESS        : 1;            /*!< [4..4] Embedded synchronization select                                    */
+      __IOM uint32_t PCKPOL     : 1;            /*!< [5..5] Pixel clock sampling along selection                               */
+      __IOM uint32_t HSPOL      : 1;            /*!< [6..6] Horizontal synchronization polarity                                */
+      __IOM uint32_t VSPOL      : 1;            /*!< [7..7] Vertical synchronization polarity                                  */
+      __IOM uint32_t FCRC       : 2;            /*!< [9..8] Frame capture rate control                                         */
+      __IOM uint32_t EDM        : 3;            /*!< [12..10] Extended data mode control                                       */
+      __IOM uint32_t SPI_MODE   : 1;            /*!< [13..13] SPI ddr mode select                                              */
+      __IOM uint32_t ENABLE     : 1;            /*!< [14..14] DCMI enable                                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BSM        : 2;            /*!< [17..16] Byte select mode                                                 */
+      __IOM uint32_t OEBS       : 1;            /*!< [18..18] Odd enable of byte select                                        */
+      __IOM uint32_t LSM        : 1;            /*!< [19..19] Line select mode                                                 */
+      __IOM uint32_t OELS       : 1;            /*!< [20..20] Odd enable of line select                                        */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t IN_WIRE    : 1;            /*!< [24..24] DCMI input data line bit sequence                                */
+      __IOM uint32_t IN_DDR     : 1;            /*!< [25..25] DDR double - edge sequential selection                           */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t DATA_LSB   : 1;            /*!< [27..27] data mode select                                                 */
+      __IOM uint32_t BIT_LSB    : 1;            /*!< [28..28] BIT mode select                                                  */
+    } bit;
+  } DCMI_CR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) DCMI_SR Control Register                                   */
+
+    struct {
+      __IM  uint32_t HSYNC      : 1;            /*!< [0..0] DCMI_HSYNC,pin status                                              */
+      __IM  uint32_t VSYNC      : 1;            /*!< [1..1] DCMI_VSYNC,pin status                                              */
+      __IM  uint32_t            : 6;
+      __IM  uint32_t AFIFO_STU  : 8;            /*!< [15..8] afifo status                                                      */
+      __IM  uint32_t CURR_ST    : 4;            /*!< [19..16] curr st                                                          */
+      __IM  uint32_t            : 4;
+      __IM  uint32_t BLOCK_EN   : 1;            /*!< [24..24] block enable                                                     */
+      __IM  uint32_t CAPTURE_EN : 1;            /*!< [25..25] capture enable                                                   */
+      __IM  uint32_t SNAPSHOT_MODE : 1;         /*!< [26..26] snapshot mode                                                    */
+    } bit;
+  } DCMI_SR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) DCMI_RIS Control Register                                  */
+
+    struct {
+      __IOM uint32_t FRAME      : 1;            /*!< [0..0] interrupt status                                                   */
+      __IOM uint32_t ERR        : 1;            /*!< [1..1] interrupt status                                                   */
+      __IOM uint32_t VSYNC      : 1;            /*!< [2..2] interrupt status                                                   */
+      __IOM uint32_t LINE       : 1;            /*!< [3..3] interrupt status                                                   */
+      __IOM uint32_t DMA0_LINES : 1;            /*!< [4..4] interrupt status                                                   */
+      __IOM uint32_t DMA0_OVFL  : 1;            /*!< [5..5] interrupt status                                                   */
+      __IOM uint32_t DMA0_FRAEND : 1;           /*!< [6..6] interrupt status                                                   */
+      __IOM uint32_t DMA1_LINES : 1;            /*!< [7..7] interrupt status                                                   */
+      __IOM uint32_t DMA1_OVFL  : 1;            /*!< [8..8] interrupt status                                                   */
+      __IOM uint32_t DMA1_FRAEND : 1;           /*!< [9..9] interrupt status                                                   */
+      __IOM uint32_t DMA2_LINES : 1;            /*!< [10..10] interrupt status                                                 */
+      __IOM uint32_t DMA2_OVFL  : 1;            /*!< [11..11] interrupt status                                                 */
+      __IOM uint32_t DMA2_FRAEND : 1;           /*!< [12..12] interrupt status                                                 */
+      __IM  uint32_t            : 11;
+      __IM  uint32_t DMA0_HALF  : 1;            /*!< [24..24] buffer status                                                    */
+      __IM  uint32_t DMA1_HALF  : 1;            /*!< [25..25] buffer status                                                    */
+      __IM  uint32_t DMA2_HALF  : 1;            /*!< [26..26] buffer status                                                    */
+    } bit;
+  } RIS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) DCMI_IER Control Register                                  */
+
+    struct {
+      __IOM uint32_t FRAME      : 1;            /*!< [0..0] capture complete interrupt enable                                  */
+      __IOM uint32_t ERR        : 1;            /*!< [1..1] synochronization error interrupt enable                            */
+      __IOM uint32_t VSYNC      : 1;            /*!< [2..2] VSYNC interrupt enable                                             */
+      __IOM uint32_t LINE       : 1;            /*!< [3..3] Line interrupt enable                                              */
+      __IOM uint32_t DMA0_LINES : 1;            /*!< [4..4] DAM0 lines interrupt enable                                        */
+      __IOM uint32_t DMA0_OVFL  : 1;            /*!< [5..5] DAM0 OVFL interrupt enable                                         */
+      __IOM uint32_t DMA0_FRAEND : 1;           /*!< [6..6] DAM0 frame end interrupt enable                                    */
+      __IOM uint32_t DMA1_LINES : 1;            /*!< [7..7] DAM1 lines interrupt enable                                        */
+      __IOM uint32_t DMA1_OVFL  : 1;            /*!< [8..8] DAM1 OVFL interrupt enable                                         */
+      __IOM uint32_t DMA1_FRAEND : 1;           /*!< [9..9] DAM1 frame end interrupt enable                                    */
+      __IOM uint32_t DMA2_LINES : 1;            /*!< [10..10] DAM2 lines interrupt enable                                      */
+      __IOM uint32_t DMA2_OVFL  : 1;            /*!< [11..11] DAM2 OVFL interrupt enable                                       */
+      __IOM uint32_t DMA2_FRAEND : 1;           /*!< [12..12] DAM2 frame end interrupt enable                                  */
+    } bit;
+  } IER;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) DCMI_MIR Control Register                                  */
+
+    struct {
+      __IOM uint32_t FRAME      : 1;            /*!< [0..0] capture complete masked interrupt status                           */
+      __IOM uint32_t ERR        : 1;            /*!< [1..1] Synochronization error masked interrupt status                     */
+      __IOM uint32_t VSYNC      : 1;            /*!< [2..2] VSYNC masked interrupt status                                      */
+      __IOM uint32_t LINE       : 1;            /*!< [3..3] Line masked interrupt status                                       */
+      __IOM uint32_t DMA0_LINES : 1;            /*!< [4..4] DMA0 Line masked interrupt status                                  */
+      __IOM uint32_t DMA0_OVFL  : 1;            /*!< [5..5] DMA0 OVFL masked interrupt status                                  */
+      __IOM uint32_t DMA0_FRAEND : 1;           /*!< [6..6] DMA0 frame end masked interrupt status                             */
+      __IOM uint32_t DMA1_LINES : 1;            /*!< [7..7] DMA1 Line masked interrupt status                                  */
+      __IOM uint32_t DMA1_OVFL  : 1;            /*!< [8..8] DMA1 OVFL masked interrupt status                                  */
+      __IOM uint32_t DMA1_FRAEND : 1;           /*!< [9..9] DMA1 frame end masked interrupt status                             */
+      __IOM uint32_t DMA2_LINES : 1;            /*!< [10..10] DMA2 Line masked interrupt status                                */
+      __IOM uint32_t DMA2_OFVL  : 1;            /*!< [11..11] DMA2 OVFL masked interrupt status                                */
+      __IOM uint32_t DMA2_FRAEND : 1;           /*!< [12..12] DMA2 frame end masked interrupt status                           */
+      __IM  uint32_t            : 11;
+      __IM  uint32_t DMA0_HALF  : 1;            /*!< [24..24] buffer interrupt status                                          */
+      __IM  uint32_t DMA1_HALF  : 1;            /*!< [25..25] buffer interrupt status                                          */
+      __IM  uint32_t DMA2_HALF  : 1;            /*!< [26..26] buffer interrupt status                                          */
+    } bit;
+  } MIR;
+  __IM  uint32_t  RESERVED;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) DCMI_ESCR control register                                 */
+
+    struct {
+      __IOM uint32_t FSC        : 8;            /*!< [7..0] frame start delimiter code                                         */
+      __IOM uint32_t LSC        : 8;            /*!< [15..8] line start delimiter code                                         */
+      __IOM uint32_t LEC        : 8;            /*!< [23..16] line end delimiter code                                          */
+      __IOM uint32_t FEC        : 8;            /*!< [31..24] Frame end delimiter code                                         */
+    } bit;
+  } ESCR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) DCMI_ESUR control register                                 */
+
+    struct {
+      __IOM uint32_t FSU        : 8;            /*!< [7..0] frame start delimiter unmask                                       */
+      __IOM uint32_t LSU        : 8;            /*!< [15..8] Line start delimiter unmask                                       */
+      __IOM uint32_t LEU        : 8;            /*!< [23..16] Line end delimiter unmask                                        */
+      __IOM uint32_t FEU        : 8;            /*!< [31..24] frame end delimiter unmask                                       */
+    } bit;
+  } ESUR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) DCMI_CWSTRT control register                               */
+
+    struct {
+      __IOM uint32_t HOFFCNT    : 14;           /*!< [13..0] Horizontal offset count,start index is 0                          */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VST        : 14;           /*!< [29..16] Vertical start line count,start index is 0                       */
+    } bit;
+  } CWSTRT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) DCMI_CWSIZE control register                               */
+
+    struct {
+      __IOM uint32_t CAPCNT     : 14;           /*!< [13..0] capture count                                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VLINE      : 14;           /*!< [29..16] Vertical line count                                              */
+    } bit;
+  } CWSIZE;
+  __IM  uint32_t  RESERVED1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) DCMI_ESHR control register                                 */
+
+    struct {
+      __IM  uint32_t            : 4;
+      __IOM uint32_t AFIFO_WR_FBD : 1;          /*!< [4..4] afifo write allow or prohibit                                      */
+      __IOM uint32_t AFIFO_RST_SW : 1;          /*!< [5..5] afifo rst_sw                                                       */
+      __IOM uint32_t END_AFIFO_RST_EN : 1;      /*!< [6..6] Reset the FIFO at the end of DCMI sampling                         */
+      __IOM uint32_t START_AFIFO_RST_EN : 1;    /*!< [7..7] Reset the FIFO at the start of DCMI sampling                       */
+      __IOM uint32_t ESS_HEADER1 : 8;           /*!< [15..8] Embedded synchronization word byte 1 value                        */
+      __IOM uint32_t ESS_HEADER2 : 8;           /*!< [23..16] Embedded synchronization word byte 2 value                       */
+      __IOM uint32_t ESS_HEADER3 : 8;           /*!< [31..24] Embedded synchronization word byte 3 value                       */
+    } bit;
+  } ESHR;
+  __IM  uint32_t  RESERVED2[3];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) RX_CNT register                                            */
+
+    struct {
+      __IM  uint32_t PIXELS     : 20;           /*!< [19..0] The number of pixels received on the last frame                   */
+      __IM  uint32_t LINES      : 12;           /*!< [31..20] The number of rows                                               */
+    } bit;
+  } RX_CNT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) DCMI_DMA0_CTRL register                                    */
+
+    struct {
+      __IOM uint32_t DMA_EN     : 1;            /*!< [0..0] DMA enable                                                         */
+      __IOM uint32_t CROP_EN    : 1;            /*!< [1..1] CROP enable                                                        */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t PIXEL_SEL_MODE : 2;        /*!< [9..8] column selection mode                                              */
+      __IOM uint32_t PIXEL_SEL_START : 1;       /*!< [10..10] column selection start                                           */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LINE_SEL_MODE_LO : 2;      /*!< [13..12] line selection mode                                              */
+      __IOM uint32_t LINE_SEL_START : 2;        /*!< [15..14] line selection start                                             */
+      __IOM uint32_t FORMAT_TRANSFER : 2;       /*!< [17..16] Format transfer                                                  */
+      __IOM uint32_t YUV_TO_RGB_MODE : 1;       /*!< [18..18] rgb mode selection                                               */
+      __IOM uint32_t RGB565_BYTE_SEQ : 1;       /*!< [19..19] rgb byte seq                                                     */
+      __IOM uint32_t YUV422_Y_LOC : 1;          /*!< [20..20] Y location of YUV422                                             */
+      __IOM uint32_t YUV422_UV_LOC : 1;         /*!< [21..21] UV location of YUV422                                            */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WORD_SEQ_PRE_FT : 1;       /*!< [24..24] WORD_SEQ_PRE_FT                                                  */
+      __IOM uint32_t WORD_SEQ_POST_FT : 1;      /*!< [25..25] WORD_SEQ_POST_FT                                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t LINE_SEL_MODE_HI : 4;      /*!< [31..28] LINE_SEL_MODE_HI                                                 */
+    } bit;
+  } DMA0_CTRL;
+  __IM  uint32_t  RESERVED3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) crop position                                              */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop start position                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSTART     : 14;           /*!< [29..16] vertical crop start position                                     */
+    } bit;
+  } DMA0_CSTART;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) crop SIZE                                                  */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop size                                               */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSIZE      : 14;           /*!< [29..16] vertical crop size                                               */
+    } bit;
+  } DMA0_CSIZE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000050) DMA buffer status                                          */
+
+    struct {
+      __IOM uint32_t LINES_IRQ_EN : 1;          /*!< [0..0] IRQ status                                                         */
+      __IOM uint32_t FRAME_START_REFRESH : 1;   /*!< [1..1] When a frame_start is encountered, update dma_addr to
+                                                     start_addr                                                                */
+      __IOM uint32_t DMA_SADDR_REFRESH_EN : 1;  /*!< [2..2] Enable                                                             */
+      __IM  uint32_t            : 5;
+      __IM  uint32_t BUFFER_EMPTY : 1;          /*!< [8..8] buffer_status                                                      */
+      __IM  uint32_t BUFFER_VALID : 1;          /*!< [9..9] buffer status                                                      */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t LINES_IRQ_SEL : 8;         /*!< [23..16] IRQ selection                                                    */
+    } bit;
+  } DMA0_BUF;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000054) DMA buffer start address                                   */
+
+    struct {
+      __IOM uint32_t SADDR      : 24;           /*!< [23..0] DMA buffer start address                                          */
+    } bit;
+  } DMA0_SADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000058) DMA buffer length                                          */
+
+    struct {
+      __IOM uint32_t LEN        : 24;           /*!< [23..0] DMA buffer length                                                 */
+    } bit;
+  } DMA0_LEN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) DMA current                                                */
+
+    struct {
+      __IM  uint32_t WADDR      : 24;           /*!< [23..0] DMA current write address                                         */
+    } bit;
+  } DMA0_WADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000060) DCMI_DMA0_CTRL register                                    */
+
+    struct {
+      __IOM uint32_t DMA_EN     : 1;            /*!< [0..0] DMA enable                                                         */
+      __IOM uint32_t CROP_EN    : 1;            /*!< [1..1] CROP enable                                                        */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t PIXEL_SEL_MODE : 2;        /*!< [9..8] column selection mode                                              */
+      __IOM uint32_t PIXEL_SEL_START : 1;       /*!< [10..10] column selection start                                           */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LINE_SEL_MODE_LO : 2;      /*!< [13..12] line selection mode                                              */
+      __IOM uint32_t LINE_SEL_START : 2;        /*!< [15..14] line selection start                                             */
+      __IOM uint32_t FORMAT_TRANSFER : 2;       /*!< [17..16] Format transfer                                                  */
+      __IOM uint32_t YUV_TO_RGB_MODE : 1;       /*!< [18..18] rgb mode selection                                               */
+      __IOM uint32_t RGB565_BYTE_SEQ : 1;       /*!< [19..19] rgb byte seq                                                     */
+      __IOM uint32_t YUV422_Y_LOC : 1;          /*!< [20..20] Y location of YUV422                                             */
+      __IOM uint32_t YUV422_UV_LOC : 1;         /*!< [21..21] UV location of YUV422                                            */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WORD_SEQ_PRE_FT : 1;       /*!< [24..24] WORD_SEQ_PRE_FT                                                  */
+      __IOM uint32_t WORD_SEQ_POST_FT : 1;      /*!< [25..25] WORD_SEQ_POST_FT                                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t LINE_SEL_MODE_HI : 4;      /*!< [31..28] LINE_SEL_MODE_HI                                                 */
+    } bit;
+  } DMA1_CTRL;
+  __IM  uint32_t  RESERVED4;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000068) crop position                                              */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop start position                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSTART     : 14;           /*!< [29..16] vertical crop start position                                     */
+    } bit;
+  } DMA1_CSTART;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000006C) crop SIZE                                                  */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop size                                               */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSIZE      : 14;           /*!< [29..16] vertical crop size                                               */
+    } bit;
+  } DMA1_CSIZE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000070) DMA buffer status                                          */
+
+    struct {
+      __IOM uint32_t LINES_IRQ_EN : 1;          /*!< [0..0] IRQ status                                                         */
+      __IOM uint32_t FRAME_START_REFRESH : 1;   /*!< [1..1] When a frame_start is encountered, update dma_addr to
+                                                     start_addr                                                                */
+      __IOM uint32_t DMA_SADDR_REFRESH_EN : 1;  /*!< [2..2] Enable                                                             */
+      __IM  uint32_t            : 5;
+      __IM  uint32_t BUFFER_EMPTY : 1;          /*!< [8..8] buffer_status                                                      */
+      __IM  uint32_t BUFFER_VALID : 1;          /*!< [9..9] buffer status                                                      */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t LINES_IRQ_SEL : 8;         /*!< [23..16] IRQ selection                                                    */
+    } bit;
+  } DMA1_BUF;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000074) DMA buffer start address                                   */
+
+    struct {
+      __IOM uint32_t SADDR      : 24;           /*!< [23..0] DMA buffer start address                                          */
+    } bit;
+  } DMA1_SADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000078) DMA buffer length                                          */
+
+    struct {
+      __IOM uint32_t LEN        : 24;           /*!< [23..0] DMA buffer length                                                 */
+    } bit;
+  } DMA1_LEN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000007C) DMA current                                                */
+
+    struct {
+      __IM  uint32_t WADDR      : 24;           /*!< [23..0] DMA current write address                                         */
+    } bit;
+  } DMA1_WADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000080) DCMI_DMA0_CTRL register                                    */
+
+    struct {
+      __IOM uint32_t DMA_EN     : 1;            /*!< [0..0] DMA enable                                                         */
+      __IOM uint32_t CROP_EN    : 1;            /*!< [1..1] CROP enable                                                        */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t PIXEL_SEL_MODE : 2;        /*!< [9..8] column selection mode                                              */
+      __IOM uint32_t PIXEL_SEL_START : 1;       /*!< [10..10] column selection start                                           */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LINE_SEL_MODE_LO : 2;      /*!< [13..12] line selection mode                                              */
+      __IOM uint32_t LINE_SEL_START : 2;        /*!< [15..14] line selection start                                             */
+      __IOM uint32_t FORMAT_TRANSFER : 2;       /*!< [17..16] Format transfer                                                  */
+      __IOM uint32_t YUV_TO_RGB_MODE : 1;       /*!< [18..18] rgb mode selection                                               */
+      __IOM uint32_t RGB565_BYTE_SEQ : 1;       /*!< [19..19] rgb byte seq                                                     */
+      __IOM uint32_t YUV422_Y_LOC : 1;          /*!< [20..20] Y location of YUV422                                             */
+      __IOM uint32_t YUV422_UV_LOC : 1;         /*!< [21..21] UV location of YUV422                                            */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WORD_SEQ_PRE_FT : 1;       /*!< [24..24] WORD_SEQ_PRE_FT                                                  */
+      __IOM uint32_t WORD_SEQ_POST_FT : 1;      /*!< [25..25] WORD_SEQ_POST_FT                                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t LINE_SEL_MODE_HI : 4;      /*!< [31..28] LINE_SEL_MODE_HI                                                 */
+    } bit;
+  } DMA2_CTRL;
+  __IM  uint32_t  RESERVED5;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000088) crop position                                              */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop start position                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSTART     : 14;           /*!< [29..16] vertical crop start position                                     */
+    } bit;
+  } DMA2_CSTART;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000008C) crop SIZE                                                  */
+
+    struct {
+      __IOM uint32_t HSIZE      : 14;           /*!< [13..0] horizonal crop size                                               */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VSIZE      : 14;           /*!< [29..16] vertical crop size                                               */
+    } bit;
+  } DMA2_CSIZE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000090) DMA buffer status                                          */
+
+    struct {
+      __IOM uint32_t LINES_IRQ_EN : 1;          /*!< [0..0] IRQ status                                                         */
+      __IOM uint32_t FRAME_START_REFRESH : 1;   /*!< [1..1] When a frame_start is encountered, update dma_addr to
+                                                     start_addr                                                                */
+      __IOM uint32_t DMA_SADDR_REFRESH_EN : 1;  /*!< [2..2] Enable                                                             */
+      __IM  uint32_t            : 5;
+      __IM  uint32_t BUFFER_EMPTY : 1;          /*!< [8..8] buffer_status                                                      */
+      __IM  uint32_t BUFFER_VALID : 1;          /*!< [9..9] buffer status                                                      */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t LINES_IRQ_SEL : 8;         /*!< [23..16] IRQ selection                                                    */
+    } bit;
+  } DMA2_BUF;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000094) DMA buffer start address                                   */
+
+    struct {
+      __IOM uint32_t SADDR      : 24;           /*!< [23..0] DMA buffer start address                                          */
+    } bit;
+  } DMA2_SADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000098) DMA buffer length                                          */
+
+    struct {
+      __IOM uint32_t LEN        : 24;           /*!< [23..0] DMA buffer length                                                 */
+    } bit;
+  } DMA2_LEN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000009C) DMA current                                                */
+
+    struct {
+      __IM  uint32_t WADDR      : 24;           /*!< [23..0] DMA current write address                                         */
+    } bit;
+  } DMA2_WADDR;
+} MDCMI_Type;                                    /*!< Size = 160 (0xa0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           MHSPI                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MHSPI (MHSPI)
+  */
+
+typedef struct {                                /*!< (@ 0x000D8400) MHSPI Structure                                            */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] 接收相位调整使能开关
+                                                     0：失能HSPI
+                                                     1：使能HSPI                                                            */
+      __IOM uint32_t START_EN   : 1;            /*!< [1..1] DCMI多行中断启动spi使能
+                                                     0: 禁止硬件启动spi
+                                                     1: 允许硬件启动spi                                                  */
+      __IOM uint32_t START_SEL  : 1;            /*!< [2..2] DCMI多行中断选择
+                                                     0: DCMI DMA0
+                                                     1: DCMI DMA1                                                              */
+      __IOM uint32_t START      : 1;            /*!< [3..3] HSPI启动位，自动开启DMA_START
+                                                     0：无动作
+                                                     1：硬件启动一次HSPI收发                                          */
+      __IOM uint32_t CPOL       : 1;            /*!< [4..4] 时钟极性位
+                                                     0：失能相位调整
+                                                     1：使能相位调整                                                    */
+      __IOM uint32_t CPHA       : 1;            /*!< [5..5] 时钟相位
+                                                     0：空闲状态时，SCK保持低电平；
+                                                     1：空闲状态时，SCK保持高电平；                               */
+      __IOM uint32_t RTX_SEQ    : 1;            /*!< [6..6] 收发序列控制位
+                                                     0：收发同时进行，长度为tx_len;
+                                                     1：先进行tx_len次发送, 再进行rx_len次接收
+                                                     （rx_len为0时跳过接收）                                           */
+      __IOM uint32_t RXD_EN     : 1;            /*!< [7..7] 接收相位调整使能开关
+                                                     0：失能相位调整;
+                                                     1：使能相位调整。                                                 */
+      __IOM uint32_t NCS_DLY    : 3;            /*!< [10..8] NCS提前拉低和滞后拉高的延时位
+                                                     0-7：spi_clk*(ncs_dly+1)。                                              */
+      __IOM uint32_t FIFO_CTRL  : 1;            /*!< [11..11] FIFO软件控制权限使能位
+                                                     0: 软件无法操作FIFO,仅运行DMA自动操作
+                                                     1: 软件可以操作FIFO,不使用DMA时,可以直接使用
+                                                     FIFO进行收发                                                          */
+      __IOM uint32_t TRX_DLY    : 4;            /*!< [15..12] 发送和接收保护间隔位
+                                                     0-7：软件增加Hspi_clk*(trx_dly+1)
+                                                     *4个周期时长。                                                      */
+      __IOM uint32_t CLK_DIV    : 4;            /*!< [19..16] HSPI预分频位
+                                                     0-7：分频值为(clk_div + 1)*2。                                      */
+      __IOM uint32_t RX_PHASE   : 4;            /*!< [23..20] 控制接收相位调整值位,按bit采样位偏移N个cl
+                                                     k个 个数
+                                                     0-7: 采样时间延后(rx_adj_clk + 1)*
+                                                     Hspi_clk不得大于clk_div。
+                                                                                                                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t Y2RGB      : 1;            /*!< [25..25] buff内容转RGB565控制位
+                                                     0：无操作;
+                                                     1：buffer内容为8-bit灰度，实际发送时会自动转
+                                                     换为16-bit RGB565发送。                                              */
+      __IOM uint32_t FIRST_BIT  : 1;            /*!< [26..26] 帧格式位
+                                                     0：先发送MSB;
+                                                     1：先发送LSB
+                                                     注：y_to_rgb_mode为1时,先进行y转rgb操
+                                                     作,再按配置比特顺序进行发送                                  */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * FIFO *                                                   */
+
+    struct {
+      __IOM uint32_t TX_RPTR_INC : 1;           /*!< [0..0] 读取TXFIFO字节位，写1, TX_DATA读
+                                                     地址加1
+                                                     0：无操作；
+                                                     1：读取FIFO中一个字节；                                          */
+      __IM  uint32_t TX_EMPTY   : 1;            /*!< [1..1] TXFIFO状态位
+                                                     0：非空;
+                                                     1：空。                                                                */
+      __IM  uint32_t TX_FULL    : 1;            /*!< [2..2] TXFIFO状态位
+                                                     0：非满;
+                                                     1：满。                                                                */
+      __IOM uint32_t RST        : 1;            /*!< [3..3] 软件复位FIFO
+                                                     0: do not effect
+                                                     1: reset fifo                                                             */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t RX_RPTR_INC : 1;           /*!< [8..8] 读取RXFIFO字节位，写1, RX_DATA读
+                                                     地址加1
+                                                     0：无操作；
+                                                     1：读取FIFO中一个字节                                             */
+      __IM  uint32_t RX_EMPTY   : 1;            /*!< [9..9] RXFIFO状态位
+                                                     0：非空;
+                                                     1：空。                                                                */
+      __IM  uint32_t RX_FULL    : 1;            /*!< [10..10] RXFIFO状态位
+                                                     0：非满;
+                                                     1：满。                                                                */
+      __IOM uint32_t AUTO_RST   : 1;            /*!< [11..11] fifo自动复位
+                                                     0: do not effect
+                                                     1: 每次传输完成后,自动复位一下fifo                           */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t TX_DATA    : 8;            /*!< [23..16] 读取Tx_FIFO数据
+                                                     0-7：写寄存器时，直接将此字节写入Tx_FIFO，
+                                                     读取此寄存器时，表示Tx_FIFO当前值;                           */
+      __IOM uint32_t RX_DATA    : 8;            /*!< [31..24] 读取RX_FIFO数据
+                                                     0-7：写寄存器时，直接将此字节写入Rx_FIFO，
+                                                     读取此寄存器时，表示Rx_FIFO当前值;                           */
+    } bit;
+  } FIFO;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * DMA *                                                    */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] DMA控制位
+                                                     0：失能DMA;
+                                                     1：使能DMA。                                                          */
+      __IOM uint32_t AUTO_START : 1;            /*!< [1..1] DMA自动传输位
+                                                     0：dma不会自动启动，必须手动通过dma_start_
+                                                     man启动;
+                                                     1：spi_start自动启动dma，无须手动启动dma
+                                                     。                                                                       */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t START      : 1;            /*!< [3..3] 启动DMA传输位，同AUTO_START搭配使用
+                                                     0：无操作；
+                                                     1：启动一次dma传输任务                                           */
+      __IOM uint32_t TX_PTR_INC : 1;            /*!< [4..4] TXFIFO状态位
+                                                     0：tx_addr自增
+                                                     1：tx_addr不自增。                                                   */
+      __IOM uint32_t RX_PTR_INC : 1;            /*!< [5..5] RXFIFO状态位
+                                                     0：rx_addr自增;
+                                                     1：rx_addr不自增。                                                   */
+      __IOM uint32_t PINGPANG_EN : 1;           /*!< [6..6] SPI发送数据时,DMA从内存中乒乓buffer
+                                                     取数
+                                                     0: disable pingpang
+                                                     1: enable pingpang,tx_saddr~
+                                                     tx_saddr+tx_len和tx_saddr+tx_
+                                                     len ~ tx_saddr+tx_len*2                                                   */
+    } bit;
+  } DMA;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * IRQ *                                                    */
+
+    struct {
+      __IOM uint32_t DMA_RIS    : 1;            /*!< [0..0] DMA发送完成标志位
+                                                     0: DMA发送未完成；
+                                                     1: DMA完成一次传输发送；                                         */
+      __IOM uint32_t TXFL_RIS   : 1;            /*!< [1..1] 发送FIFO低水准线标志位
+                                                     0: 不低于低水准线；
+                                                     1: 低于低水准线；                                                  */
+      __IOM uint32_t TXFO_RIS   : 1;            /*!< [2..2] 发送FIFO溢出标志位
+                                                     0: 发送FIFO未溢出设定字节个数;
+                                                     1: 发送FIFO溢出设定字节个数。                                  */
+      __IOM uint32_t RXFH_RIS   : 1;            /*!< [3..3] 接收FIFO高水准线标志位
+                                                     0: 不高于低水准线;
+                                                     1: 高于水准线。                                                     */
+      __IOM uint32_t RXFO_RIS   : 1;            /*!< [4..4] 接收FIFO溢出标志位
+                                                     0: 接收FIFO未溢出设定字节个数;
+                                                     1: 接收FIFO溢出设定字节个数。                                  */
+      __IOM uint32_t SOQ_RIS    : 1;            /*!< [5..5] HSPI start信号来临时，上次传输还未完成
+                                                     ，
+                                                     此时会错过一个HSPI任务，出现错误。
+                                                     0: 未错过任务；
+                                                     1: 出错，错过一次任务                                            */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t DMA_MIS    : 1;            /*!< [8..8] DMA传输状态位
+                                                     0: DMA发送未完成;
+                                                     1: DMA发送完成。                                                     */
+      __IOM uint32_t TXFL_MIS   : 1;            /*!< [9..9] 发送FIFO低水准线状态位
+                                                     0: 不低于低水准线；
+                                                     1: 低于低水准线。                                                  */
+      __IOM uint32_t TXFO_MIS   : 1;            /*!< [10..10] 发送FIFO溢出状态位
+                                                     0: 发送FIFO未溢出设定字节个数;
+                                                     1: 发送FIFO溢出设定字节个数。                                  */
+      __IOM uint32_t RXFH_MIS   : 1;            /*!< [11..11] 接收FIFO高水准线状态位
+                                                     0: 不高于低水准线;
+                                                     1: 高于水准线。                                                     */
+      __IOM uint32_t RXFO_MIS   : 1;            /*!< [12..12] 接收FIFO溢出状态位
+                                                     0: 接收FIFO未溢出设定字节个数;
+                                                     1: 接收FIFO溢出设定字节个数。                                  */
+      __IOM uint32_t SOQ_MIS    : 1;            /*!< [13..13] 丢失一次HSPI任务状态位
+                                                     0: 未错过任务；
+                                                     1: 出错，错过一次任务。                                         */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t DMA_EN     : 1;            /*!< [16..16] DMA发送完成控制位
+                                                     0: 失能DMA发送;
+                                                     1: 使能DMA发送。                                                     */
+      __IOM uint32_t TXFL_EN    : 1;            /*!< [17..17] 发送FIFO低水准线控制位
+                                                     0: 失能低于低水准线；
+                                                     1: 使能低于低水准线。                                            */
+      __IOM uint32_t TXFO_EN    : 1;            /*!< [18..18] 发送FIFO溢出控制位
+                                                     0: 失能发送FIFO未溢出;
+                                                     1: 使能发送FIFO溢出。                                              */
+      __IOM uint32_t RXFH_EN    : 1;            /*!< [19..19] 接收FIFO高水准线控制位
+                                                     0: 失能高于低水准线;
+                                                     1: 使能高于水准线。                                               */
+      __IOM uint32_t RXFO_EN    : 1;            /*!< [20..20] 接收FIFO溢出控制位
+                                                     0: 失能接收FIFO未溢出;
+                                                     1: 使能接收FIFO溢出;                                                */
+      __IOM uint32_t SOQ_EN     : 1;            /*!< [21..21] 检测START信号丢失使能位
+                                                     0: 失能；
+                                                     1: 使能。                                                              */
+    } bit;
+  } IRQ;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * DMA_TX_SADDR *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 20;           /*!< [19..0] 存放发送数据起始地址，必须四字节对齐。         */
+    } bit;
+  } DMA_TX_SADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * DMA_RX_SADDR *                                           */
+
+    struct {
+      __IOM uint32_t VAL        : 20;           /*!< [19..0] 接收数据的起始地址，必须四字节对齐               */
+    } bit;
+  } DMA_RX_SADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * DMA_TX_LEN *                                             */
+
+    struct {
+      __IOM uint32_t VAL        : 20;           /*!< [19..0] HSPI发送数据字节长度，配置为0时，表示仅接收    */
+    } bit;
+  } DMA_TX_LEN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) * DMA_RX_LEN *                                             */
+
+    struct {
+      __IOM uint32_t VAL        : 20;           /*!< [19..0] HSPI接收数据字节长度，配置为0时，表示仅发送    */
+    } bit;
+  } DMA_RX_LEN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * DMA_TX_ADDR *                                            */
+
+    struct {
+      __IM  uint32_t VAL        : 20;           /*!< [19..0] 存放当前发送数据的地址。                              */
+    } bit;
+  } DMA_TX_ADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * DMA_RX_ADDR *                                            */
+
+    struct {
+      __IM  uint32_t VAL        : 20;           /*!< [19..0] 存放当前接收数据的地址。                              */
+    } bit;
+  } DMA_RX_ADDR;
+  __IM  uint32_t  RESERVED[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000030) * FIFO_CTRL *                                              */
+
+    struct {
+      __IOM uint32_t RX_WATERLEVEL : 5;         /*!< [4..0] 发送FIFO低水线，
+                                                     发送FIFO数据小于等于此长度，并且水线值不为0时，
+                                                     触发tx_fifo_lo中断。                                                 */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t TX_WATERLEVEL : 5;         /*!< [12..8] 接收FIFO高水线，
+                                                     接收FIFO数据大于等于此长度，并且水线值不为0时，
+                                                     触发rx_fifo_hi中断。                                                 */
+      __IM  uint32_t            : 3;
+      __IM  uint32_t RX_ITEMS   : 5;            /*!< [20..16] 读取Tx_FIFO的数据个数。                                  */
+      __IM  uint32_t            : 3;
+      __IM  uint32_t TX_ITEMS   : 5;            /*!< [28..24] 读取RX_FIFO的数据个数。                                  */
+    } bit;
+  } FIFO_CTRL;
+} MHSPI_Type;                                   /*!< Size = 52 (0x34)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MWDT                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MWDT (MWDT)
+  */
+
+typedef struct {                                /*!< (@ 0x000F0000) MWDT Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CONFIG *                                                 */
+
+    struct {
+      __IOM uint32_t RELOAD     : 5;            /*!< [4..0] WDT计数时长为(2^(wdt_preset-1
+                                                     ))个hclk_div时钟周期                                                 */
+      __IOM uint32_t MODE       : 1;            /*!< [5..5] 0 :复位 1:中断                                                 */
+      __IOM uint32_t EN         : 1;            /*!< [6..6] 0 :WDT功能关闭. 1: WDT 功能打开.                           */
+      __IOM uint32_t CLK_DIV    : 4;            /*!< [10..7] hclk预分频,最大16分频,实际使用的时钟频率
+                                                     是clk/(wdt_clk_div+1)                                                    */
+      __IOM uint32_t OFF        : 1;            /*!< [11..11] 关闭wdt
+                                                     wdt_off_lock为0,并且wdt_on为0时,设
+                                                     置wdt_off为1,再设置wdt_off为0,可关闭w
+                                                     dt                                                                        */
+      __IOM uint32_t OFF_LOCK   : 1;            /*!< [12..12] wdt_off_lock
+                                                     1: wdt_off不起作用
+                                                     0: wdt_off起作用                                                       */
+    } bit;
+  } CONFIG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * CNT *                                                    */
+
+    struct {
+      __IM  uint32_t CNT        : 32;           /*!< [31..0] WDT CNT                                                           */
+    } bit;
+  } CNT;
+
+  union {
+    union {
+      __IOM uint32_t reg;                       /*!< (@ 0x00000008) WDT IRQ STATUS                                             */
+
+      struct {
+        __IM  uint32_t STATE    : 1;            /*!< [0..0] WDT IRQ STATUS                                                     */
+      } bit;
+    } IRQ_STATUS;
+
+    union {
+      __IOM uint32_t reg;                       /*!< (@ 0x00000008) WDT KICK, 必须写 0x5937                                 */
+
+      struct {
+        __OM  uint32_t VALUE    : 32;           /*!< [31..0] WDT KICK,必须写 0x5937                                         */
+      } bit;
+    } KICK;
+  };
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * CLEAR *                                                  */
+
+    struct {
+      __IOM uint32_t CLEAR      : 1;            /*!< [0..0] 向这个寄存器中写1清除WDT 中断                          */
+    } bit;
+  } CLEAR;
+} MWDT_Type;                                    /*!< Size = 16 (0x10)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MSCI0                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MSCI0 (MSCI0)
+  */
+
+typedef struct {                                /*!< (@ 0x000F0400) MSCI0 Structure                                            */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * MODE *                                                   */
+
+    struct {
+      __IOM uint32_t TPS        : 1;            /*!< [0..0] 模式控制位
+                                                     0:T=0
+                                                     1:T=1                                                                     */
+      __IOM uint32_t CODE_DRT   : 1;            /*!< [1..1] 编码选择控制位
+                                                     0:正向编码
+                                                     1:反向编码                                                            */
+      __IOM uint32_t OD         : 1;            /*!< [2..2] OD控制位
+                                                     0: 开漏模式
+                                                     1: 推挽模式(default)                                                  */
+      __IOM uint32_t ETU_NUM    : 2;            /*!< [4..3] ETU个数控制位                                                 */
+      __IOM uint32_t RET_TIME   : 3;            /*!< [7..5] 重传次数                                                       */
+      __IOM uint32_t RET_EN     : 1;            /*!< [8..8] 重传使能位
+                                                     0:失能
+                                                     1:使能                                                                  */
+      __IOM uint32_t EN         : 1;            /*!< [9..9] SCI7816使能
+                                                     0: 失能
+                                                     1: 使能                                                                 */
+      __IOM uint32_t BGT_EN     : 1;            /*!< [10..10] 块保护时间使能
+                                                     0: 失能
+                                                     1: 使能                                                                 */
+      __IOM uint32_t CWT_EN     : 1;            /*!< [11..11] CWT计时器使能
+                                                     0: 失能
+                                                     1: 使能                                                                 */
+      __IOM uint32_t CLK_SEL    : 3;            /*!< [14..12] CLK时钟源控制位(PWM0~PWM7)                                 */
+      __IOM uint32_t MST_EN     : 1;            /*!< [15..15] 主机模式使能
+                                                     0: 失能
+                                                     1: 使能                                                                 */
+      __IOM uint32_t EDC_EN     : 1;            /*!< [16..16] EDC错误检测使能
+                                                     0: 失能
+                                                     1: 使能                                                                 */
+    } bit;
+  } MODE;
+  __IM  uint32_t  RESERVED;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t RFIFO_CL   : 1;            /*!< [0..0] 接收FIFO内容清除控制位
+                                                     0:不起作用
+                                                     1:清除FIFO内数据                                                     */
+      __IOM uint32_t TFIFO_CL   : 1;            /*!< [1..1] 发送FIFO内容清除控制位
+                                                     0:不起作用
+                                                     1:清除FIFO内数据                                                     */
+      __IOM uint32_t TS_TEST    : 1;            /*!< [2..2] 检测TS字节
+                                                     0:不起作用
+                                                     1:接收到数据为03时校验位电平取反                            */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * STATUS *                                                 */
+
+    struct {
+      __IOM uint32_t RFIFO_N    : 1;            /*!< [0..0] 接收缓冲器空状态位
+                                                     0:接收缓冲器空
+                                                     1:接收缓冲器中不空                                                */
+      __IOM uint32_t RFIFO_F    : 1;            /*!< [1..1] 接收缓冲器满状态位
+                                                     0:接收缓冲器不满
+                                                     1:接收缓冲器满                                                      */
+      __IOM uint32_t PRT_CHK    : 1;            /*!< [2..2] 奇偶校验状态位
+                                                     0: 奇偶校验正确
+                                                     1: 奇偶校验错误                                                     */
+      __IOM uint32_t TFIFO_N    : 1;            /*!< [3..3] 发送缓冲器空状态位
+                                                     0: 发送缓冲器空
+                                                     1: 发送缓冲器中不空                                               */
+      __IOM uint32_t TFIFO_F    : 1;            /*!< [4..4] 发送缓冲器满状态位
+                                                     0: 发送缓冲器不满
+                                                     1: 发送缓冲器满                                                     */
+      __IOM uint32_t RET_CHK    : 1;            /*!< [5..5] 重传奇偶校验检测状态位
+                                                     0: 奇偶校验正确
+                                                     1: 奇偶校验错误（在重传功能开启时,只有在发送达到重
+                                                     ��
+                                                     次数时仍有错误发生,此位才被置位）                         */
+      __IOM uint32_t BGT_OT     : 1;            /*!< [6..6] BGT超时状态位
+                                                     0:没超时
+                                                     1:超时 (参考:SCI7816_BGT寄存器说明）                            */
+      __IOM uint32_t CWT_OT     : 1;            /*!< [7..7] CWT超时状态位
+                                                     0:没超时
+                                                     1:超时 (参考:SCI7816_CWT寄存器说明）                            */
+      __IOM uint32_t CHK_BIT    : 1;            /*!< [8..8] 检验位状态
+                                                     0:检验位正确
+                                                     1:检验位错误                                                         */
+    } bit;
+  } STATUS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * INT_IO *                                                 */
+
+    struct {
+      __IOM uint32_t R_FNS      : 1;            /*!< [0..0] 接收完成标志位
+                                                     0:没接收完成
+                                                     1:已接收完成                                                         */
+      __IOM uint32_t T_FNS      : 1;            /*!< [1..1] 发送完成标志位
+                                                     0:没发送完成
+                                                     1:已发送完成                                                         */
+    } bit;
+  } INT_IO;
+  __IM  uint32_t  RESERVED1[3];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * DATA *                                                   */
+
+    struct {
+      __IOM uint32_t VAL        : 8;            /*!< [7..0] 在发送或接收模式下分别充当发送或接收buffer
+                                                     角色                                                                    */
+    } bit;
+  } DATA;
+  __IM  uint32_t  RESERVED2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * ETU *                                                    */
+
+    struct {
+      __IOM uint32_t VAL        : 13;           /*!< [12..0] 配置SCI7816通讯速率                                         */
+    } bit;
+  } ETU;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) * BGT *                                                    */
+
+    struct {
+      __IOM uint32_t VAL        : 6;            /*!< [5..0] 配置SCI7816块反向发送时间间隔,max 6
+                                                     3                                                                         */
+    } bit;
+  } BGT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000030) * CWT *                                                    */
+
+    struct {
+      __IOM uint32_t CWT_TMR    : 24;           /*!< [23..0] 配置SCI7816CWT定时值,发送字节完成,接
+                                                     收起始时启动计时                                                  */
+      __IOM uint32_t CWT_SRT    : 1;            /*!< [24..24] CWT计时开始
+                                                     0:CWT未开始计时
+                                                     1:CWT计时立即生效                                                   */
+    } bit;
+  } CWT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000034) * EDC *                                                    */
+
+    struct {
+      __IOM uint32_t VAL        : 8;            /*!< [7..0] 保存 LRC 计算结果                                            */
+    } bit;
+  } EDC;
+  __IM  uint32_t  RESERVED3[10];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000060) * IS *                                                     */
+
+    struct {
+      __IOM uint32_t R_DONE     : 1;            /*!< [0..0] 成功接收到1个字节                                          */
+      __IOM uint32_t R_ERR      : 1;            /*!< [1..1] 接收错误中断,T0 重试次数超过配置,T1 奇偶
+                                                     校验错误                                                              */
+      __IOM uint32_t CWT_TO     : 1;            /*!< [2..2] 接收 CWT 定时器超时中断                                   */
+      __IOM uint32_t BWT_TO     : 1;            /*!< [3..3] 接收 BWT 定时器超时中断                                   */
+      __IOM uint32_t T_DONE     : 1;            /*!< [4..4] 成功传输 FIFO 中的最后一个字节                         */
+      __IOM uint32_t T_ERR      : 1;            /*!< [5..5] 发送错误,T0 重试次数超过配置,T1 从未触发
+                                                     此错误                                                                 */
+      __IOM uint32_t RFIFO_HA   : 1;            /*!< [6..6] R_ITEMS <= RH_WTL
+                                                     发生中断后,应首先读取rx_fifo至水线以下,或改变水
+                                                     线,才能清除中断
+                                                     RH_WTL为0时,不触发此中断                                          */
+      __IOM uint32_t TFIFO_LA   : 1;            /*!< [7..7] T_ITEMS <= TL_WTL
+                                                     发生中断后,应首先填充T_ITEMS至水线以上,或改变水
+                                                     线,才能清除中断
+                                                     TL_WTL为0时,不触发此中断                                          */
+      __IOM uint32_t RFIFO_OVF  : 1;            /*!< [8..8] 设备接收字节时 接收FIFO 满,RFIFO_O
+                                                     VF 溢出中断                                                           */
+      __IOM uint32_t TFIFO_OVF  : 1;            /*!< [9..9] 主机写入 发送FIFO 时 发送FIFO 满,T
+                                                     FIFO_OVF 溢出中断
+                                                     接收时,主机读 FIFO 下溢可能会导致此中断断言             */
+      __IOM uint32_t SHTCUT     : 1;            /*!< [10..10] tbd                                                              */
+      __IOM uint32_t T_FNS      : 1;            /*!< [11..11] 发送完成                                                     */
+      __IOM uint32_t R_FNS      : 1;            /*!< [12..12] 接收完成                                                     */
+      __IOM uint32_t CWT_FLG    : 1;            /*!< [13..13] cwt标志, 写 '1' 清除 IS 和 IES                             */
+      __IOM uint32_t R_SRT      : 1;            /*!< [14..14] 接收到毛刺信号,会触发此中断,仅rx_en使能时
+                                                     会触发
+                                                     bwt期间,bwt会自动恢复重启,可以触发超时
+                                                     cwt期间,毛刺到来会重置cwt计数器,wt超时时间会变
+                                                     长                                                                       */
+    } bit;
+  } IS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000064) * IE *                                                     */
+
+    struct {
+      __IOM uint32_t R_DONE     : 1;            /*!< [0..0] 使能 R_DONE 中断控制位                                      */
+      __IOM uint32_t R_ERR      : 1;            /*!< [1..1] 使能 R_ERR 中断控制位                                       */
+      __IOM uint32_t CWT_TO     : 1;            /*!< [2..2] 使能 CWT_TO 中断控制位                                      */
+      __IOM uint32_t BWT_TO     : 1;            /*!< [3..3] 使能 BWT_TO 中断控制位                                      */
+      __IOM uint32_t T_DONE     : 1;            /*!< [4..4] 使能 T_DONE 中断控制位                                      */
+      __IOM uint32_t T_ERR      : 1;            /*!< [5..5] 使能 T_ERR 中断控制位                                       */
+      __IOM uint32_t RFIFO_HA   : 1;            /*!< [6..6] 使能 RFIFO_HA 中断控制位                                    */
+      __IOM uint32_t TFIFO_LA   : 1;            /*!< [7..7] 使能 TFIFO_LA 中断控制位                                    */
+      __IOM uint32_t RFIFO_OVF  : 1;            /*!< [8..8] 使能 RFIFO_OVF 中断控制位                                   */
+      __IOM uint32_t TFIFO_OVF  : 1;            /*!< [9..9] 使能 TFIFO_OVF 中断控制位                                   */
+      __IOM uint32_t SHTCUT     : 1;            /*!< [10..10] 使能 SHTCUT 中断控制位                                    */
+      __IOM uint32_t T_FNS      : 1;            /*!< [11..11] 使能 T_FNS 中断控制位                                     */
+      __IOM uint32_t R_FNS      : 1;            /*!< [12..12] 使能 R_FNS 中断控制位                                     */
+      __IOM uint32_t CWT_FLG    : 1;            /*!< [13..13] 使能 CWT_FLG 中断控制位                                   */
+      __IOM uint32_t R_SRT      : 1;            /*!< [14..14] 使能 R_SRT 中断控制位                                     */
+    } bit;
+  } IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000068) * IES *                                                    */
+
+    struct {
+      __IOM uint32_t R_DONE     : 1;            /*!< [0..0] 使能 R_DONE 中断状态控制位                                */
+      __IOM uint32_t R_ERR      : 1;            /*!< [1..1] 使能 R_ERR 中断状态控制位                                 */
+      __IOM uint32_t CWT_TO     : 1;            /*!< [2..2] 使能 CWT_TO 中断状态控制位                                */
+      __IOM uint32_t BWT_TO     : 1;            /*!< [3..3] 使能 BWT_TO 中断状态控制位                                */
+      __IOM uint32_t T_DONE     : 1;            /*!< [4..4] 使能 T_DONE 中断状态控制位                                */
+      __IOM uint32_t T_ERR      : 1;            /*!< [5..5] 使能 T_ERR 中断状态控制位                                 */
+      __IOM uint32_t RFIFO_HA   : 1;            /*!< [6..6] 使能 RFIFO_HA 中断状态控制位                              */
+      __IOM uint32_t TFIFO_LA   : 1;            /*!< [7..7] 使能 TFIFO_LA 中断状态控制位                              */
+      __IOM uint32_t RFIFO_OVF  : 1;            /*!< [8..8] 使能 RFIFO_OVF 中断状态控制位                             */
+      __IOM uint32_t TFIFO_OVF  : 1;            /*!< [9..9] 使能 TFIFO_OVF 中断状态控制位                             */
+      __IOM uint32_t SHTCUT     : 1;            /*!< [10..10] 使能 SHTCUT 中断状态控制位                              */
+      __IOM uint32_t T_FNS      : 1;            /*!< [11..11] 使能 T_FNS 中断状态控制位                               */
+      __IOM uint32_t R_FNS      : 1;            /*!< [12..12] 使能 R_FNS 中断状态控制位                               */
+      __IOM uint32_t CWT_FLG    : 1;            /*!< [13..13] 使能 CWT_FLG 中断状态控制位                             */
+      __IOM uint32_t R_SRT      : 1;            /*!< [14..14] 使能 R_SRT 中断状态控制位                               */
+    } bit;
+  } IES;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000006C) * CTRL2 *                                                  */
+
+    struct {
+      __IOM uint32_t TX_EN      : 1;            /*!< [0..0] 使能发送数据控制位
+                                                     0:失能
+                                                     1:使能                                                                  */
+      __IOM uint32_t RX_EN      : 1;            /*!< [1..1] 使能接收数据控制位
+                                                     0:失能
+                                                     1:使能                                                                  */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t FST_EN     : 1;            /*!< [8..8] 使能发送第一个字节控制位
+                                                     0:第一个字节传输失能
+                                                     1:第一个字节发送开始或当 BGT_FLG 置'1'                        */
+      __OM  uint32_t FST_RF     : 1;            /*!< [9..9] 写1将刷新 FST_FLG 置1                                         */
+      __IOM uint32_t FST_W      : 1;            /*!< [10..10] 发送第一个字节等待块保护时间
+                                                     0:第一个字节发送不考虑 BGT_FLG
+                                                     1:当发送第一个字节时,等待 BGT_FLG 置”1”                   */
+      __IM  uint32_t FST_FLG    : 1;            /*!< [11..11] 发送第一个字节标志位
+                                                     0:不传输第一个字节
+                                                     1:下面的字节是要传送的第一个字节                           */
+      __IOM uint32_t BGTS_SL    : 1;            /*!< [12..12] BGT开始选择控制位
+                                                     0:接收开始
+                                                     1:接收启动位,更可重新定位                                      */
+      __IOM uint32_t CWTS_SL    : 1;            /*!< [13..13] CWT开始选择控制位
+                                                     0:接收缓冲器等待或者发送字节结束
+                                                     1:接收起始位或发送起始位                                       */
+      __IOM uint32_t CWTC_DSA   : 1;            /*!< [14..14] 清除 CWT 计数器控制位
+                                                     0:使用发送开始位或接收开始位清除 CWT 计数器
+                                                     1:不清除 CWT 计数器                                                 */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t CWT_EN     : 1;            /*!< [16..16] 接收 CWT 定时器使能控制位
+                                                     0:接收 CWT 定时器失能
+                                                     1:接收 CWT 定时器使能                                              */
+      __OM  uint32_t CWT_ST     : 1;            /*!< [17..17] 写”1”接收 CWT 停止,始终读回”0”                  */
+      __OM  uint32_t CWT_SRT    : 1;            /*!< [18..18] 写”1”接收 CWT 开始,始终读回”0”                  */
+      __OM  uint32_t CWT_RLD    : 1;            /*!< [19..19] 写”1”接收 CWT 重新装载,始终读回”0”            */
+      __IOM uint32_t CWTA_SRT   : 1;            /*!< [20..20] 接收 CWT 自动启动使能控制位
+                                                     0:接收 CWT 定时器不会自动启动
+                                                     1:当发送”CWTA_SRT”位时,接收 CWT 定时器
+                                                     将自动启动                                                           */
+      __IM  uint32_t CWT_RNG    : 1;            /*!< [21..21] 接收 CWT 定时器运行状态                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t BWT_EN     : 1;            /*!< [24..24] 接收 BWT 使能控制位
+                                                     0:接收 BWT 定时器失能
+                                                     1:接收 BWT 定时器使能                                              */
+      __OM  uint32_t BWT_ST     : 1;            /*!< [25..25] 写”1”接收 BWT 停止,始终读回”0”                  */
+      __OM  uint32_t BWT_SRT    : 1;            /*!< [26..26] 写”1”接收 BWT 开始,始终读回”0”                  */
+      __OM  uint32_t BWT_RLD    : 1;            /*!< [27..27] 写”1”接收 BWT 重新装载,始终读回”0”            */
+      __IOM uint32_t BWTA_SRT   : 1;            /*!< [28..28] 接收 BWT 自动启动使能控制位
+                                                     0:接收 BWT 定时器不会自动启动
+                                                     1:当发送”BWTA_SRT”位时,接收 BWT 定时器
+                                                     将自动启动                                                           */
+      __IOM uint32_t BWTA_ST    : 1;            /*!< [29..29] 接收 BWT 自动停止使能控制位
+                                                     0:接收 BWT 定时器不会自动停止
+                                                     1:当发送”BWTA_ST”位时,接收 BWT 定时器将
+                                                     自动停止                                                              */
+      __IM  uint32_t BWT_RNG    : 1;            /*!< [30..30] 接收 BWT 定时器运行状态                                 */
+    } bit;
+  } CTRL2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000070) * CWT_TO *                                                 */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 CWT 超时预设值                                        */
+    } bit;
+  } CWT_TO;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000074) * CWT_RLD *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 CWT 重新加载值                                        */
+    } bit;
+  } CWT_RLD;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000078) * CWT_CNT *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 CWT 当前计数值                                        */
+    } bit;
+  } CWT_CNT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000007C) * STATUS_FSM *                                             */
+
+    struct {
+      __IM  uint32_t TX_IDLE    : 1;            /*!< [0..0] TX_IDLE_STATE                                                      */
+      __IM  uint32_t TX_STR     : 1;            /*!< [1..1] TX_START_STATE                                                     */
+      __IM  uint32_t TX_LD_DTA  : 1;            /*!< [2..2] TX_LOAD_DATA_STATE                                                 */
+      __IM  uint32_t TX_DTA     : 1;            /*!< [3..3] TX_DATA_STATE                                                      */
+      __IM  uint32_t TX_PRT     : 1;            /*!< [4..4] TX_PARITY_STATE                                                    */
+      __IM  uint32_t TX_INT_GAD : 1;            /*!< [5..5] TX_INT_GUARD_STATE                                                 */
+      __IM  uint32_t TX_ERR_DET : 1;            /*!< [6..6] TX_ERROR_DETECT_STATE                                              */
+      __IM  uint32_t TX_ERR_GAD : 1;            /*!< [7..7] TX_ERROR_GUARD_STATE                                               */
+      __IM  uint32_t TX_GAD     : 1;            /*!< [8..8] TX_GUARD_STATE                                                     */
+      __IM  uint32_t            : 7;
+      __IM  uint32_t RX_IDLE    : 1;            /*!< [16..16] RX_IDLE_STATE                                                    */
+      __IM  uint32_t RX_RDY     : 1;            /*!< [17..17] RX_READY_STATE                                                   */
+      __IM  uint32_t RX_STR     : 1;            /*!< [18..18] RX_START_STATE                                                   */
+      __IM  uint32_t RX_DTA     : 1;            /*!< [19..19] RX_DATA_STATE                                                    */
+      __IM  uint32_t RX_PRT     : 1;            /*!< [20..20] RX_PARITY_STATE                                                  */
+      __IM  uint32_t RX_PRT_CHK : 1;            /*!< [21..21] RX_PARITY_CHECK_STATE                                            */
+      __IM  uint32_t RX_ERR     : 1;            /*!< [22..22] RX_ERROR_STATE                                                   */
+      __IM  uint32_t RX_GARD    : 1;            /*!< [23..23] RX_GUARD_STATE                                                   */
+      __IM  uint32_t RX_ERR_GAD : 1;            /*!< [24..24] RX_ERROR_GUARD_STATE                                             */
+      __IM  uint32_t RX_WAIT    : 1;            /*!< [25..25] RX_WAIT_STATE                                                    */
+    } bit;
+  } STATUS_FSM;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000080) * BWT_TO *                                                 */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 BWT 超时预设值                                        */
+    } bit;
+  } BWT_TO;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000084) * BWT_RLD *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 BWT 重装载值                                           */
+    } bit;
+  } BWT_RLD;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000088) * BWT_CNT *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 24;           /*!< [23..0] 接收 BWT 当前计数值                                        */
+    } bit;
+  } BWT_CNT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000008C) * FIFO_CTRL *                                              */
+
+    struct {
+      __IOM uint32_t TL_WTL     : 4;            /*!< [3..0] T_ITEMS <= TL_WTL 时,触发 T
+                                                     FIFO_LA 中断
+                                                     注意：TL_WTL 为0时,不触发中断                                   */
+      __IOM uint32_t RH_WTL     : 4;            /*!< [7..4] FIFO_ITEMS >= RH_WTL 时,触
+                                                     发 RFIFO_HA 中断
+                                                     注意:RH_WTL 为0时,不触发中断                                     */
+      __IM  uint32_t T_ITEMS    : 4;            /*!< [11..8] 发送 FIFO 字节数                                             */
+      __IM  uint32_t R_ITEMS    : 4;            /*!< [15..12] 接收 FIFO 字节数                                            */
+    } bit;
+  } FIFO_CTRL;
+} MSCI0_Type;                                   /*!< Size = 144 (0x90)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MTIM                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 TIMER (MTIM)
+  */
+
+typedef struct {                                /*!< (@ 0x000F0C00) MTIM Structure                                             */
+
+  union {
+    __IOM uint32_t reg[18];                     /*!< (@ 0x00000000) period Register                                            */
+
+    struct {
+      __IOM uint32_t period     : 32;           /*!< [31..0] period                                                            */
+    } bit[18];
+  } PERIOD;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) pwm Control Register(0~7)                                  */
+
+    struct {
+      __IOM uint32_t PWM0EN     : 1;            /*!< [0..0] Enable or disable TIMER                                            */
+      __IOM uint32_t PWM0FIR    : 1;            /*!< [1..1] TIMER initial level                                                */
+      __IOM uint32_t PWM0MD     : 1;            /*!< [2..2] TIMER mode                                                         */
+      __IOM uint32_t PWM0REL    : 1;            /*!< [3..3] TIMER AUTO RELOAD                                                  */
+      __IOM uint32_t PWM1EN     : 1;            /*!< [4..4] Enable or disable TIMER1                                           */
+      __IOM uint32_t PWM1FIR    : 1;            /*!< [5..5] TIMER initial level                                                */
+      __IOM uint32_t PWM1MD     : 1;            /*!< [6..6] TIMER mode                                                         */
+      __IOM uint32_t PWM1REL    : 1;            /*!< [7..7] TIMER AUTO RELOAD                                                  */
+      __IOM uint32_t PWM2EN     : 1;            /*!< [8..8] Enable or disable TIMER2                                           */
+      __IOM uint32_t PWM2FIR    : 1;            /*!< [9..9] TIMER initial level                                                */
+      __IOM uint32_t PWM2MD     : 1;            /*!< [10..10] TIMER mode                                                       */
+      __IOM uint32_t PWM2REL    : 1;            /*!< [11..11] TIMER AUTO RELOAD                                                */
+      __IOM uint32_t PWM3EN     : 1;            /*!< [12..12] Enable or disable TIMER3                                         */
+      __IOM uint32_t PWM3FIR    : 1;            /*!< [13..13] TIMER initial level                                              */
+      __IOM uint32_t PWM3MD     : 1;            /*!< [14..14] TIMER mode                                                       */
+      __IOM uint32_t PWM3REL    : 1;            /*!< [15..15] TIMER AUTO RELOAD                                                */
+      __IOM uint32_t PWM4EN     : 1;            /*!< [16..16] Enable or disable TIMER4                                         */
+      __IOM uint32_t PWM4FIR    : 1;            /*!< [17..17] TIMER initial level                                              */
+      __IOM uint32_t PWM4MD     : 1;            /*!< [18..18] TIMER mode                                                       */
+      __IOM uint32_t PWM4REL    : 1;            /*!< [19..19] TIMER AUTO RELOAD                                                */
+      __IOM uint32_t PWM5EN     : 1;            /*!< [20..20] Enable or disable TIMER5                                         */
+      __IOM uint32_t PWM5FIR    : 1;            /*!< [21..21] TIMER initial level                                              */
+      __IOM uint32_t PW5MD      : 1;            /*!< [22..22] TIMER mode                                                       */
+      __IOM uint32_t PWM5REL    : 1;            /*!< [23..23] TIMER AUTO RELOAD                                                */
+      __IOM uint32_t PWM6EN     : 1;            /*!< [24..24] Enable or disable TIMER6                                         */
+      __IOM uint32_t PWM6FIR    : 1;            /*!< [25..25] TIMER initial level                                              */
+      __IOM uint32_t PWM6MD     : 1;            /*!< [26..26] TIMER mode                                                       */
+      __IOM uint32_t PWM6REL    : 1;            /*!< [27..27] TIMER AUTO RELOAD                                                */
+      __IOM uint32_t PWM7EN     : 1;            /*!< [28..28] Enable or disable TIMER7                                         */
+      __IOM uint32_t PWM7FIR    : 1;            /*!< [29..29] TIMER initial level                                              */
+      __IOM uint32_t PWM7MD     : 1;            /*!< [30..30] TIMER mode                                                       */
+      __IOM uint32_t PWM7REL    : 1;            /*!< [31..31] TIMER AUTO RELOAD                                                */
+    } bit;
+  } CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) pwm Control Register(8)                                    */
+
+    struct {
+      __IOM uint32_t PWM8EN     : 1;            /*!< [0..0] Enable or disable TIMER                                            */
+      __IOM uint32_t PWM8FIR    : 1;            /*!< [1..1] TIMER initial level                                                */
+      __IOM uint32_t PWM8MD     : 1;            /*!< [2..2] TIMER mode                                                         */
+      __IOM uint32_t PWM8REL    : 1;            /*!< [3..3] TIMER AUTO RELOAD                                                  */
+      __IOM uint32_t IRQ_EN     : 9;            /*!< [12..4] The timer crresponds to the interrupt enable control
+                                                     bit                                                                       */
+      __IOM uint32_t IRQ_CLR    : 9;            /*!< [21..13] Clear interrupt control bits                                     */
+    } bit;
+  } CTRL2;
+
+  union {
+    __IM  uint32_t reg[9];                      /*!< (@ 0x00000050) [0..8]                                                     */
+
+    struct {
+      __IM  uint32_t cnt        : 32;           /*!< [31..0] cnt                                                               */
+    } bit[9];
+  } CNT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000074) pwm IRQ status Register                                    */
+
+    struct {
+      __IM  uint32_t PWM_IRQ_PEND : 9;          /*!< [8..0] PWM_IRQ status                                                     */
+    } bit;
+  } IRQ_NUM;
+} MTIM_Type;                                    /*!< Size = 120 (0x78)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MCRC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MCRC (MCRC)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8204) MCRC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * RESULT *                                                 */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 存放CRC运算的初值及结果                                 */
+    } bit;
+  } RESULT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * MASK *                                                   */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 计算掩码,不影响CRC最终运算结果                       */
+    } bit;
+  } MASK;
+  __IM  uint32_t  RESERVED[29];
+
+  union {
+    __IOM uint16_t reg;                         /*!< (@ 0x0000007C) * DATA *                                                   */
+
+    struct {
+      __IOM uint16_t VAL        : 16;           /*!< [15..0] 存放参与CRC运算的数据                                    */
+    } bit;
+  } DATA;
+  __IM  uint16_t  RESERVED1;
+} MCRC_Type;                                    /*!< Size = 128 (0x80)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MRCC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MRCC (MRCC)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8400) MRCC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * HCLK_CTRL *                                              */
+
+    struct {
+      __IM  uint32_t            : 12;
+      __IOM uint32_t USB_SEL    : 2;            /*!< [13..12] USB时钟clk_usb选择。
+                                                     0: rc192m分频后生成的48M时钟
+                                                     1: pll_hsi_48m,切换PLL频率会抖动
+                                                     2: pll_hse_48m,切换PLL频率会抖动                                   */
+      __IOM uint32_t UART_SEL   : 2;            /*!< [15..14] UART时钟clk_uart选择。
+                                                     0: rc192m分频后生成的48M时钟
+                                                     1: pll_hsi_48m,切换PLL频率会抖动
+                                                     2: pll_hse_48m,切换PLL频率会抖动                                   */
+    } bit;
+  } HCLK_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * PCLK_CTRL *                                              */
+
+    struct {
+      __IOM uint32_t SEL        : 2;            /*!< [1..0] PCLK使用的分频值选择
+                                                     0: 1分频
+                                                     1: 2分频
+                                                     2: 4分频
+                                                     3: 8分频                                                                */
+      __IOM uint32_t DIV_EN     : 1;            /*!< [2..2] PCLK分频使能                                                   */
+    } bit;
+  } PCLK_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * RSA_CLK *                                                */
+
+    struct {
+      __IOM uint32_t CLK_CFG    : 4;            /*!< [3..0] 每16个clk_rsa中,前n个可以强制为0,此
+                                                     寄存器用于选择n值,从这里输出的时钟最终给到RSA模块1
+                                                     : 每16个clk_rsa中,前3个周期强制为0
+                                                     2, 4, 5 :每16个clk_rsa中,前2个周期强
+                                                     制为0
+                                                     3 : 每16个clk_rsa中,第一个强制为0
+                                                     6, 7 :clk_rsa输入等于输出
+                                                     Others : 每16个clk_rsa中,前7个周期强
+                                                     制为0                                                                   */
+    } bit;
+  } RSA_CLK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * CLK_EN *                                                 */
+
+    struct {
+      __IOM uint32_t RNG        : 1;            /*!< [0..0] rng数字模块时钟开关                                        */
+      __IOM uint32_t QSPI       : 1;            /*!< [1..1] qspi数字模块时钟开关                                       */
+      __IOM uint32_t SHA        : 1;            /*!< [2..2] SHA数字模块时钟开关                                        */
+      __IOM uint32_t CRC        : 1;            /*!< [3..3] CRC数字模块时钟开关                                        */
+      __IOM uint32_t PWM        : 1;            /*!< [4..4] PWM数字模块时钟开关                                        */
+      __IOM uint32_t WDT        : 1;            /*!< [5..5] WDT数字模块时钟开关                                        */
+      __IOM uint32_t USB        : 1;            /*!< [6..6] USB数字模块时钟开关                                        */
+      __IOM uint32_t SPI        : 1;            /*!< [7..7] SPI数字模块时钟开关                                        */
+      __IOM uint32_t DES        : 1;            /*!< [8..8] DES数字模块时钟开关                                        */
+      __IOM uint32_t RSA        : 1;            /*!< [9..9] RSA数字模块时钟开关                                        */
+      __IOM uint32_t AES        : 1;            /*!< [10..10] AES数字模块时钟开关                                      */
+      __IOM uint32_t GPIO       : 1;            /*!< [11..11] GPIO数字模块时钟开关                                     */
+      __IOM uint32_t SCI0       : 1;            /*!< [12..12] SCI0数字模块时钟开关                                     */
+      __IOM uint32_t SCI1       : 1;            /*!< [13..13] SCI1数字模块时钟开关                                     */
+      __IOM uint32_t SM4        : 1;            /*!< [14..14] SM4数字模块时钟开关                                      */
+      __IOM uint32_t UART       : 1;            /*!< [15..15] UART数字模块时钟开关                                     */
+      __IOM uint32_t MSR        : 1;            /*!< [16..16] 7811数字模块时钟开关                                     */
+      __IOM uint32_t MSR_ADC    : 1;            /*!< [17..17] 7811_ADC数字模块时钟开关                                 */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PSRAM      : 1;            /*!< [19..19] PSRAM数字模块时钟开关                                    */
+      __IOM uint32_t HSPI       : 1;            /*!< [20..20] HSPI数字模块时钟开关                                     */
+      __IOM uint32_t DAC        : 1;            /*!< [21..21] DAC数字模块时钟开关                                      */
+      __IOM uint32_t DCMI       : 1;            /*!< [22..22] DCMI数字模块时钟开关                                     */
+      __IOM uint32_t SD         : 1;            /*!< [23..23] SD数字模块时钟开关                                       */
+      __IOM uint32_t CHGPUMP    : 1;            /*!< [24..24] CHGPUMP数字模块时钟开关                                  */
+      __IOM uint32_t MEMCP      : 1;            /*!< [25..25] MEMCP数字模块时钟开关                                    */
+      __IOM uint32_t MPU_DMA    : 1;            /*!< [26..26] MPU_DMA数字模块时钟开关                                  */
+      __IOM uint32_t RV_SYS     : 1;            /*!< [27..27] RV_SYS数字模块时钟开关                                   */
+      __IOM uint32_t RV_REG     : 1;            /*!< [28..28] RV_REG数字模块时钟开关                                   */
+      __IOM uint32_t RC48M      : 1;            /*!< [29..29] RC48M数字模块时钟开关                                    */
+    } bit;
+  } CLK_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * MCU_CLK *                                                */
+
+    struct {
+      __IOM uint32_t SEL        : 2;            /*!< [1..0] MCU时钟来源选择
+                                                     0: rc192m
+                                                     1: pll_192M
+                                                     2: pll_256M
+                                                     3: pll_48M,                                                               */
+      __IOM uint32_t RC_32K     : 1;            /*!< [2..2] 为1则使能内部RC32K（LSI）为系统时钟,同
+                                                     时屏蔽其他所有的设置                                            */
+      __IOM uint32_t DIV_EN     : 1;            /*!< [3..3] 为1则使能MCU时钟分频                                       */
+      __IOM uint32_t DIV_SEL    : 1;            /*!< [4..4] MCU时钟分频选择
+                                                     0：选择非分频时钟作为 clk_mcu
+                                                     1：选择分频时钟作为clk_mcu
+                                                     注意：当从'1'变为'0'时,应先设置div_sel为'
+                                                     0',延迟至少两个周期,然后清除div_en,不要同时清
+                                                     除这两位。当从'0'变为'1'时,应先设置div_en为
+                                                     '1',延迟至少两个周期,然后设置                                 */
+      __IOM uint32_t RAND_EN    : 1;            /*!< [5..5] 为1则使能MCU时钟随机功能                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t DIV_LO     : 8;            /*!< [15..8] 输入给MCU的时钟的低电平持续时间 = (DIV
+                                                     _LO+1)个clk                                                              */
+      __IOM uint32_t DIV_HI     : 8;            /*!< [23..16] 输入给MCU的时钟的低电平持续时间 = (DIV
+                                                     _HI +1)个clk                                                             */
+      __IOM uint32_t RAND_MASK  : 4;            /*!< [27..24] DIV_HI和DIV_LO会加上(随机数& RA
+                                                     ND_MASK)                                                                  */
+    } bit;
+  } MCU_CLK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * PER1_CLK *                                               */
+
+    struct {
+      __IOM uint32_t AHB_SEL    : 2;            /*!< [1..0] AHB总线时钟来源选择
+                                                     0: CLK_MCU
+                                                     1: RC192M
+                                                     2: pll_192M
+                                                     3: pll_48M                                                                */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t AHB_RAND_EN : 1;           /*!< [3..3] 为1则使能AHB总线时钟随机功能                           */
+      __IOM uint32_t AHB_RAND_MASK : 4;         /*!< [7..4] AHB_DIV_HI和AHB_DIV_LO会加上
+                                                     (随机数&AHB_RAND_MASK)                                                 */
+      __IOM uint32_t AHB_DIV_LO : 4;            /*!< [11..8] 输入给AHB的时钟的低电平持续时间 = (AHB
+                                                     _DIV_LO+1)个clk                                                          */
+      __IOM uint32_t AHB_DIV_HI : 4;            /*!< [15..12] 输入给AHB的时钟的高电平持续时间 = (AHB
+                                                     _DIV_HI +1)个clk                                                         */
+      __IOM uint32_t QSPI_SEL   : 2;            /*!< [17..16] QSPI总线时钟来源选择
+                                                     0: CLK_MCU
+                                                     1: RC192M
+                                                     2: pll_192M
+                                                     3: pll_48M                                                                */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t QSPI_DIV_LO : 4;           /*!< [27..24] 输入给QSPI的时钟的低电平持续时间 = (QS
+                                                     PI_DIV_LO+1)个clk                                                        */
+      __IOM uint32_t QSPI_DIV_HI : 4;           /*!< [31..28] 输入给QSPI的时钟的低电平持续时间 = (QS
+                                                     PI_DIV_HI+1)个clk                                                        */
+    } bit;
+  } PER1_CLK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * PER2_CLK *                                               */
+
+    struct {
+      __IOM uint32_t PSRAM_SEL  : 2;            /*!< [1..0] PSRAM总线时钟来源选择
+                                                     0: CLK_MCU
+                                                     1: RC192M
+                                                     2: pll_192M
+                                                     3: pll_256M                                                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PSRAM_PLL_SEL : 1;         /*!< [3..3] PSRAM时钟来源选择
+                                                     0: pll_hsi
+                                                     1: pll_hse                                                                */
+      __IOM uint32_t PSRAM_DIV_SEL : 1;         /*!< [4..4] PSRAM时钟分频选择
+                                                     0：选择非分频时钟作为 clk_psram
+                                                     1：选择分频时钟作为clk_psram                                     */
+      __IOM uint32_t PSRAM_DIV_EN : 1;          /*!< [5..5] 为1则使能PSRAM时钟分频                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PSRAM_DIV_LO : 4;          /*!< [11..8] 输入给PSRAM的时钟的低电平持续时间 = (P
+                                                     SRAM_DIV_LO+1)个clk                                                      */
+      __IOM uint32_t PSRAM_DIV_HI : 4;          /*!< [15..12] 输入给PSRAM的时钟的高电平持续时间 = (P
+                                                     SRAM_DIV_HI +1)个clk                                                     */
+      __IOM uint32_t HSPI_SEL   : 2;            /*!< [17..16] PSRAM总线时钟来源选择
+                                                     0: CLK_MCU
+                                                     1: RC192M
+                                                     2: pll_192M
+                                                     3: pll_256M                                                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t HSPI_PLL_SEL : 1;          /*!< [19..19] HSPI时钟来源选择
+                                                     0: pll_hsi
+                                                     1: pll_hse                                                                */
+      __IOM uint32_t HSPI_DIV_SEL : 1;          /*!< [20..20] HSPI时钟分频选择
+                                                     0：选择非分频时钟作为 clk_hspi
+                                                     1：选择分频时钟作为 clk_hspi                                     */
+      __IOM uint32_t HSPI_DIV_EN : 1;           /*!< [21..21] 为1则使能HSPI时钟分频                                    */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t HSPI_DIV_LO : 4;           /*!< [27..24] 输入给HSPI的时钟的低电平持续时间 = (HS
+                                                     PI_DIV_LO+1)个clk                                                        */
+      __IOM uint32_t HSPI_DIV_HI : 4;           /*!< [31..28] 输入给HSPI的时钟的高电平持续时间 = (HS
+                                                     PI_DIV_HI +1)个clk                                                       */
+    } bit;
+  } PER2_CLK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) * PER3_CLK *                                               */
+
+    struct {
+      __IOM uint32_t ICE_SEL    : 2;            /*!< [1..0] ICE时钟来源选择
+                                                     0: rc48m
+                                                     1: pll_hsi_48m
+                                                     2: pll_hse_48m                                                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t ICE_EN     : 1;            /*!< [3..3] ICE时钟分频使能来源选择
+                                                     0：选择非分频时钟作为 clk_ice
+                                                     1：选择分频时钟作为clk_ice                                       */
+      __IOM uint32_t ICE_DIV_LO : 2;            /*!< [5..4] 输入给ICE的时钟的低电平持续时间 = (ICE
+                                                     _DIV_LO+1)个clk                                                          */
+      __IOM uint32_t ICE_DIV_HI : 2;            /*!< [7..6] 输入给ICE的时钟的高电平持续时间 = (ICE
+                                                     _DIV_HI +1)个clk                                                         */
+      __IOM uint32_t ADAC_SEL   : 2;            /*!< [9..8] ADAC时钟来源选择
+                                                     0: rc48m
+                                                     1: pll_hsi_48m
+                                                     2: pll_hse_48m                                                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t ADAC_EN    : 1;            /*!< [11..11] ADAC时钟分频使能来源选择
+                                                     0：选择非分频时钟作为 clk_adac
+                                                     1：选择分频时钟作为clk_adac                                      */
+      __IOM uint32_t ADAC_DIV_LO : 2;           /*!< [13..12] 输入给ADAC的时钟的低电平持续时间 = (AD
+                                                     AC_DIV_LO+1)个clk                                                        */
+      __IOM uint32_t ADAC_DIV_HI : 2;           /*!< [15..14] 输入给ADAC的时钟的高电平持续时间 = (AD
+                                                     AC_DIV_HI +1)个clk                                                       */
+      __IOM uint32_t GPIO0_SEL  : 2;            /*!< [17..16] GPIO偶数脚时钟输出,需要把偶数的GPIO配置
+                                                     成 55:GPIO_CLK_OUT
+                                                     0: clk_rc48m
+                                                     1: clk_pll_hsi_48m
+                                                     2: clk_pll_hse_48m                                                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t GPIO0_EN   : 1;            /*!< [19..19] GPIO偶数脚时钟输出使能                                  */
+      __IOM uint32_t GPIO0_DIV_LO : 2;          /*!< [21..20] GPIO偶数脚输出的时钟的低电平持续时间
+                                                     = (
+                                                     GPIO0_DIV_LO+1)个clk                                                     */
+      __IOM uint32_t GPIO0_DIV_HI : 2;          /*!< [23..22] GPIO偶数脚输出的时钟的高电平持续时间
+                                                     = (
+                                                     GPIO0_DIV_HI+1)个clk                                                     */
+      __IOM uint32_t GPIO1_SEL  : 2;            /*!< [25..24] GPIO奇数脚时钟输出,需要把奇数的GPIO配置
+                                                     成 55:GPIO_CLK_OUT
+                                                     0: clk_rc48m
+                                                     1: clk_pll_hsi_48m
+                                                     2: clk_pll_hse_48m                                                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t GPIO1_EN   : 1;            /*!< [27..27] GPIO奇数脚时钟输出使能                                  */
+      __IOM uint32_t GPIO1_DIV_LO : 2;          /*!< [29..28] GPIO奇数脚输出的时钟的低电平持续时间
+                                                     = (
+                                                     GPIO1_DIV_LO+1)个clk                                                     */
+      __IOM uint32_t GPIO1_DIV_HI : 2;          /*!< [31..30] GPIO奇数脚输出的时钟的高电平持续时间
+                                                     = (
+                                                     GPIO1_DIV_HI+1)个clk                                                     */
+    } bit;
+  } PER3_CLK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * CLK_PLL_SEL *                                            */
+
+    struct {
+      __IOM uint32_t PLL_SEL_LOCK : 1;          /*!< [0..0] 为1后锁定AHB,QSPI,MCU,RSA的时钟
+                                                     选择,且无法解锁。                                                 */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t AHB_PLL_SEL : 4;           /*!< [11..8] AHB的时钟来源选择
+                                                     0x5: PLL_HSE
+                                                     Others:PLL_HSI                                                            */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t QSPI_PLL_SEL : 4;          /*!< [19..16] QSPI的时钟来源选择
+                                                     0x5: PLL_HSE
+                                                     Others:PLL_HSI                                                            */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t MCU_PLL_SEL : 4;           /*!< [27..24] MCU的时钟来源选择
+                                                     0x5: PLL_HSE
+                                                     Others:PLL_HSI                                                            */
+      __IOM uint32_t RSA_PLL_SEL : 4;           /*!< [31..28] RSA的时钟来源选择
+                                                     0x5: PLL_HSE
+                                                     Others:PLL_HSI                                                            */
+    } bit;
+  } CLK_PLL_SEL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * OSC32K_CALI *                                            */
+
+    struct {
+      __IM  uint32_t CNT        : 24;           /*!< [23..0] time所表示的时间长度内,48M时钟计数值
+                                                     注意：校准时钟源使用的是clk_gpio1_sel选择的
+                                                     48M时钟                                                                 */
+      __IOM uint32_t START      : 1;            /*!< [24..24] 校准启动信号
+                                                     写'1'后,延迟1us,再写'0',上升沿触发校准开始                 */
+      __IM  uint32_t DONE       : 1;            /*!< [25..25] 校准完成信号
+                                                     校准开始后,此信号会变成'0',校准完成后,此信号会变为
+                                                     '1'                                                                       */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t TIME       : 4;            /*!< [31..28] 校准持续时长,校准时间长度为(2^cali_ti
+                                                     me)个 OSC32K 周期                                                      */
+    } bit;
+  } OSC32K_CALI;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * CLK_RSA *                                                */
+
+    struct {
+      __IOM uint32_t SEL        : 2;            /*!< [1..0] RSA时钟来源选择
+                                                     0: cpu
+                                                     1: rc192m
+                                                     2: pll_out_norm, (192M)
+                                                     3: pll_out_max, (256M)                                                    */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t RAND_EN    : 1;            /*!< [3..3] RSA时钟随机使能
+                                                     0:失能RSA时钟随机
+                                                     1:使能RSA时钟随机                                                   */
+      __IOM uint32_t RAND_MASK  : 4;            /*!< [7..4] DIV_HI和DIV_LO会加上(随机数& RA
+                                                     ND_MASK)                                                                  */
+      __IOM uint32_t DIV_LO     : 4;            /*!< [11..8] 输入给RSA的时钟的低电平持续时间 = (DIV
+                                                     _LO+1)个clk                                                              */
+      __IOM uint32_t DIV_HI     : 4;            /*!< [15..12] 输入给RSA的时钟的高电平持续时间 = (DIV
+                                                     _HI+1)个clk                                                              */
+    } bit;
+  } CLK_RSA;
+} MRCC_Type;                                    /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                         MSYSCTRL                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MSYSCTRL (MSYSCTRL)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8520) MSYSCTRL Structure                                         */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CHGR_EVENT_IRQ *                                         */
+
+    struct {
+      __IOM uint32_t VBAT_LV    : 1;            /*!< [0..0] ad_lpm_chgr_state_vbat_l
+                                                     v                                                                         */
+      __IOM uint32_t RCH_EN     : 1;            /*!< [1..1] ad_lpm_chgr_state_rch_en                                           */
+      __IOM uint32_t IND        : 1;            /*!< [2..2] ad_lpm_chgr_state_ind                                              */
+      __IOM uint32_t ICHG       : 1;            /*!< [3..3] ad_lpm_chgr_state_ichg                                             */
+      __IOM uint32_t RESET      : 1;            /*!< [4..4] ad_lpm_chgr_reset                                                  */
+      __IOM uint32_t UVLO_OK_AON : 1;           /*!< [5..5] ad_lpm_chgr_uvlo_ok_aon                                            */
+      __IOM uint32_t PGOOD      : 1;            /*!< [6..6] ad_lpm_chgr_pgood                                                  */
+      __IOM uint32_t DPPM_OV_CV : 1;            /*!< [7..7] ad_lpm_chgr_dppm_ov_cv                                             */
+      __IOM uint32_t DPPM_OV_CC : 1;            /*!< [8..8] ad_lpm_chgr_dppm_ov_cc                                             */
+      __IOM uint32_t CC_OV_CV   : 1;            /*!< [9..9] ad_lpm_chgr_cc_ov_cv                                               */
+      __IOM uint32_t DET_AON    : 1;            /*!< [10..10] ad_lpm_chgr_in_det_aon                                           */
+      __IOM uint32_t VBAT_OV    : 1;            /*!< [11..11] ad_lpm_vbat_ov_flag                                              */
+      __IOM uint32_t PWK        : 1;            /*!< [12..12] power key irq                                                    */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t IE         : 1;            /*!< [16..16] chgr中断使能总开关                                        */
+      __IOM uint32_t EVENT0_EN  : 1;            /*!< [17..17] chgr_event[9:0]事件检测使能,使能
+                                                     中断前必须先使能这一比特                                      */
+      __IOM uint32_t EVENT1_EN  : 1;            /*!< [18..18] chgr_event[11:10]事件检测使能,
+                                                     使能中断前必须先使能这一比特,power_key一直使能
+                                                     ,无法更改                                                             */
+    } bit;
+  } CHGR_EVENT_IRQ;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * CHGR_EVENT_ICTRL *                                       */
+
+    struct {
+      __IOM uint32_t VBAT_LV_IE : 1;            /*!< [0..0] ad_lpm_chgr_state_vbat_l
+                                                     v 中断使能
+                                                     0: 禁止
+                                                     1: 使能                                                                 */
+      __IM  uint32_t RCH_EN_IE  : 1;            /*!< [1..1] ad_lpm_chgr_state_rch_en                                           */
+      __IOM uint32_t IND_IE     : 1;            /*!< [2..2] ad_lpm_chgr_state_ind                                              */
+      __IM  uint32_t ICHG_IE    : 1;            /*!< [3..3] ad_lpm_chgr_state_ichg                                             */
+      __IOM uint32_t RESET_IE   : 1;            /*!< [4..4] ad_lpm_chgr_reset                                                  */
+      __IM  uint32_t UVLO_OK_AON_IE : 1;        /*!< [5..5] ad_lpm_chgr_uvlo_ok_aon                                            */
+      __IOM uint32_t PGOOD_IE   : 1;            /*!< [6..6] ad_lpm_chgr_pgood                                                  */
+      __IM  uint32_t DPPM_OV_CV_IE : 1;         /*!< [7..7] ad_lpm_chgr_dppm_ov_cv                                             */
+      __IOM uint32_t DPPM_OV_CC_IE : 1;         /*!< [8..8] ad_lpm_chgr_dppm_ov_cc                                             */
+      __IM  uint32_t CC_OV_CV_IE : 1;           /*!< [9..9] ad_lpm_chgr_cc_ov_cv                                               */
+      __IOM uint32_t DET_AON_IE : 1;            /*!< [10..10] ad_lpm_chgr_in_det_aon                                           */
+      __IM  uint32_t VBAT_OV_IE : 1;            /*!< [11..11] ad_lpm_vbat_ov_flag                                              */
+      __IOM uint32_t PWK_IE     : 1;            /*!< [12..12] power_key                                                        */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t VBAT_LV_IT : 1;            /*!< [16..16] ad_lpm_chgr_state_vbat_l
+                                                     v 中断类型
+                                                     0: 低电平
+                                                     1: 高电平                                                              */
+      __IM  uint32_t RCH_EN_IT  : 1;            /*!< [17..17] ad_lpm_chgr_state_rch_en                                         */
+      __IOM uint32_t IND_IT     : 1;            /*!< [18..18] ad_lpm_chgr_state_ind                                            */
+      __IM  uint32_t ICHG_IT    : 1;            /*!< [19..19] ad_lpm_chgr_state_ichg                                           */
+      __IOM uint32_t RESET_IT   : 1;            /*!< [20..20] ad_lpm_chgr_reset                                                */
+      __IM  uint32_t UVLO_OK_AON_IT : 1;        /*!< [21..21] ad_lpm_chgr_uvlo_ok_aon                                          */
+      __IOM uint32_t PGOOD_IT   : 1;            /*!< [22..22] ad_lpm_chgr_pgood                                                */
+      __IM  uint32_t DPPM_OV_CV_IT : 1;         /*!< [23..23] ad_lpm_chgr_dppm_ov_cv                                           */
+      __IOM uint32_t DPPM_OV_CC_IT : 1;         /*!< [24..24] ad_lpm_chgr_dppm_ov_cc                                           */
+      __IM  uint32_t CC_OV_CV_IT : 1;           /*!< [25..25] ad_lpm_chgr_cc_ov_cv                                             */
+      __IOM uint32_t DET_AON_IT : 1;            /*!< [26..26] ad_lpm_chgr_in_det_aon                                           */
+      __IM  uint32_t VBAT_OV_IT : 1;            /*!< [27..27] ad_lpm_vbat_ov_flag                                              */
+      __IOM uint32_t PWK_IT     : 1;            /*!< [28..28] power_key                                                        */
+    } bit;
+  } CHGR_EVENT_ICTRL;
+  __IOM uint32_t  RNG_CTRL;                     /*!< (@ 0x00000008) * RNG_CTRL *                                               */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * RNG_DATA0 *                                              */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 访问此寄存器可以获得随机数                           */
+    } bit;
+  } RNG_DATA0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * RNG_DATA1 *                                              */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 访问此寄存器可以获得随机数                           */
+    } bit;
+  } RNG_DATA1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * RNG_DATA2 *                                              */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 访问此寄存器可以获得随机数                           */
+    } bit;
+  } RNG_DATA2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * RNG_DATA3 *                                              */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 访问此寄存器可以获得随机数                           */
+    } bit;
+  } RNG_DATA3;
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x0000001C) * rom_switch *                                             */
+
+    struct {
+      __IOM uint8_t ROM_SW      : 1;            /*!< [0..0] 写1后置位,写0无效,模块复位后,恢复到0。(产
+                                                     品阶段固定为1)
+                                                     锁定的寄存器：
+                                                     ALARM_EN
+                                                     BTM_EN
+                                                     gpio_ICE
+                                                     gpio_SWDAT
+                                                     sfr_ramkey_sel
+                                                     sfr_medcon_wr
+                                                     QAES regs                                                                 */
+      __IOM uint8_t LOCK_SEC    : 1;            /*!< [1..1] loc_sec                                                            */
+      __IM  uint8_t             : 1;
+      __IOM uint8_t DEBUG_EN    : 1;            /*!< [3..3] 使能DEBUG功能(产品阶段固定为0)
+                                                     0: 失能debug功能;
+                                                     1: 使能debug功能                                                      */
+      __IOM uint8_t LOCK_OTP    : 1;            /*!< [4..4] lock_otp
+                                                     写1锁定寄存器 sfr_otphid_addr / sf
+                                                     r_otpuser_addr                                                            */
+      __IOM uint8_t LOCK_ANA    : 1;            /*!< [5..5] 锁定模拟寄存器                                              */
+      __IOM uint8_t SRAM_NEXE   : 1;            /*!< [6..6] RAM不能跑程序,写0无效(产品阶段固定为1)              */
+      __IOM uint8_t ALARM_EN    : 1;            /*!< [7..7] 报警使能
+                                                     1：使能报警
+                                                     0：失能报警                                                          */
+    } bit;
+  } rom_switch;
+  __IM  uint8_t   RESERVED;
+  __IM  uint16_t  RESERVED1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * LPM_BUSY_CFG *                                           */
+
+    struct {
+      __IOM uint32_t RTC_EN     : 1;            /*!< [0..0] 0: 总线访问RTC时,不等待RTC完成直接返回
+                                                     ,软件查询STATE标志确定是否访问完成
+                                                     1: 总线访问RTC时,等待LPM访问完成才释放总线,软
+                                                     件无须查询STATE标志                                                */
+      __IOM uint32_t LPM_EN     : 1;            /*!< [1..1] 0: 总线访问LPM时,不等待LPM完成直接返回
+                                                     ,软件查询STATE标志确定是否访问完成
+                                                     1: 总线访问LPM时,等待LPM访问完成才释放总线,软
+                                                     件无须查询STATE标志                                                */
+      __IM  uint32_t RTC_STATE  : 1;            /*!< [2..2] 0: rtc access finish
+                                                     1: rtc access ongoing                                                     */
+      __IM  uint32_t LPM_STATE  : 1;            /*!< [3..3] 0: lpm access finish
+                                                     1: lpm access ongoing                                                     */
+      __IM  uint32_t AON_STATE  : 1;            /*!< [4..4] 0: lpm/rtc register acce
+                                                     ss finish
+                                                     1: lpm/rtc register access o
+                                                     ngoing                                                                    */
+    } bit;
+  } LPM_BUSY_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * LPM_RDATA *                                              */
+
+    struct {
+      __IM  uint32_t RDATA      : 32;           /*!< [31..0] lpm access read data                                              */
+    } bit;
+  } LPM_RDATA;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * RTC_RDATA *                                              */
+
+    struct {
+      __IM  uint32_t RDATA      : 32;           /*!< [31..0] rtc access read data                                              */
+    } bit;
+  } RTC_RDATA;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) * AON_RDATA *                                              */
+
+    struct {
+      __IM  uint32_t RDATA      : 32;           /*!< [31..0] lpm/rtc access read data
+                                                     , the last read value of lpm
+                                                     or rtc                                                                    */
+    } bit;
+  } AON_RDATA;
+  __IM  uint32_t  RESERVED2[4];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) * pwk_state *                                              */
+
+    struct {
+      __IM  uint32_t STATE      : 1;            /*!< [0..0] POWER_KEY按键状态                                              */
+    } bit;
+  } pwk_state;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000044) * VIO_IRQ *                                                */
+
+    struct {
+      __IOM uint32_t IE         : 1;            /*!< [0..0] vio 中断总开关                                                */
+      __IOM uint32_t VIO0_EN    : 1;            /*!< [1..1] vio0 pgood 中断开关                                            */
+      __IOM uint32_t VIO1_EN    : 1;            /*!< [2..2] vio1 pgood 中断开关                                            */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t IRQ_STATE  : 1;            /*!< [4..4] vio pgood 中断总状态
+                                                     1: vio0或vio1其中之一电压低于配置值                           */
+      __IOM uint32_t VIO0_IRQ   : 1;            /*!< [5..5] vio pgood irq 状态
+                                                     1: vio 电压低于配置值,vio_pgood由高变为
+                                                     低                                                                       */
+      __IOM uint32_t VIO1_IRQ   : 1;            /*!< [6..6] vio1 pgood irq 状态
+                                                     1: vio1 电压低于配置值,vio1_pgood由高
+                                                     变为低                                                                 */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t VIO0_STATUS : 1;           /*!< [8..8] vio pgood状态
+                                                     1: vio 电源电压正常
+                                                     0: vio电源电压低于设定值                                         */
+      __IM  uint32_t VIO1_STATUS : 1;           /*!< [9..9] vio1 pgood状态
+                                                     1: vio1 电源电压正常
+                                                     0: vio1电源电压低于设定值                                        */
+    } bit;
+  } VIO_IRQ;
+} MSYSCTRL_Type;                                /*!< Size = 72 (0x48)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          MRSTGEN                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MRSTGEN (MRSTGEN)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8574) MRSTGEN Structure                                          */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * RST_EN *                                                 */
+
+    struct {
+      __IOM uint32_t SOFT       : 1;            /*!< [0..0] 1: 使能软件复位功能                                        */
+      __IOM uint32_t WDT        : 1;            /*!< [1..1] 1: 使能看门狗复位功能                                     */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VDDSEC_U   : 1;            /*!< [4..4] 1: 使能安全域电源1.2v输出低压自检复位功能         */
+      __IOM uint32_t VSEC_O     : 1;            /*!< [5..5] 1: 使能锂电池3.3v输出高压自检复位功能               */
+      __IOM uint32_t VSEC_U     : 1;            /*!< [6..6] 1: 使能锂电池3.3v输出低压自检复位功能               */
+      __IOM uint32_t DVDD_U     : 1;            /*!< [7..7] 1: 使能纽扣电池1.2v输出低压自检复位功能            */
+      __IOM uint32_t VBUT_O     : 1;            /*!< [8..8] 1: 使能纽扣电池3.3v输出高压自检复位功能            */
+      __IOM uint32_t VBUT_U     : 1;            /*!< [9..9] 1: 使能纽扣电池3.3v输出低压自检复位功能            */
+      __IOM uint32_t TS_O       : 1;            /*!< [10..10] 1: 使能高温自检复位功能                                */
+      __IOM uint32_t TS_U       : 1;            /*!< [11..11] 1: 使能低温自检复位功能                                */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t GPIO_SEL   : 1;            /*!< [16..16] 复位GPIO选择
+                                                     0: ice_rst/m0_dbg_rst复位外设时,不
+                                                     复位GPIO
+                                                     1: ice_rst/m0_dbg_rst复位外设时,复
+                                                     位GPIO                                                                   */
+    } bit;
+  } RST_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * RST_TYPE *                                               */
+
+    struct {
+      __IOM uint32_t SOFT       : 1;            /*!< [0..0] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t WDT        : 1;            /*!< [1..1] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t VDDSEC_U   : 1;            /*!< [4..4] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t VSEC_O     : 1;            /*!< [5..5] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t VSEC_U     : 1;            /*!< [6..6] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t DVDD_U     : 1;            /*!< [7..7] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t VBUT_O     : 1;            /*!< [8..8] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t VBUT_U     : 1;            /*!< [9..9] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t TS_O       : 1;            /*!< [10..10] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+      __IOM uint32_t TS_U       : 1;            /*!< [11..11] 软件可读写,若对应的复位信号触发,则硬件自动置1
+                                                     ,清0需由软件完成。                                                */
+    } bit;
+  } RST_TYPE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * RESET *                                                  */
+
+    struct {
+      __OM  uint32_t RESET      : 8;            /*!< [7..0] 复位使能:
+                                                     写入 '0x55' ,触发软件复位,sw_rst
+                                                     写入 '0x50' ,触发软件复位,ic_rst
+                                                     写入 '0xAB“ ,触发sci复位,rst_sci
+                                                     写入 '0xAE“ ,触发sci2复位,rst_sci_
+                                                     2
+                                                     写入 '0xC3' ,触发7811复位,rst_7811                                  */
+    } bit;
+  } RESET;
+} MRSTGEN_Type;                                 /*!< Size = 12 (0xc)                                                           */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          MSECURE                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MSECURE (MSECURE)
+  */
+
+typedef struct {                                /*!< (@ 0x000F85C0) MSECURE Structure                                          */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t SEC_EN     : 8;            /*!< [7..0] 1: sensor检测使能。
+                                                     [7]: 低温自检,ad_ts_uth/uthb
+                                                     [6]: 高温自检,ad_ts_oth/othb
+                                                     [5]: 纽扣电池3.3v输出低压自检,ad_vbat_
+                                                     uvh/uvhb
+                                                     [4]: 纽扣电池3.3v输出高压自检,ad_vbat_
+                                                     ovh/ovhb
+                                                     [3]: 纽扣电池1.2v输出低压自检,ad_dvddl
+                                                     pm_uvh/uvhb
+                                                     [2]: 锂电池3.3v输出低压自检,ad_vsec_u
+                                                     v/uvb
+                                                     [1]: 锂电池3.3v输出高压自检,ad_vsec_o
+                                                     v/ovb
+                                                     [0]: 安全域电源1.2v输出低压自检,ad_vdds
+                                                     ec_uv/uvb                                                                 */
+      __IOM uint32_t THRESHOLD  : 4;            /*!< [11..8] sensor检测警报持续时间门限,大于此门限发出
+                                                     警报,否则不报警。
+                                                     时间门限值: (2^sensor_delay)*hclk                                    */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * result *                                                 */
+
+    struct {
+      __IM  uint32_t            : 1;
+      __IM  uint32_t STATE      : 8;            /*!< [8..1] 1: 对应检测项报警。
+                                                     [8]: 低温自检警报
+                                                     [7]: 高温自检警报
+                                                     [6]: 纽扣电池3.3v输出低压自检警报
+                                                     [5]: 纽扣电池3.3v输出高压自检警报
+                                                     [4]: 纽扣电池1.2v输出低压自检警报
+                                                     [3]: 锂电池3.3v输出低压自检警报
+                                                     [2]: 锂电池3.3v输出高压自检警报
+                                                     [1]: 安全域电源1.2v输出低压自检警报                          */
+      __IM  uint32_t VDDSEC_UVH : 1;            /*!< [9..9] 安全域电源1.2v输出低压自检电路结果输出            */
+      __IM  uint32_t VDDSEC_UHVB : 1;           /*!< [10..10] 安全域电源1.2v输出低压自检电路结果输出          */
+      __IM  uint32_t VSEC_OVH   : 1;            /*!< [11..11] 锂电池3.3v输出高压自检电路结果输出                */
+      __IM  uint32_t VSEC_OVHB  : 1;            /*!< [12..12] 锂电池3.3v输出高压自检电路结果输出                */
+      __IM  uint32_t VSEC_UVH   : 1;            /*!< [13..13] 锂电池3.3v输出低压自检电路结果输出                */
+      __IM  uint32_t VSEC_UHVB  : 1;            /*!< [14..14] 锂电池3.3v输出低压自检电路结果输出                */
+      __IM  uint32_t DVDDLPM_UVH : 1;           /*!< [15..15] 纽扣电池1.2v输出低压自检电路结果输出             */
+      __IM  uint32_t DVDDLPM_UVHB : 1;          /*!< [16..16] 纽扣电池1.2v输出低压自检电路结果输出             */
+      __IM  uint32_t VBUT_OVH   : 1;            /*!< [17..17] 纽扣电池3.3v输出高压自检电路结果输出             */
+      __IM  uint32_t VBUT_OVHB  : 1;            /*!< [18..18] 纽扣电池3.3v输出高压自检电路结果输出             */
+      __IM  uint32_t VBUT_UVH   : 1;            /*!< [19..19] 纽扣电池3.3v输出低压自检电路结果输出             */
+      __IM  uint32_t VBUT_UVHB  : 1;            /*!< [20..20] 纽扣电池3.3v输出低压自检电路结果输出             */
+      __IM  uint32_t TS_OTH     : 1;            /*!< [21..21] 高温自检电路结果输出                                   */
+      __IM  uint32_t TS_OTHB    : 1;            /*!< [22..22] 高温自检电路结果输出                                   */
+      __IM  uint32_t TS_UTH     : 1;            /*!< [23..23] 低温自检电路结果输出                                   */
+      __IM  uint32_t TS_UTHB    : 1;            /*!< [24..24] 低温自检电路结果输出                                   */
+    } bit;
+  } result;
+  __IM  uint32_t  RESERVED[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * RTC_IE *                                                 */
+
+    struct {
+      __IOM uint32_t LSI_IE     : 1;            /*!< [0..0] 1: enable rtc_lsi irq                                              */
+      __IOM uint32_t LSE_IE     : 1;            /*!< [1..1] 1: enable rtc_lse irq                                              */
+      __IM  uint32_t            : 14;
+      __IM  uint32_t LSI_IRQ    : 1;            /*!< [16..16] rtc_lsi_irq flag, 仅指中断标志
+                                                     ,清除需要使用RTC_LSI寄存器                                       */
+      __IM  uint32_t LSE_IRQ    : 1;            /*!< [17..17] rtc_lse_irq flag, 仅指中断标志
+                                                     ,清除需要使用RTC_LSE寄存器                                       */
+    } bit;
+  } RTC_IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * IE *                                                     */
+
+    struct {
+      __IOM uint32_t IE         : 1;            /*!< [0..0] SEC中断总开关
+                                                     both lpm security events and
+                                                     core security events will t
+                                                     rigger secure_irq                                                         */
+      __IOM uint32_t CORE_IE    : 1;            /*!< [1..1] CORE SEC中断开关
+                                                     1: enable core security even
+                                                     t interrupt                                                               */
+      __IM  uint32_t            : 14;
+      __IM  uint32_t LPM_IRQ    : 1;            /*!< [16..16] lpm security irq status                                          */
+    } bit;
+  } IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * SENSOR_CTRL *                                            */
+
+    struct {
+      __IOM uint32_t VSEC_EN    : 4;            /*!< [3..0] 0x5, disable sensor, els
+                                                     e enable sensor                                                           */
+      __IOM uint32_t VDDSEC_EN  : 4;            /*!< [7..4] 0x5, disable sensor, els
+                                                     e enable sensor                                                           */
+      __IM  uint32_t            : 8;
+      __IOM uint32_t VSEC_L_SEL : 4;            /*!< [19..16] threshold voltage select
+                                                     ion(sim tt 50deg, voltage fr
+                                                     om low to high):
+                                                     0000: 1.938
+                                                     0001: 1.971
+                                                     0010: 2.005
+                                                     0011: 2.040
+                                                     0100: 2.076
+                                                     0101: 2.113
+                                                     0110: 2.152
+                                                     0111: 2.193
+                                                     1000: 2.235
+                                                     1001: 2.278
+                                                     1010: 2.324
+                                                     1011: 2.371
+                                                     1100: 2.420
+                                                     1101: 2.471
+                                                     1110: 2.525
+                                                     1111: 2.580                                                               */
+      __IOM uint32_t VSEC_H_SEL : 4;            /*!< [23..20] threshold voltage select
+                                                     ion(sim tt 50deg, voltage fr
+                                                     om low to high):
+                                                     0000: 3.369
+                                                     0001: 3.419
+                                                     0010: 3.469
+                                                     0011: 3.522
+                                                     0100: 3.576
+                                                     0101: 3.631
+                                                     0110: 3.688
+                                                     0111: 3.748
+                                                     1000: 3.809
+                                                     1001: 3.872
+                                                     1010: 3.937
+                                                     1011: 4.005
+                                                     1100: 4.074
+                                                     1101: 4.147
+                                                     1110: 4.222
+                                                     1111: 4.299                                                               */
+      __IOM uint32_t VDDSEC_SEL : 4;            /*!< [27..24] threshold voltage select
+                                                     ion(sim tt 50deg, voltage fr
+                                                     om low to high):
+                                                     0000: 867mV
+                                                     0001: 887mV
+                                                     0010: 907mV
+                                                     0011: 927mV
+                                                     0100: 947mV
+                                                     0101: 967mV
+                                                     0110: 987mV
+                                                     0111: 1005mV
+                                                     1000: 1025mV
+                                                     1001: 1045mV
+                                                     1010: 1065mV
+                                                     1011: 1085mV
+                                                     1100: 1105mV
+                                                     1101: 1125mV
+                                                     1110: 1145mV
+                                                     1111: 1165mV                                                              */
+    } bit;
+  } SENSOR_CTRL;
+} MSECURE_Type;                                 /*!< Size = 28 (0x1c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MGPIO                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 8 GPIO (MGPIO)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8700) MGPIO Structure                                            */
+
+  union {
+    __IOM uint8_t reg[80];                      /*!< (@ 0x00000000) [0..79]                                                    */
+
+    struct {
+      __IOM uint8_t FUNC        : 6;            /*!< [5..0] GPIO function                                                      */
+      __IOM uint8_t MODE        : 2;            /*!< [7..6] GPIO mode                                                          */
+    } bit[80];
+  } CTRL;
+  __IM  uint16_t  RESERVED[24];
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x00000080) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } INTR;
+  __IM  uint16_t  RESERVED1[3];
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x00000090) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } IRQ_LEVEL;
+  __IM  uint16_t  RESERVED2[3];
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x000000A0) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } IRQ_RISE;
+  __IM  uint16_t  RESERVED3[3];
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x000000B0) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } IRQ_FALL;
+  __IM  uint16_t  RESERVED4[3];
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x000000C0) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } IRQ_STATUS;
+  __IM  uint16_t  RESERVED5[2];
+  __IM  uint8_t   RESERVED6;
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x000000CF) GPIO_IRQ_INDEX register                                    */
+
+    struct {
+      __IM  uint8_t INDEX       : 8;            /*!< [7..0] GPIO_IRQ_INDEX                                                     */
+    } bit;
+  } IRQ_NUM;
+
+  union {
+    __IOM uint16_t reg[5];                      /*!< (@ 0x000000D0) [0..4]                                                     */
+
+    struct {
+      __IOM uint16_t PIN0       : 1;            /*!< [0..0] PIN0                                                               */
+      __IOM uint16_t PIN1       : 1;            /*!< [1..1] PIN1                                                               */
+      __IOM uint16_t PIN2       : 1;            /*!< [2..2] PIN2                                                               */
+      __IOM uint16_t PIN3       : 1;            /*!< [3..3] PIN3                                                               */
+      __IOM uint16_t PIN4       : 1;            /*!< [4..4] PIN4                                                               */
+      __IOM uint16_t PIN5       : 1;            /*!< [5..5] PIN5                                                               */
+      __IOM uint16_t PIN6       : 1;            /*!< [6..6] PIN6                                                               */
+      __IOM uint16_t PIN7       : 1;            /*!< [7..7] PIN7                                                               */
+      __IOM uint16_t PIN8       : 1;            /*!< [8..8] PIN8                                                               */
+      __IOM uint16_t PIN9       : 1;            /*!< [9..9] PIN9                                                               */
+      __IOM uint16_t PIN10      : 1;            /*!< [10..10] PIN10                                                            */
+      __IOM uint16_t PIN11      : 1;            /*!< [11..11] PIN11                                                            */
+      __IOM uint16_t PIN12      : 1;            /*!< [12..12] PIN12                                                            */
+      __IOM uint16_t PIN13      : 1;            /*!< [13..13] PIN13                                                            */
+      __IOM uint16_t PIN14      : 1;            /*!< [14..14] PIN14                                                            */
+      __IOM uint16_t PIN15      : 1;            /*!< [15..15] PIN15                                                            */
+    } bit[5];
+  } IN_LEVEL;
+  __IM  uint16_t  RESERVED7[3];
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x000000E0) GPIO_OD register                                           */
+
+    struct {
+      __IOM uint8_t PA10        : 1;            /*!< [0..0] GPIO_OD                                                            */
+      __IOM uint8_t PB6         : 1;            /*!< [1..1] GPIO_OD                                                            */
+      __IOM uint8_t PC1         : 1;            /*!< [2..2] GPIO_OD                                                            */
+      __IOM uint8_t PC8         : 1;            /*!< [3..3] GPIO_OD                                                            */
+      __IOM uint8_t PD0         : 1;            /*!< [4..4] GPIO_OD                                                            */
+      __IOM uint8_t PD12        : 1;            /*!< [5..5] GPIO_OD                                                            */
+      __IOM uint8_t PE12        : 1;            /*!< [6..6] GPIO_OD                                                            */
+      __IOM uint8_t PE6         : 1;            /*!< [7..7] GPIO_OD                                                            */
+    } bit;
+  } OD_CTRL;
+  __IM  uint8_t   RESERVED8;
+  __IM  uint16_t  RESERVED9;
+} MGPIO_Type;                                   /*!< Size = 228 (0xe4)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MDMA                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 DMA (MDMA)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8800) MDMA Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) DMA_SRC_ADDR register                                      */
+
+    struct {
+      __OM  uint32_t VAL        : 32;           /*!< [31..0] source address                                                    */
+    } bit;
+  } SRC_ADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) DMA_DEST_ADDR register                                     */
+
+    struct {
+      __OM  uint32_t VAL        : 32;           /*!< [31..0] dest address                                                      */
+    } bit;
+  } DEST_ADDR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) DMA_LEN_LOW register                                       */
+
+    struct {
+      __IOM uint32_t RX_LEN_L   : 16;           /*!< [15..0] buff len                                                          */
+      __IOM uint32_t TX_LEN_L   : 16;           /*!< [31..16] buff len                                                         */
+    } bit;
+  } LEN_LOW;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) DMA control register                                       */
+
+    struct {
+      __IOM uint32_t LOOPBACK   : 1;            /*!< [0..0] loop back mode                                                     */
+      __IOM uint32_t INT_MODE   : 1;            /*!< [1..1] enable interrupt                                                   */
+      __IOM uint32_t RADDR_LOCK : 1;            /*!< [2..2] lock read addr                                                     */
+      __IOM uint32_t WADDR_LOCK : 1;            /*!< [3..3] lock write addr                                                    */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t RX_LEN_H   : 4;            /*!< [11..8] rx len                                                            */
+      __IOM uint32_t TX_LEN_H   : 4;            /*!< [15..12] tx len                                                           */
+      __IOM uint32_t PP_BUF     : 1;            /*!< [16..16] flag slave/dcmi                                                  */
+      __IM  uint32_t            : 12;
+      __IOM uint32_t RESET      : 1;            /*!< [29..29] init write 0,write 1                                             */
+      __IOM uint32_t CLEAR_INT  : 1;            /*!< [30..30] clear DMA int                                                    */
+      __IOM uint32_t START      : 1;            /*!< [31..31] enable DMA                                                       */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) DMA status                                                 */
+
+    struct {
+      __IM  uint32_t DONE       : 1;            /*!< [0..0] DMA status                                                         */
+    } bit;
+  } STATUS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) Sends the current address of the BUF read pointer          */
+
+    struct {
+      __IM  uint32_t VAL        : 32;           /*!< [31..0] Sends the current address of the BUF read pointer                 */
+    } bit;
+  } RPTR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) received the current address of the BUF read
+                                                                    pointer                                                    */
+
+    struct {
+      __IM  uint32_t VAL        : 32;           /*!< [31..0] receiced the current address of the BUF read pointer              */
+    } bit;
+  } WPRT;
+} MDMA_Type;                                    /*!< Size = 28 (0x1c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MSPI                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MSPI (MSPI)
+  */
+
+typedef struct {                                /*!< (@ 0x000F891C) MSPI Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t CLK_DIV    : 3;            /*!< [2..0] SPICLK 分频系数 (1<<CTRL[2:0
+                                                     ])                                                                        */
+      __IOM uint32_t MODE       : 1;            /*!< [3..3] 0: Master Mode 1：Slave
+                                                     Mode                                                                      */
+      __IOM uint32_t CPHA       : 1;            /*!< [4..4] CPHA 1: 偶数边沿采样 0: 奇数边沿
+                                                     采样                                                                    */
+      __IOM uint32_t CPOL       : 1;            /*!< [5..5] CPOL （空闲状态时钟电平） 1: High
+                                                     0: Low                                                                    */
+      __IOM uint32_t RESET      : 1;            /*!< [6..6] spi_reset                                                          */
+      __IOM uint32_t DCMI_EN    : 1;            /*!< [7..7] 0: 8-bit spi mode
+                                                     1: 8-bit byte y extended to
+                                                     16-bit rgb565                                                             */
+      __IOM uint32_t RW_DELAY   : 7;            /*!< [14..8] 反向间隔（value*16个clock）                                */
+      __IOM uint32_t AUTO_START : 1;            /*!< [15..15] 1: spi dma可以被dcmi多行中断自动启
+                                                     动                                                                       */
+      __IOM uint32_t SCK_DIR    : 1;            /*!< [16..16] ncs 与 sck 输入输出选择
+                                                     0: 输出(master mode)
+                                                     1: 输入(slave mode)                                                     */
+      __IOM uint32_t RX_PHASE   : 1;            /*!< [17..17] 0: normal receive sample
+                                                     point
+                                                     1: receive sample point dela
+                                                     y one clock of ahb_bus                                                    */
+      __IOM uint32_t FIRST_BIT  : 1;            /*!< [18..18] 1: 先发送lsb
+                                                     0:先发送MSB                                                            */
+      __IOM uint32_t WAIT_DMA   : 1;            /*!< [19..19] 0: ignore dma status
+                                                     1: 等待dma 完全写入ram ,再开始接收下1 by
+                                                     te                                                                        */
+    } bit;
+  } CTRL;
+} MSPI_Type;                                    /*!< Size = 4 (0x4)                                                            */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MUART                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MUART (MUART)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8B1C) MUART Structure                                            */
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x00000000) * CTRL *                                                   */
+
+    struct {
+      __IOM uint8_t RX_EN       : 1;            /*!< [0..0] UART 使能位
+                                                     0：失能Rx功能
+                                                     1：使能Rx功能
+                                                                                                                               */
+      __IOM uint8_t PARITY      : 1;            /*!< [1..1] UART 校验位
+                                                     0：Parity_Even(偶校验)
+                                                     1：Parity_Odd(奇校验)
+                                                                                                                               */
+      __IOM uint8_t DATA_BITS   : 1;            /*!< [2..2] UART 校验使能位
+                                                     0：无校验位,仅发送8bit数据
+                                                     1：有校验位,发送9bit数据。
+                                                                                                                               */
+      __IOM uint8_t STOP_BITS   : 1;            /*!< [3..3] UART 停止位
+                                                     0：1bit停止位
+                                                     1：2bit停止位
+                                                                                                                               */
+      __IOM uint8_t FLOW_CTRL   : 1;            /*!< [4..4] UART 模块流控控制位
+                                                     0：无流控模式
+                                                     1：有流控模式
+                                                                                                                               */
+      __IOM uint8_t SMART_CARD  : 1;            /*!< [5..5] UART 智能卡模式控制位
+                                                     0：关闭智能卡
+                                                     1：开启智能卡模式                                                 */
+      __IOM uint8_t HDX_EN      : 1;            /*!< [6..6] UART全双工/双工模式控制位
+                                                     0：全双工
+                                                     1：半双工
+                                                                                                                               */
+      __IOM uint8_t RESET_BAUD  : 1;            /*!< [7..7] UART重置波特率位
+                                                     0：无操作
+                                                     1：必须先配置好波特率，置位1后 波特率才能生效。
+                                                                                                                               */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x00000001) * RX_INT_LEN *                                             */
+
+    struct {
+      __IOM uint8_t VAL         : 8;            /*!< [7..0] 控制串口接收中断长度，为0不触发中断               */
+    } bit;
+  } RX_INT_LEN;
+
+  union {
+    __IOM uint16_t reg;                         /*!< (@ 0x00000002) * BAUD *                                                   */
+
+    struct {
+      __IOM uint16_t BAUD_RATE  : 15;           /*!< [14..0] 配置波特率 (波特率=时钟/寄存器的值)                */
+      __IOM uint16_t TX_INT_EN  : 1;            /*!< [15..15] 发送中断使能位 0：失能tx中断 1：使能tx
+                                                     中断                                                                    */
+    } bit;
+  } BAUD;
+
+  union {
+    __IOM uint16_t reg;                         /*!< (@ 0x00000004) * TIMEOUT_INT *                                            */
+
+    struct {
+      __IOM uint16_t VAL        : 16;           /*!< [15..0] 0：不启用。当收到数据后开始计时，超时未收到下一
+
+                                                     个字节则触发中断，接收超时中断时间值（48*value）
+                                                     。                                                                       */
+    } bit;
+  } TIMEOUT_INT;
+  __IM  uint16_t  RESERVED;
+
+  union {
+    __IOM uint8_t reg;                          /*!< (@ 0x00000008) * RX_DATA *                                                */
+
+    struct {
+      __IM  uint8_t VAL         : 8;            /*!< [7..0] 读取UART的数据                                                */
+    } bit;
+  } RX_DATA;
+  __IM  uint8_t   RESERVED1;
+  __IM  uint16_t  RESERVED2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * STATUS *                                                 */
+
+    struct {
+      __IOM uint32_t RX_EMPTY   : 1;            /*!< [0..0] 0:rx buf 非空 1:rx buf 为空                                    */
+      __IOM uint32_t RX_FULL    : 1;            /*!< [1..1] 0:rx buf 未满 1:rx buf 满                                       */
+      __IOM uint32_t RX_NEAR_FULL : 1;          /*!< [2..2] 0:rx buf 数据未接近满 1:rx bu
+                                                     f 数据接近满                                                         */
+      __IM  uint32_t            : 9;
+      __IOM uint32_t RX_ITEMS_H : 4;            /*!< [15..12] 当前RX BUF中的数据个数高4位                            */
+      __IOM uint32_t RX_ITEMS_L : 16;            /*!< [23..16] 当前RX BUF中的数据个数低16位                           */
+    } bit;
+  } STATUS;
+} MUART_Type;                                   /*!< Size = 16 (0x10)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MIIC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MIIC (MIIC)
+  */
+
+typedef struct {                                /*!< (@ 0x000F911C) MIIC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL1 *                                                  */
+
+    struct {
+      __IOM uint32_t SCLL       : 8;            /*!< [7..0] scll scl低电平时间                                            */
+      __IOM uint32_t SCLH       : 8;            /*!< [15..8] sclh scl高电平时间                                           */
+      __IOM uint32_t STSU       : 8;            /*!< [23..16] stsu 起始位建立时间                                       */
+      __IOM uint32_t STHD       : 8;            /*!< [31..24] sthd 起始位保持时间                                       */
+    } bit;
+  } CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * CTRL2 *                                                  */
+
+    struct {
+      __IOM uint32_t SOSU       : 8;            /*!< [7..0] sosu 停止位建立时间                                         */
+      __IOM uint32_t DTSU       : 8;            /*!< [15..8] dtsu 数据位的建立时间                                     */
+      __IOM uint32_t DTHD       : 8;            /*!< [23..16] dthd 数据位的保持时间                                    */
+      __IOM uint32_t RESTART    : 1;            /*!< [24..24] restart 注意！！！这一bit是控
+                                                     制I2C协议中restart时序的,而不是复位I2C寄存
+                                                     器；在写从设备的时候置0,在读从设备的时候要置1        */
+    } bit;
+  } CTRL2;
+} MIIC_Type;                                    /*!< Size = 8 (0x8)                                                            */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MLPM                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MLPM (MLPM)
+  */
+
+typedef struct {                                /*!< (@ 0x000FA800) MLPM Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) analog register                                            */
+
+    struct {
+      __IOM uint32_t RG_LPM_LDO_LPM_VSEL : 5;   /*!< [4..0] digital aon ldo vout sel                                           */
+      __IOM uint32_t RG_LPM_LDO_LPM_0P33VDD_BYPB : 1;/*!< [5..5] LPM 0.33vdd ldo bypass to gnd enable control, low active      */
+      __IOM uint32_t RG_LPM_HVLDO_OCP_EN : 1;   /*!< [6..6] HVLDO over current protection enable                               */
+      __IOM uint32_t RG_LPM_POR_DEGLITCH_OPT : 1;/*!< [7..7] Vcoin POR deglitch optimization control, high active              */
+      __IOM uint32_t RG_LPM_VSEC_POR_DEGLITCH_OPT : 1;/*!< [8..8] Vlion POR deglitch optimization control, high active         */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t RG_LPM_LDO_SEC_VTRIM : 4;  /*!< [15..12] Security main LDO output voltage control                         */
+      __IOM uint32_t RG_LPM_OSC192M_VC : 9;     /*!< [24..16] RC OSC 192MHz frequency control                                  */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t RG_LPM_LDO_SEC_EN : 1;     /*!< [28..28] Security main LDO enable                                         */
+      __IOM uint32_t RG_LPM_LDO_OSC192M_EN : 1; /*!< [29..29] RC OSC 192MHz LDO enable                                         */
+      __IOM uint32_t RG_LPM_OSC192M_RSTN : 1;   /*!< [30..30] RC OSC 192MHz resetn                                             */
+      __IOM uint32_t RG_LPM_OSC192M_EN : 1;     /*!< [31..31] RC OSC 192MHz enable                                             */
+    } bit;
+  } LDO_POR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) analog register                                            */
+
+    struct {
+      __IOM uint32_t OSC_XTAL_REF_MODE_EN : 1;  /*!< [0..0] mode cfg                                                           */
+      __IOM uint32_t OSC_XTAL_IB_OBUF : 2;      /*!< [2..1] xtal output buffer bias current ctrl                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t OSC_XTAL_IB_CTRL : 4;      /*!< [7..4] xtal core bias current ctrl                                        */
+      __IOM uint32_t OSC_XTAL_CTRIM : 5;        /*!< [12..8] xtal cap bank selection                                           */
+      __IOM uint32_t OSC_XTAL_EN_REG : 1;       /*!< [13..13] xtal regulator enable, high active                               */
+      __IOM uint32_t OSC_XTAL_EN : 1;           /*!< [14..14] xtal core enable, high active                                    */
+      __IOM uint32_t OSC_XTAL_DIV2_EN : 1;      /*!< [15..15] xtal to clkpll ref freq div2 enable, high active                 */
+    } bit;
+  } OSC_XTAL;
+  __IM  uint32_t  RESERVED[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) XO32K control                                              */
+
+    struct {
+      __IOM uint32_t RG_LPM_XO32K_RG_XTAL_CGM_ISEL : 2;/*!< [1..0] xo32k constant-gm current selection                         */
+      __IOM uint32_t RG_LPM_XO32K_RDC_SEL : 3;  /*!< [4..2] xo32k gm gate-drain dc res type selection                          */
+      __IOM uint32_t RG_LPM_XO32K_ITUNE : 5;    /*!< [9..5] xo32k gm current selection                                         */
+      __IOM uint32_t RG_LPM_XO32K_GMP_BYPASS : 1;/*!< [10..10] xo32k gm pmos bypass, high active. when xo32k mode              */
+      __IOM uint32_t RG_LPM_XO32K_DISCONNECT : 1;/*!< [11..11] disconnect xo32k analog circuit from gpio pad, high
+                                                     active                                                                    */
+      __IOM uint32_t RG_LPM_XO32K_COMP_VREF_TUNE : 2;/*!< [13..12] xo32k comp voltage selection when vrefn from vgen,
+                                                     control bits higher                                                       */
+      __IOM uint32_t RG_LPM_XO32K_COMP_VN_SEL : 1;/*!< [14..14] xo32k hysteresis comp negative input signal selection          */
+      __IOM uint32_t RG_LPM_XO32K_COMP_VGEN_EN : 1;/*!< [15..15] xo32k comp vrefn voltage gen circuit enable, high active      */
+      __IOM uint32_t RG_LPM_XO32K_COMP_TH_SEL : 2;/*!< [17..16] xo32k hysteresis comp threshold voltage selection,
+                                                     control bits higher, vth higher                                           */
+      __IOM uint32_t RG_LPM_XO32K_COMP_ISEL : 2;/*!< [19..18] xo32k hysteresis comp current selection                          */
+      __IOM uint32_t RG_LPM_XO32K_COMP_IB_LARGE : 1;/*!< [20..20] xo32k hysteresis comp and current-starved invter bais
+                                                     current enlarge control, high active                                      */
+      __IOM uint32_t DA_LPM_XO32K_EN : 1;       /*!< [21..21] xo32k enable, high active                                        */
+    } bit;
+  } XO32K;
+  __IM  uint32_t  RESERVED1[3];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) CHGR control register                                      */
+
+    struct {
+      __IOM uint32_t RG_LPM_CHGR_TERMC : 2;     /*!< [1..0] Charging termination current control                               */
+      __IOM uint32_t RG_LPM_CHGR_TCC : 2;       /*!< [3..2] analog register                                                    */
+      __IOM uint32_t RG_LPM_CHGR_SHUTDOWN_SW : 1;/*!< [4..4] Force off charger pass transistor                                 */
+      __IOM uint32_t RG_LPM_CHGR_SHUTDOWN_CORE : 1;/*!< [5..5] Force off charger CC/CV loop                                    */
+      __IOM uint32_t RG_LPM_CHGR_SHUTDOWN_BIAS : 1;/*!< [6..6] Force off charger bias                                          */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t RG_LPM_CHGR_RCHC : 4;      /*!< [11..8] Battery voltage threshold adjustments for re-charging
+                                                     in 53mV/steps                                                             */
+      __IOM uint32_t RG_LPM_CHGR_INSC_ENB : 1;  /*!< [12..12] Charger input sink current enable. Used to wake up
+                                                     charger case and to be turned off upon the end of charging
+                                                     process                                                                   */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t RG_LPM_CHGR_ICHG_SET : 4;  /*!< [19..16] Charging current control in CC phase                             */
+      __IOM uint32_t RG_LPM_CHGR_FORCE_CV : 1;  /*!< [20..20] Charger CV mode force enable                                     */
+      __IOM uint32_t RG_LPM_CHGR_FORCE_CORE_ON : 1;/*!< [21..21] Force on charger CC/CV loop when charger is in standby
+                                                     mode                                                                      */
+      __IOM uint32_t RG_LPM_CHGR_FORCE_CC : 1;  /*!< [22..22] Charger CC mode force enable                                     */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t RG_LPM_CHGR_CVC : 4;       /*!< [27..24] analog register                                                  */
+      __IOM uint32_t RG_LPM_CHGR_RLIMIT_ENB : 1;/*!< [28..28] analog register                                                  */
+    } bit;
+  } CHGR_CTRL;
+  __IM  uint32_t  RESERVED2[119];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000200) * GPIO_WKEN_W0 *                                           */
+
+    struct {
+      __IOM uint32_t LOW        : 32;           /*!< [31..0] gpio[31:0] 深度睡眠唤醒使能                               */
+    } bit;
+  } GPIO_WKEN_W0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000204) * GPIO_WKEN_W1 *                                           */
+
+    struct {
+      __IOM uint32_t MID        : 32;           /*!< [31..0] gpio[63:32] 深度睡眠唤醒使能                              */
+    } bit;
+  } GPIO_WKEN_W1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000208) * GPIO_WKEN_W2 *                                           */
+
+    struct {
+      __IOM uint32_t HIGH       : 16;           /*!< [15..0] gpio[79:64] 深度睡眠唤醒使能                              */
+    } bit;
+  } GPIO_WKEN_W2;
+  __IM  uint32_t  RESERVED3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000210) * GPIO_WK_LEVEL *                                          */
+
+    struct {
+      __IOM uint32_t LEVEL      : 1;            /*!< [0..0] GPIO唤醒电平设置
+                                                     0: GPIO高电平唤醒深度睡眠
+                                                     1: GPIO低电平唤醒深度睡眠                                        */
+    } bit;
+  } GPIO_WK_LEVEL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000214) * GPIO_LATCH *                                             */
+
+    struct {
+      __IOM uint32_t LATCH      : 1;            /*!< [0..0] nan                                                                */
+    } bit;
+  } GPIO_LATCH;
+  __IM  uint32_t  RESERVED4[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000220) * DEEP_SLEEP *                                             */
+
+    struct {
+      __OM  uint32_t EN         : 8;            /*!< [7..0] 写0x5a会进入深度睡眠                                       */
+    } bit;
+  } DEEP_SLEEP;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000224) * WAKEUP_CTRL *                                            */
+
+    struct {
+      __IOM uint32_t SEC_EN     : 1;            /*!< [0..0] 1: 使能安全事件唤醒深度睡眠                            */
+      __IOM uint32_t RTC_LSI    : 1;            /*!< [1..1] 1:使能LSI定时唤醒深度睡眠                                */
+      __IOM uint32_t RTC_LSE    : 1;            /*!< [2..2] 1: 使能LSE定时唤醒深度睡眠                               */
+    } bit;
+  } WAKEUP_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000228) * WAIT_LDO_CTRL *                                          */
+
+    struct {
+      __IOM uint32_t CNT        : 10;           /*!< [9..0] core_ldo打开后,等待cnt个osc32k
+                                                     周期后,开始启动系统,首次上电默认值为32ms
+                                                     deep_sleep时,可通过合理设置此延迟值,减少系统
+                                                     退出deep_sleep时间                                                    */
+    } bit;
+  } WAIT_LDO_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000022C) * WKUP_HVLDO_CTRL *                                        */
+
+    struct {
+      __IOM uint32_t FIRST      : 1;            /*!< [0..0] 1: 深度睡眠唤醒时,先打开HVLDO,再进行上
+                                                     电过程                                                                 */
+      __IM  uint32_t            : 15;
+      __IOM uint32_t CHGR_IN_TURN_ON : 8;       /*!< [23..16] chgr_in事件打开系统使能
+                                                     0xaa: 关闭chgr_in事件打开系统功能
+                                                     others: 打开chgr_in事件打开系统功能                             */
+      __IOM uint32_t PWK_OFF_DISABLE : 8;       /*!< [31..24] power key off disable
+                                                     0xaa: 禁用power key 关闭系统功能
+                                                     others: 使能power 关闭系统功能                                    */
+    } bit;
+  } WKUP_HVLDO_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000230) * RTC_LSE_CTRL *                                           */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] 使能 RTC LSE的时钟                                            */
+      __IOM uint32_t SEL        : 1;            /*!< [1..1] RTC_LSE的时钟选择
+                                                     0: 用LSI作为RTC_LSE的时钟
+                                                     1:用LSEZ作为RTC_LSE的时钟                                           */
+    } bit;
+  } RTC_LSE_CTRL;
+  __IM  uint32_t  RESERVED5[3];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000240) * CHGR_EVENT_EN *                                          */
+
+    struct {
+      __IOM uint32_t EVENT0     : 1;            /*!< [0..0] 1: 使能CHGR_WKUP[9:0]充电标志位
+                                                     检测和唤醒,使能后需要延时1ms再配置CHGR_WKUP
+                                                     _HI_EN[9:0]/CHGR_WKUP_LO_EN[
+                                                     9:0]                                                                      */
+      __IOM uint32_t EVENT1     : 1;            /*!< [1..1] 1: 使能CHGR_WKUP[11:10]充电标
+                                                     志位检测和唤醒,使能后需要延时1ms再配置CHGR_WK
+                                                     UP_HI_EN[11:10]/CHGR_WKUP_LO
+                                                     _EN[11:10]                                                                */
+    } bit;
+  } CHGR_EVENT_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000244) * CHGR_WKUP_HI_EN *                                        */
+
+    struct {
+      __IOM uint32_t VBAT_LV    : 1;            /*!< [0..0] ad_lpm_chgr_state_vbat_l
+                                                     v                                                                         */
+      __IOM uint32_t RCH_EN     : 1;            /*!< [1..1] ad_lpm_chgr_state_rch_en                                           */
+      __IOM uint32_t IND        : 1;            /*!< [2..2] ad_lpm_chgr_state_ind                                              */
+      __IOM uint32_t ICHG       : 1;            /*!< [3..3] ad_lpm_chgr_state_ichg                                             */
+      __IOM uint32_t RESET      : 1;            /*!< [4..4] ad_lpm_chgr_reset                                                  */
+      __IOM uint32_t UVLO_OK_AON : 1;           /*!< [5..5] ad_lpm_chgr_uvlo_ok_aon                                            */
+      __IOM uint32_t PGOOD      : 1;            /*!< [6..6] ad_lpm_chgr_pgood                                                  */
+      __IOM uint32_t DPPM_OV_CV : 1;            /*!< [7..7] ad_lpm_chgr_dppm_ov_cv                                             */
+      __IOM uint32_t DPPM_OV_CC : 1;            /*!< [8..8] ad_lpm_chgr_dppm_ov_cc                                             */
+      __IOM uint32_t CC_OV_CV   : 1;            /*!< [9..9] ad_lpm_chgr_cc_ov_cv                                               */
+      __IOM uint32_t DET_AON    : 1;            /*!< [10..10] ad_lpm_chgr_in_det_aon                                           */
+      __IOM uint32_t VBAT_OV    : 1;            /*!< [11..11] ad_lpm_vbat_ov_flag                                              */
+      __IOM uint32_t PWK        : 1;            /*!< [12..12] power_key                                                        */
+    } bit;
+  } CHGR_WKUP_HI_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000248) * CHGR_WKUP_LO_EN *                                        */
+
+    struct {
+      __IOM uint32_t VBAT_LV    : 1;            /*!< [0..0] ad_lpm_chgr_state_vbat_l
+                                                     v                                                                         */
+      __IOM uint32_t RCH_EN     : 1;            /*!< [1..1] ad_lpm_chgr_state_rch_en                                           */
+      __IOM uint32_t IND        : 1;            /*!< [2..2] ad_lpm_chgr_state_ind                                              */
+      __IOM uint32_t ICHG       : 1;            /*!< [3..3] ad_lpm_chgr_state_ichg                                             */
+      __IOM uint32_t RESET      : 1;            /*!< [4..4] ad_lpm_chgr_reset                                                  */
+      __IOM uint32_t UVLO_OK_AON : 1;           /*!< [5..5] ad_lpm_chgr_uvlo_ok_aon                                            */
+      __IOM uint32_t PGOOD      : 1;            /*!< [6..6] ad_lpm_chgr_pgood                                                  */
+      __IOM uint32_t DPPM_OV_CV : 1;            /*!< [7..7] ad_lpm_chgr_dppm_ov_cv                                             */
+      __IOM uint32_t DPPM_OV_CC : 1;            /*!< [8..8] ad_lpm_chgr_dppm_ov_cc                                             */
+      __IOM uint32_t CC_OV_CV   : 1;            /*!< [9..9] ad_lpm_chgr_cc_ov_cv                                               */
+      __IOM uint32_t DET_AON    : 1;            /*!< [10..10] ad_lpm_chgr_in_det_aon                                           */
+      __IOM uint32_t VBAT_OV    : 1;            /*!< [11..11] ad_lpm_vbat_ov_flag                                              */
+      __IOM uint32_t PWK        : 1;            /*!< [12..12] power_key                                                        */
+    } bit;
+  } CHGR_WKUP_LO_EN;
+  __IM  uint32_t  RESERVED6[5];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000260) * PWK_CTRL *                                               */
+
+    struct {
+      __IOM uint32_t ON_TIME    : 2;            /*!< [1..0] power key 按下多长时间唤醒系统配置
+                                                     00: 128ms
+                                                     01: 384ms
+                                                     10: 640ms
+                                                     11: 896ms                                                                 */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t OFF_TIME   : 2;            /*!< [5..4] power_key按下多长时间关闭系统配置
+                                                     00: 4s
+                                                     01: 5s
+                                                     10: 6s
+                                                     11: 7s                                                                    */
+      __IM  uint32_t            : 10;
+      __OM  uint32_t LDO_OFF    : 1;            /*!< [16..16] 写1 关闭HVLDO                                                 */
+      __OM  uint32_t LDO_EN     : 1;            /*!< [17..17] 写1 打开HVLDO                                                 */
+    } bit;
+  } PWK_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000264) * LDO_EXEN_CTRL *                                          */
+
+    struct {
+      __IOM uint32_t OEN        : 1;            /*!< [0..0] 0: enable output
+                                                     1: disable output                                                         */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t OUT        : 1;            /*!< [2..2] nan                                                                */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PD         : 1;            /*!< [4..4] 1: enable pull-down                                                */
+      __IOM uint32_t PU         : 1;            /*!< [5..5] 1: enable pull-up                                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t IE         : 1;            /*!< [8..8] 0: disable input
+                                                     1: enable input                                                           */
+      __IM  uint32_t IN         : 1;            /*!< [9..9] ldo_exen input value                                               */
+      __IM  uint32_t            : 14;
+      __IOM uint32_t GPIO       : 8;            /*!< [31..24] 0xaa: gpio 模式,pu/pd/ie/o
+                                                     /oen受寄存器控制
+                                                     others: ldo_exen模式,pu/pd/ie始
+                                                     终为0,oen为0允许输出,o输出hvldo_en信号                         */
+    } bit;
+  } LDO_EXEN_CTRL;
+  __IM  uint32_t  RESERVED7[6];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000280) * CLK_CTRL *                                               */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] 1: 使能寄存器时钟                                           */
+    } bit;
+  } CLK_CTRL;
+  __IM  uint32_t  RESERVED8[7];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x000002A0) * ACCESS_CODE *                                            */
+
+    struct {
+      __IOM uint32_t ACCESS_CODE : 8;           /*!< [7..0] 按照顺序写入'0x55->0xaa->0x17'
+                                                     来设置或者清除 'access_en'                                         */
+    } bit;
+  } ACCESS_CODE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x000002A4) * ACCESS_EN *                                              */
+
+    struct {
+      __IOM uint32_t ACCESS_EN  : 1;            /*!< [0..0] 这1bit 只能在ACCESS_CODE设置后写
+                                                     入
+                                                     1: 打开LPM寄存器写入权限
+                                                     0: 关闭LPM寄存器写入权限
+                                                     注：每次退出深度睡眠后,access_code和acce
+                                                     ss_en会自动清0,必须重新使能                                     */
+    } bit;
+  } ACCESS_EN;
+  __IM  uint32_t  RESERVED9[22];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000300) * BAKEUP_REG0 *                                            */
+
+    struct {
+      __IOM uint32_t REG        : 32;           /*!< [31..0] 复位值是0x5555_5555                                           */
+    } bit;
+  } BAKEUP_REG0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000304) * BAKEUP_REG1 *                                            */
+
+    struct {
+      __IOM uint32_t REG        : 32;           /*!< [31..0] 复位值是0xaaaa_aaaa                                           */
+    } bit;
+  } BAKEUP_REG1;
+  __IM  uint32_t  RESERVED10[6];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000320) * BAKEUP_REG2 *                                            */
+
+    struct {
+      __IOM uint32_t REG        : 32;           /*!< [31..0] 无复位功能寄存器                                          */
+    } bit;
+  } BAKEUP_REG2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000324) * BAKEUP_REG3 *                                            */
+
+    struct {
+      __IOM uint32_t REG        : 32;           /*!< [31..0] 无复位功能寄存器                                          */
+    } bit;
+  } BAKEUP_REG3;
+} MLPM_Type;                                    /*!< Size = 808 (0x328)                                                        */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MBPK                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MBPK (MBPK)
+  */
+
+typedef struct {                                /*!< (@ 0x000FAC00) MBPK Structure                                             */
+  __IOM uint32_t  KEY[32];                      /*!< (@ 0x00000000) key                                                        */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000080) * RST *                                                    */
+
+    struct {
+      __OM  uint32_t RESET      : 1;            /*!< [0..0] 写1会复位KEY,BPK的配置,SENSOR的配
+                                                     置。                                                                    */
+    } bit;
+  } RST;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000084) * CLR *                                                    */
+
+    struct {
+      __OM  uint32_t CLR        : 4;            /*!< [3..0] 每一bit控制256-bit 的KEY清除 ,
+                                                     写“1”将清除相应的区域                                        */
+    } bit;
+  } CLR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000088) * LR *                                                     */
+
+    struct {
+      __IOM uint32_t LOCK_READ  : 4;            /*!< [3..0] 每一bit控制256-bit 的KEY的锁定 ,
+                                                     写“1”将锁定读取相应的区域                                  */
+    } bit;
+  } LR;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000008C) * LW *                                                     */
+
+    struct {
+      __IOM uint32_t LOCK_WRITE : 4;            /*!< [3..0] 每一bit控制256-bit 的KEY的锁定 ,
+                                                     写“1”将锁定写入相应的区域                                  */
+    } bit;
+  } LW;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000090) * LOCK *                                                   */
+
+    struct {
+      __IOM uint32_t LOCK_SELF  : 1;            /*!< [0..0] 1:锁定LOCK寄存器本身(通常用于配置好其他的
+                                                     锁定过后,且无法解锁)                                             */
+      __IOM uint32_t LKW_LOCK   : 1;            /*!< [1..1] 1:锁定LOCK_WRITE寄存器                                        */
+      __IOM uint32_t LKR_LOCK   : 1;            /*!< [2..2] 1:锁定LOCK_READ寄存器                                         */
+      __IOM uint32_t CLR_LOCK   : 1;            /*!< [3..3] 1:锁定CLR寄存器                                               */
+      __IOM uint32_t RESET_LOCK : 1;            /*!< [4..4] 1:锁定RESET寄存器                                             */
+    } bit;
+  } LOCK;
+} MBPK_Type;                                    /*!< Size = 148 (0x94)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MSEC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MSEC (MSEC)
+  */
+
+typedef struct {                                /*!< (@ 0x000FAE00) MSEC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * LC *                                                     */
+
+    struct {
+      __IOM uint32_t VAL        : 8;            /*!< [7..0] 仅支持比特置1操作,不支持清0回退
+                                                     0x01: 上电非安全状态
+                                                     其他值：用户自定义                                               */
+    } bit;
+  } LC;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * LOCK *                                                   */
+
+    struct {
+      __IOM uint32_t LOCK_SELF  : 1;            /*!< [0..0] 1:锁定LOCK寄存器本身(通常用于配置好其他的
+                                                     锁定过后,且无法解锁)                                             */
+      __IOM uint32_t ACTION     : 1;            /*!< [1..1] 1:锁定 ALERT_ACTION寄存器                                     */
+      __IOM uint32_t TAMPER     : 1;            /*!< [2..2] 1:锁定TAMP_EN/TAMP_CTRL/TA
+                                                     MP_STA_CTRL/TAMP_DYN_CTRL寄存器                                        */
+      __IOM uint32_t SENSOR     : 1;            /*!< [3..3] 1:锁定SENSOR_EN/SENSOR_CTR
+                                                     L/SENSOR_THRES寄存器                                                   */
+      __IOM uint32_t SHIELD     : 1;            /*!< [4..4] 1:锁定SHIELD_EN/SHIELD_CTR
+                                                     L寄存器                                                                */
+    } bit;
+  } LOCK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * ALERT_FILT *                                             */
+
+    struct {
+      __IM  uint32_t CNT        : 4;            /*!< [3..0] 当TAMPER/SENSOR/SHIELD的报警
+                                                     发生时cnt寄存器会加1                                              */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t THOLD      : 4;            /*!< [11..8] 当THOLD的配置大于等于CNT的值的时候会触发
+                                                     ALERT_ACTION                                                              */
+      __IM  uint32_t            : 4;
+      __OM  uint32_t CNT_CLR    : 1;            /*!< [16..16] 写1 清除CNT寄存器的是值                                 */
+    } bit;
+  } ALERT_FILT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * ALERT_ACTION *                                           */
+
+    struct {
+      __IOM uint32_t CLEAR_KEY  : 4;            /*!< [3..0] 当ALERT_ACTION发生时,除了该寄存器配
+                                                     置成0x5能失能清除秘钥动作,其他配置都会导致清除秘钥
+                                                                                                                               */
+      __IM  uint32_t            : 12;
+      __IOM uint32_t RESET_SYSTEM : 4;          /*!< [19..16] 当ALERT_ACTION发生时,除了该寄存器配
+                                                     置成0x5能失能复位系统动作,其他配置都会导致复位系统
+                                                                                                                               */
+    } bit;
+  } ALERT_ACTION;
+  __IM  uint32_t  RESERVED[4];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * SOFT_ATTACK_EN *                                         */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] 置‘1’后无法清0
+                                                     1: 使能soft_attack功能                                                */
+    } bit;
+  } SOFT_ATTACK_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * SOFT_ATTACK_LOCK *                                       */
+
+    struct {
+      __IOM uint32_t LOCK       : 1;            /*!< [0..0] 软件攻击锁定
+                                                     0: 解锁 soft attack
+                                                     1: 锁定 soft attack
+                                                     注：写此寄存器可置1和清0,写其他任意寄存器,此寄存器
+                                                     ��
+                                                     置1                                                                      */
+    } bit;
+  } SOFT_ATTACK_LOCK;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * SOFT_ATTACK *                                            */
+
+    struct {
+      __OM  uint32_t TRIGGER    : 1;            /*!< [0..0] 写1触发软件攻击
+                                                     注：必须先写soft_attack_lock为0,再写此
+                                                     寄存器,中间不能插入其他寄存器读写操作                   */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t TYPE       : 4;            /*!< [7..4] soft_attack位检测到1时,锁存写数据的
+                                                     比特7到4                                                               */
+    } bit;
+  } SOFT_ATTACK;
+  __IM  uint32_t  RESERVED1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000030) * IE *                                                     */
+
+    struct {
+      __IOM uint32_t TAMPER     : 1;            /*!< [0..0] 1:使能TAMPER触发中断                                         */
+      __IOM uint32_t SENSOR     : 1;            /*!< [1..1] 1:使能SENSOR触发中断                                         */
+      __IOM uint32_t SHIELD     : 1;            /*!< [2..2] 1:使能SHIELD触发中断                                         */
+      __IOM uint32_t SOFT_ATTACK : 1;           /*!< [3..3] 1:使能soft attact触发中断                                    */
+      __IOM uint32_t KEY_CLEAR  : 1;            /*!< [4..4] 1:使能清除秘钥触发中断                                   */
+    } bit;
+  } IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000034) * IRQ *                                                    */
+
+    struct {
+      __IOM uint32_t TAMPER     : 1;            /*!< [0..0] 写‘1’清除TAMPER中断状态                                 */
+      __IOM uint32_t SENSOR     : 1;            /*!< [1..1] 写‘1’清除SENSOR中断状态                                 */
+      __IOM uint32_t SHIELD     : 1;            /*!< [2..2] 写‘1’清除SHIELD中断状态                                 */
+      __IOM uint32_t SOFT_ATTACK : 1;           /*!< [3..3] 写‘1’清除SOFT_ATTACK中断状态                            */
+      __IOM uint32_t KEY_CLEAR  : 1;            /*!< [4..4] 写‘1’清除KEY_CLEAR中断状态                              */
+    } bit;
+  } IRQ;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000038) * STATUS *                                                 */
+
+    struct {
+      __IM  uint32_t TAMP_ALARM : 8;            /*!< [7..0] TAMPER中断状态,每1BIT代表一个TAMP
+                                                     ER触发中断                                                            */
+      __IM  uint32_t SENSOR_ALARM : 1;          /*!< [8..8] SENSOR中断状态                                                 */
+      __IM  uint32_t            : 7;
+      __IM  uint32_t SHIELD_ALARM : 1;          /*!< [16..16] SHIELD中断状态                                               */
+      __IM  uint32_t SOFT_ATTACK : 1;           /*!< [17..17] 软件攻击中断状态                                         */
+      __IM  uint32_t KEY_CLEAR  : 1;            /*!< [18..18] 清除秘钥中断状态                                         */
+    } bit;
+  } STATUS;
+  __IM  uint32_t  RESERVED2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) * TAMP_EN *                                                */
+
+    struct {
+      __IOM uint32_t TAMP_0     : 4;            /*!< [3..0] TAMPER0 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_1     : 4;            /*!< [7..4] TAMPER1 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_2     : 4;            /*!< [11..8] TAMPER2 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_3     : 4;            /*!< [15..12] TAMPER3 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_4     : 4;            /*!< [19..16] TAMPER4 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_5     : 4;            /*!< [23..20] TAMPER5 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_6     : 4;            /*!< [27..24] TAMPER6 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TAMP_7     : 4;            /*!< [31..28] TAMPER7 使能
+                                                     0x5:使能
+                                                     Others:使能                                                             */
+    } bit;
+  } TAMP_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000044) * TAMP_CTRL *                                              */
+
+    struct {
+      __IOM uint32_t MODE       : 4;            /*!< [3..0] TAMPER IO模式(每1BIT控制两个IO,
+                                                     按顺序对应IO0~7)
+                                                     0:静态模式
+                                                     1:动态模式                                                            */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t IE         : 8;            /*!< [15..8] TAMPER IO使能
+                                                     动态模式,输入管脚需要使能IE,输出管脚不需要
+                                                     静态模式,所有管脚均需要使能IE,PULL_AUTO为1
+                                                     时,自动在静态检测期间使能IE,其他时间禁止IE,以减少
+                                                     功耗                                                                    */
+      __IOM uint32_t PD_EN      : 8;            /*!< [23..16] TAMPER IO下拉使能(每1BIT对应控制一
+                                                     个 TAMPER IO)
+                                                     动态模式:需要把输入脚上拉或下拉
+                                                     静态模式:把对应IO下拉,PULL_AUTO为1时,自动
+                                                     在静态检测期间使能下拉,其他时间禁止下拉,以减少功�
+                                                                                                                               */
+      __IOM uint32_t PU_EN      : 8;            /*!< [31..24] TAMPER IO上拉使能(每1BIT对应控制一
+                                                     个 TAMPER IO)
+                                                     动态模式:需要把输入脚上拉或下拉
+                                                     静态模式:把对应IO上拉,PULL_AUTO为1时,自动
+                                                     在静态检测期间使能上拉,其他时间禁止上拉,以减少功�
+
+                                                     注：Tamper IO 上电默认开启上拉,每个IO上拉或
+                                                     下拉只能选择一个                                                  */
+    } bit;
+  } TAMP_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) * TAMP_STA_CTRL *                                          */
+
+    struct {
+      __IOM uint32_t PERIOD     : 2;            /*!< [1..0] 静态检测周期
+                                                     0: 32ms
+                                                     1: 125ms
+                                                     2: 500ms
+                                                     3: 0.9999s                                                                */
+      __IOM uint32_t CHK_WIN    : 2;            /*!< [3..2] 窗口内采样过滤选择
+                                                     0: 窗口内进行一次采样,一次采样成功即触发窗口报警
+                                                     1: 窗口内进行两次采样,连续两次采样成功即触发窗口报
+                                                     ��
+                                                     2: 窗口内进行三次采样,连续三次采样成功即触发窗口报
+                                                     ��
+                                                     3: 窗口内进行四次采样,连续四次采样成功即触发窗口报
+                                                     ��                                                                        */
+      __IOM uint32_t FILT_WIN   : 2;            /*!< [5..4] 静态检测窗口报警过滤选择
+                                                     0: 一个窗口检测到报警即为报警
+                                                     1: 连续两个窗口检测到报警即为报警
+                                                     2: 连续三个窗口检测到报警即为报警
+                                                     3: 连续四个窗口检测到报警即为报警                          */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PROT_EN    : 1;            /*!< [8..8] 静态报警触发后,IO是否启动自动保护
+                                                     0: 不开启 ,继续进行检测
+                                                     1: 开启 ,停止检测,进入保护模式,保护模式由PROT
+                                                     _MODE确定                                                               */
+      __IOM uint32_t PROT_MODE  : 1;            /*!< [9..9] 静态报警触发后,保护模式选择
+                                                     0: 引脚处于高阻状态
+                                                     1: 引脚自动上下拉（取决于外部电平）                       */
+      __IOM uint32_t PULL_AUTO  : 1;            /*!< [10..10] 0: 静态上下拉由软件控制
+                                                     1: 静态上下拉只在配置工作期间有效,由硬件自动控制    */
+      __IM  uint32_t            : 9;
+      __IOM uint32_t CHK_GAP    : 2;            /*!< [21..20] 静态检测间隔
+                                                     0: 1ms
+                                                     1: 2ms
+                                                     2: 4ms
+                                                     3: 8ms                                                                    */
+      __IOM uint32_t CHK_DLY    : 2;            /*!< [23..22] 静态上下拉开启后,延迟多长时间后进行检测
+                                                     0: 1ms
+                                                     1: 4ms
+                                                     2: 8ms
+                                                     3: 16ms                                                                   */
+      __IOM uint32_t ALERT_LEVEL : 8;           /*!< [31..24] 分别对应8个引脚的静态报警电平
+                                                     0: 低电平报警
+                                                     1: 高电平报警                                                        */
+    } bit;
+  } TAMP_STA_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) * TAMP_DYN_CTRL *                                          */
+
+    struct {
+      __IOM uint32_t PERIOD     : 2;            /*!< [1..0] 动态检测周期
+                                                     0: 32ms
+                                                     1: 125ms
+                                                     2: 500ms
+                                                     3: 0.9999s                                                                */
+      __IOM uint32_t CHK_WIN    : 2;            /*!< [3..2] 窗口内采样过滤选择
+                                                     0: 窗口内进行一次采样,一次采样成功即触发窗口报警
+                                                     1: 窗口内进行两次采样,连续两次采样成功即触发窗口报
+                                                     ��
+                                                     2: 窗口内进行三次采样,连续三次采样成功即触发窗口报
+                                                     ��
+                                                     3: 窗口内进行四次采样,连续四次采样成功即触发窗口报
+                                                     ��                                                                        */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t PROT_EN    : 1;            /*!< [8..8] 动态报警触发后,IO是否启动自动保护
+                                                     0: 不开启
+                                                     1: 开启 ,保护模式由PROT_MODE确定                                 */
+      __IOM uint32_t PROT_MODE  : 1;            /*!< [9..9] 动态报警触发后,保护模式选择
+                                                     0: 引脚处于高阻状态
+                                                     1: 引脚自动上下拉（取决于外部电平）                       */
+    } bit;
+  } TAMP_DYN_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000050) * TAMP_IO_STATUS *                                         */
+
+    struct {
+      __IM  uint32_t IE         : 8;            /*!< [7..0] IO IE状态                                                        */
+      __IM  uint32_t OEN        : 8;            /*!< [15..8] IO使能状态                                                    */
+      __IM  uint32_t PD         : 8;            /*!< [23..16] IO下拉状态                                                   */
+      __IM  uint32_t PU         : 8;            /*!< [31..24] IO上拉状态                                                   */
+    } bit;
+  } TAMP_IO_STATUS;
+  __IM  uint32_t  RESERVED3[11];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000080) * SENSOR_EN *                                              */
+
+    struct {
+      __IOM uint32_t VBUT_1_2_EN : 4;           /*!< [3..0] 纽扣电池1.2V输出电压传感器使能:
+                                                     0x5:失能
+                                                     Others:使能                                                             */
+      __IOM uint32_t VBUT_3_3_EN : 4;           /*!< [7..4] 纽扣电池3.3V输入电压传感器使能:
+                                                     0x5:失能
+                                                     Others:使能                                                             */
+      __IOM uint32_t TEMP_EN    : 4;            /*!< [11..8] 温度传感器使能:
+                                                     0x5:失能
+                                                     Others:使能                                                             */
+    } bit;
+  } SENSOR_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000084) * SENSOR_CTRL *                                            */
+
+    struct {
+      __IM  uint32_t            : 16;
+      __IOM uint32_t DUR        : 2;            /*!< [17..16] Sensor检测时间长度。
+                                                     00: always on
+                                                     01: 2ms
+                                                     10: 8ms
+                                                     11: 16ms                                                                  */
+      __IOM uint32_t DELAY      : 2;            /*!< [19..18] 警报持续时间门限,大于门限的信号,将触发报警。用
+                                                     于滤除毛刺,防止虚警。
+                                                     00: 1*(1/32k)=31.25us
+                                                     01: 8*(1/32k)=250us
+                                                     10: 32*(1/32k)=1ms
+                                                     11: 128*(1/32k)=4ms
+                                                     注：这个时间必须小于sensor_duration时间                       */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t CHK_EN     : 5;            /*!< [28..24] 传感器检测使能
+                                                     [4]: 低温检测使能
+                                                     [3]: 高温检测使能
+                                                     [2]: 纽扣电池3.3v输出低压检测使能
+                                                     [1]: 纽扣电池3.3v输出高压检测使能
+                                                     [0]: 纽扣电池1.2v输出低压检测使能                             */
+    } bit;
+  } SENSOR_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000088) * SENSOR_THRES *                                           */
+
+    struct {
+      __IOM uint32_t DVDDLPM_L  : 4;            /*!< [3..0] 纽扣电池1.2V输出电压低报警设置
+                                                     报警值等于 0.83+DVDDLPM_L*0.02                                       */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t VBUT_L     : 4;            /*!< [11..8] 纽扣电池3.3V输入电压低报警设置
+                                                     0000: 1.938
+                                                     0001: 1.971
+                                                     0010: 2.005
+                                                     0011: 2.040
+                                                     0100: 2.076
+                                                     0101: 2.113
+                                                     0110: 2.152
+                                                     0111: 2.193
+                                                     1000: 2.235
+                                                     1001: 2.278
+                                                     1010: 2.324
+                                                     1011: 2.371
+                                                     1100: 2.420
+                                                     1101: 2.471
+                                                     1110: 2.525
+                                                     1111: 2.580                                                               */
+      __IOM uint32_t VBUT_H     : 4;            /*!< [15..12] 纽扣电池3.3V输入电压高报警设置
+                                                     0000: 3.471
+                                                     0001: 3.577
+                                                     0010: 3.690
+                                                     0011: 3.810
+                                                     0100: 3.938
+                                                     0101: 4.076
+                                                     0110: 4.223
+                                                     0111: 4.381
+                                                     1000: 4.552
+                                                     1001: 4.736
+                                                     1010: 4.936
+                                                     1011: 5.154
+                                                     1100: 5.392
+                                                     1101: 5.653
+                                                     1110: 5.926
+                                                     1111: 6.115                                                               */
+      __IOM uint32_t TS_UTC     : 3;            /*!< [18..16] 低温报警温度设置
+                                                     0: -40
+                                                     1: -35
+                                                     2: -30
+                                                     3: -25
+                                                     4: -20                                                                    */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t TS_OTC     : 3;            /*!< [22..20] 高温报警温度设置
+                                                     0: 85
+                                                     1: 90
+                                                     2: 95
+                                                     3: 100
+                                                     4: 105                                                                    */
+    } bit;
+  } SENSOR_THRES;
+  __IM  uint32_t  RESERVED4[13];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x000000C0) * SHIELD_EN *                                              */
+
+    struct {
+      __IOM uint32_t EN_0       : 4;            /*!< [3..0] SHIELD 0使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_1       : 4;            /*!< [7..4] SHIELD 1使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_2       : 4;            /*!< [11..8] SHIELD 2使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_3       : 4;            /*!< [15..12] SHIELD 3使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_4       : 4;            /*!< [19..16] SHIELD 4使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_5       : 4;            /*!< [23..20] SHIELD 5使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_6       : 4;            /*!< [27..24] SHIELD 6使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+      __IOM uint32_t EN_7       : 4;            /*!< [31..28] SHIELD 7使能
+                                                     0x5 :失能
+                                                     Others: 使能                                                            */
+    } bit;
+  } SHIELD_EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x000000C4) * SHIELD_CTRL *                                            */
+
+    struct {
+      __IOM uint32_t PERIOD     : 2;            /*!< [1..0] Shield工作周期
+                                                     0: 32ms
+                                                     1: 125ms
+                                                     2: 500ms
+                                                     3: 0.9999s                                                                */
+      __IM  uint32_t            : 6;
+      __IOM uint32_t CHK_WIN    : 2;            /*!< [9..8] 窗口内采样过滤选择
+                                                     0: 窗口内进行一次采样,一次采样成功即触发窗口报警
+                                                     1: 窗口内进行两次采样,连续两次采样成功即触发窗口报
+                                                     ��
+                                                     2: 窗口内进行三次采样,连续三次采样成功即触发窗口报
+                                                     ��
+                                                     3: 窗口内进行四次采样,连续四次采样成功即触发窗口报
+                                                     ��                                                                        */
+    } bit;
+  } SHIELD_CTRL;
+} MSEC_Type;                                    /*!< Size = 200 (0xc8)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MRTC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MRTC (MRTC)
+  */
+
+typedef struct {                                /*!< (@ 0x000FAF00) MRTC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * EN *                                                     */
+
+    struct {
+      __IOM uint32_t VAL        : 1;            /*!< [0..0] 1: 使能RTC 0:失能RTC                                           */
+    } bit;
+  } EN;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * SEC_CNT *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 16;           /*!< [15..0] 设置一秒校准值                                             */
+    } bit;
+  } SEC_CNT;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * IE *                                                     */
+
+    struct {
+      __IOM uint32_t SEC        : 1;            /*!< [0..0] 1: 允许秒中断 0:禁止秒中断                               */
+      __IOM uint32_t ALARM      : 1;            /*!< [1..1] 1: 允许闹钟中断 0:禁止闹钟中断                         */
+    } bit;
+  } IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * IRQ_STATUS *                                             */
+
+    struct {
+      __IOM uint32_t SEC        : 1;            /*!< [0..0] 1: 秒中断,scnd_ie为0时也会置位,但不
+                                                     会触发中断                                                           */
+      __IOM uint32_t ALARM      : 1;            /*!< [1..1] 1: 闹钟中断,clk_alm_ie为0时也会置
+                                                     位,但不会触发中断                                                 */
+    } bit;
+  } IRQ_STATUS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * ALARM *                                                  */
+
+    struct {
+      __IOM uint32_t IRQPREVAL  : 32;           /*!< [31..0] 闹钟中断预设值                                             */
+    } bit;
+  } ALARM;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * TIME *                                                   */
+
+    struct {
+      __IOM uint32_t VAL        : 32;           /*!< [31..0] 读操作读取当前RTC计数器值
+                                                     写操作改写当前RTC计数器值,仅支持32-bit操作                */
+    } bit;
+  } TIME;
+} MRTC_Type;                                    /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           MADC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MADC (MADC)
+  */
+
+typedef struct {                                /*!< (@ 0x000FBB00) MADC Structure                                             */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * CTRL1 *                                                  */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] adc模块数字开关
+                                                     0: 失能ADC模块
+                                                     1: 使能ADC模块                                                        */
+      __IOM uint32_t AWD_EN     : 1;            /*!< [1..1] ADC看门狗使能,ADC采样值超过看门狗门限时会
+                                                     触发ADC看门狗中断
+                                                     0::失能
+                                                     1::使能                                                                 */
+      __IOM uint32_t SAMP_EDGE  : 1;            /*!< [2..2] ADC采样边沿选择
+                                                     0:下降沿采样
+                                                     1: 上升沿采样                                                        */
+    } bit;
+  } CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * CTRL2 *                                                  */
+
+    struct {
+      __OM  uint32_t SGL_START  : 1;            /*!< [0..0] 软件写'1',启动一次ADC采(仅在SAMP_M
+                                                     ODE为0时生效)                                                         */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t SAMP_MODE  : 1;            /*!< [8..8] 采样模式
+                                                     0:单次采样模式
+                                                     1:连续采样模式                                                      */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t TRIG_EN    : 9;            /*!< [24..16] 定时器溢出触发ADC采样(仅适用于单次采样模式)
+                                                     0:失能
+                                                     1:使能                                                                  */
+    } bit;
+  } CTRL2;
+  __IM  uint32_t  RESERVED[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * IE *                                                     */
+
+    struct {
+      __IOM uint32_t DONE       : 1;            /*!< [0..0] 采样结束中断使能
+                                                     0:失能
+                                                     1.使能                                                                  */
+      __IOM uint32_t FIFO_OVER  : 1;            /*!< [1..1] FIFO数据超过FIFO_LIMIT中断使能
+                                                     0:失能
+                                                     1.使能                                                                  */
+      __IOM uint32_t FIFO_FULL  : 1;            /*!< [2..2] FIFO数据溢出中断使能
+                                                     0:失能
+                                                     1.使能                                                                  */
+      __IOM uint32_t AWD        : 1;            /*!< [3..3] ADC看门狗中断使能
+                                                     0:失能
+                                                     1.使能                                                                  */
+    } bit;
+  } IE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * STATUS *                                                 */
+
+    struct {
+      __IOM uint32_t DONE       : 1;            /*!< [0..0] 采样结束中断状态,写1清除中断                          */
+      __IOM uint32_t FIFO_OVER  : 1;            /*!< [1..1] FIFO数据超过FIFO_LIMIT中断状态,写
+                                                     1清除中断                                                             */
+      __IOM uint32_t FIFO_FULL  : 1;            /*!< [2..2] FIFO数据溢出中断状态,写1清除中断                      */
+      __IOM uint32_t AWD        : 1;            /*!< [3..3] ADC看门狗中断状态,写1清除中断                          */
+    } bit;
+  } STATUS;
+  __IM  uint32_t  RESERVED1[2];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * FIFO_CTRL *                                              */
+
+    struct {
+      __IOM uint32_t LIMIT      : 5;            /*!< [4..0] 当LIMIT>0,且ITEMS>=LIMIT时触
+                                                     发FIFO_OVER中断                                                        */
+      __IM  uint32_t            : 3;
+      __IM  uint32_t ITEMS      : 5;            /*!< [12..8] FIFO中的有效数据量                                         */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t RST        : 1;            /*!< [16..16] ADC FIFO复位                                                   */
+      __IOM uint32_t EN         : 1;            /*!< [17..17] ADC FIFO使能
+                                                     1:ADC数据有效转换值会写入FIFO
+                                                     0:ADC数据有效转换值不会写入FIFO                                */
+    } bit;
+  } FIFO_CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * FIFO *                                                   */
+
+    struct {
+      __IM  uint32_t DATA       : 13;           /*!< [12..0] 使用FIFO时的ADC取数寄存器(未使能电压转换
+                                                     功能时,读到的为原始AD值;使能电压转换功能时,读到的�
+
+                                                     电压值的二进制补码,单位为mv)                                  */
+    } bit;
+  } FIFO;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * DATA *                                                   */
+
+    struct {
+      __IM  uint32_t VAL        : 13;           /*!< [12..0] 不使用FIFO时的ADC取数寄存器(未使能电压转
+                                                     换功能时,读到的为原始AD值;使能电压转换功能时,读到�
+
+                                                     为电压值的二进制补码,单位为mv)                               */
+    } bit;
+  } DATA;
+  __IM  uint32_t  RESERVED2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000030) * AWD *                                                    */
+
+    struct {
+      __IOM uint32_t LOW_LIMIT  : 13;           /*!< [12..0] ADC看门狗的低阈值(使能电压转换时,需同时启用
+                                                     负电压归零功能才能使用ADC看门狗功能)                      */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t HIGH_LIMIT : 13;           /*!< [28..16] ADC看门狗的高阈值(使能电压转换时,需同时启用
+                                                     负电压归零功能才能使用ADC看门狗功能)                      */
+    } bit;
+  } AWD;
+  __IM  uint32_t  RESERVED3[3];
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) * REF_AD *                                                 */
+
+    struct {
+      __IOM uint32_t VAL        : 10;           /*!< [9..0] 基准电压AD值                                                  */
+    } bit;
+  } REF_AD;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000044) * REF_VOL *                                                */
+
+    struct {
+      __IOM uint32_t VAL        : 13;           /*!< [12..0] 基准电压(mV)                                                  */
+    } bit;
+  } REF_VOL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) * SLOPE *                                                  */
+
+    struct {
+      __IOM uint32_t VAL        : 10;           /*!< [9..0] 电压转换斜率((vol_high-vol_low
+                                                     )/(vol_high_ref-vol_low_ref)
+                                                     )*64计算得到的10-bit整数值                                        */
+    } bit;
+  } SLOPE;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) * CONVERT_CTRL *                                           */
+
+    struct {
+      __IOM uint32_t EN         : 1;            /*!< [0..0] 电压转换功能开关
+                                                     1: 使能电压转换
+                                                     0: 失能电压转换(输出原始ADC采样值)                           */
+      __IOM uint32_t NEG_ZERO   : 1;            /*!< [1..1] 负电压归零控制(写1时,负电压以0V输出)                */
+    } bit;
+  } CONVERT_CTRL;
+} MADC_Type;                                    /*!< Size = 80 (0x50)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                         MISO7811                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief MISO7811 (MISO7811)
+  */
+
+typedef struct {                                /*!< (@ 0x000F8F00) MISO7811 Structure                                         */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) * BASE_ADDR_T1 *                                           */
+
+    struct {
+      __IOM uint32_t ISO_BASE_ADDR : 20;        /*!< [19..0] Character write base add
+                                                     ress for track 1                                                          */
+    } bit;
+  } BASE_ADDR_T1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) * BASE_ADDR_T2 *                                           */
+
+    struct {
+      __IOM uint32_t ISO_BASE_ADDR : 20;        /*!< [19..0] Character write base add
+                                                     ress for track 2                                                          */
+    } bit;
+  } BASE_ADDR_T2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) * BASE_ADDR_T3 *                                           */
+
+    struct {
+      __IOM uint32_t ISO_BASE_ADDR : 20;        /*!< [19..0] Character write base add
+                                                     ress for track 3                                                          */
+    } bit;
+  } BASE_ADDR_T3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) * CTRL *                                                   */
+
+    struct {
+      __IOM uint32_t RX_EN      : 1;            /*!< [0..0] 7811 decoder enable                                                */
+      __IOM uint32_t T1_IRQ_EN  : 1;            /*!< [1..1] 7811 track 1 interrupt
+                                                     enable                                                                    */
+      __IOM uint32_t T1_CLR_IRQ : 1;            /*!< [2..2] Clear 7811 track 1 inter
+                                                     rupt                                                                      */
+      __IOM uint32_t T2_IRQ_EN  : 1;            /*!< [3..3] 7811 track 2 interrupt
+                                                     enable                                                                    */
+      __IOM uint32_t T2_CLR_IRQ : 1;            /*!< [4..4] Clear 7811 track 2 inter
+                                                     rupt                                                                      */
+      __IOM uint32_t T3_IRQ_EN  : 1;            /*!< [5..5] 7811 track 3 interrupt
+                                                     enable                                                                    */
+      __IOM uint32_t T3_CLR_IRQ : 1;            /*!< [6..6] Clear 7811 track 3 inter
+                                                     rupt                                                                      */
+      __IOM uint32_t SOFT_RESET : 1;            /*!< [7..7] soft reset for AHB bus c
+                                                     ontrol                                                                    */
+      __IOM uint32_t TIMER_EN   : 1;            /*!< [8..8] Timer enable                                                       */
+      __IOM uint32_t TIMER_IRQ_EN : 1;          /*!< [9..9] 7811 timer interrupt ena
+                                                     ble                                                                       */
+      __IOM uint32_t TIMER_CLR_IRQ : 1;         /*!< [10..10] Clear 7811 timer interru
+                                                     pt                                                                        */
+      __IOM uint32_t T1_DC_CANCEL_EN : 1;       /*!< [11..11] Enable DC cancellation f
+                                                     or track 1                                                                */
+      __IOM uint32_t T1_DC_CALC_WIN : 2;        /*!< [13..12] DC calculation window co
+                                                     nfiguration for track 1                                                   */
+      __IOM uint32_t T2_DC_CANCEL_EN : 1;       /*!< [14..14] Enable DC cancellation f
+                                                     or track 2                                                                */
+      __IOM uint32_t T2_DC_CALC_WIN : 2;        /*!< [16..15] DC calculation window co
+                                                     nfiguration for track 2                                                   */
+      __IOM uint32_t T3_DC_CANCEL_EN : 1;       /*!< [17..17] Enable DC cancellation f
+                                                     or track 3                                                                */
+      __IOM uint32_t T3_DC_CALC_WIN : 2;        /*!< [19..18] DC calculation window co
+                                                     nfiguration for track 3                                                   */
+      __IOM uint32_t T1_CHANNEL_SEL : 2;        /*!< [21..20] Channel select signal fo
+                                                     r track 1                                                                 */
+      __IOM uint32_t T2_CHANNEL_SEL : 2;        /*!< [23..22] Channel select signal fo
+                                                     r track 2                                                                 */
+      __IOM uint32_t T3_CHANNEL_SEL : 2;        /*!< [25..24] Channel select signal fo
+                                                     r track 3                                                                 */
+      __IOM uint32_t T1_BUFFULL_IRQ_EN : 1;     /*!< [26..26] 7811 track 1 buffer full
+                                                     interrupt enable                                                          */
+      __IOM uint32_t T1_BUFFULL_CLR_IRQ : 1;    /*!< [27..27] Clear 7811 track 1 buffe
+                                                     r full interrupt                                                          */
+      __IOM uint32_t T2_BUFFULL_IRQ_EN : 1;     /*!< [28..28] 7811 track 2 buffer full
+                                                     interrupt enable                                                          */
+      __IOM uint32_t T2_BUFFULL_CLR_IRQ : 1;    /*!< [29..29] Clear 7811 track 2 buffe
+                                                     r full interrupt                                                          */
+      __IOM uint32_t T3_BUFFULL_IRQ_EN : 1;     /*!< [30..30] 7811 track 3 buffer full
+                                                     interrupt enable                                                          */
+      __IOM uint32_t T3_BUFFULL_CLR_IRQ : 1;    /*!< [31..31] Clear 7811 track 3 buffe
+                                                     r full interrupt                                                          */
+    } bit;
+  } CTRL;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) * T1_PEAK_VALUE_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 9;            /*!< [8..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IOM uint32_t ALPHA      : 4;            /*!< [12..9] Coefficient for peak val
+                                                     ue update IIR filter                                                      */
+      __IOM uint32_t THLD_RATIO : 4;            /*!< [16..13] Peak value threshold rat
+                                                     io                                                                        */
+    } bit;
+  } T1_PEAK_VALUE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) * T1_PEAK_WIDTH_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 15;           /*!< [14..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t UPDATA_RATIO1 : 4;         /*!< [19..16] Pulse width update ratio
+                                                     1                                                                         */
+      __IOM uint32_t UPDATA_RATIO2 : 4;         /*!< [23..20] Pulse width update ratio
+                                                     2                                                                         */
+      __IOM uint32_t UPDATA_RATIO3 : 4;         /*!< [27..24] Pulse width update ratio
+                                                     3                                                                         */
+      __IOM uint32_t UPDATA_RATIO4 : 4;         /*!< [31..28] Pulse width update ratio
+                                                     4                                                                         */
+    } bit;
+  } T1_PEAK_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) * T1_PULSE_WIDTH_CFG *                                     */
+
+    struct {
+      __IOM uint32_t SYNC_ZERO_WIN : 3;         /*!< [2..0] Synchronized zero judgem
+                                                     ent window                                                                */
+      __IOM uint32_t PULSE_WID_MAX : 15;        /*!< [17..3] Maximum pulse width valu
+                                                     e                                                                         */
+      __IOM uint32_t PULSE_WID_BETA : 4;        /*!< [21..18] Coefficient for pulse wi
+                                                     dth threshold IIR filter                                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PEAK_SEL_RATIO1 : 4;       /*!< [27..24] Pulse width thld ratio1
+                                                     for peak select                                                           */
+      __IOM uint32_t PEAK_SEL_RATIO2 : 4;       /*!< [31..28] Pulse width thld ratio2
+                                                     for peak select                                                           */
+    } bit;
+  } T1_PULSE_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) * T1_DECODE_CFG *                                          */
+
+    struct {
+      __IOM uint32_t RATIO1     : 4;            /*!< [3..0] Pulse width threshold1 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO2     : 4;            /*!< [7..4] Pulse width threshold2 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO3     : 4;            /*!< [11..8] Pulse width threshold3 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO4     : 4;            /*!< [15..12] Pulse width threshold4 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO5     : 4;            /*!< [19..16] Pulse width threshold5 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO6     : 4;            /*!< [23..20] Pulse width threshold6 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO7     : 4;            /*!< [27..24] Pulse width threshold7 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO8     : 4;            /*!< [31..28] Pulse width threshold8 f
+                                                     or decode                                                                 */
+    } bit;
+  } T1_DECODE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000020) * T2_PEAK_VALUE_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 9;            /*!< [8..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IOM uint32_t ALPHA      : 4;            /*!< [12..9] Coefficient for peak val
+                                                     ue update IIR filter                                                      */
+      __IOM uint32_t THLD_RATIO : 4;            /*!< [16..13] Peak value threshold rat
+                                                     io                                                                        */
+    } bit;
+  } T2_PEAK_VALUE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000024) * T2_PEAK_WIDTH_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 15;           /*!< [14..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PULSE_WID_RATIO1 : 4;      /*!< [19..16] Pulse width update ratio
+                                                     1                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO2 : 4;      /*!< [23..20] Pulse width update ratio
+                                                     2                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO3 : 4;      /*!< [27..24] Pulse width update ratio
+                                                     3                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO4 : 4;      /*!< [31..28] Pulse width update ratio
+                                                     4                                                                         */
+    } bit;
+  } T2_PEAK_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000028) * T2_PULSE_WIDTH_CFG *                                     */
+
+    struct {
+      __IOM uint32_t SYNC_ZERO_WIN : 3;         /*!< [2..0] Synchronized zero judgem
+                                                     ent window                                                                */
+      __IOM uint32_t PULSE_WID_MAX : 15;        /*!< [17..3] Maximum pulse width valu
+                                                     e                                                                         */
+      __IOM uint32_t PULSE_WID_BETA : 4;        /*!< [21..18] Coefficient for pulse wi
+                                                     dth threshold IIR filter                                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PEAK_SEL_RATIO1 : 4;       /*!< [27..24] Pulse width thld ratio1
+                                                     for peak select                                                           */
+      __IOM uint32_t PEAK_SEL_RATIO2 : 4;       /*!< [31..28] Pulse width thld ratio2
+                                                     for peak select                                                           */
+    } bit;
+  } T2_PULSE_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) * T2_DECODE_CFG *                                          */
+
+    struct {
+      __IOM uint32_t RATIO1     : 4;            /*!< [3..0] Pulse width threshold1 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO2     : 4;            /*!< [7..4] Pulse width threshold2 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO3     : 4;            /*!< [11..8] Pulse width threshold3 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO4     : 4;            /*!< [15..12] Pulse width threshold4 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO5     : 4;            /*!< [19..16] Pulse width threshold5 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO6     : 4;            /*!< [23..20] Pulse width threshold6 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO7     : 4;            /*!< [27..24] Pulse width threshold7 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO8     : 4;            /*!< [31..28] Pulse width threshold8 f
+                                                     or decode                                                                 */
+    } bit;
+  } T2_DECODE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000030) * T3_PEAK_VALUE_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 9;            /*!< [8..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IOM uint32_t ALPHA      : 4;            /*!< [12..9] Coefficient for peak val
+                                                     ue update IIR filter                                                      */
+      __IOM uint32_t THLD_RATIO : 4;            /*!< [16..13] Peak value threshold rat
+                                                     io                                                                        */
+    } bit;
+  } T3_PEAK_VALUE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000034) * T3_PEAK_WIDTH_CFG *                                      */
+
+    struct {
+      __IOM uint32_t THLD_INIT  : 15;           /*!< [14..0] Initial peak value thres
+                                                     hold                                                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PULSE_WID_RATIO1 : 4;      /*!< [19..16] Pulse width update ratio
+                                                     1                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO2 : 4;      /*!< [23..20] Pulse width update ratio
+                                                     2                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO3 : 4;      /*!< [27..24] Pulse width update ratio
+                                                     3                                                                         */
+      __IOM uint32_t PULSE_WID_RATIO4 : 4;      /*!< [31..28] Pulse width update ratio
+                                                     4                                                                         */
+    } bit;
+  } T3_PEAK_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000038) * T3_PULSE_WIDTH_CFG *                                     */
+
+    struct {
+      __IOM uint32_t SYNC_ZERO_WIN : 3;         /*!< [2..0] Synchronized zero judgem
+                                                     ent window                                                                */
+      __IOM uint32_t PULSE_WID_MAX : 15;        /*!< [17..3] Maximum pulse width valu
+                                                     e                                                                         */
+      __IOM uint32_t PULSE_WID_BETA : 4;        /*!< [21..18] Coefficient for pulse wi
+                                                     dth threshold IIR filter                                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PEAK_SEL_RATIO1 : 4;       /*!< [27..24] Pulse width thld ratio1
+                                                     for peak select                                                           */
+      __IOM uint32_t PEAK_SEL_RATIO2 : 4;       /*!< [31..28] Pulse width thld ratio2
+                                                     for peak select                                                           */
+    } bit;
+  } T3_PULSE_WIDTH_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) * T3_DECODE_CFG *                                          */
+
+    struct {
+      __IOM uint32_t RATIO1     : 4;            /*!< [3..0] Pulse width threshold1 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO2     : 4;            /*!< [7..4] Pulse width threshold2 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO3     : 4;            /*!< [11..8] Pulse width threshold3 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO4     : 4;            /*!< [15..12] Pulse width threshold4 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO5     : 4;            /*!< [19..16] Pulse width threshold5 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO6     : 4;            /*!< [23..20] Pulse width threshold6 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO7     : 4;            /*!< [27..24] Pulse width threshold7 f
+                                                     or decode                                                                 */
+      __IOM uint32_t RATIO8     : 4;            /*!< [31..28] Pulse width threshold8 f
+                                                     or decode                                                                 */
+    } bit;
+  } T3_DECODE_CFG;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000040) * STATUS *                                                 */
+
+    struct {
+      __IM  uint32_t T1_WR_DONE : 1;            /*!< [0..0] Shared memory write done
+                                                     signal for track1                                                         */
+      __IM  uint32_t T2_WR_DONE : 1;            /*!< [1..1] Shared memory write done
+                                                     signal for track2                                                         */
+      __IM  uint32_t T3_WR_DONE : 1;            /*!< [2..2] Shared memory write done
+                                                     signal for track3                                                         */
+      __IM  uint32_t TIMER_MEET : 1;            /*!< [3..3] Timer meet limit                                                   */
+      __IM  uint32_t T1_BUF_FULL : 1;           /*!< [4..4] Track 1 buffer full                                                */
+      __IM  uint32_t T2_BUF_FULL : 1;           /*!< [5..5] Track 2 buffer full                                                */
+      __IM  uint32_t T3_BUF_FULL : 1;           /*!< [6..6] Track 3 buffer full                                                */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t T1_RX_DONE : 1;            /*!< [8..8] 7811 decoder rx done sig
+                                                     nal for track1                                                            */
+      __IM  uint32_t T2_RX_DONE : 1;            /*!< [9..9] 7811 decoder rx done sig
+                                                     nal for track2                                                            */
+      __IM  uint32_t T3_RX_DONE : 1;            /*!< [10..10] 7811 decoder rx done sig
+                                                     nal for track3                                                            */
+      __IM  uint32_t T1_FIFO_WR_ERR : 1;        /*!< [11..11] Track 1 fifo write error                                         */
+      __IM  uint32_t T2_FIFO_WR_ERR : 1;        /*!< [12..12] Track 2 fifo write error                                         */
+      __IM  uint32_t T3_FIFO_WR_ERR : 1;        /*!< [13..13] Track 3 fifo write error                                         */
+    } bit;
+  } STATUS;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000044) * CHAR_NUM *                                               */
+
+    struct {
+      __IM  uint32_t TRACK1     : 8;            /*!< [7..0] Track 1 character number                                           */
+      __IM  uint32_t TRACK2     : 8;            /*!< [15..8] Track 2 character number                                          */
+      __IM  uint32_t TRACK3     : 8;            /*!< [23..16] Track 3 character number                                         */
+    } bit;
+  } CHAR_NUM;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000048) * INTERFER_CHAR_NUM *                                      */
+
+    struct {
+      __IM  uint32_t TRACK1     : 8;            /*!< [7..0] Track 1 interference cha
+                                                     racter number                                                             */
+      __IM  uint32_t TRACK2     : 8;            /*!< [15..8] Track 2 interference cha
+                                                     racter number                                                             */
+      __IM  uint32_t TRACK3     : 8;            /*!< [23..16] Track 3 interference cha
+                                                     racter number                                                             */
+    } bit;
+  } INTERFER_CHAR_NUM;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) * DC_EST *                                                 */
+
+    struct {
+      __IM  uint32_t TRACK1     : 10;           /*!< [9..0] Track 1 dc value for dco
+                                                     c                                                                         */
+      __IM  uint32_t TRACK2     : 10;           /*!< [19..10] Track 2 dc value for dco
+                                                     c                                                                         */
+      __IM  uint32_t TRACK3     : 10;           /*!< [29..20] Track 3 dc value for dco
+                                                     c                                                                         */
+    } bit;
+  } DC_EST;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000050) * END_ADDR_T1 *                                            */
+
+    struct {
+      __IOM uint32_t ISO_END_ADDR : 20;         /*!< [19..0] Character write end addr
+                                                     ess for track 1                                                           */
+    } bit;
+  } END_ADDR_T1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000054) * END_ADDR_T2 *                                            */
+
+    struct {
+      __IOM uint32_t ISO_END_ADDR : 20;         /*!< [19..0] Character write end addr
+                                                     ess for track 2                                                           */
+    } bit;
+  } END_ADDR_T2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000058) * END_ADDR_T3 *                                            */
+
+    struct {
+      __IOM uint32_t ISO_END_ADDR : 20;         /*!< [19..0] Character write end addr
+                                                     ess for track 3                                                           */
+    } bit;
+  } END_ADDR_T3;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) * TIMER_LIMIT *                                            */
+
+    struct {
+      __IOM uint32_t LIMIT      : 32;           /*!< [31..0] Timer limit for interrup
+                                                     t                                                                         */
+    } bit;
+  } TIMER_LIMIT;
+} MISO7811_Type;                                /*!< Size = 96 (0x60)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                        ANA_LDO_CLK                                        ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ANA_LDO_CLK (ANA_LDO_CLK)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB200) ANA_LDO_CLK Structure                                      */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) LDO control                                                */
+
+    struct {
+      __IOM uint32_t OTP_LDO_VSEL : 3;          /*!< [2..0] OTP ldo25 voitage selction                                         */
+      __IOM uint32_t OTP_LDO_EN : 1;            /*!< [3..3] OTP ldo25 enable                                                   */
+      __IOM uint32_t LDO_CARD_VSEL : 2;         /*!< [5..4] 7816 LDO output voltage select                                     */
+      __IOM uint32_t LDO_CARD_EN : 1;           /*!< [6..6] 7816 LDO enable                                                    */
+      __IOM uint32_t LDO_CARD_OCP_EN : 1;       /*!< [7..7] 7816 LDO over-current protection                                   */
+      __IOM uint32_t LDO_CARD_VTRIM : 3;        /*!< [10..8] 7816 LDO output voltage trim                                      */
+      __IOM uint32_t LDO_CARD_0P33VDD : 1;      /*!< [11..11] 7816 sink LDO for GPIO floating ground pull down                 */
+      __IOM uint32_t LDO_BBPLLVCO_VSEL : 2;     /*!< [13..12] bbpll vco ldo output voltage select                              */
+      __IOM uint32_t LDO_BBPLL_VSEL : 2;        /*!< [15..14] bbpll ldo output voltage select                                  */
+      __IOM uint32_t LDO_IBLOAD_SEL : 1;        /*!< [16..16] bbpll bleed current sel                                          */
+      __IOM uint32_t LDO_HVSEL  : 1;            /*!< [17..17] bbpll ldo high voltage sel                                       */
+      __IOM uint32_t LDO_EN_BBPLL2 : 1;         /*!< [18..18] bbpll2 ldo enable                                                */
+      __IOM uint32_t LDO_EN_BBPLL1 : 1;         /*!< [19..19] bbpll1 ldo enable                                                */
+    } bit;
+  } LDO_CTRL;
+} ANA_LDO_CLK_Type;                             /*!< Size = 4 (0x4)                                                            */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                         ANA_BBPLL                                         ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ANA_BBPLL (ANA_BBPLL)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB210) ANA_BBPLL Structure                                        */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) BBPLL1 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL1_CP_IBSEL : 3;       /*!< [2..0] lcp sel                                                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BBPLL1_CLKGEN_CK48M_WIDTH : 2;/*!< [5..4] pulse width select                                              */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t BBPLL1_CLKGEN_CK48M_SEL : 1;/*!< [8..8] Pulse width select mode enable                                    */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t BBPLL1_CLKGEN_CK48M_DIVN : 7;/*!< [22..16] div_ratio of 48MHz                                             */
+    } bit;
+  } BBPLL1_CTRL0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) BBPLL1 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL1_DIVR_FRAC : 24;     /*!< [23..0] divr of pll                                                       */
+    } bit;
+  } BBPLL1_CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) BBPLL1 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL1_VCO_IBSEL : 2;      /*!< [1..0] Bias current select of vco                                         */
+      __IOM uint32_t BBPLL1_RSTN : 1;           /*!< [2..2] Reset signal of pll                                                */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BBPLL1_LOOPDIV_WIDTH : 2;  /*!< [5..4] Pulse width select                                                 */
+      __IOM uint32_t BBPLL1_LOOPDIV_SEL : 1;    /*!< [6..6] Pulse width select mode enable                                     */
+      __IOM uint32_t BBPLL1_FREFDIV2_SEL : 1;   /*!< [7..7] Reference clk div sel                                              */
+      __IOM uint32_t BBPLL1_EN_VCO : 1;         /*!< [8..8] VCO enable                                                         */
+      __IOM uint32_t BBPLL1_EN_PFDCP : 1;       /*!< [9..9] pfd and chargepump enable                                          */
+      __IOM uint32_t BBPLL1_EN_LOOPDIV : 1;     /*!< [10..10] loopdivider enable                                               */
+      __IOM uint32_t BBPLL1_EN_CLKGEN_CK48M_DIV2 : 1;/*!< [11..11] 48M div2 enable                                             */
+      __IOM uint32_t BBPLL1_EN_CLKGEN_256M : 1; /*!< [12..12] 256M clk_gen enable                                              */
+      __IOM uint32_t BBPLL1_EN_CLKGEN_192M : 1; /*!< [13..13] 192M clk_gen enable                                              */
+      __IOM uint32_t BBPLL1_EN_CLKGEN_48M : 1;  /*!< [14..14] 48M clk_gen enable                                               */
+      __IOM uint32_t BBPLL1_EN_CLKGEN : 1;      /*!< [15..15] clk_gen enable                                                   */
+      __IOM uint32_t BBPLL1_DIVR_INT : 6;       /*!< [21..16] divr of pll                                                      */
+    } bit;
+  } BBPLL1_CTRL2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) BBPLL2 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL2_CP_IBSEL : 3;       /*!< [2..0] lcp sel                                                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BBPLL2_CLKGEN_CK48M_WIDTH : 2;/*!< [5..4] pulse width select                                              */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t BBPLL2_CLKGEN_CK48M_SEL : 1;/*!< [8..8] Pulse width select mode enable                                    */
+      __IM  uint32_t            : 7;
+      __IOM uint32_t BBPLL2_CLKGEN_CK48M_DIVN : 7;/*!< [22..16] div_ratio of 48MHz                                             */
+    } bit;
+  } BBPLL2_CTRL0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000010) BBPLL2 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL2_DIVR_FRAC : 24;     /*!< [23..0] divr of pll                                                       */
+    } bit;
+  } BBPLL2_CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000014) BBPLL2 control                                             */
+
+    struct {
+      __IOM uint32_t BBPLL2_VCO_IBSEL : 2;      /*!< [1..0] Bias current select of vco                                         */
+      __IOM uint32_t BBPLL2_RSTN : 1;           /*!< [2..2] Reset signal of pll                                                */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t BBPLL2_LOOPDIV_WIDTH : 2;  /*!< [5..4] Pulse width select                                                 */
+      __IOM uint32_t BBPLL2_LOOPDIV_SEL : 1;    /*!< [6..6] Pulse width select mode enable                                     */
+      __IOM uint32_t BBPLL2_FREFDIV2_SEL : 1;   /*!< [7..7] Reference clk div sel                                              */
+      __IOM uint32_t BBPLL2_EN_VCO : 1;         /*!< [8..8] VCO enable                                                         */
+      __IOM uint32_t BBPLL2_EN_PFDCP : 1;       /*!< [9..9] pfd and chargepump enable                                          */
+      __IOM uint32_t BBPLL2_EN_LOOPDIV : 1;     /*!< [10..10] loopdivider enable                                               */
+      __IOM uint32_t BBPLL2_EN_CLKGEN_CK48M_DIV2 : 1;/*!< [11..11] 48M div2 enable                                             */
+      __IOM uint32_t BBPLL2_EN_CLKGEN_256M : 1; /*!< [12..12] 256M clk_gen enable                                              */
+      __IOM uint32_t BBPLL2_EN_CLKGEN_192M : 1; /*!< [13..13] 192M clk_gen enable                                              */
+      __IOM uint32_t BBPLL2_EN_CLKGEN_48M : 1;  /*!< [14..14] 48M clk_gen enable                                               */
+      __IOM uint32_t BBPLL2_EN_CLKGEN : 1;      /*!< [15..15] clk_gen enable                                                   */
+      __IOM uint32_t BBPLL2_DIVR_INT : 6;       /*!< [21..16] divr of pll                                                      */
+    } bit;
+  } BBPLL2_CTRL2;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000018) BBPLL control                                              */
+
+    struct {
+      __IOM uint32_t BBPLL_TST_SEL : 3;         /*!< [2..0] pll test select                                                    */
+      __IOM uint32_t BBPLL_TST_EN_VCTRL : 1;    /*!< [3..3] vctrl test enable                                                  */
+      __IOM uint32_t BBPLL_TST_EN_CK : 1;       /*!< [4..4] clk test enable                                                    */
+      __IOM uint32_t BBPLL_TST_EN : 1;          /*!< [5..5] pll test enable                                                    */
+      __IOM uint32_t BBPLL_TST_CKSEL : 1;       /*!< [6..6] clk test select                                                    */
+      __IOM uint32_t BBPLL_PFD_TONSEL : 1;      /*!< [7..7] pfd ton select                                                     */
+      __IOM uint32_t BBPLL_PFD_PWERES_SEL : 2;  /*!< [9..8] Power Res select                                                   */
+      __IOM uint32_t BBPLL_DSM_ORDER_SEL : 1;   /*!< [10..10] DSM mesh order select                                            */
+      __IOM uint32_t BBPLL_DSM_DITHEREN : 1;    /*!< [11..11] DSM dither enable                                                */
+      __IOM uint32_t BBPLL2_PFD_FREF_PHSEL : 1; /*!< [12..12] fref phase select                                                */
+      __IOM uint32_t BBPLL2_PFD_FDIV_PHSEL : 1; /*!< [13..13] fdiv phase select                                                */
+      __IOM uint32_t BBPLL2_DSM_CKSEL : 1;      /*!< [14..14] DSM clk select                                                   */
+      __IOM uint32_t BBPLL2_DSM_CK_PHSEL : 1;   /*!< [15..15] DSM clk phase select                                             */
+      __IOM uint32_t BBPLL1_PFD_FREF_PHSEL : 1; /*!< [16..16] fref phase select                                                */
+      __IOM uint32_t BBPLL1_PFD_FDIV_PHSEL : 1; /*!< [17..17] fdiv phase select                                                */
+      __IOM uint32_t BBPLL1_DSM_CKSEL : 1;      /*!< [18..18] DSM clk select                                                   */
+      __IOM uint32_t BBPLL1_DSM_CK_PHSEL : 1;   /*!< [19..19] DSM clk phase select                                             */
+      __IOM uint32_t BBPLL_CKIN_SEL : 2;        /*!< [21..20] PLL clk input select                                             */
+      __IOM uint32_t RG_BBPLL_CLKGEN_PWERES_SEL : 2;/*!< [23..22] Power Res select                                             */
+    } bit;
+  } BBPLL_CTRL;
+} ANA_BBPLL_Type;                               /*!< Size = 28 (0x1c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          ANA_MCR                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ANA_MCR (ANA_MCR)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB230) ANA_MCR Structure                                          */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) MCR control                                                */
+
+    struct {
+      __IM  uint32_t            : 9;
+      __IOM uint32_t ADC_CLK_EN : 1;            /*!< [9..9] MCR ADC clock enable                                               */
+      __IOM uint32_t ADC_EN     : 1;            /*!< [10..10] MCR ADC enable                                                   */
+      __IOM uint32_t ADC_EN_BIASGEN : 1;        /*!< [11..11] MCR ADC reference voltage enable                                 */
+      __IOM uint32_t ADC_EN_CONSTGM : 1;        /*!< [12..12] MCR ADC constant Gm bias enable                                  */
+      __IOM uint32_t ADC_EN_REG : 1;            /*!< [13..13] MCR ADC regulator enable                                         */
+      __IOM uint32_t ADC_CLKSEL : 2;            /*!< [15..14] MCR ADC clock select                                             */
+      __IOM uint32_t DCOC_PGA0  : 6;            /*!< [21..16] MCR CH0 PGA DCOC DAC input                                       */
+      __IOM uint32_t ADC_REFBUF_VREF : 2;       /*!< [23..22] MCR ADC differential reference voltage control                   */
+      __IOM uint32_t DCOC_PGA1  : 6;            /*!< [29..24] MCR CH1 PGA DCOC DAC input                                       */
+      __IOM uint32_t ADC_REGA_VCTRL : 2;        /*!< [31..30] MCR ADC analog regulator output voltage control                  */
+    } bit;
+  } CTRL0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) MCR control                                                */
+
+    struct {
+      __IOM uint32_t DCOC_PGA2  : 6;            /*!< [5..0] MCR CH2 PGA DCOC DAC input                                         */
+      __IOM uint32_t ADC_REGD_VCTRL : 2;        /*!< [7..6] MCR ADC digital regulator output voltage control                   */
+      __IOM uint32_t ADC_IBC_REFBUF : 3;        /*!< [10..8] MCR ADC differential reference voltage buffer bias current
+                                                     control                                                                   */
+      __IOM uint32_t ADC_IBC_REFBUF2 : 1;       /*!< [11..11] MCR ADC bias voltage buffer bias current control                 */
+      __IOM uint32_t ADC_VCTRL_BIASGEN : 3;     /*!< [14..12] MCR ADC bias voltage control                                     */
+      __IOM uint32_t PGA0_EN    : 1;            /*!< [15..15] MCR CH0 PGA enable                                               */
+      __IOM uint32_t PGA_CSEL   : 3;            /*!< [18..16] MCR lowpass cap selection cap                                    */
+      __IOM uint32_t PGA1_EN    : 1;            /*!< [19..19] MCR CH1 PGA enable                                               */
+      __IOM uint32_t PGA_IOUTSEL : 3;           /*!< [22..20] MCR PAG output current enhance                                   */
+      __IOM uint32_t PGA2_EN    : 1;            /*!< [23..23] MCR CH2 PGA enable                                               */
+      __IOM uint32_t PGA_R1SEL  : 3;            /*!< [26..24] pag input resistor selection                                     */
+      __IOM uint32_t PGA_VCM_GEN_EN : 1;        /*!< [27..27] MCR PGA input common mode buffer enable                          */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t PGA_CM_EN  : 1;            /*!< [31..31] MCR PGA input common mode feedback enable                        */
+    } bit;
+  } CTRL1;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000008) MCR control                                                */
+
+    struct {
+      __IM  uint32_t            : 8;
+      __IOM uint32_t PGA_RES_BYPASS : 1;        /*!< [8..8] MCR control                                                        */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t PGA_LDO_EN : 1;            /*!< [11..11] MCR PGA LDO enable                                               */
+      __IOM uint32_t ADC_CHANNEL_SEL : 2;       /*!< [13..12] mcr adc test channel sel                                         */
+      __IOM uint32_t ADC_CHANNEL_EN : 1;        /*!< [14..14] mcr adc test channel enable                                      */
+      __IOM uint32_t ADC_OUT_EN : 1;            /*!< [15..15] MCR adc input connect to test pad enable                         */
+      __IOM uint32_t PGA0_GC    : 5;            /*!< [20..16] MCR CH0 PGA gain control                                         */
+      __IOM uint32_t PGA1_GC    : 5;            /*!< [25..21] MCR CH1 PGA gain control                                         */
+      __IOM uint32_t PGA2_GC    : 5;            /*!< [30..26] MCR CH2 PGA gain control                                         */
+    } bit;
+  } CTRL2;
+} ANA_MCR_Type;                                 /*!< Size = 12 (0xc)                                                           */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                        ADC_ANALOG                                         ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ADC_ANALOG (ADC_ANALOG)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB240) ADC_ANALOG Structure                                       */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) ADC_CTRL0                                                  */
+
+    struct {
+      __IOM uint32_t MISC_SARADC_EN_REG : 1;    /*!< [0..0] GPADC regulator enable. 0: off; 1: on                              */
+      __IOM uint32_t MISC_SARADC_EN_CONSTGM : 1;/*!< [1..1] GPADC constant Gm bias enable. 0: off; 1: on                       */
+      __IOM uint32_t MISC_SARADC_EN_BIASGEN : 1;/*!< [2..2] GPADC reference voltage enable. 0: off; 1: on                      */
+      __IOM uint32_t MISC_SARADC_EN : 1;        /*!< [3..3] GPADC enable. 0: off; 1: on                                        */
+      __IOM uint32_t MISC_SARADC_clk            : 2;
+      __IM  uint32_t  							: 2;
+      __IOM uint32_t MISC_GBG_FASTSETTLING : 1; /*!< [8..8] The global bandgap fast settling enable                            */
+      __IOM uint32_t MISC_GBG_EN : 1;           /*!< [9..9] The global bandgap enable                                          */
+    } bit;
+  } ADC_CTRL0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) ADC_CTRL1                                                  */
+
+    struct {
+      __IOM uint32_t MISC_SARADC_VCTRL_BIASGEN : 3;/*!< [2..0] GPADC bias voltage control 425mV+25mV*misc_saradc_vctrl_biasgen */
+      __IOM uint32_t MISC_SARADC_SEL_CH_S : 3;  /*!< [5..3] GPADC channel select                                               */
+      __IOM uint32_t MISC_SARADC_REGD_VCTRL : 2;/*!< [7..6] GPADC digital regulator output voltage control. 0: 1.0V;
+                                                     1: 1.1V; 2: 1.2V; 3: 1.3V                                                 */
+      __IOM uint32_t MISC_SARADC_REGA_VCTRL : 2;/*!< [9..8] GPADC analog regulator output voltage control. 0: 1.0V;
+                                                     1: 1.1V; 2: 1.2V; 3: 1.3V                                                 */
+      __IOM uint32_t MISC_SARADC_REFBUF_VREF_CTRL : 2;/*!< [11..10] GPADC differential reference voltage control.              */
+      __IOM uint32_t MISC_SARADC_MODE : 3;      /*!< [14..12] 0=gpio,1=gpio diff,2=hvin,3=vinlpm,4=temperature                 */
+      __IOM uint32_t MISC_SARADC_IBUF_GC : 2;   /*!< [16..15] GPADC full scale control                                         */
+      __IOM uint32_t MISC_SARADC_IBUF_EN_RC : 1;/*!< [17..17] GPADC input buffer feedback capacitor enable                     */
+      __IOM uint32_t MISC_SARADC_IBUF_BW : 2;   /*!< [19..18] GPADC input buffer bandwidth control                             */
+      __IOM uint32_t MISC_SARADC_IBC_REFBUF : 3;/*!< [22..20] GPADC differential reference voltage buffer bias current
+                                                     control                                                                   */
+      __IOM uint32_t MISC_SARADC_IBC_REFBUF2 : 1;/*!< [23..23] GPADC bias voltage buffer bias current control                  */
+      __IOM uint32_t MISC_SARADC_IBC_IBUF : 3;  /*!< [26..24] GPAADC input buffer bias control                                 */
+      __IOM uint32_t MISC_SARADC_IBC_CMBUF : 1; /*!< [27..27] GPADC biasgen buffer bias current control                        */
+    } bit;
+  } ADC_CTRL1;
+} ADC_ANALOG_Type;                              /*!< Size = 8 (0x8)                                                            */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          ANA_RNG                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ANA_RNG (ANA_RNG)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB260) ANA_RNG Structure                                          */
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000000) RNG control                                                */
+
+    struct {
+      __IM  uint32_t            : 17;
+      __IOM uint32_t RG_NCS_I_SET : 3;          /*!< [19..17] NCS current setting                                              */
+      __IOM uint32_t DA_NCS_EN  : 1;            /*!< [20..20] NCS enable                                                       */
+      __IOM uint32_t DA_NCS_RESETN : 1;         /*!< [21..21] NCS reset                                                        */
+      __IOM uint32_t DA_LDO_TRNG_EN : 1;        /*!< [22..22] Security TRNG LDO enable.                                        */
+      __IOM uint32_t DA_TRNG_BIAS_EN : 1;       /*!< [23..23] TRNG bias enable signal, high active                             */
+      __IOM uint32_t DA_TRNG_TRNGA_OSCJ_EN : 1; /*!< [24..24] TRNGA LFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGB_OSCJ_EN : 1; /*!< [25..25] TRNGB LFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGC_OSCJ_EN : 1; /*!< [26..26] TRNGC LFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGD_OSCJ_EN : 1; /*!< [27..27] TRNGD LFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGOA_EN : 1;     /*!< [28..28] TRNGA HFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGOB_EN : 1;     /*!< [29..29] TRNGB HFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGOC_EN : 1;     /*!< [30..30] TRNGC HFOSC enable signal,high active                            */
+      __IOM uint32_t DA_TRNG_TRNGOD_EN : 1;     /*!< [31..31] TRNGD HFOSC enable signal,high active                            */
+    } bit;
+  } RNG_CTRL0;
+
+  union {
+    __IOM uint32_t reg;                         /*!< (@ 0x00000004) RNG control                                                */
+
+    struct {
+      __IOM uint32_t RG_TRNG_TRNGA_ON_JITTER : 2;/*!< [1..0] TRNGA LFOSC jitter control signal                                 */
+      __IOM uint32_t RG_TRNG_TRNGA_OSCJ_TRIM : 2;/*!< [3..2] TRNGA LFOSC frequency control signal                              */
+      __IOM uint32_t RG_TRNG_TRNGA_OSCJ_VREF : 3;/*!< [6..4] TRNGA LFOSC vref control signal                                   */
+      __IOM uint32_t DA_TRNG_TRNGOA_CLR : 1;    /*!< [7..7] TRNGA sample DFF output clear signal,low active                    */
+      __IOM uint32_t RG_TRNG_TRNGB_ON_JITTER : 2;/*!< [9..8] TRNGB LFOSC jitter control signal                                 */
+      __IOM uint32_t RG_TRNG_TRNGB_OSCJ_TRIM : 2;/*!< [11..10] TRNGB LFOSC frequency control signal                            */
+      __IOM uint32_t RG_TRNG_TRNGB_OSCJ_VREF : 3;/*!< [14..12] TRNGB LFOSC vref control signal                                 */
+      __IOM uint32_t DA_TRNG_TRNGOB_CLR : 1;    /*!< [15..15] TRNGB sample DFF output clear signal,low active                  */
+      __IOM uint32_t RG_TRNG_TRNGC_ON_JITTER : 2;/*!< [17..16] TRNGC LFOSC jitter control signal                               */
+      __IOM uint32_t RG_TRNG_TRNGC_OSCJ_TRIM : 2;/*!< [19..18] TRNGC LFOSC frequency control signal                            */
+      __IOM uint32_t RG_TRNG_TRNGC_OSCJ_VREF : 3;/*!< [22..20] TRNGC LFOSC vref control signal                                 */
+      __IOM uint32_t DA_TRNG_TRNGOC_CLR : 1;    /*!< [23..23] TRNGC sample DFF output clear signal,low active                  */
+      __IOM uint32_t RG_TRNG_TRNGD_ON_JITTER : 2;/*!< [25..24] TRNGD LFOSC jitter control signal                               */
+      __IOM uint32_t RG_TRNG_TRNGD_OSCJ_TRIM : 2;/*!< [27..26] TRNGD LFOSC frequency control signal                            */
+      __IOM uint32_t RG_TRNG_TRNGD_OSCJ_VREF : 3;/*!< [30..28] TRNGD LFOSC vref control signal                                 */
+      __IOM uint32_t DA_TRNG_TRNGOD_CLR : 1;    /*!< [31..31] TRNGD sample DFF output clear signal,low active                  */
+    } bit;
+  } RNG_CTRL1;
+} ANA_RNG_Type;                                 /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          ANA_CHGR                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 32 ANA_CHGR (ANA_CHGR)
+  */
+
+typedef struct {                                /*!< (@ 0x000FB270) ANA_CHGR Structure                                          */
+
+    union {
+        __IM uint32_t reg;                         /*!< (@ 0x00000000) CHGR state                                                */
+
+        struct {
+            __IM uint32_t CHGR_STATE_VBAT_LV : 1;
+            __IM uint32_t CHGR_STATE_RCH_EN : 1;
+            __IM uint32_t CHGR_STATE_IND : 1;
+            __IM uint32_t CHGR_STATE_ICHG : 1;
+            __IM uint32_t CHGR_RESET : 1;
+            __IM uint32_t CHGR_UVLO_OK_AON : 1;
+            __IM uint32_t CHGR_PGOOD : 1;
+            __IM uint32_t CHGR_DPPM_OV_CV : 1;
+            __IM uint32_t CHGR_DPPM_OV_CC : 1;
+            __IM uint32_t CHGR_CC_OV_CV : 1;
+            __IM uint32_t CHGR_IN_DET_AON : 1;
+            __IM uint32_t VBAT_OV_FLAG : 1;
+        } bit;
+    } STATE;
+} ANA_CHGR_Type;                                 /*!< Size = 4 (0x4)                                                            */
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+#define MMCU_BASE                   0x000D0000UL
+#define MMPU_BASE                   0x000D8080UL
+#define MDCMI_BASE                  0x000D8200UL
+#define MHSPI_BASE                  0x000D8400UL
+#define MWDT_BASE                   0x000F0000UL
+#define MSCI0_BASE                  0x000F0400UL
+#define MSCI1_BASE                  0x000F0800UL
+#define MTIM_BASE                   0x000F0C00UL
+#define MCRC_BASE                   0x000F8204UL
+#define MRCC_BASE                   0x000F8400UL
+#define MSYSCTRL_BASE               0x000F8520UL
+#define MRSTGEN_BASE                0x000F8574UL
+#define MSECURE_BASE                0x000F85C0UL
+#define MGPIO_BASE                  0x000F8700UL
+#define MDMA_BASE                   0x000F8800UL
+#define MDMA_QSPI_BASE              0x000F8800UL
+#define MDMA_SPI0_BASE              0x000F8900UL
+#define MDMA_SPI1_BASE              0x000F8A00UL
+#define MDMA_UART0_BASE             0x000F8B00UL
+#define MDMA_UART1_BASE             0x000F8C00UL
+#define MDMA_UART2_BASE             0x000F8D00UL
+#define MDMA_UART3_BASE             0x000F8E00UL
+#define MDMA_7811_BASE              0x000F8F00UL
+#define MDMA_MEMCP_BASE             0x000F9000UL
+#define MDMA_IIC0_BASE              0x000F9100UL
+#define MDMA_IIC1_BASE              0x000F9200UL
+#define MSPI_BASE                   0x000F891CUL
+#define MSPI0_BASE                  0x000F891CUL
+#define MSPI1_BASE                  0x000F8A1CUL
+#define MUART_BASE                  0x000F8B1CUL
+#define MUART0_BASE                 0x000F8B1CUL
+#define MUART1_BASE                 0x000F8C1CUL
+#define MUART2_BASE                 0x000F8D1CUL
+#define MUART3_BASE                 0x000F8E1CUL
+#define MIIC_BASE                   0x000F911CUL
+#define MI2C0_BASE                  0x000F911CUL
+#define MI2C1_BASE                  0x000F921CUL
+#define MLPM_BASE                   0x000FA800UL
+#define MBPK_BASE                   0x000FAC00UL
+#define MSEC_BASE                   0x000FAE00UL
+#define MRTC_BASE                   0x000FAF00UL
+#define MRTCLSI_BASE                0x000FAF00UL
+#define MRTCLSE_BASE                0x000FB000UL
+#define MADC_BASE                   0x000FBB00UL
+#define MISO7811_BASE               0x000F8F00UL
+#define ANA_LDO_CLK_BASE            0x000FB200UL
+#define ANA_BBPLL_BASE              0x000FB210UL
+#define ANA_MCR_BASE                0x000FB230UL
+#define ADC_ANALOG_BASE             0x000FB240UL
+#define ANA_RNG_BASE                0x000FB260UL
+#define ANA_CHGR_BASE               0x000FB270UL
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define MMCU                        ((MMCU_Type*)              MMCU_BASE)
+#define MMPU                        ((MMPU_Type*)			   MMPU_BASE)
+#define MDCMI                       ((MDCMI_Type*) 			   MDCMI_BASE)
+#define MHSPI                       ((MHSPI_Type*)             MHSPI_BASE)
+#define MWDT                        ((MWDT_Type*)              MWDT_BASE)
+#define MSCI0                       ((MSCI0_Type*)             MSCI0_BASE)
+#define MSCI1                       ((MSCI0_Type*)             MSCI1_BASE)
+#define MTIM                        ((MTIM_Type*)              MTIM_BASE)
+#define MCRC                        ((MCRC_Type*)              MCRC_BASE)
+#define MRCC                        ((MRCC_Type*)              MRCC_BASE)
+#define MSYSCTRL                    ((MSYSCTRL_Type*)          MSYSCTRL_BASE)
+#define MRSTGEN                     ((MRSTGEN_Type*)           MRSTGEN_BASE)
+#define MSECURE                     ((MSECURE_Type*)           MSECURE_BASE)
+#define MGPIO                       ((MGPIO_Type*)             MGPIO_BASE)
+#define MDMA                        ((MDMA_Type*)              MDMA_BASE)
+#define MDMA_QSPI                   ((MDMA_Type*)              MDMA_QSPI_BASE)
+#define MDMA_SPI0                   ((MDMA_Type*)              MDMA_SPI0_BASE)
+#define MDMA_SPI1                   ((MDMA_Type*)              MDMA_SPI1_BASE)
+#define MDMA_UART0                  ((MDMA_Type*)              MDMA_UART0_BASE)
+#define MDMA_UART1                  ((MDMA_Type*)              MDMA_UART1_BASE)
+#define MDMA_UART2                  ((MDMA_Type*)              MDMA_UART2_BASE)
+#define MDMA_UART3                  ((MDMA_Type*)              MDMA_UART3_BASE)
+#define MDMA_7811                   ((MDMA_Type*)              MDMA_7811_BASE)
+#define MDMA_MEMCP                  ((MDMA_Type*)              MDMA_MEMCP_BASE)
+#define MDMA_IIC0                   ((MDMA_Type*)              MDMA_IIC0_BASE)
+#define MDMA_IIC1                   ((MDMA_Type*)              MDMA_IIC1_BASE)
+#define MSPI                        ((MSPI_Type*)              MSPI_BASE)
+#define MSPI0                       ((MSPI_Type*)              MSPI0_BASE)
+#define MSPI1                       ((MSPI_Type*)              MSPI1_BASE)
+#define MUART                       ((MUART_Type*)             MUART_BASE)
+#define MUART0                      ((MUART_Type*)             MUART0_BASE)
+#define MUART1                      ((MUART_Type*)             MUART1_BASE)
+#define MUART2                      ((MUART_Type*)             MUART2_BASE)
+#define MUART3                      ((MUART_Type*)             MUART3_BASE)
+#define MIIC                        ((MIIC_Type*)              MIIC_BASE)
+#define MI2C0                       ((MIIC_Type*)              MI2C0_BASE)
+#define MI2C1                       ((MIIC_Type*)              MI2C1_BASE)
+#define MLPM                        ((MLPM_Type*)              MLPM_BASE)
+#define MBPK                        ((MBPK_Type*)              MBPK_BASE)
+#define MSEC                        ((MSEC_Type*)              MSEC_BASE)
+#define MRTC                        ((MRTC_Type*)              MRTC_BASE)
+#define MRTCLSI                     ((MRTC_Type*)              MRTCLSI_BASE)
+#define MRTCLSE                     ((MRTC_Type*)              MRTCLSE_BASE)
+#define MADC                        ((MADC_Type*)              MADC_BASE)
+#define MISO7811                    ((MISO7811_Type*)          MISO7811_BASE)
+#define ANA_LDO_CLK                 ((ANA_LDO_CLK_Type*)       ANA_LDO_CLK_BASE)
+#define ANA_BBPLL                   ((ANA_BBPLL_Type*)         ANA_BBPLL_BASE)
+#define ANA_MCR                     ((ANA_MCR_Type*)           ANA_MCR_BASE)
+#define ADC_ANALOG                  ((ADC_ANALOG_Type*)        ADC_ANALOG_BASE)
+#define ANA_RNG                     ((ANA_RNG_Type*)           ANA_RNG_BASE)
+#define ANA_CHGR                    ((ANA_CHGR_Type*)          ANA_CHGR_BASE)
+
+
+#define MCU_TypeDef                 MMCU_Type
+#define DCMI_TypeDef                MDCMI_Type
+#define HSPI_TypeDef                MHSPI_Type
+#define WDT_TypeDef                 MWDT_Type
+#define SCI7816_TypeDef             MSCI0_Type
+#define TIM_Module_TypeDef          MTIM_Type
+#define RCC_TypeDef                 MRCC_Type
+#define SYSCTRL_TypeDef             MSYSCTRL_Type
+#define RSTGEN_TypeDef              MRSTGEN_Type
+#define SECURE_TypeDef              MSECURE_Type
+#define DMA_TypeDef                 MDMA_Type
+#define SPI_TypeDef                 MSPI_Type
+#define UART_TypeDef                MUART_Type
+#define ISO7811_TypeDef             MISO7811_Type
+#define I2C_TypeDef                 MIIC_Type
+#define LPM_TypeDef                 MLPM_Type
+#define BPK_TypeDef                 MBPK_Type
+#define SEC_TypeDef                 MSEC_Type
+#define RTC_TypeDef                 MRTC_Type
+#define ANA_LDO_CLK_TypeDef         ANA_LDO_CLK_Type
+#define ANA_BBPLL_TypeDef           ANA_BBPLL_Type
+#define ANA_MCR_TypeDef             ANA_MCR_Type
+#define ADC_ANALOG_TypeDef          ADC_ANALOG_Type
+#define ANA_RNG_TypeDef             ANA_RNG_Type
+#define ANA_CHGR_TypeDef            ANA_CHGR_Type
+#define ADC_TypeDef                 MADC_Type
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+#define YC3122_FLASH_BASE           (0x01000000UL)   /*!< (FLASH     )      Base Address */
+#define YC3122_SRAM_BASE            (0x00020000UL)   /*!< (SRAM      )      Base Address */
+#define YC3122_PERIPH_BASE          (0x000B0000UL)   /*!< (Peripheral)      Base Address */
+#define YC3122_FPERIPH_BASE         (0x000D0000UL)   /*!< (fast Peripheral) Base Address>*/
+#define YC3122_SRAM_SIZE            (0x80000)
+#define YC3122_OTP_BASE             (0x00000000UL)
+#define YC3122_OTP_SIZE             (0x2000)
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if defined (__CC_ARM)
+#pragma pop
+#elif defined (__ICCARM__)
+/* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic pop
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+#pragma warning restore
+#elif defined (__CSMC__)
+/* anonymous unions are enabled by default */
+#endif
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                     Peripheral Registers_Bits_Definition                   */
+/******************************************************************************/
+/******************  Bit definition for TIM_CTRL register  ********************/
+#define TIM_CTRL_ENABLE         BIT0
+#define TIM_CTRL_START_LEVEL    BIT1
+#define TIM_CTRL_MODE           BIT2
+#define TIM_CTRL_AUTO_RELOAD    BIT3
+
+/********************  Bit definition for rst register  ***********************/
+#define SW_RST                  ((uint8_t)0x55)
+#define SCI_RST                 ((uint8_t)0xAB)
+#define MSR_RST                 ((uint8_t)0xC3)
+
+/*******************  Bit definition for BPK_LR register  *********************/
+#define BPK_LR_LOCK_SELF        BIT0
+#define BPK_LR_LOCK_KEYWRITE    BIT1
+#define BPK_LR_LOCK_KEYREAD     BIT2
+#define BPK_LR_LOCK_KEYCLEAR    BIT3
+#define BPK_LR_LOCK_RESET       BIT4
+#define BPK_LR_LOCK_ALL         (BIT1|BIT2|BIT3|BIT4)
+
+/******************  Bit definition for SENSOR_LR register  *******************/
+#define SEC_LOCK_LOCK           BIT0
+#define ACTION_LOCK             BIT1
+#define TAMPER_LOCK             BIT2
+#define SENSOR_LOCK             BIT3
+#define SHIELD_LOCK             BIT4
+#define SENSOR_LOCK_ALL         (BIT1|BIT2|BIT3|BIT4)
+
+/******************  Bit definition for RTC_IRQ register  *********************/
+#define RTC_SECOND_IRQ          BIT0
+#define RTC_ALARM_IRQ           BIT1
+#define RTC_ALL_IRQ             (BIT0|BIT1)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __YC3122_H__ */
+
+/** @} */ /* End of group YC3122 */
+
+/** @} */ /* End of group  */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/arm/startup_yc3122.s

@@ -0,0 +1,284 @@
+;/*
+; * Copyright (c) 2006-2020, YICHIP Development Team
+; * @file     yc_startup.s
+; * @brief    source file for setting startup
+; *
+; * Change Logs:
+; * Date           Author             Version        Notes
+; * 2020-11-06     wushengyan         V1.0.0         the first version
+; * 2021-03-11     wushengyan         V1.0.2         Change for New ROM
+; */
+Stack_Size      EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=4
+Stack_Mem       SPACE   Stack_Size
+__initial_sp   
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=4
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset Rom code change to 0x1000200
+                AREA    RESET, CODE, READONLY   ,ALIGN=4
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+__Vectors       DCD     __initial_sp
+                DCD     Reset_Handler           ;//reset    1
+                DCD     0x00000000              ;//NMI      2
+                DCD     hard_fault_handler   ;//HARD     3
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     svc_handler          ;//SVC      11
+                DCD     0                       ;
+                DCD     0                       ;
+                DCD     pendsv_handler       ;//PENDSV  14
+                DCD     systick_handler      ;//SYSTICK 15
+                DCD     USB_IRQHandler          ;//IQR0
+                DCD     I2C0_IRQHandler         ;//IQR1
+                DCD     I2C1_IRQHandler         ;//IQR2
+                DCD     QSPI_IRQHandler         ;//IQR3
+                DCD     SPI0_IRQHandler         ;//IQR4
+                DCD     SPI1_IRQHandler         ;
+                DCD     HSPI_IRQHandler         ;
+                DCD     SEC_IRQHandler          ;
+                DCD     UART0_IRQHandler        ;
+                DCD     UART1_IRQHandler        ;
+                DCD     UART2_IRQHandler        ;
+                DCD     UART3_IRQHandler        ;
+                DCD     MEMCP_IRQHandler        ;
+                DCD     SCI0_IRQHandler         ;
+                DCD     SCI1_IRQHandler         ;
+                DCD     MSR_IRQHandler          ;
+                DCD     GPIO_IRQHandler         ;
+                DCD     TMRG0_IRQHandler        ;
+                DCD     TMRG1_IRQHandler        ;
+                DCD     SDIO_IRQHandler         ;
+                DCD     PSARM_IRQHandler        ;
+                DCD     RSA_IRQHandler          ;
+                DCD     SM4_IRQHandler          ;
+                DCD     TRNG_IRQHandler         ;
+                DCD     WDT_IRQHandler          ;
+                DCD     DCMI_IRQHandler         ;
+                DCD     ADC_IRQHandler          ;
+                DCD     RTC_IRQHandler          ;
+                DCD     BIN_IRQHandler          ;
+                DCD     POWER_IRQHandler        ;
+                DCD     SOFTWARE_IRQHandler     ;
+                DCD     RISCV_IRQHandler        ;
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+isr             PROC
+                LDR R1,=0x1000200
+                LDR R0,[R0,R1]
+                BX  R0
+                NOP
+                NOP
+                NOP
+                ENDP
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler
+                IMPORT  __main
+		IMPORT  SystemInit
+		LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                    
+hard_fault_handler PROC
+			EXPORT  hard_fault_handler 
+            IMPORT HardFault_Handler
+			ldr r0,=HardFault_Handler       
+			bx r0
+			nop
+			ENDP
+		
+svc_handler PROC
+			EXPORT  svc_handler         
+			ldr r0,=SVC_IRQHandler
+			bx r0
+			nop
+			ENDP
+
+pendsv_handler PROC
+			EXPORT  pendsv_handler
+            IMPORT  PendSV_Handler
+			ldr r0,=PendSV_Handler
+			bx r0
+			nop
+			ENDP
+		
+systick_handler 	PROC
+			EXPORT systick_handler 
+            IMPORT SysTick_Handler
+			ldr r0,=SysTick_Handler
+			bx r0
+			nop
+			ENDP
+
+
+                ALIGN
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT      HARD_FAULT_IRQHandler       [WEAK]
+                EXPORT      SVC_IRQHandler              [WEAK]
+                EXPORT      PENDSV_IRQHandler           [WEAK]
+                EXPORT      SYSTICK_IRQHandler          [WEAK]
+                EXPORT      EXTI0_IRQHandler            [WEAK]
+                EXPORT      EXTI1_IRQHandler            [WEAK]
+                EXPORT      EXTI2_IRQHandler            [WEAK]
+                EXPORT      EXTI3_IRQHandler            [WEAK]
+                EXPORT      EXTI4_IRQHandler            [WEAK]
+                EXPORT      TIMER0_IRQHandler           [WEAK]
+                EXPORT      TIMER1_IRQHandler           [WEAK]
+                EXPORT      TIMER2_IRQHandler           [WEAK]
+                EXPORT      TIMER3_IRQHandler           [WEAK]
+                EXPORT      TIMER4_IRQHandler           [WEAK]
+                EXPORT      TIMER5_IRQHandler           [WEAK]
+                EXPORT      TIMER6_IRQHandler           [WEAK]
+                EXPORT      TIMER7_IRQHandler           [WEAK]
+                EXPORT      TIMER8_IRQHandler           [WEAK]
+                EXPORT      CHGRIN_IRQHandler           [WEAK]
+                EXPORT      VBAT_IRQHandler             [WEAK]
+                EXPORT      USB_IRQHandler              [WEAK]
+                EXPORT      I2C0_IRQHandler             [WEAK]
+                EXPORT      I2C1_IRQHandler             [WEAK]
+                EXPORT      QSPI_IRQHandler             [WEAK]
+                EXPORT      SPI0_IRQHandler             [WEAK]
+                EXPORT      SPI1_IRQHandler             [WEAK]
+                EXPORT      HSPI_IRQHandler             [WEAK]
+                EXPORT      SEC_IRQHandler              [WEAK]
+                EXPORT      UART0_IRQHandler            [WEAK]
+                EXPORT      UART1_IRQHandler            [WEAK]
+                EXPORT      UART2_IRQHandler            [WEAK]
+                EXPORT      UART3_IRQHandler            [WEAK]
+                EXPORT      MEMCP_IRQHandler            [WEAK]
+                EXPORT      SCI0_IRQHandler             [WEAK]
+                EXPORT      SCI1_IRQHandler             [WEAK]
+                EXPORT      MSR_IRQHandler              [WEAK]
+                EXPORT      GPIO_IRQHandler             [WEAK]
+                EXPORT      TMRG0_IRQHandler            [WEAK]
+                EXPORT      TMRG1_IRQHandler            [WEAK]
+                EXPORT      SDIO_IRQHandler             [WEAK]
+                EXPORT      PSARM_IRQHandler            [WEAK]
+                EXPORT      RSA_IRQHandler              [WEAK]
+                EXPORT      SM4_IRQHandler              [WEAK]
+                EXPORT      TRNG_IRQHandler             [WEAK]
+                EXPORT      WDT_IRQHandler              [WEAK]
+                EXPORT      DCMI_IRQHandler             [WEAK]
+                EXPORT      ADC_IRQHandler              [WEAK]
+                EXPORT      RTC_IRQHandler              [WEAK]
+                EXPORT      BIN_IRQHandler              [WEAK]
+                EXPORT      POWER_IRQHandler            [WEAK]
+                EXPORT      SOFTWARE_IRQHandler         [WEAK]
+                EXPORT      RISCV_IRQHandler            [WEAK]
+
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+HARD_FAULT_IRQHandler
+SVC_IRQHandler
+PENDSV_IRQHandler
+SYSTICK_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+TIMER4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+TIMER7_IRQHandler
+TIMER8_IRQHandler
+CHGRIN_IRQHandler
+VBAT_IRQHandler
+USB_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+QSPI_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+HSPI_IRQHandler
+SEC_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+MEMCP_IRQHandler
+SCI0_IRQHandler
+SCI1_IRQHandler
+MSR_IRQHandler
+GPIO_IRQHandler
+TMRG0_IRQHandler
+TMRG1_IRQHandler
+SDIO_IRQHandler
+PSARM_IRQHandler
+RSA_IRQHandler
+SM4_IRQHandler
+TRNG_IRQHandler
+WDT_IRQHandler
+DCMI_IRQHandler
+ADC_IRQHandler
+RTC_IRQHandler
+BIN_IRQHandler
+POWER_IRQHandler
+SOFTWARE_IRQHandler
+RISCV_IRQHandler
+                B   .
+                ENDP
+
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, = __initial_sp
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+            END

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/gcc/startup_yc3122.S

@@ -0,0 +1,214 @@
+;/*
+; * Copyright (c) 2006-2020, YICHIP Development Team
+; * @file     yc_flash_start_gcc.s
+; * @brief    source file for setting flash_start_gcc
+; *
+; * Change Logs:
+; * Date           Author             Version        Notes
+; * 2020-11-06     wushengyan         V1.0.0         the first version
+; */
+
+.org 0x200
+        .global Reset_Handler,HARD_FAULT_IRQHandler,SVC_IRQHandler,PENDSV_IRQHandler,SYSTICK_IRQHandler
+
+vectors:
+                .long     0x00030000
+                .long     Reset_Handler             ;//reset  1
+                .long     0x00000000                ;//NMI    2
+                .long     hard_fault_handler     ;//HARD   3
+                .long     0                         ;
+                .long     0                         ;
+                .long     0                         ;
+                .long     0                         ;
+                .long     0                         ;
+                .long     0                         ;
+                .long     0                         ;
+                .long     svc_handler            ;//SVC     11
+                .long     0                         ;
+                .long     0                         ;
+                .long     pendsv_handler         ;//PENDSV  14
+                .long     systick_handler        ;//SYSTICK 15
+                .long     USB_IRQHandler            ;//IQR0
+                .long     I2C0_IRQHandler           ;//IQR1
+                .long     I2C1_IRQHandler           ;//IQR2
+                .long     QSPI_IRQHandler           ;//IQR3
+                .long     SPI0_IRQHandler           ;//IQR4
+                .long     SPI1_IRQHandler           ;
+                .long     HSPI_IRQHandler           ;
+                .long     SEC_IRQHandler            ;
+                .long     UART0_IRQHandler          ;
+                .long     UART1_IRQHandler          ;
+                .long     UART2_IRQHandler          ;
+                .long     UART3_IRQHandler          ;
+                .long     MEMCP_IRQHandler          ;
+                .long     SCI0_IRQHandler           ;
+                .long     SCI1_IRQHandler           ;
+                .long     MSR_IRQHandler            ;
+                .long     GPIO_IRQHandler           ;
+                .long     TMRG0_IRQHandler          ;
+                .long     TMRG1_IRQHandler          ;
+                .long     SDIO_IRQHandler           ;
+                .long     PSARM_IRQHandler          ;
+                .long     RSA_IRQHandler            ;
+                .long     SM4_IRQHandler            ;
+                .long     TRNG_IRQHandler           ;
+                .long     WDT_IRQHandler            ;
+                .long     DCMI_IRQHandler           ;
+                .long     ADC_IRQHandler            ;
+                .long     RTC_IRQHandler            ;
+                .long     BIN_IRQHandler            ;
+                .long     POWER_IRQHandler          ;
+                .long     SOFTWARE_IRQHandler       ;
+                .long     RISCV_IRQHandler          ;
+                .thumb_func
+isr:
+        LDR R1,=0x1000200
+        LDR R0,[R0,R1]
+        BX  R0
+        NOP
+        NOP
+        NOP
+        .thumb_func
+Reset_Handler:
+	LDR R0,=SystemInit
+	BLX R0
+        LDR R0,=hardware_init
+        BX  R0
+		
+hard_fault_handler:
+			ldr r0,=HardFault_Handler       
+			bx r0
+		
+svc_handler:      
+			ldr r0,=SVC_IRQHandler
+			bx r0
+
+pendsv_handler:
+			ldr r0,=PendSV_Handler
+			bx r0
+		
+systick_handler:
+			ldr r0,=SysTick_Handler
+			bx r0
+
+        .thumb
+        .thumb_func
+hardware_init:
+        ldr r1, =__exidx_start
+        ldr r2, =__data_start__
+        ldr r3, =__data_end__
+
+        sub r3, r2
+        ble .L_loop1_done
+
+    .L_loop1:
+        sub r3, #4
+        ldr r0, [r1,r3]
+        str r0, [r2,r3]
+        bgt .L_loop1
+
+    .L_loop1_done:
+
+;/*  Single BSS section scheme.
+; *
+; *  The BSS section is specified by following symbols
+; *    _sbss: start of the BSS section.
+; *    _ebss: end of the BSS section.
+; *
+; *  Both addresses must be aligned to 4 bytes boundary.
+; */
+        ldr    r1, =__bss_start__
+        ldr    r2, =__bss_end__
+
+        mov    r0, #0
+
+        sub    r2, r1
+        ble    .L_loop3_done
+
+    .L_loop3:
+        sub    r2, #4
+        str    r0, [r1, r2]
+        bgt    .L_loop3
+    .L_loop3_done:
+        ldr    r0,=0x12345
+        ldr    r3,=0x1111
+        bl    main
+
+        .globl delay
+        .syntax unified
+delay:
+        subs r0,#1
+        bne delay
+        nop
+        bx lr
+
+.align    1
+.thumb_func
+.weak    Default_Handler
+.type    Default_Handler, %function
+
+Default_Handler:
+    b    .
+    .size    Default_Handler, . - Default_Handler
+
+/*  Macro to define default handlers. Default handler
+ *  will be weak symbol and just dead loops. They can be
+ *  overwritten by other handlers
+ */
+    .macro    def_irq_handler    handler_name
+    .weak    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler      HARD_FAULT_IRQHandler
+    def_irq_handler      SVC_IRQHandler
+    def_irq_handler      PENDSV_IRQHandler
+    def_irq_handler      SYSTICK_IRQHandler
+    def_irq_handler      EXTI0_IRQHandler
+    def_irq_handler      EXTI1_IRQHandler
+    def_irq_handler      EXTI2_IRQHandler
+    def_irq_handler      EXTI3_IRQHandler
+    def_irq_handler      EXTI4_IRQHandler
+    def_irq_handler      TIMER0_IRQHandler
+    def_irq_handler      TIMER1_IRQHandler
+    def_irq_handler      TIMER2_IRQHandler
+    def_irq_handler      TIMER3_IRQHandler
+    def_irq_handler      TIMER4_IRQHandler
+    def_irq_handler      TIMER5_IRQHandler
+    def_irq_handler      TIMER6_IRQHandler
+    def_irq_handler      TIMER7_IRQHandler
+    def_irq_handler      TIMER8_IRQHandler
+    def_irq_handler      CHGRIN_IRQHandler
+    def_irq_handler      VBAT_IRQHandler
+    def_irq_handler      USB_IRQHandler
+    def_irq_handler      I2C0_IRQHandler
+    def_irq_handler      I2C1_IRQHandler
+    def_irq_handler      QSPI_IRQHandler
+    def_irq_handler      SPI0_IRQHandler
+    def_irq_handler      SPI1_IRQHandler
+    def_irq_handler      HSPI_IRQHandler
+    def_irq_handler      SEC_IRQHandler
+    def_irq_handler      UART0_IRQHandler
+    def_irq_handler      UART1_IRQHandler
+    def_irq_handler      UART2_IRQHandler
+    def_irq_handler      UART3_IRQHandler
+    def_irq_handler      MEMCP_IRQHandler
+    def_irq_handler      SCI0_IRQHandler
+    def_irq_handler      SCI1_IRQHandler
+    def_irq_handler      MSR_IRQHandler
+    def_irq_handler      GPIO_IRQHandler
+    def_irq_handler      TMRG0_IRQHandler
+    def_irq_handler      TMRG1_IRQHandler
+    def_irq_handler      SDIO_IRQHandler
+    def_irq_handler      PSARM_IRQHandler
+    def_irq_handler      RSA_IRQHandler
+    def_irq_handler      SM4_IRQHandler
+    def_irq_handler      TRNG_IRQHandler
+    def_irq_handler      WDT_IRQHandler
+    def_irq_handler      DCMI_IRQHandler
+    def_irq_handler      ADC_IRQHandler
+    def_irq_handler      RTC_IRQHandler
+    def_irq_handler      BIN_IRQHandler
+    def_irq_handler      POWER_IRQHandler
+    def_irq_handler      SOFTWARE_IRQHandler
+    def_irq_handler      RISCV_IRQHandler

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/iar/startup_yc3122.s

@@ -0,0 +1,225 @@
+;/*
+; * Copyright (c) 2006-2020, YICHIP Development Team
+; * @file     startup_yc3122.s
+; * @brief    source file for setting startup
+; *
+; * Change Logs:
+; * Date           Author             Version        Notes
+; * 2022-11-08     kiven              V1.0.0         the first version
+; */
+
+        MODULE  ?cstartup                       ; // 定义模块名称
+
+        ;Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start             ; // IAR 入口函数
+        EXTERN  SystemInit                      ; // 系统初始化函数
+        PUBLIC  _vector_table                   ; // 中断向量表地址
+
+        ALIGNROM 2
+        DATA                                    ; // 定义数据段
+_vector_table                                   ;中断向量表
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                   ;//reset    1
+        DCD     0x00000000                      ;//NMI      2
+        DCD     hard_fault_handler           ;//HARD     3
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     svc_handler                  ;//SVC      11
+        DCD     0                               ;
+        DCD     0                               ;
+        DCD     pendsv_handler               ;//PENDSV  14
+        DCD     systick_handler              ;//SYSTICK 15
+        DCD     USB_IRQHandler                  ;//IQR0
+        DCD     I2C0_IRQHandler                 ;//IQR1
+        DCD     I2C1_IRQHandler                 ;//IQR2
+        DCD     QSPI_IRQHandler                 ;//IQR3
+        DCD     SPI0_IRQHandler                 ;//IQR4
+        DCD     SPI1_IRQHandler                 ;
+        DCD     HSPI_IRQHandler                 ;
+        DCD     SEC_IRQHandler                  ;
+        DCD     UART0_IRQHandler                ;
+        DCD     UART1_IRQHandler                ;
+        DCD     UART2_IRQHandler                ;
+        DCD     UART3_IRQHandler                ;
+        DCD     MEMCP_IRQHandler                ;
+        DCD     SCI0_IRQHandler                 ;
+        DCD     SCI1_IRQHandler                 ;
+        DCD     MSR_IRQHandler                  ;
+        DCD     GPIO_IRQHandler                 ;
+        DCD     TMRG0_IRQHandler                ;
+        DCD     TMRG1_IRQHandler                ;
+        DCD     SDIO_IRQHandler                 ;
+        DCD     PSARM_IRQHandler                ;
+        DCD     RSA_IRQHandler                  ;
+        DCD     SM4_IRQHandler                  ;
+        DCD     TRNG_IRQHandler                 ;
+        DCD     WDT_IRQHandler                  ;
+        DCD     DCMI_IRQHandler                 ;
+        DCD     ADC_IRQHandler                  ;
+        DCD     RTC_IRQHandler                  ;
+        DCD     BIN_IRQHandler                  ;
+        DCD     POWER_IRQHandler                ;
+        DCD     SOFTWARE_IRQHandler             ;
+        DCD     RISCV_IRQHandler                ;
+
+        THUMB                                   ;//进入THUMB模式（THUMB-2指令集）
+        SECTION .intvec:CODE:REORDER(2)
+        CODE
+        PUBLIC isr
+isr
+        LDR     R1,=_vector_table
+        LDR     R0,[R0,R1]
+        BX      R0
+        NOP
+        NOP
+        NOP
+
+        PUBLIC Reset_Handler
+Reset_Handler
+        LDR     R0, =sfe(CSTACK)
+        mov	sp, R0
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+		
+hard_fault_handler PROC
+			EXPORT  hard_fault_handler 
+            IMPORT HardFault_Handler
+			LDR r0,=HardFault_Handler       
+			BX r0
+			nop
+			ENDP
+		
+svc_handler PROC
+			EXPORT  svc_handler         
+			ldr r0,=SVC_IRQHandler
+			BX r0
+			nop
+			ENDP
+
+pendsv_handler PROC
+			EXPORT  pendsv_handler
+            IMPORT  PendSV_Handler
+			LDR r0,=PendSV_Handler
+			BX r0
+			nop
+			ENDP
+		
+systick_handler 	PROC
+			EXPORT systick_handler 
+            IMPORT SysTick_Handler
+			LDR r0,=SysTick_Handler
+			BX r0
+			nop
+			ENDP
+
+; // 定义默认的中断函数，这里只是弱定义，可以被用户自己定义的中断向量函数覆盖
+        PUBWEAK HARD_FAULT_IRQHandler
+        PUBWEAK SVC_IRQHandler
+        PUBWEAK PENDSV_IRQHandler
+        PUBWEAK SYSTICK_IRQHandler
+        PUBWEAK EXTI_IRQHandler
+        PUBWEAK TIMER0_IRQHandler
+        PUBWEAK TIMER1_IRQHandler
+        PUBWEAK TIMER2_IRQHandler
+        PUBWEAK TIMER3_IRQHandler
+        PUBWEAK TIMER4_IRQHandler
+        PUBWEAK TIMER5_IRQHandler
+        PUBWEAK TIMER6_IRQHandler
+        PUBWEAK TIMER7_IRQHandler
+        PUBWEAK TIMER8_IRQHandler
+        PUBWEAK CHGRIN_IRQHandler
+        PUBWEAK VBAT_IRQHandler
+        PUBWEAK USB_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK QSPI_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK HSPI_IRQHandler
+        PUBWEAK SEC_IRQHandler
+        PUBWEAK UART0_IRQHandler
+        PUBWEAK UART1_IRQHandler
+        PUBWEAK UART2_IRQHandler
+        PUBWEAK UART3_IRQHandler
+        PUBWEAK MEMCP_IRQHandler
+        PUBWEAK SCI0_IRQHandler
+        PUBWEAK SCI1_IRQHandler
+        PUBWEAK MSR_IRQHandler
+        PUBWEAK GPIO_IRQHandler
+        PUBWEAK TMRG0_IRQHandler
+        PUBWEAK TMRG1_IRQHandler
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK PSARM_IRQHandler
+        PUBWEAK RSA_IRQHandler
+        PUBWEAK SM4_IRQHandler
+        PUBWEAK TRNG_IRQHandler
+        PUBWEAK WDT_IRQHandler
+        PUBWEAK DCMI_IRQHandler
+        PUBWEAK ADC_IRQHandler
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK BIN_IRQHandler
+        PUBWEAK POWER_IRQHandler
+        PUBWEAK SOFTWARE_IRQHandler
+        PUBWEAK RISCV_IRQHandler
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+HARD_FAULT_IRQHandler
+SVC_IRQHandler
+PENDSV_IRQHandler
+SYSTICK_IRQHandler
+EXTI_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+TIMER4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+TIMER7_IRQHandler
+TIMER8_IRQHandler
+CHGRIN_IRQHandler
+VBAT_IRQHandler
+USB_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+QSPI_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+HSPI_IRQHandler
+SEC_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+MEMCP_IRQHandler
+SCI0_IRQHandler
+SCI1_IRQHandler
+MSR_IRQHandler
+GPIO_IRQHandler
+TMRG0_IRQHandler
+TMRG1_IRQHandler
+SDIO_IRQHandler
+PSARM_IRQHandler
+RSA_IRQHandler
+SM4_IRQHandler
+TRNG_IRQHandler
+WDT_IRQHandler
+DCMI_IRQHandler
+ADC_IRQHandler
+RTC_IRQHandler
+BIN_IRQHandler
+POWER_IRQHandler
+SOFTWARE_IRQHandler
+RISCV_IRQHandler
+        B       .
+        END

bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/system_yc3122.c

@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "system_yc3122.h"
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies             */
+#define __HSI             (192000000UL)
+
+#define __SYSTEM_CLOCK    (__HSI / 4)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+    /* ToDo: add code to initialize the system
+       do not use global variables because this function is called before
+       reaching pre-main. RW section maybe overwritten afterwards.          */
+    
+    /* Write access code "0x55->0xaa->0x17" to set or clear "access_en" */
+    MLPM->ACCESS_CODE.reg = 0x55;
+    MLPM->ACCESS_CODE.reg = 0xaa;
+    MLPM->ACCESS_CODE.reg = 0x17;
+    if (MLPM->ACCESS_EN.reg != ENABLE)
+    {
+        MLPM->ACCESS_EN.reg = ENABLE;
+    } 
+    MLPM->BAKEUP_REG1.reg = 0xaaaaaaaa;
+}

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_armcc.h

@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_armclang.h

@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_gcc.h

@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_iccarm.h

@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_armv8mbl.h

@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_armv8mml.h

@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm0.h

@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm0plus.h

@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm1.h

@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm23.h

@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm3.h

@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm33.h

@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm4.h

@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_cm7.h

@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_sc000.h

@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/core_sc300.h

@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/mpu_armv7.h

@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/mpu_armv8.h

@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/yichip/yc3122-pos/Libraries/SConscript

@@ -0,0 +1,29 @@
+from building import *
+import rtconfig
+import os
+cwd     = GetCurrentDir()
+path_sdk = os.path.join(cwd,'sdk')
+path_core = os.path.join(cwd,'core')
+path_cmin = os.path.join(cwd,'CMSIS','Include')
+path_cmde = os.path.join(cwd,'CMSIS','Device','YICHIP','YC3122')
+src = Glob('sdk/*.c')
+CPPPATH = [path_sdk,path_core,path_cmin,os.path.join(path_cmde,'Include'),cwd]
+
+src += Glob(path_cmde + '/Source/Templates/*.c')
+src += ['core/system.c']
+
+if rtconfig.PLATFORM in ['gcc']:
+	src += ['sdk/libyc_qspi.a']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += ['sdk/yc_qspi.lib']
+	
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [path_cmde + '/Source/Templates/gcc/startup_yc3122.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [path_cmde + '/Source/Templates/arm/startup_yc3122.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += [path_cmde + '/Source/Templates/iar/startup_yc3122.s']
+group = DefineGroup('Libraries', src, depend = [''],CPPPATH = CPPPATH, CPPDEFINES = ['__USE_YC_M0__'])
+
+Return('group')

bsp/yichip/yc3122-pos/Libraries/core/board_config.h

@@ -0,0 +1,1979 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_board_config.h
+ * @brief    source file for setting board_config
+ *
+ * Change Logs:
+ * Date           Author             Version        Notes
+ * 2020-11-05     wushengyan         V1.0.0         the first version
+ */
+
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include "yc3122.h"
+#include "yc_gpio.h"
+
+/*鏉垮瓙绫诲瀷*/
+#define FPGA_BOARD  (1)
+#define EVB_BOARD   (2)
+#define APP_BOARD   (3)
+#define APP_88PIN_BOARD (4)
+
+#define APP_YC3158AB_BOARD (6)
+#define APP_YC3163AB_BOARD (7)
+#define APP_YC3164AB_BOARD (8)
+#define APP_YC3165AB_BOARD (9)
+#define APP_YC3154AB_BOARD (10)
+
+#define APP_194_YC3173AB_DOORLOCK_V1_0_BOARD (80)
+
+#ifndef BOARD_TYPE
+#define BOARD_TYPE  APP_YC3165AB_BOARD
+#endif
+
+/*General function define*/
+#define GPIO_Group_To_GroupIn(Group)  ((((uint32_t)Group - GPIO_BASEADDR)/8) + (uint32_t)GPIO_IN_BASE)//((uint32_t*)GPIO_EN_BASE + (uint32_t *)(((uint32_t*)Group - (uint32_t*)GPIO_BASEADDR) & 0xff)/8)
+#define GPIO_Pin_To_PinIn(Pin)        (1 << Pin)
+
+#if (BOARD_TYPE == FPGA_BOARD)
+
+/*function define*/
+#define FPGA_reg_write(addr,wdata)  {*((volatile uint8_t*)(0xf856d)) = addr;\
+                                     *((volatile uint8_t*)(0xf856e)) = wdata;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x00;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x02;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x00;}
+
+#define FPGA_reg_read(addr)         {*((volatile uint8_t*)(0xf856d)) = addr;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x00;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x01;\
+                                     *((volatile uint8_t*)(0xf856c)) = 0x00;\
+                                     (*((volatile uint8_t*)(0xf856f)));}
+
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (115200)
+#define PRINTRX_PORT        GPIOB
+#define PRINTRX_IO_PIN      GPIO_Pin_0
+#define PRINTTX_PORT        GPIOB
+#define PRINTTX_IO_PIN      GPIO_Pin_1
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1PORT           MUART1
+#define UART1_BAUD          (115200)
+#define UART1RX_PORT        GPIOB
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOB
+#define UART1TX_IO_PIN      GPIO_Pin_1
+#define UART1RTS_PORT       GPIOB
+#define UART1RTS_IO_PIN     GPIO_Pin_2
+#define UART1CTS_PORT       GPIOB
+#define UART1CTS_IO_PIN     GPIO_Pin_3
+
+//uart2
+#define UART2PORT           MUART2
+#define UART2_BAUD          (115200)
+#define UART2RX_PORT        GPIOC
+#define UART2RX_IO_PIN      GPIO_Pin_6
+#define UART2TX_PORT        GPIOC
+#define UART2TX_IO_PIN      GPIO_Pin_5
+#define UART2RTS_PORT       GPIOD
+#define UART2RTS_IO_PIN     GPIO_Pin_0
+#define UART2CTS_PORT       GPIOD
+#define UART2CTS_IO_PIN     GPIO_Pin_1
+
+//uart3
+#define UART3PORT           MUART3
+#define UART3_BAUD          (115200)
+#define UART3RX_PORT        GPIOC
+#define UART3RX_IO_PIN      GPIO_Pin_14
+#define UART3TX_PORT        GPIOC
+#define UART3TX_IO_PIN      GPIO_Pin_13
+#define UART3RTS_PORT       GPIOC
+#define UART3RTS_IO_PIN     GPIO_Pin_15
+#define UART3CTS_PORT       GPIOC
+#define UART3CTS_IO_PIN     GPIO_Pin_12
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOD
+#define SPI0NCS_IO_PIN      GPIO_Pin_12
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOA
+#define SPI0SCK_IO_PIN      GPIO_Pin_11
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_12
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_13
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOC
+#define SPI1NCS_IO_PIN      GPIO_Pin_8
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOC
+#define SPI1SCK_IO_PIN      GPIO_Pin_9
+#define SPI1MOSI_PORT       GPIOC
+#define SPI1MOSI_IO_PIN     GPIO_Pin_10
+#define SPI1MISO_PORT       GPIOC
+#define SPI1MISO_IO_PIN     GPIO_Pin_6
+
+//tft
+#define ST7789CS_PORT       GPIOD
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOE
+#define ST7789RST_IO_PIN    GPIO_Pin_1
+#define ST7789A0_PORT       GPIOE
+#define ST7789A0_IO_PIN     GPIO_Pin_2
+#define ST7789BL_PORT       GPIOE
+#define ST7789BL_IO_PIN     GPIO_Pin_9
+#define ST7789SCK_PORT      GPIOA
+#define ST7789SCK_IO_PIN    GPIO_Pin_11
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_12
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_13
+
+//lcd
+#define ST7539CS_PORT  	    GPIOB
+#define ST7539CS_IO_PIN   	GPIO_Pin_15
+#define ST7539RST_PORT 	    GPIOB
+#define ST7539RST_IO_PIN  	GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//16Mflash
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_13
+#define FLASH16M_SCK_PORT     GPIOC
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_6
+#define FLASH16M_MOSI_PORT    GPIOC
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_7
+#define FLASH16M_MISO_PORT    GPIOC
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_8
+
+#define FLASH4M_NCS_PORT      GPIOD
+#define FLASH4M_NCS_IO_PIN    GPIO_Pin_12
+#define FLASH4M_SCK_PORT      GPIOC
+#define FLASH4M_SCK_IO_PIN    GPIO_Pin_6
+#define FLASH4M_MOSI_PORT     GPIOC
+#define FLASH4M_MOSI_IO_PIN   GPIO_Pin_7
+#define FLASH4M_MISO_PORT     GPIOC
+#define FLASH4M_MISO_IO_PIN   GPIO_Pin_8
+
+//pwm
+#define PWM0_PORT  	        GPIOB
+#define PWM0_IO_PIN   	    GPIO_Pin_8
+#define PWM1_PORT 	        GPIOB
+#define PWM1_IO_PIN  	    GPIO_Pin_9
+#define PWM2_PORT  	        GPIOB
+#define PWM2_IO_PIN   	    GPIO_Pin_10
+#define PWM3_PORT  	        GPIOB
+#define PWM3_IO_PIN   	    GPIO_Pin_11
+#define PWM4_PORT  	        GPIOB
+#define PWM4_IO_PIN   	    GPIO_Pin_12
+#define PWM5_PORT 	        GPIOB
+#define PWM5_IO_PIN  	    GPIO_Pin_13
+#define PWM6_PORT  	        GPIOB
+#define PWM6_IO_PIN   	    GPIO_Pin_14
+#define PWM7_PORT  	        GPIOB
+#define PWM7_IO_PIN   	    GPIO_Pin_15
+#define PWM8_PORT  	        GPIOD
+#define PWM8_IO_PIN   	    GPIO_Pin_2
+
+//chgr_event // j6(0308 camera)
+#define CHGR_VBAT_OV_FLAG_PORT  	        GPIOE //D2
+#define CHGR_VBAT_OV_FLAG_IO_PIN   	        GPIO_Pin_8
+#define CHGR_IN_DET_AON_PORT 	            GPIOE //D1
+#define CHGR_IN_DET_AON_IO_PIN  	        GPIO_Pin_7
+#define CHGR_CC_OV_CV_PORT  	            GPIOE //D3
+#define CHGR_CC_OV_CV_IO_PIN   	            GPIO_Pin_9
+#define CHGR_DPPM_OV_CC_PORT  	            GPIOE //D0
+#define CHGR_DPPM_OV_CC_IO_PIN   	        GPIO_Pin_6
+#define CHGR_DPPM_OV_CV_PORT  	            GPIOE //D4
+#define CHGR_DPPM_OV_CV_IO_PIN   	        GPIO_Pin_10
+#define CHGR_PGOOD_PORT 	                GPIOE //pclk
+#define CHGR_PGOOD_IO_PIN  	                GPIO_Pin_0
+#define CHGR_UVLO_OK_AON_PORT  	            GPIOE //D5
+#define CHGR_UVLO_OK_AON_IO_PIN   	        GPIO_Pin_11
+#define CHGR_RESET_PORT  	                GPIOE //D6
+#define CHGR_RESET_IO_PIN   	            GPIO_Pin_12
+#define CHGR_STSTE_ICHG_PORT  	            GPIOE //mclk
+#define CHGR_STSTE_ICHG_IO_PIN   	        GPIO_Pin_4
+#define CHGR_STATE_IND_PORT  	            GPIOE //D7
+#define CHGR_STATE_IND_IO_PIN   	        GPIO_Pin_13
+#define CHGR_STSTE_RCH_EN_PORT  	        GPIOE //hsync
+#define CHGR_STSTE_RCH_EN_IO_PIN   	        GPIO_Pin_2
+#define CHGR_STSTE_VBAT_LV_PORT  	        GPIOE //stb
+#define CHGR_STSTE_VBAT_LV_IO_PIN   	    GPIO_Pin_3
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_13
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_15
+#define SCI7816_VCARD_PORT                  GPIOA
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_1
+#define SCI7816_DETECT_PORT                 GPIOE
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_12
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (65)
+#define DCMI_LCD_CS_PIN                     (63)
+#define DCMI_LCD_CLK_PIN                    (11)
+#define DCMI_LCD_MOSI_PIN                   (12)
+#define DCMI_LCD_MISO_PIN                   (13)
+#define DCMI_LCD_A0_PIN                     (66)
+#define DCMI_LCD_BL_PIN                     (73)
+
+#define DCMI_CAMERA_SDA_PIN                 (19)
+#define DCMI_CAMERA_SCL_PIN                 (18)
+#define DCMI_CAMERA_RST_PIN                 (31)
+#define DCMI_CAMERA_PWDN_PIN                (36)
+#define DCMI_CAMERA_MCLK_PIN                (30)
+#define DCMI_CAMERA_PCLK_PIN                (32)
+#define DCMI_CAMERA_VSYNC_PIN               (34)
+#define DCMI_CAMERA_HSYNC_PIN               (33)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//fpc1020
+#define FPC1020_SPI0_PORT 	    GPIOA
+#define FPC1020_SPI0_CS_PIN 	GPIO_Pin_5
+#define FPC1020_SPI0_SCLK_PIN 	GPIO_Pin_6
+#define FPC1020_SPI0_MOSI_PIN 	GPIO_Pin_7
+#define FPC1020_SPI0_MISO_PIN 	GPIO_Pin_8
+#define FPC1020_RST_PIN 	    GPIO_Pin_9
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_10
+
+#elif (BOARD_TYPE == APP_BOARD)
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (115200)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1PORT           MUART1
+#define UART1_BAUD          (115200)
+#define UART1RX_PORT        GPIOB
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOB
+#define UART1TX_IO_PIN      GPIO_Pin_1
+#define UART1RTS_PORT       GPIOB
+#define UART1RTS_IO_PIN     GPIO_Pin_2
+#define UART1CTS_PORT       GPIOB
+#define UART1CTS_IO_PIN     GPIO_Pin_3
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+//spi2
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//lcd
+#define ST7539CS_PORT  	    GPIOD
+#define ST7539CS_IO_PIN   	GPIO_Pin_15
+#define ST7539RST_PORT 	    GPIOE
+#define ST7539RST_IO_PIN  	GPIO_Pin_1
+#define ST7539A0_PORT  	    GPIOE
+#define ST7539A0_IO_PIN   	GPIO_Pin_2
+#define ST7539BL_PORT  	    GPIOE
+#define ST7539BL_IO_PIN   	GPIO_Pin_9
+#define ST7539SCK_PORT      GPIOA
+#define ST7539SCK_IO_PIN    GPIO_Pin_11
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_12
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_13
+//tft
+#define ST7789CS_PORT       GPIOB
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOB
+#define ST7789RST_IO_PIN    GPIO_Pin_2
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_0
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_2
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_1
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+
+//pwm
+#define PWM0_PORT  	        GPIOB
+#define PWM0_IO_PIN   	    GPIO_Pin_8
+#define PWM1_PORT 	        GPIOB
+#define PWM1_IO_PIN  	    GPIO_Pin_9
+#define PWM2_PORT  	        GPIOB
+#define PWM2_IO_PIN   	    GPIO_Pin_10
+#define PWM3_PORT  	        GPIOB
+#define PWM3_IO_PIN   	    GPIO_Pin_11
+#define PWM4_PORT  	        GPIOB
+#define PWM4_IO_PIN   	    GPIO_Pin_12
+#define PWM5_PORT 	        GPIOB
+#define PWM5_IO_PIN  	    GPIO_Pin_13
+#define PWM6_PORT  	        GPIOB
+#define PWM6_IO_PIN   	    GPIO_Pin_14
+#define PWM7_PORT  	        GPIOB
+#define PWM7_IO_PIN   	    GPIO_Pin_15
+#define PWM8_PORT  	        GPIOD
+#define PWM8_IO_PIN   	    GPIO_Pin_2
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (18)
+#define DCMI_LCD_CS_PIN                     (31)
+#define DCMI_LCD_CLK_PIN                    (17)
+#define DCMI_LCD_MOSI_PIN                   (15)
+#define DCMI_LCD_MISO_PIN                   (14)
+#define DCMI_LCD_A0_PIN                     (16)
+#define DCMI_LCD_BL_PIN                     (34)
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (31)
+#define DCMI_CAMERA_PWDN_PIN                (49)
+#define DCMI_CAMERA_MCLK_PIN                (35)
+#define DCMI_CAMERA_PCLK_PIN                (36)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//fpc1020
+#define FPC1020_SPI0_PORT 	    GPIOC
+#define FPC1020_SPI0_CS_PIN 	GPIO_Pin_6
+#define FPC1020_SPI0_SCLK_PIN 	GPIO_Pin_1
+#define FPC1020_SPI0_MOSI_PIN 	GPIO_Pin_2
+#define FPC1020_SPI0_MISO_PIN 	GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+#elif (BOARD_TYPE == APP_88PIN_BOARD)
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOB
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOB
+#define ST7789RST_IO_PIN    GPIO_Pin_2
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_0
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_2
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_1
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (18)
+#define DCMI_LCD_CS_PIN                     (31)
+#define DCMI_LCD_CLK_PIN                    (17)
+#define DCMI_LCD_MOSI_PIN                   (15)
+#define DCMI_LCD_MISO_PIN                   (14)
+#define DCMI_LCD_A0_PIN                     (16)
+#define DCMI_LCD_BL_PIN                     (34)
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (32)
+#define DCMI_CAMERA_PWDN_PIN                (49)
+#define DCMI_CAMERA_MCLK_PIN                (35)
+#define DCMI_CAMERA_PCLK_PIN                (36)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//psram
+#define PSRAM_NCS_PIN                       (29)
+#define PSRAM_SCK_PIN                       (30)
+#define PSRAM_DATA0_PIN                     (28)
+#define PSRAM_DATA1_PIN                     (25)
+#define PSRAM_DATA2_PIN                     (26)
+#define PSRAM_DATA3_PIN                     (27)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_13
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_15
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+
+#elif (BOARD_TYPE == APP_YC3158AB_BOARD)
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOB
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOB
+#define ST7789RST_IO_PIN    GPIO_Pin_2
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_0
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_2
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_1
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (18)
+#define DCMI_LCD_CS_PIN                     (33)//(31)
+#define DCMI_LCD_CLK_PIN                    (17)
+#define DCMI_LCD_MOSI_PIN                   (15)
+#define DCMI_LCD_MISO_PIN                   (14)
+#define DCMI_LCD_A0_PIN                     (16)
+#define DCMI_LCD_BL_PIN                     (34)
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (32)
+#define DCMI_CAMERA_PWDN_PIN                (7)//(49)
+#define DCMI_CAMERA_MCLK_PIN                (35)
+#define DCMI_CAMERA_PCLK_PIN                (36)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (31)//(45)
+#define DCMI_CAMERA_DATA4_PIN               (58)//(44)
+#define DCMI_CAMERA_DATA5_PIN               (57)//(43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//psram
+#define PSRAM_NCS_PIN                       (45)
+#define PSRAM_SCK_PIN                       (44)
+#define PSRAM_DATA0_PIN                     (52)
+#define PSRAM_DATA1_PIN                     (49)
+#define PSRAM_DATA2_PIN                     (50)
+#define PSRAM_DATA3_PIN                     (43)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_13
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_15
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+#elif (BOARD_TYPE == APP_YC3163AB_BOARD)
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOB
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOB
+#define ST7789RST_IO_PIN    GPIO_Pin_2
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_0
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_2
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_1
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (18)
+#define DCMI_LCD_CS_PIN                     (31)
+#define DCMI_LCD_CLK_PIN                    (17)
+#define DCMI_LCD_MOSI_PIN                   (15)
+#define DCMI_LCD_MISO_PIN                   (14)
+#define DCMI_LCD_A0_PIN                     (16)
+#define DCMI_LCD_BL_PIN                     (34)
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (32)
+#define DCMI_CAMERA_PWDN_PIN                (49)
+#define DCMI_CAMERA_MCLK_PIN                (35)
+#define DCMI_CAMERA_PCLK_PIN                (36)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//psram
+#define PSRAM_NCS_PIN                       (29)
+#define PSRAM_SCK_PIN                       (30)
+#define PSRAM_DATA0_PIN                     (28)
+#define PSRAM_DATA1_PIN                     (25)
+#define PSRAM_DATA2_PIN                     (26)
+#define PSRAM_DATA3_PIN                     (27)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_13
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_15
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+
+#elif (BOARD_TYPE == APP_YC3164AB_BOARD)
+/*Print Port*/
+
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOB
+#define ST7789CS_IO_PIN     GPIO_Pin_15
+#define ST7789RST_PORT      GPIOB
+#define ST7789RST_IO_PIN    GPIO_Pin_2
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_0
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_2
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_1
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (13)
+#define DCMI_LCD_CS_PIN                     (32)
+#define DCMI_LCD_CLK_PIN                    (12)
+#define DCMI_LCD_MOSI_PIN                   (10)
+#define DCMI_LCD_MISO_PIN                   (9)
+#define DCMI_LCD_A0_PIN                     (11)
+#define DCMI_LCD_BL_PIN                     (34)
+
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (32)
+#define DCMI_CAMERA_PWDN_PIN                (49)
+#define DCMI_CAMERA_MCLK_PIN                (35)
+#define DCMI_CAMERA_PCLK_PIN                (36)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//psram
+#define PSRAM_NCS_PIN                       (45)
+#define PSRAM_SCK_PIN                       (44)
+#define PSRAM_DATA0_PIN                     (52)
+#define PSRAM_DATA1_PIN                     (49)
+#define PSRAM_DATA2_PIN                     (50)
+#define PSRAM_DATA3_PIN                     (43)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_15
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_13
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+
+#define UART2BTBAUD           115200
+#define UART2BT_TX_PORT       GPIOE
+#define UART2BT_TX_PIN        GPIO_Pin_0
+#define UART2BT_RX_PORT       GPIOD
+#define UART2BT_RX_PIN        GPIO_Pin_13
+#define UART2BT_UARTx         MUART2
+#define UART2BT_Tx_FUNC       UART2_TXD
+#define UART2BT_Rx_FUNC       UART2_RXD
+#define UART2BT_IRQN          10
+#define UART2BT_RTS_SOFT_PORT GPIOD     //鐢ㄤ簬m0鏍镐笌bt鏍歌蒋浠舵祦鎺�
+#define UART2BT_RTS_SOFT_PIN  GPIO_Pin_11
+
+#elif (BOARD_TYPE == APP_YC3165AB_BOARD)
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOC
+#define ST7789CS_IO_PIN     GPIO_Pin_7
+#define ST7789RST_PORT      GPIOC
+#define ST7789RST_IO_PIN    GPIO_Pin_5
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_1
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_8
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_0
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (37)
+#define DCMI_LCD_CS_PIN                     (39)
+#define DCMI_LCD_CLK_PIN                    (16)
+#define DCMI_LCD_MOSI_PIN                   (14)
+#define DCMI_LCD_MISO_PIN                   (15)
+#define DCMI_LCD_A0_PIN                     (17)
+#define DCMI_LCD_BL_PIN                     (40)
+
+
+#define DCMI_CAMERA_SDA_PIN                 (51)
+#define DCMI_CAMERA_SCL_PIN                 (48)
+#define DCMI_CAMERA_RST_PIN                 (0xff)
+#define DCMI_CAMERA_PWDN_PIN                (63)
+#define DCMI_CAMERA_MCLK_PIN                (41)
+#define DCMI_CAMERA_PCLK_PIN                (42)
+#define DCMI_CAMERA_VSYNC_PIN               (47)
+#define DCMI_CAMERA_HSYNC_PIN               (46)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (62)
+#define DCMI_CAMERA_DATA1_PIN               (61)
+#define DCMI_CAMERA_DATA2_PIN               (60)
+#define DCMI_CAMERA_DATA3_PIN               (59)
+#define DCMI_CAMERA_DATA4_PIN               (58)
+#define DCMI_CAMERA_DATA5_PIN               (57)
+#define DCMI_CAMERA_DATA6_PIN               (56)
+#define DCMI_CAMERA_DATA7_PIN               (55)
+
+//psram
+#define PSRAM_NCS_PIN                       (45)
+#define PSRAM_SCK_PIN                       (44)
+#define PSRAM_DATA0_PIN                     (52)
+#define PSRAM_DATA1_PIN                     (49)
+#define PSRAM_DATA2_PIN                     (50)
+#define PSRAM_DATA3_PIN                     (43)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_15
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_13
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+
+#define UART2BTBAUD           115200
+#define UART2BT_TX_PORT       GPIOE
+#define UART2BT_TX_PIN        GPIO_Pin_0
+#define UART2BT_RX_PORT       GPIOD
+#define UART2BT_RX_PIN        GPIO_Pin_13
+#define UART2BT_UARTx         MUART2
+#define UART2BT_Tx_FUNC       UART2_TXD
+#define UART2BT_Rx_FUNC       UART2_RXD
+#define UART2BT_IRQN          10
+#define UART2BT_RTS_SOFT_PORT GPIOD     //鐢ㄤ簬m0鏍镐笌bt鏍歌蒋浠舵祦鎺�
+#define UART2BT_RTS_SOFT_PIN  GPIO_Pin_11
+
+
+
+#elif (BOARD_TYPE == APP_YC3154AB_BOARD)
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//spi0
+#define SPI0PORT            MSPI0
+#define SPI0NCS_PORT        GPIOB
+#define SPI0NCS_IO_PIN      GPIO_Pin_15
+#define SPI04MNCS_PORT      GPIOD
+#define SPI04MNCS_IO_PIN    GPIO_Pin_12
+#define SPI016MNCS_PORT     GPIOD
+#define SPI016MNCS_IO_PIN   GPIO_Pin_13
+#define SPI0SCK_PORT        GPIOB
+#define SPI0SCK_IO_PIN      GPIO_Pin_1
+#define SPI0MOSI_PORT       GPIOA
+#define SPI0MOSI_IO_PIN     GPIO_Pin_15
+#define SPI0MISO_PORT       GPIOA
+#define SPI0MISO_IO_PIN     GPIO_Pin_14
+
+//spi1
+#define SPI1PORT            MSPI1
+#define SPI1NCS_PORT        GPIOB
+#define SPI1NCS_IO_PIN      GPIO_Pin_15
+#define SPI14MNCS_PORT      GPIOC
+#define SPI14MNCS_IO_PIN    GPIO_Pin_8
+#define SPI116MNCS_PORT     GPIOC
+#define SPI116MNCS_IO_PIN   GPIO_Pin_8
+#define SPI1SCK_PORT        GPIOB
+#define SPI1SCK_IO_PIN      GPIO_Pin_1
+#define SPI1MOSI_PORT       GPIOA
+#define SPI1MOSI_IO_PIN     GPIO_Pin_15
+#define SPI1MISO_PORT       GPIOA
+#define SPI1MISO_IO_PIN     GPIO_Pin_14
+
+#define SPI2PORT            HSPI
+#define SPI2NCS_PORT        GPIOB
+#define SPI2NCS_IO_PIN      GPIO_Pin_15
+#define SPI2SCK_PORT        GPIOB
+#define SPI2SCK_IO_PIN      GPIO_Pin_1
+#define SPI2MOSI_PORT       GPIOA
+#define SPI2MOSI_IO_PIN     GPIO_Pin_15
+#define SPI2MISO_PORT       GPIOA
+#define SPI2MISO_IO_PIN     GPIO_Pin_14
+
+//spi0_slaver
+#define SPI0NCS_PORT_S        GPIOB
+#define SPI0NCS_IO_PIN_S      GPIO_Pin_12
+#define SPI0SCK_PORT_S        GPIOB
+#define SPI0SCK_IO_PIN_S      GPIO_Pin_13
+#define SPI0MOSI_PORT_S       GPIOB
+#define SPI0MOSI_IO_PIN_S     GPIO_Pin_14
+#define SPI0MISO_PORT_S       GPIOB
+#define SPI0MISO_IO_PIN_S     GPIO_Pin_15
+
+//spi1_master
+#define SPI1NCS_PORT_M         GPIOC
+#define SPI1NCS_IO_PIN_M       GPIO_Pin_1
+#define SPI1SCK_PORT_M         GPIOC
+#define SPI1SCK_IO_PIN_M       GPIO_Pin_2
+#define SPI1MOSI_PORT_M        GPIOC
+#define SPI1MOSI_IO_PIN_M      GPIO_Pin_3
+#define SPI1MISO_PORT_M        GPIOC
+#define SPI1MISO_IO_PIN_M      GPIO_Pin_4
+
+//lcd
+#define ST7539CS_PORT       GPIOB
+#define ST7539CS_IO_PIN    GPIO_Pin_15
+#define ST7539RST_PORT      GPIOB
+#define ST7539RST_IO_PIN   GPIO_Pin_2
+#define ST7539A0_PORT  	    GPIOB
+#define ST7539A0_IO_PIN   	GPIO_Pin_0
+#define ST7539BL_PORT  	    GPIOC
+#define ST7539BL_IO_PIN   	GPIO_Pin_2
+#define ST7539SCK_PORT      GPIOB
+#define ST7539SCK_IO_PIN    GPIO_Pin_1
+#define ST7539MOSI_PORT     GPIOA
+#define ST7539MOSI_IO_PIN   GPIO_Pin_15
+#define ST7539MISO_PORT     GPIOA
+#define ST7539MISO_IO_PIN   GPIO_Pin_14
+
+//tft
+#define ST7789CS_PORT       GPIOC
+#define ST7789CS_IO_PIN     GPIO_Pin_7
+#define ST7789RST_PORT      GPIOC
+#define ST7789RST_IO_PIN    GPIO_Pin_5
+#define ST7789A0_PORT       GPIOB
+#define ST7789A0_IO_PIN     GPIO_Pin_1
+#define ST7789BL_PORT       GPIOC
+#define ST7789BL_IO_PIN     GPIO_Pin_8
+#define ST7789SCK_PORT      GPIOB
+#define ST7789SCK_IO_PIN    GPIO_Pin_0
+#define ST7789MOSI_PORT     GPIOA
+#define ST7789MOSI_IO_PIN   GPIO_Pin_15
+#define ST7789MISO_PORT     GPIOA
+#define ST7789MISO_IO_PIN   GPIO_Pin_14
+//pwm
+#define PWM0_PORT           GPIOB
+#define PWM0_IO_PIN         GPIO_Pin_8
+#define PWM1_PORT           GPIOB
+#define PWM1_IO_PIN         GPIO_Pin_9
+#define PWM2_PORT           GPIOB
+#define PWM2_IO_PIN         GPIO_Pin_10
+#define PWM3_PORT           GPIOB
+#define PWM3_IO_PIN         GPIO_Pin_11
+#define PWM4_PORT           GPIOB
+#define PWM4_IO_PIN         GPIO_Pin_12
+#define PWM5_PORT           GPIOB
+#define PWM5_IO_PIN         GPIO_Pin_13
+#define PWM6_PORT           GPIOB
+#define PWM6_IO_PIN         GPIO_Pin_14
+#define PWM7_PORT           GPIOB
+#define PWM7_IO_PIN         GPIO_Pin_15
+#define PWM8_PORT           GPIOD
+#define PWM8_IO_PIN         GPIO_Pin_2
+
+//16MFLASH
+#define FLASH16M_NCS_PORT     GPIOD
+#define FLASH16M_NCS_IO_PIN   GPIO_Pin_7
+#define FLASH16M_SCK_PORT     GPIOD
+#define FLASH16M_SCK_IO_PIN   GPIO_Pin_11
+#define FLASH16M_MOSI_PORT    GPIOD
+#define FLASH16M_MOSI_IO_PIN  GPIO_Pin_12
+#define FLASH16M_MISO_PORT    GPIOD
+#define FLASH16M_MISO_IO_PIN  GPIO_Pin_13
+
+//dcmi
+#define DCMI_LCD_RST_PIN                    (74)
+#define DCMI_LCD_CS_PIN                     (31)
+#define DCMI_LCD_CLK_PIN                    (17)
+#define DCMI_LCD_MOSI_PIN                   (15)
+#define DCMI_LCD_MISO_PIN                   (14)
+#define DCMI_LCD_A0_PIN                     (16)
+#define DCMI_LCD_BL_PIN                     (62)
+
+
+#define DCMI_CAMERA_SDA_PIN                 (40)
+#define DCMI_CAMERA_SCL_PIN                 (39)
+#define DCMI_CAMERA_RST_PIN                 (0xff)
+#define DCMI_CAMERA_PWDN_PIN                (49)
+#define DCMI_CAMERA_MCLK_PIN                (32)
+#define DCMI_CAMERA_PCLK_PIN                (34)
+#define DCMI_CAMERA_VSYNC_PIN               (38)
+#define DCMI_CAMERA_HSYNC_PIN               (37)
+#define DCMI_CAMERA_DATA_WIDTH              (8)
+#define DCMI_CAMERA_DATA0_PIN               (48)
+#define DCMI_CAMERA_DATA1_PIN               (47)
+#define DCMI_CAMERA_DATA2_PIN               (46)
+#define DCMI_CAMERA_DATA3_PIN               (45)
+#define DCMI_CAMERA_DATA4_PIN               (44)
+#define DCMI_CAMERA_DATA5_PIN               (43)
+#define DCMI_CAMERA_DATA6_PIN               (42)
+#define DCMI_CAMERA_DATA7_PIN               (41)
+
+//psram
+#define PSRAM_NCS_PIN                       (45)
+#define PSRAM_SCK_PIN                       (44)
+#define PSRAM_DATA0_PIN                     (52)
+#define PSRAM_DATA1_PIN                     (49)
+#define PSRAM_DATA2_PIN                     (50)
+#define PSRAM_DATA3_PIN                     (43)
+
+//i2c0
+#define I2C0PORT            MI2C0
+#define I2C0SCL_PORT        GPIOB
+#define I2C0SCL_IO_PIN      GPIO_Pin_2
+#define I2C0SDA_PORT        GPIOB
+#define I2C0SDA_IO_PIN      GPIO_Pin_3
+
+//i2c1
+#define I2C1PORT            MI2C1
+#define I2C1SCL_PORT        GPIOB
+#define I2C1SCL_IO_PIN      GPIO_Pin_4
+#define I2C1SDA_PORT        GPIOB
+#define I2C1SDA_IO_PIN      GPIO_Pin_5
+
+//sci7816
+#define SCI7816_RESET_PORT                  GPIOE
+#define SCI7816_RESET_IO_PIN                GPIO_Pin_14
+#define SCI7816_CLK_PORT                    GPIOE
+#define SCI7816_CLK_IO_PIN                  GPIO_Pin_15
+#define SCI7816_DATA_PORT                   GPIOE
+#define SCI7816_DATA_IO_PIN                 GPIO_Pin_13
+
+#define SCI7816_VCARD_PORT                  GPIOE
+#define SCI7816_VCARD_IO_PIN                GPIO_Pin_12
+#define SCI7816_DETECT_PORT                 GPIOC
+#define SCI7816_DETECT_IO_PIN               GPIO_Pin_1
+
+//sci17816
+#define SCI17816_RESET_PORT                  GPIOE
+#define SCI17816_RESET_IO_PIN                GPIO_Pin_10
+#define SCI17816_CLK_PORT                    GPIOA
+#define SCI17816_CLK_IO_PIN                  GPIO_Pin_7
+#define SCI17816_DATA_PORT                   GPIOA
+#define SCI17816_DATA_IO_PIN                 GPIO_Pin_6
+#define SCI17816_CARD1_EN_PORT               GPIOE
+#define SCI17816_CARD1_EN_IO_PIN             GPIO_Pin_11
+
+//fpc1020
+#define FPC1020_PORT 	        GPIOC
+#define FPC1020_CS_PIN       	GPIO_Pin_6
+#define FPC1020_SCLK_PIN 	    GPIO_Pin_1
+#define FPC1020_MOSI_PIN 	    GPIO_Pin_2
+#define FPC1020_MISO_PIN 	    GPIO_Pin_3
+#define FPC1020_RST_PIN 	    GPIO_Pin_4
+#define FPC1020_IRQ_PIN 	    GPIO_Pin_5
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOD
+#define NFC_RESET_PIN           GPIO_Pin_10
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_2
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_4
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_11
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_12
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_13
+
+#define UART2BTBAUD           115200
+#define UART2BT_TX_PORT       GPIOE
+#define UART2BT_TX_PIN        GPIO_Pin_0
+#define UART2BT_RX_PORT       GPIOD
+#define UART2BT_RX_PIN        GPIO_Pin_13
+#define UART2BT_UARTx         MUART2
+#define UART2BT_Tx_FUNC       UART2_TXD
+#define UART2BT_Rx_FUNC       UART2_RXD
+#define UART2BT_IRQN          10
+#define UART2BT_RTS_SOFT_PORT GPIOD     //鐢ㄤ簬m0鏍镐笌bt鏍歌蒋浠舵祦鎺�
+#define UART2BT_RTS_SOFT_PIN  GPIO_Pin_11
+
+#elif(BOARD_TYPE == APP_194_YC3173AB_DOORLOCK_V1_0_BOARD)
+//uart0
+#define PRINTPORT           MUART0
+#define PRINT_BAUD          (921600)
+#define PRINTRX_PORT        GPIOD
+#define PRINTRX_IO_PIN      GPIO_Pin_6
+#define PRINTTX_PORT        GPIOD
+#define PRINTTX_IO_PIN      GPIO_Pin_5
+#define PRINTRTS_PORT       GPIOB
+#define PRINTRTS_IO_PIN     GPIO_Pin_2
+#define PRINTCTS_PORT       GPIOB
+#define PRINTCTS_IO_PIN     GPIO_Pin_3
+
+//uart1
+#define UART1_BAUD          (921600)
+#define UART1RX_PORT        GPIOA
+#define UART1RX_IO_PIN      GPIO_Pin_0
+#define UART1TX_PORT        GPIOA
+#define UART1TX_IO_PIN      GPIO_Pin_1
+
+//nfc
+#define NFC_TEMER               TIM0
+#define NFC_SPI                 MSPI0
+#define NFC_RESET_PORT          GPIOE
+#define NFC_RESET_PIN           GPIO_Pin_0    //IO64
+#define NFC_12MCLK_PORT         GPIOD
+#define NFC_12MCLK_PIN          GPIO_Pin_7    //IO55
+#define NFC_SPI_CS_PORT         GPIOD
+#define NFC_SPI_CS_PIN          GPIO_Pin_11   //IO59
+#define NFC_SPI_SCK_PORT        GPIOD
+#define NFC_SPI_SCK_PIN         GPIO_Pin_13   //IO61
+#define NFC_SPI_MOSI_PORT       GPIOD
+#define NFC_SPI_MOSI_PIN        GPIO_Pin_14   //IO62
+#define NFC_SPI_MISO_PORT       GPIOD
+#define NFC_SPI_MISO_PIN        GPIO_Pin_15   //IO63
+
+
+//BT
+#define UART2BTBAUD           115200
+#define UART2BT_TX_PORT       GPIOB
+#define UART2BT_TX_PIN        GPIO_Pin_8
+#define UART2BT_RX_PORT       GPIOB
+#define UART2BT_RX_PIN        GPIO_Pin_7
+#define UART2BT_UARTx         MUART2
+#define UART2BT_Tx_FUNC       UART2_TXD
+#define UART2BT_Rx_FUNC       UART2_RXD
+#define UART2BT_IRQN          10
+#define UART2BT_RTS_SOFT_PORT GPIOD     //鐢ㄤ簬m0鏍镐笌bt鏍歌蒋浠舵祦鎺�
+#define UART2BT_RTS_SOFT_PIN  GPIO_Pin_11
+
+#endif
+
+#endif

bsp/yichip/yc3122-pos/Libraries/core/core_rv_31xx.h

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Development Team
+ * @file     yc_rom_api.h
+ * @brief    source file for setting rom_api
+ *
+ * Change Logs:
+ * Date           Author      Version        Notes
+ * 2021-06-23     wushengyan  V1.0.0         the first version
+ */
+#ifndef __RV_31XX_H__
+#define __RV_31XX_H__
+
+#ifdef __USE_YC_RISC_V__
+
+#include "type.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+/*end IO definitions*/
+
+
+#define __STATIC_INLINE                        static __inline
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC PLIC
+  - Core SysTick Register
+ ******************************************************************************/
+
+/********************  RISC-V REG START  **************************************/
+typedef struct
+{
+    __IO  uint32_t RV_PAUSE_EN                  : 1;
+    __IO  uint32_t RV_PAUSE_START               : 1;
+    __IO  uint32_t RV_DCLK_EN                   : 1;
+    __IO  uint32_t RV_QSORTCLK_EN               : 1;
+    __IO  uint32_t RV_BINCLK_EN                 : 1;
+    __IO  uint32_t DBG_STEP_EN                  : 1;
+    __IO  uint32_t FPU_STEP_DIS                 : 1;
+    __IO  uint32_t LONGP_STEP_EN                : 1;
+    __IO  uint32_t RV_CORECLK_EN                : 8;
+    __I   uint32_t RV_CTRL_RSVD                 : 16;
+    __IO  uint32_t RV_WKUP_SRC_EN               : 32;
+    __IO  uint32_t RV_PC_RTVEC                  : 32;
+    __IO  uint32_t RV_STACK_ADDR                : 32;
+} RVCtrl_TypeDef;
+
+typedef struct
+{
+    __IO  uint32_t ICE_CTRL                     : 16;
+    __IO  uint32_t ICE_CMD                      : 4;
+    __I   uint32_t ICE_CTRL_RSVD                : 12;
+    __IO  uint32_t ICE_BREAK0                   : 25;
+    __I   uint32_t ICE_BREAK0_RSVD              : 7;
+    __IO  uint32_t ICE_BREAK1                   : 25;
+    __I   uint32_t ICE_BREAK1_RSVD              : 7;
+    __IO  uint32_t ICE_REG_WDATA                : 32;
+    __I   uint32_t ICE_REG_RDATA                : 32;
+    __IO  uint32_t TRACE_ADDR                   : 25;
+    __I   uint32_t TRACE_ADDR_RSVD              : 7;
+    __I   uint32_t TRACE_FIFO_RDATA             : 25;
+    __I   uint32_t TRACE_FIFO_RDATA_RSVD        : 7;
+    __I   uint32_t EXE_ADDR                     : 32;
+    __I   uint32_t ICE_STATUS                   : 8;
+    __I   uint32_t ICE_STATUS_RSVD              : 24;                           //RV_CTRL
+} RVIce_TypeDef;
+
+typedef struct
+{
+    __IO  uint32_t BIN_CTRL_BLOCK_ENABLE        : 1;
+    __IO  uint32_t BIN_CTRL_GRID_MODE           : 1;
+    __IO  uint32_t BIN_CTRL_CUT_ENABLE          : 1;
+    __IO  uint32_t BIN_CTRL_SCALER_ENABLE       : 1;
+    __IO  uint32_t BIN_CTRL_INV_BIT_ENABLE      : 1;
+    __I   uint32_t BIN_CTRL_RSVD                : 3;
+    __IO  uint32_t RANGE                        : 8;
+    __IO  uint32_t SUB_HEIGHT                   : 8;
+    __IO  uint32_t SUB_WIDTH                    : 8;
+
+    __IO  uint32_t RAW_BIN_BASEADDR             : 24;
+    __I   uint32_t RAW_BIN_BASEADDR_RSVD        : 8;
+    __IO  uint32_t RGB_BASEADDR                 : 24;
+    __I   uint32_t RGB_BASEADDR_RSVD            : 8;
+    __IO  uint32_t AVG_BASEADDR                 : 24;
+    __I   uint32_t AVG_BASEADDR_RSVD            : 8;
+    __IO  uint32_t SCA_BIN_BASEADDR             : 24;
+    __I   uint32_t SCA_BIN_BASEADDR_RSVD        : 8;
+
+    __I   uint32_t BIN_STATUS                   : 32;
+    __I   uint32_t RAW_DOUT_ADDR_LOCK           : 24;
+    __I   uint32_t RAW_DOUT_ADDR_LOCK_RSVD      : 8;
+    __I   uint32_t SCA_DOUT_ADDR_LOCK           : 24;
+    __I   uint32_t SCA_DOUT_ADDR_LOCK_RSVD      : 8;
+    __IO  uint32_t QSORT_CTRL                   : 32;
+    __IO  uint32_t QSORT_BASEADDR               : 24;
+    __I   uint32_t QSORT_BASEADDR_RSVD          : 8;
+    __I   uint32_t QSORT_DONE                   : 1;
+    __I   uint32_t QSORT_DONE_RSVD              : 31;
+
+    __IO  uint32_t ONE_RGB_BASEADDR             : 24;
+    __I   uint32_t ONE_RGB_BASEADDR_RSVD        : 8;
+    __IO  uint32_t FAST_BIN_BASEADDR            : 24;
+    __I   uint32_t FAST_BIN_BASEADDR_RSVD       : 8;
+    __IO  uint32_t CANNY_BIN_BASEADDR           : 24;
+    __I   uint32_t CANNY_BIN_BASEADDR_RSVD      : 8;
+    __IO  uint32_t ONE_BIN_CTRL                 : 13;
+    __I   uint32_t ONE_BIN_CTRL_RSVD            : 19;
+    __IO  uint32_t FAST_BIN_CTRL                : 24;
+    __I   uint32_t FAST_BIN_CTRL_RSVD           : 8;
+    __IO  uint32_t CANNY_BIN_CTRL               : 23;
+    __I   uint32_t CANNY_BIN_CTRL_RSVD          : 9;
+    __IO  uint32_t CANNY_BIN_CTRL1              : 12;
+    __I   uint32_t CANNY_BIN_CTRL1_RSVD         : 20;
+    __IO  uint32_t ONE_BIN_STATUS               : 21;
+    __I   uint32_t ONE_BIN_STATUS_RSVD          : 11;
+    __IO  uint32_t FAST_BIN_BASEADDR_USED       : 24;
+    __I   uint32_t FAST_BIN_BASEADDR_USED_RSVD  : 8;
+    __IO  uint32_t CANNY_BIN_BASEADDR_USED      : 24;
+    __I   uint32_t CANNY_BIN_BASEADDR_USED_RSVD : 8;
+} RVBin_TypeDef;
+
+typedef struct
+{
+    __IO  uint32_t JTAG_SW_SEL                  :1;
+    __I   uint32_t JTAG_SW_SEL_RSVD             :3;
+    __IO  uint32_t DAP_REG_BASE_ADDR            :4;
+    __I   uint32_t DAP_CTRL_RSVD                :24;
+    __IO  uint32_t RV_TM_EN                     :1;
+    __IO  uint32_t RV_TM_EN_RSVD                :31;
+    __IO  uint32_t RV_TM_CNT                    :32;
+    __IO  uint32_t M0_TO_RV_IE                  :1;
+    __I   uint32_t M0_TO_RV_IE_RSVD             :7;
+    __IO  uint32_t M0_TO_RV_IRQ                 :1;
+    __I   uint32_t M0_TO_RV_IRQ_RSVD            :7;
+    __IO  uint32_t RV_TO_M0_IRQ_TRIG            :1;
+    __I   uint32_t RV_TO_M0_IRQ_TRIG_RSVD       :15;
+    __IO  uint32_t IRQ_SW_EN                    :1;
+    __IO  uint32_t IRQ_SW_PEND                  :1;
+    __I   uint32_t IRQ_SW_RSVD                  :6;
+    __IO  uint32_t IRQ_SW_CODE                  :8;
+    __I   uint32_t RV_SW_IRQ_RSVD               :16;
+}RVIrq_TypeDef;
+
+#define MPU_REGION_NUM    4
+typedef struct
+{
+    __IO uint8_t Protect_region[MPU_REGION_NUM];
+
+} RVMPUREGION_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t BaseAndLimit[MPU_REGION_NUM];
+
+} RVMPUBASE_TypeDef;
+
+#define BASE_LIMIT_REGION_NUM    4
+typedef struct
+{
+    __IO uint32_t MPU_ENABLE_CODE                   : 4;
+    __IO RVMPUREGION_TypeDef ICB_PROTECT;
+    __IO RVMPUREGION_TypeDef DTCM_PROTECT;
+    __IO RVMPUREGION_TypeDef ITCM_PROTECT;
+    __IO uint32_t  USER_START                       : 24;
+    __IO uint32_t  MPU_STS_CLR;
+    __I  uint32_t  FAULT_STATUS;
+    __I  uint32_t  FAULT_ADDR_ICB;
+    __I  uint32_t  FAULT_ADDR_DTCM;
+    __I  uint32_t  FAULT_ADDR_ITCM;
+    __IO RVMPUBASE_TypeDef  ICB_BASE;
+    __IO RVMPUBASE_TypeDef  DTCM_BASE;
+    __IO RVMPUBASE_TypeDef  ITCM_BASE;
+    __IO RVMPUBASE_TypeDef  ICB_LIMIT;
+    __IO RVMPUBASE_TypeDef  DTCM_LIMIT;
+    __IO RVMPUBASE_TypeDef  ITCM_LIMIT;
+} RVMPU_TypeDef;
+
+typedef struct
+{
+    __IO  uint32_t WDT_EN                       : 1;
+    __IO  uint32_t WDT_EN_LOCK                  : 1;
+    __IO  uint32_t WDT_ACT                      : 1;
+    __I   uint32_t WDT_CTRL_RSVD1               : 5;
+    __IO  uint32_t WDT_DIV                      : 4;
+    __I   uint32_t WDT_CTRL_RSVD2               : 20;
+    __IO  uint32_t WDT_KEY                      : 16;
+    __I   uint32_t WDT_KEY_RSVD                 : 16;
+    __IO  uint32_t WDT_RELOAD_VALUE             : 32;
+    __I   uint32_t WDT_CNT                      : 32;
+    __IO  uint32_t WDT_IRQ_EN                   : 1;
+    __I   uint32_t WDT_IRQ_EN_RSVD              : 31;
+    __IO  uint32_t WDT_IRQ                      : 1;
+    __I   uint32_t WDT_IRQ_RSVD                 : 31;
+} RVWdt_TypeDef;
+
+#define YC3122_RV_BASE                          (0x000E0000UL)   /* RV Base Address */
+
+#define RV_CTRL_BASEADDR                        (YC3122_RV_BASE + 0x00000) //0xe0000
+#define RV_ICE_BASEADDR                         (YC3122_RV_BASE + 0x00004) //0xe0004
+#define RV_BIN_BASEADDR                         (YC3122_RV_BASE + 0x00034) //0xe0034
+#define RV_IRQ_BASEADDR                         (YC3122_RV_BASE + 0x000D0) //0xe00d0
+#define RV_SYSTICK_BASEADDR                     (YC3122_RV_BASE + 0x000D0) //0xe00d4
+#define RV_MPU_BASEADDR                         (YC3122_RV_BASE + 0x00100) //0xe0100
+#define RV_IRQ_PRIO_BASEADDR                    (YC3122_RV_BASE + 0x01000) //0xe1000
+#define RV_IRQ_PEND_BASEADDR                    (YC3122_RV_BASE + 0x02000) //0xe2000
+#define RV_IRQ_ENAB_BASEADDR                    (YC3122_RV_BASE + 0x03000) //0xe3000
+#define RV_IRQ_THRD_BASEADDR                    (YC3122_RV_BASE + 0x04000) //0xe4000
+#define RV_IRQ_CLAM_BASEADDR                    (YC3122_RV_BASE + 0x04004) //0xe4004
+#define RV_WDT_BASEADDR                         (0xfb700) //0xfb700
+
+#define RV_CTRL1                             	((RVCtrl_TypeDef *)RV_CTRL_BASEADDR)
+#define RV_ICE                                  ((RVIce_TypeDef *)RV_ICE_BASEADDR)
+#define RV_BIN                                  ((RVBin_TypeDef *)RV_BIN_BASEADDR)
+#define RISC_IRQ                                ((RVIrq_TypeDef *)RV_IRQ_BASEADDR)
+
+/*risc-v mpu map start*/
+#define RV_MPU_ICB_PROTECT_BASE                 (RV_MPU_BASEADDR + 0x0004)
+#define RV_MPU_DTCM_PROTECT_BASE                (RV_MPU_ICB_PROTECT_BASE + 0x0004)
+#define RV_MPU_ITCM_PROTECT_BASE                (RV_MPU_DTCM_PROTECT_BASE + 0x0004)
+
+#define RV_MPU_ICB_BASE_BASE                    (RV_MPU_BASEADDR + 0x0040)
+#define RV_MPU_DTCM_BASE_BASE                   (RV_MPU_ICB_BASE_BASE + 0x0010)
+#define RV_MPU_ITCM_BASE_BASE                   (RV_MPU_DTCM_BASE_BASE + 0x0010)
+
+#define RV_MPU_ICB_LIMIT_BASE                   (RV_MPU_BASEADDR + 0x0080)
+#define RV_MPU_DTCM_LIMIT_BASE                  (RV_MPU_ICB_LIMIT_BASE + 0x0010)
+#define RV_MPU_ITCM_LIMIT_BASE                  (RV_MPU_DTCM_LIMIT_BASE + 0x0010)
+
+/*risc-v mpu reg start*/
+#define RVMPU                                   ((RVMPU_TypeDef *)RV_MPU_BASEADDR)
+#define ICB_PROTECTION                          ((RVMPUREGION_TypeDef *)RV_MPU_ICB_PROTECT_BASE)
+#define DTCM_PROTECTION                         ((RVMPUREGION_TypeDef *)RV_MPU_DTCM_PROTECT_BASE)
+#define ITCM_PROTECTION                         ((RVMPUREGION_TypeDef *)RV_MPU_ITCM_PROTECT_BASE)
+
+#define ICB_BASE                                ((RVMPUBASE_TypeDef *)RV_MPU_ICB_BASE_BASE)
+#define DTCM_BASE                               ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_BASE_BASE)
+#define ITCM_BASE                               ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_BASE_BASE)
+
+#define ICB_LIMIT                               ((RVMPUBASE_TypeDef *)RV_MPU_ICB_LIMIT_BASE)
+#define DTCM_LIMIT                              ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_LIMIT_BASE)
+#define ITCM_LIMIT                              ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_LIMIT_BASE)
+
+
+#define RV_WDT                                  ((RVWdt_TypeDef *)RV_WDT_BASEADDR)
+
+#define RV_IRQ_PRIO(x)				            *(volatile uint8_t*)(RV_IRQ_PRIO_BASEADDR + ((uint8_t)((uint8_t)(x)/2)))
+#define RV_IRQ_PEND(x)				            *(volatile uint8_t*)(RV_IRQ_PEND_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
+#define RV_IRQ_ENAB(x)				            *(volatile uint8_t*)(RV_IRQ_ENAB_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
+#define RV_IRQ_THOD					            *(volatile int*)(RV_IRQ_THRD_BASEADDR)
+#define RV_IRQ_CLAM					            *(volatile int*)(RV_IRQ_CLAM_BASEADDR)
+/********************  RISC-V REG END    **************************************/
+
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  uint32_t TM_EN;                   /*!< Offset: 0x000 (R/W)  SysTick Enable */
+  uint32_t TM_CNT;                  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+} SysTick_Type;
+
+
+
+#define SysTick             ((SysTick_Type   *)     RV_SYSTICK_BASEADDR  )   /*!< SysTick configuration struct */
+/******************************************************************************/
+
+
+/**
+ * @method	RV EnableIRQ
+ * @brief	  Enable IRQ
+ * @param	IRQn   : USB_IRQn...
+ * @retval NULL
+ */
+__STATIC_INLINE void RV_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    RV_IRQ_ENAB(IRQn) |= (uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
+  }
+}
+
+/**
+ * @method	RV DisableIRQ
+ * @brief	  Disable IRQ
+ * @param	IRQn   : USB_IRQn...
+ * @retval NULL
+ */
+__STATIC_INLINE void RV_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    RV_IRQ_ENAB(IRQn) &= ~(uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
+  }
+}
+
+/**
+ * @method	RV SetPriority
+ * @brief	  SetPriority IRQ
+ * @param	IRQn      : USB_IRQn...
+ * @param	priority  : 0~15
+ * @retval NULL
+ */
+__STATIC_INLINE void RV_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0 && priority > 0 && priority < 16)
+  {
+    RV_IRQ_PRIO(IRQn) |= (priority << (uint8_t)((uint8_t)(IRQn)%2)*4);
+  }
+}
+
+/**
+ * @method	RV Get Pending Interrupt
+ * @brief	  Reads The PLIC pending register returns the pending bit
+ * @param	IRQn      : USB_IRQn...
+ * @retval 0:  Interrupt status is not pending.
+ *         1:  Interrupt status is pending
+ */
+__STATIC_INLINE uint32_t RV_GetPendingIRQ(IRQn_Type IRQn)
+{
+
+}
+
+/**
+ * @method	RV Get Interrupt Priority
+ * @brief	  Reads the priority of a device specific interrupt
+ * @param	IRQn      : USB_IRQn...
+ * @retval  Interrupt Priority.
+ */
+__STATIC_INLINE uint32_t RV_GetPriority(IRQn_Type IRQn)
+{
+
+}
+
+/**
+ * @method NVIC_Configuration
+ * @brief  NVIC initialization function for risc-v.
+ * @param  IRQn: Interrupt vector numbers could be 0~31.
+ * @param  priority: Interrupt priority numbers could be 1~15.
+ * @param  newstate: enable or disable
+ * @retval None
+ */
+__STATIC_INLINE void NVIC_Configuration(IRQn_Type IRQn, uint32_t priority,FunctionalState newstate)
+{
+    if(newstate == ENABLE )
+    {
+    	RV_EnableIRQ(IRQn);
+    	RV_SetPriority(IRQn, priority);
+    }
+    else
+    {
+    	RV_DisableIRQ(IRQn);
+    	RV_SetPriority(IRQn, priority);
+    }
+}
+
+/**
+ * @method SysTick_Config
+ * @brief  Initializes the System Timer and its interrupt (priority default 1)
+ * @param  ticks: Number of ticks between two interrupts. (0~0xffffffff)
+ * @retval 0: FuncTion succeeded.
+ *         1: Function failed.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  SysTick->TM_CNT = ticks;
+  RV_EnableIRQ(34);    /*set systick priority*/
+  RV_SetPriority(34,15);
+  SysTick->TM_EN  = 1;
+
+  return (0UL);
+}
+
+/**
+ * @method __enable_irq
+ * @brief  Enable IRQ Interrupts
+ * @retval NONE.
+ */
+__STATIC_INLINE void __enable_irq(void)
+{
+	__asm("csrs mstatus,0x00000008");
+}
+
+/**
+ * @method __disable_irq
+ * @brief  Disable IRQ Interrupts
+ * @retval NONE.
+ */
+__STATIC_INLINE void __disable_irq(void)
+{
+	__asm("csrc mstatus,0x00000008");
+}
+
+/*make M0 and RV IRQ equ*/
+#define NVIC_EnableIRQ      RV_EnableIRQ
+#define NVIC_DisableIRQ     RV_DisableIRQ
+#define NVIC_SetPriority    RV_SetPriority
+#define NVIC_GetPendingIRQ  RV_GetPendingIRQ
+/*end*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif

bsp/yichip/yc3122-pos/Libraries/core/rom_api.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_rom_api.h
+ * @brief    source file for setting rom_api
+ *
+ * Change Logs:
+ * Date           Author      Version        Notes
+ * 2020-11-05     wushengyan         V1.0.0         the first version
+ */
+#ifndef __ROM_API_H__
+#define __ROM_API_H__
+
+#define YC3122_AA   (0)
+#define YC3122_AB   (1)
+#define IC_DEVICE   YC3122_AB
+#if (IC_DEVICE == YC3122_AA) 
+/* TIMER */
+#define FUNC_DELAY_US_ADDR                  (0x5030 + 1)
+#define FUNC_DELAY_MS_ADDR                  (0x5068 + 1)
+
+/* OTP */
+#define FUNC_INIT_OTP_ADDR                  (0x5468 + 1)
+#define FUNC_DEINIT_OTP_ADDR                (0x54c8 + 1)
+#define FUNC_READ_OTP_ADDR                  (0x5510 + 1)
+#define FUNC_WRITE_OTP_ADDR                 (0x5648 + 1)
+#define FUNC_READ_CHIPID_ADDR               (0x56ac + 1)
+#define FUNC_READ_CHIPLF_ADDR               (0x56ba + 1)
+
+/* LPM */
+#define FUNC_LIGHT_SLEEP_ADDR               (0x5338 + 1)
+#define FUNC_DEEP_SLEEP_ADDR                (0x535c + 1)
+
+/* QSPI */
+#define FUNC_ENC_WRITE_FLASH_ADDR           (0x67c0 + 1)
+#define FUNC_QSPI_FLASH_SECTORERASE_ADDR    (0x59a8 + 1)
+#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR     (0x59b4 + 1)
+#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR   (0x59c0 + 1)
+#define FUNC_QSPI_FLASH_WRITE_ADDR          (0x58e8 + 1)
+#define FUNC_QSPI_FLASH_READ_ADDR           (0x59ea + 1)
+#define FUNC_FLASH_BLANK_CHECK              (0x670c + 1)
+#define FUNC_PREFETCH                       (0x5398 + 1)
+#define FUNC_READ_FLASH_ID                  (0x5a54 + 1)
+
+#elif (IC_DEVICE == YC3122_AB)
+
+/* TIMER */
+#define FUNC_DELAY_US_ADDR                  (0x5020 + 1)
+#define FUNC_DELAY_MS_ADDR                  (0x5058 + 1)
+
+/* OTP */
+#define FUNC_INIT_OTP_ADDR                  (0x5458 + 1)
+#define FUNC_DEINIT_OTP_ADDR                (0x54b8 + 1)
+#define FUNC_READ_OTP_ADDR                  (0x5500 + 1)
+#define FUNC_WRITE_OTP_ADDR                 (0x5638 + 1)
+#define FUNC_READ_CHIPID_ADDR               (0x569c + 1)
+#define FUNC_READ_CHIPLF_ADDR               (0x56aa + 1)
+
+/* LPM */
+#define FUNC_LIGHT_SLEEP_ADDR               (0x5328 + 1)
+#define FUNC_DEEP_SLEEP_ADDR                (0x534c + 1)
+
+/* QSPI */
+#define FUNC_ENC_WRITE_FLASH_ADDR           (0x6798 + 1)
+#define FUNC_QSPI_FLASH_SECTORERASE_ADDR    (0x5998 + 1)
+#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR     (0x59a4 + 1)
+#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR   (0x59b0 + 1)
+#define FUNC_QSPI_FLASH_WRITE_ADDR          (0x58d8 + 1)
+#define FUNC_QSPI_FLASH_READ_ADDR           (0x59da + 1)
+#define FUNC_FLASH_BLANK_CHECK              (0x66e4 + 1)
+#define FUNC_PREFETCH                       (0x5388 + 1)
+#define FUNC_READ_FLASH_ID                  (0x5a44 + 1)
+#define FUNC_QSPI_FLASH_CMD                 (0x57ec + 1)
+
+#endif
+
+
+#endif

bsp/yichip/yc3122-pos/Libraries/core/system.c

@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_system.c
+ * @brief    source file for setting system
+ *
+ * Change Logs:
+ * Date           Author      Version        Notes
+ * 2020-11-05     wushengyan         V1.0.0         the first version
+ */
+
+#include <stdarg.h>
+#include "system.h"
+
+
+//*****************************************************************************
+//
+//! A simple  MyPrintf function supporting \%c, \%d, \%p, \%s, \%u,\%x, and \%X.
+//!
+//! \param format is the format string.
+//! \param ... are the optional arguments, which depend on the contents of the
+//! \return None.
+//
+//*****************************************************************************
+
+typedef struct _PrintPort_TypeDef_
+{
+    UART_TypeDef            *PrintUart;
+    GPIO_TypeDef            PrintRX_Port;
+    GPIO_Pin_TypeDef        PrintRX_Pin;
+    GPIO_TypeDef            PrintTX_Port;
+    GPIO_Pin_TypeDef        PrintTX_Pin;
+} PrintPort_TypeDef;
+
+static PrintPort_TypeDef PrintPort_Struct =
+{
+    .PrintUart    = PRINTPORT,
+    .PrintRX_Port = PRINTRX_PORT,
+    .PrintRX_Pin  = PRINTRX_IO_PIN,
+    .PrintTX_Port = PRINTTX_PORT,
+    .PrintTX_Pin  = PRINTTX_IO_PIN,
+};
+
+
+//#define SIM_PLATFORM
+
+void print_char(int data)
+{
+
+    volatile int *ptr;
+    ptr = (volatile int *)0xE0300;
+    *ptr = data;
+}
+
+void printfsend(uint8_t *buf, int len)
+{
+    uint8_t printbuf[256];
+    for (int i = 0; i < len; i++)
+    {
+        printbuf[i] = buf[i];
+#ifdef  SIM_PLATFORM
+        print_char(buf[i]);
+#endif
+    }
+#ifndef SIM_PLATFORM
+    //UART_SendBuf(PrintPort_Struct.PrintUart, printbuf, len);
+    UART_SendBuf(PRINTPORT, printbuf, len);
+#endif
+}
+
+void MyPrintf(char *format, ...)
+{
+    static const int8_t *const g_pcHex1 = "0123456789abcdef";
+    static const int8_t *const g_pcHex2 = "0123456789ABCDEF";
+
+    uint32_t ulIdx = 0, ulValue = 0, ulPos = 0, ulCount = 0, ulBase = 0, ulNeg = 0;
+    int8_t *pcStr = NULL, pcBuf[16] = {0}, cFill = 0;
+    char HexFormat;
+    va_list vaArgP;
+
+    va_start(vaArgP, format);
+
+    while (*format)
+    {
+        /* Find the first non-% character, or the end of the string. */
+        for (ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); ulIdx++)
+        {}
+
+        /* Write this portion of the string. */
+        if (ulIdx > 0)
+        {
+            printfsend((uint8_t *)format, ulIdx);
+        }
+
+        format += ulIdx;
+
+        if (*format == '%')
+        {
+            format++;
+
+            /* Set the digit count to zero, and the fill character to space */
+            /* (i.e. to the defaults) */
+            ulCount = 0;
+            cFill = ' ';
+
+again:
+            switch (*format++)
+            {
+            case '0':
+            case '1':
+            case '2':
+            case '3':
+            case '4':
+            case '5':
+            case '6':
+            case '7':
+            case '8':
+            case '9':
+            {
+                if ((format[-1] == '0') && (ulCount == 0))
+                {
+                    cFill = '0';
+                }
+
+                ulCount *= 10;
+                ulCount += format[-1] - '0';
+
+                goto again;
+            }
+
+            case 'c':
+            {
+                ulValue = va_arg(vaArgP, unsigned long);
+                printfsend((uint8_t *)&ulValue, 1);
+                break;
+            }
+
+            case 'd':
+            {
+                ulValue = va_arg(vaArgP, unsigned long);
+                ulPos = 0;
+
+                if ((long)ulValue < 0)
+                {
+                    ulValue = -(long)ulValue;
+                    ulNeg = 1;
+                }
+                else
+                {
+                    ulNeg = 0;
+                }
+
+                ulBase = 10;
+                goto convert;
+            }
+
+            case 's':
+            {
+                pcStr = (int8_t *)va_arg(vaArgP, char *);
+
+                for (ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
+                {}
+
+                printfsend((uint8_t *)pcStr, ulIdx);
+
+                if (ulCount > ulIdx)
+                {
+                    ulCount -= ulIdx;
+                    while (ulCount--)
+                    {
+                        printfsend((uint8_t *)" ", 1);
+                    }
+                }
+                break;
+            }
+
+            case 'u':
+            {
+                ulValue = va_arg(vaArgP, unsigned long);
+                ulPos = 0;
+                ulBase = 10;
+                ulNeg = 0;
+                goto convert;
+            }
+
+            case 'X':
+            {
+                ulValue = va_arg(vaArgP, unsigned long);
+                ulPos = 0;
+                ulBase = 16;
+                ulNeg = 0;
+                HexFormat = 'X';
+                goto convert;
+            }
+
+            case 'x':
+
+            case 'p':
+            {
+                ulValue = va_arg(vaArgP, unsigned long);
+                ulPos = 0;
+                ulBase = 16;
+                ulNeg = 0;
+                HexFormat = 'x';
+
+convert:
+                for (ulIdx = 1;
+                        (((ulIdx * ulBase) <= ulValue) &&
+                         (((ulIdx * ulBase) / ulBase) == ulIdx));
+                        ulIdx *= ulBase, ulCount--)
+                {
+                }
+
+                if (ulNeg)
+                {
+                    ulCount--;
+                }
+
+                if (ulNeg && (cFill == '0'))
+                {
+                    pcBuf[ulPos++] = '-';
+                    ulNeg = 0;
+                }
+
+                if ((ulCount > 1) && (ulCount < 16))
+                {
+                    for (ulCount--; ulCount; ulCount--)
+                    {
+                        pcBuf[ulPos++] = cFill;
+                    }
+                }
+
+                if (ulNeg)
+                {
+                    pcBuf[ulPos++] = '-';
+                }
+
+                for (; ulIdx; ulIdx /= ulBase)
+                {
+                    if (HexFormat == 'x')
+                        pcBuf[ulPos++] = g_pcHex1[(ulValue / ulIdx) % ulBase];//x
+                    else
+                        pcBuf[ulPos++] = g_pcHex2[(ulValue / ulIdx) % ulBase];//X
+                }
+
+                printfsend((uint8_t *)pcBuf, ulPos);
+                break;
+            }
+
+            case '%':
+            {
+                printfsend((uint8_t *)format - 1, 1);
+                break;
+            }
+
+            default:
+            {
+                printfsend((uint8_t *)"ERROR", 5);
+                break;
+            }
+            }/* switch */
+        }/* if */
+    }/* while */
+    va_end(vaArgP);
+}
+
+void printv(uint8_t *buf, uint32_t len, char *s)
+{
+    uint32_t i = 0;
+    uint32_t n = 0;
+    MyPrintf("\r\n%s:", s);
+    for (i = 0; i < len; i++)
+    {
+        if (i % 16 == 0)
+        {
+            MyPrintf("\r\n%08x:", n);
+            n += 16;
+        }
+        MyPrintf("%02x ", buf[i]);
+
+    }
+    MyPrintf("\r\n");
+}
+
+
+
+
+static void PrintPort_Init(void)
+{
+    UART_InitTypeDef   UART_InitStruct;
+    UART_InitStruct.BaudRate  = PRINT_BAUD;			//Configure serial port baud rate, the baud rate defaults to 128000.
+    UART_InitStruct.DataBits  = DATABITS_8B;
+    UART_InitStruct.StopBits  = STOPBITS_1;
+    UART_InitStruct.Parity    = YC_PARITY_NONE;
+    UART_InitStruct.FlowCtrl  = FLOWCTRL_NONE;
+    UART_InitStruct.RxMode    = MODE_RX_ENABLE;
+    UART_InitStruct.SmartCard = SMARTCARD_DISABLE;
+    UART_InitStruct.CommMode  = MODE_DUPLEX;
+
+    if (PrintPort_Struct.PrintUart == MUART0)
+    {
+        GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART0_RXD);
+        GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART0_TXD);
+    }
+    else if (PrintPort_Struct.PrintUart == MUART1)
+    {
+        GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART1_RXD);
+        GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART1_TXD);
+    }
+    else if (PrintPort_Struct.PrintUart == MUART2)
+    {
+        GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART2_RXD);
+        GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART2_TXD);
+    }
+    else if (PrintPort_Struct.PrintUart == MUART3)
+    {
+        GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART3_RXD);
+        GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART3_TXD);
+    }
+
+    UART_Init(PrintPort_Struct.PrintUart, &UART_InitStruct);
+    uint8_t print_irq = (PrintPort_Struct.PrintUart - MUART0) / (MUART1 - MUART0);
+    NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + print_irq));
+    NVIC_SetPriority((IRQn_Type)(UART0_IRQn + print_irq),1);
+}
+
+void PrintPort_Set(UART_TypeDef *UARTx)
+{
+    PrintPort_Struct.PrintUart = UARTx;
+
+//    if(UARTx == MUART1)
+//    {
+//        PrintPort_Struct.PrintRX_Port = UART1RX_PORT;
+//        PrintPort_Struct.PrintRX_Pin  = UART1RX_IO_PIN;
+//        PrintPort_Struct.PrintTX_Port = UART1TX_PORT;
+//        PrintPort_Struct.PrintTX_Pin  = UART1TX_IO_PIN;
+//    }
+}
+
+void Board_Init(void)
+{
+    /*fpga io func sel*/
+#if (BOARD_TYPE == FPGA_BOARD)
+
+    uint8_t fpga_io_func_sel_list[][2] =
+    {
+#ifdef __SPI0_FLASH_FPGA__
+        {0x02,0x01},
+        {0x08,0x01},
+        {0x21,0x40},
+#endif
+
+        {0x00,0x00},
+
+#ifdef __SPI1_FLASH_FPGA__
+        {0x05,0x01},
+        {0x08,0x01},
+        {0x21,0x80},
+#endif
+#ifdef __SCANNER_BF3007_BCTC_FPGA__
+        {0x01,0x01}, //func_sel1: ALT1 psram
+        {0x08,0x01}, //func_sel8: ALT1 tft
+        {0x09,0x01}, //func_sel9: ALT1 tft led
+        {0x02,0x01}, //func_sel9: ALT1 spia
+        {0x21,0x04}, //spi_sel:tft_spi_sel: SPIy
+        {0x20,0x02}, //iic_sel:iic0_sel: fingerprint i2c
+        {0x04,0x01}, //sel iica
+        {0x06,0x02}, //func_sel6: ALT2 fingerprint DCMI
+        {0x07,0x01}, //alt1 buzzer
+#endif
+    };
+    for(uint8_t i = 0; i < (sizeof(fpga_io_func_sel_list)/2); i ++)
+    {
+        FPGA_reg_write(fpga_io_func_sel_list[i][0],fpga_io_func_sel_list[i][1]);
+    }
+
+#endif
+
+    /*print init*/
+    PrintPort_Init();
+}
+
+void _assert_handler(const char *file, int line, const char *func)
+{
+#if defined (SDK_DEBUG)
+    if(PRINTPORT->CTRL.bit.RX_EN == MODE_RX_ENABLE) /*check printuart is init*/
+    {
+        MyPrintf("Assert trigger at file: %s line:%d func: %s\n ", file, line, func);
+    }
+#endif
+    while (1);
+}

bsp/yichip/yc3122-pos/Libraries/core/system.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_system.h
+ * @brief    source file for setting system
+ *
+ * Change Logs:
+ * Date           Author      Version        Notes
+ * 2020-11-05     wushengyan         V1.0.0         the first version
+ */
+#ifndef __SYSTEM_H__
+#define __SYSTEM_H__
+
+#define SDK_DEBUG	//Debug switch
+
+#include <string.h>
+#include "yc_uart.h"
+#include "rom_api.h"
+#include "board_config.h"
+
+#define BIT_SET(a,b) ((a) |= (1<<(b)))
+#define BIT_CLEAR(a,b) ((a) &= ~(1<<(b)))
+#define BIT_FLIP(a,b) ((a) ^= (1<<(b)))				//bit Negation
+#define BIT_GET(a,b) (((a) & (1<<(b)))>>(b))
+
+/**
+ * @brief Print format string to serial port 0.You need to initialize the serial port 0 before you use MyPrintf.
+ *
+ * @param format : format string
+ * @param ...: format parameter
+ */
+void MyPrintf(char *format, ...);
+
+void printv(uint8_t *buf, uint32_t len, char *s);
+
+void PrintPort_Set(UART_TypeDef *UARTx);
+
+void Board_Init(void);
+
+void _assert_handler(const char *file, int line, const char *func);
+
+#ifdef SDK_DEBUG
+#define _ASSERT(x)	\
+if (!(x))                                                                    \
+{                                                                             \
+    _assert_handler(__FILE__,__LINE__,__FUNCTION__);\
+}
+#else
+#define _ASSERT(x)
+#endif
+
+#define YC_DEBUG_LOG(type, message)                                          \
+do                                                                            \
+{                                                                             \
+    if (type)                                                                 \
+        MyPrintf message;                                                   \
+}                                                                             \
+while (0)
+
+#endif /*__SYSTEM_H__*/

bsp/yichip/yc3122-pos/Libraries/core/type.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_type.h
+ * @brief    source file for setting type
+ *
+ * Change Logs:
+ * Date           Author      Version        Notes
+ * 2020-11-05     wushengyan         V1.0.0         the first version
+ */
+
+#ifndef __TYPE_H__
+#define __TYPE_H__
+
+#if defined (__CC_ARM) || defined ( __ICCARM__ )
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef unsigned char      byte;
+typedef unsigned short     word;
+
+typedef signed char       int8_t;
+typedef signed short      int16_t;
+typedef signed int        int32_t;
+typedef signed long long  int64_t;
+#else
+#include "stdio.h"
+typedef unsigned char      byte;
+typedef unsigned short     word;
+#endif
+
+/** 
+  * @brief  __NOINLINE definition
+  */ 
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler 
+   ---------------- 
+*/
+#define __NOINLINE   noinline
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifndef Boolean
+typedef enum {FALSE = 0, TRUE =1} Boolean;
+#define IS_BOOLEAN(bool) ((bool == FALSE) || (bool == TRUE))
+#endif
+
+#ifndef FunctionalState
+typedef enum {DISABLE = 0, ENABLE =1} FunctionalState;
+#define IS_FUNCTIONAL_STATE(state) ((state== DISABLE) || (state == ENABLE))
+#endif
+
+#ifndef FunctionalState
+typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus;
+#define IS_ERROR_STATE(status) ((status== ERROR) || (status == SUCCESS))
+#endif
+
+#ifndef FlagStatus
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+#endif
+
+#ifndef YC_NULL
+#define YC_NULL                         (0)
+#endif
+
+#ifndef NULL
+#define NULL							(0)
+#endif
+
+#endif /*__TYPE_H__*/
+

bsp/yichip/yc3122-pos/Libraries/sdk/yc_exti.c

@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_exit.c
+ * @brief    source file for setting exit
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2021-12-24      yangzhengfeng      V1.0.0         Modify the register module configuration
+ * 2021-01-03      wangjingfan        V1.0.1         Compile error correction
+ * 2021-01-20      yangzhengfeng      V1.0.2         Update library function
+ */
+
+#include "yc_exti.h"
+
+/**
+  * @brief  Clear interrupt flag
+  * @param  EXTI_Line:EXTI_Line_0...EXTI_Line_4
+  * @param  EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
+  * @retval none
+  */
+void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
+{
+    _ASSERT(IS_EXTI_LINE(EXTI_Line));
+    _ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
+
+    MGPIO->IRQ_STATUS.reg[EXTI_Line] |= EXTI_PinSource;
+}
+
+/**
+  * @brief  Deinitializes the EXTI registers to default reset values.
+  * @param  none
+  * @retval none
+  */
+void EXTI_DeInit()
+{
+    uint32_t i;
+
+    for (i = 0; i < EXIT_Num; i++)
+    {
+        MGPIO->INTR.reg[i]           = 0;
+        MGPIO->IRQ_LEVEL.reg[i]            = 0;
+        MGPIO->IRQ_RISE.reg[i]            = 0;
+        MGPIO->IRQ_FALL.reg[i]            = 0;
+    }
+}
+
+/**
+  * @brief  get interrupt status
+  * @param  EXTI_Line:EXTI_Line_0...EXTI_Line_4
+  * @retval none
+  */
+uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line)
+{
+    _ASSERT(IS_EXTI_LINE(EXTI_Line));
+
+    return MGPIO->INTR.reg[EXTI_Line];
+}
+
+/**
+  * @brief  get interrupt pinsource status
+  * @param  EXTI_Line:EXTI_Line_0...EXTI_Line_4
+  * @param  EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
+  * @retval none
+  */
+uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
+{
+    _ASSERT(IS_EXTI_LINE(EXTI_Line));
+    _ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
+
+    if(MGPIO->INTR.reg[EXTI_Line] & EXTI_PinSource)
+    {
+        return ENABLE;
+    }
+    else
+    {
+        return DISABLE;
+    }
+
+}
+
+/**
+  * @brief  EXTI LineConfig
+  * @param  EXTI_Line:EXTI_Line_0...EXTI_Line_4
+  * @param  EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
+  * @param  EXTI_Trigger:EXTI Trigger mode
+  * @retval none
+  */
+void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger)
+{
+    _ASSERT(IS_EXTI_LINE(EXTI_Line));
+    _ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
+    _ASSERT(IS_TRIG_TYPEDEF(EXTI_Trigger));
+
+    uint16_t val_intr_lts,val_intr_rts,val_intr_fts,val_intr_en;
+    switch (EXTI_Trigger)
+    {
+    case EXTI_Trigger_Off:
+        val_intr_en  = ~EXTI_PinSource;
+        val_intr_lts = ~EXTI_PinSource;
+        val_intr_rts = ~EXTI_PinSource;
+        val_intr_fts = ~EXTI_PinSource;
+        break;
+    case EXTI_Trigger_HighLev:
+        val_intr_en  = EXTI_PinSource;
+        val_intr_lts = ~EXTI_PinSource;
+        val_intr_rts = ~EXTI_PinSource;
+        val_intr_fts = ~EXTI_PinSource;
+        break;
+    case EXTI_Trigger_LowLev:
+        val_intr_en  = EXTI_PinSource;
+        val_intr_lts = EXTI_PinSource;
+        val_intr_rts = ~EXTI_PinSource;
+        val_intr_fts = ~EXTI_PinSource;
+        break;
+    case EXTI_Trigger_Rising:
+        val_intr_en  = EXTI_PinSource;
+        val_intr_lts = ~EXTI_PinSource;
+        val_intr_rts = EXTI_PinSource;
+        val_intr_fts = ~EXTI_PinSource;
+        break;
+    case EXTI_Trigger_Falling:
+        val_intr_en  = EXTI_PinSource;
+        val_intr_lts = ~EXTI_PinSource;
+        val_intr_rts = ~EXTI_PinSource;
+        val_intr_fts = EXTI_PinSource;
+        break;
+    case EXTI_Trigger_Rising_Falling:
+        val_intr_en  = EXTI_PinSource;
+        val_intr_lts = ~EXTI_PinSource;
+        val_intr_rts = EXTI_PinSource;
+        val_intr_fts = EXTI_PinSource;
+        break;
+    default:
+        break;
+    }
+    if (EXTI_Trigger == EXTI_Trigger_Off)
+    {
+        MGPIO->INTR.reg[EXTI_Line] &= val_intr_en;
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  &= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  &= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  &= val_intr_fts;
+    }
+    else if (EXTI_Trigger == EXTI_Trigger_HighLev )
+    {
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  &= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  &= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  &= val_intr_fts;
+        MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
+    }
+    else if (EXTI_Trigger == EXTI_Trigger_LowLev )
+    {
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  |= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  &= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  &= val_intr_fts;
+        MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
+    }
+    else if (EXTI_Trigger == EXTI_Trigger_Rising )
+    {
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  &= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  |= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  &= val_intr_fts;
+        MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
+    }
+    else if (EXTI_Trigger == EXTI_Trigger_Falling )
+    {
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  &= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  &= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  |= val_intr_fts;
+        MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
+    }
+    else if (EXTI_Trigger == EXTI_Trigger_Rising_Falling )
+    {
+        MGPIO->IRQ_LEVEL.reg[EXTI_Line]  &= val_intr_lts;
+        MGPIO->IRQ_RISE.reg[EXTI_Line]  |= val_intr_rts;
+        MGPIO->IRQ_FALL.reg[EXTI_Line]  |= val_intr_fts;
+        MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
+    }
+}
+
+//extern void VBAT_IRQHandler(void);
+//extern void EXTI0_IRQHandler(void);
+//extern void EXTI1_IRQHandler(void);
+//extern void EXTI2_IRQHandler(void);
+//extern void EXTI3_IRQHandler(void);
+//extern void EXTI4_IRQHandler(void);
+
+//void GPIO_IRQHandler()
+//{
+//    uint8_t Exti_irq_index;
+
+//    NVIC_DisableIRQ(GPIO_IRQn);
+
+//    if (MSYSCTRL->CHGR_EVENT_IRQ.bit.VBAT_OV & MSYSCTRL->CHGR_EVENT_ICTRL.bit.VBAT_OV_IE)
+//    {
+//        //VBAT_IRQHandler();
+//    }
+
+//    Exti_irq_index = MGPIO->IRQ_NUM.reg;
+//    if(MGPIO->INTR.reg[Exti_irq_index/EXIT_Pin_Num] &(1 << (Exti_irq_index%EXIT_Pin_Num)))
+//    {
+//        switch (Exti_irq_index/EXIT_Pin_Num)
+//        {
+//        case EXTI_Line_0:
+//            EXTI0_IRQHandler();
+//            break;
+//        case EXTI_Line_1:
+//            EXTI1_IRQHandler();
+//            break;
+//        case EXTI_Line_2:
+//            EXTI2_IRQHandler();
+//            break;
+//        case EXTI_Line_3:
+//            EXTI3_IRQHandler();
+//            break;
+
+//        case EXTI_Line_4:
+//            EXTI4_IRQHandler();
+//            break;
+//        default:
+//            break;
+//        }
+//        EXTI_ClearITPendingBit((EXTI_LineTypeDef)(Exti_irq_index/EXIT_Pin_Num),(EXTI_PIN_TypeDef)(BIT(Exti_irq_index%EXIT_Pin_Num)));
+//    }
+//    NVIC_EnableIRQ(GPIO_IRQn);
+//}
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_exti.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_exit.h
+ * @brief    source file for setting exit
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2021-12-24      yangzhengfeng      V1.0.0         Modify the register module configuration
+ * 2021-01-03      wangjingfan        V1.0.1         Compile error correction
+ */
+
+#ifndef __YC_EXTI_H__
+#define __YC_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "yc3122.h"
+#include "yc_gpio.h"
+
+/**
+ * @brief  EXTI Trigger enumeration
+ */
+typedef enum
+{
+    EXTI_Trigger_Off            = 0,
+    EXTI_Trigger_HighLev        = 1,
+    EXTI_Trigger_LowLev         = 2,
+    EXTI_Trigger_Rising         = 3,
+    EXTI_Trigger_Falling        = 4,
+    EXTI_Trigger_Rising_Falling = 5,
+    EXTI_Trigger_DEFAULT_VAL    = 0xff
+} EXTI_TriggerTypeDef;
+
+#define IS_TRIG_TYPEDEF(TRIGTYPE)  ((TRIGTYPE) == EXTI_Trigger_Off            || \
+                                    (TRIGTYPE) == EXTI_Trigger_HighLev        || \
+                                    (TRIGTYPE) == EXTI_Trigger_LowLev         || \
+                                    (TRIGTYPE) == EXTI_Trigger_Rising         || \
+                                    (TRIGTYPE) == EXTI_Trigger_Falling        || \
+                                    (TRIGTYPE) == EXTI_Trigger_Rising_Falling)
+
+/**
+ * @brief  EXTI Trigger source
+ */
+typedef enum
+{
+    EXTI_Line_0             = 0,
+    EXTI_Line_1             = 1,
+    EXTI_Line_2             = 2,
+    EXTI_Line_3             = 3,
+    EXTI_Line_4             = 4,
+    EXTI_Line_DEFAULT_VAL   = 0xff
+} EXTI_LineTypeDef;
+
+#define IS_EXTI_LINE(LINE)     (((LINE) == EXTI_Line_0) || \
+                                ((LINE) == EXTI_Line_1) || \
+                                ((LINE) == EXTI_Line_2) || \
+                                ((LINE) == EXTI_Line_3) || \
+                                ((LINE) == EXTI_Line_4))
+
+#define IS_EXTI_PIN_SOURCE(PIN)  (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define EXTI_MODE_TypeDef              GPIO_MODULE_TypeDef
+#define EXTI_PIN_TypeDef               GPIO_Pin_TypeDef
+#define EXIT_Num                       GPIO_PORT_NUM
+#define EXIT_Pin_Num                   GPIO_PIN_NUM
+
+void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
+void EXTI_DeInit(void);
+uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line);
+uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
+void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __YC_EXTI_H__ */
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_gpio.c

@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_gpio.c
+ * @brief    source file for setting gpio
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2021-01-20      yangzhengfeng      V1.0.2         Update library function
+ * 2021-07-29      xubo               V1.0.3         Update library function
+ */
+
+#include "yc_gpio.h"
+
+uint8_t const  UnMapTb[256] = {
+    0u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x00 to 0x0F */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x10 to 0x1F */
+    5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x20 to 0x2F */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x30 to 0x3F */
+    6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x40 to 0x4F */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x50 to 0x5F */
+    5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x60 to 0x6F */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x70 to 0x7F */
+    7u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x80 to 0x8F */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x90 to 0x9F */
+    5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xA0 to 0xAF */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xB0 to 0xBF */
+    6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xC0 to 0xCF */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xD0 to 0xDF */
+    5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xE0 to 0xEF */
+    4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u  /* 0xF0 to 0xFF */
+};
+
+uint8_t UnMap(uint16_t x)
+{
+    uint8_t lx = x;
+    uint8_t hx = x >> 8;
+    if(lx)
+    {
+        return  UnMapTb[lx];
+    }
+    else
+    {
+        return  UnMapTb[hx] + 8;
+    }
+}
+
+/**
+ * @method GPIO_Config
+ * @brief  config gpio function(Only one can be configured at a time)
+ * @param  GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
+ * @param  GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)(Only one can be configured at a time)
+ * @param  function:gpio function
+ * @retval none
+ */
+void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+    _ASSERT(IS_GPIO_FUN(function));
+
+    MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = function;
+}
+
+/**
+ * @method GPIO_Init
+ * @brief  gpio mode Init
+ * @param  GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
+ * @param  GPIO_InitStruct:GPIO_InitStruct
+ * @retval none
+ */
+void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+    _ASSERT(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+
+    for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
+    {
+        if(GPIO_InitStruct->GPIO_Pin & (BIT0<<i))
+        {
+            MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = GPIO_InitStruct->GPIO_Mode << 6;
+        }
+    }
+}
+
+/**
+ * @method GPIO_PullUpCmd
+ * @brief  gpio pull up
+ * @param  GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_7)
+ * @param  NewState: new state of the port pin Pull Up.(ENABLE or DISABLE)
+ * @retval none
+ */
+void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN(GPIO_Pin));
+    _ASSERT(IS_FUNCTIONAL_STATE(NewState));
+    uint8_t i = 0;
+
+    if (ENABLE == NewState)
+    {
+        for(i = 0; i<GPIO_PIN_NUM; i++)
+        {
+            MGPIO->CTRL.bit[GPIO_GetNum(GPIOx,(GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IPU;
+        }
+    }
+    else if (DISABLE == NewState)
+    {
+        for(i = 0; i<GPIO_PIN_NUM; i++)
+        {
+            MGPIO->CTRL.bit[GPIO_GetNum(GPIOx, (GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IN_FLOATING;
+        }
+    }
+}
+
+/**
+ * @method GPIO_ReadInputData
+ * @brief  Reads the GPIO input data for 2byte.
+ * @param  GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
+ * @retval GPIO input data.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+
+    return MGPIO->IN_LEVEL.reg[GPIOx];
+}
+
+/**
+ * @method GPIO_ReadInputDataBit
+ * @brief  Reads the GPIO input data(status) for bit.
+ * @param  GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval The input bit
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+
+    if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        return (uint8_t)Bit_SET;
+    }
+    return (uint8_t)Bit_RESET;
+}
+
+/**
+ * @method GPIO_ReadOutputData
+ * @brief  Reads the GPIO output data(status) for byte.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @retval GPIO output data(status).
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+
+    return MGPIO->IN_LEVEL.reg[GPIOx];
+}
+
+/**
+ * @method GPIO_ReadOutputDataBit
+ * @brief  Reads the GPIO output data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval The output status
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+    
+    if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        return (uint8_t)Bit_SET;
+    }
+    return (uint8_t)Bit_RESET;
+}
+
+/**
+ * @method GPIO_ResetBit
+ * @brief  Reset the GPIO bit data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval none
+ */
+void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+    MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)]    = OUTPUT_LOW;
+}
+/**
+ * @method GPIO_ResetBits
+ * @brief  Reset the GPIO bit data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval none
+ */
+void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN(GPIO_Pin));
+    for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
+    {
+        if(GPIO_Pin & (BIT0<<i))
+        {
+            MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))]    = OUTPUT_LOW;
+        }
+    }
+}
+
+/**
+ * @method GPIO_SetBit
+ * @brief  Set the GPIO bit data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval none
+ */
+void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+    MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)]    = OUTPUT_HIGH;
+}
+
+/**
+ * @method GPIO_SetBits
+ * @brief  Set the GPIO bit data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @retval none
+ */
+void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN(GPIO_Pin));
+    for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
+    {
+        if(GPIO_Pin & (BIT0<<i))
+        {
+            MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))]    = OUTPUT_HIGH;
+        }
+    }
+}
+
+/**
+ * @method GPIO_Write
+ * @brief  Write the GPIO group data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  value:  select the value to read.(0 or 1)
+ * @retval none
+ */
+void GPIO_Write(GPIO_TypeDef  GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN(GPIO_Pin));
+    GPIO_SetBits(GPIOx, GPIO_Pin);
+    GPIO_ResetBits(GPIOx, (GPIO_Pin_TypeDef)(~GPIO_Pin));
+}
+
+/**
+ * @method GPIO_WriteBit
+ * @brief  Write the GPIO bit data(status) for bit.
+ * @param  GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @param  BitVal: select the value to read.(0 or 1)
+ * @retval none
+ */
+void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal)
+{
+    _ASSERT(IS_GPIO_PORT(GPIOx));
+    _ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
+
+    if (BitVal == Bit_SET)
+        GPIO_SetBit(GPIOx, GPIO_Pin);
+    else if (BitVal == Bit_RESET)
+        GPIO_ResetBit(GPIOx, GPIO_Pin);
+}
+
+
+/**
+ * @method GPIO_ODSet
+ * @brief  Set the GPIO OD MODE
+ * @param  GPIOx_Drv: where x can be (GPIOA_Drv...GPIOE_Drv) to select the GPIO_Drv group.
+ * @param  GPIO_Pin:  select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
+ * @param  Drvtype: select the value to set DRV value.(0x00....0x11)
+ * @retval none
+ */
+void GPIO_ODSet(GPIO_OD_TypeDef GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set)
+{
+    _ASSERT(IS_GPIO_OD(GPIOx_OD));
+    _ASSERT(IS_GPIO_MODE_OUT(GPIO_OD_Set));
+
+    (MGPIO->OD_CTRL.reg) |= (GPIO_OD_Set << GPIOx_OD);
+}
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_gpio.h

@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_gpio.h
+ * @brief    source file for setting gpio
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2020-12-23     yangzhengfeng       V1.1.0         Modify the register module configuration
+ */
+
+#ifndef __YC_GPIO_H__
+#define __YC_GPIO_H__
+
+#include "yc3122.h"
+#include "system.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint8_t UnMap(uint16_t x);
+#define GPIO_CONFIG(x)         *((volatile uint8_t*)(MGPIO_BASE + x))
+#define GPIO_GetNum(port, pin)    ((port * GPIO_PIN_NUM) + UnMap(pin))
+#define GPIO_OD_TypeDef        uint8_t
+#define GPIO_FUN_TYPEDEF       uint8_t
+#define GPIO_PORT_NUM          5
+#define GPIO_PIN_NUM           16
+
+#define GPIO_OD_PORTA_10           ((GPIO_OD_TypeDef)0x00)     /*!< Pin 10 selected */
+#define GPIO_OD_PORTB_06           ((GPIO_OD_TypeDef)0x01)     /*!< Pin 20 selected */
+#define GPIO_OD_PORTC_01           ((GPIO_OD_TypeDef)0x02)     /*!< Pin 33 selected */
+#define GPIO_OD_PORTC_08           ((GPIO_OD_TypeDef)0x03)     /*!< Pin 40 selected */
+#define GPIO_OD_PORTD_00           ((GPIO_OD_TypeDef)0x04)     /*!< Pin 48 selected */
+#define GPIO_OD_PORTD_12           ((GPIO_OD_TypeDef)0x05)     /*!< Pin 60 selected */
+#define GPIO_OD_PORTE_06           ((GPIO_OD_TypeDef)0x06)     /*!< Pin 76 selected */
+#define GPIO_OD_PORTE_12           ((GPIO_OD_TypeDef)0x07)     /*!< Pin 70 selected */
+
+#define IS_GPIO_OD(port_od)         ((port_od == GPIO_OD_PORTA_10) || \
+                                    (port_od == GPIO_OD_PORTB_06) || \
+                                    (port_od == GPIO_OD_PORTC_01) || \
+                                    (port_od == GPIO_OD_PORTC_08) || \
+                                    (port_od == GPIO_OD_PORTD_00) || \
+                                    (port_od == GPIO_OD_PORTD_12) || \
+                                    (port_od == GPIO_OD_PORTE_06) || \
+                                    (port_od == GPIO_OD_PORTE_12))
+typedef enum
+{
+    GPIO_Pin_0 = BIT0,
+    GPIO_Pin_1 = BIT1,
+    GPIO_Pin_2 = BIT2,
+    GPIO_Pin_3 = BIT3,
+    GPIO_Pin_4 = BIT4,
+    GPIO_Pin_5 = BIT5,
+    GPIO_Pin_6 = BIT6,
+    GPIO_Pin_7 = BIT7,
+    GPIO_Pin_8 = BIT8,
+    GPIO_Pin_9 = BIT9,
+    GPIO_Pin_10 = BIT10,
+    GPIO_Pin_11 = BIT11,
+    GPIO_Pin_12 = BIT12,
+    GPIO_Pin_13 = BIT13,
+    GPIO_Pin_14 = BIT14,
+    GPIO_Pin_15 = BIT15
+} GPIO_Pin_TypeDef;
+
+#define IS_GPIO_PIN(PIN)   (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
+#define IS_GPIO_PIN_SINGLE(PIN)    ((PIN == GPIO_Pin_0) || \
+                                    (PIN == GPIO_Pin_1) || \
+                                    (PIN == GPIO_Pin_2) || \
+                                    (PIN == GPIO_Pin_3) || \
+                                    (PIN == GPIO_Pin_4) || \
+                                    (PIN == GPIO_Pin_5) || \
+                                    (PIN == GPIO_Pin_6) || \
+                                    (PIN == GPIO_Pin_7) || \
+                                    (PIN == GPIO_Pin_8) || \
+                                    (PIN == GPIO_Pin_9) || \
+                                    (PIN == GPIO_Pin_10) || \
+                                    (PIN == GPIO_Pin_11) || \
+                                    (PIN == GPIO_Pin_12) || \
+                                    (PIN == GPIO_Pin_13) || \
+                                    (PIN == GPIO_Pin_14) || \
+                                    (PIN == GPIO_Pin_15))
+
+typedef enum
+{
+    GPIOA = 0,
+    GPIOB,
+    GPIOC,
+    GPIOD,
+    GPIOE
+} GPIO_TypeDef;
+
+#define IS_GPIO_PORT(port) (port <= GPIOE)
+
+/*******************  Bit definition for gpio funaction  **********************/
+#define INPUT                   ((GPIO_FUN_TYPEDEF) 0)
+#define QSPI_NCS                ((GPIO_FUN_TYPEDEF) 2)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define QSPI_SCK                ((GPIO_FUN_TYPEDEF) 3)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define QSPI_IO0                ((GPIO_FUN_TYPEDEF) 4)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define QSPI_IO1                ((GPIO_FUN_TYPEDEF) 5)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define QSPI_IO2                ((GPIO_FUN_TYPEDEF) 6)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define QSPI_IO3                ((GPIO_FUN_TYPEDEF) 7)        /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
+#define UART0_TXD               ((GPIO_FUN_TYPEDEF) 8)
+#define UART0_RXD               ((GPIO_FUN_TYPEDEF) 9)
+#define UART0_RTS               ((GPIO_FUN_TYPEDEF)10)
+#define UART0_CTS               ((GPIO_FUN_TYPEDEF)11)
+#define UART1_TXD               ((GPIO_FUN_TYPEDEF)12)        /*Mapping the scope GPIO[47:0]*/
+#define UART1_RXD               ((GPIO_FUN_TYPEDEF)13)        /*Mapping the scope GPIO[47:0]*/
+#define UART1_RTS               ((GPIO_FUN_TYPEDEF)14)        /*Mapping the scope GPIO[47:0]*/
+#define UART1_CTS               ((GPIO_FUN_TYPEDEF)15)        /*Mapping the scope GPIO[47:0]*/
+#define UART2_TXD               ((GPIO_FUN_TYPEDEF)36)        /*Mapping the scope GPIO[79:40]*/
+#define UART2_RXD               ((GPIO_FUN_TYPEDEF)37)        /*Mapping the scope GPIO[79:40]*/
+#define UART2_RTS               ((GPIO_FUN_TYPEDEF)38)        /*Mapping the scope GPIO[79:40]*/
+#define UART2_CTS               ((GPIO_FUN_TYPEDEF)39)        /*Mapping the scope GPIO[79:40]*/
+#define UART3_TXD               ((GPIO_FUN_TYPEDEF)53)        /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
+#define UART3_RXD               ((GPIO_FUN_TYPEDEF)53)        /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
+#define UART3_RTS               ((GPIO_FUN_TYPEDEF)53)        /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
+#define UART3_CTS               ((GPIO_FUN_TYPEDEF)53)        /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
+#define PWM_OUT                 ((GPIO_FUN_TYPEDEF)16)        /*Each group of 8 GPIOs is mapped to PWM0~7*/
+#define PWM_OUT8                ((GPIO_FUN_TYPEDEF)17)        /*Mapping the scope GPIO[79:48]*/
+#define PWM_OUT01               ((GPIO_FUN_TYPEDEF)40)        /*GPIO_INDEX%8 is not a 0 and 1 pin, each two is a group, respectively mapped to PWM0/PWM1*/
+#define PWM_OUT23               ((GPIO_FUN_TYPEDEF)41)        /*GPIO_INDEX%8 is not a 2 and 3 pin, each two is a group, respectively mapped to PWM2/PWM3*/
+#define DCMI_PCLK               ((GPIO_FUN_TYPEDEF)18)
+#define DCMI_VSYNC              ((GPIO_FUN_TYPEDEF)19)
+#define DCMI_HSYNC              ((GPIO_FUN_TYPEDEF)20)
+#define DCMI_D0                 ((GPIO_FUN_TYPEDEF)21)
+#define DCMI_D1                 ((GPIO_FUN_TYPEDEF)22)
+#define DCMI_D0_D13             ((GPIO_FUN_TYPEDEF)23)        /*GPIO[7] to GPIO[76] is a group of 14, which are mapped to D13 to D0 respectively*/
+#define SPID_SDIO               ((GPIO_FUN_TYPEDEF)27)        /*Every 3 GPIOs are a group, which are respectively mapped to SPI0_SDIO/SPI1_SDIO/SPI2_SDIO*/
+#define SPID0_NCS               ((GPIO_FUN_TYPEDEF)24)        /*Mapping the scope GPIO[79:0]*/
+#define SPID0_SCK               ((GPIO_FUN_TYPEDEF)25)        /*Mapping the scope GPIO[79:0]*/
+#define SPID0_MOSI              ((GPIO_FUN_TYPEDEF)26)        /*Mapping the scope GPIO[79:0]*/
+#define SPID0_MISO              ((GPIO_FUN_TYPEDEF)28)        /*Mapping the scope GPIO[79:0]*/
+#define SPID1_NCS               ((GPIO_FUN_TYPEDEF)48)        /*Mapping the scope GPIO[79:0]*/
+#define SPID1_SCK               ((GPIO_FUN_TYPEDEF)49)        /*Mapping the scope GPIO[79:0]*/
+#define SPID1_MOSI              ((GPIO_FUN_TYPEDEF)50)        /*Mapping the scope GPIO[79:0]*/
+#define SPID1_MISO              ((GPIO_FUN_TYPEDEF)52)        /*Mapping the scope GPIO[79:0]*/
+#define SPID_SLV_IN             ((GPIO_FUN_TYPEDEF)29)        /*Each of 6 GPIOs is a group, which are mapped to MSPI0~2 NCS_IN/SCK_IN respectively*/
+#define XTAL32K                 ((GPIO_FUN_TYPEDEF)30)        /*Mapping the scope GPIO[15:0] and [74:48]*/
+#define HSPI_NCS                ((GPIO_FUN_TYPEDEF)31)        /*Map to all pins*/
+#define HSPI_SCK                ((GPIO_FUN_TYPEDEF)32)        /*Map to all pins*/
+#define HSPI_MOSI               ((GPIO_FUN_TYPEDEF)33)        /*Map to all pins*/
+#define HSPI_MISO               ((GPIO_FUN_TYPEDEF)34)        /*Map to all pins*/
+#define DAC_OUT                 ((GPIO_FUN_TYPEDEF)35)        /*Each group of 2 GPIOs is mapped to Out P/Out N respectively*/
+#define SDIO                    ((GPIO_FUN_TYPEDEF)42)        /*Each of 6 GPIOs is a group mapped to SDIO_CLK/SDIO_CMD/DAT0/DAT1/DAT2/DAT3*/
+#define PSRAM_NCS               ((GPIO_FUN_TYPEDEF)43)
+#define PSRAM_SCK               ((GPIO_FUN_TYPEDEF)44)
+#define PSRAM_DATA_0            ((GPIO_FUN_TYPEDEF)45)        /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
+#define PSRAM_DATA_1            ((GPIO_FUN_TYPEDEF)45)        /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
+#define PSRAM_DATA_2            ((GPIO_FUN_TYPEDEF)45)        /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
+#define PSRAM_DATA_3            ((GPIO_FUN_TYPEDEF)45)        /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
+#define JTAG_RV_TCK             ((GPIO_FUN_TYPEDEF)46)        /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
+#define JTAG_RV_TMS             ((GPIO_FUN_TYPEDEF)46)        /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
+#define JTAG_RV_TDI             ((GPIO_FUN_TYPEDEF)46)        /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
+#define JTAG_RV_TDO             ((GPIO_FUN_TYPEDEF)46)        /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
+#define I2C0_SCL                ((GPIO_FUN_TYPEDEF)58)
+#define I2C0_SDA                ((GPIO_FUN_TYPEDEF)59)
+#define I2C1_SCL                ((GPIO_FUN_TYPEDEF)47)
+#define I2C1_SDA                ((GPIO_FUN_TYPEDEF)47)
+#define SCI7816_IO              ((GPIO_FUN_TYPEDEF)56)
+#define SCI7816_IO2             ((GPIO_FUN_TYPEDEF)51)
+#define NFC_CLK_OUT             ((GPIO_FUN_TYPEDEF)55)
+#define ICE                     ((GPIO_FUN_TYPEDEF)57)
+#define JTAG_SWCLK              ((GPIO_FUN_TYPEDEF)60)        /*The first 16 pins are mapped to SWCLK, and the latter pins are mapped to SWCLK/SWDIO for a group of 2 GPIOs*/
+#define JTAG_SWDIO              ((GPIO_FUN_TYPEDEF)61)        /*The first 16 pins are mapped to SWDIO*/
+#define OUTPUT_LOW              ((GPIO_FUN_TYPEDEF)62)
+#define OUTPUT_HIGH             ((GPIO_FUN_TYPEDEF)63)
+#define PULL_PU                 ((GPIO_FUN_TYPEDEF)64)
+#define PULL_PD                 ((GPIO_FUN_TYPEDEF)128)
+#define ANALOG                  ((GPIO_FUN_TYPEDEF)192)
+#define IS_GPIO_FUN(fun) (fun <= 0xff)
+
+#define IS_GPIO_MODE(mode)  (((mode) == GPIO_Mode_IN_FLOATING) || \
+                            ((mode) == GPIO_Mode_IPU)         || \
+                            ((mode) == GPIO_Mode_IPD)         || \
+                            ((mode) == GPIO_Mode_AIN)         || \
+                            ((mode) == GPIO_Mode_Out_PP))
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET   = 1
+} BitAction;
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+typedef enum
+{
+    GPIO_Mode_IN_FLOATING = 0x00,
+    GPIO_Mode_IPU         = 0x01,
+    GPIO_Mode_IPD         = 0x02,
+    GPIO_Mode_AIN         = 0x03,
+    GPIO_Mode_Out_PP      = 0x3E    /*!< analog signal mode */
+} GPIO_ModeTypeDef;
+
+/**
+  * @brief Configuration GPIO OD enumeration
+  */
+typedef enum
+{
+    GPIO_Mode_OD_RESET  = 0x0,
+    GPIO_Mode_OD_SET    = 0x1
+} GPIO_ODTypeDef;
+
+#define IS_GPIO_MODE_OUT(mode)     (((mode) == GPIO_Mode_OD_RESET) || \
+                                    ((mode) == GPIO_Mode_OD_SET))
+
+/**
+ * @brief  GPIO Init structure definition
+ */
+typedef struct
+{
+    GPIO_Pin_TypeDef GPIO_Pin;
+    GPIO_ModeTypeDef GPIO_Mode;
+} GPIO_InitTypeDef;
+
+uint32_t GPIO_GetGPIONum(GPIO_TypeDef GPIOx);
+void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function);
+void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
+void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
+void GPIO_Write(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal);
+void GPIO_ODSet(uint8_t GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __YC_GPIO_H__ */
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_qspi.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_qspi.h
+ * @brief    This file contains all the functions prototypes for the IFlash library.
+ *
+ * Change Logs:
+ * Date           Author             Version        Notes
+ * 2021-08-14     wushengyan         V1.0.0         the first version
+ */
+
+#ifndef __YC_QSPI_H__
+#define __YC_QSPI_H__
+#include "yc3122.h"
+
+#define BOOT_UART_DOWNLOAD_FLAG         0x5a5aa5a5
+#define BOOT_USB_DOWNLOAD_FLAG          0xaa5555aa
+#define BOOT_AUTO_SELECT_FLAG           0xffffffff
+
+#define ENC_BULK_BUF_SIZE               0x9000
+
+typedef enum {
+  YC_QFLASH_SIZE_UNKNOW = 0,
+  YC_QFLASH_SIZE_512KB = 1,
+  YC_QFLASH_SIZE_1MB = 2,
+  YC_QFLASH_SIZE_4MB = 3,
+} yc_qspi_flash_size_enum;
+
+typedef struct
+{
+    uint16_t is_end;
+    uint16_t enc_index;
+    uint8_t enc_buf[ENC_BULK_BUF_SIZE];
+} ENC_BulkTypeDef;
+
+
+/**
+ * @method qspi_flash_pageerase
+ * @brief  page erase (256byte)
+ * @param  flash_addr
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_pageerase(uint32_t flash_addr);
+/**
+ * @method qspi_flash_sectorerase
+ * @brief  sector erase (4K)
+ * @param  flash_addr:flash addr (4k Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_sectorerase(uint32_t flash_addr);
+
+/**
+ * @method qspi_flash_blockerase32k
+ * @brief  block erase  (32K)
+ * @param  flash_addr:flash addr (32k Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_blockerase32k(uint32_t flash_addr);
+
+/**
+ * @method qspi_flash_blockerase64k
+ * @brief  block erase  (64K)
+ * @param  flash_addr:flash addr (64k Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_blockerase64k(uint32_t flash_addr);
+
+/**
+ * @method qspi_flash_write
+ * @brief  write flash
+ * @param  flash_addr:flash addr (when flash_addr%256!=0,256-(flash_addr%256)+len must less than 256)
+ * @param  buf
+ * @param  len
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_write(uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method qspi_flash_read
+ * @brief  read flash
+ * @param  flash_addr:flash addr
+ * @param  buf
+ * @param  len
+ * @retval ERROR,SUCCESS
+ */
+uint8_t qspi_flash_read(uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method flash_blank_check
+ * @brief  check logical addr data is blank
+ * @param  startaddr:cpu addr
+ * @param  len
+ * @retval TRUE:  blank
+ *         FALSE: not blank
+ */
+Boolean flash_blank_check(uint32_t startaddr, uint32_t len);
+
+/**
+ * @method enc_write_flash
+ * @brief  write data to flash with enc
+ * @param  flash_addr:cpu addr (must 32 Bytes align)
+ * @param  buf
+ * @param  len:(must 32 Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t enc_write_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method enc_read_flash
+ * @brief  read flash data with enc
+ * @param  flash_addr:cpu addr
+ * @param  buf
+ * @param  len
+ * @retval ERROR,SUCCESS
+ */
+uint8_t enc_read_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method enc_read_flash_fast
+  * @brief  enc read flash fast(You must sure that the read area is written by enc)
+ * @param  flash_addr:cpu addr
+ * @param  buf
+ * @param  len
+  * @return SUCCESS or ERROR
+  */
+uint8_t enc_read_flash_fast(uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method enc_erase_flash_32byte
+ * @brief  erase 32 Bytes
+ * @param  flash_addr : cpu addr (must 32 Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t enc_erase_flash_32byte(uint32_t flash_addr);
+
+/**
+ * @method enc_erase_flash_32k
+ * @brief  enc erase 32K Bytes
+ * @param  flash_addr : cpu addr (must 32K Bytes align)
+ * @retval ERROR,SUCCESS
+ */
+uint8_t enc_erase_flash_32k(uint32_t flash_addr);
+
+/**
+  * @brief  enc erase flash app area
+  * @param  addr:align at 32k for CPU addr
+  * @param  len:erase len
+  * @return ERROR,SUCCESS
+  */
+uint8_t enc_earse_flash_app_area(uint32_t addr,uint32_t len);
+
+/**
+  * @brief  enc write download flag
+  * @param  addr:BOOT_UART_DOWNLOAD_FLAG,BOOT_USB_DOWNLOAD_FLAG or BOOT_AUTO_SELECT_FLAG
+  * @return ERROR,SUCCESS
+  */
+uint8_t enc_write_download_flag(uint32_t flag);
+
+/**
+ * @method enc_write_flash_bulk
+ * @brief  write bulk data to flash with enc
+* @param  EncBulkStruct:enc buf struct
+ * @param  flash_addr:cpu addr(start addr must 32k Bytes align)
+ * @param  buf
+ * @param  len: Integer multiple of 32 bytes
+ * @retval ERROR,SUCCESS
+ */
+uint8_t enc_write_flash_bulk(ENC_BulkTypeDef *EncBulkStruct,uint32_t flash_addr, uint8_t *buf, uint32_t len);
+
+/**
+ * @method prefetch
+ * @brief  fetch code to cache
+ * @param  start_addr: code start addr
+ * @param  end_addr  : code end addr
+ * @retval NULL
+ */
+void prefetch(void *start_addr, void *end_addr);
+
+/**
+ * @method read_flash_size
+ * @brief  read the chip flash size
+ * @param  NULL
+ * @retval yc_qspi_flash_size_enum
+ */
+yc_qspi_flash_size_enum read_flash_size(void);
+
+/**
+ * @method qspi_GetVersion
+ * @brief  get qspi lib version
+ * @param  NULL
+ * @retval version
+ */
+uint32_t qspi_GetVersion(void);
+
+#endif

bsp/yichip/yc3122-pos/Libraries/sdk/yc_uart.c

@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_uart.c
+ * @brief    source file for setting uart
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2020-11-06      wushengyan         V1.0.0         the first version
+ */
+
+#include "yc_uart.h"
+
+#define uart_DMA_buf_len    1024
+const UART_TypeDef * const UARTs[] = {MUART0, MUART1, MUART2, MUART3};
+uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0};
+uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0};
+uint8_t uart2_DMA_buf[uart_DMA_buf_len] = {0};
+uint8_t uart3_DMA_buf[uart_DMA_buf_len] = {0};
+
+#define RX_ENABLE           BIT0
+#define UART_DMA_ENABLE     BIT31
+#define TX_INTR_ENABLE      BIT31
+#define Set_RxITNum_Mask    0xff00
+#define Statu_RxNum_Mask    (uint32_t)0xffff0000
+
+/**
+ * @method UART_Buffer_Select
+ * @brief  select UART buffer
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval NULL
+ */
+static uint8_t *UART_Buffer_Select(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+    uint8_t *buffers[] = {uart0_DMA_buf, uart1_DMA_buf, uart2_DMA_buf, uart3_DMA_buf};
+
+    for (int i = 0; i < sizeof(UARTs) / sizeof(UARTs[0]); i++)
+    {
+        if ((void *)UARTs[i] == (void *)UARTx)
+        {
+            return buffers[i];
+        }
+    }
+    return NULL;
+}
+
+/**
+ * @method UART_DeInit
+ * @brief  DeInit UART
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval None
+ */
+void UART_DeInit(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+    UARTx->CTRL.reg = 0;
+    UARTx->RX_INT_LEN.reg = 0;
+}
+
+/**
+ * @method UART_Init
+ * @brief  Initializes the UARTx peripheral according to
+ *         the specified parameters.
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  UART_InitStruct: pointer to a UART_InitTypeDef structure that
+ *         contains the configuration information.
+ */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
+{
+    DMA_TypeDef *DMAx = NULL;
+    uint8_t *uartx_DMA_buf = NULL;
+    uint32_t temp_baudrate = 0;
+
+    _ASSERT(IS_UART(UARTx));
+    _ASSERT(IS_UART_RX_MODE(UART_InitStruct->RxMode));
+    _ASSERT(IS_UART_PARITY(UART_InitStruct->Parity));
+    _ASSERT(IS_UART_WORD_LENGTH(UART_InitStruct->DataBits));
+    _ASSERT(IS_UART_STOPBITS(UART_InitStruct->StopBits));
+    _ASSERT(IS_UART_FLOW_CTRL(UART_InitStruct->FlowCtrl));
+    _ASSERT(IS_UART_SMART_CARD(UART_InitStruct->SmartCard));
+    _ASSERT(IS_UART_COMM_MODE(UART_InitStruct->CommMode));
+    _ASSERT(IS_UART_BAUDRATE(UART_InitStruct->BaudRate));
+
+    DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
+    uartx_DMA_buf = UART_Buffer_Select(UARTx);
+    temp_baudrate = (48000000 / UART_InitStruct->BaudRate);
+
+    UART_DeInit(UARTx);
+    DMAx->DEST_ADDR.reg               = (uint32_t)uartx_DMA_buf;
+    DMAx->LEN_LOW.bit.RX_LEN_L        = uart_DMA_buf_len;
+    DMAx->CTRL.bit.LOOPBACK           = 1;
+    DMAx->CTRL.bit.RESET              = 1;
+    DMAx->CTRL.bit.RESET              = 0;
+
+    UARTx->CTRL.bit.RX_EN           = UART_InitStruct->RxMode;
+    UARTx->CTRL.bit.PARITY          = UART_InitStruct->Parity;
+    UARTx->CTRL.bit.DATA_BITS       = UART_InitStruct->DataBits;
+    UARTx->CTRL.bit.STOP_BITS       = UART_InitStruct->StopBits;
+    UARTx->CTRL.bit.FLOW_CTRL       = UART_InitStruct->FlowCtrl;
+    UARTx->CTRL.bit.SMART_CARD      = UART_InitStruct->SmartCard;
+    UARTx->CTRL.bit.HDX_EN          = UART_InitStruct->CommMode;
+    UARTx->CTRL.bit.RESET_BAUD      = ENABLE;
+    UARTx->BAUD.bit.BAUD_RATE       = temp_baudrate;
+}
+
+/**
+ * @method UART_StructInit
+ * @brief  Fills each USART_InitStruct member with its default value.
+ * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+ *         which will be initialized.
+ * @retval None
+ */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
+{
+    UART_InitStruct->BaudRate  = 9600;
+    UART_InitStruct->RxMode    = MODE_RX_ENABLE;
+    UART_InitStruct->Parity    = YC_PARITY_NONE;
+    UART_InitStruct->DataBits  = DATABITS_8B;
+    UART_InitStruct->StopBits  = STOPBITS_1;
+    UART_InitStruct->FlowCtrl  = FLOWCTRL_NONE;
+    UART_InitStruct->SmartCard = SMARTCARD_DISABLE;
+    UART_InitStruct->CommMode  = MODE_DUPLEX;
+}
+
+/**
+ * @method UART_ITConfig
+ * @brief  Enable or disable the specified UART interrupt.
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  UART_IT: specifies the UART interrupt sources
+ *         This parameter can be one of the following values:
+ *     @arg UART_IT_TX:interrupt trigger after send data completed.
+ *     @arg UART_IT_RX:interrupt trigger when received data.
+ * @param  NewState: new state of the specified UART interrupt
+ *          This parameter can be ENABLE or DISABLE
+ */
+void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState)
+{
+    _ASSERT(IS_UART(UARTx));
+    _ASSERT(IS_UART_IT(UART_IT));
+
+    if (UART_IT == UART_IT_TX)
+    {
+        UARTx->BAUD.bit.TX_INT_EN = NewState;
+    }
+    else if (UART_IT == UART_IT_RX)
+    {
+        UARTx->RX_INT_LEN.bit.VAL = NewState;
+    }
+}
+
+/**
+ * @method UART_SendData
+ * @brief  UART Send One Data
+ * @param  UARTx: Select  the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval None
+ */
+void UART_SendData(UART_TypeDef *UARTx, uint8_t Data)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    volatile uint8_t buf[1];
+
+    buf[0] = Data;
+    DMA_TypeDef *DMAx                    = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
+    DMAx->SRC_ADDR.reg                   = (uint32_t)buf;
+    DMAx->LEN_LOW.bit.TX_LEN_L           = 1;
+    DMAx->CTRL.bit.START                 = 1;
+
+    while (DMAx->STATUS.bit.DONE != 1);
+}
+
+/**
+ * @method UART_SendBuf
+ * @brief  Transmits datas via UART DMA, the function will return after datas is sent.
+ * @param  USARTx: Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  buf: pointer to a buf that contains the data you want transmit.
+ * @param  len: the buf length
+ * @retval None
+ */
+void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
+{
+    _ASSERT(IS_UART(UARTx));
+    _ASSERT(NULL != buf);
+    _ASSERT(len < 0xfffff);
+
+    DMA_TypeDef *DMAx                = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
+    DMAx->SRC_ADDR.reg               = (uint32_t)buf;
+    DMAx->LEN_LOW.bit.TX_LEN_L       = len & 0xffff;
+    DMAx->CTRL.bit.TX_LEN_H          = len >> 16;
+    DMAx->CTRL.bit.START             = 1;
+
+    while (DMAx->STATUS.bit.DONE != 1);
+}
+
+/**
+ * @method UART_ReceiveData
+ * @brief  Receive single data through the USARTx peripheral.
+ * @param  USARTx: Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval An one byte received data.
+ */
+uint8_t UART_ReceiveData(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    return UARTx->RX_DATA.bit.VAL;
+
+}
+
+/**
+ * @method UART_ReceiveBuf
+ * @brief  Receives datas through the UART DMA.
+ * @param  USARTx: Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  buf: pointer to a buf that contains the data you want receive.
+ * @param  len: the buf length, which size should be less than 20 bit (len < 0xfffff)
+ * @retval The length of received data before return.
+ */
+uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
+{
+    _ASSERT(IS_UART(UARTx));
+    _ASSERT(NULL != buf);
+    _ASSERT(len < 0xfffff);
+
+    uint32_t rcv_len = 0;
+    while ((UART_ReceiveDataLen(UARTx) > 0) && (rcv_len < len))
+    {
+        buf[rcv_len++] = UARTx->RX_DATA.bit.VAL;
+    }
+
+    return rcv_len;
+}
+
+/**
+ * @method UART_AutoFlowCtrlCmd
+ * @brief  ENABLE or DISABLE UARTx auto flow control
+ * @param  USARTx: Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  NewState: ENABLE or DISABLE auto flow control
+ * @retval None
+ */
+void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    UARTx->CTRL.bit.FLOW_CTRL = NewState;
+}
+
+/**
+ * @method UART_GetITIdentity
+ * @brief  Get IT Identity
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval IT Identity
+ */
+uint8_t UART_GetITIdentity(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+    //return (0 || (UARTx->BAUD.bit.TX_INT_EN) || (UARTx->RX_INT_LEN.bit.VAL));
+    if((UARTx->RX_INT_LEN.reg > 0)&& (UARTx->STATUS.bit.RX_ITEMS_L >=UARTx->RX_INT_LEN.reg))
+    {
+        return UART_IT_RX;
+    }
+    else if(UARTx->BAUD.bit.TX_INT_EN)
+    {
+        return UART_IT_TX;
+    }
+    return 0;
+}
+
+/**
+ * @method UART_IsRXFIFOFull
+ * @brief  Check if the Rx fifo is full or not.
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval TRUE:  Rx fifo is full.
+ *         FALSE: Rx fifo is not full
+ */
+Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    return (Boolean)(UARTx->STATUS.bit.RX_FULL);
+}
+
+/**
+ * @method UART_IsRXFIFONotEmpty
+ * @brief  Check if the Rx fifo is empty or not.
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval TRUE: Rx fifo is not empty.
+ *         FALSE: Rx fifo is empty
+ */
+Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
+}
+
+/**
+ * @method UART_IsBusy
+ * @brief  Check if the UARTx is busy or not.
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval TRUE: UARTx is busy.
+ *         FALSE: UARTx is not busy.
+ */
+Boolean UART_IsBusy(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
+}
+
+/**
+ * @method UART_SetITTimeout
+ * @brief  Sets the interruption time for serial port timeout.
+ * @param  USARTx: Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  timeout: 0x00~0xff
+ * @retval None
+ */
+void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    UARTx->TIMEOUT_INT.reg = timeout;
+}
+
+/**
+ * @method UART_SetRxITNum
+ * @brief  Set the number of uart receive data intterupt trigger
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @param  Bcnt: if the number of receive datas greater than Bcnt,interrupt trigger
+ * @retval None
+ */
+void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    UARTx->RX_INT_LEN.reg = Bcnt;
+}
+
+/**
+ * @method UART_ReceiveDataLen
+ * @brief  Return the length of received data
+ * @param  UARTx: Select the UART peripheral.
+ *         This parameter can be one of the following values:
+ *         MUART0, MUART1, MUART2 or MUART3.
+ * @retval Data len
+ */
+uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx)
+{
+    _ASSERT(IS_UART(UARTx));
+
+    return (UARTx->STATUS.bit.RX_ITEMS_H << 16) + UARTx->STATUS.bit.RX_ITEMS_L;
+}
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_uart.h

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c); 2006-2020, YICHIP Development Team
+ * @file     yc_uart.h
+ * @brief    source file for setting uart
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2020-11-06      wushengyan         V1.0.0         the first version
+ */
+
+#ifndef __YC_UART_H__
+#define __YC_UART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "yc3122.h"
+#include "system.h"
+
+/**
+ * @defgroup UARTx
+ */
+#define IS_UART(UARTx)              (((UARTx) == MUART0) ||\
+                                    ((UARTx) == MUART1) ||\
+                                    ((UARTx) == MUART2) ||\
+                                    ((UARTx) == MUART3))
+
+/**
+ * @defgroup UART_RxMode
+ */
+#define MODE_RX_ENABLE              1
+#define MODE_RX_DISABLE             0
+#define IS_UART_RX_MODE(MODE)       (((MODE) == MODE_RX_ENABLE) ||\
+                                    ((MODE) == MODE_RX_DISABLE))
+
+/**
+ * @defgroup USART_Parity
+ */
+#define YC_PARITY_NONE                 0
+#define YC_PARITY_EVEN                 0
+#define YC_PARITY_ODD                  1
+#define IS_UART_PARITY(PARITY)      (((PARITY) == YC_PARITY_NONE) ||\
+                                    ((PARITY) == YC_PARITY_EVEN)  ||\
+                                    ((PARITY) == YC_PARITY_ODD))
+
+/**
+ * @defgroup UART_DataBits
+ */
+#define DATABITS_8B                 0
+#define DATABITS_9B                 1
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == DATABITS_8B) || \
+                                    ((LENGTH) == DATABITS_9B))
+
+/**
+ * @defgroup UART_Stop_Bits
+ */
+#define STOPBITS_1                  0
+#define STOPBITS_2                  1
+#define IS_UART_STOPBITS(STOPBITS)  (((STOPBITS) == STOPBITS_1) ||  \
+                                    ((STOPBITS) == STOPBITS_2) )
+
+/**
+ * @defgroup UART_Hardware_Flow_Control
+ */
+#define FLOWCTRL_NONE               0
+#define FLOWCTRL_ENABLE             1
+#define IS_UART_FLOW_CTRL(CTRL)     (((CTRL) == FLOWCTRL_NONE) || \
+                                    ((CTRL) == FLOWCTRL_ENABLE))
+
+/**
+ * @defgroup UART_Smart_Card_Control
+ */
+#define SMARTCARD_ENABLE            1
+#define SMARTCARD_DISABLE           0
+#define IS_UART_SMART_CARD(CTRL)    (((CTRL) == SMARTCARD_ENABLE) || \
+                                    ((CTRL) == SMARTCARD_DISABLE))
+
+/**
+ * @defgroup UART_CommMode
+ */
+#define MODE_SINGLE_LINE            1
+#define MODE_DUPLEX                 0
+#define IS_UART_COMM_MODE(MODE)     (((MODE) == MODE_SINGLE_LINE) ||\
+                                    ((MODE) == MODE_DUPLEX))
+
+/**
+ * @defgroup USART_BaudRate
+ */
+#define IS_UART_BAUDRATE(BAUDRATE)  (((BAUDRATE) > 0x5B8) &&\
+                                    ((BAUDRATE) < 0x0044AA21))
+
+/**
+ * @defgroup UART_Interrupt_Type_definition
+ */
+#define UART_IT_TX                  0x01
+#define UART_IT_RX                  0x02
+#define IS_UART_IT(ITx)             (((ITx) == UART_IT_TX) || ((ITx) == UART_IT_RX))
+
+typedef struct
+{
+    uint8_t RxMode;        /*!< Specifies wether the Receive or Transmit mode
+                                is enabled or disabled. This parameter can be
+                                a value of @ref UART_Mode */
+
+    uint8_t Parity;        /*!< Specifies the parity mode.
+                                This parameter can be a value of
+                                @ref UART_Parity @note When parity is enabled,
+                                the computed parity is inserted at
+                                the MSB position of the transmitted data
+                                (9th bit when the word length is set to
+                                9 data bits; 8th bit when the word length is
+                                set to 8 data bits);. */
+
+    uint8_t DataBits;      /*!< Specifies the number of data bits transmitted
+                                or received in a frame. This parameter can be
+                                a value of @ref UART_DataBits */
+
+    uint8_t StopBits;      /*!< Specifies the number of stop bits transmitted.
+                                parameter can be a value of @ref UART_Stop_Bits */
+
+    uint8_t FlowCtrl;      /*!< Specifies wether the hardware flow control mode
+                                is enabled or disabled. This parameter can be
+                                a value of @ref UART_Hardware_Flow_Control */
+
+    uint8_t SmartCard;
+
+    uint8_t CommMode;
+
+    uint32_t BaudRate;     /*!< This member configures the USART
+                                communication baud rate. */
+} UART_InitTypeDef;
+
+void UART_DeInit(UART_TypeDef *UARTx);
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
+void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
+void UART_SendData(UART_TypeDef *UARTx, uint8_t Data);
+void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
+uint8_t UART_ReceiveData(UART_TypeDef *UARTx);
+uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
+void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+uint8_t UART_GetITIdentity(UART_TypeDef *UARTx);
+Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx);
+Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx);
+Boolean UART_IsBusy(UART_TypeDef *UARTx);
+void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout);
+void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt);
+uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_wdt.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_wdt.c
+ * @brief    This file provides all the WDT firmware functions.
+ *
+ * Change Logs:
+ * Date           Author             Version        Notes
+ * 2021-01-04     yangzhengfeng      V1.0.0         the first version
+ */
+#include "yc_wdt.h"
+
+/**
+ * @brief  Set WDT Clk Div
+ * @param  Wdtclkdiv: Wdtclkdiv value equal 1 to 16
+ * @retval none
+ */
+void WDT_CLKDIV(uint32_t Wdtclkdiv)
+{
+    _ASSERT(IS_WDT_CLKDI(Wdtclkdiv));
+
+    MWDT->CONFIG.bit.CLK_DIV = Wdtclkdiv;
+}
+
+/**
+ * @brief  Set reload counter
+ * @param  Reload: Reload counter equal to 2 to 31
+ * @retval none
+ */
+void WDT_SetReload(uint32_t Reload)
+{
+    _ASSERT(IS_WDT_RELOAD(Reload));
+
+    MWDT->CONFIG.bit.RELOAD = Reload;
+}
+
+/**
+ * @brief  Feed the watchdog function
+ * @param  none
+ * @retval none
+ */
+void WDT_ReloadCounter(void)
+{
+    MWDT->KICK.reg = COUNTER_RELOAD_KEY;
+}
+
+/**
+ * @brief  Enable WDT
+ * @param  none
+ * @retval none
+ */
+void WDT_Enable(void)
+{
+    MWDT->CONFIG.bit.EN = ENABLE;
+}
+
+/**
+ * @brief Set WDT  mode
+ * @param WDT_Mode : Select the following values :
+ *        WDT_CPUReset
+ *        WDT_Interrupt.
+ * @retval none
+ * @description If Select WDT_CPUReset Mode,the bit for WDT RESET will be set;if
+ *              Select WDT_Interrupt the bit for WDT RESET will
+ */
+void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode)
+{
+    _ASSERT(IS_WDT_MODE(WDT_Mode));
+
+    if(WDT_CPUReset == WDT_Mode)
+    {
+        MWDT->CONFIG.bit.MODE = WDT_CPUReset;
+        MRSTGEN->RST_EN.bit.WDT = ENABLE;
+    }
+    else if(WDT_Interrupt == WDT_Mode)
+    {
+        MWDT->CONFIG.bit.MODE = WDT_Interrupt;
+        MRSTGEN->RST_EN.bit.WDT = DISABLE;
+    }
+}
+
+/**
+ * @brief  Get interrupt Status
+ * @param  none
+ * @retval SET:interrupt ocuured.
+ */
+uint8_t WDT_GetITStatus(void)
+{
+    uint16_t ret;
+
+    ret = MWDT->IRQ_STATUS.bit.STATE;
+
+    return ret ;
+}
+
+/**
+ * @brief  Clear interrupt
+ * @param  none
+ * @retval none
+ */
+void WDT_ClearITPendingBit(void)
+{
+    MWDT->CLEAR.reg = 1;
+}
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/sdk/yc_wdt.h

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_wdt.h
+ * @brief    This file provides all the WDT firmware functions.
+ *
+ * Change Logs:
+ * Date           Author             Version        Notes
+ * 2021-01-04     yangzhengfeng      V1.0.0         the first version
+ */
+
+#ifndef __YC_WDT_H__
+#define __YC_WDT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "yc3122.h"
+#include "system.h"
+
+
+typedef enum
+{
+    WDT_CPUReset = 0,
+    WDT_Interrupt,
+} WDT_ModeTypeDef;
+
+#define  WDTCLKDIV_1                0x00
+#define  WDTCLKDIV_2                0x01
+#define  WDTCLKDIV_3                0x02
+#define  WDTCLKDIV_4                0x03
+#define  WDTCLKDIV_5                0x04
+#define  WDTCLKDIV_6                0x05
+#define  WDTCLKDIV_7                0x06
+#define  WDTCLKDIV_8                0x07
+#define  WDTCLKDIV_9                0x08
+#define  WDTCLKDIV_10               0x09
+#define  WDTCLKDIV_11               0x0A
+#define  WDTCLKDIV_12               0x0B
+#define  WDTCLKDIV_13               0x0c
+#define  WDTCLKDIV_14               0x0D
+#define  WDTCLKDIV_15               0x0E
+#define  WDTCLKDIV_16               0x0F
+
+/**************the value of feed dog************/
+#define COUNTER_RELOAD_KEY          0x5937
+#define ITSTATUS                    0x01
+#define IS_WDT_CLKDI(wdtclkdiv)     (wdtclkdiv < 16)
+#define IS_WDT_RELOAD(load)         (load <= 0x1f)
+#define IS_WDT_MODE(mode)           ((mode == WDT_CPUReset) || (mode == WDT_Interrupt))
+
+void WDT_CLKDIV(uint32_t Wdtclkdiv);
+void WDT_SetReload(uint32_t Reload);
+void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode);
+void WDT_ClearITPendingBit(void);
+void WDT_Enable(void);
+void WDT_ReloadCounter(void);
+uint8_t WDT_GetITStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__YC_WDT_H__*/
+
+/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

bsp/yichip/yc3122-pos/Libraries/startup/startup_rv32.s

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file     yc_startup_yc3122.s
+ * @brief    source file for setting startup_yc3122
+ *
+ * Change Logs:
+ * Date           Author             Version        Notes
+ * 2020-11-06     wushengyan         V1.0.0         the first version
+ */
+
+#define REGBYTES (4)
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x1880
+#define MSTATUS_MIE  0x00000008
+#define MSTATUS_FS   0x00006000
+
+	.equ __stack_size,0x9000
+
+	.text
+	.globl flash_start
+	.globl delay
+	.globl __stack_size
+	.section .text.startup
+flash_start:
+	la sp, _stack
+
+	/* set exception and irq mtvec */
+	la a0,trap
+	ori a0,a0,1
+	csrw mtvec,a0
+
+	/* enable fs */
+	li t0,MSTATUS_FS
+	csrs mstatus,t0
+	csrw fcsr,x0
+
+	/* Load data section */
+	la a0, _sidata
+	la a1, _sdata
+	la a2, _edata
+	bgeu a1,a2,2f
+1:      
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0,a0,4
+	addi a1,a1,4
+	bltu a1,a2,1b
+2: 
+	/* clear bss section */
+	la a0,_sbss
+	la a1,_ebss
+	bgeu a0,a1,2f
+1:
+	sw zero,(a0)
+	addi a0,a0,4
+	bltu a0,a1,1b
+2:
+	/*clear heap/statck*/
+	la a0,_ebss
+	la a1,_stack
+	bgeu a0,a1,2f
+1:
+	sw zero,(a0)
+	addi a0,a0,4
+	bltu a0,a1,1b
+2:
+
+#ifndef __NO_SYSTEM_INIT
+//        jal systeminit
+#endif
+
+#ifndef __NO_BOARD_INIT
+//        jal board_init
+#endif
+	li t0, 0x00000800
+	csrs 0x304,t0
+
+	li t0, MSTATUS_MIE
+	csrs mstatus, t0
+
+	jal main
+
+        /* never retch here*/
+__exit:
+	j __exit
+
+
+
+
+
+
+.macro DISABLE_MIE
+    csrc mstatus, MSTATUS_MIE
+.endm
+
+.macro ENABLE_MIE
+    csrs mstatus, MSTATUS_MIE
+.endm
+
+.macro GET_IRQ_NUM
+    li t1,0x000E4004
+    lw t1,0(t1)
+    li t3,0x01
+    li t5,0x00
+get_irq_num_loop:
+    and t4, t1, t3
+    blt  x0, t4, get_irq_num_end
+    addi t5, t5, 1
+    slli t3, t3, 1
+    j get_irq_num_loop
+get_irq_num_end:
+    mv   t1,  t5
+.endm
+
+
+
+.macro SAVE_CONTEXT
+    addi sp,sp,-40*4
+    sw x1 , 0 *REGBYTES(sp) /* ra */
+    sw x4 , 1 *REGBYTES(sp) /* tp */
+    sw x5 , 2 *REGBYTES(sp) /* t0 */
+    sw x6 , 3 *REGBYTES(sp) /* t1 */
+    sw x7 , 4 *REGBYTES(sp) /* t2 */
+    sw x10, 5 *REGBYTES(sp) /* a0 */
+    sw x11, 6 *REGBYTES(sp) /* a1 */
+    sw x12, 7 *REGBYTES(sp) /* a2 */
+    sw x13, 8 *REGBYTES(sp) /* a3 */
+    sw x14, 9 *REGBYTES(sp) /* a4 */
+    sw x15, 10*REGBYTES(sp) /* a5 */
+    sw x16, 11*REGBYTES(sp) /* a6 */
+    sw x17, 12*REGBYTES(sp) /* a7 */
+    sw x28, 13*REGBYTES(sp) /* t3 */
+    sw x29, 14*REGBYTES(sp) /* t4 */
+    sw x30, 15*REGBYTES(sp) /* t5 */
+    sw x31, 16*REGBYTES(sp) /* t6 */
+
+    fsw f0, 17*REGBYTES(sp) /* ft0 */
+    fsw f1, 18*REGBYTES(sp) /* ft1 */
+    fsw f2, 19*REGBYTES(sp) /* ft2 */
+    fsw f3, 20*REGBYTES(sp) /* ft3 */
+    fsw f4, 21*REGBYTES(sp) /* ft4 */
+    fsw f5, 22*REGBYTES(sp) /* ft5 */
+    fsw f6, 23*REGBYTES(sp) /* ft6 */
+    fsw f7, 24*REGBYTES(sp) /* ft7 */
+    fsw f10,25*REGBYTES(sp) /* fa0 */
+    fsw f11,26*REGBYTES(sp) /* fa1 */
+    fsw f12,27*REGBYTES(sp) /* fa2 */
+    fsw f13,28*REGBYTES(sp) /* fa3 */
+    fsw f14,29*REGBYTES(sp) /* fa4 */
+    fsw f15,30*REGBYTES(sp) /* fa5 */
+    fsw f16,31*REGBYTES(sp) /* fa6 */
+    fsw f17,32*REGBYTES(sp) /* fa7 */
+    fsw f28,33*REGBYTES(sp) /* ft8 */
+    fsw f29,34*REGBYTES(sp) /* ft9 */
+    fsw f30,35*REGBYTES(sp) /* ft10*/
+    fsw f31,36*REGBYTES(sp) /* ft11*/
+.endm
+
+.macro RESTORE_CONTEXT
+    lw x1 , 0 *REGBYTES(sp) /* ra */
+    lw x4 , 1 *REGBYTES(sp) /* tp */
+    lw x5 , 2 *REGBYTES(sp) /* t0 */
+    lw x6 , 3 *REGBYTES(sp) /* t1 */
+    lw x7 , 4 *REGBYTES(sp) /* t2 */
+    lw x10, 5 *REGBYTES(sp) /* a0 */
+    lw x11, 6 *REGBYTES(sp) /* a1 */
+    lw x12, 7 *REGBYTES(sp) /* a2 */
+    lw x13, 8 *REGBYTES(sp) /* a3 */
+    lw x14, 9 *REGBYTES(sp) /* a4 */
+    lw x15, 10*REGBYTES(sp) /* a5 */
+    lw x16, 11*REGBYTES(sp) /* a6 */
+    lw x17, 12*REGBYTES(sp) /* a7 */
+    lw x28, 13*REGBYTES(sp) /* t3 */
+    lw x29, 14*REGBYTES(sp) /* t4 */
+    lw x30, 15*REGBYTES(sp) /* t5 */
+    lw x31, 16*REGBYTES(sp) /* t6 */
+
+    flw f0, 17*REGBYTES(sp) /* ft0 */
+    flw f1, 18*REGBYTES(sp) /* ft1 */
+    flw f2, 19*REGBYTES(sp) /* ft2 */
+    flw f3, 20*REGBYTES(sp) /* ft3 */
+    flw f4, 21*REGBYTES(sp) /* ft4 */
+    flw f5, 22*REGBYTES(sp) /* ft5 */
+    flw f6, 23*REGBYTES(sp) /* ft6 */
+    flw f7, 24*REGBYTES(sp) /* ft7 */
+    flw f10,25*REGBYTES(sp) /* fa0 */
+    flw f11,26*REGBYTES(sp) /* fa1 */
+    flw f12,27*REGBYTES(sp) /* fa2 */
+    flw f13,28*REGBYTES(sp) /* fa3 */
+    flw f14,29*REGBYTES(sp) /* fa4 */
+    flw f15,30*REGBYTES(sp) /* fa5 */
+    flw f16,31*REGBYTES(sp) /* fa6 */
+    flw f17,32*REGBYTES(sp) /* fa7 */
+    flw f28,33*REGBYTES(sp) /* ft8 */
+    flw f29,34*REGBYTES(sp) /* ft9 */
+    flw f30,35*REGBYTES(sp) /* ft10*/
+    flw f31,36*REGBYTES(sp) /* ft11*/
+    addi sp, sp, 40*REGBYTES
+.endm
+
+.macro SAVE_CSR_CONTEXT
+    csrr t0,mepc
+    csrr t1,mcause
+    sw   t0,37*REGBYTES(sp) /* mepc */
+    sw   t1,38*REGBYTES(sp) /* mcause */
+.endm
+
+.macro RESTORE_CSR_CONTEXT
+    lw   t0,37*REGBYTES(sp) /* mepc */
+    lw   t1,38*REGBYTES(sp) /* mcause */
+    csrw mcause, t1
+    csrw mepc,   t0
+.endm
+
+
+
+    .align 2
+    .global Default_IRQHandler
+    .weak   Default_IRQHandler
+    .type   Default_IRQHandler, %function
+Default_IRQHandler:
+
+    SAVE_CONTEXT
+
+    SAVE_CSR_CONTEXT
+
+    /* get irq */
+    la t0,isr_table
+//    GET_IRQ_NUM    		/* t1: irq num */
+    li t1,0x000E4004		/* t1: irq num */
+    lw t1,0(t1)
+    slli t2, t1, 2
+    add t0, t0, t2
+    lw t2, (t0)
+    sw t1,39*REGBYTES(sp)
+
+
+    ENABLE_MIE
+
+    jalr t2         /* jump to irq */
+
+    DISABLE_MIE
+
+    /* clear pending mask*/
+    lw t1,39*REGBYTES(sp)
+    li t0,0x000E4004
+    sw t1,(t0)
+
+    /* enable pri mie*/
+    li      t0, MSTATUS_PRV1
+    csrs    mstatus, t0
+
+    RESTORE_CSR_CONTEXT
+
+    RESTORE_CONTEXT
+
+    mret
+
+
+/* trap start*/
+.section .text.trap
+/* In CLIC mode, the exeception entry must be 64bytes aligned */
+.align 6
+.global trap
+.weak trap
+.type trap, %function
+trap:
+    /* check for interrupt */
+    addi sp,sp,-4
+    sw   t0,0x0(sp)
+    csrr t0,mcause
+    blt  t0,x0, .Interrupt /* go to Interrupt*/
+    addi sp,sp,4
+
+    /* save regs */
+    addi sp,sp,-22*4
+    sw   x1 , 0 *REGBYTES(sp)
+    sw   x2 , 1 *REGBYTES(sp)
+    sw   x3 , 2 *REGBYTES(sp)
+    sw   x4 , 3 *REGBYTES(sp)
+    sw   x5 , 4 *REGBYTES(sp)
+    sw   x6 , 5 *REGBYTES(sp)
+    sw   x7 , 6 *REGBYTES(sp)
+    sw   x8 , 7 *REGBYTES(sp)
+    sw   x9 , 8 *REGBYTES(sp)
+    sw   x10, 9 *REGBYTES(sp)
+    sw   x11, 10*REGBYTES(sp)
+    sw   x12, 11*REGBYTES(sp)
+    sw   x13, 12*REGBYTES(sp)
+    sw   x14, 13*REGBYTES(sp)
+    sw   x15, 14*REGBYTES(sp)
+    sw   x16, 15*REGBYTES(sp)
+    sw   x17, 16*REGBYTES(sp)
+    sw   x28, 17*REGBYTES(sp)
+    sw   x29, 18*REGBYTES(sp)
+    sw   x30, 19*REGBYTES(sp)
+    sw   x31, 20*REGBYTES(sp)
+    
+    csrr a0,  mepc
+    sw   a0,  21*REGBYTES(sp)
+    csrr a0,  mstatus
+    sw   a0,  22*REGBYTES(sp)
+    mv   a0,  sp
+
+
+    jal trap_c
+
+    /*never reatch here */
+    j .
+
+.Interrupt:
+    lw    t0, 0x0(sp)
+    addi  sp, sp, 4
+
+    j    Default_IRQHandler
+/* trap end*/
+
+
+
+	.global trap_c
+	.weak trap_c
+	.type trap_c,%function
+trap_c:
+	j trap_c
+
+
+    .align  6
+    .weak   Default_Handler
+    .global Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    j       Default_Handler
+    .size   Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro  def_irq_handler handler_name
+    .weak   \handler_name
+    .globl  \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+
+    def_irq_handler USB_IRQHandler
+    def_irq_handler I2C0_IRQHandler
+    def_irq_handler I2C1_IRQHandler
+    def_irq_handler QSPI_IRQHandler
+    def_irq_handler SPI0_IRQHandler
+    def_irq_handler SPI1_IRQHandler
+    def_irq_handler HSPI_IRQHandler
+    def_irq_handler SEC_IRQHandler
+    def_irq_handler UART0_IRQHandler
+    def_irq_handler UART1_IRQHandler
+    def_irq_handler UART2_IRQHandler
+    def_irq_handler UART3_IRQHandler
+    def_irq_handler MEMCP_IRQHandler
+    def_irq_handler SCI0_IRQHandler
+    def_irq_handler SCI1_IRQHandler
+    def_irq_handler MSR_IRQHandler
+    def_irq_handler GPIO_IRQHandler
+    def_irq_handler TMRG0_IRQHandler
+    def_irq_handler TMRG1_IRQHandler
+    def_irq_handler SDIO_IRQHandler
+    def_irq_handler PSARM_IRQHandler
+    def_irq_handler RSA_IRQHandler
+    def_irq_handler SM4_IRQHandler
+    def_irq_handler TRNG_IRQHandler
+    def_irq_handler WDT_IRQHandler
+    def_irq_handler DCMI_IRQHandler
+    def_irq_handler ADC_IRQHandler
+    def_irq_handler RTC_IRQHandler
+    def_irq_handler BIN_IRQHandler
+    def_irq_handler POWER_IRQHandler
+    def_irq_handler SOFTWARE_IRQHandler
+    def_irq_handler IPC_IRQHandler
+    def_irq_handler QR_IRQHandler
+    def_irq_handler ONE_BIN_IRQHandler
+    def_irq_handler SYSTICK_IRQHandler
+    def_irq_handler VBAT_IRQHandler
+    def_irq_handler EXTI0_IRQHandler
+    def_irq_handler EXTI1_IRQHandler
+    def_irq_handler EXTI2_IRQHandler
+    def_irq_handler EXTI3_IRQHandler
+    def_irq_handler EXTI4_IRQHandler
+
+    .align 4
+isr_table:
+    .long USB_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long QSPI_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long HSPI_IRQHandler
+    .long SEC_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long UART3_IRQHandler
+    .long MEMCP_IRQHandler
+    .long SCI0_IRQHandler
+    .long SCI1_IRQHandler
+    .long MSR_IRQHandler
+    .long GPIO_IRQHandler
+    .long TMRG0_IRQHandler
+    .long TMRG1_IRQHandler
+    .long SDIO_IRQHandler
+    .long PSARM_IRQHandler
+    .long RSA_IRQHandler
+    .long SM4_IRQHandler
+    .long TRNG_IRQHandler
+    .long WDT_IRQHandler
+    .long DCMI_IRQHandler
+    .long ADC_IRQHandler
+    .long RTC_IRQHandler
+    .long BIN_IRQHandler
+    .long POWER_IRQHandler
+    .long SOFTWARE_IRQHandler
+    .long IPC_IRQHandler
+    .long QR_IRQHandler
+    .long ONE_BIN_IRQHandler
+    .long SYSTICK_IRQHandler

bsp/yichip/yc3122-pos/README.md

@@ -0,0 +1,47 @@
+# YC3122-pos 板级支持包 说明
+
+标签： YICHIP、Cortex-M0、RISC_V YC3121、国产MCU
+
+---
+
+## 1. 简介
+
+本文档为 YC3122-pos 的 BSP(板级支持包) 说明。
+
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+YC3122-pos 开发板由易兆微提供，可满足基础测试及高端开发需求。
+
+开发板外观如下图所示：
+
+YC3122-pos
+
+![YC3122-pos](figures/YC3122-pos.png)
+
+YC3122-pos 开发板板载资源如下：
+
+- MCU：YC3122  ARM 32-bit Cortex-M0和RISC V 双核处理器，RISC V支持浮点算法主频 192MHz，512KB/1MB/4MB FLASH ，320KB SRAM
+- 常用外设
+  - LED：4 个
+  - 梯形矩阵键盘
+  - 蜂鸣器
+  - USB
+  - UART
+  - I2C
+  - DCMI
+  - GPIO(80个)
+  - SDIO2.0
+  - ADC
+  - SPI LCD
+  - SPI NFC
+  - 7816接口 （接触IC卡，支持3V , 1.8V）
+  - 7811接口 （三轨磁条卡解码模块，支持ISO/ABA AAMVA 及IBM等标准卡）
+  - TIMER：9个32bi位 （支持PWM）
+  - TRNG：（1个真随机数发生器）
+  - 安全加密算法
+    - 对称算法：对称算法：DES、TDES、AES-128/192/256、国密IV（SM4）
+    - 非对称算法：RSA-1024/2048、国密II（SM2）、ECC
+    - HASH 校验算法：SHA-1/224/256/384/512、国密III（SM3）
+- 调试接口：SWD / ICE

bsp/yichip/yc3122-pos/SConscript

@@ -0,0 +1,11 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+objs = []
+list = os.listdir(cwd)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+Return('objs')

bsp/yichip/yc3122-pos/SConstruct

@@ -0,0 +1,40 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/yichip/yc3122-pos/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/yichip/yc3122-pos/applications/main.c

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+/* defined the LED pin: PA12 */
+#define LED_PIN (51)
+#define FS_PARTITION_NAME "filesystem"
+
+#ifdef BSP_USING_INTER_FLASH
+#include <dfs_elm.h>
+#include <dfs_file.h>
+#include <unistd.h>
+#include <dfs_fs.h>
+#include <fal.h>
+static void elmfs_sample(void)
+{
+    fal_init();
+
+    struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
+    if (flash_dev == NULL)
+    {
+        LOG_E("Can't create a block device on '%s' partition.", FS_PARTITION_NAME);
+    }
+    else
+    {
+        LOG_I("Create a block device on the %s partition of flash successful...", FS_PARTITION_NAME);
+    }
+    if (dfs_mkfs("elm", flash_dev->parent.name) == 0)
+    {
+        LOG_I("dfs_mkfs ok!\n");
+    }
+    else
+    {
+        LOG_E("dfs_mkfs err!\n");
+    }
+
+    if (dfs_mount(flash_dev->parent.name, "/", "elm", 0, 0) == 0)
+    {
+        LOG_I("Filesystem initialized!");
+    }
+    else
+    {
+        LOG_E("Failed to initialize filesystem!");
+        LOG_D("You should create a filesystem on the block device first!");
+    }
+    struct statfs elm_stat;
+    if (statfs("/", &elm_stat) == 0)
+    {
+        LOG_I("elmfat filesystem block size:0x%x,total blocks:0x%x,free blocks:0x%x\n", elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
+    }
+
+    if (mkdir("/user", 0x777) == 0)
+    {
+        LOG_I("make a directory: '/user'.\n");
+    }
+
+    LOG_I("open file\n");
+    int fd = open("/user/test.txt", O_WRONLY | O_CREAT);
+    LOG_I("open file ok\n");
+    char str[] = "elmfat mount";
+    if (fd >= 0)
+    {
+        LOG_I("write file\n");
+        if (write(fd, str, sizeof(str)) == sizeof(str))
+            LOG_I("write data done.\n");
+        close(fd);
+    }
+    int size;
+    char buf[20];
+    fd = open("/user/test.txt", O_RDONLY);
+    if (fd >= 0)
+    {
+        LOG_I("read file\n");
+        size = read(fd, buf, sizeof(buf));
+        close(fd);
+        if (size == sizeof(str))
+        {
+            LOG_I("Read data from file test.txt(size:%d):%s\n", size, buf);
+        }
+    }
+    else
+    {
+        LOG_E("open err\n");
+    }
+
+    if (statfs("/", &elm_stat) == 0)
+    {
+        LOG_I("elmfat filesystem block size:0x%x,total blocks:0x%x,free blocks:0x%x\n", elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
+    }
+}
+#endif
+int main(void)
+{
+#ifdef BSP_USING_INTER_FLASH
+    elmfs_sample();
+#endif
+    int count = 1;
+    /* set LED4 pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/yichip/yc3122-pos/drivers/Kconfig

@@ -0,0 +1,26 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable UART0 PC6/5(R/T)"
+                select RT_USING_SERIAL
+                default y
+
+            config BSP_USING_UART1
+                bool "Enable UART1 PC2/3(R/T)"
+                select RT_USING_SERIAL
+                default n
+        endmenu
+		
+		config BSP_USING_INTER_FLASH
+			bool "Enable inter flash"
+			default n
+    endmenu
+
+endmenu

bsp/yichip/yc3122-pos/drivers/SConscript

@@ -0,0 +1,29 @@
+# RT-Thread building script for component
+
+from building import *
+import os
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+board.c
+""")
+
+# add gpio driver code
+if  GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
+    src += ['drv_uart.c']
+
+# add inter flash fal filesystem
+if GetDepend('BSP_USING_INTER_FLASH'):
+	src += Glob('ports/*.c')
+
+path_ports = os.path.join(cwd,'ports')
+CPPPATH = [cwd,path_ports]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/yichip/yc3122-pos/drivers/board.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#include <board.h>
+#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
+    static struct rt_memheap system_heap;
+#endif
+#define SystemCoreClock (48000000)
+
+static void bsp_clock_config(void)
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+}
+
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#ifdef RT_USING_SERIAL
+    extern int rt_hw_uart_init(void);
+#endif
+
+void rt_hw_board_init()
+{
+    bsp_clock_config();
+
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/yichip/yc3122-pos/drivers/board.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+#include <rtthread.h>
+#include <yc3122.h>
+#include "yc_gpio.h"
+#include "yc_uart.h"
+#include "yc_exti.h"
+
+#define SRAM_BASE 0x20000
+#define SRAM_SIZE 0x10000
+
+#ifdef BSP_USING_EXT_SRAM
+    #define EXT_SRAM_BASE SRAMM_BASE
+    #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
+    #define EXT_SRAM_BEGIN EXT_SRAM_BASE
+    #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
+#endif
+
+#define SRAM_END (SRAM_BASE + SRAM_SIZE)
+#if defined(__ARMCC_VERSION)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section = "HEAP"
+    #define HEAP_rBEGIN (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+#define HEAP_END SRAM_END
+#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
+extern void rt_hw_board_init(void);
+#endif

bsp/yichip/yc3122-pos/drivers/drv_gpio.c

@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include <rthw.h>
+
+#define PIN_MAX_NUM     (48)
+
+typedef void (*pin_callback_t)(void *args);
+struct pin
+{
+    uint32_t package_index;
+    const char *name;
+    IRQn_Type irq;
+    rt_uint32_t irq_mode;
+    pin_callback_t callback;
+    void *callback_args;
+};
+typedef struct pin pin_t;
+
+
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+{
+    /* Configure GPIO_InitStructure */
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_CONFIG(pin) = OUTPUT_LOW;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_CONFIG(pin) = INPUT;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_CONFIG(pin) = PULL_PU;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_CONFIG(pin) = PULL_PD;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_CONFIG(pin) = PULL_PU;
+    }
+}
+
+static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+{
+    if (value)
+    {
+        GPIO_CONFIG(pin) = OUTPUT_HIGH;
+    }
+    else
+    {
+        GPIO_CONFIG(pin) = OUTPUT_LOW;
+    }
+}
+
+static rt_int8_t yc_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    //return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0;
+    return GPIO_ReadInputDataBit((GPIO_TypeDef)(pin / 16), (GPIO_Pin_TypeDef)(1 << (pin % 16)));
+}
+
+static rt_err_t yc_pin_attach_irq(struct rt_device *device,
+                                  rt_base_t pin,
+                                  rt_uint8_t mode,
+                                  pin_callback_t cb,
+                                  void *args)
+{
+    rt_int32_t index = -1;
+    rt_base_t level;
+    if (pin >= PIN_MAX_NUM)
+    {
+        return -RT_EINVAL;
+    }
+
+    index = pin;
+    level = rt_hw_interrupt_disable();
+
+    pin_irq_hdr_tab[index].pin = pin;
+    pin_irq_hdr_tab[index].hdr = cb;
+    pin_irq_hdr_tab[index].mode = mode;
+    pin_irq_hdr_tab[index].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_base_t pin)
+{
+    rt_int32_t index = -1;
+    rt_base_t level;
+    if (pin >= PIN_MAX_NUM)
+    {
+        return -RT_EINVAL;
+    }
+
+    index = pin;
+    level = rt_hw_interrupt_disable();
+
+    pin_irq_hdr_tab[index].pin = -1;
+    pin_irq_hdr_tab[index].hdr = RT_NULL;
+    pin_irq_hdr_tab[index].mode = 0;
+    pin_irq_hdr_tab[index].args = RT_NULL;
+
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+static rt_err_t yc_pin_irq_enable(struct rt_device *device,
+                                  rt_base_t pin,
+                                  rt_uint8_t enabled)
+{
+    rt_int32_t index;
+    rt_base_t level = 0;
+    rt_int8_t TrigMode = 0;
+    if (pin >= PIN_MAX_NUM)
+    {
+        return -RT_EINVAL;
+    }
+
+    index = pin;
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        switch (pin_irq_hdr_tab[index].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            TrigMode = EXTI_Trigger_Rising;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            TrigMode = EXTI_Trigger_Falling;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            TrigMode = EXTI_Trigger_Rising_Falling;
+            break;
+        case PIN_IRQ_MODE_HIGH_LEVEL:
+            GPIO_CONFIG(pin) = PULL_PD;
+            TrigMode = EXTI_Trigger_HighLev;
+            break;
+        case PIN_IRQ_MODE_LOW_LEVEL:
+            GPIO_CONFIG(pin) = PULL_PU;
+            TrigMode = EXTI_Trigger_LowLev;
+            break;
+        default:
+            rt_hw_interrupt_enable(level);
+            return -RT_EINVAL;
+        }
+
+        level = rt_hw_interrupt_disable();
+        NVIC_EnableIRQ(GPIO_IRQn);
+        EXTI_LineConfig((EXTI_LineTypeDef)(pin / 16), (EXTI_PIN_TypeDef)(1 << (pin % 16)), (EXTI_TriggerTypeDef)TrigMode);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        NVIC_DisableIRQ(GPIO_IRQn);
+        MGPIO->INTR.reg[pin / 16] &= ~(1 << (pin % 16));
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops yc3122_pin_ops =
+{
+    yc_pin_mode,
+    yc_pin_write,
+    yc_pin_read,
+    yc_pin_attach_irq,
+    yc_pin_detach_irq,
+    yc_pin_irq_enable,
+    RT_NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    result = rt_device_pin_register("pin", &yc3122_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+void GPIO_IRQHandler(void)
+{
+//    int i;
+
+    rt_interrupt_enter();
+//    for (i = 0; i < PIN_MAX_NUM; i++)
+//    {
+//        if ((GPIO_TRIG_MODE(i / 16) & (1 << (i % 16))) == (GPIO_IN(i / 16) & (1 << (i % 16))))
+//        {
+//            if (pin_irq_hdr_tab[i].hdr)
+//            {
+//                pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args);
+//            }
+//        }
+//    }
+    rt_interrupt_leave();
+}

bsp/yichip/yc3122-pos/drivers/drv_gpio.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/yichip/yc3122-pos/drivers/drv_uart.c

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+struct yc3122_uart
+{
+    UART_TypeDef  *uart;
+    IRQn_Type irq;
+};
+
+static rt_err_t yc3122_uart_configure(struct rt_serial_device *serial,
+                                      struct serial_configure *cfg)
+{
+    struct yc3122_uart *uart;
+    UART_InitTypeDef UART_initStruct;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct yc3122_uart *)serial->parent.user_data;
+    NVIC_DisableIRQ(uart->irq);
+    UART_initStruct.BaudRate = cfg->baud_rate;
+    UART_initStruct.FlowCtrl = FLOWCTRL_NONE ;
+    UART_initStruct.CommMode = MODE_DUPLEX;
+    UART_initStruct.SmartCard = SMARTCARD_DISABLE;
+    UART_initStruct.RxMode    = MODE_RX_ENABLE;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_9:
+        UART_initStruct.DataBits = DATABITS_9B;
+        break;
+    default:
+        UART_initStruct.DataBits = DATABITS_8B;
+        break;
+    }
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        UART_initStruct.StopBits = STOPBITS_2;
+        break;
+    default:
+        UART_initStruct.StopBits = STOPBITS_1;
+        break;
+    }
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        UART_initStruct.Parity = YC_PARITY_ODD;
+        break;
+    case PARITY_EVEN:
+        UART_initStruct.Parity = YC_PARITY_EVEN;
+        break;
+    default:
+        UART_initStruct.Parity = YC_PARITY_NONE;
+        break;
+    }
+    UART_Init(uart->uart, &UART_initStruct);
+    return RT_EOK;
+}
+
+static rt_err_t yc3122_uart_control(struct rt_serial_device *serial,
+                                    int cmd, void *arg)
+{
+    struct yc3122_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct yc3122_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_SetRxITNum(uart->uart, 0);
+        NVIC_DisableIRQ(uart->irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ITConfig(uart->uart, UART_IT_RX, ENABLE);
+        UART_SetRxITNum(uart->uart, 1);
+        NVIC_EnableIRQ((IRQn_Type)uart->irq);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int yc3122_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct yc3122_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct yc3122_uart *)serial->parent.user_data;
+    while (UART_IsBusy(uart->uart));
+    UART_SendData(uart->uart, c);
+    return 1;
+}
+
+static int yc3122_uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct yc3122_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct yc3122_uart *)serial->parent.user_data;
+    ch = -1;
+    if (UART_ReceiveDataLen(uart->uart) != 0)
+    {
+        ch = UART_ReceiveData(uart->uart);
+    }
+    return ch;
+}
+
+static const struct rt_uart_ops yc3122_uart_ops =
+{
+    yc3122_uart_configure,
+    yc3122_uart_control,
+    yc3122_uart_putc,
+    yc3122_uart_getc,
+};
+
+#if defined(BSP_USING_UART0)
+/* UART0 device driver structure */
+static struct yc3122_uart uart0;
+static struct rt_serial_device serial0;
+void UART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* UART in mode Receiver */
+    if (UART_GetITIdentity(uart0.uart) == UART_IT_RX)
+    {
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+/* UART1 device driver structure */
+static struct yc3122_uart uart1;
+static struct rt_serial_device serial1;
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* UART in mode Receiver */
+    if (UART_GetITIdentity(uart1.uart) == UART_IT_RX)
+    {
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+int rt_hw_uart_init(void)
+{
+    struct yc3122_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#ifdef BSP_USING_UART0
+
+    GPIO_CONFIG(53) = UART0_TXD;
+    GPIO_CONFIG(54) = UART0_RXD;
+    uart = &uart0;
+    uart->uart = MUART0;
+    uart->irq = UART0_IRQn;
+    serial0.ops = &yc3122_uart_ops;
+    serial0.config = config;
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, RT_CONSOLE_DEVICE_NAME,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART0 */
+#ifdef BSP_USING_UART1
+    GPIO_CONFIG(53) = UART1_TXD;
+    GPIO_CONFIG(54) = UART1_RXD;
+    uart = &uart1;
+    uart->uart = MUART1;
+    uart->irq = UART1_IRQn;
+    serial1.ops = &yc3122_uart_ops;
+    serial1.config = config;
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+    return 0;
+}

bsp/yichip/yc3122-pos/drivers/drv_uart.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WSY          first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/yichip/yc3122-pos/drivers/linker_scripts/link.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x1000200;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x1000200;
+define symbol __ICFEDIT_region_ROM_end__   = 0x1ffffff;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0xF800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/yichip/yc3122-pos/drivers/linker_scripts/link.lds

@@ -0,0 +1,161 @@
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x80000 /* 512K */
+  RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        *flash_start*.o
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+
+     . = ALIGN(4);
+    __exidx_start = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        PROVIDE(end = .);
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

bsp/yichip/yc3122-pos/drivers/linker_scripts/link.sct

@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x01000200 0x0007FE00  {    ; load region size_region
+  ER_IROM1 0x01000200 0x0007FE00  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x00020004 0x0004FFFC  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/yichip/yc3122-pos/drivers/ports/fal_cfg.h

@@ -0,0 +1,51 @@
+/*
+ * File      : fal_cfg.h
+ * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-21     MurphyZhao   the first version
+ */
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable yc3122 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_YC3122
+/* enable SFUD flash driver sample */
+//#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev yc3122_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &yc3122_onchip_flash,                                           \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+#define APP_START_ADDR              (0)
+#define APP_SIZE                    (128*1024)
+#define PARAM_START_ADDR            (APP_START_ADDR+APP_SIZE)
+#define PARAM_SIZE                  (64*1024)
+#define DOWNLOAD_START_ADDR         (PARAM_START_ADDR+PARAM_SIZE)
+#define DOWNLOAD_SIZE               (APP_SIZE)
+#define FONT_START_ADDR             (DOWNLOAD_START_ADDR+DOWNLOAD_SIZE)
+#define FONT_SIZE                   (64*1024)
+#define FILESYSTEM_ADDR             (FONT_START_ADDR+FONT_SIZE)
+#define FILESYSTEM_SIZE             (128*1024)
+/* partition table */
+#define FAL_PART_TABLE                                                                                              \
+{                                                                                                                   \
+    {FAL_PART_MAGIC_WROD,        "app",    "onchip_flash",    APP_START_ADDR,           APP_SIZE, 0}, \
+    {FAL_PART_MAGIC_WROD,      "param",    "onchip_flash",    PARAM_START_ADDR,         PARAM_SIZE, 0}, \
+    {FAL_PART_MAGIC_WROD,   "download",    "onchip_flash",    DOWNLOAD_START_ADDR,      DOWNLOAD_SIZE, 0}, \
+    {FAL_PART_MAGIC_WROD,       "font",    "onchip_flash",    FONT_START_ADDR,          FONT_SIZE, 0}, \
+    {FAL_PART_MAGIC_WROD, "filesystem",    "onchip_flash",    FILESYSTEM_ADDR,          FILESYSTEM_SIZE, 0}, \
+}
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

bsp/yichip/yc3122-pos/drivers/ports/fal_flash_yc3122_port.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2020, YICHIP Development Team
+ * @file
+ * @brief
+ *
+ * Change Logs:
+ * Date            Author             Version        Notes
+ * 2020-11-06      dengzhiqian         V1.0.0         the first version
+ */
+
+#include <fal.h>
+#include "board.h"
+#include "yc_qspi.h"
+#include "rtdbg.h"
+
+#define FLASH_START_ADRESS ((uint32_t)0x1000000)
+#define FLASH_SIZE ((uint32_t)4 * 1024 * 1024)
+#define FLASH_BLOCK_SIZE ((uint32_t)512)
+#define FLASH_END_ADDRESS ((uint32_t)(FLASH_START_ADRESS + FLASH_SIZE))
+#define FLASH_PAGE_NBPERBANK 256
+#define FLASH_BANK_NUMBER 2
+#define FLASH_PAGE_SIZE 256
+// #define LOGOPEN
+#ifdef LOGOPEN
+    #define YC3122_FLASH_DEBUG LOG_D
+#else
+    #define YC3122_FLASH_DEBUG(...)
+#endif
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    uint32_t addr = yc3122_onchip_flash.addr + offset;
+
+    if ((addr + size) > FLASH_END_ADDRESS)
+    {
+        YC3122_FLASH_DEBUG("ERROR: read outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -1;
+    }
+    YC3122_FLASH_DEBUG("r_ addr:0x%x,size:0x%x\n", addr, size);
+    qspi_flash_read(addr, buf, size);
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    uint32_t addr = yc3122_onchip_flash.addr + offset;
+
+    if ((addr + size) > FLASH_END_ADDRESS)
+    {
+        YC3122_FLASH_DEBUG("ERROR: write outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -1;
+    }
+    if (size < 1)
+    {
+        return -1;
+    }
+    YC3122_FLASH_DEBUG("w_ addr:0x%x,size:0x%x\n", addr, size);
+    qspi_flash_write(addr, (uint8_t *)buf, size);
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    uint32_t addr = yc3122_onchip_flash.addr + offset;
+    if ((addr + size) > FLASH_END_ADDRESS || addr % 0x100 != 0)
+    {
+        YC3122_FLASH_DEBUG("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -1;
+    }
+    YC3122_FLASH_DEBUG("s_ addr:0x%x,size:0x%x\n", addr, size);
+    if (addr % FLASH_PAGE_SIZE != 0)
+    {
+        YC3122_FLASH_DEBUG("ERROR: erase addr is not page alignment\n");
+    }
+    for (uint32_t i = 0; i < size; i += 256)
+        qspi_flash_pageerase(addr + i);
+    return size;
+}
+
+const struct fal_flash_dev yc3122_onchip_flash =
+{
+    "onchip_flash",
+    FLASH_START_ADRESS,
+    FLASH_SIZE,
+    FLASH_BLOCK_SIZE,
+    {NULL, read, write, erase},
+    8,
+};

bsp/yichip/yc3122-pos/project.ewd

@@ -0,0 +1,2834 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rt-thread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>29</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
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+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\Synwit\SWM320.ddf</state>
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+                    <name>RunToEnable</name>
+                    <state>1</state>
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+                <option>
+                    <name>RunToName</name>
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+                    <name>CExtraOptions</name>
+                    <state></state>
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+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
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+                    <name>OCDownloadSuppressDownload</name>
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+                <option>
+                    <name>OCDownloadVerifyAll</name>
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+                    <name>CLowLevel</name>
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+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
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+                    <name>CDevice</name>
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+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$\config\flashloader\Synwit\FlashSWM320xE.board</state>
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+                    <name>OCImagesSuppressCheck1</name>
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+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
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+                    <name>OCImagesPath2</name>
+                    <state></state>
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+                    <state>0</state>
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+                    <name>OCImagesPath3</name>
+                    <state></state>
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+                    <name>OverrideDefFlashBoard</name>
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+                    <name>OCImagesOffset1</name>
+                    <state></state>
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+                    <name>OCImagesOffset2</name>
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+                    <name>OCImagesOffset3</name>
+                    <state></state>
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+                    <name>OCAllMTBOptions</name>
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+                    <state>53461</state>
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+                    <name>OCMulticoreWorkspace</name>
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+                    <state></state>
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+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
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+                    <name>OCDownloadExtraImage</name>
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+                <option>
+                    <name>OCAttachSlave</name>
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+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
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+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
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+                <version>1</version>
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+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
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+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
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+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
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+                    <name>OCDriverInfo</name>
+                    <state>1</state>
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+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
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+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
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+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
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+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
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+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
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+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
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+                    <name>CMSISDAPJtagSpeedList</name>
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+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
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+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
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+                <option>
+                    <name>RDICatchReset</name>
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+                    <name>RDICatchUndef</name>
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+                    <name>RDICatchSWI</name>
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+                    <name>RDICatchData</name>
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+                    <name>RDICatchPrefetch</name>
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+                    <name>RDICatchIRQ</name>
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+                    <name>RDICatchFIQ</name>
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+                    <name>CatchCORERESET</name>
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+                    <name>CatchBUSERR</name>
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+                    <name>CatchDummy</name>
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+                    <name>CMSISDAPMultiCPUEnable</name>
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+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
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+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
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+                    <name>OCProbeConfig</name>
+                    <state></state>
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+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
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+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
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+                    <name>ICpuName</name>
+                    <state></state>
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+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
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+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
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+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
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+                <wantNonLocal>1</wantNonLocal>
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+                    <state>1</state>
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+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
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+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
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+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
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+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
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+            <archiveVersion>2</archiveVersion>
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+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
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+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
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+                    <state>10</state>
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+                    <state>300</state>
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+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
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+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
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+                    <name>IjetPowerRadio</name>
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+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
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+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
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+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
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+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
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+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
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+                <option>
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+                    <name>IjetIRLength</name>
+                    <state>0</state>
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+                    <name>IjetJtagSpeedList</name>
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+                    <state>0</state>
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+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
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+                    <name>IjetSwoPin</name>
+                    <state>0</state>
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+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
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+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
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+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
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+                <option>
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+                    <name>RDICatchUndef</name>
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+                    <name>RDICatchFIQ</name>
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+                    <name>CCJLinkDoUpdateBreakpoints</name>
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+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>7</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>6</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+                <loadFlag>1</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>29</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.20.1.14181</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>ARMSIM_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreMaster</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticorePort</name>
+                    <state>53461</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
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+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>6</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+                <loadFlag>1</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>

bsp/yichip/yc3122-pos/project.ewp

@@ -0,0 +1,2303 @@
+<project>
+  <fileVersion>3</fileVersion>
+  <configuration>
+    <name>rt-thread</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>29</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>build\iar\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\iar\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\iar\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>6.30.6.53380</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>8.11.3.13977</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>SWM320xE	Synwit SWM320xE</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>25</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>25</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>SWM320xE	Synwit SWM320xE</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>25</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>OGCMSISPackSelectDevice</name>
+        </option>
+        <option>
+          <name>OgLibHeap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGLibAdditionalLocale</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenLocaleTags</name>
+          <state />
+        </option>
+        <option>
+          <name>GenLocaleDisplayOnly</name>
+          <state />
+        </option>
+        <option>
+          <name>DSPExtension</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>34</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state />
+          <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
+          <state>RT_USING_DLIBC</state>
+          <state>RT_USING_LIBC</state>
+          <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
+          <state>__RTTHREAD__</state>
+          <state>__USE_YC_M0__</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state />
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
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+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state />
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state />
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogCallGraph</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile_AltDefault</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkEncInput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutputBom</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkHeapSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLocaleSelect</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state />
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data />
+    </settings>
+  </configuration>
+  <group>
+    <name>Applications</name>
+    <file>
+      <name>$PROJ_DIR$\applications\main.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Compiler</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+    </file>
+  </group>
+  <group>
+    <name>CPU</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\context_iar.S</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\cpuport.c</name>
+    </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\mtd\mtd_nor.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\sfud\src\sfud.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\sfud\src\sfud_sfdp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\spi\spi_flash_sfud.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Drivers</name>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\board.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Finsh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\scheduler_up.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Libraries</name>
+    <file>
+      <name>$PROJ_DIR$\Libraries\core\system.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\sdk\yc_wdt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\sdk\yc_exti.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\sdk\yc_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\iar\startup_yc3122.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\sdk\yc_gpio.c</name>
+    </file>
+  </group>
+  <group>
+    <name>POSIX</name>
+  </group>
+</project>

bsp/yichip/yc3122-pos/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/yichip/yc3122-pos/project.uvoptx

@@ -0,0 +1,925 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Compiler</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
+      <FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
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bsp/yichip/yc3122-pos/project.uvprojx

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+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls>  --c99</MiscControls>
+                      <Define> </Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>sfud_sfdp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\sfud\src\sfud_sfdp.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls>  --c99</MiscControls>
+                      <Define> </Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls>  --c99</MiscControls>
+                      <Define> </Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls>  --c99</MiscControls>
+                      <Define> </Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>spi_flash_sfud.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\spi_flash_sfud.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls>  --c99</MiscControls>
+                      <Define> </Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\board.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_parse.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>memheap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\memheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler_up.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler_up.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>yc_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\sdk\yc_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>yc_wdt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\sdk\yc_wdt.c</FilePath>
+            </File>
+            <File>
+              <FileName>system.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\core\system.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_yc3122.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\arm\startup_yc3122.s</FilePath>
+            </File>
+            <File>
+              <FileName>sdk_yc_qspi.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>Libraries\sdk\yc_qspi.lib</FilePath>
+            </File>
+            <File>
+              <FileName>system_yc3122.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c</FilePath>
+            </File>
+            <File>
+              <FileName>yc_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\sdk\yc_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>yc_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\sdk\yc_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/yichip/yc3122-pos/rtconfig.h

@@ -0,0 +1,239 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50001
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+#define RT_USING_MTD_NOR
+#define RT_USING_SPI
+#define RT_USING_SFUD
+#define RT_SFUD_USING_SFDP
+#define RT_SFUD_USING_FLASH_INFO_TABLE
+#define RT_SFUD_SPI_MAX_HZ 50000000
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_YC3122
+
+/* Hardware Drivers Config */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+
+/* UART Drivers */
+
+#define BSP_USING_UART0
+
+#endif

bsp/yichip/yc3122-pos/rtconfig.py

@@ -0,0 +1,152 @@
+# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad	(REV D)
+
+import os
+import sys
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+# device options
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+    PLATFORM = 'gcc'
+    EXEC_PATH = 'C:\gcc-arm-none-eabi-7-2018-q2-update-win32'
+elif CROSS_TOOL == 'keil':
+    PLATFORM = 'armcc'
+    EXEC_PATH = 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iccarm'
+    EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M0 '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "drivers\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf.exe --text -a -c --output=@L_asm.txt "!L" \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M0'
+    AFLAGS += ' --fpu None'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/yichip/yc3122-pos/template.ewp

@@ -0,0 +1,2032 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rt-thread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>29</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>build\iar\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>build\iar\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>build\iar\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>6.30.6.53380</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.11.3.13977</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>SWM320xE	Synwit SWM320xE</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>25</version>
+                    <state>39</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>25</version>
+                    <state>39</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>SWM320xE	Synwit SWM320xE</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>25</version>
+                    <state>39</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>34</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state>Pa050</state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>../../../rtthread.bin</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>20</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>rtthread.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>__iar_program_start</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>29</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>Release\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Release\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Release\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>6.30.6.53380</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.11.3.13977</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>Default	None</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>25</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>25</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>Default	None</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>25</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>34</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>11111110</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>20</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>lnk0t.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+</project>

bsp/yichip/yc3122-pos/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/yichip/yc3122-pos/template.uvopt

@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32F4xx\DM00053488.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F4xx\DM00031020.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>0</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>6</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-O207 -S0 -C0 -FO7  -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/yichip/yc3122-pos/template.uvoptx

@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/yichip/yc3122-pos/template.uvprojx

@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.5.1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf.exe --text -a -c --output=@L_asm.txt "!L"</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4100</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>1</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>