[bsp][driver][renesas] Unified Renesas SCI driver

bsp/renesas/ebf_qi_min_6m5/.config

@@ -278,16 +278,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -309,6 +299,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -330,7 +321,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -351,7 +341,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -496,9 +485,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -518,8 +504,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -557,35 +541,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -667,8 +627,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -676,6 +637,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -690,6 +659,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -712,6 +682,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -721,6 +692,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -728,6 +700,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -736,9 +709,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -753,7 +723,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -763,6 +732,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -838,9 +808,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -848,13 +816,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -899,7 +867,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -938,6 +906,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -960,7 +929,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -968,7 +937,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -981,7 +950,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1007,7 +975,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1024,11 +991,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1051,6 +1018,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 # CONFIG_SOC_SERIES_R7FA6M3 is not set
 # CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1058,6 +1026,7 @@ CONFIG_SOC_FAMILY_RENESAS=y
 CONFIG_SOC_SERIES_R7FA6M5=y
 # CONFIG_SOC_SERIES_R7FA4M2 is not set
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1081,9 +1050,10 @@ CONFIG_BSP_USING_UART4=y
 # CONFIG_BSP_UART4_TX_USING_DMA is not set
 CONFIG_BSP_UART4_RX_BUFSIZE=256
 CONFIG_BSP_UART4_TX_BUFSIZE=0
-# CONFIG_BSP_USING_I2C is not set
-# CONFIG_BSP_USING_SCI_SPI is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
 # CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ebf_qi_min_6m5/board/Kconfig

@@ -21,7 +21,6 @@ menu "Hardware Drivers Config"
             select RT_USING_SERIAL
             select RT_USING_SERIAL_V2
             if BSP_USING_UART
-
                 menuconfig BSP_USING_UART4
                     bool "Enable UART4"
                     default n
@@ -50,109 +49,385 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_I2C
-            bool "Enable I2C BUS"
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
             default n
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C1
+                    bool "Enable Hardware I2C1 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SOFT_I2C
+            bool "Enable software I2C bus"
             select RT_USING_I2C
             select RT_USING_I2C_BITOPS
             select RT_USING_PIN
-            if BSP_USING_I2C
-                menuconfig BSP_USING_SCI_I2C
-                    bool "Enable SCI I2C BUS"
+            default n
+            if BSP_USING_SOFT_I2C
+                config BSP_USING_SOFT_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 Bus (software simulation)"
                     default n
-                    if BSP_USING_SCI_I2C
-                        config BSP_USING_SCI_I2C0
-                            bool "Enable SCI I2C0 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C1
-                            bool "Enable SCI I2C1 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C2
-                            bool "Enable SCI I2C2 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C3
-                            bool "Enable SCI I2C3 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C4
-                            bool "Enable SCI I2C4 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C5
-                            bool "Enable SCI I2C5 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C6
-                            bool "Enable SCI I2C6 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C7
-                            bool "Enable SCI I2C7 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C8
-                            bool "Enable SCI I2C8 BUS"
-                            default n
-                        config BSP_USING_SCI_I2C9
-                            bool "Enable SCI I2C9 BUS"
-                            default n
+                    if BSP_USING_I2C1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050C
+                        config BSP_I2C1_SDA_PIN
+                            hex "i2c1 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050B
                     endif
-                config BSP_USING_HW_I2C
-                    bool "Enable Hardware I2C BUS"
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI 
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
                     default n
-                if BSP_USING_HW_I2C
-                    config BSP_USING_HW_I2C1
-                        bool "Enable Hardware I2C1 BUS"
-                        default n
-                endif
-                if !BSP_USING_HW_I2C
-                    menuconfig BSP_USING_I2C1
-                        bool "Enable I2C1 BUS (software simulation)"
-                        default n
-                        if BSP_USING_I2C1
-                            config BSP_I2C1_SCL_PIN
-                                hex "i2c1 scl pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050C
-                            config BSP_I2C1_SDA_PIN
-                                hex "I2C1 sda pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050B
-                        endif
-                endif
             endif
 
-        menuconfig BSP_USING_SCI_SPI
-            bool "Enable SCI SPI BUS"
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
             default n
+            config BSP_USING_SCIn_SPI
+                bool
+                default n
+                depends on BSP_USING_SCI
             select RT_USING_SPI
-            if BSP_USING_SCI_SPI 
-                config BSP_USING_SCI_SPI0
-                    bool "Enable SCI SPI0 BUS"
+
+            config BSP_USING_SCIn_I2C
+                bool
+                default n
+                depends on BSP_USING_SCI
+                select RT_USING_I2C
+
+            config BSP_USING_SCIn_UART
+                bool
+                default n
+                depends on BSP_USING_SCI
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
                     default n
-                config BSP_USING_SCI_SPI1
-                    bool "Enable SCI SPI1 BUS"
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
                     default n
-                config BSP_USING_SCI_SPI2
-                    bool "Enable SCI SPI2 BUS"
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
                     default n
-                config BSP_USING_SCI_SPI3
-                    bool "Enable SCI SPI3 BUS"
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
                     default n
-                config BSP_USING_SCI_SPI5
-                    bool "Enable SCI SPI5 BUS"
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
                     default n
-                config BSP_USING_SCI_SPI6
-                    bool "Enable SCI SPI6 BUS"
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
                     default n
-            endif
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
 
-        menuconfig BSP_USING_SPI
-            bool "Enable SPI BUS"
-            default n
-            select RT_USING_SPI
-            if BSP_USING_SPI 
-                config BSP_USING_SPI0
-                    bool "Enable SPI0 BUS"
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
                     default n
-                config BSP_USING_SPI1
-                    bool "Enable SPI1 BUS"
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
                     default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
             endif
 
     endmenu

bsp/renesas/ebf_qi_min_6m5/project.uvprojx

@@ -333,9 +333,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS</Define>
               <Undefine />
-              <IncludePath>..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\include;.;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\posix\io\poll;board\ports;board;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal</IncludePath>
+              <IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m4;board;..\..\..\components\libc\posix\ipc;board\ports;..\..\..\components\libc\posix\io\eventfd;..\libraries\HAL_Drivers\config;.;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\libraries\HAL_Drivers;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -475,6 +475,25 @@
               </FileOption>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>condvar.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_IPC_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath> </IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
           <Files>
             <File>
               <FileName>dataqueue.c</FileName>
@@ -692,30 +711,30 @@
           <GroupName>Finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>msh.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_parse.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/renesas/ebf_qi_min_6m5/rtconfig.h

@@ -137,12 +137,6 @@
 /* CYW43012 WiFi */
 
 
-/* BL808 WiFi */
-
-
-/* CYW43439 WiFi */
-
-
 /* IoT Cloud */
 
 
@@ -184,20 +178,15 @@
 
 /* peripheral libraries and drivers */
 
-/* HAL & SDK Drivers */
-
-/* STM32 HAL & SDK Drivers */
-
-
-/* Kendryte SDK */
-
-
 /* sensors drivers */
 
 
 /* touch drivers */
 
 
+/* Kendryte SDK */
+
+
 /* AI packages */
 
 

bsp/renesas/libraries/HAL_Drivers/SConscript

@@ -32,15 +32,9 @@ if GetDepend(['BSP_USING_SOFT_I2C']):
 if GetDepend(['BSP_USING_HW_I2C']):
         src += ['drv_i2c.c']
 
-if GetDepend(['BSP_USING_SCI_I2C']):
-        src += ['drv_sci_i2c.c']
-
 if GetDepend(['BSP_USING_SPI']):
     src += ['drv_spi.c']
 
-if GetDepend(['BSP_USING_SCI_SPI']):
-    src += ['drv_sci_spi.c']
-
 if GetDepend(['BSP_USING_SOFT_SPI']):
     src += ['drv_soft_spi.c']
 

bsp/renesas/libraries/HAL_Drivers/drv_gpio.c

@@ -115,6 +115,15 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     fsp_err_t err;
 
+    /* Initialize the IOPORT module and configure the pins */
+    err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("GPIO open failed");
+        return;
+    }
+
     switch (mode)
     {
     case PIN_MODE_OUTPUT:
@@ -346,16 +355,6 @@ int rt_hw_pin_init(void)
     ra_pin_map_init();
 #endif
 
-    fsp_err_t err;
-    /* Initialize the IOPORT module and configure the pins */
-    err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
-
-    if (err != FSP_SUCCESS)
-    {
-        LOG_E("GPIO open failed");
-        return -1;
-    }
-
     return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
 }
 

bsp/renesas/libraries/HAL_Drivers/drv_pwm.c

@@ -10,7 +10,7 @@
 
 #include "drv_pwm.h"
 
-#ifdef RT_USING_PWM
+#ifdef BSP_USING_PWM
 
 /* Declare the control function first */
 static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
@@ -217,4 +217,4 @@ int rt_hw_pwm_init(void)
     return ret;
 }
 INIT_BOARD_EXPORT(rt_hw_pwm_init);
-#endif /* RT_USING_PWM */
+#endif /* BSP_USING_PWM */

bsp/renesas/libraries/HAL_Drivers/drv_sci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -80,7 +80,7 @@ struct ra_sci_param
 #ifdef RT_USING_SPI
     rt_weak const struct rt_spi_ops            sci_ops_spi;
 #endif
-#ifdef RT_USING_UART
+#ifdef RT_USING_SERIAL
     rt_weak const struct rt_uart_ops           sci_ops_uart;
 #endif
 
@@ -101,7 +101,7 @@ struct ra_sci_object
             struct rt_i2c_bus_device    ibus;
         };
 #endif
-#ifdef RT_USING_UART
+#ifdef RT_USING_SERIAL
         struct
         {
             struct rt_serial_device     ubus;
@@ -121,12 +121,14 @@ struct ra_sci_object
 #define RA_SCI_EVENT_ERROR          8
 #define RA_SCI_EVENT_ALL            15
 
-#if defined(SOC_SERIES_R7FA4M2)
-#define RA_SCI_HANDLE_ITEM(idx,type,id)    {.bus_name=CONCAT3STR(sci_,type,idx),.sci_ctrl=&g_sci##idx##_ctrl,.sci_cfg=&g_sci##idx##_cfg,.ops=&sci_ops_##type}
-#else
-#define RA_SCI_HANDLE_ITEM(idx,type,id)    {.bus_name=CONCAT3STR(sci_,type,idx),.sci_ctrl=&g_##type##idx##_ctrl,.sci_cfg=&g_##type##idx##_cfg,.ops=&sci_ops_##type}
-#endif
-
+/**
+ * Bus name format: sci[x][y], where x=0~9 and y=s/i/u
+ * Example:
+ * - sci_spi:  sci0s
+ * - sci_i2c:  sci0i
+ * - sci_uart: sci0u
+ */
+#define RA_SCI_HANDLE_ITEM(idx,type,id)    {.bus_name=CONCAT3STR(sci,idx,id),.sci_ctrl=&g_sci##idx##_ctrl,.sci_cfg=&g_sci##idx##_cfg,.ops=&sci_ops_##type}
 
 const static struct ra_sci_param sci_param[] =
 {
@@ -667,12 +669,8 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
     /**< config bitrate */
 #ifdef R_SCI_B_SPI_H
     R_SCI_B_SPI_CalculateBitrate(obj->spi_cfg->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
-#else
-#if defined(SOC_SERIES_R7FA4M2)
-    R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &cfg_ext->clk_div, false);
 #else
     R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &spi_cfg->clk_div, false);
-#endif
 #endif
 
     /**< init */
@@ -753,6 +751,7 @@ const struct rt_spi_ops sci_ops_spi =
 
 static int ra_hw_sci_init(void)
 {
+    int bufsz_idx = 0;
     for (rt_uint8_t idx = 0; idx < RA_SCI_INDEX_MAX; idx++)
     {
         struct ra_sci_object *obj = &sci_obj[idx];

bsp/renesas/libraries/HAL_Drivers/drv_sci.h

@@ -23,7 +23,9 @@
 extern "C" {
 #endif
 
-rt_err_t drv_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
+#ifdef BSP_USING_SCIn_SPI
+rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
+#endif
 
 #ifdef __cplusplus
 }

bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c

@@ -1,209 +0,0 @@
-/*
- * Copyright (c) 2006-2023, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2023-06-04     vandoul       first version
- */
-
-#include <rtdevice.h>
-#include <rtthread.h>
-#include "board.h"
-
-#include <stdlib.h>
-
-#ifdef BSP_USING_SCI_I2C
-
-#define DBG_TAG              "drv.sci2c"
-#ifdef DRV_DEBUG
-    #define DBG_LVL               DBG_LOG
-#else
-    #define DBG_LVL               DBG_INFO
-#endif /* DRV_DEBUG */
-#include <rtdbg.h>
-
-#include <hal_data.h>
-
-struct ra_sci_i2c_handle
-{
-    struct rt_i2c_bus_device bus;
-    char bus_name[RT_NAME_MAX];
-    const i2c_master_cfg_t *i2c_cfg;
-    void *i2c_ctrl;
-    struct rt_event event;
-};
-
-enum
-{
-    I2C_EVENT_ABORTED     = 1UL<<I2C_MASTER_EVENT_ABORTED    ,  ///< A transfer was aborted
-    I2C_EVENT_RX_COMPLETE = 1UL<<I2C_MASTER_EVENT_RX_COMPLETE,  ///< A receive operation was completed successfully
-    I2C_EVENT_TX_COMPLETE = 1UL<<I2C_MASTER_EVENT_TX_COMPLETE,  ///< A transmit operation was completed successfully
-};
-#define I2C_EVENT_ALL       (I2C_EVENT_ABORTED|I2C_EVENT_RX_COMPLETE|I2C_EVENT_TX_COMPLETE)
-
-//static volatile  = I2C_MASTER_EVENT_ABORTED;
-static struct ra_sci_i2c_handle ra_sci_i2cs[] =
-{
-#ifdef BSP_USING_SCI_I2C0
-    {.bus_name = "sci2c0", .i2c_cfg = &g_sci_i2c0_cfg, .i2c_ctrl = &g_sci_i2c0_ctrl,},
-#endif
-#ifdef BSP_USING_SCI_I2C1
-    {.bus_name = "sci2c1", .i2c_cfg = &g_sci_i2c1_cfg, .i2c_ctrl = &g_sci_i2c1_ctrl,},
-#endif
-#ifdef BSP_USING_SCI_I2C2
-    {.bus_name = "sci2c2", .i2c_cfg = &g_sci_i2c2_cfg, .i2c_ctrl = &g_sci_i2c2_ctrl,},
-#endif
-#ifdef BSP_USING_SCI_I2C3
-    {.bus_name = "sci2c3", .i2c_cfg = &g_sci_i2c3_cfg, .i2c_ctrl = &g_sci_i2c3_ctrl,},
-#endif
-#ifdef BSP_USING_SCI_I2C4
-    {.bus_name = "sci2c4", .i2c_cfg = &g_sci_i2c4_cfg, .i2c_ctrl = &g_sci_i2c4_ctrl,},
-#endif
-#ifdef BSP_USING_SCI_I2C5
-    {.bus_name = "sci2c5", .i2c_cfg = &g_sci_i2c5_cfg, .i2c_ctrl = &g_sci_i2c5_ctrl,},
-#endif
-};
-
-void sci_i2c_master_callback(i2c_master_callback_args_t *p_args)
-{
-    if (NULL != p_args)
-    {
-        /* capture callback event for validating the i2c transfer event*/
-        struct ra_sci_i2c_handle *ra_sci_i2c = (struct ra_sci_i2c_handle *)p_args->p_context;
-        rt_event_send(&ra_sci_i2c->event, 1UL << p_args->event);
-        LOG_D("event:%x", p_args->event);
-    }
-    LOG_D("p_args:%p", p_args);
-}
-
-static rt_err_t validate_i2c_event(struct ra_sci_i2c_handle *handle)
-{
-    rt_uint32_t event = 0;
-    if(RT_EOK != rt_event_recv(&handle->event, I2C_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(10), &event))
-    {
-        return -RT_ETIMEOUT;
-    }
-    if(event != I2C_EVENT_ABORTED)
-    {
-        return RT_EOK;
-    }
-
-    return -RT_ERROR;
-}
-
-static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
-                                struct rt_i2c_msg msgs[],
-                                rt_uint32_t num)
-{
-    rt_size_t i;
-    struct rt_i2c_msg *msg = msgs;
-    RT_ASSERT(bus != RT_NULL);
-    struct ra_sci_i2c_handle *ra_sci_i2c = rt_container_of(bus, struct ra_sci_i2c_handle, bus);
-    i2c_master_ctrl_t *master_ctrl = ra_sci_i2c->i2c_ctrl;
-    fsp_err_t err     = FSP_SUCCESS;
-    bool restart = false;
-
-    for (i = 0; i < num; i++)
-    {
-        if (msg[i].flags & RT_I2C_NO_START)
-        {
-            restart = true;
-        }
-        if (msg[i].flags & RT_I2C_ADDR_10BIT)
-        {
-            //LOG_E("10Bit not support");
-            //break;
-            R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT);
-        }
-        else
-        {
-            //master_ctrl->slave = msg[i].addr;
-            R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT);
-        }
-
-        if (msg[i].flags & RT_I2C_RD)
-        {
-            err = R_SCI_I2C_Read(master_ctrl, msg[i].buf, msg[i].len, restart);
-            if (FSP_SUCCESS == err)
-            {
-                /* handle error */
-                if(RT_EOK != validate_i2c_event(ra_sci_i2c))
-                {
-                    //LOG_E("POWER_CTL reg I2C read failed,%d", ra_sci_i2c->event);
-                    break;
-                }
-            }
-            /* handle error */
-            else
-            {
-                /* Write API returns itself is not successful */
-                //LOG_E("R_IIC_MASTER_Write API failed");
-                break;
-            }
-        }
-        else
-        {
-            err = R_SCI_I2C_Write(master_ctrl, msg[i].buf, msg[i].len, restart);
-            if (FSP_SUCCESS == err)
-            {
-                if(RT_EOK != validate_i2c_event(ra_sci_i2c))
-                {
-                    //LOG_E("POWER_CTL reg I2C write failed,%d", ra_sci_i2c->event);
-                    break;
-                }
-            }
-            /* handle error */
-            else
-            {
-                /* Write API returns itself is not successful */
-                //LOG_E("R_IIC_MASTER_Write API failed");
-                break;
-            }
-        }
-    }
-    return (rt_ssize_t)i;
-}
-
-static const struct rt_i2c_bus_device_ops ra_i2c_ops =
-{
-    .master_xfer        = ra_i2c_mst_xfer,
-    .slave_xfer         = RT_NULL,
-    .i2c_bus_control    = RT_NULL
-};
-
-int ra_hw_i2c_init(void)
-{
-    fsp_err_t err     = FSP_SUCCESS;
-    for(rt_uint32_t i=0; i<sizeof(ra_sci_i2cs)/sizeof(ra_sci_i2cs[0]); i++)
-    {
-        ra_sci_i2cs[i].bus.ops = &ra_i2c_ops;
-        ra_sci_i2cs[i].bus.priv = 0;
-        if(RT_EOK != rt_event_init(&ra_sci_i2cs[i].event, ra_sci_i2cs[i].bus_name, RT_IPC_FLAG_FIFO))
-        {
-            LOG_E("init event failed");
-            continue;
-        }
-        /* opening IIC master module */
-        err = R_SCI_I2C_Open(ra_sci_i2cs[i].i2c_ctrl, ra_sci_i2cs[i].i2c_cfg);
-        if(err != FSP_SUCCESS)
-        {
-            LOG_E("R_IIC_MASTER_Open API failed,%d", err);
-            continue;
-        }
-        err = R_SCI_I2C_CallbackSet(ra_sci_i2cs[i].i2c_ctrl, sci_i2c_master_callback, &ra_sci_i2cs[i], RT_NULL);
-        /* handle error */
-        if (FSP_SUCCESS != err)
-        {
-            LOG_E("R_SCI_I2C_CallbackSet API failed,%d", err);
-            continue;
-        }
-        rt_i2c_bus_device_register(&ra_sci_i2cs[i].bus, ra_sci_i2cs[i].bus_name);
-    }
-
-    return 0;
-}
-INIT_DEVICE_EXPORT(ra_hw_i2c_init);
-
-#endif /* BSP_USING_I2C */

bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.c

@@ -1,391 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-08-23     Mr.Tiger     first version
- * 2021-11-04     Sherman      ADD complete_event
- * 2022-12-7      Vandoul      ADD sci spi
- */
-/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
-
-#include "drv_sci_spi.h"
-
-#ifdef RT_USING_SPI
-
-//#define DRV_DEBUG
-#define DBG_TAG              "drv.scispi"
-#ifdef DRV_DEBUG
-    #define DBG_LVL               DBG_LOG
-#else
-    #define DBG_LVL               DBG_INFO
-#endif /* DRV_DEBUG */
-#include <rtdbg.h>
-
-#ifdef R_SCI_B_SPI_H
-#define R_SCI_SPI_Write R_SCI_B_SPI_Write
-#define R_SCI_SPI_Read R_SCI_B_SPI_Read
-#define R_SCI_SPI_WriteRead R_SCI_B_SPI_WriteRead
-#define R_SCI_SPI_Open R_SCI_B_SPI_Open
-#define R_SCI_SPI_Close R_SCI_B_SPI_Close
-#endif
-
-#define RA_SCI_SPI0_EVENT 0x0001
-#define RA_SCI_SPI1_EVENT 0x0002
-#define RA_SCI_SPI2_EVENT 0x0004
-#define RA_SCI_SPI3_EVENT 0x0008
-#define RA_SCI_SPI4_EVENT 0x0010
-#define RA_SCI_SPI5_EVENT 0x0020
-#define RA_SCI_SPI6_EVENT 0x0040
-#define RA_SCI_SPI7_EVENT 0x0080
-#define RA_SCI_SPI8_EVENT 0x0100
-#define RA_SCI_SPI9_EVENT 0x0200
-static struct rt_event complete_event = {0};
-
-static struct ra_sci_spi_handle spi_handle[] =
-{
-#ifdef BSP_USING_SCI_SPI0
-    {.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI1
-    {.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI2
-    {.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI3
-    {.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI4
-    {.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI5
-    {.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI6
-    {.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI7
-    {.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI8
-    {.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
-#endif
-
-#ifdef BSP_USING_SCI_SPI9
-    {.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
-#endif
-};
-
-static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
-#define SCI_SPIx_CALLBACK(n)        \
-void sci_spi##n##_callback(spi_callback_args_t *p_args) \
-{ \
-    rt_interrupt_enter(); \
-    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
-    { \
-        rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
-    } \
-    rt_interrupt_leave(); \
-}
-
-SCI_SPIx_CALLBACK(0);
-SCI_SPIx_CALLBACK(1);
-SCI_SPIx_CALLBACK(2);
-SCI_SPIx_CALLBACK(3);
-SCI_SPIx_CALLBACK(4);
-SCI_SPIx_CALLBACK(5);
-SCI_SPIx_CALLBACK(6);
-SCI_SPIx_CALLBACK(7);
-SCI_SPIx_CALLBACK(8);
-SCI_SPIx_CALLBACK(9);
-
-#define SCI_SPIx_EVENT_RECV(n)      \
-    rt_event_recv(event, \
-    RA_SCI_SPI##n##_EVENT, \
-    RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
-    rt_tick_from_millisecond(1000), \
-    &recved);
-
-static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
-{
-    rt_uint32_t recved = 0x00;
-    rt_err_t ret = RT_EOK;
-
-    switch (bus_name[4])
-    {
-    case '0':
-        ret = SCI_SPIx_EVENT_RECV(0);
-        break;
-    case '1':
-        ret = SCI_SPIx_EVENT_RECV(1);
-        break;
-    case '2':
-        ret = SCI_SPIx_EVENT_RECV(2);
-        break;
-    case '3':
-        ret = SCI_SPIx_EVENT_RECV(3);
-        break;
-    case '4':
-        ret = SCI_SPIx_EVENT_RECV(4);
-        break;
-    case '5':
-        ret = SCI_SPIx_EVENT_RECV(5);
-        break;
-    case '6':
-        ret = SCI_SPIx_EVENT_RECV(6);
-        break;
-    case '7':
-        ret = SCI_SPIx_EVENT_RECV(7);
-        break;
-    case '8':
-        ret = SCI_SPIx_EVENT_RECV(8);
-        break;
-    case '9':
-        ret = SCI_SPIx_EVENT_RECV(9);
-        break;
-    default:
-        break;
-    }
-    if (ret != RT_EOK)
-    {
-        LOG_D("%s ra_wait_complete failed!", bus_name);
-        return ret;
-    }
-    return -RT_EINVAL;
-}
-
-static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
-{
-    spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
-    if(data_width == 1)
-        bit_width = SPI_BIT_WIDTH_8_BITS;
-    else if(data_width == 2)
-        bit_width = SPI_BIT_WIDTH_16_BITS;
-    else if(data_width == 4)
-        bit_width = SPI_BIT_WIDTH_32_BITS;
-
-    return bit_width;
-}
-
-static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
-{
-    RT_ASSERT(device != NULL);
-    RT_ASSERT(send_buf != NULL);
-    RT_ASSERT(len > 0);
-    rt_err_t err = RT_EOK;
-    struct ra_sci_spi *spi_dev =  rt_container_of(device->bus, struct ra_sci_spi, bus);
-
-    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
-    /**< send msessage */
-    err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
-    if (RT_EOK != err)
-    {
-        LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
-        return -RT_ERROR;
-    }
-    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
-    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
-    return len;
-}
-
-static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
-{
-    RT_ASSERT(device != NULL);
-    RT_ASSERT(recv_buf != NULL);
-    RT_ASSERT(len > 0);
-    rt_err_t err = RT_EOK;
-    struct ra_sci_spi *spi_dev =  rt_container_of(device->bus, struct ra_sci_spi, bus);
-
-    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
-    /**< receive message */
-    err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
-    if (RT_EOK != err)
-    {
-        LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
-        return -RT_ERROR;
-    }
-    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
-    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
-    return len;
-}
-
-static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
-{
-    RT_ASSERT(device != NULL);
-    RT_ASSERT(message != NULL);
-    RT_ASSERT(message->length > 0);
-    rt_err_t err = RT_EOK;
-    struct ra_sci_spi *spi_dev =  rt_container_of(device->bus, struct ra_sci_spi, bus);
-
-    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
-    /**< write and receive message */
-    err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
-    if (RT_EOK != err)
-    {
-        LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
-        return -RT_ERROR;
-    }
-    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
-    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
-    return message->length;
-}
-
-/**< init spi TODO : MSB does not support modification */
-static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
-                                    struct rt_spi_configuration *configuration)
-{
-    RT_ASSERT(device != NULL);
-    RT_ASSERT(configuration != NULL);
-    rt_err_t err = RT_EOK;
-
-    struct ra_sci_spi *spi_dev =  rt_container_of(device->bus, struct ra_sci_spi, bus);
-
-    /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
-    rt_uint8_t data_width = configuration->data_width / 8;
-    RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
-    configuration->data_width = configuration->data_width / 8;
-    spi_dev->rt_spi_cfg_t = configuration;
-
-#ifdef R_SCI_B_SPI_H
-    sci_b_spi_extended_cfg_t spi_cfg = *(sci_b_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
-#else
-    sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
-#endif
-
-    /**< Configure Select Line */
-    rt_pin_write(device->cs_pin, PIN_HIGH);
-
-    /**< config bitrate */
-#ifdef R_SCI_B_SPI_H
-    R_SCI_B_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
-#else
-    R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
-#endif
-
-    /**< init */
-    err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
-    /* handle error */
-    if(err == FSP_ERR_IN_USE) {
-        R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
-        err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
-    }
-    if (RT_EOK != err)
-    {
-        LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
-        return -RT_ERROR;
-    }
-    return RT_EOK;
-}
-
-static rt_ssize_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
-{
-    RT_ASSERT(device != RT_NULL);
-    RT_ASSERT(device->bus != RT_NULL);
-    RT_ASSERT(message != RT_NULL);
-
-    rt_err_t err = RT_EOK;
-
-    if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
-    {
-        if (device->config.mode & RT_SPI_CS_HIGH)
-            rt_pin_write(device->cs_pin, PIN_HIGH);
-        else
-            rt_pin_write(device->cs_pin, PIN_LOW);
-    }
-
-    if (message->length > 0)
-    {
-        if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
-        {
-            /**< receive message */
-            err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
-        }
-        else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
-        {
-            /**< send message */
-            err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
-        }
-        else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
-        {
-            /**< send and receive message */
-            err =  ra_write_read_message(device, message);
-        }
-    }
-
-    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
-    {
-        if (device->config.mode & RT_SPI_CS_HIGH)
-            rt_pin_write(device->cs_pin, PIN_LOW);
-        else
-            rt_pin_write(device->cs_pin, PIN_HIGH);
-    }
-    return err;
-}
-
-static const struct rt_spi_ops ra_spi_ops =
-{
-    .configure = ra_hw_spi_configure,
-    .xfer = ra_spixfer,
-};
-
-int ra_hw_sci_spi_init(void)
-{
-    for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
-    {
-        spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
-
-        /**< register spi bus */
-        rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
-        if (RT_EOK != err)
-        {
-            LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
-            return -RT_ERROR;
-        }
-    }
-
-    if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
-    {
-        LOG_E("SPI transfer event init fail!");
-        return -RT_ERROR;
-    }
-    return RT_EOK;
-}
-INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
-
-/**
-  * Attach the spi device to SPI bus, this function must be used after initialization.
-  */
-rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
-{
-    RT_ASSERT(bus_name != RT_NULL);
-    RT_ASSERT(device_name != RT_NULL);
-
-    rt_err_t result;
-    struct rt_spi_device *spi_device;
-
-    /* attach the device to spi bus*/
-    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
-    RT_ASSERT(spi_device != RT_NULL);
-
-    result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
-    if (result != RT_EOK)
-    {
-        LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
-    }
-
-    LOG_D("%s attach to %s done", device_name, bus_name);
-
-    return result;
-}
-#endif /* RT_USING_SPI */

bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h

@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-08-23     Mr.Tiger     first version
- * 2022-12-7      Vandoul      ADD sci spi
- */
-
-#ifndef __DRV_SCI_SPI_H__
-#define __DRV_SCI_SPI_H__
-
-#include <rtthread.h>
-#include <rtdevice.h>
-#include "hal_data.h"
-#include "board.h"
-#include <rthw.h>
-#include <drv_common.h>
-#include <drv_config.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(R_SCI_SPI_H) || defined(R_SCI_B_SPI_H)
-struct ra_sci_spi_handle
-{
-    const char bus_name[RT_NAME_MAX];
-    const spi_cfg_t               *spi_cfg_t;
-#ifdef R_SCI_B_SPI_H
-    const sci_b_spi_instance_ctrl_t *spi_ctrl_t;
-#else
-    const sci_spi_instance_ctrl_t *spi_ctrl_t;
-#endif
-};
-
-struct ra_sci_spi
-{
-    rt_uint32_t                  cs_pin;
-    struct ra_sci_spi_handle    *ra_spi_handle_t;
-    struct rt_spi_configuration *rt_spi_cfg_t;
-    struct rt_spi_bus            bus;
-};
-#endif
-
-rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
-
-#ifdef __cplusplus
-}
-#endif
-
-/* stm32 spi dirver class */
-
-#endif /*__DRV_SPI_H__ */

bsp/renesas/libraries/HAL_Drivers/drv_spi.c

@@ -13,7 +13,7 @@
 
 #include "drv_spi.h"
 
-#ifdef RT_USING_SPI
+#ifdef BSP_USING_SPI
 
 //#define DRV_DEBUG
 #define DBG_TAG              "drv.spi"
@@ -310,4 +310,4 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
 
     return result;
 }
-#endif /* RT_USING_SPI */
+#endif /* BSP_USING_SPI */

bsp/renesas/ra2l1-cpk/.config

@@ -294,16 +294,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -325,6 +315,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -346,7 +337,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -367,7 +357,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -512,9 +501,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -534,8 +520,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -573,35 +557,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -683,8 +643,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -692,6 +653,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -706,6 +675,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -728,6 +698,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -737,6 +708,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -744,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -752,9 +725,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -769,7 +739,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -779,6 +748,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -854,9 +824,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -864,13 +832,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -915,7 +883,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -954,6 +922,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -976,7 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -984,7 +953,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -997,7 +966,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1023,7 +991,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1040,11 +1007,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1067,6 +1034,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 # CONFIG_SOC_SERIES_R7FA6M3 is not set
 # CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1074,6 +1042,7 @@ CONFIG_SOC_SERIES_R7FA2L1=y
 # CONFIG_SOC_SERIES_R7FA6M5 is not set
 # CONFIG_SOC_SERIES_R7FA4M2 is not set
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1102,13 +1071,15 @@ CONFIG_BSP_USING_UART9=y
 # CONFIG_BSP_UART9_TX_USING_DMA is not set
 CONFIG_BSP_UART9_RX_BUFSIZE=256
 CONFIG_BSP_UART9_TX_BUFSIZE=0
-# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_DAC is not set
 # CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_CAN is not set
 # CONFIG_BSP_USING_LPM is not set
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ra2l1-cpk/.settings/standalone.prefs

@@ -1,21 +1,19 @@
-#Fri Jul 22 15:41:36 CST 2022
+#Sat Apr 13 23:24:56 CST 2024
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=2985489297,ra/board/ra2l1_cpk/board_init.h|383876238,ra/board/ra2l1_cpk/board_leds.h|2918861270,ra/board/ra2l1_cpk/board_leds.c|586415029,ra/board/ra2l1_cpk/board.h|1521504391,ra/board/ra2l1_cpk/board_init.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2425160085,ra/fsp/inc/api/bsp_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2208590403,ra/fsp/inc/instances/r_ioport.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3297195641,ra/fsp/inc/fsp_version.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1728953905,ra/fsp/inc/fsp_features.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=ra/board/ra2l1_cpk/board_init.h|ra/board/ra2l1_cpk/board_leds.h|ra/board/ra2l1_cpk/board_leds.c|ra/board/ra2l1_cpk/board.h|ra/board/ra2l1_cpk/board_init.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3297195641,ra/fsp/inc/fsp_version.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1728953905,ra/fsp/inc/fsp_features.h|2425160085,ra/fsp/inc/api/bsp_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|546480625,ra/fsp/inc/fsp_common_api.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#R7FA2L1AB2DFM\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c
 com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.629312687=false
 com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=

bsp/renesas/ra2l1-cpk/board/Kconfig

@@ -161,36 +161,37 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_I2C
-            bool "Enable I2C BUS"
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
             default n
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C1
+                    bool "Enable Hardware I2C1 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SOFT_I2C
+            bool "Enable software I2C bus"
             select RT_USING_I2C
             select RT_USING_I2C_BITOPS
             select RT_USING_PIN
-            if BSP_USING_I2C
-                config BSP_USING_HW_I2C
-                    bool "Enable Hardware I2C BUS"
-                    default n
-                if BSP_USING_HW_I2C
-                    config BSP_USING_HW_I2C1
-                        bool "Enable Hardware I2C1 BUS"
-                        default n
-                endif
-                if !BSP_USING_HW_I2C
-                    menuconfig BSP_USING_I2C1
-                        bool "Enable I2C1 BUS (software simulation)"
-                        default y
-                        if BSP_USING_I2C1
-                            config BSP_I2C1_SCL_PIN
-                                hex "i2c1 scl pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050C
-                            config BSP_I2C1_SDA_PIN
-                                hex "I2C1 sda pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050B
-                        endif
-                endif
+            default n
+            if BSP_USING_SOFT_I2C
+                config BSP_USING_SOFT_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 Bus (software simulation)"
+                    default n
+                    if BSP_USING_I2C1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050C
+                        config BSP_I2C1_SDA_PIN
+                            hex "i2c1 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050B
+                    endif
             endif
 
         menuconfig BSP_USING_SPI
@@ -305,6 +306,325 @@ menu "Hardware Drivers Config"
                     default n
             endif
 
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
+            default n
+
+
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
+                    default n
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
+                    default n
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
+                    default n
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
+                    default n
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
+                    default n
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
+                    default n
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
+                    default n
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
+                    default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/renesas/ra2l1-cpk/buildinfo.gpdsc

@@ -56,45 +56,56 @@
         <file category="source" name="ra/board/ra2l1_cpk/board_leds.c"/>
         <file category="header" name="ra/board/ra2l1_cpk/board_leds.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
-        <file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
         <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h" path=""/>
@@ -102,9 +113,12 @@
         <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h" path=""/>
-        <file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
+        <file category="other" name="ra/fsp/src/r_dtc/r_dtc.o"/>
         <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
+        <file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
+        <file category="other" name="ra/fsp/src/r_sci_spi/r_sci_spi.o"/>
         <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
+        <file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
         <file category="other" name="ra/SConscript"/>
       </files>
     </component>
@@ -112,13 +126,11 @@
       <files>
         <file category="include" name="ra_cfg/fsp_cfg/"/>
         <file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
-        <file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
         <file category="other" name="ra_cfg/SConscript"/>

bsp/renesas/ra2l1-cpk/configuration.xml

@@ -150,10 +150,6 @@
       <description>SCI UART</description>
       <originalPack>Renesas.RA.3.5.0.pack</originalPack>
     </component>
-    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.5.0">
-      <description>External Interrupt</description>
-      <originalPack>Renesas.RA.3.5.0.pack</originalPack>
-    </component>
   </raComponentSelection>
   <raElcConfiguration/>
   <raIcuConfiguration/>
@@ -192,26 +188,13 @@
       <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority2"/>
       <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority2"/>
     </module>
-    <module id="module.driver.external_irq_on_icu.832378872">
-      <property id="module.driver.external_irq.name" value="g_external_irq3"/>
-      <property id="module.driver.external_irq.channel" value="3"/>
-      <property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
-      <property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
-      <property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
-      <property id="module.driver.external_irq.p_callback" value="irq_callback"/>
-      <property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority2"/>
-    </module>
     <context id="_hal.0">
       <stack module="module.driver.ioport_on_ioport.0"/>
       <stack module="module.driver.uart_on_sci_uart.629312687"/>
-      <stack module="module.driver.external_irq_on_icu.832378872"/>
     </context>
     <config id="config.driver.ioport">
       <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
     </config>
-    <config id="config.driver.icu">
-      <property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
-    </config>
     <config id="config.driver.sci_uart">
       <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
       <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>

bsp/renesas/ra2l1-cpk/project.uvprojx

@@ -334,9 +334,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations  -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __RTTHREAD__</Define>
               <Undefine />
-              <IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m23;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;ra_cfg\fsp_cfg\bsp;.;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;board\ports;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;ra_cfg\fsp_cfg;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;board;..\..\..\components\libc\posix\io\epoll;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh</IncludePath>
+              <IncludePath>ra_cfg\fsp_cfg\bsp;..\..\..\components\libc\posix\ipc;board;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m23;.;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;board\ports;..\..\..\components\drivers\include;..\..\..\components\drivers\include;ra_cfg\fsp_cfg;..\..\..\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\finsh;..\libraries\HAL_Drivers</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -476,6 +476,25 @@
               </FileOption>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>condvar.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_IPC_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath> </IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
           <Files>
             <File>
               <FileName>dataqueue.c</FileName>
@@ -700,23 +719,23 @@
           </Files>
           <Files>
             <File>
-              <FileName>dfs_fs.c</FileName>
+              <FileName>dfs_file.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_fs.c</FilePath>
+              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_file.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs.c</FileName>
+              <FileName>dfs_fs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs.c</FilePath>
+              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_fs.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_file.c</FileName>
+              <FileName>dfs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_file.c</FilePath>
+              <FilePath>..\..\..\components\dfs\dfs_v1\src\dfs.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -724,9 +743,9 @@
           <GroupName>Finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -738,23 +757,23 @@
           </Files>
           <Files>
             <File>
-              <FileName>msh_parse.c</FileName>
+              <FileName>msh_file.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_file.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h

@@ -1,177 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup EXTERNAL_IRQ_API External IRQ Interface
- * @brief Interface for detecting external interrupts.
- *
- * @section EXTERNAL_IRQ_API_Summary Summary
- * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
- * external IRQ pin.
- *
- * The  External IRQ Interface can be implemented by:
- * - @ref ICU
- *
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_EXTERNAL_IRQ_API_H
-#define R_EXTERNAL_IRQ_API_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/**********************************************************************************************************************
- * Macro definitions
- *********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- *********************************************************************************************************************/
-
-/** Callback function parameter data */
-typedef struct st_external_irq_callback_args
-{
-    /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
-    void const * p_context;
-    uint32_t     channel;              ///< The physical hardware channel that caused the interrupt.
-} external_irq_callback_args_t;
-
-/** Condition that will trigger an interrupt when detected. */
-typedef enum e_external_irq_trigger
-{
-    EXTERNAL_IRQ_TRIG_FALLING   = 0,   ///< Falling edge trigger
-    EXTERNAL_IRQ_TRIG_RISING    = 1,   ///< Rising edge trigger
-    EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2,   ///< Both edges trigger
-    EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3,   ///< Low level trigger
-} external_irq_trigger_t;
-
-/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
- * conditions that are shorter than 3 periods of the filter clock.
- */
-typedef enum e_external_irq_pclk_div
-{
-    EXTERNAL_IRQ_PCLK_DIV_BY_1  = 0,   ///< Filter using PCLK divided by 1
-    EXTERNAL_IRQ_PCLK_DIV_BY_8  = 1,   ///< Filter using PCLK divided by 8
-    EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2,   ///< Filter using PCLK divided by 32
-    EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3,   ///< Filter using PCLK divided by 64
-} external_irq_pclk_div_t;
-
-/** User configuration structure, used in open function */
-typedef struct st_external_irq_cfg
-{
-    uint8_t                 channel;   ///< Hardware channel used.
-    uint8_t                 ipl;       ///< Interrupt priority
-    IRQn_Type               irq;       ///< NVIC interrupt number assigned to this instance
-    external_irq_trigger_t  trigger;   ///< Trigger setting.
-    external_irq_pclk_div_t pclk_div;  ///< Digital filter clock divisor setting.
-    bool filter_enable;                ///< Digital filter enable/disable setting.
-
-    /** Callback provided external input trigger occurs. */
-    void (* p_callback)(external_irq_callback_args_t * p_args);
-
-    /** Placeholder for user data.  Passed to the user callback in @ref external_irq_callback_args_t. */
-    void const * p_context;
-    void const * p_extend;             ///< External IRQ hardware dependent configuration.
-} external_irq_cfg_t;
-
-/** External IRQ control block.  Allocate an instance specific control block to pass into the external IRQ API calls.
- * @par Implemented as
- * - icu_instance_ctrl_t
- */
-typedef void external_irq_ctrl_t;
-
-/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
-typedef struct st_external_irq_api
-{
-    /** Initial configuration.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqOpen()
-     *
-     * @param[out]  p_ctrl  Pointer to control block. Must be declared by user. Value set here.
-     * @param[in]   p_cfg   Pointer to configuration structure. All elements of the structure must be set by user.
-     */
-    fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);
-
-    /** Enable callback when an external trigger condition occurs.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqEnable()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);
-
-    /** Disable callback when external trigger condition occurs.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqDisable()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);
-
-    /**
-     * Specify callback function and optional context pointer and working memory pointer.
-     * @par Implemented as
-     * - R_ICU_ExternalIrqCallbackSet()
-     *
-     * @param[in]   p_ctrl                   Pointer to the Extneral IRQ control block.
-     * @param[in]   p_callback               Callback function
-     * @param[in]   p_context                Pointer to send to callback function
-     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
-     *                                       Callback arguments allocated here are only valid during the callback.
-     */
-    fsp_err_t (* callbackSet)(external_irq_ctrl_t * const          p_api_ctrl,
-                              void (                             * p_callback)(external_irq_callback_args_t *),
-                              void const * const                   p_context,
-                              external_irq_callback_args_t * const p_callback_memory);
-
-    /** Allow driver to be reconfigured. May reduce power consumption.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqClose()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
-} external_irq_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_external_irq_instance
-{
-    external_irq_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
-    external_irq_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
-    external_irq_api_t const * p_api;  ///< Pointer to the API structure for this instance
-} external_irq_instance_t;
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-/*******************************************************************************************************************//**
- * @} (end defgroup EXTERNAL_IRQ_API)
- **********************************************************************************************************************/
-
-#endif

bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h

@@ -1,95 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup ICU
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_ICU_H
-#define R_ICU_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "bsp_api.h"
-#include "r_external_irq_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- *********************************************************************************************************************/
-
-/** ICU private control block. DO NOT MODIFY.  Initialization occurs when R_ICU_ExternalIrqOpen is called. */
-typedef struct st_icu_instance_ctrl
-{
-    uint32_t  open;                                             ///< Used to determine if channel control block is in use
-    IRQn_Type irq;                                              ///< NVIC interrupt number
-    uint8_t   channel;                                          ///< Channel
-
-#if BSP_TZ_SECURE_BUILD
-    external_irq_callback_args_t * p_callback_memory;           // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
-#endif
-    void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin.
-
-    /** Placeholder for user data.  Passed to the user callback in ::external_irq_callback_args_t. */
-    void const * p_context;
-} icu_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const external_irq_api_t g_external_irq_on_icu;
-
-/** @endcond */
-
-/***********************************************************************************************************************
- * Public APIs
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg);
-
-fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl);
-
-fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl);
-
-fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const          p_api_ctrl,
-                                       void (                             * p_callback)(external_irq_callback_args_t *),
-                                       void const * const                   p_context,
-                                       external_irq_callback_args_t * const p_callback_memory);
-
-fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl);
-
-/*******************************************************************************************************************//**
- * @} (end defgroup ICU)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif                                 // R_ICU_H

bsp/renesas/ra2l1-cpk/ra/fsp/src/r_icu/r_icu.c

@@ -1,370 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_icu.h"
-#include "r_icu_cfg.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** "ICU" in ASCII, used to determine if channel is open. */
-#define ICU_OPEN              (0x00494355U)
-
-#define ICU_IRQMD_OFFSET      (0)
-#define ICU_FCLKSEL_OFFSET    (4)
-#define ICU_FLTEN_OFFSET      (7)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private function prototypes
- **********************************************************************************************************************/
-void r_icu_isr(void);
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Global Variables
- **********************************************************************************************************************/
-
-/* ICU implementation of External IRQ API. */
-const external_irq_api_t g_external_irq_on_icu =
-{
-    .open        = R_ICU_ExternalIrqOpen,
-    .enable      = R_ICU_ExternalIrqEnable,
-    .disable     = R_ICU_ExternalIrqDisable,
-    .callbackSet = R_ICU_ExternalIrqCallbackSet,
-    .close       = R_ICU_ExternalIrqClose,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup ICU
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configure an IRQ input pin for use with the external interrupt interface.  Implements @ref external_irq_api_t::open.
- *
- * The Open function is responsible for preparing an external IRQ pin for operation.
- *
- * @retval FSP_SUCCESS                    Open successful.
- * @retval FSP_ERR_ASSERTION              One of the following is invalid:
- *                                          - p_ctrl or p_cfg is NULL
- * @retval FSP_ERR_ALREADY_OPEN           The channel specified has already been opened. No configurations were changed.
- *                                        Call the associated Close function to reconfigure the channel.
- * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in
- *                                        r_bsp_cfg.h.
- * @retval FSP_ERR_INVALID_ARGUMENT       p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to
- *                                        use callback function.
- *
- * @note This function is reentrant for different channels.  It is not reentrant for the same channel.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
-
-    /* Callback must be used with a valid interrupt priority otherwise it will never be called. */
-    if (p_cfg->p_callback)
-    {
-        FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT);
-    }
-#endif
-
-    p_ctrl->irq = p_cfg->irq;
-
-    /* IELSR Must be zero when modifying the IRQCR bits.
-     * (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */
-    uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq];
-    R_ICU->IELSR[p_ctrl->irq] = 0;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* If this is a secure build, the callback provided in p_cfg must be secure. */
-    p_ctrl->p_callback_memory = NULL;
-#endif
-
-    /* Initialize control block. */
-    p_ctrl->p_callback = p_cfg->p_callback;
-    p_ctrl->p_context  = p_cfg->p_context;
-    p_ctrl->channel    = p_cfg->channel;
-
-    /* Disable digital filter */
-    R_ICU->IRQCR[p_ctrl->channel] = 0U;
-
-    /* Set the digital filter divider. */
-    uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET);
-
-    /* Enable/Disable digital filter. */
-    irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET);
-
-    /* Set the IRQ trigger. */
-    irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET);
-
-    /* Write IRQCR */
-    R_ICU->IRQCR[p_ctrl->channel] = irqcr;
-
-    /* Restore IELSR. */
-    R_ICU->IELSR[p_ctrl->irq] = ielsr;
-
-    /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases
-     * where the external IRQ driver is used to generate ELC events only (without CPU interrupts).
-     * In such cases we will not set the IRQ priority but will continue with the processing.
-     */
-    if (p_ctrl->irq >= 0)
-    {
-        R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl);
-    }
-
-    /* Mark the control block as open */
-    p_ctrl->open = ICU_OPEN;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable.
- *
- * @retval FSP_SUCCESS                 Interrupt Enabled successfully.
- * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
- * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
- * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
-#endif
-
-    /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */
-    R_BSP_IrqEnable(p_ctrl->irq);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable.
- *
- * @retval FSP_SUCCESS                 Interrupt disabled successfully.
- * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
- * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
- * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
-#endif
-
-    /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
-    R_BSP_IrqDisable(p_ctrl->irq);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback and has option of providing memory for callback structure.
- * Implements external_irq_api_t::callbackSet
- *
- * @retval  FSP_SUCCESS                  Callback updated successfully.
- * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
- * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
- * @retval  FSP_ERR_NO_CALLBACK_MEMORY   p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl,
-                                        void (                    * p_callback)(
-                                            external_irq_callback_args_t *),
-                                        void const * const                   p_context,
-                                        external_irq_callback_args_t * const p_callback_memory)
-{
-    icu_instance_ctrl_t * p_ctrl = p_api_ctrl;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* cmse_check_address_range returns NULL if p_callback is located in secure memory */
-    bool callback_is_secure =
-        (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-#else
-    FSP_PARAMETER_NOT_USED(p_callback_memory);
-#endif
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_callback);
-
- #if BSP_TZ_SECURE_BUILD
-
-    /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
-    external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
-                                                                                               CMSE_AU_NONSECURE);
-    FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-#endif
-
-#if BSP_TZ_SECURE_BUILD
-    p_ctrl->p_callback_memory = p_callback_memory;
-    p_ctrl->p_callback        = callback_is_secure ? p_callback :
-                                (void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
-    p_ctrl->p_callback = p_callback;
-#endif
-    p_ctrl->p_context = p_context;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Close the external interrupt channel. Implements @ref external_irq_api_t::close.
- *
- * @retval     FSP_SUCCESS          Successfully closed.
- * @retval     FSP_ERR_ASSERTION    The parameter p_ctrl is NULL.
- * @retval     FSP_ERR_NOT_OPEN     The channel is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Cleanup. Disable interrupt */
-    if (p_ctrl->irq >= 0)
-    {
-        /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
-        R_BSP_IrqDisable(p_ctrl->irq);
-        R_FSP_IsrContextSet(p_ctrl->irq, NULL);
-    }
-
-    p_ctrl->open = 0U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup ICU)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * ICU External Interrupt ISR.
- **********************************************************************************************************************/
-void r_icu_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE
-
-    IRQn_Type             irq    = R_FSP_CurrentIrqGet();
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    bool level_irq = false;
-    if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD)
-    {
-        level_irq = true;
-    }
-    else
-    {
-        /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active
-         * it will not be missed. */
-        R_BSP_IrqStatusClear(irq);
-    }
-
-    if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback))
-    {
-#if BSP_TZ_SECURE_BUILD
-
-        /* p_callback can point to a secure function or a non-secure function. */
-        external_irq_callback_args_t args;
-        if (!cmse_is_nsfptr(p_ctrl->p_callback))
-        {
-            /* If p_callback is secure, then the project does not need to change security state. */
-            args.channel   = p_ctrl->channel;
-            args.p_context = p_ctrl->p_context;
-            p_ctrl->p_callback(&args);
-        }
-        else
-        {
-            /* Save current state of p_callback_args so that it can be shared between interrupts. */
-            args = *p_ctrl->p_callback_memory;
-
-            /* Set the callback args passed to the Non-secure calback. */
-            p_ctrl->p_callback_memory->channel   = p_ctrl->channel;
-            p_ctrl->p_callback_memory->p_context = p_ctrl->p_context;
-
-            /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
-            icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback);
-            p_callback(p_ctrl->p_callback_memory);
-
-            /* Restore the state of p_callback_args. */
-            *p_ctrl->p_callback_memory = args;
-        }
-
-#else
-
-        /* Set data to identify callback to user, then call user callback. */
-        external_irq_callback_args_t args;
-        args.channel   = p_ctrl->channel;
-        args.p_context = p_ctrl->p_context;
-        p_ctrl->p_callback(&args);
-#endif
-    }
-
-    if (level_irq)
-    {
-        /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not
-         * be called again. */
-        R_BSP_IrqStatusClear(irq);
-    }
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE
-}

bsp/renesas/ra2l1-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h

@@ -1,5 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_ICU_CFG_H_
-#define R_ICU_CFG_H_
-#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#endif /* R_ICU_CFG_H_ */

bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c

@@ -1,34 +1,5 @@
 /* generated HAL source file - do not edit */
 #include "hal_data.h"
-icu_instance_ctrl_t g_external_irq3_ctrl;
-const external_irq_cfg_t g_external_irq3_cfg =
-{
-    .channel             = 3,
-    .trigger             = EXTERNAL_IRQ_TRIG_RISING,
-    .filter_enable       = false,
-    .pclk_div            = EXTERNAL_IRQ_PCLK_DIV_BY_64,
-    .p_callback          = irq_callback,
-    /** If NULL then do not add & */
-#if defined(NULL)
-    .p_context           = NULL,
-#else
-    .p_context           = &NULL,
-#endif
-    .p_extend            = NULL,
-    .ipl                 = (2),
-#if defined(VECTOR_NUMBER_ICU_IRQ3)
-    .irq                 = VECTOR_NUMBER_ICU_IRQ3,
-#else
-    .irq                 = FSP_INVALID_VECTOR,
-#endif
-};
-/* Instance structure to use this module. */
-const external_irq_instance_t g_external_irq3 =
-{
-    .p_ctrl        = &g_external_irq3_ctrl,
-    .p_cfg         = &g_external_irq3_cfg,
-    .p_api         = &g_external_irq_on_icu
-};
 sci_uart_instance_ctrl_t     g_uart9_ctrl;
 
             baud_setting_t               g_uart9_baud_setting =

bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h

@@ -4,21 +4,9 @@
 #include <stdint.h>
 #include "bsp_api.h"
 #include "common_data.h"
-#include "r_icu.h"
-#include "r_external_irq_api.h"
 #include "r_sci_uart.h"
             #include "r_uart_api.h"
 FSP_HEADER
-/** External IRQ on ICU Instance. */
-extern const external_irq_instance_t g_external_irq3;
-
-/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
-extern icu_instance_ctrl_t g_external_irq3_ctrl;
-extern const external_irq_cfg_t g_external_irq3_cfg;
-
-#ifndef irq_callback
-void irq_callback(external_irq_callback_args_t * p_args);
-#endif
 /** UART on SCI Instance. */
             extern const uart_instance_t      g_uart9;
 

bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c

@@ -4,15 +4,13 @@
         #if VECTOR_DATA_IRQ_COUNT > 0
         BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
         {
-                        [3] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
-            [4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
+                        [4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
             [5] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
             [6] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
             [7] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
         };
         const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
         {
-            [3] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
             [4] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
             [5] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
             [6] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */

bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h

@@ -3,18 +3,15 @@
         #define VECTOR_DATA_H
                 /* Number of interrupts allocated */
         #ifndef VECTOR_DATA_IRQ_COUNT
-        #define VECTOR_DATA_IRQ_COUNT    (5)
+        #define VECTOR_DATA_IRQ_COUNT    (4)
         #endif
         /* ISR prototypes */
-        void r_icu_isr(void);
         void sci_uart_rxi_isr(void);
         void sci_uart_txi_isr(void);
         void sci_uart_tei_isr(void);
         void sci_uart_eri_isr(void);
 
         /* Vector table allocations */
-        #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */
-        #define ICU_IRQ3_IRQn          ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */
         #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
         #define SCI9_RXI_IRQn          ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
         #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 5) /* SCI9 TXI (Transmit data empty) */

bsp/renesas/ra2l1-cpk/rtconfig.h

@@ -145,12 +145,6 @@
 /* CYW43012 WiFi */
 
 
-/* BL808 WiFi */
-
-
-/* CYW43439 WiFi */
-
-
 /* IoT Cloud */
 
 
@@ -192,20 +186,15 @@
 
 /* peripheral libraries and drivers */
 
-/* HAL & SDK Drivers */
-
-/* STM32 HAL & SDK Drivers */
-
-
-/* Kendryte SDK */
-
-
 /* sensors drivers */
 
 
 /* touch drivers */
 
 
+/* Kendryte SDK */
+
+
 /* AI packages */
 
 

bsp/renesas/ra4m2-eco/.config

@@ -160,13 +160,7 @@ CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-CONFIG_RT_USING_SPI=y
-# CONFIG_RT_USING_SPI_BITOPS is not set
-# CONFIG_RT_USING_QSPI is not set
-CONFIG_RT_USING_SPI_MSD=y
-# CONFIG_RT_USING_SFUD is not set
-# CONFIG_RT_USING_ENC28J60 is not set
-# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -299,16 +293,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -330,6 +314,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -351,7 +336,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -372,7 +356,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -519,9 +502,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -541,8 +521,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -580,35 +558,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -690,8 +644,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -699,6 +654,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -713,6 +676,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -735,6 +699,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -744,6 +709,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -751,6 +717,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -759,9 +726,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -776,7 +740,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -786,6 +749,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -861,9 +825,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -871,13 +833,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -922,7 +884,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -961,6 +923,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -983,7 +946,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -991,7 +954,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -1004,7 +967,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1030,7 +992,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1047,11 +1008,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1074,6 +1035,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 # CONFIG_SOC_SERIES_R7FA6M3 is not set
 # CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1081,6 +1043,7 @@ CONFIG_SOC_FAMILY_RENESAS=y
 # CONFIG_SOC_SERIES_R7FA6M5 is not set
 CONFIG_SOC_SERIES_R7FA4M2=y
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1090,6 +1053,7 @@ CONFIG_SOC_R7FA4M2AD=y
 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_FS is not set
 
 #
 # On-chip Peripheral Drivers
@@ -1114,13 +1078,7 @@ CONFIG_BSP_UART4_RX_BUFSIZE=256
 CONFIG_BSP_UART4_TX_BUFSIZE=0
 # CONFIG_BSP_USING_UART9 is not set
 # CONFIG_BSP_USING_SPI is not set
-CONFIG_BSP_USING_SCI_SPI=y
-# CONFIG_BSP_USING_SCI_SPI0 is not set
-# CONFIG_BSP_USING_SCI_SPI1 is not set
-# CONFIG_BSP_USING_SCI_SPI2 is not set
-# CONFIG_BSP_USING_SCI_SPI3 is not set
-# CONFIG_BSP_USING_SCI_SPI4 is not set
-CONFIG_BSP_USING_SCI_SPI9=y
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ra4m2-eco/.secure_azone

@@ -22,7 +22,6 @@
         </peripheral>
         <peripheral name="SCI0" group="SCI" security=""/>
         <peripheral name="SCI4" group="SCI" security=""/>
-        <peripheral name="SCI9" group="SCI" security=""/>
         <peripheral name="ICU">
             <slot name="IRQ0" secure="false"/>
             <slot name="IRQ1" secure="false"/>
@@ -32,10 +31,6 @@
             <slot name="IRQ5" secure="false"/>
             <slot name="IRQ6" secure="false"/>
             <slot name="IRQ7" secure="false"/>
-            <slot name="IRQ8" secure="false"/>
-            <slot name="IRQ9" secure="false"/>
-            <slot name="IRQ10" secure="false"/>
-            <slot name="IRQ11" secure="false"/>
         </peripheral>
     </partition>
 </azone>

bsp/renesas/ra4m2-eco/.secure_xml

@@ -9,7 +9,7 @@
     <option key="#DeviceCommand#" value="R7FA4M2AD"/>
     <option key="#RTOS#" value="_none"/>
     <option key="#pinconfiguration#" value="R7FA4M2AD3CFP.pincfg"/>
-    <option key="#FSPVersion#" value="4.1.0"/>
+    <option key="#FSPVersion#" value="4.2.0"/>
     <option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
   </generalSettings>
   <raClockConfiguration>

bsp/renesas/ra4m2-eco/.settings/standalone.prefs

@@ -1,28 +1,23 @@
-#Wed Dec 07 23:22:04 CST 2022
-com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/all=3347489174,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/all=500387124,ra/fsp/src/r_ioport/r_ioport.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|2490905981,ra/fsp/inc/instances/r_ioport.h
-com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=true
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/all=3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/all=545907899,ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h|2766481316,ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h|1942810345,ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_sci_spi.342272802=false
+#Mon Apr 15 16:00:07 CST 2024
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.788093718=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/all=2970687511,ra/fsp/inc/api/r_transfer_api.h|428353588,ra/fsp/inc/instances/r_dtc.h|1071048478,ra/fsp/src/r_dtc/r_dtc.c
 com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/all=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/all=3958601320,ra/fsp/inc/instances/r_sci_uart.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|134969800,ra/fsp/inc/api/r_uart_api.h|2640391634,ra/fsp/src/r_sci_uart/r_sci_uart.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.2.0/all=3710703039,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.2.0/all=2490905981,ra/fsp/inc/instances/r_ioport.h|500387124,ra/fsp/src/r_ioport/r_ioport.c|3837163319,ra/fsp/inc/api/r_ioport_api.h
 com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/all=2999473418,ra/fsp/src/r_sci_spi/r_sci_spi.c|2970687511,ra/fsp/inc/api/r_transfer_api.h|2516469150,ra/fsp/inc/api/r_spi_api.h|57267461,ra/fsp/inc/instances/r_sci_spi.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/all=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/all=2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|2222043441,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c|1844682318,ra/fsp/src/bsp/mcu/all/bsp_io.h|502753616,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2635614327,ra/fsp/src/bsp/mcu/all/bsp_security.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|1799272679,ra/fsp/inc/fsp_features.h|805765460,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2015535075,ra/fsp/inc/fsp_common_api.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2854226690,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|29339077,ra/fsp/inc/fsp_version.h|547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|604332916,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2074918554,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1303542530,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|571584658,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1218854983,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3954882015,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|715820739,ra/fsp/inc/api/bsp_api.h|539993079,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1374997543,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3748852695,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2294599662,ra/fsp/src/bsp/mcu/all/bsp_common.h|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2490905981,ra/fsp/inc/instances/r_ioport.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.2.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.2.0/all=134969800,ra/fsp/inc/api/r_uart_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|2640391634,ra/fsp/src/r_sci_uart/r_sci_uart.c|3958601320,ra/fsp/inc/instances/r_sci_uart.h
+com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=true
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.2.0/all=1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.2.0/all=547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1234378052,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|816208395,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|502753616,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1623877800,ra/fsp/src/bsp/mcu/all/bsp_security.c|2973649161,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|2490905981,ra/fsp/inc/instances/r_ioport.h|2294599662,ra/fsp/src/bsp/mcu/all/bsp_common.h|1303542530,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2854226690,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|76443894,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|539993079,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1799272679,ra/fsp/inc/fsp_features.h|3837163319,ra/fsp/inc/api/r_ioport_api.h|270846514,ra/fsp/inc/fsp_version.h|1218854983,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1844682318,ra/fsp/src/bsp/mcu/all/bsp_io.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|604332916,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c|715820739,ra/fsp/inc/api/bsp_api.h|2222043441,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2795027356,ra/fsp/inc/fsp_common_api.h|805765460,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3748852695,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.2.0/all=1942810345,ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h|1974362915,ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h|2766481316,ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1802976382=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.2.0/all=

bsp/renesas/ra4m2-eco/board/Kconfig

@@ -9,6 +9,20 @@ menu "Hardware Drivers Config"
 
     menu "Onboard Peripheral Drivers"
 
+        menuconfig BSP_USING_FS
+            bool "Enable filesystem"
+            default n
+            if BSP_USING_FS
+                config BSP_USING_SPICARD_FS
+                    bool "Enable SPI FLASH filesystem"
+                    select BSP_USING_SCI
+                    select BSP_USING_SCI9
+                    select BSP_USING_SCI9_SPI
+                    select RT_USING_SPI_MSD
+                    select RT_USING_DFS_ELMFAT
+                    default n
+            endif
+
     endmenu
 
     menu "On-chip Peripheral Drivers"
@@ -185,46 +199,358 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-    menuconfig BSP_USING_SPI
-            bool "Enable SPI"
+        menuconfig BSP_USING_SPI
+                bool "Enable SPI"
+                default n
+                select RT_USING_SPI
+                if BSP_USING_SPI
+                    config BSP_USING_SPI0
+                        bool "Enable SPI0 BUS"
+                        default n
+
+                    config BSP_USING_SPI1
+                        bool "Enable SPI1 BUS"
+                        default n
+                endif
+
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
             default n
-            select RT_USING_SPI
-            if BSP_USING_SPI
-                config BSP_USING_SPI0
-                    bool "Enable SPI0 BUS"
-                    default n
+            config BSP_USING_SCIn_SPI
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SPI
+                default n
 
-                config BSP_USING_SPI1
-                    bool "Enable SPI1 BUS"
+            config BSP_USING_SCIn_I2C
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_SCIn_UART
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SERIAL
+                select RT_USING_SERIAL_V2
+                default n
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
+                    default n
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
+                    default n
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
+                    default n
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
                     default n
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
+                    default n
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
+                    default n
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
+                    default n
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
+                    default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
             endif
+        endmenu
 
-    menuconfig BSP_USING_SCI_SPI
-        bool "Enable SCI SPI BUS"
-        default n
-        select RT_USING_SPI
-        if BSP_USING_SCI_SPI 
-            config BSP_USING_SCI_SPI0
-                bool "Enable SCI SPI0 BUS"
-                default n
-            config BSP_USING_SCI_SPI1
-                bool "Enable SCI SPI1 BUS"
-                default n
-            config BSP_USING_SCI_SPI2
-                bool "Enable SCI SPI2 BUS"
-                default n
-            config BSP_USING_SCI_SPI3
-                bool "Enable SCI SPI3 BUS"
-                default n
-            config BSP_USING_SCI_SPI4
-                bool "Enable SCI SPI4 BUS"
-                default n
-            config BSP_USING_SCI_SPI9
-                bool "Enable SCI SPI9 BUS"
-                default n
-        endif
-    endmenu
     menu "Board extended module Drivers"
 
     endmenu
+
 endmenu

bsp/renesas/ra4m2-eco/board/ports/mnt.c

@@ -0,0 +1,38 @@
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef BSP_USING_FS
+
+#include <dfs_fs.h>
+
+#include <spi_msd.h>
+#include "drv_sci.h"
+
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+void sd_mount(void)
+{
+    uint32_t cs_pin = BSP_IO_PORT_06_PIN_03;
+    rt_hw_sci_spi_device_attach("sci9s", "scpi90", cs_pin);
+    msd_init("sd0", "scpi90");
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
+    }
+    else
+    {
+        LOG_W("sd card mount to '/' failed!");
+    }
+    return 0;
+}
+
+int mount_init(void)
+{
+    sd_mount();
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(mount_init);
+
+#endif  /* BSP_USING_FS */

bsp/renesas/ra4m2-eco/buildinfo.gpdsc

@@ -11,7 +11,7 @@
     <generator id="Renesas RA Smart Configurator">
       <project_files>
         <file category="include" name="src/"/>
-        <file category="source" name="src/hal_entry.cpp"/>
+        <file category="source" name="src/hal_entry.c"/>
       </project_files>
     </generator>
   </generators>
@@ -55,53 +55,65 @@
         <file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
         <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
-        <file category="header" name="ra/fsp/inc/api/r_spi_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_dtc.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_sci_spi.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
         <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
         <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
         <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h" path=""/>
-        <file category="source" name="ra/fsp/src/r_dtc/r_dtc.c"/>
+        <file category="other" name="ra/fsp/src/r_dtc/r_dtc.o"/>
         <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
-        <file category="source" name="ra/fsp/src/r_sci_spi/r_sci_spi.c"/>
+        <file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
+        <file category="other" name="ra/fsp/src/r_sci_spi/r_sci_spi.o"/>
         <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
+        <file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
         <file category="other" name="ra/SConscript"/>
       </files>
     </component>
@@ -115,9 +127,7 @@
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_dtc_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_sci_spi_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
         <file category="other" name="ra_cfg/SConscript"/>
       </files>

bsp/renesas/ra4m2-eco/configuration.xml

@@ -9,7 +9,7 @@
     <option key="#DeviceCommand#" value="R7FA4M2AD"/>
     <option key="#RTOS#" value="_none"/>
     <option key="#pinconfiguration#" value="R7FA4M2AD3CFP.pincfg"/>
-    <option key="#FSPVersion#" value="4.1.0"/>
+    <option key="#FSPVersion#" value="4.2.0"/>
     <option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
   </generalSettings>
   <raBspConfiguration>
@@ -123,45 +123,37 @@
     <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
   </raClockConfiguration>
   <raComponentSelection>
-    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="4.1.0">
-      <description>Board Support Package Common Files</description>
-      <originalPack>Renesas.RA.4.1.0.pack</originalPack>
-    </component>
-    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="4.1.0">
-      <description>I/O Port</description>
-      <originalPack>Renesas.RA.4.1.0.pack</originalPack>
-    </component>
-    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.4.1.0">
-      <description>Arm CMSIS Version 5 - Core (M)</description>
-      <originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.4.1.0.pack</originalPack>
-    </component>
-    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="R7FA4M2AD3CFP" vendor="Renesas" version="4.1.0">
+    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="R7FA4M2AD3CFP" vendor="Renesas" version="4.2.0">
       <description>Board support package for R7FA4M2AD3CFP</description>
-      <originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
+      <originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="" vendor="Renesas" version="4.1.0">
+    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="" vendor="Renesas" version="4.2.0">
       <description>Board support package for RA4M2</description>
-      <originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
+      <originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="fsp" variant="" vendor="Renesas" version="4.1.0">
+    <component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="fsp" variant="" vendor="Renesas" version="4.2.0">
       <description>Board support package for RA4M2 - FSP Data</description>
-      <originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
+      <originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.4.2.0">
+      <description>Arm CMSIS Version 5 - Core (M)</description>
+      <originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="4.1.0">
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="4.2.0">
       <description>Custom Board Support Files</description>
-      <originalPack>Renesas.RA_board_custom.4.1.0.pack</originalPack>
+      <originalPack>Renesas.RA_board_custom.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="4.1.0">
-      <description>SCI UART</description>
-      <originalPack>Renesas.RA.4.1.0.pack</originalPack>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="4.2.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_dtc" variant="" vendor="Renesas" version="4.1.0">
-      <description>Data Transfer Controller</description>
-      <originalPack>Renesas.RA.4.1.0.pack</originalPack>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="4.2.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.4.2.0.pack</originalPack>
     </component>
-    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_spi" variant="" vendor="Renesas" version="4.1.0">
-      <description>Serial Peripheral Interface on Serial Communications Interface</description>
-      <originalPack>Renesas.RA.4.1.0.pack</originalPack>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="4.2.0">
+      <description>SCI UART</description>
+      <originalPack>Renesas.RA.4.2.0.pack</originalPack>
     </component>
   </raComponentSelection>
   <raElcConfiguration/>
@@ -227,70 +219,14 @@
       <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
       <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
     </module>
-    <module id="module.driver.spi_on_sci_spi.342272802">
-      <property id="module.driver.spi.name" value="g_sci_spi9"/>
-      <property id="module.driver.spi.channel" value="9"/>
-      <property id="module.driver.spi.operating_mode" value="module.driver.spi.operating_mode.mode_master"/>
-      <property id="module.driver.spi.clk_phase" value="module.driver.spi.clk_phase.clk_phase_edge_odd"/>
-      <property id="module.driver.spi.clk_polarity" value="module.driver.spi.clk_polarity.clk_polarity_low"/>
-      <property id="module.driver.spi.mode_fault" value="module.driver.spi.mode_fault.mode_fault_error_disable"/>
-      <property id="module.driver.spi.bit_order" value="module.driver.spi.bit_order.bit_order_msb_first"/>
-      <property id="module.driver.spi.p_callback" value="sci_spi9_callback"/>
-      <property id="module.driver.spi.rxi_ipl" value="board.icu.common.irq.priority12"/>
-      <property id="module.driver.spi.txi_ipl" value="board.icu.common.irq.priority12"/>
-      <property id="module.driver.spi.tei_ipl" value="board.icu.common.irq.priority12"/>
-      <property id="module.driver.spi.eri_ipl" value="board.icu.common.irq.priority12"/>
-      <property id="module.driver.spi.bitrate" value="8000000"/>
-      <property id="module.driver.spi.bitrate_modulation" value="module.driver.spi.bitrate_modulation.disabled"/>
-    </module>
-    <module id="module.driver.transfer_on_dtc.351428579">
-      <property id="module.driver.transfer.name" value="g_transfer0"/>
-      <property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
-      <property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
-      <property id="module.driver.transfer.dest_addr_mode" value="module.driver.transfer.dest_addr_mode.addr_mode_fixed"/>
-      <property id="module.driver.transfer.src_addr_mode" value="module.driver.transfer.src_addr_mode.addr_mode_fixed"/>
-      <property id="module.driver.transfer.repeat_area" value="module.driver.transfer.repeat_area.repeat_area_source"/>
-      <property id="module.driver.transfer.p_dest" value="NULL"/>
-      <property id="module.driver.transfer.p_src" value="NULL"/>
-      <property id="module.driver.transfer.interrupt" value="module.driver.transfer.interrupt.interrupt_end"/>
-      <property id="module.driver.transfer.length" value="0"/>
-      <property id="module.driver.transfer.num_blocks" value="0"/>
-      <property id="module.driver.transfer.activation_source" value="_disabled"/>
-    </module>
-    <module id="module.driver.transfer_on_dtc.2037472890">
-      <property id="module.driver.transfer.name" value="g_transfer1"/>
-      <property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
-      <property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
-      <property id="module.driver.transfer.dest_addr_mode" value="module.driver.transfer.dest_addr_mode.addr_mode_fixed"/>
-      <property id="module.driver.transfer.src_addr_mode" value="module.driver.transfer.src_addr_mode.addr_mode_fixed"/>
-      <property id="module.driver.transfer.repeat_area" value="module.driver.transfer.repeat_area.repeat_area_source"/>
-      <property id="module.driver.transfer.p_dest" value="NULL"/>
-      <property id="module.driver.transfer.p_src" value="NULL"/>
-      <property id="module.driver.transfer.interrupt" value="module.driver.transfer.interrupt.interrupt_end"/>
-      <property id="module.driver.transfer.length" value="0"/>
-      <property id="module.driver.transfer.num_blocks" value="0"/>
-      <property id="module.driver.transfer.activation_source" value="_disabled"/>
-    </module>
     <context id="_hal.0">
       <stack module="module.driver.ioport_on_ioport.0"/>
       <stack module="module.driver.uart_on_sci_uart.1802976382"/>
       <stack module="module.driver.uart_on_sci_uart.788093718"/>
-      <stack module="module.driver.spi_on_sci_spi.342272802">
-        <stack module="module.driver.transfer_on_dtc.351428579" requires="module.driver.spi_on_sci_spi.requires.transfer_tx"/>
-        <stack module="module.driver.transfer_on_dtc.2037472890" requires="module.driver.spi_on_sci_spi.requires.transfer_rx"/>
-      </stack>
     </context>
     <config id="config.driver.ioport">
       <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
     </config>
-    <config id="config.driver.sci_spi">
-      <property id="config.driver.sci_spi.param_checking_enable" value="config.driver.sci_spi.param_checking_enable.bsp"/>
-      <property id="config.driver.sci_spi.dtc_support_enable" value="config.driver.sci_spi.dtc_support_enable.enabled"/>
-    </config>
-    <config id="config.driver.dtc">
-      <property id="config.driver.dtc.param_checking_enable" value="config.driver.dtc.param_checking_enable.bsp"/>
-      <property id="config.driver.dtc.vector_table" value=".fsp_dtc_vector_table"/>
-    </config>
     <config id="config.driver.sci_uart">
       <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
       <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>

bsp/renesas/ra4m2-eco/memory_regions.scat

@@ -12,11 +12,11 @@
                 #define OPTION_SETTING_S_LENGTH 0x100
                 #define ID_CODE_START  0x00000000
                 #define ID_CODE_LENGTH 0x0
-                #define SDRAM_START  0x00000000
+                #define SDRAM_START  0x80010000
                 #define SDRAM_LENGTH 0x0
                 #define QSPI_FLASH_START  0x60000000
                 #define QSPI_FLASH_LENGTH 0x4000000
-                #define OSPI_DEVICE_0_START  0x00000000
+                #define OSPI_DEVICE_0_START  0x80020000
                 #define OSPI_DEVICE_0_LENGTH 0x0
-                #define OSPI_DEVICE_1_START  0x00000000
+                #define OSPI_DEVICE_1_START  0x80030000
                 #define OSPI_DEVICE_1_LENGTH 0x0

bsp/renesas/ra4m2-eco/project.uvprojx

@@ -334,9 +334,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>__RTTHREAD__, RT_USING_ARMLIBC, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, RT_USING_LIBC</Define>
               <Undefine />
-              <IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\libraries\HAL_Drivers;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\dfs\dfs_v1\filesystems\devfs;board\ports;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;.;board;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\libc\posix\ipc</IncludePath>
+              <IncludePath>..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\epoll;..\libraries\HAL_Drivers\config;board\ports;..\libraries\HAL_Drivers;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\libcpu\arm\common;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;board;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\ipc;.;..\..\..\components\dfs\dfs_v1\filesystems\devfs</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -478,47 +478,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>dataqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
-              <FileOption>
-                <FileArmAds>
-                  <Cads>
-                    <VariousControls>
-                      <MiscControls> </MiscControls>
-                      <Define>__RT_IPC_SOURCE__</Define>
-                      <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>pipe.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
-              <FileOption>
-                <FileArmAds>
-                  <Cads>
-                    <VariousControls>
-                      <MiscControls> </MiscControls>
-                      <Define>__RT_IPC_SOURCE__</Define>
-                      <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>ringblk_buf.c</FileName>
+              <FileName>condvar.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -535,9 +497,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>ringbuffer.c</FileName>
+              <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -554,9 +516,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>waitqueue.c</FileName>
+              <FileName>pipe.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -573,9 +535,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>workqueue.c</FileName>
+              <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -592,9 +554,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>pin.c</FileName>
+              <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\pin\pin.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -611,9 +573,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>serial_v2.c</FileName>
+              <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\serial\serial_v2.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -630,9 +592,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>spi_core.c</FileName>
+              <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
+              <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -649,9 +611,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>spi_dev.c</FileName>
+              <FileName>pin.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
+              <FilePath>..\..\..\components\drivers\pin\pin.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -668,9 +630,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>spi_msd.c</FileName>
+              <FileName>serial_v2.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\spi\spi_msd.c</FilePath>
+              <FilePath>..\..\..\components\drivers\serial\serial_v2.c</FilePath>
               <FileOption>
                 <FileArmAds>
                   <Cads>
@@ -726,25 +688,6 @@
               </FileOption>
             </File>
           </Files>
-          <Files>
-            <File>
-              <FileName>drv_sci_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\HAL_Drivers\drv_sci_spi.c</FilePath>
-              <FileOption>
-                <FileArmAds>
-                  <Cads>
-                    <VariousControls>
-                      <MiscControls>  -std=c99</MiscControls>
-                      <Define> </Define>
-                      <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-          </Files>
           <Files>
             <File>
               <FileName>drv_usart_v2.c</FileName>
@@ -807,37 +750,37 @@
           <GroupName>Finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_parse.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>msh_file.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_file.c</FileName>
+              <FileName>msh.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/renesas/ra4m2-eco/ra/fsp/inc/api/r_ioport_api.h

@@ -69,6 +69,12 @@ typedef enum e_ioport_peripheral
 
     /** Pin will function as an AGT peripheral pin */
     IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+	
+	 /** Pin will function as an AGT peripheral pin */
+    IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+	
+	 /** Pin will function as an AGT peripheral pin */
+    IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
     /** Pin will function as a GPT peripheral pin */
     IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),

bsp/renesas/ra4m2-eco/ra/fsp/inc/api/r_spi_api.h

@@ -1,299 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_SPI_API_H
-#define R_SPI_API_H
-
-/*****************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup SPI_API SPI Interface
- * @brief Interface for SPI communications.
- *
- * @section SPI_API_SUMMARY Summary
- * Provides a common interface for communication using the SPI Protocol.
- *
- * Implemented by:
- * - @ref SPI
- * - @ref SCI_SPI
- *
- * @{
- ********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Includes
- ********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-#include "r_transfer_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/*********************************************************************************************************************
- * Macro definitions
- ********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- ********************************************************************************************************************/
-
-/** Data bit width */
-typedef enum e_spi_bit_width
-{
-    SPI_BIT_WIDTH_4_BITS  = (3),       ///< Data bit width is 4 bits (byte)
-    SPI_BIT_WIDTH_5_BITS  = (4),       ///< Data bit width is 5 bits (byte)
-    SPI_BIT_WIDTH_6_BITS  = (5),       ///< Data bit width is 6 bits (byte)
-    SPI_BIT_WIDTH_7_BITS  = (6),       ///< Data bit width is 7 bits (byte)
-    SPI_BIT_WIDTH_8_BITS  = (7),       ///< Data bit width is 8 bits (byte)
-    SPI_BIT_WIDTH_9_BITS  = (8),       ///< Data bit width is 9 bits (word)
-    SPI_BIT_WIDTH_10_BITS = (9),       ///< Data bit width is 10 bits (word)
-    SPI_BIT_WIDTH_11_BITS = (10),      ///< Data bit width is 11 bits (word)
-    SPI_BIT_WIDTH_12_BITS = (11),      ///< Data bit width is 12 bits (word)
-    SPI_BIT_WIDTH_13_BITS = (12),      ///< Data bit width is 13 bits (word)
-    SPI_BIT_WIDTH_14_BITS = (13),      ///< Data bit width is 14 bits (word)
-    SPI_BIT_WIDTH_15_BITS = (14),      ///< Data bit width is 15 bits (word)
-    SPI_BIT_WIDTH_16_BITS = (15),      ///< Data bit width is 16 bits (word)
-    SPI_BIT_WIDTH_17_BITS = (16),      ///< Data bit width is 17 bits (word)
-    SPI_BIT_WIDTH_18_BITS = (17),      ///< Data bit width is 18 bits (word)
-    SPI_BIT_WIDTH_19_BITS = (18),      ///< Data bit width is 19 bits (word)
-    SPI_BIT_WIDTH_20_BITS = (19),      ///< Data bit width is 20 bits (longword)
-    SPI_BIT_WIDTH_21_BITS = (20),      ///< Data bit width is 21 bits (word)
-    SPI_BIT_WIDTH_22_BITS = (21),      ///< Data bit width is 22 bits (word)
-    SPI_BIT_WIDTH_23_BITS = (22),      ///< Data bit width is 23 bits (longword)
-    SPI_BIT_WIDTH_24_BITS = (23),      ///< Data bit width is 24 bits (longword)
-    SPI_BIT_WIDTH_25_BITS = (25),      ///< Data bit width is 25 bits (longword)
-    SPI_BIT_WIDTH_26_BITS = (25),      ///< Data bit width is 26 bits (word)
-    SPI_BIT_WIDTH_27_BITS = (26),      ///< Data bit width is 27 bits (word)
-    SPI_BIT_WIDTH_28_BITS = (27),      ///< Data bit width is 28 bits (word)
-    SPI_BIT_WIDTH_29_BITS = (28),      ///< Data bit width is 29 bits (word)
-    SPI_BIT_WIDTH_30_BITS = (29),      ///< Data bit width is 30 bits (longword)
-    SPI_BIT_WIDTH_31_BITS = (30),      ///< Data bit width is 31 bits (longword)
-    SPI_BIT_WIDTH_32_BITS = (31)       ///< Data bit width is 32 bits (longword)
-} spi_bit_width_t;
-
-/** Master or slave operating mode */
-typedef enum e_spi_mode
-{
-    SPI_MODE_MASTER,                   ///< Channel operates as SPI master
-    SPI_MODE_SLAVE                     ///< Channel operates as SPI slave
-} spi_mode_t;
-
-/** Clock phase */
-typedef enum e_spi_clk_phase
-{
-    SPI_CLK_PHASE_EDGE_ODD,            ///< 0: Data sampling on odd edge, data variation on even edge
-    SPI_CLK_PHASE_EDGE_EVEN            ///< 1: Data variation on odd edge, data sampling on even edge
-} spi_clk_phase_t;
-
-/** Clock polarity */
-typedef enum e_spi_clk_polarity
-{
-    SPI_CLK_POLARITY_LOW,              ///< 0: Clock polarity is low when idle
-    SPI_CLK_POLARITY_HIGH              ///< 1: Clock polarity is high when idle
-} spi_clk_polarity_t;
-
-/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be
- *  controlled by the master. This usually happens when the connecting device is also acting as master.
- *  A similar situation can also happen when configured as a slave. */
-typedef enum e_spi_mode_fault
-{
-    SPI_MODE_FAULT_ERROR_ENABLE,       ///< Mode fault error flag on
-    SPI_MODE_FAULT_ERROR_DISABLE       ///< Mode fault error flag off
-} spi_mode_fault_t;
-
-/** Bit order */
-typedef enum e_spi_bit_order
-{
-    SPI_BIT_ORDER_MSB_FIRST,           ///< Send MSB first in transmission
-    SPI_BIT_ORDER_LSB_FIRST            ///< Send LSB first in transmission
-} spi_bit_order_t;
-
-/** SPI events */
-typedef enum e_spi_event
-{
-    SPI_EVENT_TRANSFER_COMPLETE = 1,   ///< The data transfer was completed
-    SPI_EVENT_TRANSFER_ABORTED,        ///< The data transfer was aborted
-    SPI_EVENT_ERR_MODE_FAULT,          ///< Mode fault error
-    SPI_EVENT_ERR_READ_OVERFLOW,       ///< Read overflow error
-    SPI_EVENT_ERR_PARITY,              ///< Parity error
-    SPI_EVENT_ERR_OVERRUN,             ///< Overrun error
-    SPI_EVENT_ERR_FRAMING,             ///< Framing error
-    SPI_EVENT_ERR_MODE_UNDERRUN        ///< Underrun error
-} spi_event_t;
-
-/** Common callback parameter definition */
-typedef struct st_spi_callback_args
-{
-    uint32_t     channel;              ///< Device channel number
-    spi_event_t  event;                ///< Event code
-    void const * p_context;            ///< Context provided to user during callback
-} spi_callback_args_t;
-
-/** Non-secure arguments for write-read guard function */
-typedef struct st_spi_write_read_guard_args
-{
-    void const          * p_src;
-    void                * p_dest;
-    uint32_t const        length;
-    spi_bit_width_t const bit_width;
-} spi_write_read_guard_args_t;
-
-/** SPI interface configuration */
-typedef struct st_spi_cfg
-{
-    uint8_t channel;                                   ///< Channel number to be used
-
-    IRQn_Type                   rxi_irq;               ///< Receive Buffer Full IRQ number
-    IRQn_Type                   txi_irq;               ///< Transmit Buffer Empty IRQ number
-    IRQn_Type                   tei_irq;               ///< Transfer Complete IRQ number
-    IRQn_Type                   eri_irq;               ///< Error IRQ number
-    uint8_t                     rxi_ipl;               ///< Receive Interrupt priority
-    uint8_t                     txi_ipl;               ///< Transmit Interrupt priority
-    uint8_t                     tei_ipl;               ///< Transfer Complete Interrupt priority
-    uint8_t                     eri_ipl;               ///< Error Interrupt priority
-    spi_mode_t                  operating_mode;        ///< Select master or slave operating mode
-    spi_clk_phase_t             clk_phase;             ///< Data sampling on odd or even clock edge
-    spi_clk_polarity_t          clk_polarity;          ///< Clock level when idle
-    spi_mode_fault_t            mode_fault;            ///< Mode fault error (master/slave conflict) flag
-    spi_bit_order_t             bit_order;             ///< Select to transmit MSB/LSB first
-    transfer_instance_t const * p_transfer_tx;         ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here.  Set to NULL if unused.
-    transfer_instance_t const * p_transfer_rx;         ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here.  Set to NULL if unused.
-    void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function
-    void const * p_context;                            ///< User defined context passed to callback function
-    void const * p_extend;                             ///< Extended SPI hardware dependent configuration
-} spi_cfg_t;
-
-/** SPI control block.  Allocate an instance specific control block to pass into the SPI API calls.
- * @par Implemented as
- * - spi_instance_ctrl_t
- * - spi_b_instance_ctrl_t
- * - sci_spi_instance_ctrl_t
- */
-typedef void spi_ctrl_t;
-
-/** Shared Interface definition for SPI */
-typedef struct st_spi_api
-{
-    /** Initialize a channel for SPI communication mode.
-     * @par Implemented as
-     * - @ref R_SPI_Open()
-     * - @ref R_SPI_B_Open()
-     * - @ref R_SCI_SPI_Open()
-     *
-     * @param[in, out] p_ctrl Pointer to user-provided storage for the control block.
-     * @param[in]      p_cfg  Pointer to SPI configuration structure.
-     */
-    fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg);
-
-    /** Receive data from a SPI device.
-     * @par Implemented as
-     * - @ref R_SPI_Read()
-     * - @ref R_SPI_B_Read()
-     * - @ref R_SCI_SPI_Read()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the
-     *                       bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     * @param[out] p_dest    Pointer to destination buffer into which data will be copied that is received from a SPI
-     *                       device. It is the responsibility of the caller to ensure that adequate space is available
-     *                       to hold the requested data count.
-     */
-    fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length,
-                       spi_bit_width_t const bit_width);
-
-    /** Transmit data to a SPI device.
-     * @par Implemented as
-     * - @ref R_SPI_Write()
-     * - @ref R_SPI_B_Write()
-     * - @ref R_SCI_SPI_Write()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  p_src     Pointer to a source data buffer from which data will be transmitted to a SPI device.
-     *                       The argument must not be NULL.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the
-     *                       bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     */
-    fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length,
-                        spi_bit_width_t const bit_width);
-
-    /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex).
-     * @par Implemented as
-     * - @ref R_SPI_WriteRead()
-     * - @ref R_SPI_B_WriteRead()
-     * - @ref R_SCI_SPI_WriteRead()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  p_src     Pointer to a source data buffer from which data will be transmitted to a SPI device.
-     *                       The argument must not be NULL.
-     * @param[out] p_dest    Pointer to destination buffer into which data will be copied that is received from a SPI
-     *                       device. It is the responsibility of the caller to ensure that adequate space is available
-     *                       to hold the requested data count. The argument must not be NULL.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     */
-    fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length,
-                            spi_bit_width_t const bit_width);
-
-    /**
-     * Specify callback function and optional context pointer and working memory pointer.
-     * @par Implemented as
-     * - @ref R_SPI_CallbackSet()
-     * - @ref R_SPI_B_CallbackSet()
-     * - @ref R_SCI_SPI_CallbackSet()
-     *
-     * @param[in]   p_ctrl                   Pointer to the SPI control block.
-     * @param[in]   p_callback               Callback function
-     * @param[in]   p_context                Pointer to send to callback function
-     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
-     *                                       Callback arguments allocated here are only valid during the callback.
-     */
-    fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *),
-                              void const * const p_context, spi_callback_args_t * const p_callback_memory);
-
-    /** Remove power to the SPI channel designated by the handle and disable the associated interrupts.
-     * @par Implemented as
-     * - @ref R_SPI_Close()
-     * - @ref R_SPI_B_Close()
-     * - @ref R_SCI_SPI_Close()
-     *
-     * @param[in]  p_ctrl  Pointer to the control block for the channel.
-     */
-    fsp_err_t (* close)(spi_ctrl_t * const p_ctrl);
-} spi_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_spi_instance
-{
-    spi_ctrl_t      * p_ctrl;          ///< Pointer to the control structure for this instance
-    spi_cfg_t const * p_cfg;           ///< Pointer to the configuration structure for this instance
-    spi_api_t const * p_api;           ///< Pointer to the API structure for this instance
-} spi_instance_t;
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-/*****************************************************************************************************************//**
- * @} (end defgroup SPI_API)
- ********************************************************************************************************************/
-
-#endif

bsp/renesas/ra4m2-eco/ra/fsp/inc/fsp_common_api.h

@@ -297,6 +297,17 @@ typedef enum e_fsp_err
     FSP_ERR_WIFI_FAILED           = 70004,           ///< WiFi Failed.
     FSP_ERR_WIFI_SCAN_COMPLETE    = 70005,           ///< Wifi scan has completed.
     FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006,           ///< WiFi module is not connected to access point
+    FSP_ERR_WIFI_UNKNOWN_AT_CMD   = 70007,           ///< DA16200 Unknown AT command Error
+    FSP_ERR_WIFI_INSUF_PARAM      = 70008,           ///< DA16200 Insufficient parameter
+    FSP_ERR_WIFI_TOO_MANY_PARAMS  = 70009,           ///< DA16200 Too many parameters
+    FSP_ERR_WIFI_INV_PARAM_VAL    = 70010,           ///< DA16200 Wrong parameter value        
+    FSP_ERR_WIFI_NO_RESULT        = 70011,           ///< DA16200 No result
+    FSP_ERR_WIFI_RSP_BUF_OVFLW    = 70012,           ///< DA16200 Response buffer overflow
+    FSP_ERR_WIFI_FUNC_NOT_CONFIG  = 70013,           ///< DA16200 Function is not configured    
+    FSP_ERR_WIFI_NVRAM_WR_FAIL    = 70014,           ///< DA16200 NVRAM write failure
+    FSP_ERR_WIFI_RET_MEM_WR_FAIL  = 70015,           ///< DA16200 Retention memory write failure
+    FSP_ERR_WIFI_UNKNOWN_ERR      = 70016,           ///< DA16200 unknown error
+
 
     /* Start of SF_CELLULAR Specific */
     FSP_ERR_CELLULAR_CONFIG_FAILED       = 80000,    ///< Cellular module Configuration failed.

bsp/renesas/ra4m2-eco/ra/fsp/inc/fsp_version.h

@@ -45,7 +45,7 @@ extern "C" {
  #define FSP_VERSION_MAJOR (4U)
 
 /** FSP pack minor version. */
- #define FSP_VERSION_MINOR (1U)
+ #define FSP_VERSION_MINOR (2U)
 
 /** FSP pack patch version. */
  #define FSP_VERSION_PATCH (0U)
@@ -54,10 +54,10 @@ extern "C" {
  #define FSP_VERSION_BUILD           (0U)
 
 /** Public FSP version name. */
- #define FSP_VERSION_STRING          ("4.1.0")
+ #define FSP_VERSION_STRING          ("4.2.0")
 
 /** Unique FSP version ID. */
- #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 4.1.0")
+ #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 4.2.0")
 
 /**********************************************************************************************************************
  * Typedef definitions

bsp/renesas/ra4m2-eco/ra/fsp/inc/instances/r_dtc.h

@@ -1,106 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup DTC
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_DTC_H
-#define R_DTC_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "bsp_api.h"
-#include "r_transfer_api.h"
-#include "r_dtc_cfg.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** Max configurable number of transfers in NORMAL MODE */
-#define DTC_MAX_NORMAL_TRANSFER_LENGTH    (0x10000)
-
-/** Max number of transfers per repeat for REPEAT MODE */
-#define DTC_MAX_REPEAT_TRANSFER_LENGTH    (0x100)
-
-/** Max number of transfers per block in BLOCK MODE */
-#define DTC_MAX_BLOCK_TRANSFER_LENGTH     (0x100)
-
-/** Max configurable number of blocks to transfer in BLOCK MODE */
-#define DTC_MAX_BLOCK_COUNT               (0x10000)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** DTC transfer configuration extension. This extension is required. */
-typedef struct st_dtc_extended_cfg
-{
-    /** Select which IRQ will trigger the transfer. */
-    IRQn_Type activation_source;
-} dtc_extended_cfg_t;
-
-/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */
-typedef struct st_dtc_instance_ctrl
-{
-    uint32_t  open;                    // Driver ID
-    IRQn_Type irq;                     // Transfer activation IRQ number.
-} dtc_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const transfer_api_t g_transfer_on_dtc;
-
-/** @endcond */
-
-/**********************************************************************************************************************
- * Public Function Prototypes
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg);
-fsp_err_t R_DTC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info);
-fsp_err_t R_DTC_Reset(transfer_ctrl_t * const p_api_ctrl,
-                      void const * volatile   p_src,
-                      void * volatile         p_dest,
-                      uint16_t const          num_transfers);
-fsp_err_t R_DTC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode);
-fsp_err_t R_DTC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_Enable(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_Disable(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties);
-fsp_err_t R_DTC_Close(transfer_ctrl_t * const p_api_ctrl);
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
-
-/*******************************************************************************************************************//**
- * @} (end defgroup DTC)
- **********************************************************************************************************************/

bsp/renesas/ra4m2-eco/ra/fsp/inc/instances/r_sci_spi.h

@@ -1,120 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_SCI_SPI_H
-#define R_SCI_SPI_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_spi_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/*****************************************************************************************************************//**
- * @ingroup SCI_SPI
- * @{
- ********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** Settings for adjusting the SPI CLK. */
-typedef struct
-{
-    uint8_t brr;
-    uint8_t cks : 2;
-    uint8_t mddr;                      ///< Set to 0 to disable MDDR.
-} sci_spi_div_setting_t;
-
-/** SCI SPI extended configuration */
-typedef struct st_sci_spi_extended_cfg
-{
-    sci_spi_div_setting_t clk_div;
-} sci_spi_extended_cfg_t;
-
-/** SPI instance control block. DO NOT INITIALIZE. */
-typedef struct st_sci_spi_instance_ctrl
-{
-    uint32_t          open;
-    spi_cfg_t const * p_cfg;
-    R_SCI0_Type     * p_reg;
-    uint8_t         * p_src;
-    uint8_t         * p_dest;
-    uint32_t          tx_count;
-    uint32_t          rx_count;
-    uint32_t          count;
-
-    /* Pointer to callback and optional working memory */
-    void (* p_callback)(spi_callback_args_t *);
-    spi_callback_args_t * p_callback_memory;
-
-    /* Pointer to context to be passed into callback function */
-    void const * p_context;
-} sci_spi_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const spi_api_t g_spi_on_sci;
-
-/** @endcond */
-
-/**********************************************************************************************************************
- * Public Function Prototypes
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg);
-fsp_err_t R_SCI_SPI_Read(spi_ctrl_t * const    p_api_ctrl,
-                         void                * p_dest,
-                         uint32_t const        length,
-                         spi_bit_width_t const bit_width);
-fsp_err_t R_SCI_SPI_Write(spi_ctrl_t * const    p_api_ctrl,
-                          void const          * p_src,
-                          uint32_t const        length,
-                          spi_bit_width_t const bit_width);
-fsp_err_t R_SCI_SPI_WriteRead(spi_ctrl_t * const    p_api_ctrl,
-                              void const          * p_src,
-                              void                * p_dest,
-                              uint32_t const        length,
-                              spi_bit_width_t const bit_width);
-fsp_err_t R_SCI_SPI_Close(spi_ctrl_t * const p_api_ctrl);
-fsp_err_t R_SCI_SPI_CalculateBitrate(uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr);
-fsp_err_t R_SCI_SPI_CallbackSet(spi_ctrl_t * const          p_api_ctrl,
-                                void (                    * p_callback)(spi_callback_args_t *),
-                                void const * const          p_context,
-                                spi_callback_args_t * const p_callback_memory);
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
-
-/*******************************************************************************************************************//**
- * @} (end ingroup SCI_SPI)
- **********************************************************************************************************************/

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_clocks.c

@@ -116,7 +116,15 @@
   #endif
  #endif
 #endif
-
+#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_1            (0) // Divide USB source clock by 1
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_2            (1) // Divide USB source clock by 2
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_3            (5) // Divide USB source clock by 3
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_4            (2) // Divide USB source clock by 4
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_5            (6) // Divide USB source clock by 5
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_6            (3) // Divide USB source clock by 6
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_8            (4) // Divide USB source clock by 8
+#endif /* BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ*/
 /* Choose the value to write to FLLCR2 (if applicable). */
 #if BSP_PRV_HOCO_USE_FLL
  #if 1U == BSP_CFG_HOCO_FREQUENCY
@@ -267,6 +275,24 @@
                                                      BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) |                    \
                                                     (BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK))
  #endif
+ #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+  #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE
+   #define BSP_PRV_PLL_USED                        (1)
+  #else
+   #define BSP_PRV_PLL_USED                        (0)
+  #endif
+
+  #define BSP_PRV_PLLCCR_PLLMUL_MASK               (0xFFU)   // PLLMUL is 8 bits wide
+  #define BSP_PRV_PLLCCR_PLLMUL_BIT                (8)       // PLLMUL starts at bit 8
+  #define BSP_PRV_PLSET_MASK                       (0x01U)   // PLSET is 1 bit wide
+  #define BSP_PRV_PLSET_BIT                        (6)       // PLSET starts at bit 6
+  #define BSP_PRV_PLLCCR_RESET                     (0x0008U) // Bit 3 must be written as 1
+  #define BSP_PRV_PLLCCR                           (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
+                                                     BSP_PRV_PLLCCR_PLLMUL_BIT) |                      \
+                                                    ((BSP_CFG_PLSET & BSP_PRV_PLSET_MASK) <<           \
+                                                     BSP_PRV_PLSET_BIT) |                              \
+                                                    BSP_PRV_PLLCCR_RESET
+ #endif
 #endif
 
 #if BSP_FEATURE_CGC_HAS_PLL2
@@ -338,13 +364,15 @@
  #define BSP_PRV_MAIN_OSC_USED                    (1)
 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
+#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED                    (1)
 #elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
 #elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
 #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
-#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
  #define BSP_PRV_MAIN_OSC_USED                    (1)
@@ -352,7 +380,7 @@
  #define BSP_PRV_MAIN_OSC_USED                    (0)
 #endif
 
-/* All clocks with configurable source can use HOCO except the I3CCLK. */
+/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */
 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
  #define BSP_PRV_HOCO_USED                        (1)
  #define BSP_PRV_STABILIZE_HOCO                   (1)
@@ -383,7 +411,7 @@
  #define BSP_PRV_HOCO_USED                        (1)
 #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
  #define BSP_PRV_HOCO_USED                        (1)
-#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
  #define BSP_PRV_HOCO_USED                        (1)
 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
  #define BSP_PRV_HOCO_USED                        (1)
@@ -418,7 +446,7 @@
  #define BSP_PRV_MOCO_USED                        (1)
 #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
  #define BSP_PRV_MOCO_USED                        (1)
-#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
  #define BSP_PRV_MOCO_USED                        (1)
 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
  #define BSP_PRV_MOCO_USED                        (1)
@@ -476,8 +504,10 @@
     (BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
     (BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
     (BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
+    (BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
     (BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
     (BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||       \
+    (BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) ||  \
     (BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED))
 
  #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS    (1U)
@@ -1132,6 +1162,8 @@ static void bsp_clock_freq_var_init (void)
     g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL]   = BSP_CFG_PLL1P_FREQUENCY_HZ;
     g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ;
     g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ;
+ #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U;
  #else
     g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >>
                                                 BSP_CFG_PLL_DIV;
@@ -1583,6 +1615,11 @@ void bsp_clock_init (void)
     bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE);
 #endif
 
+    /* Set the CEC clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+    bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE);
+#endif
+
     /* Set the I3C clock if it exists on the MCU */
 #if BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
     bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE);
@@ -1599,8 +1636,8 @@ void bsp_clock_init (void)
 #endif
 
     /* Set the USB-HS clock if it exists on the MCU */
-#if BSP_FEATURE_BSP_HAS_USBHS_CLOCK && (BSP_CFG_UHSCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
-    bsp_peripheral_clock_set(&R_SYSTEM->USBHSCKCR, &R_SYSTEM->USBHSCKDIVCR, BSP_CFG_UHSCK_DIV, BSP_CFG_UHSCK_SOURCE);
+#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+    bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, &R_SYSTEM->USB60CKDIVCR, BSP_CFG_U60CK_DIV, BSP_CFG_U60CK_SOURCE);
 #endif
 
     /* Lock CGC and LPM protection registers. */

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_clocks.h

@@ -61,7 +61,10 @@ FSP_HEADER
  *  - When the PLL only accepts the main oscillator as a source and XTAL is not used
  */
 #if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
-    !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
+    !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                    \
+    (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                      \
+    (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                      \
+    !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
  #define BSP_PRV_PLL_SUPPORTED              (1)
  #if BSP_FEATURE_CGC_HAS_PLL2
   #define BSP_PRV_PLL2_SUPPORTED            (1)
@@ -169,14 +172,14 @@ FSP_HEADER
 #define BSP_CLOCKS_USB_CLOCK_DIV_6       (3)  // Divide USB source clock by 6
 #define BSP_CLOCKS_USB_CLOCK_DIV_8       (4)  // Divide USB source clock by 8
 
-/* USBHS clock divider options. */
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_1     (0)  // Divide USBHS source clock by 1
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_2     (1)  // Divide USBHS source clock by 2
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_3     (5)  // Divide USBHS source clock by 3
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_4     (2)  // Divide USBHS source clock by 4
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_5     (6)  // Divide USBHS source clock by 5
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_6     (3)  // Divide USBHS source clock by 6
-#define BSP_CLOCKS_USBHS_CLOCK_DIV_8     (4)  // Divide USBHS source clock by 8
+/* USB60 clock divider options. */
+#define BSP_CLOCKS_USB60_CLOCK_DIV_1     (0)  // Divide USB60 source clock by 1
+#define BSP_CLOCKS_USB60_CLOCK_DIV_2     (1)  // Divide USB60 source clock by 2
+#define BSP_CLOCKS_USB60_CLOCK_DIV_3     (5)  // Divide USB60 source clock by 3
+#define BSP_CLOCKS_USB60_CLOCK_DIV_4     (2)  // Divide USB60 source clock by 4
+#define BSP_CLOCKS_USB60_CLOCK_DIV_5     (6)  // Divide USB60 source clock by 5
+#define BSP_CLOCKS_USB60_CLOCK_DIV_6     (3)  // Divide USB66 source clock by 6
+#define BSP_CLOCKS_USB60_CLOCK_DIV_8     (4)  // Divide USB60 source clock by 8
 
 /* GLCD clock divider options. */
 #define BSP_CLOCKS_LCD_CLOCK_DIV_1       (0)  // Divide LCD source clock by 1
@@ -197,7 +200,9 @@ FSP_HEADER
 /* CANFD clock divider options. */
 #define BSP_CLOCKS_CANFD_CLOCK_DIV_1     (0)  // Divide CANFD source clock by 1
 #define BSP_CLOCKS_CANFD_CLOCK_DIV_2     (1)  // Divide CANFD source clock by 2
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_3     (5)  // Divide CANFD source clock by 3
 #define BSP_CLOCKS_CANFD_CLOCK_DIV_4     (2)  // Divide CANFD source clock by 4
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_5     (6)  // Divide CANFD source clock by 5
 #define BSP_CLOCKS_CANFD_CLOCK_DIV_6     (3)  // Divide CANFD source clock by 6
 #define BSP_CLOCKS_CANFD_CLOCK_DIV_8     (4)  // Divide CANFD source clock by 8
 
@@ -242,6 +247,10 @@ FSP_HEADER
 #define BSP_CLOCKS_IIC_CLOCK_DIV_6       (3)  // Divide IIC source clock by 6
 #define BSP_CLOCKS_IIC_CLOCK_DIV_8       (4)  // Divide IIC source clock by 8
 
+/* CEC clock divider options. */
+#define BSP_CLOCKS_CEC_CLOCK_DIV_1       (0)  // Divide CEC source clock by 1
+#define BSP_CLOCKS_CEC_CLOCK_DIV_2       (1)  // Divide CEC source clock by 2
+
 /* I3C clock divider options. */
 #define BSP_CLOCKS_I3C_CLOCK_DIV_1       (0)  // Divide I3C source clock by 1
 #define BSP_CLOCKS_I3C_CLOCK_DIV_2       (1)  // Divide I3C source clock by 2
@@ -1044,6 +1053,8 @@ typedef enum e_cgc_pll_mul
     CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33
     CGC_PLL_MUL_180_5  = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50
     CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66
+    CGC_PLL_MUL_732_0  = BSP_CLOCKS_PLL_MUL(732U, 0U),  ///< PLL multiplier of 732.00
+    CGC_PLL_MUL_781_0  = BSP_CLOCKS_PLL_MUL(781U, 0U),  ///< PLL multiplier of 781.00
 } cgc_pll_mul_t;
 
 /***********************************************************************************************************************

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h

@@ -90,6 +90,8 @@ FSP_HEADER
   #define BSP_MSTP_BIT_FSP_IP_KEY(channel)      (1U << 4U);
   #define BSP_MSTP_REG_FSP_IP_POEG(channel)     R_MSTP->MSTPCRD
   #define BSP_MSTP_BIT_FSP_IP_POEG(channel)     (1U << (14U - channel));
+  #define BSP_MSTP_REG_FSP_IP_ULPT(channel)     R_MSTP->MSTPCRE
+  #define BSP_MSTP_BIT_FSP_IP_ULPT(channel)     (1U << (9U - channel));
  #else
   #define BSP_MSTP_REG_FSP_IP_GPT(channel)      R_MSTP->MSTPCRE
   #define BSP_MSTP_BIT_FSP_IP_GPT(channel)      (1U << (31 - channel));

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c

@@ -62,6 +62,27 @@
 
 #if !BSP_CFG_BOOT_IMAGE
 
+ #if BSP_FEATURE_BSP_HAS_OSIS_REG == 1
+
+/** ID code definitions defined here. */
+BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
+{
+    BSP_CFG_ID_CODE_LONG_1,
+  #if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+  #endif
+    BSP_CFG_ID_CODE_LONG_2,
+  #if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+  #endif
+    BSP_CFG_ID_CODE_LONG_3,
+  #if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+  #endif
+    BSP_CFG_ID_CODE_LONG_4
+};
+ #endif
+
  #if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers)
 
 /** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
@@ -84,23 +105,22 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION
     (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
 };
 
-/** ID code definitions defined here. */
-BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
-{
-    BSP_CFG_ID_CODE_LONG_1,
-  #if BSP_FEATURE_BSP_OSIS_PADDING
-    0xFFFFFFFFU,
-  #endif
-    BSP_CFG_ID_CODE_LONG_2,
-  #if BSP_FEATURE_BSP_OSIS_PADDING
-    0xFFFFFFFFU,
-  #endif
-    BSP_CFG_ID_CODE_LONG_3,
-  #if BSP_FEATURE_BSP_OSIS_PADDING
-    0xFFFFFFFFU,
-  #endif
-    BSP_CFG_ID_CODE_LONG_4
-};
+ #elif BSP_FEATURE_BSP_HAS_OSIS_REG == 1
+
+    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
+        BSP_CFG_ROM_REG_OFS0;
+
+    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
+        0xFFFFFFFF;
+
+    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
+        BSP_ROM_REG_OFS1_SETTING;
+
+    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
+        BSP_CFG_ROM_REG_BPS0;
+
+    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
+        BSP_CFG_ROM_REG_PBPS0;
 
  #else                                 /* CM33 parts */
 

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_security.c

@@ -55,37 +55,9 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
  #endif
 
  #if   defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
-  #pragma section=".tz_flash_nsc_start"
-  #pragma section=".tz_ram_nsc_start"
-  #pragma section=".tz_ram_ns_start"
-  #pragma section=".tz_data_flash_ns_start"
-  #pragma section=".tz_sdram_ns_start"
-  #pragma section=".tz_qspi_flash_ns_start"
-  #pragma section=".tz_ospi_device_0_ns_start"
-  #pragma section=".tz_ospi_device_1_ns_start"
-
-/* &__tz_<REGION>_C is the address of the non-secure callable section. Must assign value to this variable or
- * linker will give error. */
-
-/* &__tz_<REGION>_N is the start address of the non-secure region. */
-BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
-BSP_DONT_REMOVE void * __tz_RAM_C               BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
-BSP_DONT_REMOVE void * __tz_RAM_N               BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
-BSP_DONT_REMOVE void * __tz_DATA_FLASH_N        BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
-
-  #if BSP_FEATURE_SDRAM_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start";
-  #endif
-BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
-  #if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
-  #endif
-  #if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
-  #endif
+  #pragma section=".tz_flash_ns_start"
 
-extern void const * const              __tz_FLASH_N;
-BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start");
  #elif defined(__ARMCC_VERSION)
   #if BSP_FEATURE_BSP_HAS_ITCM
 extern const uint32_t Image$$__tz_ITCM_N$$Base;

bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h

@@ -94,11 +94,12 @@
 #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER                (0)
 #define BSP_FEATURE_BSP_HAS_ADC_CLOCK                        (0)
 #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK                      (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_CEC_CLOCK                        (0) // Feature not available on this MCU
 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB               (0U)
 #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE                (0)
 #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR                   (0U)
 #define BSP_FEATURE_BSP_HAS_DTCM                             (0) // Feature not available on this MCU
-#define BSP_FEATURE_BSP_HAS_GPT_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_GPT_CLOCK                        (0) // Mutually exclusive with USB60 Clock
 #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN                  (0)
 #define BSP_FEATURE_BSP_HAS_I3C_CLOCK                        (0)
 #define BSP_FEATURE_BSP_HAS_IIC_CLOCK                        (0U)
@@ -111,13 +112,14 @@
 #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2                       (0) // Feature not available on this MCU
 #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_BSP_HAS_SCI_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK                      (0)
 #define BSP_FEATURE_BSP_HAS_SECURITY_MPU                     (0U)
 #define BSP_FEATURE_BSP_HAS_SPI_CLOCK                        (0)
 #define BSP_FEATURE_BSP_HAS_SP_MON                           (0U)
 #define BSP_FEATURE_BSP_HAS_SYRACCR                          (0U)
 #define BSP_FEATURE_BSP_HAS_TZFSAR                           (1)
+#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ                  (0U) // Feature not available on this MCU
 #define BSP_FEATURE_BSP_HAS_USBCKDIVCR                       (1U) // On the RA4M2 there are specific registers for configuring the USB clock.
-#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK                      (0)
 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV                    (1U)
 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ                    (1U)
 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL                    (1U)
@@ -129,6 +131,7 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (8U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
+#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -146,6 +149,7 @@
 #define BSP_FEATURE_CANFD_FD_SUPPORT                         (0U)
 #define BSP_FEATURE_CANFD_LITE                               (0U)
 #define BSP_FEATURE_CANFD_NUM_CHANNELS                       (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CANFD_NUM_INSTANCES                      (0U)
 
 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO                    (0U)
 #define BSP_FEATURE_CAN_CLOCK                                (0U)
@@ -173,9 +177,9 @@
 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2                        (1U) // On the RA4M2 there is another register to enable write access for SRAMWTSC.
 #define BSP_FEATURE_CGC_HAS_SRAMWTSC                         (1U)
 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR                  (0U)
-#define BSP_FEATURE_CGC_HOCOWTCR_VALUE                       (6U)
-#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE            (0)
 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY                  (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE            (0)
+#define BSP_FEATURE_CGC_HOCOWTCR_VALUE                       (6U)
 #define BSP_FEATURE_CGC_ICLK_DIV_RESET                       (BSP_CLOCKS_SYS_CLOCK_DIV_4)
 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US            (61U)
 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ                (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
@@ -207,7 +211,6 @@
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
-#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS            (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE9                          (1)
 
 #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT             (2U)
@@ -220,6 +223,7 @@
 #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE                   (0) // Feature not available on this MCU
 #define BSP_FEATURE_DAC8_MAX_CHANNELS                        (0) // Feature not available on this MCU
 
+#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK                    (0x01U)
 #define BSP_FEATURE_DAC_HAS_CHARGEPUMP                       (0U)
 #define BSP_FEATURE_DAC_HAS_DAVREFCR                         (0U)
 #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE                (1U)
@@ -288,6 +292,7 @@
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK                    (0xFFFFU)
 #define BSP_FEATURE_ICU_WUPEN_MASK                           (0x7FB0DFFFFULL) // Note there is another WUPEN1 register
+#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT                    (0U)
 
 #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER             (0U)
 #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS                     (0)              // Feature not available on this MCU TODO_CHECK_FEATURE
@@ -309,16 +314,24 @@
 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED                 (0U)
 #define BSP_FEATURE_LPM_DPSIEGR_MASK                         (0x13DFF3U)
 #define BSP_FEATURE_LPM_DPSIER_MASK                          (0x0D1FDFF3U)
+#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP                       (0U)
 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY                     (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT                  (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY                    (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP                   (0U)
+#define BSP_FEATURE_LPM_HAS_LDO_CONTROL                      (0U)
 #define BSP_FEATURE_LPM_HAS_LPSCR                            (0U)
+#define BSP_FEATURE_LPM_HAS_PDRAMSCR                         (0U)
 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE                        (0U)
 #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY                       (1U)
+#define BSP_FEATURE_LPM_HAS_SNOOZE                           (1U)
 #define BSP_FEATURE_LPM_HAS_SNZEDCR1                         (1U)
 #define BSP_FEATURE_LPM_HAS_SNZREQCR1                        (1U)
 #define BSP_FEATURE_LPM_HAS_STCONR                           (0U)
 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14                     (0)
-#define BSP_FEATURE_LPM_SNZEDCR_MASK                         (0x0000019FU)                         // note there is another SNZEDCR1 register
-#define BSP_FEATURE_LPM_SNZREQCR_MASK                        (0x77300FFFFULL)                      // note there is another SNZEREQCR1 register
+#define BSP_FEATURE_LPM_SNZEDCR_MASK                         (0x0000019FU)    // note there is another SNZEDCR1 register
+#define BSP_FEATURE_LPM_SNZREQCR_MASK                        (0x77300FFFFULL) // note there is another SNZEREQCR1 register
+#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED                (0U)
 
 #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER                   (1U)
 #define BSP_FEATURE_LVD_HAS_LVDLVLR                          (0U)
@@ -369,6 +382,7 @@
 #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                   (0) // Feature not available on this MCU
 #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN              (0) // Feature not available on this MCU
 #define BSP_FEATURE_SLCDC_MAX_NUM_SEG                        (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_VL1SEL                         (0)
 
 #define BSP_FEATURE_SPI_CLK                                  (FSP_PRIV_CLOCK_PCLKA)
 #define BSP_FEATURE_SPI_HAS_SPCR3                            (1U)

bsp/renesas/ra4m2-eco/ra/fsp/src/r_dtc/r_dtc.c

@@ -1,617 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include <string.h>
-#include "r_dtc.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** Driver ID (DTC in ASCII), used to identify Data Transfer Controller (DTC) configuration  */
-#define DTC_OPEN                    (0x44544300)
-
-/** Size of vector table is based on number of vectors defined in BSP. */
-#define DTC_VECTOR_TABLE_ENTRIES    (BSP_ICU_VECTOR_MAX_ENTRIES)
-
-/** The size of transfer_info_t is defined in the Hardware Manual therefore it must be 16 bytes. */
-#define DTC_TRANSFER_INFO_SIZE      (16U)
-
-/* Compiler specific macro to specify vector table section. */
-#ifndef DTC_CFG_VECTOR_TABLE_SECTION_NAME
- #define DTC_SECTION_ATTRIBUTE
- #ifndef SUPPRESS_WARNING_DTC_CFG_VECTOR_TABLE_SECTION_NAME
-  #warning "DTC vector table is aligned on 1K boundary. Automatic placing could lead to memory holes."
- #endif
-#else
- #define DTC_SECTION_ATTRIBUTE    BSP_PLACE_IN_SECTION(DTC_CFG_VECTOR_TABLE_SECTION_NAME)
-#endif
-
-/* Used to generate a compiler error (divided by 0 error) if the assertion fails.  This is used in place of "#error"
- * for expressions that cannot be evaluated by the preprocessor like sizeof(). */
-#define DTC_COMPILE_TIME_ASSERT(e)       ((void) sizeof(char[1 - 2 * !(e)]))
-
-/* Calculate the mask bits for byte alignment from the transfer_size_t. */
-#define DTC_PRV_MASK_ALIGN_N_BYTES(x)    ((1U << (x)) - 1U)
-
-/* Counter Register A Lower Byte Mask */
-#define DTC_PRV_MASK_CRAL             (0xFFU)
-
-/* Counter Register A Upper Byte Offset */
-#define DTC_PRV_OFFSET_CRAH           (8U)
-
-/* Offset of in_progress bit in R_DTC->DTCSTS. */
-#define DTC_PRV_OFFSET_IN_PROGRESS    (15U)
-
-/* DTC Control Register RRS Enable value. */
-#define DTC_PRV_RRS_ENABLE            (0x18)
-
-/* DTC Control Register RRS Disable value. */
-#define DTC_PRV_RRS_DISABLE           (0x08)
-
-/***********************************************************************************************************************
- * Private function prototypes
- **********************************************************************************************************************/
-
-static fsp_err_t r_dtc_prv_enable(dtc_instance_ctrl_t * p_ctrl);
-static void      r_dtc_state_initialize(void);
-static void      r_dtc_block_repeat_initialize(transfer_info_t * p_info);
-static void      r_dtc_set_info(dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info);
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
- #if BSP_CFG_ASSERT != 3
-static fsp_err_t r_dtc_length_assert(transfer_info_t * p_info);
-
- #endif
-static fsp_err_t r_dtc_source_destination_parameter_check(transfer_info_t * p_info);
-
-#endif
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-static transfer_info_t * gp_dtc_vector_table[DTC_VECTOR_TABLE_ENTRIES] BSP_ALIGN_VARIABLE(1024)
-DTC_SECTION_ATTRIBUTE;
-
-/***********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** DTC implementation of transfer API. */
-const transfer_api_t g_transfer_on_dtc =
-{
-    .open          = R_DTC_Open,
-    .reconfigure   = R_DTC_Reconfigure,
-    .reset         = R_DTC_Reset,
-    .infoGet       = R_DTC_InfoGet,
-    .softwareStart = R_DTC_SoftwareStart,
-    .softwareStop  = R_DTC_SoftwareStop,
-    .enable        = R_DTC_Enable,
-    .disable       = R_DTC_Disable,
-    .close         = R_DTC_Close,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup DTC
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configure the vector table if it hasn't been configured, enable the Module and copy the pointer to the transfer info
- * into the DTC vector table. Implements @ref transfer_api_t::open.
- *
- * Example:
- * @snippet r_dtc_example.c R_DTC_Open
- *
- * @retval FSP_SUCCESS              Successful open.
- *                                      Transfer transfer info pointer copied to DTC Vector table.
- *                                      Module started.
- *                                      DTC vector table configured.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- * @retval FSP_ERR_ALREADY_OPEN     The control structure is already opened.
- * @retval FSP_ERR_IN_USE           The index for this IRQ in the DTC vector table is already configured.
- * @retval FSP_ERR_IRQ_BSP_DISABLED The IRQ associated with the activation source is not enabled in the BSP.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg)
-{
-    /* Generate a compiler error if transfer_info_t is modified. */
-    DTC_COMPILE_TIME_ASSERT(sizeof(transfer_info_t) == DTC_TRANSFER_INFO_SIZE);
-
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open != DTC_OPEN, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ASSERT(NULL != p_cfg->p_extend);
-    FSP_ASSERT(NULL != p_cfg->p_info);
-    fsp_err_t err = r_dtc_length_assert(p_cfg->p_info);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
-    /* One time initialization for all DTC instances. */
-    r_dtc_state_initialize();
-
-    /* Make sure the activation source is mapped in the ICU. */
-    dtc_extended_cfg_t * p_dtc_cfg = (dtc_extended_cfg_t *) p_cfg->p_extend;
-    IRQn_Type            irq       = p_dtc_cfg->activation_source;
-    FSP_ERROR_RETURN(irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED);
-
-    /* Make sure the activation source is not already being used by the DTC. */
-    FSP_ERROR_RETURN(NULL == gp_dtc_vector_table[irq], FSP_ERR_IN_USE);
-
-    /* irq is used to index the DTC vector table. */
-    p_ctrl->irq = irq;
-
-    /* Copy p_info into the DTC vector table. */
-    r_dtc_set_info(p_ctrl, p_cfg->p_info);
-
-    /* Mark driver as open by initializing it to "DTC" in its ASCII equivalent. */
-    p_ctrl->open = DTC_OPEN;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Copy pointer to transfer info into the DTC vector table and enable transfer in ICU.
- * Implements @ref transfer_api_t::reconfigure.
- *
- * @retval FSP_SUCCESS              Transfer is configured and will start when trigger occurs.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_NOT_ENABLED      Transfer source address is NULL or is not aligned corrrectly.
- *                                  Transfer destination address is NULL or is not aligned corrrectly.
- *
- * @note p_info must persist until all transfers are completed.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Reconfigure (transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_info);
-    FSP_ASSERT(FSP_SUCCESS == r_dtc_length_assert(p_info));
-#endif
-
-    /* Disable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Wait for current transfer to finish. */
-    uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS;
-    while (in_progress == R_DTC->DTCSTS)
-    {
-        ;
-    }
-
-    /* Copy p_info into the DTC vector table. */
-    r_dtc_set_info(p_ctrl, p_info);
-
-    /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */
-    /* Enable transfers on this activation source. */
-    FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Reset transfer source, destination, and number of transfers. Implements @ref transfer_api_t::reset.
- *
- * @retval FSP_SUCCESS              Transfer reset successfully (transfers are enabled).
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_NOT_ENABLED      Transfer source address is NULL or is not aligned corrrectly.
- *                                  Transfer destination address is NULL or is not aligned corrrectly.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl,
-                       void const * volatile   p_src,
-                       void * volatile         p_dest,
-                       uint16_t const          num_transfers)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Disable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Wait for current transfer to finish. */
-    uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS;
-    while (in_progress == R_DTC->DTCSTS)
-    {
-        ;
-    }
-
-    /* Disable read skip prior to modifying settings. It will be enabled later
-     * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_DISABLE;
-#endif
-
-    /* Reset transfer based on input parameters. */
-    if (NULL != p_src)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->p_src = p_src;
-    }
-
-    if (NULL != p_dest)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->p_dest = p_dest;
-    }
-
-    if (TRANSFER_MODE_BLOCK == gp_dtc_vector_table[p_ctrl->irq]->transfer_settings_word_b.mode)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->num_blocks = num_transfers;
-    }
-    else if (TRANSFER_MODE_NORMAL == gp_dtc_vector_table[p_ctrl->irq]->transfer_settings_word_b.mode)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->length = num_transfers;
-    }
-    else                               /* (TRANSFER_MODE_REPEAT == gp_dtc_vector_table[p_ctrl->irq]->transfer_settings_word_b.mode) */
-    {
-        /* Do nothing. */
-    }
-
-    /* Enable read skip after all settings are written. */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_ENABLE;
-#endif
-
-    /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */
-    /* Enable transfers on this activation source. */
-    FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Placeholder for unsupported softwareStart function. Implements @ref transfer_api_t::softwareStart.
- *
- * @retval FSP_ERR_UNSUPPORTED      DTC software start is not supported.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_SoftwareStart (transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode)
-{
-    /* This function isn't supported.  It is defined only to implement a required function of transfer_api_t.
-     * Mark the input parameter as unused since this function isn't supported. */
-    FSP_PARAMETER_NOT_USED(p_api_ctrl);
-    FSP_PARAMETER_NOT_USED(mode);
-
-    return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * Placeholder for unsupported softwareStop function. Implements @ref transfer_api_t::softwareStop.
- *
- * @retval FSP_ERR_UNSUPPORTED      DTC software stop is not supported.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_SoftwareStop (transfer_ctrl_t * const p_api_ctrl)
-{
-    /* This function isn't supported.  It is defined only to implement a required function of transfer_api_t.
-     * Mark the input parameter as unused since this function isn't supported. */
-    FSP_PARAMETER_NOT_USED(p_api_ctrl);
-
-    return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * Enable transfers on this activation source. Implements @ref transfer_api_t::enable.
- *
- * Example:
- * @snippet r_dtc_example.c R_DTC_Enable
- *
- * @retval FSP_SUCCESS              Transfers will be triggered by the activation source
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Enable (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    return r_dtc_prv_enable(p_ctrl);
-}
-
-/*******************************************************************************************************************//**
- * Disable transfer on this activation source. Implements @ref transfer_api_t::disable.
- *
- * @retval FSP_SUCCESS              Transfers will not occur on activation events.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Disable (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Disable transfer. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Provides information about this transfer. Implements @ref transfer_api_t::infoGet.
- *
- * @retval FSP_SUCCESS              p_info updated with current instance information.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized. Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_InfoGet (transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_properties);
-#endif
-
-    transfer_info_t * p_info = gp_dtc_vector_table[p_ctrl->irq];
-
-    p_properties->block_count_max       = 0U;
-    p_properties->block_count_remaining = 0U;
-
-    if (TRANSFER_MODE_NORMAL != p_info->transfer_settings_word_b.mode)
-    {
-        /* Repeat and Block Mode */
-
-        /* transfer_length_max is the same for Block and repeat mode. */
-        p_properties->transfer_length_max       = DTC_MAX_REPEAT_TRANSFER_LENGTH;
-        p_properties->transfer_length_remaining = p_info->length & DTC_PRV_MASK_CRAL;
-
-        if (TRANSFER_MODE_BLOCK == p_info->transfer_settings_word_b.mode)
-        {
-            p_properties->block_count_max       = DTC_MAX_BLOCK_COUNT;
-            p_properties->block_count_remaining = p_info->num_blocks;
-        }
-    }
-    else
-    {
-        p_properties->transfer_length_max       = DTC_MAX_NORMAL_TRANSFER_LENGTH;
-        p_properties->transfer_length_remaining = p_info->length;
-    }
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disables DTC activation in the ICU, then clears transfer data from the DTC vector table.
- * Implements @ref transfer_api_t::close.
- *
- * @retval FSP_SUCCESS              Successful close.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Close (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-    fsp_err_t             err    = FSP_SUCCESS;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Clear DTC enable bit in ICU. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Clear pointer in vector table. */
-    gp_dtc_vector_table[p_ctrl->irq] = NULL;
-
-    /* Mark instance as closed. */
-    p_ctrl->open = 0U;
-
-    return err;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup DTC)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Verify that the source and destination pointers are valid then enable the DTC.
- *
- * @retval FSP_SUCCESS              Successfully enabled
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_prv_enable (dtc_instance_ctrl_t * p_ctrl)
-{
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    fsp_err_t err = r_dtc_source_destination_parameter_check(gp_dtc_vector_table[p_ctrl->irq]);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
-    /* Enable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 1U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * One time state initialization for all DTC instances.
- **********************************************************************************************************************/
-static void r_dtc_state_initialize (void)
-{
-    /* Stores initialization state to skip initialization in ::R_DTC_Open after the first call. */
-    static bool g_dtc_state_initialized = false;
-
-    /* DTC requires a one time initialization.  This will be handled only the first time this function
-     *  is called. This initialization:
-     *  -# Stores the register base addresses for DTC and ICU.
-     *  -# Powers on the DTC block.
-     *  -# Initializes the vector table to NULL pointers.
-     *  -# Sets the vector table base address.
-     *  -# Enables DTC transfers. */
-    if (!g_dtc_state_initialized)
-    {
-        g_dtc_state_initialized = true;
-
-        /** Power on DTC */
-        R_BSP_MODULE_START(FSP_IP_DTC, 0);
-
-        /* The DTC vector table must be cleared during initialization because it is located in
-         * its own section outside of the .BSS section which is cleared during startup. */
-        memset(&gp_dtc_vector_table, 0U, DTC_VECTOR_TABLE_ENTRIES * sizeof(transfer_info_t *));
-
-        /* Set DTC vector table. */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
-        R_DTC->DTCVBR_SEC = (uint32_t) gp_dtc_vector_table;
-#else
-        R_DTC->DTCVBR = (uint32_t) gp_dtc_vector_table;
-#endif
-
-        /* Enable the DTC Peripheral */
-        R_DTC->DTCST = 1U;
-    }
-}
-
-/*******************************************************************************************************************//**
- * Configure the p_info state and write p_info to DTC vector table.
- **********************************************************************************************************************/
-static void r_dtc_set_info (dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info)
-{
-    /* Update internal variables. */
-    r_dtc_block_repeat_initialize(p_info);
-
-    /* Disable read skip prior to modifying settings. It will be enabled later
-     * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_DISABLE;
-#endif
-
-    /* Update the entry in the DTC Vector table. */
-    gp_dtc_vector_table[p_ctrl->irq] = p_info;
-
-    /* Enable read skip after all settings are written. */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_ENABLE;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Configure the length setting for block and repeat mode.
- **********************************************************************************************************************/
-static void r_dtc_block_repeat_initialize (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        /* Update the CRA register to the desired settings */
-        if (TRANSFER_MODE_NORMAL != p_info[i].transfer_settings_word_b.mode)
-        {
-            uint8_t CRAL = p_info[i].length & DTC_PRV_MASK_CRAL;
-            p_info[i].length = (uint16_t) ((CRAL << DTC_PRV_OFFSET_CRAH) | CRAL);
-        }
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); /* Increment 'i' after checking. */
-}
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-
- #if BSP_CFG_ASSERT != 3
-
-/*******************************************************************************************************************//**
- * Check to make sure that the length is valid for block and repeat mode.
- *
- * @retval FSP_SUCCESS              Parameters are valid.
- * @retval FSP_ERR_ASSERTION        Invalid length for block or repeat mode.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- *
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_length_assert (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.src_addr_mode,
-                         FSP_ERR_UNSUPPORTED);
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.dest_addr_mode,
-                         FSP_ERR_UNSUPPORTED);
-
-        if (TRANSFER_MODE_NORMAL != p_info[i].transfer_settings_word_b.mode)
-        {
-            /* transfer_length_max is the same for Block and repeat mode. */
-            FSP_ASSERT(p_info[i].length <= DTC_MAX_REPEAT_TRANSFER_LENGTH);
-        }
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); /* Increment 'i' after checking. */
-
-    return FSP_SUCCESS;
-}
-
- #endif
-
-/*******************************************************************************************************************//**
- * Check that the source and destination are not NULL and that they are aligned correctly.
- *
- * @retval FSP_SUCCESS              Parameters are valid.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- *
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_source_destination_parameter_check (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.src_addr_mode,
-                         FSP_ERR_UNSUPPORTED);
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.dest_addr_mode,
-                         FSP_ERR_UNSUPPORTED);
-        FSP_ASSERT(NULL != p_info[i].p_src);
-        FSP_ASSERT(NULL != p_info[i].p_dest);
-        FSP_ASSERT(0U ==
-                   ((uint32_t) p_info[i].p_dest & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].transfer_settings_word_b.size)));
-        FSP_ASSERT(0U ==
-                   ((uint32_t) p_info[i].p_src & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].transfer_settings_word_b.size)));
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); /* Increment 'i' after checking. */
-
-    return FSP_SUCCESS;
-}
-
-#endif

bsp/renesas/ra4m2-eco/ra/fsp/src/r_sci_spi/r_sci_spi.c

@@ -1,1019 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include <string.h>
-#include "r_sci_spi.h"
-#include "r_sci_spi_cfg.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-#define SCI_SPI_PRV_SCMR_RESERVED_MASK          (0x62U)
-
-#define SCI_SPI_PRV_DTC_RX_TRANSFER_SETTINGS    ((TRANSFER_MODE_NORMAL << 30U) | (TRANSFER_SIZE_1_BYTE << 28U) | \
-                                                 (TRANSFER_ADDR_MODE_FIXED << 26U) | (TRANSFER_IRQ_END << 21U) | \
-                                                 (TRANSFER_ADDR_MODE_INCREMENTED << 18U))
-
-#define SCI_SPI_PRV_DTC_TX_TRANSFER_SETTINGS    ((TRANSFER_MODE_NORMAL << 30U) | (TRANSFER_SIZE_1_BYTE << 28U) |       \
-                                                 (TRANSFER_ADDR_MODE_INCREMENTED << 26U) | (TRANSFER_IRQ_END << 21U) | \
-                                                 (TRANSFER_ADDR_MODE_FIXED << 18U))
-
-#define SCI_SPI_PRV_CLK_MIN_DIV                 (4U)
-#define SCI_SPI_PRV_CLK_MAX_DIV                 ((UINT16_MAX + 1U) * 2U)
-
-/** "SCIS" in ASCII, used to determine if channel is open. */
-#define SCI_SPI_OPEN                            (0x53434953ULL)
-
-/***********************************************************************************************************************
- * Private global variables.
- **********************************************************************************************************************/
-
-const spi_api_t g_spi_on_sci =
-{
-    .open        = R_SCI_SPI_Open,
-    .read        = R_SCI_SPI_Read,
-    .write       = R_SCI_SPI_Write,
-    .writeRead   = R_SCI_SPI_WriteRead,
-    .close       = R_SCI_SPI_Close,
-    .callbackSet = R_SCI_SPI_CallbackSet
-};
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * sci_spi_prv_ns_callback)(spi_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_spi_prv_ns_callback)(spi_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private function declarations.
- **********************************************************************************************************************/
-
-static void r_sci_spi_hw_config(sci_spi_instance_ctrl_t * const p_ctrl);
-
-#if SCI_SPI_DTC_SUPPORT_ENABLE == 1
-static fsp_err_t r_sci_spi_transfer_config(sci_spi_instance_ctrl_t * const p_ctrl);
-
-#endif
-static fsp_err_t r_sci_spi_write_read_common(sci_spi_instance_ctrl_t * const p_ctrl,
-                                             void const                    * p_src,
-                                             void                          * p_dest,
-                                             uint32_t const                  length);
-static void r_sci_spi_start_transfer(sci_spi_instance_ctrl_t * const p_ctrl);
-static void r_sci_spi_transmit(sci_spi_instance_ctrl_t * p_ctrl);
-static void r_sci_spi_call_callback(sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event);
-
-void sci_spi_txi_isr(void);
-void sci_spi_rxi_isr(void);
-void sci_spi_tei_isr(void);
-void sci_spi_eri_isr(void);
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup SCI_SPI
- * @{
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Initialize a channel for SPI communication mode. Implements @ref spi_api_t::open.
- *
- * This function performs the following tasks:
- *   - Performs parameter checking and processes error conditions.
- *   - Enables the clock for the SCI channel.
- *   - Initializes the associated registers with default value and the user-configurable options.
- *   - Provides the channel handle for use with other API functions.
- *
- * @param      p_api_ctrl                      Pointer to the control structure.
- * @param      p_cfg                           Pointer to a configuration structure.
- *
- * @retval     FSP_SUCCESS                     Channel initialized successfully.
- * @retval     FSP_ERR_ASSERTION               An input parameter is invalid or NULL.
- * @retval     FSP_ERR_ALREADY_OPEN            The instance has already been opened.
- * @retval     FSP_ERR_IP_CHANNEL_NOT_PRESENT  The channel number is invalid.
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-    fsp_err_t                 err    = FSP_SUCCESS;
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SCI_SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ASSERT(NULL != p_cfg->p_extend);
-    FSP_ASSERT(NULL != p_cfg->p_callback);
-    FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
-    FSP_ASSERT(p_cfg->rxi_irq >= 0);
-    FSP_ASSERT(p_cfg->txi_irq >= 0);
-    FSP_ASSERT(p_cfg->tei_irq >= 0);
-    FSP_ASSERT(p_cfg->eri_irq >= 0);
-#endif
-
-    p_ctrl->p_reg = (R_SCI0_Type *) ((R_SCI1_BASE - R_SCI0_BASE) * p_cfg->channel + R_SCI0_BASE);
-    p_ctrl->p_cfg = p_cfg;
-
-    p_ctrl->p_callback        = p_cfg->p_callback;
-    p_ctrl->p_context         = p_cfg->p_context;
-    p_ctrl->p_callback_memory = NULL;
-
-#if SCI_SPI_DTC_SUPPORT_ENABLE == 1
-
-    /* Open the SCI SPI transfer interface if available. */
-    err = r_sci_spi_transfer_config(p_ctrl);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
-    /* Write user configuration to registers. */
-    r_sci_spi_hw_config(p_ctrl);
-
-    /* Enable required interrupts. */
-    R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl);
-    R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl);
-    R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->tei_ipl, p_ctrl);
-    R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl);
-
-    p_ctrl->open = SCI_SPI_OPEN;
-
-    return err;
-}
-
-/*******************************************************************************************************************//**
- * Receive data from an SPI device. Implements @ref spi_api_t::read.
- *
- * The function performs the following tasks:
- *   - Performs parameter checking and processes error conditions.
- *   - Enable transmitter.
- *   - Enable receiver.
- *   - Enable interrupts.
- *   - Start data transmission by writing data to the TXD register.
- *   - Receive data from receive buffer full interrupt occurs and copy data to the buffer of destination.
- *   - Complete data reception via receive buffer full interrupt and transmitting dummy data.
- *   - Disable transmitter.
- *   - Disable receiver.
- *   - Disable interrupts.
- *
- * @param      p_api_ctrl           Pointer to the control structure.
- * @param      p_dest               Pointer to the destination buffer.
- * @param[in]  length               The number of bytes to transfer.
- * @param[in]  bit_width            Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).
- *
- * @retval     FSP_SUCCESS          Read operation successfully completed.
- * @retval     FSP_ERR_ASSERTION    One of the following invalid parameters passed:
- *                                  - Pointer p_api_ctrl is NULL
- *                                  - Bit width is not 8 bits
- *                                  - Length is equal to 0
- *                                  - Pointer to destination is NULL
- * @retval     FSP_ERR_NOT_OPEN     The channel has not been opened. Open the channel first.
- * @retval     FSP_ERR_UNSUPPORTED  The given bit_width is not supported.
- * @retval     FSP_ERR_IN_USE       A transfer is already in progress.
- *
- * @return     See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This
- *             function calls:
- *               - @ref transfer_api_t::reconfigure
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_Read (spi_ctrl_t * const    p_api_ctrl,
-                          void                * p_dest,
-                          uint32_t const        length,
-                          spi_bit_width_t const bit_width)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-
-    /* Check bit_width parameter, in simple SPI, only 8 bits operation is allowed. */
-    FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED);
-
-    /* Check the destination, should not be NULL. */
-    FSP_ASSERT(NULL != p_dest);
-#else
-    FSP_PARAMETER_NOT_USED(bit_width);
-#endif
-
-    return r_sci_spi_write_read_common(p_ctrl, NULL, p_dest, length);
-}
-
-/*******************************************************************************************************************//**
- * Transmit data to a SPI  device. Implements @ref spi_api_t::write.
- *
- * The function performs the following tasks:
- *   - Performs parameter checking and processes error conditions.
- *   - Enable transmitter.
- *   - Enable interrupts.
- *   - Start data transmission with data via transmit buffer empty interrupt.
- *   - Copy data from source buffer to the SPI data register for transmission.
- *   - Complete data transmission via transmit buffer empty interrupt.
- *   - Disable transmitter.
- *   - Disable receiver.
- *   - Disable interrupts.
- *
- * @param      p_api_ctrl           Pointer to the control structure.
- * @param      p_src                Pointer to the source buffer.
- * @param[in]  length               The number of bytes to transfer.
- * @param[in]  bit_width            Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).
- *
- * @retval     FSP_SUCCESS          Write operation successfully completed.
- * @retval     FSP_ERR_ASSERTION    One of the following invalid parameters passed:
- *                                  - Pointer p_api_ctrl is NULL
- *                                  - Pointer to source is NULL
- *                                  - Length is equal to 0
- *                                  - Bit width is not equal to 8 bits
- * @retval     FSP_ERR_NOT_OPEN     The channel has not been opened. Open the channel first.
- * @retval     FSP_ERR_UNSUPPORTED  The given bit_width is not supported.
- * @retval     FSP_ERR_IN_USE       A transfer is already in progress.
- *
- * @return     See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This
- *             function calls:
- *               - @ref transfer_api_t::reconfigure
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_Write (spi_ctrl_t * const    p_api_ctrl,
-                           void const          * p_src,
-                           uint32_t const        length,
-                           spi_bit_width_t const bit_width)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED);
-    FSP_ASSERT(NULL != p_src);
-#else
-    FSP_PARAMETER_NOT_USED(bit_width);
-#endif
-
-    return r_sci_spi_write_read_common(p_ctrl, p_src, NULL, length);
-}
-
-/*******************************************************************************************************************//**
- * Simultaneously transmit data to SPI device while receiving data from SPI device (full duplex).
- * Implements @ref spi_api_t::writeRead.
- *
- * The function performs the following tasks:
- *   - Performs parameter checking and processes error conditions.
- *   - Enable transmitter.
- *   - Enable receiver.
- *   - Enable interrupts.
- *   - Start data transmission using transmit buffer empty interrupt (or by writing to the TDR register).
- *   - Copy data from source buffer to the SPI data register for transmission.
- *   - Receive data from receive buffer full interrupt and copy data to the destination buffer.
- *   - Complete data transmission and reception via transmit end interrupt.
- *   - Disable transmitter.
- *   - Disable receiver.
- *   - Disable interrupts.
- *
- * @param      p_api_ctrl           Pointer to the control structure.
- * @param      p_src                Pointer to the source buffer.
- * @param      p_dest               Pointer to the destination buffer.
- * @param[in]  length               The number of bytes to transfer.
- * @param[in]  bit_width            Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).
- *
- * @retval     FSP_SUCCESS          Write operation successfully completed.
- * @retval     FSP_ERR_ASSERTION    One of the following invalid parameters passed:
- *                                  - Pointer p_api_ctrl is NULL
- *                                  - Pointer to source is NULL
- *                                  - Pointer to destination is NULL
- *                                  - Length is equal to 0
- *                                  - Bit width is not equal to 8 bits
- * @retval     FSP_ERR_NOT_OPEN     The channel has not been opened. Open the channel first.
- * @retval     FSP_ERR_UNSUPPORTED  The given bit_width is not supported.
- * @retval     FSP_ERR_IN_USE       A transfer is already in progress.
- *
- * @return     See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This
- *             function calls:
- *               - @ref transfer_api_t::reconfigure
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_WriteRead (spi_ctrl_t * const    p_api_ctrl,
-                               void const          * p_src,
-                               void                * p_dest,
-                               uint32_t const        length,
-                               spi_bit_width_t const bit_width)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED);
-    FSP_ASSERT(NULL != p_src);
-    FSP_ASSERT(NULL != p_dest);
-#else
-    FSP_PARAMETER_NOT_USED(bit_width);
-#endif
-
-    return r_sci_spi_write_read_common(p_ctrl, p_src, p_dest, length);
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback and has option of providing memory for callback structure.
- * Implements spi_api_t::callbackSet
- *
- * @retval  FSP_SUCCESS                  Callback updated successfully.
- * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
- * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
- * @retval  FSP_ERR_NO_CALLBACK_MEMORY   p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_CallbackSet (spi_ctrl_t * const          p_api_ctrl,
-                                 void (                    * p_callback)(spi_callback_args_t *),
-                                 void const * const          p_context,
-                                 spi_callback_args_t * const p_callback_memory)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-
-#if (SCI_SPI_CFG_PARAM_CHECKING_ENABLE)
-    FSP_ASSERT(p_ctrl);
-    FSP_ASSERT(p_callback);
-    FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* Get security state of p_callback */
-    bool callback_is_secure =
-        (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-
- #if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-
-    /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
-    spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
-                                                                                      CMSE_AU_NONSECURE);
-    FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-#endif
-
-    /* Store callback and context */
-#if BSP_TZ_SECURE_BUILD
-    p_ctrl->p_callback = callback_is_secure ? p_callback :
-                         (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
-    p_ctrl->p_callback = p_callback;
-#endif
-    p_ctrl->p_context         = p_context;
-    p_ctrl->p_callback_memory = p_callback_memory;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disable the SCI channel and set the instance as not open. Implements @ref spi_api_t::close.
- *
- * @param      p_api_ctrl         Pointer to an opened instance.
- *
- * @retval     FSP_SUCCESS        Channel successfully closed.
- * @retval     FSP_ERR_ASSERTION  The parameter p_api_ctrl is NULL.
- * @retval     FSP_ERR_NOT_OPEN   The channel has not been opened. Open the channel first.
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_Close (spi_ctrl_t * const p_api_ctrl)
-{
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Clear the RE and TE bits in SCR. */
-    p_ctrl->p_reg->SCR = 0;
-
-    R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq);
-
-    /* Disable the clock to the SCI channel. */
-    R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel);
-
-    if (NULL != p_ctrl->p_cfg->p_transfer_rx)
-    {
-        p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl);
-    }
-
-    if (NULL != p_ctrl->p_cfg->p_transfer_tx)
-    {
-        p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl);
-    }
-
-    p_ctrl->open = 0U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Calculate the register settings required to achieve the desired bitrate.
- *
- * @param[in]  bitrate            bitrate [bps]. For example, 250,000; 500,00; 2,500,000 (max), etc.
- * @param      sclk_div           Pointer to sci_spi_div_setting_t used to configure baudrate settings.
- * @param[in]  use_mddr           Calculate the divider settings for use with MDDR.
- *
- * @retval     FSP_SUCCESS        Baud rate is set successfully.
- * @retval     FSP_ERR_ASSERTION  Baud rate is not achievable.
- * @note       The application must pause for 1 bit time after the BRR register is loaded before transmitting/receiving
- *             to allow time for the clock to settle.
- **********************************************************************************************************************/
-fsp_err_t R_SCI_SPI_CalculateBitrate (uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr)
-{
-    uint32_t peripheral_clock = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK);
-
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != sclk_div);
-    FSP_ASSERT(bitrate);
-    FSP_ASSERT(bitrate >= (peripheral_clock + SCI_SPI_PRV_CLK_MAX_DIV - 1U) / SCI_SPI_PRV_CLK_MAX_DIV);
-#endif
-
-    int32_t divisor = 0;
-    int32_t brr     = 0;
-    int32_t cks     = -1;
-
-    for (uint32_t i = 0; i <= 3; i++)
-    {
-        cks++;
-        divisor = (1 << (2 * (i + 1))) * (int32_t) bitrate;
-
-        /* Calculate BRR so that the bit rate is the largest possible value less than or equal to the desired
-         * bitrate. */
-        brr = ((int32_t) peripheral_clock + divisor - 1) / divisor - 1;
-
-        if (brr <= UINT8_MAX)
-        {
-            break;
-        }
-    }
-
-    /* If mddr is not used, set it to 0. */
-    int64_t mddr = 0;
-
-    if (use_mddr)
-    {
-        /* Calculate BRR by rounding down. */
-        brr = (int32_t) peripheral_clock / divisor - 1;
-
-        /*
-         * If a bit rate greater than the max possible bit rate is passed in, this
-         * calculation will be negative.
-         */
-        if (brr < 0)
-        {
-            brr = 0;
-        }
-
-        /* In the most extreme case this will result in a bit rate that is ~2 times the
-         * desired bitrate (This will be compensated for by setting MDDR).
-         */
-        if (brr > UINT8_MAX)
-        {
-            brr = UINT8_MAX;
-        }
-
-        /* The maximum result of this calculation is 256 which occurs when the exact bitrate can be achieved without
-         * using mddr (promote to 64 bit so the intermediate calculation does not overflow). */
-        mddr = (int64_t) divisor * (brr + 1) * (UINT8_MAX + 1) / peripheral_clock;
-
-        if (mddr > UINT8_MAX)
-        {
-            /* Set MDDR to 0 to disable it. */
-            mddr = 0;
-        }
-    }
-
-    sclk_div->brr  = (uint8_t) brr;
-    sclk_div->cks  = (uint8_t) (cks & 3);
-    sclk_div->mddr = (uint8_t) mddr;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup SCI_SPI)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configures SCI registers based on the user configuration.
- * @param      p_ctrl          Pointer to control structure.
- **********************************************************************************************************************/
-static void r_sci_spi_hw_config (sci_spi_instance_ctrl_t * const p_ctrl)
-{
-    spi_cfg_t const        * p_cfg    = p_ctrl->p_cfg;
-    sci_spi_extended_cfg_t * p_extend = (sci_spi_extended_cfg_t *) p_cfg->p_extend;
-
-    /* Initialize registers to their reset values. */
-    uint32_t smr  = R_SCI0_SMR_CM_Msk;
-    uint32_t scr  = 0;
-    uint32_t scmr = (2U << R_SCI0_SCMR_CHR1_Pos) | R_SCI0_SCMR_BCP2_Msk | SCI_SPI_PRV_SCMR_RESERVED_MASK;
-    uint32_t spmr = 0U;
-    uint32_t mddr = UINT8_MAX;
-    uint32_t semr = 0;
-
-    /* Select the baud rate generator clock divider. */
-    smr |= (uint32_t) (p_extend->clk_div.cks << R_SCI0_SMR_CKS_Pos);
-
-    if (p_extend->clk_div.mddr > INT8_MAX)
-    {
-        /* If a valid MDDR setting is given than enable MDDR. */
-        semr |= R_SCI0_SEMR_BRME_Msk;
-        mddr  = p_extend->clk_div.mddr;
-    }
-
-    if (SPI_MODE_SLAVE == p_cfg->operating_mode)
-    {
-        /* Select slave mode. */
-        spmr |= R_SCI0_SPMR_MSS_Msk;
-
-        /* Select to use SSLn input pin */
-        spmr |= R_SCI0_SPMR_SSE_Msk;
-
-        /* Use external clock for baud rate (Default is on-chip baud rate generator). */
-        scr |= (2U << R_SCI0_SCR_CKE_Pos);
-    }
-
-    if (SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase)
-    {
-        /* In order to get sampling on the even clock edge (CPHA = 1) set SPMR.CKPH to 0. */
-        if (SPI_CLK_POLARITY_LOW == p_cfg->clk_polarity)
-        {
-            /* If SPMR.CKPH is set to 0 then CKPOL must be set to 1 to make the clock low during idle (CPOL = 0).
-             * See Figure 34.70 in the RA6M3 manual R01UH0886EJ0100. */
-            spmr |= R_SCI0_SPMR_CKPOL_Msk;
-        }
-    }
-    else
-    {
-        /* In order to get sampling on the ODD edge (CPHA = 0) set SPMR.CKPH to 1. */
-        spmr |= R_SCI0_SPMR_CKPH_Msk;
-
-        if (SPI_CLK_POLARITY_HIGH == p_cfg->clk_polarity)
-        {
-            /* If SPMR.CKPH is set to 1 then CKPOL must be set to 1 to make the clock high during idle (CPOL = 1).
-             * See Figure 34.70 in the RA6M3 manual R01UH0886EJ0100. */
-            spmr |= R_SCI0_SPMR_CKPOL_Msk;
-        }
-    }
-
-    if (SPI_BIT_ORDER_MSB_FIRST == p_cfg->bit_order)
-    {
-        /* Configure MSB first (Default is LSB). */
-        scmr |= R_SCI0_SCMR_SDIR_Msk;
-    }
-
-    /* Enable Clock for the SCI Channel. */
-    R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel);
-
-    /* Clear the RE and TE bits before writing other settings. See section 34.2 Register Descriptions in the
-     * RA6M3 manual R01UH0886EJ0100. */
-    p_ctrl->p_reg->SCR = 0;
-
-    /* Must read SSR in order to clear the RX overflow error. Reference section 34.2.13 Serial Status Register (SSR)
-     * in the RA6M3 manual R01UH0886EJ0100.*/
-    p_ctrl->p_reg->SSR;
-
-    /* Clear the error status flags. */
-    p_ctrl->p_reg->SSR = (uint8_t) (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk);
-
-    /* Disable fifo mode. See Figure 34.32 Example flow of SCI initialization in clock synchronous mode with non-FIFO
-     * selected in the RA6M3 manual R01UH0886EJ0100. */
-    p_ctrl->p_reg->FCR = R_SCI0_FCR_RSTRG_Msk | (8U << R_SCI0_FCR_RTRG_Pos);
-
-    /* Write settings to registers. */
-    p_ctrl->p_reg->SMR  = (uint8_t) smr;
-    p_ctrl->p_reg->SCR  = (uint8_t) scr;
-    p_ctrl->p_reg->SCMR = (uint8_t) scmr;
-    p_ctrl->p_reg->BRR  = p_extend->clk_div.brr;
-    p_ctrl->p_reg->MDDR = (uint8_t) mddr;
-    p_ctrl->p_reg->SEMR = (uint8_t) semr;
-    p_ctrl->p_reg->SPMR = (uint8_t) spmr;
-
-    /* Set unused registers to their value after reset. */
-    p_ctrl->p_reg->SNFR  = 0;
-    p_ctrl->p_reg->SIMR1 = 0;
-    p_ctrl->p_reg->SIMR2 = 0;
-    p_ctrl->p_reg->SIMR3 = 0;
-    p_ctrl->p_reg->CDR   = 0;
-    p_ctrl->p_reg->DCCR  = R_SCI0_DCCR_IDSEL_Msk;
-    p_ctrl->p_reg->SPTR  = R_SCI0_SPTR_SPB2DT_Msk;
-}
-
-#if SCI_SPI_DTC_SUPPORT_ENABLE == 1
-
-/*******************************************************************************************************************//**
- * Configures SCI SPI related transfer drivers (if enabled).
- *
- * @param[in]     p_cfg                     Pointer to SCI SPI specific configuration structure.
- * @param[in]     p_fsp_feature             FSP feature.
- *
- * @retval        FSP_SUCCESS               Operation successfully completed.
- * @retval        FSP_ERR_ASSERTION         One of the following invalid parameters passed:
- *                                          - Pointer p_cfg is NULL
- *                                          - Interrupt is not enabled
- * @retval        FSP_ERR_INVALID_ARGUMENT  DTC is used for data transmission but not used for data reception or
- *                                          vice versa.
- **********************************************************************************************************************/
-static fsp_err_t r_sci_spi_transfer_config (sci_spi_instance_ctrl_t * const p_ctrl)
-{
-    fsp_err_t               err   = FSP_SUCCESS;
-    spi_cfg_t const * const p_cfg = p_ctrl->p_cfg;
-
-    if (NULL != p_cfg->p_transfer_rx)
-    {
-        /* Set the initial configuration for the rx transfer instance. */
-        transfer_instance_t const * p_transfer = p_cfg->p_transfer_rx;
-        p_transfer->p_cfg->p_info->transfer_settings_word = SCI_SPI_PRV_DTC_RX_TRANSFER_SETTINGS;
-        p_transfer->p_cfg->p_info->p_src = (void *) &p_ctrl->p_reg->RDR;
-
-        /* Open the transfer instance. */
-        err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-
-    if (NULL != p_cfg->p_transfer_tx)
-    {
-        /* Set the initial configuration for the tx transfer instance. */
-        transfer_instance_t const * p_transfer = p_cfg->p_transfer_tx;
-        p_transfer->p_cfg->p_info->transfer_settings_word = SCI_SPI_PRV_DTC_TX_TRANSFER_SETTINGS;
-        p_transfer->p_cfg->p_info->p_dest                 = (void *) &p_ctrl->p_reg->TDR;
-
-        /* Open the transfer instance. */
-        err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
-        if (FSP_SUCCESS != err)
-        {
-            if (NULL != p_cfg->p_transfer_rx)
-            {
-                /* If the tx transfer instance could not be opened, close the rx transfer instance. */
-                p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl);
-            }
-
-            return err;
-        }
-    }
-
-    return err;
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * Initiates writ or read process. Common routine used by SPI API write or read functions.
- *
- * @param[in]  p_ctrl             Pointer to the control block.
- * @param[in]  p_src              Pointer to data buffer which need to be sent.
- * @param[out] p_dest             Pointer to buffer where received data will be stored.
- * @param[in]  length             Number of data transactions to be performed.
- *
- * @retval     FSP_SUCCESS        Operation successfully completed.
- * @retval     FSP_ERR_NOT_OPEN   The channel has not been opened. Open the channel first.
- * @retval     FSP_ERR_ASSERTION  One of the following invalid parameters passed:
- *                                  - Pointer p_ctrl is NULL
- *                                  - length == 0
- *                                  - if DTC is used and length > UINT16_MAX
- * @retval     FSP_ERR_IN_USE     A transfer is already in progress.
- *
- * @return     See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This
- *             function calls:
- *               - @ref transfer_api_t::reconfigure
- **********************************************************************************************************************/
-static fsp_err_t r_sci_spi_write_read_common (sci_spi_instance_ctrl_t * const p_ctrl,
-                                              void const                    * p_src,
-                                              void                          * p_dest,
-                                              uint32_t const                  length)
-{
-#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(0 != length);
-    if ((NULL != p_ctrl->p_cfg->p_transfer_tx) || (NULL != p_ctrl->p_cfg->p_transfer_rx))
-    {
-        /* The DTC is only capable of a max of 64K transfers. */
-        FSP_ASSERT(length <= UINT16_MAX);
-    }
-#endif
-
-    /* TE and RE must be zero in order to write one to TE or RE (TE and RE will only be set if there is a transfer in
-     * progress. Reference section 34.2.11 Serial Control Register (SCR) in the RA6M3 manual R01UH0886EJ0100. */
-    FSP_ERROR_RETURN(0 == (p_ctrl->p_reg->SCR & (R_SCI0_SCR_RE_Msk | R_SCI0_SCR_TE_Msk)), FSP_ERR_IN_USE);
-
-    /* Setup the control block. */
-    p_ctrl->count    = length;
-    p_ctrl->tx_count = 0U;
-    p_ctrl->rx_count = 0U;
-    p_ctrl->p_src    = (uint8_t *) p_src;
-    p_ctrl->p_dest   = (uint8_t *) p_dest;
-
-#if SCI_SPI_DTC_SUPPORT_ENABLE == 1
-    if (p_ctrl->p_cfg->p_transfer_tx)
-    {
-        /* Configure the tx transfer instance. */
-        p_ctrl->tx_count = length;
-        transfer_instance_t const * p_transfer = p_ctrl->p_cfg->p_transfer_tx;
-        p_transfer->p_cfg->p_info->length = (uint16_t) length;
-
-        if (NULL == p_src)
-        {
-            /* If the source is NULL transmit using a dummy value using FIXED mode. */
-            static uint8_t tx_dummy = 0;
-            p_transfer->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED;
-            p_transfer->p_cfg->p_info->p_src = &tx_dummy;
-        }
-        else
-        {
-            p_transfer->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
-            p_transfer->p_cfg->p_info->p_src = p_src;
-        }
-
-        /* Enable the transfer instance. */
-        fsp_err_t err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_transfer->p_cfg->p_info);
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-
-    /* The rx transfer instance is not used if p_dest is NULL. */
-    if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (NULL != p_dest))
-    {
-        /* Configure the rx transfer instance. */
-        p_ctrl->rx_count = length;
-        transfer_instance_t const * p_transfer = p_ctrl->p_cfg->p_transfer_rx;
-
-        /* Enable the transfer instance. */
-        fsp_err_t err = p_transfer->p_api->reset(p_transfer->p_ctrl, NULL, p_dest, (uint16_t) length);
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-#endif
-
-    /* Enable transmit and receive interrupts. */
-    r_sci_spi_start_transfer(p_ctrl);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enables and disables Receive and Transmit mode based on the current configuration.
- *
- * @param      p_ctrl          Pointer to control structure.
- **********************************************************************************************************************/
-static void r_sci_spi_start_transfer (sci_spi_instance_ctrl_t * const p_ctrl)
-{
-    /* TE must always be enabled even when receiving data. When RE is enabled without also enabling TE, the SCI will
-     * continue transfering data until the RE bit is cleared. At high bitrates, it is not possible to clear the RE bit
-     * fast enough and there will be additional clock pulses at the end of the transfer. */
-    uint32_t interrupt_settings = R_SCI0_SCR_TE_Msk;
-
-    if ((NULL == p_ctrl->p_dest) || (NULL != p_ctrl->p_cfg->p_transfer_tx) || (NULL != p_ctrl->p_cfg->p_transfer_rx))
-    {
-        /* Enable the transmit IRQ. */
-        interrupt_settings |= R_SCI0_SCR_TIE_Msk;
-    }
-
-    if (NULL != p_ctrl->p_dest)
-    {
-        /* Enable Receive mode and the Receive buffer full IRQ. */
-        interrupt_settings |= (R_SCI0_SCR_RE_Msk | R_SCI0_SCR_RIE_Msk);
-    }
-
-    /* Write the transfer settings. */
-    p_ctrl->p_reg->SCR |= (uint8_t) interrupt_settings;
-
-    /* Transmit from RXI interrupt. */
-    if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (NULL == p_ctrl->p_cfg->p_transfer_rx) && (NULL != p_ctrl->p_dest))
-    {
-        /* The rxi interrupt must be disabled so that r_sci_spi_transmit is not interrupted before it updates the
-         * tx_count. */
-        R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq);
-
-        /* When transmitting from the RXI interrupt, the first byte must be written here because the transmit buffer
-         * empty IRQ is disabled. */
-        r_sci_spi_transmit(p_ctrl);
-
-        if ((SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode) && (1 < p_ctrl->count))
-        {
-            /* First call writes directly to the TSR register. The second call writes to the TDR register. */
-            r_sci_spi_transmit(p_ctrl);
-        }
-
-        /* In master mode the rxi interrupt will fire as soon as it is enabled. */
-        R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq);
-    }
-}
-
-/*******************************************************************************************************************//**
- * Transmit a single byte of data.
- * @param      p_ctrl          Pointer to the control structure.
- **********************************************************************************************************************/
-static void r_sci_spi_transmit (sci_spi_instance_ctrl_t * p_ctrl)
-{
-    if (p_ctrl->tx_count < p_ctrl->count)
-    {
-        if (p_ctrl->p_src)
-        {
-            p_ctrl->p_reg->TDR = p_ctrl->p_src[p_ctrl->tx_count];
-        }
-        else
-        {
-            /* Do a dummy write if there is no tx buffer. */
-            p_ctrl->p_reg->TDR = 0;
-        }
-
-        p_ctrl->tx_count++;
-    }
-}
-
-/*******************************************************************************************************************//**
- * Calls user callback.
- *
- * @param[in]     p_ctrl     Pointer to SPI instance control block
- * @param[in]     event      Event code
- **********************************************************************************************************************/
-static void r_sci_spi_call_callback (sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event)
-{
-    spi_callback_args_t args;
-
-    /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
-     * stored in non-secure memory so they can be accessed by a non-secure callback function. */
-    spi_callback_args_t * p_args = p_ctrl->p_callback_memory;
-    if (NULL == p_args)
-    {
-        /* Store on stack */
-        p_args = &args;
-    }
-    else
-    {
-        /* Save current arguments on the stack in case this is a nested interrupt. */
-        args = *p_args;
-    }
-
-    p_args->channel   = p_ctrl->p_cfg->channel;
-    p_args->event     = event;
-    p_args->p_context = p_ctrl->p_context;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* p_callback can point to a secure function or a non-secure function. */
-    if (!cmse_is_nsfptr(p_ctrl->p_callback))
-    {
-        /* If p_callback is secure, then the project does not need to change security state. */
-        p_ctrl->p_callback(p_args);
-    }
-    else
-    {
-        /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
-        sci_spi_prv_ns_callback p_callback = (sci_spi_prv_ns_callback) (p_ctrl->p_callback);
-        p_callback(p_args);
-    }
-
-#else
-
-    /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
-    p_ctrl->p_callback(p_args);
-#endif
-    if (NULL != p_ctrl->p_callback_memory)
-    {
-        /* Restore callback memory in case this is a nested interrupt. */
-        *p_ctrl->p_callback_memory = args;
-    }
-}
-
-/*******************************************************************************************************************//**
- * This function is the ISR handler for R_SCI_SPI Transmit Buffer Empty IRQ.
- *
- * The Transmit Buffer Empty IRQ is enabled in the following conditions:
- *   - The transfer is started using R_SCI_SPI_Write API (There is no data to receive).
- *   - The rxi IRQ is serviced using a DTC instance.
- *   - The txi IRQ is serviced using a DTC instance (The interrupt will fire on the last byte transfered).
- *
- **********************************************************************************************************************/
-void sci_spi_txi_isr (void)
-{
-    /* Save context if RTOS is used. */
-    FSP_CONTEXT_SAVE;
-    IRQn_Type irq = R_FSP_CurrentIrqGet();
-    R_BSP_IrqStatusClear(irq);
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    /* Write the next byte to the TDR register. */
-    r_sci_spi_transmit(p_ctrl);
-
-    if ((p_ctrl->tx_count == p_ctrl->count) && (NULL == p_ctrl->p_dest))
-    {
-        /* If the last byte is transmitted and there is no data to receive then enable the transmit end IRQ and disable
-         * the transmit IRQ. */
-        p_ctrl->p_reg->SCR = (uint8_t) ((p_ctrl->p_reg->SCR & ~R_SCI0_SCR_TIE_Msk) | R_SCI0_SCR_TEIE_Msk);
-    }
-
-    /* Restore context if RTOS is used. */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * This function is the ISR handler for R_SCI_SPI Receive Buffer Full IRQ.
- * This handler also handles Transmit Buffer Empty IRQs.
- *
- * The Receive Buffer Full IRQ is enabled in the following conditions:
- *   - The transfer is started using either the R_SCI_SPI_Read or R_SCI_SPI_WriteRead API.
- *
- **********************************************************************************************************************/
-void sci_spi_rxi_isr (void)
-{
-    /* Save context if RTOS is used. */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type irq = R_FSP_CurrentIrqGet();
-    R_BSP_IrqStatusClear(irq);
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    /* Write the next byte to the TDR register
-     * (Whenever the rxi isr is enabled, the transmit isr is disabled and transmit is handled here). */
-    r_sci_spi_transmit(p_ctrl);
-
-    /* Read the next byte from the RDR register. */
-    if (p_ctrl->rx_count < p_ctrl->count)
-    {
-        p_ctrl->p_dest[p_ctrl->rx_count++] = p_ctrl->p_reg->RDR;
-    }
-
-    if (p_ctrl->rx_count == p_ctrl->count)
-    {
-        /* If the last byte is received then enable the transmit end IRQ and disable the receive and transmit IRQs. */
-        p_ctrl->p_reg->SCR =
-            (uint8_t) ((p_ctrl->p_reg->SCR & ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_RIE_Msk)) | R_SCI0_SCR_TEIE_Msk);
-    }
-
-    /* Restore context if RTOS is used. */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * This function is the ISR handler for R_SCI_SPI Transmit End IRQ.
- *
- * The Transmit End IRQ is enabled after the last byte of data has been transfered.
- *
- **********************************************************************************************************************/
-void sci_spi_tei_isr (void)
-{
-    /* Save context if RTOS is used. */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type                 irq    = R_FSP_CurrentIrqGet();
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    /* Disables receiver, transmitter and transmit end IRQ. */
-    p_ctrl->p_reg->SCR &= (uint8_t) R_SCI0_SCR_CKE_Msk;
-
-    /* Notify the user that the transfer has completed. */
-    r_sci_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE);
-
-    R_BSP_IrqStatusClear(irq);
-
-    /* Restore context if RTOS is used. */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * This function is the ISR handler for  R_SCI_SPI Error IRQs.
- *
- * This handler is only enabled if the user passes in a valid IRQ number in Pointer to a configuration structure.
- * structure.
- **********************************************************************************************************************/
-void sci_spi_eri_isr (void)
-{
-    /* Save context if RTOS is used. */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type                 irq    = R_FSP_CurrentIrqGet();
-    sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    /* Disables receiver, transmitter and transmit end IRQ. */
-    p_ctrl->p_reg->SCR &= (uint8_t) R_SCI0_SCR_CKE_Msk;
-
-    /* Must read SSR in order to clear the RX overflow error. Reference section 34.2.13 Serial Status Register (SSR)
-     * in the RA6M3 manual R01UH0886EJ0100.*/
-    p_ctrl->p_reg->SSR;
-
-    /* Clear the error status flags (The only possible error is an RX overflow). */
-    p_ctrl->p_reg->SSR = (uint8_t) (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk);
-
-    /* Notify the user that an error occurred. */
-    r_sci_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW);
-
-    /* Clear pending IRQ to make sure it doesn't fire again after exiting. */
-    R_BSP_IrqStatusClear(irq);
-
-    /* Restore context if RTOS is used. */
-    FSP_CONTEXT_RESTORE;
-}

bsp/renesas/ra4m2-eco/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h

@@ -80,7 +80,7 @@ extern "C" {
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
-            (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
@@ -140,7 +140,7 @@ extern "C" {
 #ifndef BSP_TZ_CFG_MSSAR
 #define BSP_TZ_CFG_MSSAR (\
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
-            (((2 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
             0xfffffffc) /* Unused */
 #endif
 
@@ -246,7 +246,7 @@ extern "C" {
 #endif
 
             /* Set DTCSTSAR if the Secure program uses the DTC. */
-#if 2 == RA_NOT_DEFINED
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
  #define BSP_TZ_CFG_DTC_USED (0U)
 #else
  #define BSP_TZ_CFG_DTC_USED (1U)

bsp/renesas/ra4m2-eco/ra_cfg/fsp_cfg/r_dtc_cfg.h

@@ -1,14 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_DTC_CFG_H_
-#define R_DTC_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* R_DTC_CFG_H_ */

bsp/renesas/ra4m2-eco/ra_cfg/fsp_cfg/r_sci_spi_cfg.h

@@ -1,14 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_SCI_SPI_CFG_H_
-#define R_SCI_SPI_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SCI_SPI_DTC_SUPPORT_ENABLE (1)
-#define SCI_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* R_SCI_SPI_CFG_H_ */

bsp/renesas/ra4m2-eco/ra_gen/hal_data.c

@@ -1,122 +1,5 @@
 /* generated HAL source file - do not edit */
 #include "hal_data.h"
-dtc_instance_ctrl_t g_transfer1_ctrl;
-
-transfer_info_t g_transfer1_info =
-{
-    .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
-    .transfer_settings_word_b.repeat_area    = TRANSFER_REPEAT_AREA_DESTINATION,
-    .transfer_settings_word_b.irq            = TRANSFER_IRQ_END,
-    .transfer_settings_word_b.chain_mode     = TRANSFER_CHAIN_MODE_DISABLED,
-    .transfer_settings_word_b.src_addr_mode  = TRANSFER_ADDR_MODE_FIXED,
-    .transfer_settings_word_b.size           = TRANSFER_SIZE_1_BYTE,
-    .transfer_settings_word_b.mode           = TRANSFER_MODE_NORMAL,
-    .p_dest                                  = (void *) NULL,
-    .p_src                                   = (void const *) NULL,
-    .num_blocks                              = 0,
-    .length                                  = 0,
-};
-
-const dtc_extended_cfg_t g_transfer1_cfg_extend =
-{
-    .activation_source   = VECTOR_NUMBER_SCI9_RXI,
-};
-const transfer_cfg_t g_transfer1_cfg =
-{
-    .p_info              = &g_transfer1_info,
-    .p_extend            = &g_transfer1_cfg_extend,
-};
-
-/* Instance structure to use this module. */
-const transfer_instance_t g_transfer1 =
-{
-    .p_ctrl        = &g_transfer1_ctrl,
-    .p_cfg         = &g_transfer1_cfg,
-    .p_api         = &g_transfer_on_dtc
-};
-dtc_instance_ctrl_t g_transfer0_ctrl;
-
-transfer_info_t g_transfer0_info =
-{
-    .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
-    .transfer_settings_word_b.repeat_area    = TRANSFER_REPEAT_AREA_SOURCE,
-    .transfer_settings_word_b.irq            = TRANSFER_IRQ_END,
-    .transfer_settings_word_b.chain_mode     = TRANSFER_CHAIN_MODE_DISABLED,
-    .transfer_settings_word_b.src_addr_mode  = TRANSFER_ADDR_MODE_INCREMENTED,
-    .transfer_settings_word_b.size           = TRANSFER_SIZE_1_BYTE,
-    .transfer_settings_word_b.mode           = TRANSFER_MODE_NORMAL,
-    .p_dest                                  = (void *) NULL,
-    .p_src                                   = (void const *) NULL,
-    .num_blocks                              = 0,
-    .length                                  = 0,
-};
-
-const dtc_extended_cfg_t g_transfer0_cfg_extend =
-{
-    .activation_source   = VECTOR_NUMBER_SCI9_TXI,
-};
-const transfer_cfg_t g_transfer0_cfg =
-{
-    .p_info              = &g_transfer0_info,
-    .p_extend            = &g_transfer0_cfg_extend,
-};
-
-/* Instance structure to use this module. */
-const transfer_instance_t g_transfer0 =
-{
-    .p_ctrl        = &g_transfer0_ctrl,
-    .p_cfg         = &g_transfer0_cfg,
-    .p_api         = &g_transfer_on_dtc
-};
-sci_spi_instance_ctrl_t g_sci_spi9_ctrl;
-
-/** SPI extended configuration */
-const sci_spi_extended_cfg_t g_sci_spi9_cfg_extend =
-{
-    .clk_div = {
-        /* Actual calculated bitrate: 6250000. */ .cks = 0, .brr = 3, .mddr = 0,
-    }
-};
-
-const spi_cfg_t g_sci_spi9_cfg =
-{
-    .channel         = 9,
-    .operating_mode  = SPI_MODE_MASTER,
-    .clk_phase       = SPI_CLK_PHASE_EDGE_ODD,
-    .clk_polarity    = SPI_CLK_POLARITY_LOW,
-    .mode_fault      = SPI_MODE_FAULT_ERROR_DISABLE,
-    .bit_order       = SPI_BIT_ORDER_MSB_FIRST,
-#define RA_NOT_DEFINED (1)
-#if (RA_NOT_DEFINED == g_transfer0)
-    .p_transfer_tx   = NULL,
-#else
-    .p_transfer_tx   = &g_transfer0,
-#endif
-#if (RA_NOT_DEFINED == g_transfer1)
-    .p_transfer_rx   = NULL,
-#else
-    .p_transfer_rx   = &g_transfer1,
-#endif
-#undef RA_NOT_DEFINED
-    .p_callback      = sci_spi9_callback,
-    .p_context       = NULL,
-    .rxi_irq         = VECTOR_NUMBER_SCI9_RXI,
-    .txi_irq         = VECTOR_NUMBER_SCI9_TXI,
-    .tei_irq         = VECTOR_NUMBER_SCI9_TEI,
-    .eri_irq         = VECTOR_NUMBER_SCI9_ERI,
-    .rxi_ipl         = (12),
-    .txi_ipl         = (12),
-    .tei_ipl         = (12),
-    .eri_ipl         = (12),
-    .p_extend        = &g_sci_spi9_cfg_extend,
-};
-/* Instance structure to use this module. */
-const spi_instance_t g_sci_spi9 =
-{
-    .p_ctrl          = &g_sci_spi9_ctrl,
-    .p_cfg           = &g_sci_spi9_cfg,
-    .p_api           = &g_spi_on_sci
-};
 sci_uart_instance_ctrl_t     g_uart4_ctrl;
 
             baud_setting_t               g_uart4_baud_setting =

bsp/renesas/ra4m2-eco/ra_gen/hal_data.h

@@ -4,36 +4,9 @@
 #include <stdint.h>
 #include "bsp_api.h"
 #include "common_data.h"
-#include "r_dtc.h"
-#include "r_transfer_api.h"
-#include "r_sci_spi.h"
-#include "r_spi_api.h"
 #include "r_sci_uart.h"
             #include "r_uart_api.h"
 FSP_HEADER
-/* Transfer on DTC Instance. */
-extern const transfer_instance_t g_transfer1;
-
-/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
-extern dtc_instance_ctrl_t g_transfer1_ctrl;
-extern const transfer_cfg_t g_transfer1_cfg;
-/* Transfer on DTC Instance. */
-extern const transfer_instance_t g_transfer0;
-
-/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
-extern dtc_instance_ctrl_t g_transfer0_ctrl;
-extern const transfer_cfg_t g_transfer0_cfg;
-/** SPI on SCI Instance. */
-extern const spi_instance_t g_sci_spi9;
-
-/** Access the SCI_SPI instance using these structures when calling API functions directly (::p_api is not used). */
-extern sci_spi_instance_ctrl_t g_sci_spi9_ctrl;
-extern const spi_cfg_t g_sci_spi9_cfg;
-
-/** Called by the driver when a transfer has completed or an error has occurred (Must be implemented by the user). */
-#ifndef sci_spi9_callback
-void sci_spi9_callback(spi_callback_args_t * p_args);
-#endif
 /** UART on SCI Instance. */
             extern const uart_instance_t      g_uart4;
 

bsp/renesas/ra4m2-eco/ra_gen/vector_data.c

@@ -12,10 +12,6 @@
             [5] = sci_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */
             [6] = sci_uart_tei_isr, /* SCI4 TEI (Transmit end) */
             [7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */
-            [8] = sci_spi_rxi_isr, /* SCI9 RXI (Received data full) */
-            [9] = sci_spi_txi_isr, /* SCI9 TXI (Transmit data empty) */
-            [10] = sci_spi_tei_isr, /* SCI9 TEI (Transmit end) */
-            [11] = sci_spi_eri_isr, /* SCI9 ERI (Receive error) */
         };
         const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
         {
@@ -27,9 +23,5 @@
             [5] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TXI), /* SCI4 TXI (Transmit data empty) */
             [6] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TEI), /* SCI4 TEI (Transmit end) */
             [7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */
-            [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
-            [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
-            [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
-            [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
         };
         #endif

bsp/renesas/ra4m2-eco/ra_gen/vector_data.h

@@ -6,17 +6,13 @@
         #endif
                 /* Number of interrupts allocated */
         #ifndef VECTOR_DATA_IRQ_COUNT
-        #define VECTOR_DATA_IRQ_COUNT    (12)
+        #define VECTOR_DATA_IRQ_COUNT    (8)
         #endif
         /* ISR prototypes */
         void sci_uart_rxi_isr(void);
         void sci_uart_txi_isr(void);
         void sci_uart_tei_isr(void);
         void sci_uart_eri_isr(void);
-        void sci_spi_rxi_isr(void);
-        void sci_spi_txi_isr(void);
-        void sci_spi_tei_isr(void);
-        void sci_spi_eri_isr(void);
 
         /* Vector table allocations */
         #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 0) /* SCI0 RXI (Receive data full) */
@@ -35,14 +31,6 @@
         #define SCI4_TEI_IRQn          ((IRQn_Type) 6) /* SCI4 TEI (Transmit end) */
         #define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
         #define SCI4_ERI_IRQn          ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
-        #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 8) /* SCI9 RXI (Received data full) */
-        #define SCI9_RXI_IRQn          ((IRQn_Type) 8) /* SCI9 RXI (Received data full) */
-        #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 9) /* SCI9 TXI (Transmit data empty) */
-        #define SCI9_TXI_IRQn          ((IRQn_Type) 9) /* SCI9 TXI (Transmit data empty) */
-        #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 10) /* SCI9 TEI (Transmit end) */
-        #define SCI9_TEI_IRQn          ((IRQn_Type) 10) /* SCI9 TEI (Transmit end) */
-        #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 11) /* SCI9 ERI (Receive error) */
-        #define SCI9_ERI_IRQn          ((IRQn_Type) 11) /* SCI9 ERI (Receive error) */
         #ifdef __cplusplus
         }
         #endif

bsp/renesas/ra4m2-eco/rtconfig.h

@@ -92,8 +92,6 @@
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V2
 #define RT_SERIAL_USING_DMA
-#define RT_USING_SPI
-#define RT_USING_SPI_MSD
 #define RT_USING_PIN
 
 /* Using USB */
@@ -147,12 +145,6 @@
 /* CYW43012 WiFi */
 
 
-/* BL808 WiFi */
-
-
-/* CYW43439 WiFi */
-
-
 /* IoT Cloud */
 
 
@@ -194,20 +186,15 @@
 
 /* peripheral libraries and drivers */
 
-/* HAL & SDK Drivers */
-
-/* STM32 HAL & SDK Drivers */
-
-
-/* Kendryte SDK */
-
-
 /* sensors drivers */
 
 
 /* touch drivers */
 
 
+/* Kendryte SDK */
+
+
 /* AI packages */
 
 
@@ -267,6 +254,7 @@
 
 /* Onboard Peripheral Drivers */
 
+
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
@@ -277,8 +265,6 @@
 #define BSP_USING_UART4
 #define BSP_UART4_RX_BUFSIZE 256
 #define BSP_UART4_TX_BUFSIZE 0
-#define BSP_USING_SCI_SPI
-#define BSP_USING_SCI_SPI9
 
 /* Board extended module Drivers */
 

bsp/renesas/ra4m2-eco/src/hal_entry.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2021-10-10     Sherman       first version
+ */
+
+#include <rtthread.h>
+#include "hal_data.h"
+#include <rtdevice.h>
+
+
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+
+    while (1)
+    {
+        rt_thread_mdelay(500);
+    }
+}

bsp/renesas/ra4m2-eco/src/hal_entry.cpp

@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2022-12-7      Vandoul      first version.
- */
-#include "rtthread.h"
-#include "drivers/pin.h"
-#include "hal_data.h"
-#include "drivers/spi.h"
-#ifdef __cplusplus
-extern "C"{
-#endif
-#include "bsp_api.h"
-#include "spi_msd.h"
-#ifdef __cplusplus
-}
-#endif
-
-static struct rt_spi_device sd_device;
-
-void hal_entry(void)
-{
-    rt_kprintf("hal_entry run.\r\n");
-    rt_pin_mode(BSP_IO_PORT_04_PIN_04, PIN_MODE_OUTPUT);
-    rt_kprintf("init spi sdcard.\r\n");
-    rt_pin_mode(BSP_IO_PORT_06_PIN_03, PIN_MODE_OUTPUT);
-    if(RT_EOK == rt_spi_bus_attach_device(&sd_device, "scpi9-0", "scpi9", (void *)BSP_IO_PORT_06_PIN_03)) {
-        if(RT_EOK != msd_init("sd0", "scpi9-0")) {
-            rt_kprintf("msd init failed!\r\n");
-        }
-    } else {
-        rt_kprintf("spi bus attach failed!\r\n");
-    }
-    
-    while (1)
-    {
-        rt_pin_write(BSP_IO_PORT_04_PIN_04, !rt_pin_read(BSP_IO_PORT_04_PIN_04));
-        rt_thread_mdelay(1000);
-    }
-}
-

bsp/renesas/ra6m3-ek/.config

@@ -278,16 +278,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -309,6 +299,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -330,7 +321,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -351,7 +341,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -498,9 +487,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -520,8 +506,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -559,35 +543,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -669,8 +629,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -678,6 +639,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -692,6 +661,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -714,6 +684,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -723,6 +694,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -730,6 +702,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -738,9 +711,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -755,7 +725,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -765,6 +734,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -840,9 +810,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -850,13 +818,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -901,7 +869,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -940,6 +908,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -962,7 +931,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -970,7 +939,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -983,7 +952,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1009,7 +977,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1026,11 +993,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1053,6 +1020,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 CONFIG_SOC_SERIES_R7FA6M3=y
 # CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1060,6 +1028,7 @@ CONFIG_SOC_SERIES_R7FA6M3=y
 # CONFIG_SOC_SERIES_R7FA6M5 is not set
 # CONFIG_SOC_SERIES_R7FA4M2 is not set
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1086,13 +1055,14 @@ CONFIG_BSP_USING_UART7=y
 # CONFIG_BSP_UART7_TX_USING_DMA is not set
 CONFIG_BSP_UART7_RX_BUFSIZE=256
 CONFIG_BSP_UART7_TX_BUFSIZE=0
-# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
 # CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_TIM is not set
-# CONFIG_BSP_USING_SCI_SPI is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ra6m3-ek/board/Kconfig

@@ -65,7 +65,6 @@ menu "Hardware Drivers Config"
             select RT_USING_SERIAL
             select RT_USING_SERIAL_V2
             if BSP_USING_UART
-
                 menuconfig BSP_USING_UART7
                     bool "Enable UART7"
                     default n
@@ -94,36 +93,37 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_I2C
-            bool "Enable I2C BUS"
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
             default n
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C0
+                    bool "Enable Hardware I2C0 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SOFT_I2C
+            bool "Enable software I2C bus"
             select RT_USING_I2C
             select RT_USING_I2C_BITOPS
             select RT_USING_PIN
-            if BSP_USING_I2C
-                config BSP_USING_HW_I2C
-                    bool "Enable Hardware I2C BUS"
-                    default n
-                if BSP_USING_HW_I2C
-                    config BSP_USING_HW_I2C0
-                        bool "Enable Hardware I2C0 BUS"
-                        default n
-                endif
-                if !BSP_USING_HW_I2C
-                    menuconfig BSP_USING_I2C1
-                        bool "Enable I2C1 BUS (software simulation)"
-                        default y
-                        if BSP_USING_I2C1
-                            config BSP_I2C1_SCL_PIN
-                                hex "i2c1 scl pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050C
-                            config BSP_I2C1_SDA_PIN
-                                hex "I2C1 sda pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050B
-                        endif
-                endif
+            default n
+            if BSP_USING_SOFT_I2C
+                config BSP_USING_SOFT_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 Bus (software simulation)"
+                    default n
+                    if BSP_USING_I2C1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050C
+                        config BSP_I2C1_SDA_PIN
+                            hex "i2c1 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050B
+                    endif
             endif
 
         menuconfig BSP_USING_PWM
@@ -149,28 +149,6 @@ menu "Hardware Drivers Config"
                 default n
         endif
 
-        menuconfig BSP_USING_SCI_SPI
-            bool "Enable SCI SPI BUS"
-            default n
-            select RT_USING_SPI
-            if BSP_USING_SCI_SPI 
-                config BSP_USING_SCI_SPI0
-                    bool "Enable SCI SPI0 BUS"
-                    default n
-                config BSP_USING_SCI_SPI1
-                    bool "Enable SCI SPI1 BUS"
-                    default n
-                config BSP_USING_SCI_SPI2
-                    bool "Enable SCI SPI2 BUS"
-                    default n
-                config BSP_USING_SCI_SPI3
-                    bool "Enable SCI SPI3 BUS"
-                    default n
-                config BSP_USING_SCI_SPI6
-                    bool "Enable SCI SPI6 BUS"
-                    default n
-            endif
-
         menuconfig BSP_USING_SPI
             bool "Enable SPI BUS"
             default n
@@ -196,6 +174,341 @@ menu "Hardware Drivers Config"
             select BSP_USING_GPIO
             default n
 
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
+            default n
+            config BSP_USING_SCIn_SPI
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SPI
+                default n
+
+            config BSP_USING_SCIn_I2C
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_SCIn_UART
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SERIAL
+                select RT_USING_SERIAL_V2
+                default n
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
+                    default n
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
+                    default n
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
+                    default n
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
+                    default n
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
+                    default n
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
+                    default n
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
+                    default n
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
+                    default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/renesas/ra6m3-ek/project.uvprojx

@@ -333,9 +333,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall  -Wmissing-declarations  -Wpointer-arith  -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>__CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, RT_USING_ARMLIBC</Define>
               <Undefine />
-              <IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\posix\io\poll;.;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal</IncludePath>
+              <IncludePath>board\ports;.;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\..\..\components\libc\posix\io\eventfd;..\..\..\include;..\libraries\HAL_Drivers\config;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -475,6 +475,25 @@
               </FileOption>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>condvar.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_IPC_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath> </IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
           <Files>
             <File>
               <FileName>dataqueue.c</FileName>
@@ -656,30 +675,30 @@
           <GroupName>Finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_parse.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>msh.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/renesas/ra6m3-ek/rtconfig.h

@@ -137,12 +137,6 @@
 /* CYW43012 WiFi */
 
 
-/* BL808 WiFi */
-
-
-/* CYW43439 WiFi */
-
-
 /* IoT Cloud */
 
 
@@ -184,20 +178,15 @@
 
 /* peripheral libraries and drivers */
 
-/* HAL & SDK Drivers */
-
-/* STM32 HAL & SDK Drivers */
-
-
-/* Kendryte SDK */
-
-
 /* sensors drivers */
 
 
 /* touch drivers */
 
 
+/* Kendryte SDK */
+
+
 /* AI packages */
 
 

bsp/renesas/ra6m3-hmi-board/.config

@@ -278,16 +278,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -309,6 +299,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -330,7 +321,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -351,7 +341,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -498,9 +487,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -520,8 +506,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -559,35 +543,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -669,8 +629,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -678,6 +639,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -692,6 +661,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -714,6 +684,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -723,6 +694,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -730,6 +702,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -738,9 +711,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -755,7 +725,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -765,6 +734,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -840,9 +810,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -850,13 +818,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -901,7 +869,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -940,6 +908,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -962,7 +931,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -970,7 +939,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -983,7 +952,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1009,7 +977,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1026,11 +993,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1053,6 +1020,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 CONFIG_SOC_SERIES_R7FA6M3=y
 # CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1060,6 +1028,7 @@ CONFIG_SOC_SERIES_R7FA6M3=y
 # CONFIG_SOC_SERIES_R7FA6M5 is not set
 # CONFIG_SOC_SERIES_R7FA4M2 is not set
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1071,6 +1040,9 @@ CONFIG_SOC_R7FA6M4AF=y
 #
 # CONFIG_BSP_USING_ARDUINO is not set
 # CONFIG_BSP_USING_FS is not set
+# CONFIG_BSP_USING_SPI_LCD is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_TOUCH is not set
 # CONFIG_BSP_USING_LVGL is not set
 
 #
@@ -1087,8 +1059,6 @@ CONFIG_BSP_USING_UART9=y
 # CONFIG_BSP_UART9_TX_USING_DMA is not set
 CONFIG_BSP_UART9_RX_BUFSIZE=256
 CONFIG_BSP_UART9_TX_BUFSIZE=0
-# CONFIG_BSP_USING_SCI_SPI is not set
-# CONFIG_BSP_USING_SCI is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_SOFT_SPI is not set
 # CONFIG_BSP_USING_SOFT_I2C is not set
@@ -1097,7 +1067,10 @@ CONFIG_BSP_UART9_TX_BUFSIZE=0
 # CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_SDHI is not set
 # CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_G2D is not set
+# CONFIG_BSP_USING_JPEG is not set
 # CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ra6m3-hmi-board/.settings/standalone.prefs

@@ -1,4 +1,4 @@
-#Sat Apr 13 10:31:40 CST 2024
+#Sat Apr 13 22:34:17 CST 2024
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sdhi\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_sci_spi.148160771=false
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/libraries=

bsp/renesas/ra6m3-hmi-board/board/Kconfig

@@ -41,19 +41,36 @@ menu "Hardware Drivers Config"
                     default n
                 config BSP_USING_SPICARD_FS
                     bool "Enable SPI FLASH filesystem"
-                    select BSP_USING_SPI
-                    select BSP_USING_SCI_SPI6
+                    select BSP_USING_SCI
+                    select BSP_USING_SCI7
+                    select BSP_USING_SCI7_SPI
                     select RT_USING_SPI_MSD
                     select RT_USING_DFS_ELMFAT
                     default n
             endif
 
         config BSP_USING_SPI_LCD
+            bool
             select BSP_USING_GPIO
             select BSP_USING_SPI
             select BSP_USING_SPI0
             default n
 
+        config BSP_USING_LCD
+            bool "Enable LCD-RGB565"
+            select BSP_USING_GPIO
+            select BSP_USING_PWM
+            select BSP_USING_PWM5
+            default n
+
+        config BSP_USING_TOUCH
+            bool "Enable Touch GT911"
+            select RT_USING_TOUCH
+            select RT_TOUCH_PIN_IRQ
+            select BSP_USING_SOFT_I2C
+            select BSP_USING_I2C1
+            default n
+
         menuconfig BSP_USING_LVGL
             bool "Enable LVGL for LCD"
             select PKG_USING_LVGL
@@ -67,16 +84,8 @@ menu "Hardware Drivers Config"
                 config BSP_USING_LCD_RGB
                     bool "Enable LVGL for LCD_RGB565"
                     select BSP_USING_LCD
-                    select RT_USING_TOUCH
-                    select RT_TOUCH_PIN_IRQ
+                    select BSP_USING_TOUCH
                     default n
-                    if BSP_USING_LCD_RGB
-                        config BSP_USING_TOUCH
-                            bool "Enable Touch GT911"
-                            select BSP_USING_SOFT_I2C
-                            select BSP_USING_I2C0
-                            default y
-                    endif
 
                 menuconfig BSP_USING_LVGL_DEMO
                     bool "Enable LVGL demo for LCD"
@@ -100,8 +109,6 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-
-
     endmenu
 
     menu "On-chip Peripheral Drivers"
@@ -168,49 +175,201 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_SCI_SPI
-            bool "Enable SCI SPI BUS"
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
             default n
             select RT_USING_SPI
-            if BSP_USING_SCI_SPI 
-                config BSP_USING_SCI_SPI0
-                    bool "Enable SCI SPI0 BUS"
+            if BSP_USING_SPI 
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
                     default n
-                config BSP_USING_SCI_SPI1
-                    bool "Enable SCI SPI1 BUS"
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
                     default n
-                config BSP_USING_SCI_SPI2
-                    bool "Enable SCI SPI2 BUS"
+            endif
+
+        menuconfig BSP_USING_SOFT_SPI
+            bool "Enable soft SPI BUS"
+            default n
+            select RT_USING_PIN
+            select RT_USING_SPI_BITOPS
+            select RT_USING_SPI
+            if BSP_USING_SOFT_SPI
+                config BSP_USING_SOFT_SPI1
+                    bool "Enable soft SPI1 BUS (software simulation)"
+                    default n
+                    if BSP_USING_SOFT_SPI1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_S_SPI1_SCK_PIN
+                            hex "spi1 sck pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x0204
+                        config BSP_S_SPI1_MOSI_PIN
+                            hex "spi1 mosi pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050C
+                        config BSP_S_SPI1_MISO_PIN
+                            hex "spi1 miso pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050B
+                    endif
+            endif
+
+        menuconfig BSP_USING_SOFT_I2C
+            bool "Enable software I2C bus"
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            default n
+            if BSP_USING_SOFT_I2C
+                config BSP_USING_SOFT_I2C
+                menuconfig BSP_USING_I2C0
+                    bool "Enable I2C0 Bus (software simulation)"
                     default n
-                config BSP_USING_SCI_SPI3
-                    bool "Enable SCI SPI3 BUS"
+                    if BSP_USING_I2C0
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C0_SCL_PIN
+                            hex "i2c0 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x202
+                        config BSP_I2C0_SDA_PIN
+                            hex "i2c0 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x203
+                    endif
+
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 Bus (software simulation)"
                     default n
-                config BSP_USING_SCI_SPI6
-                    bool "Enable SCI SPI6 BUS"
+                    if BSP_USING_I2C1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x202
+                        config BSP_I2C1_SDA_PIN
+                            hex "i2c1 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x203
+                    endif
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
                     default n
             endif
 
+        menuconfig BSP_USING_DAC
+	        bool "Enable DAC"
+	        default n
+	        select RT_USING_DAC
+	        if BSP_USING_DAC
+	            config BSP_USING_DAC0
+	                bool "Enable DAC0"
+	                default n
+	        endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+            config BSP_USING_PWM0
+                bool "Enable GPT0 (32-Bits) output PWM"
+                default n
+
+            config BSP_USING_PWM2
+                bool "Enable GPT2 (32-Bits) output PWM"
+                default n
+
+            config BSP_USING_PWM5
+                bool "Enable GPT5 (32-Bits) output PWM"
+                default n
+
+            config BSP_USING_PWM8
+                bool "Enable GPT8 (32-Bits) output PWM"
+                default n
+
+            endif
+
+        menuconfig BSP_USING_SDHI
+            bool "Enable SDHI"
+            default n
+            select RT_USING_SDIO
+            select RT_USING_DFS
+            select RT_LIBC_USING_FILEIO
+            select RT_USING_POSIX_DEVIO
+            if BSP_USING_SDHI
+                menuconfig BSP_USING_SDHI0
+                    bool "Enable SDHI0"
+                    default n
+                    if BSP_USING_SDHI0
+                        config SDHI_USING_1_BIT
+                            bool "Use 1-bit Mode(4-bit when disable)"
+                            default y
+                    endif
+
+                menuconfig BSP_USING_SDHI1
+                    bool "Enable SDHI1"
+                    default n
+                    if BSP_USING_SDHI1
+                        config SDHI_USING_1_BIT
+                            bool "Use 1-bit Mode(4-bit when disable)"
+                            default y
+                    endif
+                endif
+
+        menuconfig BSP_USING_CAN
+            bool "Enable CAN"
+            default n
+            select RT_USING_CAN
+            if BSP_USING_CAN
+                config BSP_USING_CAN0
+                    bool "Enable CAN0"
+                    default n
+            endif
+
+        config BSP_USING_G2D
+            bool
+            default n
+
+        config BSP_USING_JPEG
+            bool
+            default n
+
+        config BSP_USING_ETH
+            bool "Enable Ethernet"
+            select RT_USING_SAL
+            select RT_USING_LWIP
+            select RT_USING_NETDEV
+            default n
+
         menuconfig BSP_USING_SCI
             bool "Enable SCI Controller"
             default n
             config BSP_USING_SCIn_SPI
                 bool
-                default n
                 depends on BSP_USING_SCI
-            select RT_USING_SPI
+                select RT_USING_SPI
+                default n
 
             config BSP_USING_SCIn_I2C
                 bool
-                default n
                 depends on BSP_USING_SCI
                 select RT_USING_I2C
+                default n
 
             config BSP_USING_SCIn_UART
                 bool
-                default n
                 depends on BSP_USING_SCI
-            select RT_USING_SERIAL
-            select RT_USING_SERIAL_V2
+                select RT_USING_SERIAL
+                select RT_USING_SERIAL_V2
+                default n
 
             if BSP_USING_SCI
                 config BSP_USING_SCI0
@@ -525,166 +684,10 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_SPI
-            bool "Enable SPI BUS"
-            default n
-            select RT_USING_SPI
-            if BSP_USING_SPI 
-                config BSP_USING_SPI0
-                    bool "Enable SPI0 BUS"
-                    default n
-                config BSP_USING_SPI1
-                    bool "Enable SPI1 BUS"
-                    default n
-            endif
-
-        menuconfig BSP_USING_SOFT_SPI
-            bool "Enable soft SPI BUS"
-            default n
-            select RT_USING_PIN
-            select RT_USING_SPI_BITOPS
-            select RT_USING_SPI
-            if BSP_USING_SOFT_SPI
-                config BSP_USING_SOFT_SPI1
-                    bool "Enable soft SPI1 BUS (software simulation)"
-                    default n
-                    if BSP_USING_SOFT_SPI1
-                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
-                        config BSP_S_SPI1_SCK_PIN
-                            hex "spi1 sck pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x0204
-                        config BSP_S_SPI1_MOSI_PIN
-                            hex "spi1 mosi pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x050C
-                        config BSP_S_SPI1_MISO_PIN
-                            hex "spi1 miso pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x050B
-                    endif
-            endif
-
-        menuconfig BSP_USING_SOFT_I2C
-            bool "Enable software I2C bus"
-            select RT_USING_I2C
-            select RT_USING_I2C_BITOPS
-            select RT_USING_PIN
-            default n
-            if BSP_USING_SOFT_I2C
-                config BSP_USING_SOFT_I2C
-                menuconfig BSP_USING_I2C0
-                    bool "Enable I2C0 Bus (software simulation)"
-                    default n
-                    if BSP_USING_I2C0
-                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
-                        config BSP_I2C0_SCL_PIN
-                            hex "i2c0 scl pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x202
-                        config BSP_I2C0_SDA_PIN
-                            hex "i2c0 sda pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x203
-                    endif
-            endif
-
-    menuconfig BSP_USING_ADC
-        bool "Enable ADC"
-        default n
-        select RT_USING_ADC
-        if BSP_USING_ADC
-            config BSP_USING_ADC0
-                bool "Enable ADC0"
-                default n
-        endif
-
-        menuconfig BSP_USING_DAC
-	        bool "Enable DAC"
-	        default n
-	        select RT_USING_DAC
-	        if BSP_USING_DAC
-	            config BSP_USING_DAC0
-	                bool "Enable DAC0"
-	                default n
-	        endif
-
-        menuconfig BSP_USING_PWM
-            bool "Enable PWM"
-            default n
-            select RT_USING_PWM
-            if BSP_USING_PWM
-            config BSP_USING_PWM0
-                bool "Enable GPT0 (32-Bits) output PWM"
-                default n
-
-            config BSP_USING_PWM2
-                bool "Enable GPT2 (32-Bits) output PWM"
-                default n
-
-            config BSP_USING_PWM8
-                bool "Enable GPT8 (32-Bits) output PWM"
-                default n
-
-            endif
-
-        menuconfig BSP_USING_SDHI
-            bool "Enable SDHI"
-            default n
-            select RT_USING_SDIO
-            select RT_USING_DFS
-            select RT_LIBC_USING_FILEIO
-            select RT_USING_POSIX_DEVIO
-            if BSP_USING_SDHI
-                menuconfig BSP_USING_SDHI0
-                    bool "Enable SDHI0"
-                    default n
-                    if BSP_USING_SDHI0
-                        config SDHI_USING_1_BIT
-                            bool "Use 1-bit Mode(4-bit when disable)"
-                            default y
-                    endif
-
-                menuconfig BSP_USING_SDHI1
-                    bool "Enable SDHI1"
-                    default n
-                    if BSP_USING_SDHI1
-                        config SDHI_USING_1_BIT
-                            bool "Use 1-bit Mode(4-bit when disable)"
-                            default y
-                    endif
-                endif
-
-        menuconfig BSP_USING_CAN
-            bool "Enable CAN"
-            default n
-            select RT_USING_CAN
-            if BSP_USING_CAN
-                config BSP_USING_CAN0
-                    bool "Enable CAN0"
-                    default n
-            endif
-
-        config BSP_USING_G2D
-            default n
-
-        config BSP_USING_JPEG
-            default n
-
-        config BSP_USING_ETH
-            bool "Enable Ethernet"
-            select RT_USING_SAL
-            select RT_USING_LWIP
-            select RT_USING_NETDEV
-            default n
-
-        config BSP_USING_LCD
-            select BSP_USING_GPIO
-            default n
-
     endmenu
 
     menu "Board extended module Drivers"
+
         menuconfig BSP_USING_RW007
             bool "Enable RW007"
             default n
@@ -694,31 +697,33 @@ menu "Hardware Drivers Config"
             select BSP_USING_SCI3_SPI
             select RT_USING_MEMPOOL
             select RW007_NOT_USE_EXAMPLE_DRIVERS
+            
+            if BSP_USING_RW007
+                config RA_RW007_SPI_BUS_NAME
+                    string "RW007 BUS NAME"
+                    default "sci3s"
+
+                config RA_RW007_CS_PIN
+                    hex "(HEX)CS pin index"
+                    default 0x0308
+
+                config RA_RW007_BOOT0_PIN
+                    hex "(HEX)BOOT0 pin index (same as spi clk pin)"
+                    default 0x030B
+
+                config RA_RW007_BOOT1_PIN
+                    hex "(HEX)BOOT1 pin index (same as spi cs pin)"
+                    default 0x0308
+
+                config RA_RW007_INT_BUSY_PIN
+                    hex "(HEX)INT/BUSY pin index"
+                    default 0x000F
+
+                config RA_RW007_RST_PIN
+                    hex "(HEX)RESET pin index"
+                    default 0x030C
+            endif
 
-        if BSP_USING_RW007
-            config RA_RW007_SPI_BUS_NAME
-                string "RW007 BUS NAME"
-                default "sci_spi3"
-
-            config RA_RW007_CS_PIN
-                hex "(HEX)CS pin index"
-                default 0x0308
-
-            config RA_RW007_BOOT0_PIN
-                hex "(HEX)BOOT0 pin index (same as spi clk pin)"
-                default 0x030B
-
-            config RA_RW007_BOOT1_PIN
-                hex "(HEX)BOOT1 pin index (same as spi cs pin)"
-                default 0x0308
-
-            config RA_RW007_INT_BUSY_PIN
-                hex "(HEX)INT/BUSY pin index"
-                default 0x000F
-
-            config RA_RW007_RST_PIN
-                hex "(HEX)RESET pin index"
-                default 0x030C
-        endif
     endmenu
+
 endmenu

bsp/renesas/ra6m3-hmi-board/board/ports/lcd_port.h

@@ -8,8 +8,8 @@
  * 2018-07-28     liu2guang      the first version for STM32F469NI-Discovery.
  */
 
-#ifndef __DRV_LCD_H_
-#define __DRV_LCD_H_
+#ifndef __LCD_PORT_H_
+#define __LCD_PORT_H_
 
 #include <rtthread.h>
 #include <rtdevice.h>
@@ -31,4 +31,4 @@ typedef enum
 
 #define LCD_BL_PIN  BSP_IO_PORT_01_PIN_00
 
-#endif
+#endif  /* __LCD_PORT_H_ */

bsp/renesas/ra6m3-hmi-board/board/ports/mnt.c

@@ -103,11 +103,11 @@ static void sd_mount(void)
 
 #else
 #include <spi_msd.h>
-#include "drv_sci_spi.h"
+#include "drv_sci.h"
 int sd_mount(void)
 {
     uint32_t cs_pin = BSP_IO_PORT_06_PIN_11;
-    rt_hw_sci_spi_device_attach("scpi7", "scpi70", cs_pin);
+    rt_hw_sci_spi_device_attach("sci7s", "scpi70", cs_pin);
     msd_init("sd0", "scpi70");
     if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
     {

bsp/renesas/ra6m3-hmi-board/board/ports/wifi/drv_rw007.c

@@ -2,7 +2,7 @@
 #include <rtdbg.h>
 #ifdef BSP_USING_RW007
 #include <rtdevice.h>
-#include <drv_sci_spi.h>
+#include <drv_sci.h>
 #include <board.h>
 #include <spi_wifi_rw007.h>
 

bsp/renesas/ra6m3-hmi-board/board/ra6m3_it.c

@@ -7,24 +7,6 @@ rt_weak void can0_callback(can_callback_args_t *p_args)
 }
 #endif
 
-#ifdef BSP_USING_SCI_SPI
-rt_weak void sci_spi3_callback(spi_callback_args_t *p_args)
-{
-}
-
-rt_weak void sci_spi4_callback(spi_callback_args_t *p_args)
-{
-}
-
-rt_weak void sci_spi6_callback(spi_callback_args_t *p_args)
-{
-}
-
-rt_weak void sci_spi7_callback(spi_callback_args_t *p_args)
-{
-}
-#endif
-
 #ifdef BSP_USING_ETH
 rt_weak void user_ether0_callback(ether_callback_args_t *p_args)
 {

bsp/renesas/ra6m3-hmi-board/configuration.xml

@@ -771,7 +771,7 @@
       <property id="module.driver.ether_phy.flow_control" value="module.driver.ether_phy.flow_control.0"/>
     </module>
     <module id="module.driver.spi_on_sci_spi.148160771">
-      <property id="module.driver.spi.name" value="g_spi3"/>
+      <property id="module.driver.spi.name" value="g_sci3"/>
       <property id="module.driver.spi.channel" value="3"/>
       <property id="module.driver.spi.operating_mode" value="module.driver.spi.operating_mode.mode_master"/>
       <property id="module.driver.spi.clk_phase" value="module.driver.spi.clk_phase.clk_phase_edge_odd"/>

bsp/renesas/ra6m3-hmi-board/project.uvprojx

@@ -333,9 +333,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall  -Wmissing-declarations  -Wpointer-arith  -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>RT_USING_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS</Define>
               <Undefine />
-              <IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\epoll;..\libraries\HAL_Drivers;board\ports\wifi;..\..\..\components\libc\posix\io\eventfd;..\..\..\libcpu\arm\common;board\ports;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\finsh;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\compilers\common\extension;..\libraries\HAL_Drivers\config;board;..\..\..\components\libc\compilers\common\extension\fcntl\octal</IncludePath>
+              <IncludePath>..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\libraries\HAL_Drivers\config;board\ports;..\..\..\include;.;board;..\..\..\components\finsh;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board\ports\wifi;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>

bsp/renesas/ra6m3-hmi-board/rtconfig.h

@@ -137,12 +137,6 @@
 /* CYW43012 WiFi */
 
 
-/* BL808 WiFi */
-
-
-/* CYW43439 WiFi */
-
-
 /* IoT Cloud */
 
 
@@ -184,20 +178,15 @@
 
 /* peripheral libraries and drivers */
 
-/* HAL & SDK Drivers */
-
-/* STM32 HAL & SDK Drivers */
-
-
-/* Kendryte SDK */
-
-
 /* sensors drivers */
 
 
 /* touch drivers */
 
 
+/* Kendryte SDK */
+
+
 /* AI packages */
 
 

bsp/renesas/ra6m4-cpk/.config

@@ -284,16 +284,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
-
-#
-# BL808 WiFi
-#
-# CONFIG_PKG_USING_WLAN_BL808 is not set
-
-#
-# CYW43439 WiFi
-#
-# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -315,6 +305,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -336,7 +327,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
-# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -357,7 +347,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
-# CONFIG_PKG_USING_LHC_MODBUS is not set
 
 #
 # security packages
@@ -504,9 +493,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_CORE is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set
-# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
@@ -526,8 +512,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
-# CONFIG_PKG_USING_FILEX is not set
-# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -565,35 +549,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SFDB is not set
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
-# CONFIG_PKG_USING_R_RHEALSTONE is not set
 
 #
 # peripheral libraries and drivers
 #
 
-#
-# HAL & SDK Drivers
-#
-
-#
-# STM32 HAL & SDK Drivers
-#
-# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-
 #
 # sensors drivers
 #
@@ -675,8 +635,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
-# CONFIG_PKG_USING_CST812T is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -684,6 +645,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -698,6 +667,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
@@ -720,6 +690,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -729,6 +700,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -736,6 +708,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -744,9 +717,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ST7789 is not set
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
-# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
-# CONFIG_PKG_USING_BT_MX01 is not set
-# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
@@ -761,7 +731,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
-# CONFIG_PKG_USING_R_TINYMAIX is not set
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -771,6 +740,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -846,9 +816,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
-# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
@@ -856,13 +824,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -907,7 +875,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -946,6 +914,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -968,7 +937,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -976,7 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -989,7 +958,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
@@ -1015,7 +983,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
 
 #
 # Data Storage
@@ -1032,11 +999,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 
 #
 # Other
@@ -1059,6 +1026,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Uncategorized
 #
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 CONFIG_SOC_FAMILY_RENESAS=y
 # CONFIG_SOC_SERIES_R7FA6M3 is not set
 CONFIG_SOC_SERIES_R7FA6M4=y
@@ -1066,6 +1034,7 @@ CONFIG_SOC_SERIES_R7FA6M4=y
 # CONFIG_SOC_SERIES_R7FA6M5 is not set
 # CONFIG_SOC_SERIES_R7FA4M2 is not set
 # CONFIG_SOC_SERIES_R7FA8M85 is not set
+# CONFIG_SOC_SERIES_R9A07G0 is not set
 
 #
 # Hardware Drivers Config
@@ -1101,16 +1070,15 @@ CONFIG_BSP_UART7_RX_BUFSIZE=256
 CONFIG_BSP_UART7_TX_BUFSIZE=0
 # CONFIG_BSP_USING_UART8 is not set
 # CONFIG_BSP_USING_UART9 is not set
-# CONFIG_BSP_USING_I2C is not set
-# CONFIG_BSP_USING_SCI_SPI is not set
-CONFIG_BSP_USING_SPI=y
-CONFIG_BSP_USING_SPI0=y
-# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_DAC is not set
 # CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_SDHI is not set
 # CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_SCI is not set
 
 #
 # Board extended module Drivers

bsp/renesas/ra6m4-cpk/.settings/standalone.prefs

@@ -1,24 +1,25 @@
-#Mon Jul 24 15:57:07 CST 2023
+#Mon Apr 15 16:27:43 CST 2024
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|2044432844,ra/fsp/inc/instances/r_spi.h|1108533607,ra/fsp/inc/api/r_spi_api.h|1854500045,ra/fsp/src/r_spi/r_spi.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2425160085,ra/fsp/inc/api/bsp_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3297195641,ra/fsp/inc/fsp_version.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|1728953905,ra/fsp/inc/fsp_features.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_spi.1251360366=false
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#3.5.0/all=1854500045,ra/fsp/src/r_spi/r_spi.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|2044432844,ra/fsp/inc/instances/r_spi.h|1108533607,ra/fsp/inc/api/r_spi_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2208590403,ra/fsp/inc/instances/r_ioport.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1728953905,ra/fsp/inc/fsp_features.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|546480625,ra/fsp/inc/fsp_common_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2425160085,ra/fsp/inc/api/bsp_api.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3297195641,ra/fsp/inc/fsp_version.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.201575186=false
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=1906465970,ra/fsp/inc/api/r_external_irq_api.h|2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c
 com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#3.5.0/all=3271601603,ra/fsp/inc/instances/r_dtc.h|356298762,ra/fsp/src/r_dtc/r_dtc.c|1610456547,ra/fsp/inc/api/r_transfer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|3271601603,ra/fsp/inc/instances/r_dtc.h|356298762,ra/fsp/src/r_dtc/r_dtc.c
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/all=ra/board/ra6m4_cpk/board_leds.c|ra/board/ra6m4_cpk/board_init.h|ra/board/ra6m4_cpk/board.h|ra/board/ra6m4_cpk/board_init.c|ra/board/ra6m4_cpk/board_ethernet_phy.h|ra/board/ra6m4_cpk/board_leds.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=

bsp/renesas/ra6m4-cpk/board/Kconfig

@@ -322,58 +322,37 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
-        menuconfig BSP_USING_I2C
-            bool "Enable I2C BUS"
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
             default n
-            select RT_USING_I2C
-            select RT_USING_I2C_BITOPS
-            select RT_USING_PIN
-            if BSP_USING_I2C
-                config BSP_USING_HW_I2C
-                    bool "Enable Hardware I2C BUS"
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C1
+                    bool "Enable Hardware I2C1 BUS"
                     default n
-                if BSP_USING_HW_I2C
-                    config BSP_USING_HW_I2C1
-                        bool "Enable Hardware I2C1 BUS"
-                        default n
-                endif
-                if !BSP_USING_HW_I2C
-                    menuconfig BSP_USING_I2C1
-                        bool "Enable I2C1 BUS (software simulation)"
-                        default y
-                        if BSP_USING_I2C1
-                            config BSP_I2C1_SCL_PIN
-                                hex "i2c1 scl pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050C
-                            config BSP_I2C1_SDA_PIN
-                                hex "I2C1 sda pin number"
-                                range 0x0000 0x0B0F
-                                default 0x050B
-                        endif
-                endif
             endif
 
-        menuconfig BSP_USING_SCI_SPI
-            bool "Enable SCI SPI BUS"
+        menuconfig BSP_USING_SOFT_I2C
+            bool "Enable software I2C bus"
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
             default n
-            select RT_USING_SPI
-            if BSP_USING_SCI_SPI 
-                config BSP_USING_SCI_SPI0
-                    bool "Enable SCI SPI0 BUS"
-                    default n
-                config BSP_USING_SCI_SPI1
-                    bool "Enable SCI SPI1 BUS"
-                    default n
-                config BSP_USING_SCI_SPI2
-                    bool "Enable SCI SPI2 BUS"
-                    default n
-                config BSP_USING_SCI_SPI3
-                    bool "Enable SCI SPI3 BUS"
-                    default n
-                config BSP_USING_SCI_SPI6
-                    bool "Enable SCI SPI6 BUS"
-                    default n
+            if BSP_USING_SOFT_I2C
+                config BSP_USING_SOFT_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 Bus (software simulation)"
+                    default n
+                    if BSP_USING_I2C1
+                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050C
+                        config BSP_I2C1_SDA_PIN
+                            hex "i2c1 sda pin number (hex)"
+                            range 0x0000 0xFFFF
+                            default 0x050B
+                    endif
             endif
     
         menuconfig BSP_USING_SPI
@@ -504,6 +483,341 @@ menu "Hardware Drivers Config"
                     default n
             endif
 
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
+            default n
+            config BSP_USING_SCIn_SPI
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SPI
+                default n
+
+            config BSP_USING_SCIn_I2C
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_SCIn_UART
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SERIAL
+                select RT_USING_SERIAL_V2
+                default n
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
+                    default n
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
+                    default n
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
+                    default n
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
+                    default n
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
+                    default n
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
+                    default n
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
+                    default n
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
+                    default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/renesas/ra6m4-cpk/buildinfo.gpdsc

@@ -57,19 +57,14 @@
         <file category="source" name="ra/board/ra6m4_cpk/board_leds.c"/>
         <file category="header" name="ra/board/ra6m4_cpk/board_leds.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
-        <file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
-        <file category="header" name="ra/fsp/inc/api/r_spi_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
         <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_dtc.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
         <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
-        <file category="header" name="ra/fsp/inc/instances/r_spi.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
@@ -103,11 +98,8 @@
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h" path=""/>
         <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h" path=""/>
-        <file category="source" name="ra/fsp/src/r_dtc/r_dtc.c"/>
-        <file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
         <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
         <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
-        <file category="source" name="ra/fsp/src/r_spi/r_spi.c"/>
         <file category="other" name="ra/SConscript"/>
       </files>
     </component>
@@ -120,11 +112,8 @@
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_dtc_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
         <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
-        <file category="header" name="ra_cfg/fsp_cfg/r_spi_cfg.h" path=""/>
         <file category="other" name="ra_cfg/SConscript"/>
       </files>
     </component>

bsp/renesas/ra6m4-cpk/configuration.xml

@@ -216,18 +216,18 @@
       <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
       <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
     </module>
-    <module id="module.driver.external_irq_on_icu.1658263033">
-      <property id="module.driver.external_irq.name" value="g_external_irq0"/>
-      <property id="module.driver.external_irq.channel" value="0"/>
+    <module id="module.driver.external_irq_on_icu.209215844">
+      <property id="module.driver.external_irq.name" value="g_external_irq15"/>
+      <property id="module.driver.external_irq.channel" value="15"/>
       <property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
       <property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
       <property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
       <property id="module.driver.external_irq.p_callback" value="irq_callback"/>
       <property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority12"/>
     </module>
-    <module id="module.driver.spi_on_spi.1282792503">
-      <property id="module.driver.spi.name" value="g_spi0"/>
-      <property id="module.driver.spi.channel" value="0"/>
+    <module id="module.driver.spi_on_spi.1251360366">
+      <property id="module.driver.spi.name" value="g_spi1"/>
+      <property id="module.driver.spi.channel" value="1"/>
       <property id="module.driver.spi.rxi_ipl" value="board.icu.common.irq.priority12"/>
       <property id="module.driver.spi.txi_ipl" value="board.icu.common.irq.priority12"/>
       <property id="module.driver.spi.tei_ipl" value="board.icu.common.irq.priority12"/>
@@ -237,7 +237,7 @@
       <property id="module.driver.spi.clk_polarity" value="module.driver.spi.clk_polarity.clk_polarity_low"/>
       <property id="module.driver.spi.mode_fault" value="module.driver.spi.mode_fault.mode_fault_error_disable"/>
       <property id="module.driver.spi.bit_order" value="module.driver.spi.bit_order.bit_order_msb_first"/>
-      <property id="module.driver.spi.p_callback" value="spi0_callback"/>
+      <property id="module.driver.spi.p_callback" value="spi1_callback"/>
       <property id="module.driver.spi.spi_clksyn" value="module.driver.spi.spi_clksyn.spi_clksyn"/>
       <property id="module.driver.spi.spi_comm" value="module.driver.spi.spi_comm.full_duplex"/>
       <property id="module.driver.spi.ssl_polarity" value="module.driver.spi.ssl_polarity.low"/>
@@ -250,7 +250,7 @@
       <property id="module.driver.spi.ssl_negation_delay" value="module.driver.spi.ssl_negation_delay.one"/>
       <property id="module.driver.spi.next_access_delay" value="module.driver.spi.next_access_delay.one"/>
     </module>
-    <module id="module.driver.transfer_on_dtc.1780258871">
+    <module id="module.driver.transfer_on_dtc.572577316">
       <property id="module.driver.transfer.name" value="g_transfer0"/>
       <property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
       <property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
@@ -264,7 +264,7 @@
       <property id="module.driver.transfer.num_blocks" value="0"/>
       <property id="module.driver.transfer.activation_source" value="_disabled"/>
     </module>
-    <module id="module.driver.transfer_on_dtc.1292359901">
+    <module id="module.driver.transfer_on_dtc.166887615">
       <property id="module.driver.transfer.name" value="g_transfer1"/>
       <property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
       <property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
@@ -281,10 +281,10 @@
     <context id="_hal.0">
       <stack module="module.driver.ioport_on_ioport.0"/>
       <stack module="module.driver.uart_on_sci_uart.201575186"/>
-      <stack module="module.driver.external_irq_on_icu.1658263033"/>
-      <stack module="module.driver.spi_on_spi.1282792503">
-        <stack module="module.driver.transfer_on_dtc.1780258871" requires="module.driver.spi_on_spi.requires.transfer_tx"/>
-        <stack module="module.driver.transfer_on_dtc.1292359901" requires="module.driver.spi_on_spi.requires.transfer_rx"/>
+      <stack module="module.driver.external_irq_on_icu.209215844"/>
+      <stack module="module.driver.spi_on_spi.1251360366">
+        <stack module="module.driver.transfer_on_dtc.572577316" requires="module.driver.spi_on_spi.requires.transfer_tx"/>
+        <stack module="module.driver.transfer_on_dtc.166887615" requires="module.driver.spi_on_spi.requires.transfer_rx"/>
       </stack>
     </context>
     <config id="config.driver.ioport">
@@ -438,8 +438,6 @@
       <configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/>
       <configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/>
       <configSetting altId="irq0.irq00.p105" configurationId="irq0.irq00"/>
-      <configSetting altId="irq0.irq11.p006" configurationId="irq0.irq11"/>
-      <configSetting altId="irq0.irq14.p505" configurationId="irq0.irq14"/>
       <configSetting altId="irq0.irq15.p506" configurationId="irq0.irq15"/>
       <configSetting altId="irq0.mode.enabled" configurationId="irq0.mode"/>
       <configSetting altId="p000.adc0.an00" configurationId="p000"/>
@@ -454,10 +452,6 @@
       <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
       <configSetting altId="p005.adc0.an05" configurationId="p005"/>
       <configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/>
-      <configSetting altId="p006.irq0.irq11" configurationId="p006"/>
-      <configSetting altId="p006.gpio_irq.gpio_irq_enabled" configurationId="p006.gpio_irq"/>
-      <configSetting altId="p006.gpio_mode.gpio_mode_irq" configurationId="p006.gpio_mode"/>
-      <configSetting altId="p006.gpio_pupd.gpio_pupd_ip_up" configurationId="p006.gpio_pupd"/>
       <configSetting altId="p008.output.low" configurationId="p008"/>
       <configSetting altId="p008.gpio_mode.gpio_mode_out.low" configurationId="p008.gpio_mode"/>
       <configSetting altId="p014.output.low" configurationId="p014"/>
@@ -475,12 +469,6 @@
       <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
       <configSetting altId="p110.debug0.tdi" configurationId="p110"/>
       <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
-      <configSetting altId="p202.spi0.miso" configurationId="p202"/>
-      <configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/>
-      <configSetting altId="p203.spi0.mosi" configurationId="p203"/>
-      <configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/>
-      <configSetting altId="p204.spi0.rspck" configurationId="p204"/>
-      <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
       <configSetting altId="p212.cgc0.extal" configurationId="p212"/>
       <configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/>
       <configSetting altId="p213.cgc0.xtal" configurationId="p213"/>
@@ -495,8 +483,6 @@
       <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
       <configSetting altId="p412.spi1.rspck" configurationId="p412"/>
       <configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
-      <configSetting altId="p413.spi1.ssl0" configurationId="p413"/>
-      <configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
       <configSetting altId="p414.output.low" configurationId="p414"/>
       <configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/>
       <configSetting altId="p415.output.low" configurationId="p415"/>
@@ -509,13 +495,9 @@
       <configSetting altId="p503.gpio_mode.gpio_mode_out.low" configurationId="p503.gpio_mode"/>
       <configSetting altId="p504.output.low" configurationId="p504"/>
       <configSetting altId="p504.gpio_mode.gpio_mode_out.low" configurationId="p504.gpio_mode"/>
-      <configSetting altId="p505.irq0.irq14" configurationId="p505"/>
-      <configSetting altId="p505.gpio_irq.gpio_irq_enabled" configurationId="p505.gpio_irq"/>
-      <configSetting altId="p505.gpio_mode.gpio_mode_irq" configurationId="p505.gpio_mode"/>
       <configSetting altId="p506.irq0.irq15" configurationId="p506"/>
       <configSetting altId="p506.gpio_irq.gpio_irq_enabled" configurationId="p506.gpio_irq"/>
       <configSetting altId="p506.gpio_mode.gpio_mode_irq" configurationId="p506.gpio_mode"/>
-      <configSetting altId="p506.gpio_pupd.gpio_pupd_ip_up" configurationId="p506.gpio_pupd"/>
       <configSetting altId="p511.iic1.sda" configurationId="p511"/>
       <configSetting altId="p511.gpio_speed.gpio_speed_medium" configurationId="p511.gpio_drivecapacity"/>
       <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
@@ -536,17 +518,12 @@
       <configSetting altId="sci7.pairing.c" configurationId="sci7.pairing"/>
       <configSetting altId="sci7.rxd.p614" configurationId="sci7.rxd"/>
       <configSetting altId="sci7.txd.p613" configurationId="sci7.txd"/>
-      <configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/>
-      <configSetting altId="spi0.mode.enabled.free" configurationId="spi0.mode"/>
-      <configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/>
       <configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/>
-      <configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/>
       <configSetting altId="spi1.miso.p410" configurationId="spi1.miso"/>
       <configSetting altId="spi1.mode.enabled.b" configurationId="spi1.mode"/>
       <configSetting altId="spi1.mosi.p411" configurationId="spi1.mosi"/>
       <configSetting altId="spi1.pairing.b" configurationId="spi1.pairing"/>
       <configSetting altId="spi1.rspck.p412" configurationId="spi1.rspck"/>
-      <configSetting altId="spi1.ssl0.p413" configurationId="spi1.ssl0"/>
       <configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/>
       <configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/>
       <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>

bsp/renesas/ra6m4-cpk/project.uvprojx

@@ -334,9 +334,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>__RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC</Define>
               <Undefine />
-              <IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\extension\fcntl\octal;.;board;board\ports;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\libraries\HAL_Drivers;..\..\..\components\finsh;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\ipc</IncludePath>
+              <IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\finsh;board;.;..\libraries\HAL_Drivers;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers\config;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;board\ports;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -476,6 +476,25 @@
               </FileOption>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>condvar.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_IPC_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath> </IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
           <Files>
             <File>
               <FileName>dataqueue.c</FileName>
@@ -683,13 +702,6 @@
               <FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
             </File>
           </Files>
-          <Files>
-            <File>
-              <FileName>drv_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\HAL_Drivers\drv_spi.c</FilePath>
-            </File>
-          </Files>
           <Files>
             <File>
               <FileName>drv_usart_v2.c</FileName>
@@ -702,30 +714,30 @@
           <GroupName>Finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_parse.c</FileName>
+              <FileName>msh.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_external_irq_api.h

@@ -1,177 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup EXTERNAL_IRQ_API External IRQ Interface
- * @brief Interface for detecting external interrupts.
- *
- * @section EXTERNAL_IRQ_API_Summary Summary
- * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
- * external IRQ pin.
- *
- * The  External IRQ Interface can be implemented by:
- * - @ref ICU
- *
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_EXTERNAL_IRQ_API_H
-#define R_EXTERNAL_IRQ_API_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/**********************************************************************************************************************
- * Macro definitions
- *********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- *********************************************************************************************************************/
-
-/** Callback function parameter data */
-typedef struct st_external_irq_callback_args
-{
-    /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
-    void const * p_context;
-    uint32_t     channel;              ///< The physical hardware channel that caused the interrupt.
-} external_irq_callback_args_t;
-
-/** Condition that will trigger an interrupt when detected. */
-typedef enum e_external_irq_trigger
-{
-    EXTERNAL_IRQ_TRIG_FALLING   = 0,   ///< Falling edge trigger
-    EXTERNAL_IRQ_TRIG_RISING    = 1,   ///< Rising edge trigger
-    EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2,   ///< Both edges trigger
-    EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3,   ///< Low level trigger
-} external_irq_trigger_t;
-
-/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
- * conditions that are shorter than 3 periods of the filter clock.
- */
-typedef enum e_external_irq_pclk_div
-{
-    EXTERNAL_IRQ_PCLK_DIV_BY_1  = 0,   ///< Filter using PCLK divided by 1
-    EXTERNAL_IRQ_PCLK_DIV_BY_8  = 1,   ///< Filter using PCLK divided by 8
-    EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2,   ///< Filter using PCLK divided by 32
-    EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3,   ///< Filter using PCLK divided by 64
-} external_irq_pclk_div_t;
-
-/** User configuration structure, used in open function */
-typedef struct st_external_irq_cfg
-{
-    uint8_t                 channel;   ///< Hardware channel used.
-    uint8_t                 ipl;       ///< Interrupt priority
-    IRQn_Type               irq;       ///< NVIC interrupt number assigned to this instance
-    external_irq_trigger_t  trigger;   ///< Trigger setting.
-    external_irq_pclk_div_t pclk_div;  ///< Digital filter clock divisor setting.
-    bool filter_enable;                ///< Digital filter enable/disable setting.
-
-    /** Callback provided external input trigger occurs. */
-    void (* p_callback)(external_irq_callback_args_t * p_args);
-
-    /** Placeholder for user data.  Passed to the user callback in @ref external_irq_callback_args_t. */
-    void const * p_context;
-    void const * p_extend;             ///< External IRQ hardware dependent configuration.
-} external_irq_cfg_t;
-
-/** External IRQ control block.  Allocate an instance specific control block to pass into the external IRQ API calls.
- * @par Implemented as
- * - icu_instance_ctrl_t
- */
-typedef void external_irq_ctrl_t;
-
-/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
-typedef struct st_external_irq_api
-{
-    /** Initial configuration.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqOpen()
-     *
-     * @param[out]  p_ctrl  Pointer to control block. Must be declared by user. Value set here.
-     * @param[in]   p_cfg   Pointer to configuration structure. All elements of the structure must be set by user.
-     */
-    fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);
-
-    /** Enable callback when an external trigger condition occurs.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqEnable()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);
-
-    /** Disable callback when external trigger condition occurs.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqDisable()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);
-
-    /**
-     * Specify callback function and optional context pointer and working memory pointer.
-     * @par Implemented as
-     * - R_ICU_ExternalIrqCallbackSet()
-     *
-     * @param[in]   p_ctrl                   Pointer to the Extneral IRQ control block.
-     * @param[in]   p_callback               Callback function
-     * @param[in]   p_context                Pointer to send to callback function
-     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
-     *                                       Callback arguments allocated here are only valid during the callback.
-     */
-    fsp_err_t (* callbackSet)(external_irq_ctrl_t * const          p_api_ctrl,
-                              void (                             * p_callback)(external_irq_callback_args_t *),
-                              void const * const                   p_context,
-                              external_irq_callback_args_t * const p_callback_memory);
-
-    /** Allow driver to be reconfigured. May reduce power consumption.
-     * @par Implemented as
-     * - @ref R_ICU_ExternalIrqClose()
-     *
-     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
-     */
-    fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
-} external_irq_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_external_irq_instance
-{
-    external_irq_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
-    external_irq_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
-    external_irq_api_t const * p_api;  ///< Pointer to the API structure for this instance
-} external_irq_instance_t;
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-/*******************************************************************************************************************//**
- * @} (end defgroup EXTERNAL_IRQ_API)
- **********************************************************************************************************************/
-
-#endif

bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_spi_api.h

@@ -1,299 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_SPI_API_H
-#define R_SPI_API_H
-
-/*****************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup SPI_API SPI Interface
- * @brief Interface for SPI communications.
- *
- * @section SPI_API_SUMMARY Summary
- * Provides a common interface for communication using the SPI Protocol.
- *
- * Implemented by:
- * - @ref SPI
- * - @ref SCI_SPI
- *
- * @{
- ********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Includes
- ********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-#include "r_transfer_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/*********************************************************************************************************************
- * Macro definitions
- ********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- ********************************************************************************************************************/
-
-/** Data bit width */
-typedef enum e_spi_bit_width
-{
-    SPI_BIT_WIDTH_4_BITS  = (3),       ///< Data bit width is 4 bits (byte)
-    SPI_BIT_WIDTH_5_BITS  = (4),       ///< Data bit width is 5 bits (byte)
-    SPI_BIT_WIDTH_6_BITS  = (5),       ///< Data bit width is 6 bits (byte)
-    SPI_BIT_WIDTH_7_BITS  = (6),       ///< Data bit width is 7 bits (byte)
-    SPI_BIT_WIDTH_8_BITS  = (7),       ///< Data bit width is 8 bits (byte)
-    SPI_BIT_WIDTH_9_BITS  = (8),       ///< Data bit width is 9 bits (word)
-    SPI_BIT_WIDTH_10_BITS = (9),       ///< Data bit width is 10 bits (word)
-    SPI_BIT_WIDTH_11_BITS = (10),      ///< Data bit width is 11 bits (word)
-    SPI_BIT_WIDTH_12_BITS = (11),      ///< Data bit width is 12 bits (word)
-    SPI_BIT_WIDTH_13_BITS = (12),      ///< Data bit width is 13 bits (word)
-    SPI_BIT_WIDTH_14_BITS = (13),      ///< Data bit width is 14 bits (word)
-    SPI_BIT_WIDTH_15_BITS = (14),      ///< Data bit width is 15 bits (word)
-    SPI_BIT_WIDTH_16_BITS = (15),      ///< Data bit width is 16 bits (word)
-    SPI_BIT_WIDTH_17_BITS = (16),      ///< Data bit width is 17 bits (word)
-    SPI_BIT_WIDTH_18_BITS = (17),      ///< Data bit width is 18 bits (word)
-    SPI_BIT_WIDTH_19_BITS = (18),      ///< Data bit width is 19 bits (word)
-    SPI_BIT_WIDTH_20_BITS = (19),      ///< Data bit width is 20 bits (longword)
-    SPI_BIT_WIDTH_21_BITS = (20),      ///< Data bit width is 21 bits (word)
-    SPI_BIT_WIDTH_22_BITS = (21),      ///< Data bit width is 22 bits (word)
-    SPI_BIT_WIDTH_23_BITS = (22),      ///< Data bit width is 23 bits (longword)
-    SPI_BIT_WIDTH_24_BITS = (23),      ///< Data bit width is 24 bits (longword)
-    SPI_BIT_WIDTH_25_BITS = (25),      ///< Data bit width is 25 bits (longword)
-    SPI_BIT_WIDTH_26_BITS = (25),      ///< Data bit width is 26 bits (word)
-    SPI_BIT_WIDTH_27_BITS = (26),      ///< Data bit width is 27 bits (word)
-    SPI_BIT_WIDTH_28_BITS = (27),      ///< Data bit width is 28 bits (word)
-    SPI_BIT_WIDTH_29_BITS = (28),      ///< Data bit width is 29 bits (word)
-    SPI_BIT_WIDTH_30_BITS = (29),      ///< Data bit width is 30 bits (longword)
-    SPI_BIT_WIDTH_31_BITS = (30),      ///< Data bit width is 31 bits (longword)
-    SPI_BIT_WIDTH_32_BITS = (31)       ///< Data bit width is 32 bits (longword)
-} spi_bit_width_t;
-
-/** Master or slave operating mode */
-typedef enum e_spi_mode
-{
-    SPI_MODE_MASTER,                   ///< Channel operates as SPI master
-    SPI_MODE_SLAVE                     ///< Channel operates as SPI slave
-} spi_mode_t;
-
-/** Clock phase */
-typedef enum e_spi_clk_phase
-{
-    SPI_CLK_PHASE_EDGE_ODD,            ///< 0: Data sampling on odd edge, data variation on even edge
-    SPI_CLK_PHASE_EDGE_EVEN            ///< 1: Data variation on odd edge, data sampling on even edge
-} spi_clk_phase_t;
-
-/** Clock polarity */
-typedef enum e_spi_clk_polarity
-{
-    SPI_CLK_POLARITY_LOW,              ///< 0: Clock polarity is low when idle
-    SPI_CLK_POLARITY_HIGH              ///< 1: Clock polarity is high when idle
-} spi_clk_polarity_t;
-
-/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be
- *  controlled by the master. This usually happens when the connecting device is also acting as master.
- *  A similar situation can also happen when configured as a slave. */
-typedef enum e_spi_mode_fault
-{
-    SPI_MODE_FAULT_ERROR_ENABLE,       ///< Mode fault error flag on
-    SPI_MODE_FAULT_ERROR_DISABLE       ///< Mode fault error flag off
-} spi_mode_fault_t;
-
-/** Bit order */
-typedef enum e_spi_bit_order
-{
-    SPI_BIT_ORDER_MSB_FIRST,           ///< Send MSB first in transmission
-    SPI_BIT_ORDER_LSB_FIRST            ///< Send LSB first in transmission
-} spi_bit_order_t;
-
-/** SPI events */
-typedef enum e_spi_event
-{
-    SPI_EVENT_TRANSFER_COMPLETE = 1,   ///< The data transfer was completed
-    SPI_EVENT_TRANSFER_ABORTED,        ///< The data transfer was aborted
-    SPI_EVENT_ERR_MODE_FAULT,          ///< Mode fault error
-    SPI_EVENT_ERR_READ_OVERFLOW,       ///< Read overflow error
-    SPI_EVENT_ERR_PARITY,              ///< Parity error
-    SPI_EVENT_ERR_OVERRUN,             ///< Overrun error
-    SPI_EVENT_ERR_FRAMING,             ///< Framing error
-    SPI_EVENT_ERR_MODE_UNDERRUN        ///< Underrun error
-} spi_event_t;
-
-/** Common callback parameter definition */
-typedef struct st_spi_callback_args
-{
-    uint32_t     channel;              ///< Device channel number
-    spi_event_t  event;                ///< Event code
-    void const * p_context;            ///< Context provided to user during callback
-} spi_callback_args_t;
-
-/** Non-secure arguments for write-read guard function */
-typedef struct st_spi_write_read_guard_args
-{
-    void const          * p_src;
-    void                * p_dest;
-    uint32_t const        length;
-    spi_bit_width_t const bit_width;
-} spi_write_read_guard_args_t;
-
-/** SPI interface configuration */
-typedef struct st_spi_cfg
-{
-    uint8_t channel;                                   ///< Channel number to be used
-
-    IRQn_Type                   rxi_irq;               ///< Receive Buffer Full IRQ number
-    IRQn_Type                   txi_irq;               ///< Transmit Buffer Empty IRQ number
-    IRQn_Type                   tei_irq;               ///< Transfer Complete IRQ number
-    IRQn_Type                   eri_irq;               ///< Error IRQ number
-    uint8_t                     rxi_ipl;               ///< Receive Interrupt priority
-    uint8_t                     txi_ipl;               ///< Transmit Interrupt priority
-    uint8_t                     tei_ipl;               ///< Transfer Complete Interrupt priority
-    uint8_t                     eri_ipl;               ///< Error Interrupt priority
-    spi_mode_t                  operating_mode;        ///< Select master or slave operating mode
-    spi_clk_phase_t             clk_phase;             ///< Data sampling on odd or even clock edge
-    spi_clk_polarity_t          clk_polarity;          ///< Clock level when idle
-    spi_mode_fault_t            mode_fault;            ///< Mode fault error (master/slave conflict) flag
-    spi_bit_order_t             bit_order;             ///< Select to transmit MSB/LSB first
-    transfer_instance_t const * p_transfer_tx;         ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here.  Set to NULL if unused.
-    transfer_instance_t const * p_transfer_rx;         ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here.  Set to NULL if unused.
-    void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function
-    void const * p_context;                            ///< User defined context passed to callback function
-    void const * p_extend;                             ///< Extended SPI hardware dependent configuration
-} spi_cfg_t;
-
-/** SPI control block.  Allocate an instance specific control block to pass into the SPI API calls.
- * @par Implemented as
- * - spi_instance_ctrl_t
- * - spi_b_instance_ctrl_t
- * - sci_spi_instance_ctrl_t
- */
-typedef void spi_ctrl_t;
-
-/** Shared Interface definition for SPI */
-typedef struct st_spi_api
-{
-    /** Initialize a channel for SPI communication mode.
-     * @par Implemented as
-     * - @ref R_SPI_Open()
-     * - @ref R_SPI_B_Open()
-     * - @ref R_SCI_SPI_Open()
-     *
-     * @param[in, out] p_ctrl Pointer to user-provided storage for the control block.
-     * @param[in]      p_cfg  Pointer to SPI configuration structure.
-     */
-    fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg);
-
-    /** Receive data from a SPI device.
-     * @par Implemented as
-     * - @ref R_SPI_Read()
-     * - @ref R_SPI_B_Read()
-     * - @ref R_SCI_SPI_Read()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the
-     *                       bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     * @param[out] p_dest    Pointer to destination buffer into which data will be copied that is received from a SPI
-     *                       device. It is the responsibility of the caller to ensure that adequate space is available
-     *                       to hold the requested data count.
-     */
-    fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length,
-                       spi_bit_width_t const bit_width);
-
-    /** Transmit data to a SPI device.
-     * @par Implemented as
-     * - @ref R_SPI_Write()
-     * - @ref R_SPI_B_Write()
-     * - @ref R_SCI_SPI_Write()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  p_src     Pointer to a source data buffer from which data will be transmitted to a SPI device.
-     *                       The argument must not be NULL.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the
-     *                       bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     */
-    fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length,
-                        spi_bit_width_t const bit_width);
-
-    /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex).
-     * @par Implemented as
-     * - @ref R_SPI_WriteRead()
-     * - @ref R_SPI_B_WriteRead()
-     * - @ref R_SCI_SPI_WriteRead()
-     *
-     * @param[in]  p_ctrl    Pointer to the control block for the channel.
-     * @param[in]  p_src     Pointer to a source data buffer from which data will be transmitted to a SPI device.
-     *                       The argument must not be NULL.
-     * @param[out] p_dest    Pointer to destination buffer into which data will be copied that is received from a SPI
-     *                       device. It is the responsibility of the caller to ensure that adequate space is available
-     *                       to hold the requested data count. The argument must not be NULL.
-     * @param[in]  length    Number of units of data to be transferred (unit size specified by the bit_width).
-     * @param[in]  bit_width Data bit width to be transferred.
-     */
-    fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length,
-                            spi_bit_width_t const bit_width);
-
-    /**
-     * Specify callback function and optional context pointer and working memory pointer.
-     * @par Implemented as
-     * - @ref R_SPI_CallbackSet()
-     * - @ref R_SPI_B_CallbackSet()
-     * - @ref R_SCI_SPI_CallbackSet()
-     *
-     * @param[in]   p_ctrl                   Pointer to the SPI control block.
-     * @param[in]   p_callback               Callback function
-     * @param[in]   p_context                Pointer to send to callback function
-     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
-     *                                       Callback arguments allocated here are only valid during the callback.
-     */
-    fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *),
-                              void const * const p_context, spi_callback_args_t * const p_callback_memory);
-
-    /** Remove power to the SPI channel designated by the handle and disable the associated interrupts.
-     * @par Implemented as
-     * - @ref R_SPI_Close()
-     * - @ref R_SPI_B_Close()
-     * - @ref R_SCI_SPI_Close()
-     *
-     * @param[in]  p_ctrl  Pointer to the control block for the channel.
-     */
-    fsp_err_t (* close)(spi_ctrl_t * const p_ctrl);
-} spi_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_spi_instance
-{
-    spi_ctrl_t      * p_ctrl;          ///< Pointer to the control structure for this instance
-    spi_cfg_t const * p_cfg;           ///< Pointer to the configuration structure for this instance
-    spi_api_t const * p_api;           ///< Pointer to the API structure for this instance
-} spi_instance_t;
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-/*****************************************************************************************************************//**
- * @} (end defgroup SPI_API)
- ********************************************************************************************************************/
-
-#endif

bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_dtc.h

@@ -1,106 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup DTC
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_DTC_H
-#define R_DTC_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "bsp_api.h"
-#include "r_transfer_api.h"
-#include "r_dtc_cfg.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** Max configurable number of transfers in NORMAL MODE */
-#define DTC_MAX_NORMAL_TRANSFER_LENGTH    (0x10000)
-
-/** Max number of transfers per repeat for REPEAT MODE */
-#define DTC_MAX_REPEAT_TRANSFER_LENGTH    (0x100)
-
-/** Max number of transfers per block in BLOCK MODE */
-#define DTC_MAX_BLOCK_TRANSFER_LENGTH     (0x100)
-
-/** Max configurable number of blocks to transfer in BLOCK MODE */
-#define DTC_MAX_BLOCK_COUNT               (0x10000)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** DTC transfer configuration extension. This extension is required. */
-typedef struct st_dtc_extended_cfg
-{
-    /** Select which IRQ will trigger the transfer. */
-    IRQn_Type activation_source;
-} dtc_extended_cfg_t;
-
-/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */
-typedef struct st_dtc_instance_ctrl
-{
-    uint32_t  open;                    // Driver ID
-    IRQn_Type irq;                     // Transfer activation IRQ number.
-} dtc_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const transfer_api_t g_transfer_on_dtc;
-
-/** @endcond */
-
-/**********************************************************************************************************************
- * Public Function Prototypes
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg);
-fsp_err_t R_DTC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info);
-fsp_err_t R_DTC_Reset(transfer_ctrl_t * const p_api_ctrl,
-                      void const * volatile   p_src,
-                      void * volatile         p_dest,
-                      uint16_t const          num_transfers);
-fsp_err_t R_DTC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode);
-fsp_err_t R_DTC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_Enable(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_Disable(transfer_ctrl_t * const p_api_ctrl);
-fsp_err_t R_DTC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties);
-fsp_err_t R_DTC_Close(transfer_ctrl_t * const p_api_ctrl);
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
-
-/*******************************************************************************************************************//**
- * @} (end defgroup DTC)
- **********************************************************************************************************************/

bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_icu.h

@@ -1,95 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup ICU
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_ICU_H
-#define R_ICU_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "bsp_api.h"
-#include "r_external_irq_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/*********************************************************************************************************************
- * Typedef definitions
- *********************************************************************************************************************/
-
-/** ICU private control block. DO NOT MODIFY.  Initialization occurs when R_ICU_ExternalIrqOpen is called. */
-typedef struct st_icu_instance_ctrl
-{
-    uint32_t  open;                                             ///< Used to determine if channel control block is in use
-    IRQn_Type irq;                                              ///< NVIC interrupt number
-    uint8_t   channel;                                          ///< Channel
-
-#if BSP_TZ_SECURE_BUILD
-    external_irq_callback_args_t * p_callback_memory;           // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
-#endif
-    void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin.
-
-    /** Placeholder for user data.  Passed to the user callback in ::external_irq_callback_args_t. */
-    void const * p_context;
-} icu_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const external_irq_api_t g_external_irq_on_icu;
-
-/** @endcond */
-
-/***********************************************************************************************************************
- * Public APIs
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg);
-
-fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl);
-
-fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl);
-
-fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const          p_api_ctrl,
-                                       void (                             * p_callback)(external_irq_callback_args_t *),
-                                       void const * const                   p_context,
-                                       external_irq_callback_args_t * const p_callback_memory);
-
-fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl);
-
-/*******************************************************************************************************************//**
- * @} (end defgroup ICU)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif                                 // R_ICU_H

bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_spi.h

@@ -1,201 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_SPI_H
-#define R_SPI_H
-
-/*******************************************************************************************************************//**
- * @addtogroup SPI
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_spi_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/*************************************************************************************************
- * Type defines for the SPI interface API
- *************************************************************************************************/
-
-/** 3-Wire or 4-Wire mode. */
-typedef enum e_spi_ssl_mode
-{
-    SPI_SSL_MODE_SPI,                  ///< SPI operation (4-wire method)
-    SPI_SSL_MODE_CLK_SYN               ///< Clock Synchronous operation (3-wire method)
-} spi_ssl_mode_t;
-
-/** Transmit Only (Half Duplex), or Full Duplex. */
-typedef enum e_spi_communication
-{
-    SPI_COMMUNICATION_FULL_DUPLEX,     ///< Full-Duplex synchronous serial communication
-    SPI_COMMUNICATION_TRANSMIT_ONLY    ///< Transit only serial communication
-} spi_communication_t;
-
-/** Slave Select Polarity. */
-typedef enum e_spi_sslp
-{
-    SPI_SSLP_LOW,                      ///< SSLP signal polarity active low
-    SPI_SSLP_HIGH                      ///< SSLP signal polarity active high
-} spi_ssl_polarity_t;
-
-/** The Slave Select Line */
-typedef enum e_spi_ssl_select
-{
-    SPI_SSL_SELECT_SSL0,               ///< Select SSL0
-    SPI_SSL_SELECT_SSL1,               ///< Select SSL1
-    SPI_SSL_SELECT_SSL2,               ///< Select SSL2
-    SPI_SSL_SELECT_SSL3                ///< Select SSL3
-} spi_ssl_select_t;
-
-/** MOSI Idle Behavior. */
-typedef enum e_spi_mosi_idle_value_fixing
-{
-    SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit
-    SPI_MOSI_IDLE_VALUE_FIXING_LOW,     ///< MOSIn level low during MOSI idling
-    SPI_MOSI_IDLE_VALUE_FIXING_HIGH     ///< MOSIn level high during MOSI idling
-} spi_mosi_idle_value_fixing_t;
-
-/** Parity Mode */
-typedef enum e_spi_parity_mode
-{
-    SPI_PARITY_MODE_DISABLE,           ///< Disable parity
-    SPI_PARITY_MODE_ODD,               ///< Select even parity
-    SPI_PARITY_MODE_EVEN               ///< Select odd parity
-} spi_parity_t;
-
-/** Byte Swapping Enable/Disable. */
-typedef enum
-{
-    SPI_BYTE_SWAP_DISABLE = 0,         ///< Disable Byte swapping for 16/32-Bit transfers
-    SPI_BYTE_SWAP_ENABLE               ///< Enable Byte swapping for 16/32-Bit transfers
-} spi_byte_swap_t;
-
-/** Delay count for SPI delay settings. */
-typedef enum e_spi_clock_delay_count
-{
-    SPI_DELAY_COUNT_1,                 ///< Set RSPCK delay count to 1 RSPCK
-    SPI_DELAY_COUNT_2,                 ///< Set RSPCK delay count to 2 RSPCK
-    SPI_DELAY_COUNT_3,                 ///< Set RSPCK delay count to 3 RSPCK
-    SPI_DELAY_COUNT_4,                 ///< Set RSPCK delay count to 4 RSPCK
-    SPI_DELAY_COUNT_5,                 ///< Set RSPCK delay count to 5 RSPCK
-    SPI_DELAY_COUNT_6,                 ///< Set RSPCK delay count to 6 RSPCK
-    SPI_DELAY_COUNT_7,                 ///< Set RSPCK delay count to 7 RSPCK
-    SPI_DELAY_COUNT_8                  ///< Set RSPCK delay count to 8 RSPCK
-} spi_delay_count_t;
-
-/** SPI Clock Divider settings. */
-typedef struct
-{
-    uint8_t spbr;                      ///< SPBR register setting
-    uint8_t brdv : 2;                  ///< BRDV setting in SPCMD0
-} rspck_div_setting_t;
-
-/** Extended SPI interface configuration */
-typedef struct st_spi_extended_cfg
-{
-    spi_ssl_mode_t               spi_clksyn;         ///< Select spi or clock syn mode operation
-    spi_communication_t          spi_comm;           ///< Select full-duplex or transmit-only communication
-    spi_ssl_polarity_t           ssl_polarity;       ///< Select SSLn signal polarity
-    spi_ssl_select_t             ssl_select;         ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3
-    spi_mosi_idle_value_fixing_t mosi_idle;          ///< Select MOSI idle fixed value and selection
-    spi_parity_t                 parity;             ///< Select parity and enable/disable parity
-    spi_byte_swap_t              byte_swap;          ///< Select byte swap mode
-    rspck_div_setting_t          spck_div;           ///< Register values for configuring the SPI Clock Divider.
-    spi_delay_count_t            spck_delay;         ///< SPI Clock Delay Register Setting
-    spi_delay_count_t            ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting
-    spi_delay_count_t            next_access_delay;  ///< SPI Next-Access Delay Register Setting
-} spi_extended_cfg_t;
-
-/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref spi_api_t::open is called. */
-typedef struct st_spi_instance_ctrl
-{
-    uint32_t          open;            ///< Indicates whether the open() API has been successfully called.
-    spi_cfg_t const * p_cfg;           ///< Pointer to instance configuration
-    R_SPI0_Type     * p_regs;          ///< Base register for this channel
-    void const      * p_tx_data;       ///< Buffer to transmit
-    void            * p_rx_data;       ///< Buffer to receive
-    uint32_t          tx_count;        ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)
-    uint32_t          rx_count;        ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)
-    uint32_t          count;           ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)
-    spi_bit_width_t   bit_width;       ///< Bits per Data frame (8-bit, 16-bit, 32-bit)
-
-    /* Pointer to callback and optional working memory */
-    void (* p_callback)(spi_callback_args_t *);
-    spi_callback_args_t * p_callback_memory;
-
-    /* Pointer to context to be passed into callback function */
-    void const * p_context;
-} spi_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Filled in Interface API structure for this Instance. */
-extern const spi_api_t g_spi_on_spi;
-
-/** @endcond */
-
-/***********************************************************************************************************************
- * Public APIs
- **********************************************************************************************************************/
-fsp_err_t R_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg);
-
-fsp_err_t R_SPI_Read(spi_ctrl_t * const    p_api_ctrl,
-                     void                * p_dest,
-                     uint32_t const        length,
-                     spi_bit_width_t const bit_width);
-
-fsp_err_t R_SPI_Write(spi_ctrl_t * const    p_api_ctrl,
-                      void const          * p_src,
-                      uint32_t const        length,
-                      spi_bit_width_t const bit_width);
-
-fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const    p_api_ctrl,
-                          void const          * p_src,
-                          void                * p_dest,
-                          uint32_t const        length,
-                          spi_bit_width_t const bit_width);
-
-fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl);
-
-fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div);
-fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const          p_api_ctrl,
-                            void (                    * p_callback)(spi_callback_args_t *),
-                            void const * const          p_context,
-                            spi_callback_args_t * const p_callback_memory);
-
-/*******************************************************************************************************************//**
- * @} (end ingroup SPI)
- **********************************************************************************************************************/
-
-/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif

bsp/renesas/ra6m4-cpk/ra/fsp/src/r_dtc/r_dtc.c

@@ -1,611 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include <string.h>
-#include "r_dtc.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** Driver ID (DTC in ASCII), used to identify Data Transfer Controller (DTC) configuration  */
-#define DTC_OPEN                    (0x44544300)
-
-/** Size of vector table is based on number of vectors defined in BSP. */
-#define DTC_VECTOR_TABLE_ENTRIES    (BSP_ICU_VECTOR_MAX_ENTRIES)
-
-/** The size of transfer_info_t is defined in the Hardware Manual therefore it must be 16 bytes. */
-#define DTC_TRANSFER_INFO_SIZE      (16U)
-
-/* Compiler specific macro to specify vector table section. */
-#ifndef DTC_CFG_VECTOR_TABLE_SECTION_NAME
- #define DTC_SECTION_ATTRIBUTE
- #ifndef SUPPRESS_WARNING_DTC_CFG_VECTOR_TABLE_SECTION_NAME
-  #warning "DTC vector table is aligned on 1K boundary. Automatic placing could lead to memory holes."
- #endif
-#else
- #define DTC_SECTION_ATTRIBUTE    BSP_PLACE_IN_SECTION(DTC_CFG_VECTOR_TABLE_SECTION_NAME)
-#endif
-
-/* Used to generate a compiler error (divided by 0 error) if the assertion fails.  This is used in place of "#error"
- * for expressions that cannot be evaluated by the preprocessor like sizeof(). */
-#define DTC_COMPILE_TIME_ASSERT(e)       ((void) sizeof(char[1 - 2 * !(e)]))
-
-/* Calculate the mask bits for byte alignment from the transfer_size_t. */
-#define DTC_PRV_MASK_ALIGN_N_BYTES(x)    ((1U << (x)) - 1U)
-
-/* Counter Register A Lower Byte Mask */
-#define DTC_PRV_MASK_CRAL             (0xFFU)
-
-/* Counter Register A Upper Byte Offset */
-#define DTC_PRV_OFFSET_CRAH           (8U)
-
-/* Offset of in_progress bit in R_DTC->DTCSTS. */
-#define DTC_PRV_OFFSET_IN_PROGRESS    (15U)
-
-/* DTC Control Register RRS Enable value. */
-#define DTC_PRV_RRS_ENABLE            (0x18)
-
-/* DTC Control Register RRS Disable value. */
-#define DTC_PRV_RRS_DISABLE           (0x08)
-
-/***********************************************************************************************************************
- * Private function prototypes
- **********************************************************************************************************************/
-
-static fsp_err_t r_dtc_prv_enable(dtc_instance_ctrl_t * p_ctrl);
-static void      r_dtc_state_initialize(void);
-static void      r_dtc_block_repeat_initialize(transfer_info_t * p_info);
-static void      r_dtc_set_info(dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info);
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
- #if BSP_CFG_ASSERT != 3
-static fsp_err_t r_dtc_length_assert(transfer_info_t * p_info);
-
- #endif
-static fsp_err_t r_dtc_source_destination_parameter_check(transfer_info_t * p_info);
-
-#endif
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-static transfer_info_t * gp_dtc_vector_table[DTC_VECTOR_TABLE_ENTRIES] BSP_ALIGN_VARIABLE(1024)
-DTC_SECTION_ATTRIBUTE;
-
-/***********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** DTC implementation of transfer API. */
-const transfer_api_t g_transfer_on_dtc =
-{
-    .open          = R_DTC_Open,
-    .reconfigure   = R_DTC_Reconfigure,
-    .reset         = R_DTC_Reset,
-    .infoGet       = R_DTC_InfoGet,
-    .softwareStart = R_DTC_SoftwareStart,
-    .softwareStop  = R_DTC_SoftwareStop,
-    .enable        = R_DTC_Enable,
-    .disable       = R_DTC_Disable,
-    .close         = R_DTC_Close,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup DTC
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configure the vector table if it hasn't been configured, enable the Module and copy the pointer to the transfer info
- * into the DTC vector table. Implements @ref transfer_api_t::open.
- *
- * Example:
- * @snippet r_dtc_example.c R_DTC_Open
- *
- * @retval FSP_SUCCESS              Successful open.
- *                                      Transfer transfer info pointer copied to DTC Vector table.
- *                                      Module started.
- *                                      DTC vector table configured.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- * @retval FSP_ERR_ALREADY_OPEN     The control structure is already opened.
- * @retval FSP_ERR_IN_USE           The index for this IRQ in the DTC vector table is already configured.
- * @retval FSP_ERR_IRQ_BSP_DISABLED The IRQ associated with the activation source is not enabled in the BSP.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg)
-{
-    /* Generate a compiler error if transfer_info_t is modified. */
-    DTC_COMPILE_TIME_ASSERT(sizeof(transfer_info_t) == DTC_TRANSFER_INFO_SIZE);
-
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open != DTC_OPEN, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ASSERT(NULL != p_cfg->p_extend);
-    FSP_ASSERT(NULL != p_cfg->p_info);
-    fsp_err_t err = r_dtc_length_assert(p_cfg->p_info);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
-    /* One time initialization for all DTC instances. */
-    r_dtc_state_initialize();
-
-    /* Make sure the activation source is mapped in the ICU. */
-    dtc_extended_cfg_t * p_dtc_cfg = (dtc_extended_cfg_t *) p_cfg->p_extend;
-    IRQn_Type            irq       = p_dtc_cfg->activation_source;
-    FSP_ERROR_RETURN(irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED);
-
-    /* Make sure the activation source is not already being used by the DTC. */
-    FSP_ERROR_RETURN(NULL == gp_dtc_vector_table[irq], FSP_ERR_IN_USE);
-
-    /* irq is used to index the DTC vector table. */
-    p_ctrl->irq = irq;
-
-    /* Copy p_info into the DTC vector table. */
-    r_dtc_set_info(p_ctrl, p_cfg->p_info);
-
-    /* Mark driver as open by initializing it to "DTC" in its ASCII equivalent. */
-    p_ctrl->open = DTC_OPEN;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Copy pointer to transfer info into the DTC vector table and enable transfer in ICU.
- * Implements @ref transfer_api_t::reconfigure.
- *
- * @retval FSP_SUCCESS              Transfer is configured and will start when trigger occurs.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_NOT_ENABLED      Transfer source address is NULL or is not aligned corrrectly.
- *                                  Transfer destination address is NULL or is not aligned corrrectly.
- *
- * @note p_info must persist until all transfers are completed.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Reconfigure (transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_info);
-    FSP_ASSERT(FSP_SUCCESS == r_dtc_length_assert(p_info));
-#endif
-
-    /* Disable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Wait for current transfer to finish. */
-    uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS;
-    while (in_progress == R_DTC->DTCSTS)
-    {
-        ;
-    }
-
-    /* Copy p_info into the DTC vector table. */
-    r_dtc_set_info(p_ctrl, p_info);
-
-    /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */
-    /* Enable transfers on this activation source. */
-    FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Reset transfer source, destination, and number of transfers. Implements @ref transfer_api_t::reset.
- *
- * @retval FSP_SUCCESS              Transfer reset successfully (transfers are enabled).
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_NOT_ENABLED      Transfer source address is NULL or is not aligned corrrectly.
- *                                  Transfer destination address is NULL or is not aligned corrrectly.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl,
-                       void const * volatile   p_src,
-                       void * volatile         p_dest,
-                       uint16_t const          num_transfers)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Disable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Wait for current transfer to finish. */
-    uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS;
-    while (in_progress == R_DTC->DTCSTS)
-    {
-        ;
-    }
-
-    /* Disable read skip prior to modifying settings. It will be enabled later
-     * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */
-#if FSP_PRIV_TZ_USE_SECURE_REGS
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_DISABLE;
-#endif
-
-    /* Reset transfer based on input parameters. */
-    if (NULL != p_src)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->p_src = p_src;
-    }
-
-    if (NULL != p_dest)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->p_dest = p_dest;
-    }
-
-    if (TRANSFER_MODE_BLOCK == gp_dtc_vector_table[p_ctrl->irq]->mode)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->num_blocks = num_transfers;
-    }
-    else if (TRANSFER_MODE_NORMAL == gp_dtc_vector_table[p_ctrl->irq]->mode)
-    {
-        gp_dtc_vector_table[p_ctrl->irq]->length = num_transfers;
-    }
-    else                               /* (TRANSFER_MODE_REPEAT == gp_dtc_vector_table[p_ctrl->irq]->mode) */
-    {
-        /* Do nothing. */
-    }
-
-    /* Enable read skip after all settings are written. */
-#if FSP_PRIV_TZ_USE_SECURE_REGS
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_ENABLE;
-#endif
-
-    /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */
-    /* Enable transfers on this activation source. */
-    FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Placeholder for unsupported softwareStart function. Implements @ref transfer_api_t::softwareStart.
- *
- * @retval FSP_ERR_UNSUPPORTED      DTC software start is not supported.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_SoftwareStart (transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode)
-{
-    /* This function isn't supported.  It is defined only to implement a required function of transfer_api_t.
-     * Mark the input parameter as unused since this function isn't supported. */
-    FSP_PARAMETER_NOT_USED(p_api_ctrl);
-    FSP_PARAMETER_NOT_USED(mode);
-
-    return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * Placeholder for unsupported softwareStop function. Implements @ref transfer_api_t::softwareStop.
- *
- * @retval FSP_ERR_UNSUPPORTED      DTC software stop is not supported.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_SoftwareStop (transfer_ctrl_t * const p_api_ctrl)
-{
-    /* This function isn't supported.  It is defined only to implement a required function of transfer_api_t.
-     * Mark the input parameter as unused since this function isn't supported. */
-    FSP_PARAMETER_NOT_USED(p_api_ctrl);
-
-    return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * Enable transfers on this activation source. Implements @ref transfer_api_t::enable.
- *
- * Example:
- * @snippet r_dtc_example.c R_DTC_Enable
- *
- * @retval FSP_SUCCESS              Transfers will be triggered by the activation source
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Enable (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    return r_dtc_prv_enable(p_ctrl);
-}
-
-/*******************************************************************************************************************//**
- * Disable transfer on this activation source. Implements @ref transfer_api_t::disable.
- *
- * @retval FSP_SUCCESS              Transfers will not occur on activation events.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Disable (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Disable transfer. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Provides information about this transfer. Implements @ref transfer_api_t::infoGet.
- *
- * @retval FSP_SUCCESS              p_info updated with current instance information.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized. Call R_DTC_Open to initialize the control block.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_InfoGet (transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_properties);
-#endif
-
-    transfer_info_t * p_info = gp_dtc_vector_table[p_ctrl->irq];
-
-    p_properties->block_count_max       = 0U;
-    p_properties->block_count_remaining = 0U;
-
-    if (TRANSFER_MODE_NORMAL != p_info->mode)
-    {
-        /* Repeat and Block Mode */
-
-        /* transfer_length_max is the same for Block and repeat mode. */
-        p_properties->transfer_length_max       = DTC_MAX_REPEAT_TRANSFER_LENGTH;
-        p_properties->transfer_length_remaining = p_info->length & DTC_PRV_MASK_CRAL;
-
-        if (TRANSFER_MODE_BLOCK == p_info->mode)
-        {
-            p_properties->block_count_max       = DTC_MAX_BLOCK_COUNT;
-            p_properties->block_count_remaining = p_info->num_blocks;
-        }
-    }
-    else
-    {
-        p_properties->transfer_length_max       = DTC_MAX_NORMAL_TRANSFER_LENGTH;
-        p_properties->transfer_length_remaining = p_info->length;
-    }
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disables DTC activation in the ICU, then clears transfer data from the DTC vector table.
- * Implements @ref transfer_api_t::close.
- *
- * @retval FSP_SUCCESS              Successful close.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_NOT_OPEN         Handle is not initialized.  Call R_DTC_Open to initialize the control block.
- **********************************************************************************************************************/
-fsp_err_t R_DTC_Close (transfer_ctrl_t * const p_api_ctrl)
-{
-    dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl;
-    fsp_err_t             err    = FSP_SUCCESS;
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Clear DTC enable bit in ICU. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U;
-
-    /* Clear pointer in vector table. */
-    gp_dtc_vector_table[p_ctrl->irq] = NULL;
-
-    /* Mark instance as closed. */
-    p_ctrl->open = 0U;
-
-    return err;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup DTC)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Verify that the source and destination pointers are valid then enable the DTC.
- *
- * @retval FSP_SUCCESS              Successfully enabled
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_prv_enable (dtc_instance_ctrl_t * p_ctrl)
-{
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-    fsp_err_t err = r_dtc_source_destination_parameter_check(gp_dtc_vector_table[p_ctrl->irq]);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
-    /* Enable transfers on this activation source. */
-    R_ICU->IELSR_b[p_ctrl->irq].DTCE = 1U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * One time state initialization for all DTC instances.
- **********************************************************************************************************************/
-static void r_dtc_state_initialize (void)
-{
-    /* Stores initialization state to skip initialization in ::R_DTC_Open after the first call. */
-    static bool g_dtc_state_initialized = false;
-
-    /* DTC requires a one time initialization.  This will be handled only the first time this function
-     *  is called. This initialization:
-     *  -# Stores the register base addresses for DTC and ICU.
-     *  -# Powers on the DTC block.
-     *  -# Initializes the vector table to NULL pointers.
-     *  -# Sets the vector table base address.
-     *  -# Enables DTC transfers. */
-    if (!g_dtc_state_initialized)
-    {
-        g_dtc_state_initialized = true;
-
-        /** Power on DTC */
-        R_BSP_MODULE_START(FSP_IP_DTC, 0);
-
-        /* The DTC vector table must be cleared during initialization because it is located in
-         * its own section outside of the .BSS section which is cleared during startup. */
-        memset(&gp_dtc_vector_table, 0U, DTC_VECTOR_TABLE_ENTRIES * sizeof(transfer_info_t *));
-
-        /* Set DTC vector table. */
-#if FSP_PRIV_TZ_USE_SECURE_REGS
-        R_DTC->DTCVBR_SEC = (uint32_t) gp_dtc_vector_table;
-#else
-        R_DTC->DTCVBR = (uint32_t) gp_dtc_vector_table;
-#endif
-
-        /* Enable the DTC Peripheral */
-        R_DTC->DTCST = 1U;
-    }
-}
-
-/*******************************************************************************************************************//**
- * Configure the p_info state and write p_info to DTC vector table.
- **********************************************************************************************************************/
-static void r_dtc_set_info (dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info)
-{
-    /* Update internal variables. */
-    r_dtc_block_repeat_initialize(p_info);
-
-    /* Disable read skip prior to modifying settings. It will be enabled later
-     * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */
-#if FSP_PRIV_TZ_USE_SECURE_REGS
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_DISABLE;
-#endif
-
-    /* Update the entry in the DTC Vector table. */
-    gp_dtc_vector_table[p_ctrl->irq] = p_info;
-
-    /* Enable read skip after all settings are written. */
-#if DTC_PRV_USE_SECURE_REGS
-    R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE;
-#else
-    R_DTC->DTCCR = DTC_PRV_RRS_ENABLE;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Configure the length setting for block and repeat mode.
- **********************************************************************************************************************/
-static void r_dtc_block_repeat_initialize (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        /* Update the CRA register to the desired settings */
-        if (TRANSFER_MODE_NORMAL != p_info[i].mode)
-        {
-            uint8_t CRAL = p_info[i].length & DTC_PRV_MASK_CRAL;
-            p_info[i].length = (uint16_t) ((CRAL << DTC_PRV_OFFSET_CRAH) | CRAL);
-        }
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */
-}
-
-#if DTC_CFG_PARAM_CHECKING_ENABLE
-
- #if BSP_CFG_ASSERT != 3
-
-/*******************************************************************************************************************//**
- * Check to make sure that the length is valid for block and repeat mode.
- *
- * @retval FSP_SUCCESS              Parameters are valid.
- * @retval FSP_ERR_ASSERTION        Invalid length for block or repeat mode.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- *
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_length_assert (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].src_addr_mode, FSP_ERR_UNSUPPORTED);
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].dest_addr_mode, FSP_ERR_UNSUPPORTED);
-
-        if (TRANSFER_MODE_NORMAL != p_info[i].mode)
-        {
-            /* transfer_length_max is the same for Block and repeat mode. */
-            FSP_ASSERT(p_info[i].length <= DTC_MAX_REPEAT_TRANSFER_LENGTH);
-        }
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */
-
-    return FSP_SUCCESS;
-}
-
- #endif
-
-/*******************************************************************************************************************//**
- * Check that the source and destination are not NULL and that they are aligned correctly.
- *
- * @retval FSP_SUCCESS              Parameters are valid.
- * @retval FSP_ERR_ASSERTION        An input parameter is invalid.
- * @retval FSP_ERR_UNSUPPORTED      Address Mode Offset is selected.
- *
- **********************************************************************************************************************/
-static fsp_err_t r_dtc_source_destination_parameter_check (transfer_info_t * p_info)
-{
-    uint32_t i = 0;
-    do
-    {
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].src_addr_mode, FSP_ERR_UNSUPPORTED);
-        FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].dest_addr_mode, FSP_ERR_UNSUPPORTED);
-        FSP_ASSERT(NULL != p_info[i].p_src);
-        FSP_ASSERT(NULL != p_info[i].p_dest);
-        FSP_ASSERT(0U == ((uint32_t) p_info[i].p_dest & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].size)));
-        FSP_ASSERT(0U == ((uint32_t) p_info[i].p_src & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].size)));
-    } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */
-
-    return FSP_SUCCESS;
-}
-
-#endif

bsp/renesas/ra6m4-cpk/ra/fsp/src/r_icu/r_icu.c

@@ -1,370 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_icu.h"
-#include "r_icu_cfg.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** "ICU" in ASCII, used to determine if channel is open. */
-#define ICU_OPEN              (0x00494355U)
-
-#define ICU_IRQMD_OFFSET      (0)
-#define ICU_FCLKSEL_OFFSET    (4)
-#define ICU_FLTEN_OFFSET      (7)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private function prototypes
- **********************************************************************************************************************/
-void r_icu_isr(void);
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Global Variables
- **********************************************************************************************************************/
-
-/* ICU implementation of External IRQ API. */
-const external_irq_api_t g_external_irq_on_icu =
-{
-    .open        = R_ICU_ExternalIrqOpen,
-    .enable      = R_ICU_ExternalIrqEnable,
-    .disable     = R_ICU_ExternalIrqDisable,
-    .callbackSet = R_ICU_ExternalIrqCallbackSet,
-    .close       = R_ICU_ExternalIrqClose,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup ICU
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configure an IRQ input pin for use with the external interrupt interface.  Implements @ref external_irq_api_t::open.
- *
- * The Open function is responsible for preparing an external IRQ pin for operation.
- *
- * @retval FSP_SUCCESS                    Open successful.
- * @retval FSP_ERR_ASSERTION              One of the following is invalid:
- *                                          - p_ctrl or p_cfg is NULL
- * @retval FSP_ERR_ALREADY_OPEN           The channel specified has already been opened. No configurations were changed.
- *                                        Call the associated Close function to reconfigure the channel.
- * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in
- *                                        r_bsp_cfg.h.
- * @retval FSP_ERR_INVALID_ARGUMENT       p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to
- *                                        use callback function.
- *
- * @note This function is reentrant for different channels.  It is not reentrant for the same channel.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
-
-    /* Callback must be used with a valid interrupt priority otherwise it will never be called. */
-    if (p_cfg->p_callback)
-    {
-        FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT);
-    }
-#endif
-
-    p_ctrl->irq = p_cfg->irq;
-
-    /* IELSR Must be zero when modifying the IRQCR bits.
-     * (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */
-    uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq];
-    R_ICU->IELSR[p_ctrl->irq] = 0;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* If this is a secure build, the callback provided in p_cfg must be secure. */
-    p_ctrl->p_callback_memory = NULL;
-#endif
-
-    /* Initialize control block. */
-    p_ctrl->p_callback = p_cfg->p_callback;
-    p_ctrl->p_context  = p_cfg->p_context;
-    p_ctrl->channel    = p_cfg->channel;
-
-    /* Disable digital filter */
-    R_ICU->IRQCR[p_ctrl->channel] = 0U;
-
-    /* Set the digital filter divider. */
-    uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET);
-
-    /* Enable/Disable digital filter. */
-    irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET);
-
-    /* Set the IRQ trigger. */
-    irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET);
-
-    /* Write IRQCR */
-    R_ICU->IRQCR[p_ctrl->channel] = irqcr;
-
-    /* Restore IELSR. */
-    R_ICU->IELSR[p_ctrl->irq] = ielsr;
-
-    /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases
-     * where the external IRQ driver is used to generate ELC events only (without CPU interrupts).
-     * In such cases we will not set the IRQ priority but will continue with the processing.
-     */
-    if (p_ctrl->irq >= 0)
-    {
-        R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl);
-    }
-
-    /* Mark the control block as open */
-    p_ctrl->open = ICU_OPEN;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable.
- *
- * @retval FSP_SUCCESS                 Interrupt Enabled successfully.
- * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
- * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
- * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
-#endif
-
-    /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */
-    R_BSP_IrqEnable(p_ctrl->irq);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable.
- *
- * @retval FSP_SUCCESS                 Interrupt disabled successfully.
- * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
- * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
- * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
-#endif
-
-    /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
-    R_BSP_IrqDisable(p_ctrl->irq);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback and has option of providing memory for callback structure.
- * Implements external_irq_api_t::callbackSet
- *
- * @retval  FSP_SUCCESS                  Callback updated successfully.
- * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
- * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
- * @retval  FSP_ERR_NO_CALLBACK_MEMORY   p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl,
-                                        void (                    * p_callback)(
-                                            external_irq_callback_args_t *),
-                                        void const * const                   p_context,
-                                        external_irq_callback_args_t * const p_callback_memory)
-{
-    icu_instance_ctrl_t * p_ctrl = p_api_ctrl;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* cmse_check_address_range returns NULL if p_callback is located in secure memory */
-    bool callback_is_secure =
-        (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-#else
-    FSP_PARAMETER_NOT_USED(p_callback_memory);
-#endif
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(NULL != p_callback);
-
- #if BSP_TZ_SECURE_BUILD
-
-    /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
-    external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
-                                                                                               CMSE_AU_NONSECURE);
-    FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-#endif
-
-#if BSP_TZ_SECURE_BUILD
-    p_ctrl->p_callback_memory = p_callback_memory;
-    p_ctrl->p_callback        = callback_is_secure ? p_callback :
-                                (void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
-    p_ctrl->p_callback = p_callback;
-#endif
-    p_ctrl->p_context = p_context;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Close the external interrupt channel. Implements @ref external_irq_api_t::close.
- *
- * @retval     FSP_SUCCESS          Successfully closed.
- * @retval     FSP_ERR_ASSERTION    The parameter p_ctrl is NULL.
- * @retval     FSP_ERR_NOT_OPEN     The channel is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl)
-{
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
-
-#if ICU_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-    /* Cleanup. Disable interrupt */
-    if (p_ctrl->irq >= 0)
-    {
-        /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
-        R_BSP_IrqDisable(p_ctrl->irq);
-        R_FSP_IsrContextSet(p_ctrl->irq, NULL);
-    }
-
-    p_ctrl->open = 0U;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup ICU)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * ICU External Interrupt ISR.
- **********************************************************************************************************************/
-void r_icu_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE
-
-    IRQn_Type             irq    = R_FSP_CurrentIrqGet();
-    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    bool level_irq = false;
-    if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD)
-    {
-        level_irq = true;
-    }
-    else
-    {
-        /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active
-         * it will not be missed. */
-        R_BSP_IrqStatusClear(irq);
-    }
-
-    if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback))
-    {
-#if BSP_TZ_SECURE_BUILD
-
-        /* p_callback can point to a secure function or a non-secure function. */
-        external_irq_callback_args_t args;
-        if (!cmse_is_nsfptr(p_ctrl->p_callback))
-        {
-            /* If p_callback is secure, then the project does not need to change security state. */
-            args.channel   = p_ctrl->channel;
-            args.p_context = p_ctrl->p_context;
-            p_ctrl->p_callback(&args);
-        }
-        else
-        {
-            /* Save current state of p_callback_args so that it can be shared between interrupts. */
-            args = *p_ctrl->p_callback_memory;
-
-            /* Set the callback args passed to the Non-secure calback. */
-            p_ctrl->p_callback_memory->channel   = p_ctrl->channel;
-            p_ctrl->p_callback_memory->p_context = p_ctrl->p_context;
-
-            /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
-            icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback);
-            p_callback(p_ctrl->p_callback_memory);
-
-            /* Restore the state of p_callback_args. */
-            *p_ctrl->p_callback_memory = args;
-        }
-
-#else
-
-        /* Set data to identify callback to user, then call user callback. */
-        external_irq_callback_args_t args;
-        args.channel   = p_ctrl->channel;
-        args.p_context = p_ctrl->p_context;
-        p_ctrl->p_callback(&args);
-#endif
-    }
-
-    if (level_irq)
-    {
-        /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not
-         * be called again. */
-        R_BSP_IrqStatusClear(irq);
-    }
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE
-}

bsp/renesas/ra6m4-cpk/ra/fsp/src/r_spi/r_spi.c

@@ -1,1208 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_spi.h"
-#include "r_spi_cfg.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/** "SPI" in ASCII, used to determine if channel is open. */
-#define SPI_OPEN                        (0x52535049ULL)
-
-/** SPI base register access macro.  */
-#define SPI_REG(channel)    ((R_SPI0_Type *) ((uint32_t) R_SPI0 +                       \
-                                              ((uint32_t) R_SPI1 - (uint32_t) R_SPI0) * \
-                                              (channel)))
-
-#define SPI_DTC_MAX_TRANSFER            (0x10000)
-
-#define SPI_DTC_RX_TRANSFER_SETTINGS    ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) |         \
-                                         (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) |         \
-                                         (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \
-                                         (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) |              \
-                                         (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS))
-
-#define SPI_DTC_TX_TRANSFER_SETTINGS    ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) |               \
-                                         (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) |               \
-                                         (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \
-                                         (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) |                    \
-                                         (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS))
-
-#define SPI_CLK_N_DIV_MULTIPLIER        (512U)                              ///< Maximum divider for N=0
-#define SPI_CLK_MAX_DIV                 (4096U)                             ///< Maximum SPI CLK divider
-#define SPI_CLK_MIN_DIV                 (2U)                                ///< Minimum SPI CLK divider
-
-/* SPCMD0 Bit Field Definitions */
-#define R_SPI0_SPCMD0_CPHA_Pos          (0U)                                ///< Clock Phase setting offset
-#define R_SPI0_SPCMD0_CPHA_Msk          (1U << R_SPI0_SPCMD0_CPHA_Pos)      ///< Clock Phase setting mask
-#define R_SPI0_SPCMD0_CPOL_Pos          (1U)                                ///< Clock Polarity setting offset
-#define R_SPI0_SPCMD0_CPOL_Msk          (1U << R_SPI0_SPCMD0_CPOL_Pos)      ///< Clock Polarity setting mask
-#define R_SPI0_SPCMD0_BRDV_Pos          (2U)                                ///< Bitrate division setting offset
-#define R_SPI0_SPCMD0_BRDV_Msk          (0x0003U << R_SPI0_SPCMD0_BRDV_Pos) ///< Bitrate division setting mask
-#define R_SPI0_SPCMD0_SSLA_Pos          (4U)                                ///< SSL Signal selection setting offset
-#define R_SPI0_SPCMD0_SSLA_Msk          (0x0007U << R_SPI0_SPCMD0_SSLA_Pos) ///< SSL Signal selection setting mask
-#define R_SPI0_SPCMD0_SSLKP_Pos         (7U)                                ///< SSL Level Keep setting offset
-#define R_SPI0_SPCMD0_SSLKP_Msk         (1U << R_SPI0_SPCMD0_SSLKP_Pos)     ///< SSL Level Keep setting mask
-#define R_SPI0_SPCMD0_SPB_Pos           (8U)                                ///< Bit Width setting offset
-#define R_SPI0_SPCMD0_SPB_Msk           (0x000FU << R_SPI0_SPCMD0_SPB_Pos)  ///< Bit Width setting mask
-#define R_SPI0_SPCMD0_LSBF_Pos          (12U)                               ///< LSB/MSB setting offset
-#define R_SPI0_SPCMD0_LSBF_Msk          (1U << R_SPI0_SPCMD0_LSBF_Pos)      ///< LSB/MSB setting mask
-#define R_SPI0_SPCMD0_SPNDEN_Pos        (13)                                ///< SPI Next-Access Delay Enable setting offset
-#define R_SPI0_SPCMD0_SPNDEN_Msk        (1U << R_SPI0_SPCMD0_SPNDEN_Pos)    ///< SPI Next-Access Delay Enable setting mask
-#define R_SPI0_SPCMD0_SLNDEN_Pos        (14)                                ///< SSL Negation Delay Setting Enable setting offset
-#define R_SPI0_SPCMD0_SLNDEN_Msk        (1U << R_SPI0_SPCMD0_SLNDEN_Pos)    ///< SSL Negation Delay Setting Enable setting mask
-#define R_SPI0_SPCMD0_SCKDEN_Pos        (15)                                ///< RSPCK Delay Setting Enable setting offset
-#define R_SPI0_SPCMD0_SCKDEN_Msk        (1U << R_SPI0_SPCMD0_SCKDEN_Pos)    ///< RSPCK Delay Setting Enable setting mask
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * spi_prv_ns_callback)(spi_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_prv_ns_callback)(spi_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private function declarations
- **********************************************************************************************************************/
-static fsp_err_t r_spi_transfer_config(spi_cfg_t const * const p_cfg);
-static void      r_spi_hw_config(spi_instance_ctrl_t * p_ctrl);
-static void      r_spi_nvic_config(spi_instance_ctrl_t * p_ctrl);
-
-static void      r_spi_bit_width_config(spi_instance_ctrl_t * p_ctrl);
-static void      r_spi_start_transfer(spi_instance_ctrl_t * p_ctrl);
-static fsp_err_t r_spi_write_read_common(spi_ctrl_t * const    p_api_ctrl,
-                                         void const          * p_src,
-                                         void                * p_dest,
-                                         uint32_t const        length,
-                                         spi_bit_width_t const bit_width);
-
-static void r_spi_receive(spi_instance_ctrl_t * p_ctrl);
-static void r_spi_transmit(spi_instance_ctrl_t * p_ctrl);
-static void r_spi_call_callback(spi_instance_ctrl_t * p_ctrl, spi_event_t event);
-
-/***********************************************************************************************************************
- * ISR prototypes
- **********************************************************************************************************************/
-void spi_rxi_isr(void);
-void spi_txi_isr(void);
-void spi_tei_isr(void);
-void spi_eri_isr(void);
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Global variables
- **********************************************************************************************************************/
-
-/* SPI implementation of SPI interface. */
-const spi_api_t g_spi_on_spi =
-{
-    .open        = R_SPI_Open,
-    .read        = R_SPI_Read,
-    .write       = R_SPI_Write,
-    .writeRead   = R_SPI_WriteRead,
-    .close       = R_SPI_Close,
-    .callbackSet = R_SPI_CallbackSet
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup SPI
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * This functions initializes a channel for SPI communication mode. Implements @ref spi_api_t::open.
- *
- * This function performs the following tasks:
- * - Performs parameter checking and processes error conditions.
- * - Configures the pperipheral registers acording to the configuration.
- * - Initialize the control structure for use in other @ref SPI_API functions.
- *
- * @retval     FSP_SUCCESS                     Channel initialized successfully.
- * @retval     FSP_ERR_ALREADY_OPEN            Instance was already initialized.
- * @retval     FSP_ERR_ASSERTION               An invalid argument was given in the configuration structure.
- * @retval     FSP_ERR_UNSUPPORTED             A requested setting is not possible on this device with the current build
- *                                             configuration.
- * @retval     FSP_ERR_IP_CHANNEL_NOT_PRESENT  The channel number is invalid.
- * @return     See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This
- *             function calls: @ref transfer_api_t::open
- * @note       This function is reentrant.
- **********************************************************************************************************************/
-fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg)
-{
-    fsp_err_t err = FSP_SUCCESS;
-
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
-    FSP_ASSERT(NULL != p_cfg);
-    FSP_ASSERT(NULL != p_cfg->p_callback);
-    FSP_ASSERT(NULL != p_cfg->p_extend);
-    FSP_ERROR_RETURN(BSP_FEATURE_SPI_MAX_CHANNEL > p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT);
-    FSP_ASSERT(p_cfg->rxi_irq >= 0);
-    FSP_ASSERT(p_cfg->txi_irq >= 0);
-    FSP_ASSERT(p_cfg->tei_irq >= 0);
-    FSP_ASSERT(p_cfg->eri_irq >= 0);
-
-    /* CPHA=0 is not supported in slave mode because of hardware limitations. Reference section 38.3.10.2(3) "Slave
-     * mode operation" in the RA6M3 manual R01UH0886EJ0100. */
-    if (SPI_MODE_SLAVE == p_cfg->operating_mode)
-    {
-        FSP_ERROR_RETURN(SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase, FSP_ERR_UNSUPPORTED);
-    }
-
- #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 || SPI_TRANSMIT_FROM_RXI_ISR == 1
-    spi_extended_cfg_t * p_extend = (spi_extended_cfg_t *) p_cfg->p_extend;
- #endif
- #if SPI_TRANSMIT_FROM_RXI_ISR == 1
-
-    /* Half Duplex - Transmit Only mode is not supported when transmit interrupt is handled in the RXI ISR. */
-    FSP_ERROR_RETURN(p_extend->spi_comm != SPI_COMMUNICATION_TRANSMIT_ONLY, FSP_ERR_UNSUPPORTED);
-
-    /* When the TXI Interrupt is handled in the RXI ISR, a TX DTC instance must be present if there is a
-     * RX DTC instance present otherwise the TXI Interrupts will not be processed. */
-    if (p_cfg->p_transfer_rx)
-    {
-        FSP_ERROR_RETURN(0 != p_cfg->p_transfer_tx, FSP_ERR_UNSUPPORTED);
-    }
- #endif
-
- #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0
-    if ((SPI_MODE_MASTER == p_cfg->operating_mode))
-    {
-        /* 4-Wire Mode is not supported in master mode on devices without SSL_LEVEL_KEEP */
-        FSP_ERROR_RETURN(SPI_SSL_MODE_SPI != p_extend->spi_clksyn, FSP_ERR_UNSUPPORTED);
-    }
- #endif
-#endif
-
-    /* Configure transfers if they are provided in p_cfg. */
-    err = r_spi_transfer_config(p_cfg);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
-    /* Get the register address of the channel. */
-    p_ctrl->p_cfg             = p_cfg;
-    p_ctrl->p_callback        = p_cfg->p_callback;
-    p_ctrl->p_context         = p_cfg->p_context;
-    p_ctrl->p_callback_memory = NULL;
-
-    p_ctrl->p_regs = SPI_REG(p_ctrl->p_cfg->channel);
-
-    /* Configure hardware registers according to the r_spi_api configuration structure. */
-    r_spi_hw_config(p_ctrl);
-
-    /* Enable interrupts in NVIC. */
-    r_spi_nvic_config(p_ctrl);
-
-    p_ctrl->open = SPI_OPEN;
-
-    return err;
-}
-
-/*******************************************************************************************************************//**
- * This function receives data from a SPI device. Implements @ref spi_api_t::read.
- *
- * The function performs the following tasks:
- * - Performs parameter checking and processes error conditions.
- * - Sets up the instance to complete a SPI read operation.
- *
- * @retval  FSP_SUCCESS                   Read operation successfully completed.
- * @retval  FSP_ERR_ASSERTION             NULL pointer to control or destination parameters or transfer length is zero.
- * @retval  FSP_ERR_NOT_OPEN              The channel has not been opened. Open channel first.
- * @retval  FSP_ERR_IN_USE                A transfer is already in progress.
- **********************************************************************************************************************/
-fsp_err_t R_SPI_Read (spi_ctrl_t * const    p_api_ctrl,
-                      void                * p_dest,
-                      uint32_t const        length,
-                      spi_bit_width_t const bit_width)
-{
-    return r_spi_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width);
-}
-
-/*******************************************************************************************************************//**
- * This function transmits data to a SPI device using the TX Only Communications Operation Mode.
- * Implements @ref spi_api_t::write.
- *
- * The function performs the following tasks:
- * - Performs parameter checking and processes error conditions.
- * - Sets up the instance to complete a SPI write operation.
- *
- * @retval  FSP_SUCCESS                     Write operation successfully completed.
- * @retval  FSP_ERR_ASSERTION               NULL pointer to control or source parameters or transfer length is zero.
- * @retval  FSP_ERR_NOT_OPEN                The channel has not been opened. Open the channel first.
- * @retval  FSP_ERR_IN_USE                  A transfer is already in progress.
- **********************************************************************************************************************/
-fsp_err_t R_SPI_Write (spi_ctrl_t * const    p_api_ctrl,
-                       void const          * p_src,
-                       uint32_t const        length,
-                       spi_bit_width_t const bit_width)
-{
-    return r_spi_write_read_common(p_api_ctrl, p_src, NULL, length, bit_width);
-}
-
-/*******************************************************************************************************************//**
- * This function simultaneously transmits and receive data. Implements @ref spi_api_t::writeRead.
- *
- * The function performs the following tasks:
- * - Performs parameter checking and processes error conditions.
- * - Sets up the instance to complete a SPI writeRead operation.
- *
- * @retval  FSP_SUCCESS                   Write operation successfully completed.
- * @retval  FSP_ERR_ASSERTION             NULL pointer to control, source or destination parameters or
- *                                        transfer length is zero.
- * @retval  FSP_ERR_NOT_OPEN              The channel has not been opened. Open the channel first.
- * @retval  FSP_ERR_IN_USE                A transfer is already in progress.
- *********************************************************************************************************************/
-fsp_err_t R_SPI_WriteRead (spi_ctrl_t * const    p_api_ctrl,
-                           void const          * p_src,
-                           void                * p_dest,
-                           uint32_t const        length,
-                           spi_bit_width_t const bit_width)
-{
-#if SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(p_src != NULL);
-    FSP_ASSERT(p_dest != NULL);
-#endif
-
-    return r_spi_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width);
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback and has option of providing memory for callback structure.
- * Implements spi_api_t::callbackSet
- *
- * @retval  FSP_SUCCESS                  Callback updated successfully.
- * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
- * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
- * @retval  FSP_ERR_NO_CALLBACK_MEMORY   p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const          p_api_ctrl,
-                             void (                    * p_callback)(spi_callback_args_t *),
-                             void const * const          p_context,
-                             spi_callback_args_t * const p_callback_memory)
-{
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl;
-
-#if (SPI_CFG_PARAM_CHECKING_ENABLE)
-    FSP_ASSERT(p_ctrl);
-    FSP_ASSERT(p_callback);
-    FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* Get security state of p_callback */
-    bool callback_is_secure =
-        (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-
- #if SPI_CFG_PARAM_CHECKING_ENABLE
-
-    /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
-    spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
-                                                                                      CMSE_AU_NONSECURE);
-    FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-#endif
-
-    /* Store callback and context */
-#if BSP_TZ_SECURE_BUILD
-    p_ctrl->p_callback = callback_is_secure ? p_callback :
-                         (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
-    p_ctrl->p_callback = p_callback;
-#endif
-    p_ctrl->p_context         = p_context;
-    p_ctrl->p_callback_memory = p_callback_memory;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close.
- *
- * Disables SPI operations by disabling the SPI bus.
- * - Disables the SPI peripheral.
- * - Disables all the associated interrupts.
- * - Update control structure so it will not work with @ref SPI_API functions.
- *
- * @retval  FSP_SUCCESS              Channel successfully closed.
- * @retval  FSP_ERR_ASSERTION        A required pointer argument is NULL.
- * @retval  FSP_ERR_NOT_OPEN         The channel has not been opened. Open the channel first.
- **********************************************************************************************************************/
-fsp_err_t R_SPI_Close (spi_ctrl_t * const p_api_ctrl)
-{
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-    p_ctrl->open = 0;
-
-#if SPI_DTC_SUPPORT_ENABLE == 1
-    if (NULL != p_ctrl->p_cfg->p_transfer_rx)
-    {
-        p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl);
-    }
-
-    if (NULL != p_ctrl->p_cfg->p_transfer_tx)
-    {
-        p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl);
-    }
-#endif
-
-    /* Disable interrupts in NVIC. */
-    R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq);
-    R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq);
-
-    /* Disable the SPI Transfer. */
-    p_ctrl->p_regs->SPCR_b.SPE = 0U;
-
-    /* Clear the status register. */
-
-    /* The status register must be read before cleared. Reference section 38.2.4 SPI Status Register (SPSR) in the
-     * RA6M3 manual R01UH0886EJ0100. */
-    p_ctrl->p_regs->SPSR;
-    p_ctrl->p_regs->SPSR = 0;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Calculates the SPBR register value and the BRDV bits for a desired bitrate.
- * If the desired bitrate is faster than the maximum bitrate, than the bitrate is set to the
- * maximum bitrate. If the desired bitrate is slower than the minimum bitrate, than an error is returned.
- *
- * @param[in] bitrate             Desired bitrate
- * @param[out] spck_div           Memory location to store bitrate register settings.
- *
- * @retval FSP_SUCCESS            Valid spbr and brdv values were calculated
- * @retval FSP_ERR_UNSUPPORTED    Bitrate is not achievable
- **********************************************************************************************************************/
-fsp_err_t R_SPI_CalculateBitrate (uint32_t bitrate, rspck_div_setting_t * spck_div)
-{
-    /* desired_divider = Smallest integer greater than or equal to SPI_CLK / bitrate. */
-    uint32_t desired_divider = (R_FSP_SystemClockHzGet(BSP_FEATURE_SPI_CLK) + bitrate - 1) / bitrate;
-
-    /* Can't achieve bitrate slower than desired. */
-    if (desired_divider > SPI_CLK_MAX_DIV)
-    {
-        return FSP_ERR_UNSUPPORTED;
-    }
-
-    if (desired_divider < SPI_CLK_MIN_DIV)
-    {
-        /* Configure max bitrate (SPI_CLK / 2) */
-        spck_div->brdv = 0;
-        spck_div->spbr = 0;
-
-        return FSP_SUCCESS;
-    }
-
-    /*
-     * Possible SPI_CLK dividers for values of N:
-     *   N = 0; div = [2,4,6,..,512]
-     *   N = 1; div = [4,8,12,..,1024]
-     *   N = 2; div = [8,16,32,..,2048]
-     *   N = 3; div = [16,32,64,..,4096]
-     */
-    uint8_t i;
-    for (i = 0; i < 4; i++)
-    {
-        /* Select smallest value for N possible. */
-
-        /* div <= 512; N = 0
-         * 512 < div <= 1024; N=1
-         * ...
-         */
-        if (desired_divider <= (SPI_CLK_N_DIV_MULTIPLIER << i))
-        {
-            break;
-        }
-    }
-
-    spck_div->brdv = i & 0x03U;
-
-    /*
-     * desired_divider = 2 * (spbr + 1) * 2^i.
-     *
-     * With desired_divider and i known, solve for spbr.
-     *
-     * spbr = SPI_CLK_DIV / (2 * 2^i) - 1
-     */
-    uint32_t spbr_divisor = (2U * (1U << i));
-
-    /* spbr = (Smallest integer greater than or equal to SPI_CLK_DIV / (2 * 2^i)) - 1. */
-    spck_div->spbr = (uint8_t) (((desired_divider + spbr_divisor - 1U) / spbr_divisor) - 1U) & UINT8_MAX;
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup SPI)
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Private Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Configure the given transfer instances for receiving and transmitting data without CPU intervention.
- *
- * @param      p_cfg           Configuration structure with references to receive and transmit transfer instances.
- *
- * @retval     FSP_SUCCESS     The given transfer instances were configured successfully.
- * @return                     See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally
- *                             calls @ref transfer_api_t::open.
- **********************************************************************************************************************/
-static fsp_err_t r_spi_transfer_config (spi_cfg_t const * const p_cfg)
-{
-    fsp_err_t err = FSP_SUCCESS;
-
-#if SPI_DTC_SUPPORT_ENABLE == 1
-    const transfer_instance_t * p_transfer_tx = p_cfg->p_transfer_tx;
-    void * p_spdr = (void *) &(SPI_REG(p_cfg->channel)->SPDR);
-    if (p_transfer_tx)
-    {
-        p_transfer_tx->p_cfg->p_info->transfer_settings_word = SPI_DTC_TX_TRANSFER_SETTINGS;
-        p_transfer_tx->p_cfg->p_info->p_dest                 = p_spdr;
-
-        err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg);
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-
-    const transfer_instance_t * p_transfer_rx = p_cfg->p_transfer_rx;
-    if (p_transfer_rx)
-    {
-        p_transfer_rx->p_cfg->p_info->transfer_settings_word = SPI_DTC_RX_TRANSFER_SETTINGS;
-        p_transfer_rx->p_cfg->p_info->p_src = p_spdr;
-
-        err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg);
-
-        if ((FSP_SUCCESS != err) && p_transfer_tx)
-        {
-            p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl);
-        }
-    }
-
-#else
-    FSP_PARAMETER_NOT_USED(p_cfg);
-#endif
-
-    return err;
-}
-
-/*******************************************************************************************************************//**
- * Hardware configuration for settings given by the configuration structure.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- **********************************************************************************************************************/
-static void r_spi_hw_config (spi_instance_ctrl_t * p_ctrl)
-{
-    uint32_t spcr   = 0;
-    uint32_t sslp   = 0;
-    uint32_t sppcr  = 0;
-    uint32_t spcr2  = 0;
-    uint32_t spckd  = 0;
-    uint32_t sslnd  = 0;
-    uint32_t spnd   = 0;
-    uint32_t spcmd0 = 0;
-    uint32_t spdcr2 = 0;
-
-    /* Enable Receive Buffer Full interrupt. */
-    spcr |= R_SPI0_SPCR_SPRIE_Msk;
-
-    /* The TXI interrupt is not needed when TRANSMIT_FROM_RXI_ISR optimization is enabled. */
-#if SPI_TRANSMIT_FROM_RXI_ISR == 0
-
-    /* Enable Transmit Buffer Empty interrupt. */
-    spcr |= R_SPI0_SPCR_SPTIE_Msk;
-#endif
-
-    /* Enable Error interrupt. */
-    spcr |= R_SPI0_SPCR_SPEIE_Msk;
-
-    /* Configure Master Mode setting. */
-    spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR_MSTR_Pos;
-
-    /* Enable SCK Auto Stop setting in order to prevent RX Overflow in Master Mode */
-    spcr2 |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR2_SCKASE_Pos;
-
-    /* Configure CPHA setting. */
-    spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI0_SPCMD0_CPHA_Pos;
-
-    /* Configure CPOL setting. */
-    spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_polarity << R_SPI0_SPCMD0_CPOL_Pos;
-
-    /* Configure Bit Order (MSB,LSB) */
-    spcmd0 |= (uint32_t) p_ctrl->p_cfg->bit_order << R_SPI0_SPCMD0_LSBF_Pos;
-
-    if (p_ctrl->p_cfg->p_transfer_tx)
-    {
-        /* Transmit Buffer Empty IRQ must be enabled for DTC even if TRANSMIT_FROM_RXI is enabled. */
-        spcr |= R_SPI0_SPCR_SPTIE_Msk;
-    }
-
-    spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend);
-
-    if (SPI_SSL_MODE_SPI == p_extend->spi_clksyn)
-    {
-#if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 1
-
-        /* Configure SSL Level Keep Setting. */
-        spcmd0 |= R_SPI0_SPCMD0_SSLKP_Msk;
-#endif
-
-        /* Configure 4-Wire Mode Setting. */
-        spcr &= ~R_SPI0_SPCR_SPMS_Msk;
-    }
-    else
-    {
-        /* Configure 3-Wire Mode Setting. */
-        spcr |= R_SPI0_SPCR_SPMS_Msk;
-    }
-
-    /* Configure Full Duplex or TX Only Setting. */
-    spcr &= (uint32_t) ~(p_extend->spi_comm << R_SPI0_SPCR_SPRIE_Pos),
-    spcr |=
-        (uint32_t) ((p_extend->spi_comm << R_SPI0_SPCR_TXMD_Pos) |
-                    (p_extend->spi_comm << R_SPI0_SPCR_SPTIE_Pos));
-
-    /* Configure SSLn polarity setting. */
-    sslp &= ~0x0FU;
-    sslp |= (uint32_t) p_extend->ssl_polarity << p_extend->ssl_select;
-
-    /* Configure SSLn setting. (SSL0, SSL1, SSL2, SSL3)*/
-    spcmd0 &= ~R_SPI0_SPCMD0_SSLA_Msk;
-    spcmd0 |= (uint32_t) p_extend->ssl_select << R_SPI0_SPCMD0_SSLA_Pos;
-
-    if (SPI_MOSI_IDLE_VALUE_FIXING_DISABLE != p_extend->mosi_idle)
-    {
-        /* Enable mosi value fixing */
-        sppcr |= R_SPI0_SPPCR_MOIFE_Msk;
-
-        if (SPI_MOSI_IDLE_VALUE_FIXING_HIGH == p_extend->mosi_idle)
-        {
-            sppcr |= R_SPI0_SPPCR_MOIFV_Msk;
-        }
-    }
-
-    if (SPI_PARITY_MODE_DISABLE != p_extend->parity)
-    {
-        /* Enable Parity Mode. */
-        spcr2 |= R_SPI0_SPCR2_SPPE_Msk;
-
-        if (SPI_PARITY_MODE_ODD == p_extend->parity)
-        {
-            /* Configure ODD Parity Setting. */
-            spcr2 |= R_SPI0_SPCR2_SPOE_Msk;
-        }
-    }
-
-    /* Configure byte swapping for 16/32-Bit mode. */
-    spdcr2 |= p_extend->byte_swap;
-
-    /* Configure the Bit Rate Division Setting */
-    spcmd0 |= (uint32_t) p_extend->spck_div.brdv << R_SPI0_SPCMD0_BRDV_Pos;
-
-    /* Enable all delay settings. */
-    if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode)
-    {
-        /* Note that disabling delay settings is same as setting delay to 1. */
-        spcmd0 |= (uint32_t) R_SPI0_SPCMD0_SPNDEN_Msk | R_SPI0_SPCMD0_SLNDEN_Msk | R_SPI0_SPCMD0_SCKDEN_Msk;
-
-        spckd = p_extend->spck_delay;
-        sslnd = p_extend->ssl_negation_delay;
-        spnd  = p_extend->next_access_delay;
-    }
-
-    /* Power up the SPI module. */
-    R_BSP_MODULE_START(FSP_IP_SPI, p_ctrl->p_cfg->channel);
-
-    /* Clear the status register. */
-
-    /* The status register must be read before cleared. Reference section 38.2.4 SPI Status Register (SPSR) in the
-     * RA6M3 manual R01UH0886EJ0100. */
-    p_ctrl->p_regs->SPSR;
-    p_ctrl->p_regs->SPSR = 0;
-
-    /* Write registers */
-    p_ctrl->p_regs->SPCR     = (uint8_t) spcr;
-    p_ctrl->p_regs->SSLP     = (uint8_t) sslp;
-    p_ctrl->p_regs->SPPCR    = (uint8_t) sppcr;
-    p_ctrl->p_regs->SPBR     = p_extend->spck_div.spbr;
-    p_ctrl->p_regs->SPCKD    = (uint8_t) spckd;
-    p_ctrl->p_regs->SSLND    = (uint8_t) sslnd;
-    p_ctrl->p_regs->SPND     = (uint8_t) spnd;
-    p_ctrl->p_regs->SPCR2    = (uint8_t) spcr2;
-    p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0;
-    p_ctrl->p_regs->SPDCR2   = (uint8_t) spdcr2;
-
-#if BSP_FEATURE_SPI_HAS_SPCR3 == 1
-    p_ctrl->p_regs->SPCR3 = R_SPI0_SPCR3_CENDIE_Msk;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Enable Receive Buffer Full, Transmit Buffer Empty, and Error Interrupts in the NVIC.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- **********************************************************************************************************************/
-static void r_spi_nvic_config (spi_instance_ctrl_t * p_ctrl)
-{
-    R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->txi_ipl, p_ctrl);
-    R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->rxi_ipl, p_ctrl);
-    R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl);
-
-    R_BSP_IrqCfg(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->tei_ipl, p_ctrl);
-
-    /* Note tei_irq is not enabled until the last data frame is transfered. */
-}
-
-/*******************************************************************************************************************//**
- * Setup the bit width configuration for a transfer.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- *
- * Note: For 8-Bit wide data frames, the devices require the SPBYT bit to enable byte level access to the
- * data register. Although this register is not documented in some MCU hardware manuals, it does seem to be available
- * on all of them.
- **********************************************************************************************************************/
-static void r_spi_bit_width_config (spi_instance_ctrl_t * p_ctrl)
-{
-    uint32_t spdcr  = p_ctrl->p_regs->SPDCR;
-    uint32_t spcmd0 = p_ctrl->p_regs->SPCMD[0];
-
-    if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */
-    {
-        /* Configure Word access to data register. */
-        spdcr &= ~R_SPI0_SPDCR_SPBYT_Msk;
-        spdcr |= R_SPI0_SPDCR_SPLW_Msk;
-    }
-    else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/
-    {
-        /* Set SPBYT so 8bit transfer works with the DTC/DMAC. */
-        spdcr |= R_SPI0_SPDCR_SPBYT_Msk;
-    }
-    else                               /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */
-    {
-        /* Configure Half-Word access to data register. */
-        spdcr &= ~(R_SPI0_SPDCR_SPBYT_Msk | R_SPI0_SPDCR_SPLW_Msk);
-    }
-
-    /* Configure data length based on the selected bit width . */
-    uint32_t bit_width = p_ctrl->bit_width;
-    if (bit_width > SPI_BIT_WIDTH_16_BITS)
-    {
-        bit_width = ((bit_width + 1) >> 2) - 5;
-    }
-
-    spcmd0 &= ~R_SPI0_SPCMD0_SPB_Msk;
-    spcmd0 |= bit_width << R_SPI0_SPCMD0_SPB_Pos;
-
-    p_ctrl->p_regs->SPDCR    = (uint8_t) spdcr;
-    p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0;
-}
-
-/*******************************************************************************************************************//**
- * Initiates a SPI transfer by setting the SPE bit in SPCR.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- *
- * Note: When not using the DTC to transmit, this function pre-loads the SPI shift-register and shift-register-buffer
- * instead of waiting for the transmit buffer empty interrupt. This is required when transmitting from the
- * Receive Buffer Full interrupt, but it does not interfere with transmitting when using the transmit buffer empty
- * interrupt.
- **********************************************************************************************************************/
-static void r_spi_start_transfer (spi_instance_ctrl_t * p_ctrl)
-{
-#if SPI_TRANSMIT_FROM_RXI_ISR == 1
-    if (!p_ctrl->p_cfg->p_transfer_tx)
-    {
-        /* Handle the first two transmit empty events here because transmit interrupt may not be enabled. */
-
-        /* Critical section required so that the txi interrupt can be handled here instead of in the ISR. */
-        FSP_CRITICAL_SECTION_DEFINE;
-        FSP_CRITICAL_SECTION_ENTER;
-
-        /* Enable the SPI Transfer. */
-        p_ctrl->p_regs->SPCR_b.SPE = 1;
-
-        /* Must call transmit to kick off transfer when transmitting from rxi ISR. */
-        r_spi_transmit(p_ctrl);        ///< First data immediately copied into the SPI shift register.
-
-        /* Second transmit significantly improves slave mode performance. */
-        r_spi_transmit(p_ctrl);        ///< Second data copied into the SPI transmit buffer.
-
-        /* Must clear the txi IRQ status (The interrupt was handled here). */
-        R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq);
-
-        FSP_CRITICAL_SECTION_EXIT;
-    }
-    else
-    {
-        /* Enable the SPI Transfer. */
-        p_ctrl->p_regs->SPCR_b.SPE = 1;
-    }
-
-#else
-
-    /* Enable the SPI Transfer. */
-    p_ctrl->p_regs->SPCR_b.SPE = 1;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Configures the driver state and initiates a SPI transfer for all modes of operation.
- *
- * @param[in]  p_api_ctrl        pointer to control structure.
- * @param      p_src             Buffer to transmit data from.
- * @param      p_dest            Buffer to store received data in.
- * @param[in]  length            Number of transfers
- * @param[in]  bit_width         Data frame size (8-Bit, 16-Bit, 32-Bit)
- *
- * @retval     FSP_SUCCESS       Transfer was started successfully.
- * @retval     FSP_ERR_ASSERTION An argument is invalid.
- * @retval     FSP_ERR_NOT_OPEN  The instance has not been initialized.
- * @retval     FSP_ERR_IN_USE    A transfer is already in progress.
- * @return                       See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally
- *                               calls @ref transfer_api_t::reconfigure.
- **********************************************************************************************************************/
-static fsp_err_t r_spi_write_read_common (spi_ctrl_t * const    p_api_ctrl,
-                                          void const          * p_src,
-                                          void                * p_dest,
-                                          uint32_t const        length,
-                                          spi_bit_width_t const bit_width)
-{
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl;
-
-#if SPI_CFG_PARAM_CHECKING_ENABLE
-    FSP_ASSERT(NULL != p_ctrl);
-    FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-    FSP_ASSERT(p_src || p_dest);
-    FSP_ASSERT(0 != length);
-    if (p_ctrl->p_cfg->p_transfer_tx || p_ctrl->p_cfg->p_transfer_rx)
-    {
-        FSP_ASSERT(length <= SPI_DTC_MAX_TRANSFER);
-    }
-
-    /* Reject bit width settings not compatible with R_SPI */
-    FSP_ASSERT(!((bit_width < SPI_BIT_WIDTH_8_BITS) ||
-                 ((bit_width > SPI_BIT_WIDTH_16_BITS) && ((bit_width + 1) & 0x3)) ||
-                 (bit_width == SPI_BIT_WIDTH_28_BITS)));
-#endif
-
-    FSP_ERROR_RETURN(0 == (p_ctrl->p_regs->SPCR & R_SPI0_SPCR_SPE_Msk), FSP_ERR_IN_USE);
-
-    p_ctrl->p_tx_data = p_src;
-    p_ctrl->p_rx_data = p_dest;
-    p_ctrl->tx_count  = 0;
-    p_ctrl->rx_count  = 0;
-    p_ctrl->count     = length;
-    p_ctrl->bit_width = bit_width;
-
-#if SPI_DTC_SUPPORT_ENABLE == 1
-    if (p_ctrl->p_cfg->p_transfer_rx)
-    {
-        /* When the rxi interrupt is called, all transfers will be finished. */
-        p_ctrl->rx_count = length;
-
-        /* Configure the receive DMA instance. */
-        if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width)
-        {
-            p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_4_BYTE;
-        }
-        else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width)
-        {
-            p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_1_BYTE;
-        }
-        else
-        {
-            p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_2_BYTE;
-        }
-
-        p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
-        p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length         = (uint16_t) length;
-        p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest         = p_dest;
-
-        if (NULL == p_dest)
-        {
-            static uint32_t dummy_rx;
-            p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED;
-            p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest         = &dummy_rx;
-        }
-
-        fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl,
-                                                                         p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info);
-
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-
-    if (p_ctrl->p_cfg->p_transfer_tx)
-    {
-        /* When the txi interrupt is called, all transfers will be finished. */
-        p_ctrl->tx_count = length;
-
-        /* Configure the transmit DMA instance. */
-        if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width)
-        {
-            p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_4_BYTE;
-        }
-        else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width)
-        {
-            p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_1_BYTE;
-        }
-        else
-        {
-            p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_2_BYTE;
-        }
-
-        p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
-        p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length        = (uint16_t) length;
-        p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src         = p_src;
-
-        if (NULL == p_src)
-        {
-            static uint32_t dummy_tx = 0;
-            p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED;
-            p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src         = &dummy_tx;
-        }
-
-        fsp_err_t err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl,
-                                                                         p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info);
-
-        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-    }
-#endif
-
-    r_spi_bit_width_config(p_ctrl);
-    r_spi_start_transfer(p_ctrl);
-
-    return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Copy configured bit width from the SPI data register to the current rx data location.
- * If the receive buffer is NULL, just read the SPI data register.
- * If the total transfer length has already been received than do nothing.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- **********************************************************************************************************************/
-static void r_spi_receive (spi_instance_ctrl_t * p_ctrl)
-{
-    uint32_t rx_count = p_ctrl->rx_count;
-    if (rx_count == p_ctrl->count)
-    {
-        return;
-    }
-
-    if (0 == p_ctrl->p_rx_data)
-    {
-        /* Read the received data but do nothing with it. */
-        p_ctrl->p_regs->SPDR;
-    }
-    else
-    {
-        if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width)      /* Bit Widths of 20, 24 or 32 bits */
-        {
-            ((uint32_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR;
-        }
-        else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/
-        {
-            ((uint8_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_BY;
-        }
-        else                                                /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */
-        {
-            ((uint16_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_HA;
-        }
-    }
-
-    p_ctrl->rx_count = rx_count + 1;
-}
-
-/*******************************************************************************************************************//**
- * Copy configured bit width from the current tx data location into the SPI data register.
- * If the transmit buffer is NULL, than write zero to the SPI data register.
- * If the total transfer length has already been transmitted than do nothing.
- *
- * @param[in]  p_ctrl          pointer to control structure.
- **********************************************************************************************************************/
-static void r_spi_transmit (spi_instance_ctrl_t * p_ctrl)
-{
-    uint32_t tx_count = p_ctrl->tx_count;
-    if (tx_count == p_ctrl->count)
-    {
-        return;
-    }
-
-    if (0 == p_ctrl->p_tx_data)
-    {
-        /* Transmit zero if no tx buffer present. */
-        p_ctrl->p_regs->SPDR = 0;
-    }
-    else
-    {
-        if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width)      /* Bit Widths of 20, 24 or 32 bits */
-        {
-            p_ctrl->p_regs->SPDR = ((uint32_t *) p_ctrl->p_tx_data)[tx_count];
-        }
-        else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/
-        {
-            p_ctrl->p_regs->SPDR_BY = ((uint8_t *) p_ctrl->p_tx_data)[tx_count];
-        }
-        else                                                /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */
-        {
-            p_ctrl->p_regs->SPDR_HA = ((uint16_t *) p_ctrl->p_tx_data)[tx_count];
-        }
-    }
-
-    p_ctrl->tx_count = tx_count + 1;
-}
-
-/*******************************************************************************************************************//**
- * Calls user callback.
- *
- * @param[in]     p_ctrl     Pointer to SPI instance control block
- * @param[in]     event      Event code
- **********************************************************************************************************************/
-static void r_spi_call_callback (spi_instance_ctrl_t * p_ctrl, spi_event_t event)
-{
-    spi_callback_args_t args;
-
-    /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
-     * stored in non-secure memory so they can be accessed by a non-secure callback function. */
-    spi_callback_args_t * p_args = p_ctrl->p_callback_memory;
-    if (NULL == p_args)
-    {
-        /* Store on stack */
-        p_args = &args;
-    }
-    else
-    {
-        /* Save current arguments on the stack in case this is a nested interrupt. */
-        args = *p_args;
-    }
-
-    p_args->channel   = p_ctrl->p_cfg->channel;
-    p_args->event     = event;
-    p_args->p_context = p_ctrl->p_context;
-
-#if BSP_TZ_SECURE_BUILD
-
-    /* p_callback can point to a secure function or a non-secure function. */
-    if (!cmse_is_nsfptr(p_ctrl->p_callback))
-    {
-        /* If p_callback is secure, then the project does not need to change security state. */
-        p_ctrl->p_callback(p_args);
-    }
-    else
-    {
-        /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
-        spi_prv_ns_callback p_callback = (spi_prv_ns_callback) (p_ctrl->p_callback);
-        p_callback(p_args);
-    }
-
-#else
-
-    /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
-    p_ctrl->p_callback(p_args);
-#endif
-    if (NULL != p_ctrl->p_callback_memory)
-    {
-        /* Restore callback memory in case this is a nested interrupt. */
-        *p_ctrl->p_callback_memory = args;
-    }
-}
-
-/*******************************************************************************************************************//**
- * ISR called when data is loaded into SPI data register from the shift register.
- **********************************************************************************************************************/
-void spi_rxi_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type irq = R_FSP_CurrentIrqGet();
-    R_BSP_IrqStatusClear(irq);
-
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    r_spi_receive(p_ctrl);
-
-#if SPI_TRANSMIT_FROM_RXI_ISR == 1
-
-    /* It is a little faster to handle the transmit buffer empty event in the receive buffer full ISR.
-     * Note that this is only possible when the instance is not using a transfer instance to receive data. */
-    r_spi_transmit(p_ctrl);
-#endif
-
-    if (p_ctrl->rx_count == p_ctrl->count)
-    {
-        /* If the transmit and receive ISRs are too slow to keep up at high bitrates,
-         * the hardware will generate an interrupt before all of the transfers are completed.
-         * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */
-        R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq);
-    }
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * ISR called when data is copied from the SPI data register into the SPI shift register.
- **********************************************************************************************************************/
-void spi_txi_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type irq = R_FSP_CurrentIrqGet();
-    R_BSP_IrqStatusClear(irq);
-
-#if SPI_TRANSMIT_FROM_RXI_ISR == 0
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend);
-    if (p_extend && (SPI_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm))
-    {
-        /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled
-         * after this interrupt. */
-        if (p_ctrl->tx_count == p_ctrl->count - 1)
-        {
-            /* If the transmit and receive ISRs are too slow to keep up at high bitrates,
-             * the hardware will generate an interrupt before all of the transfers are completed.
-             * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */
-            R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq);
-        }
-        else if (p_ctrl->p_cfg->p_transfer_tx)
-        {
-            /* If DMA is used to transmit data, enable the interrupt after all the data has been transfered, but do not
-             * clear the IRQ Pending Bit. */
-            R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq);
-        }
-        else
-        {
-        }
-    }
-
-    /* Transmit happens after checking if the last transfer has been written to the transmit buffer in order
-     * to ensure that the end interrupt is not enabled while there is data still in the transmit buffer. */
-    r_spi_transmit(p_ctrl);
-#endif
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * ISR called when the SPI peripheral transitions from the transferring state to the IDLE state.
- **********************************************************************************************************************/
-void spi_tei_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type irq = R_FSP_CurrentIrqGet();
-    R_BSP_IrqStatusClear(irq);
-
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    if ((0 == p_ctrl->p_regs->SPSR_b.IDLNF) || (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode))
-    {
-        R_BSP_IrqDisable(irq);
-
-        /* Disable the SPI Transfer. */
-        p_ctrl->p_regs->SPCR_b.SPE = 0;
-
-        /* Signal that a transfer has completed. */
-        r_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE);
-    }
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * ISR called in the event that an error occurs (Ex: RX_OVERFLOW).
- **********************************************************************************************************************/
-void spi_eri_isr (void)
-{
-    /* Save context if RTOS is used */
-    FSP_CONTEXT_SAVE;
-
-    IRQn_Type             irq    = R_FSP_CurrentIrqGet();
-    spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
-    /* Disable the SPI Transfer. */
-    p_ctrl->p_regs->SPCR_b.SPE = 0;
-
-    /* Read the status register. */
-    uint8_t status = p_ctrl->p_regs->SPSR;
-
-    /* Clear the status register. */
-    p_ctrl->p_regs->SPSR = 0;
-
-    /* Check if the error is a Parity Error. */
-    if (R_SPI0_SPSR_PERF_Msk & status)
-    {
-        r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_PARITY);
-    }
-
-    /* Check if the error is a Receive Buffer Overflow Error. */
-    if (R_SPI0_SPSR_OVRF_Msk & status)
-    {
-        r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW);
-    }
-
-    /* Check if the error is a Mode Fault Error. */
-    if (R_SPI0_SPSR_MODF_Msk & status)
-    {
-        /* Check if the error is a Transmit Buffer Underflow Error. */
-        if (R_SPI0_SPSR_UDRF_Msk & status)
-        {
-            r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_MODE_UNDERRUN);
-        }
-    }
-
-    R_BSP_IrqStatusClear(irq);
-
-    /* Restore context if RTOS is used */
-    FSP_CONTEXT_RESTORE;
-}
-
-/* End of file R_SPI. */

bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h

@@ -76,7 +76,7 @@
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
-            (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
             (((1 > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
@@ -138,7 +138,7 @@
 #ifndef BSP_TZ_CFG_MSSAR
 #define BSP_TZ_CFG_MSSAR (\
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
-            (((2 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
             0xfffffffc) /* Unused */
 #endif
 
@@ -190,7 +190,7 @@
             /* Security attribution for registers for IRQ channels. */
 #ifndef BSP_TZ_CFG_ICUSARA
 #define BSP_TZ_CFG_ICUSARA (\
-            (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
@@ -244,7 +244,7 @@
 #endif
 
             /* Set DTCSTSAR if the Secure program uses the DTC. */
-#if 2 == RA_NOT_DEFINED
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
  #define BSP_TZ_CFG_DTC_USED (0U)
 #else
  #define BSP_TZ_CFG_DTC_USED (1U)

bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_dtc_cfg.h

@@ -1,6 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_DTC_CFG_H_
-#define R_DTC_CFG_H_
-#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
-#endif /* R_DTC_CFG_H_ */

bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h

@@ -1,5 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_ICU_CFG_H_
-#define R_ICU_CFG_H_
-#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#endif /* R_ICU_CFG_H_ */

bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_spi_cfg.h

@@ -1,7 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_SPI_CFG_H_
-#define R_SPI_CFG_H_
-#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-                 #define SPI_DTC_SUPPORT_ENABLE (1)
-                 #define SPI_TRANSMIT_FROM_RXI_ISR (0)
-#endif /* R_SPI_CFG_H_ */

bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c

@@ -1,173 +1,5 @@
 /* generated HAL source file - do not edit */
 #include "hal_data.h"
-dtc_instance_ctrl_t g_transfer1_ctrl;
-
-transfer_info_t g_transfer1_info =
-{
-    .dest_addr_mode      = TRANSFER_ADDR_MODE_INCREMENTED,
-    .repeat_area         = TRANSFER_REPEAT_AREA_DESTINATION,
-    .irq                 = TRANSFER_IRQ_END,
-    .chain_mode          = TRANSFER_CHAIN_MODE_DISABLED,
-    .src_addr_mode       = TRANSFER_ADDR_MODE_FIXED,
-    .size                = TRANSFER_SIZE_2_BYTE,
-    .mode                = TRANSFER_MODE_NORMAL,
-    .p_dest              = (void *) NULL,
-    .p_src               = (void const *) NULL,
-    .num_blocks          = 0,
-    .length              = 0,
-};
-const dtc_extended_cfg_t g_transfer1_cfg_extend =
-{
-    .activation_source   = VECTOR_NUMBER_SPI0_RXI,
-};
-const transfer_cfg_t g_transfer1_cfg =
-{
-    .p_info              = &g_transfer1_info,
-    .p_extend            = &g_transfer1_cfg_extend,
-};
-
-/* Instance structure to use this module. */
-const transfer_instance_t g_transfer1 =
-{
-    .p_ctrl        = &g_transfer1_ctrl,
-    .p_cfg         = &g_transfer1_cfg,
-    .p_api         = &g_transfer_on_dtc
-};
-dtc_instance_ctrl_t g_transfer0_ctrl;
-
-transfer_info_t g_transfer0_info =
-{
-    .dest_addr_mode      = TRANSFER_ADDR_MODE_FIXED,
-    .repeat_area         = TRANSFER_REPEAT_AREA_SOURCE,
-    .irq                 = TRANSFER_IRQ_END,
-    .chain_mode          = TRANSFER_CHAIN_MODE_DISABLED,
-    .src_addr_mode       = TRANSFER_ADDR_MODE_INCREMENTED,
-    .size                = TRANSFER_SIZE_2_BYTE,
-    .mode                = TRANSFER_MODE_NORMAL,
-    .p_dest              = (void *) NULL,
-    .p_src               = (void const *) NULL,
-    .num_blocks          = 0,
-    .length              = 0,
-};
-const dtc_extended_cfg_t g_transfer0_cfg_extend =
-{
-    .activation_source   = VECTOR_NUMBER_SPI0_TXI,
-};
-const transfer_cfg_t g_transfer0_cfg =
-{
-    .p_info              = &g_transfer0_info,
-    .p_extend            = &g_transfer0_cfg_extend,
-};
-
-/* Instance structure to use this module. */
-const transfer_instance_t g_transfer0 =
-{
-    .p_ctrl        = &g_transfer0_ctrl,
-    .p_cfg         = &g_transfer0_cfg,
-    .p_api         = &g_transfer_on_dtc
-};
-spi_instance_ctrl_t g_spi0_ctrl;
-
-/** SPI extended configuration for SPI HAL driver */
-const spi_extended_cfg_t g_spi0_ext_cfg =
-{
-    .spi_clksyn         = SPI_SSL_MODE_CLK_SYN,
-    .spi_comm           = SPI_COMMUNICATION_FULL_DUPLEX,
-    .ssl_polarity        = SPI_SSLP_LOW,
-    .ssl_select          = SPI_SSL_SELECT_SSL0,
-    .mosi_idle           = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
-    .parity              = SPI_PARITY_MODE_DISABLE,
-    .byte_swap           = SPI_BYTE_SWAP_DISABLE,
-    .spck_div            = {
-        /* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0
-    },
-    .spck_delay          = SPI_DELAY_COUNT_1,
-    .ssl_negation_delay  = SPI_DELAY_COUNT_1,
-    .next_access_delay   = SPI_DELAY_COUNT_1
- };
-
-/** SPI configuration for SPI HAL driver */
-const spi_cfg_t g_spi0_cfg =
-{
-    .channel             = 0,
-
-#if defined(VECTOR_NUMBER_SPI0_RXI)
-    .rxi_irq             = VECTOR_NUMBER_SPI0_RXI,
-#else
-    .rxi_irq             = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SPI0_TXI)
-    .txi_irq             = VECTOR_NUMBER_SPI0_TXI,
-#else
-    .txi_irq             = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SPI0_TEI)
-    .tei_irq             = VECTOR_NUMBER_SPI0_TEI,
-#else
-    .tei_irq             = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SPI0_ERI)
-    .eri_irq             = VECTOR_NUMBER_SPI0_ERI,
-#else
-    .eri_irq             = FSP_INVALID_VECTOR,
-#endif
-
-    .rxi_ipl             = (12),
-    .txi_ipl             = (12),
-    .tei_ipl             = (12),
-    .eri_ipl             = (12),
-
-    .operating_mode      = SPI_MODE_MASTER,
-
-    .clk_phase           = SPI_CLK_PHASE_EDGE_ODD,
-    .clk_polarity        = SPI_CLK_POLARITY_LOW,
-
-    .mode_fault          = SPI_MODE_FAULT_ERROR_DISABLE,
-    .bit_order           = SPI_BIT_ORDER_MSB_FIRST,
-    .p_transfer_tx       = g_spi0_P_TRANSFER_TX,
-    .p_transfer_rx       = g_spi0_P_TRANSFER_RX,
-    .p_callback          = spi0_callback,
-
-    .p_context           = NULL,
-    .p_extend            = (void *)&g_spi0_ext_cfg,
-};
-
-/* Instance structure to use this module. */
-const spi_instance_t g_spi0 =
-{
-    .p_ctrl        = &g_spi0_ctrl,
-    .p_cfg         = &g_spi0_cfg,
-    .p_api         = &g_spi_on_spi
-};
-icu_instance_ctrl_t g_external_irq0_ctrl;
-const external_irq_cfg_t g_external_irq0_cfg =
-{
-    .channel             = 0,
-    .trigger             = EXTERNAL_IRQ_TRIG_RISING,
-    .filter_enable       = false,
-    .pclk_div            = EXTERNAL_IRQ_PCLK_DIV_BY_64,
-    .p_callback          = irq_callback,
-    /** If NULL then do not add & */
-#if defined(NULL)
-    .p_context           = NULL,
-#else
-    .p_context           = &NULL,
-#endif
-    .p_extend            = NULL,
-    .ipl                 = (12),
-#if defined(VECTOR_NUMBER_ICU_IRQ0)
-    .irq                 = VECTOR_NUMBER_ICU_IRQ0,
-#else
-    .irq                 = FSP_INVALID_VECTOR,
-#endif
-};
-/* Instance structure to use this module. */
-const external_irq_instance_t g_external_irq0 =
-{
-    .p_ctrl        = &g_external_irq0_ctrl,
-    .p_cfg         = &g_external_irq0_cfg,
-    .p_api         = &g_external_irq_on_icu
-};
 sci_uart_instance_ctrl_t     g_uart7_ctrl;
 
             baud_setting_t               g_uart7_baud_setting =

bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h

@@ -4,61 +4,9 @@
 #include <stdint.h>
 #include "bsp_api.h"
 #include "common_data.h"
-#include "r_dtc.h"
-#include "r_transfer_api.h"
-#include "r_spi.h"
-#include "r_icu.h"
-#include "r_external_irq_api.h"
 #include "r_sci_uart.h"
             #include "r_uart_api.h"
 FSP_HEADER
-/* Transfer on DTC Instance. */
-extern const transfer_instance_t g_transfer1;
-
-/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
-extern dtc_instance_ctrl_t g_transfer1_ctrl;
-extern const transfer_cfg_t g_transfer1_cfg;
-/* Transfer on DTC Instance. */
-extern const transfer_instance_t g_transfer0;
-
-/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
-extern dtc_instance_ctrl_t g_transfer0_ctrl;
-extern const transfer_cfg_t g_transfer0_cfg;
-/** SPI on SPI Instance. */
-extern const spi_instance_t g_spi0;
-
-/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
-extern spi_instance_ctrl_t g_spi0_ctrl;
-extern const spi_cfg_t g_spi0_cfg;
-
-/** Callback used by SPI Instance. */
-#ifndef spi0_callback
-void spi0_callback(spi_callback_args_t * p_args);
-#endif
-
-
-#define RA_NOT_DEFINED (1)
-#if (RA_NOT_DEFINED == g_transfer0)
-    #define g_spi0_P_TRANSFER_TX (NULL)
-#else
-    #define g_spi0_P_TRANSFER_TX (&g_transfer0)
-#endif
-#if (RA_NOT_DEFINED == g_transfer1)
-    #define g_spi0_P_TRANSFER_RX (NULL)
-#else
-    #define g_spi0_P_TRANSFER_RX (&g_transfer1)
-#endif
-#undef RA_NOT_DEFINED
-/** External IRQ on ICU Instance. */
-extern const external_irq_instance_t g_external_irq0;
-
-/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
-extern icu_instance_ctrl_t g_external_irq0_ctrl;
-extern const external_irq_cfg_t g_external_irq0_cfg;
-
-#ifndef irq_callback
-void irq_callback(external_irq_callback_args_t * p_args);
-#endif
 /** UART on SCI Instance. */
             extern const uart_instance_t      g_uart7;
 

bsp/renesas/ra6m4-cpk/ra_gen/pin_data.c

@@ -28,10 +28,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_00_PIN_05,
         .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
     },
-    {
-        .pin = BSP_IO_PORT_00_PIN_06,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
-    },
     {
         .pin = BSP_IO_PORT_00_PIN_08,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
@@ -44,10 +40,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_00_PIN_15,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
     },
-    {
-        .pin = BSP_IO_PORT_01_PIN_05,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
-    },
     {
         .pin = BSP_IO_PORT_01_PIN_06,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
@@ -64,18 +56,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_01_PIN_10,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
     },
-    {
-        .pin = BSP_IO_PORT_02_PIN_02,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
-    {
-        .pin = BSP_IO_PORT_02_PIN_03,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
-    {
-        .pin = BSP_IO_PORT_02_PIN_04,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
     {
         .pin = BSP_IO_PORT_03_PIN_00,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
@@ -84,22 +64,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_04_PIN_07,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
     },
-    {
-        .pin = BSP_IO_PORT_04_PIN_10,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
-    {
-        .pin = BSP_IO_PORT_04_PIN_11,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
-    {
-        .pin = BSP_IO_PORT_04_PIN_12,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
-    {
-        .pin = BSP_IO_PORT_04_PIN_13,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
-    },
     {
         .pin = BSP_IO_PORT_04_PIN_14,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
@@ -124,14 +88,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_05_PIN_04,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
     },
-    {
-        .pin = BSP_IO_PORT_05_PIN_05,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
-    },
-    {
-        .pin = BSP_IO_PORT_05_PIN_06,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
-    },
     {
         .pin = BSP_IO_PORT_05_PIN_11,
         .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)

bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c

@@ -8,11 +8,6 @@
             [1] = sci_uart_txi_isr, /* SCI7 TXI (Transmit data empty) */
             [2] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */
             [3] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */
-            [4] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
-            [5] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
-            [6] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
-            [7] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
-            [8] = spi_eri_isr, /* SPI0 ERI (Error) */
         };
         const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
         {
@@ -20,10 +15,5 @@
             [1] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TXI), /* SCI7 TXI (Transmit data empty) */
             [2] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */
             [3] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */
-            [4] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
-            [5] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
-            [6] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
-            [7] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
-            [8] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
         };
         #endif

bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h

@@ -3,18 +3,13 @@
         #define VECTOR_DATA_H
                 /* Number of interrupts allocated */
         #ifndef VECTOR_DATA_IRQ_COUNT
-        #define VECTOR_DATA_IRQ_COUNT    (9)
+        #define VECTOR_DATA_IRQ_COUNT    (4)
         #endif
         /* ISR prototypes */
         void sci_uart_rxi_isr(void);
         void sci_uart_txi_isr(void);
         void sci_uart_tei_isr(void);
         void sci_uart_eri_isr(void);
-        void r_icu_isr(void);
-        void spi_rxi_isr(void);
-        void spi_txi_isr(void);
-        void spi_tei_isr(void);
-        void spi_eri_isr(void);
 
         /* Vector table allocations */
         #define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */
@@ -25,14 +20,4 @@
         #define SCI7_TEI_IRQn          ((IRQn_Type) 2) /* SCI7 TEI (Transmit end) */
         #define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
         #define SCI7_ERI_IRQn          ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
-        #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
-        #define ICU_IRQ0_IRQn          ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
-        #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 5) /* SPI0 RXI (Receive buffer full) */
-        #define SPI0_RXI_IRQn          ((IRQn_Type) 5) /* SPI0 RXI (Receive buffer full) */
-        #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type) 6) /* SPI0 TXI (Transmit buffer empty) */
-        #define SPI0_TXI_IRQn          ((IRQn_Type) 6) /* SPI0 TXI (Transmit buffer empty) */
-        #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 7) /* SPI0 TEI (Transmission complete event) */
-        #define SPI0_TEI_IRQn          ((IRQn_Type) 7) /* SPI0 TEI (Transmission complete event) */
-        #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 8) /* SPI0 ERI (Error) */
-        #define SPI0_ERI_IRQn          ((IRQn_Type) 8) /* SPI0 ERI (Error) */
         #endif /* VECTOR_DATA_H */