Merge branch 'master' into master

.gitattributes

@@ -1,3 +1,8 @@
+*.c linguist-language=C
+*.C linguist-language=C
+*.h linguist-language=C
+*.H linguist-language=C
+
 * text=auto
 
 *.S text

.github/workflows/action.yml

@@ -32,15 +32,14 @@ jobs:
          - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}         
+         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "gkipc", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -56,7 +55,7 @@ jobs:
          - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
          - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
          - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -64,10 +63,10 @@ jobs:
          - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -75,14 +74,14 @@ jobs:
          - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-blue-pill", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -92,45 +91,46 @@ jobs:
          - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h750-artpi-h750", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
     steps:
       - uses: actions/checkout@v2
       - name: Set up Python
@@ -145,13 +145,13 @@ jobs:
           sudo apt-get -qq install gcc-multilib libsdl-dev scons
           echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
           echo "RTT_CC=gcc" >> $GITHUB_ENV
-    
+
       - name: Install Arm ToolChains
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
         shell: bash
         run: |
-          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 
-          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt  
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
+          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
           /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
           echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
 
@@ -159,8 +159,8 @@ jobs:
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
         shell: bash
         run: |
-          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 
-          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt  
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
+          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt
           /opt/mips-2016.05/bin/mips-sde-elf-gcc --version
           echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
 

Jenkinsfile

@@ -107,7 +107,6 @@ pipeline {
                         ['stm32f20x', 'sourcery-arm'],
                         ['swm320-lq100', 'sourcery-arm'],
                         ['beaglebone', 'sourcery-arm'],
-                        ['zynq7000', 'sourcery-arm'],
                         ['frdm-k64f', 'sourcery-arm'],
                         ['fh8620', 'sourcery-arm'],
                         ['xplorer4330/M4', 'sourcery-arm'],

bsp/allwinner_tina/applications/main.c

@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/drv_clock.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -541,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         *mmc_clk &= ~(0x1 << 31);
         return RT_EOK;
     }
-    
+
     if (hz <= 24000000)
     {
         pll = (0x0 << 24);
@@ -593,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         oclk_dly = 1;
         sclk_dly = 4;
     }
-    
+
     *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
            (n << 16) | (oclk_dly << 8) | (div - 1);
 

bsp/allwinner_tina/drivers/drv_clock.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_clock.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -252,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
 rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
 
 rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
-#endif
+#endif

bsp/allwinner_tina/drivers/drv_gpio.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/drv_gpio.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -241,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
 void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
 int rt_hw_gpio_init(void);
 
-#endif /* __DRV_GPIO_H__ */
+#endif /* __DRV_GPIO_H__ */

bsp/allwinner_tina/drivers/drv_sdio.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_sdio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -34,10 +20,10 @@
 
 
 #define DBG_TAG  "MMC"
-// #define DBG_LVL DBG_LOG    
-// #define DBG_LVL DBG_INFO   
+// #define DBG_LVL DBG_LOG
+// #define DBG_LVL DBG_INFO
 #define DBG_LVL DBG_WARNING
-// #define DBG_LVL DBG_ERROR  
+// #define DBG_LVL DBG_ERROR
 #include <rtdbg.h>
 
 #ifdef RT_USING_SDIO
@@ -47,12 +33,12 @@
 struct mmc_xfe_des
 {
     rt_uint32_t size;    /* block size  */
-	rt_uint32_t num;     /* block num   */
-	rt_uint8_t *buff;    /* buff addr   */
-	rt_uint32_t flag;    /* write or read or stream */
-#define MMC_DATA_WRITE	(1 << 0)
-#define MMC_DATA_READ	(1 << 1)
-#define MMC_DATA_STREAM	(1 << 2)
+    rt_uint32_t num;     /* block num   */
+    rt_uint8_t *buff;    /* buff addr   */
+    rt_uint32_t flag;    /* write or read or stream */
+#define MMC_DATA_WRITE  (1 << 0)
+#define MMC_DATA_READ   (1 << 1)
+#define MMC_DATA_STREAM (1 << 2)
 };
 
 struct mmc_flag
@@ -71,7 +57,7 @@ struct sdio_drv
     tina_mmc_t mmc_des;
     rt_uint8_t *mmc_buf;
     rt_uint8_t usedma;
-    
+
 };
 
 #ifdef CONFIG_MMC_USE_DMA
@@ -136,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc)
     mmc->risr_reg = mmc->risr_reg;
     return RT_EOK;
 }
-    
+
 static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 {
     ALIGN(32) static struct mmc_des_v4p1 pdes[128];  // mast ALIGN(32)
@@ -145,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     unsigned length = xfe->size * xfe->num;
     unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
     unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
-    
+
     if (remain)
     {
         buff_frag_num ++;
@@ -156,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     memset(pdes, 0, sizeof(pdes));
     mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
-    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) 
+    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++)
     {
         // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
         pdes[des_idx].des_chain = 1;
@@ -182,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
             pdes[des_idx].last_des = 1;
             pdes[des_idx].end_of_ring = 1;
             pdes[des_idx].buf_addr_ptr2 = 0;
-        } 
-        else 
+        }
+        else
         {
             pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
         }
@@ -217,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     mmc->dmac_reg = (1 << 1) | (1 << 7);        /* idma on              */
     rval = mmc->idie_reg & (~3);
     if (xfe->flag == MMC_DATA_WRITE)
-        rval |= (1 << 0);        
+        rval |= (1 << 0);
     else
         rval |= (1 << 1);
     mmc->idie_reg = rval;
@@ -236,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 
     if (xfe->flag == MMC_DATA_WRITE)
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 3)));
 
@@ -251,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     else
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 2)));
 
@@ -290,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
     {
         mmc_set_clk(SDMMC1, clk);
     }
-    
+
     /* Re-enable card clock */
     rval = mmc->ckcr_reg;
     rval |=  (0x1 << 16); //(3 << 16);
@@ -383,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
         cmdval |= (1 << 7);
     if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
         cmdval |= (1 << 8);
-    
+
     if (data)
     {
         cmdval |= (1 << 9) | (1 << 13);
@@ -606,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
 
     memset(&sdio->flag, 0, sizeof(struct mmc_flag));
     mmc_send_cmd(host, req->cmd);
-    
+
     return;
 }
 

bsp/allwinner_tina/drivers/drv_sdio.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_sdio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -133,8 +119,8 @@ REG[31]  : Load cmd
 #define SDXC_UPDATE_CLOCK_CMD    BIT(21)
 #define SDXC_LOAD_CMD            BIT(31)
 
-/* 
-    SD status reg 
+/*
+    SD status reg
 REG[0]   : FIFO_RX_LEVEL
 REG[1]   : FIFO_TX_LEVEL
 REG[2]   : FIFO_EMPTY
@@ -143,7 +129,7 @@ REG[4-7] : FSM_STA
 REG[8]   : CARD_PRESENT
 REG[9]   : CARD_BUSY
 REG[10]  : FSM_BUSY
-REG[11-16]: RESP_IDX 
+REG[11-16]: RESP_IDX
 REG[17-21]: FIFO_LEVEL
 REG[31]   : DMA_REQ
 */

bsp/allwinner_tina/drivers/drv_uart.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -324,4 +310,4 @@ void uart_irq_handler(int irqno, void *param)
 
 }
 
-#endif
+#endif

bsp/allwinner_tina/drivers/drv_uart.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/spi/drv_spi.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/spi/drv_spi.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_spi.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/drivers/spi/drv_spi_flash.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_spi_flash.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -65,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init);
 
 #endif
 
-#endif
+#endif

bsp/allwinner_tina/libcpu/cpu.c

@@ -1,21 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/cpuport.c

@@ -1,21 +1,7 @@
 /*
- * File      : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/interrupt.c

@@ -1,25 +1,12 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-02-08     RT-Thread    the first version
+ * 2020-03-02     Howard Su    Use structure to access registers
  */
 
 #include <rthw.h>
@@ -38,9 +25,6 @@ static void rt_hw_interrupt_handler(int vector, void *param)
     rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
-#define readl(addr)           (*(volatile unsigned int *)(addr))
-#define writel(value,addr)    (*(volatile unsigned int *)(addr) = (value))
-
 /**
  * This function will initialize hardware interrupt
  */
@@ -63,20 +47,20 @@ void rt_hw_interrupt_init(void)
     /* set base_addr reg */
     INTC->base_addr_reg = 0x00000000;
     /* clear enable */
-    INTC->en_reg0 = 0x00000000;
-    INTC->en_reg1 = 0x00000000;
+    INTC->en_reg[0] = 0x00000000;
+    INTC->en_reg[1] = 0x00000000;
     /* mask interrupt */
-    INTC->mask_reg0 = 0xFFFFFFFF;
-    INTC->mask_reg1 = 0xFFFFFFFF;
+    INTC->mask_reg[0] = 0xFFFFFFFF;
+    INTC->mask_reg[1] = 0xFFFFFFFF;
     /* clear pending */
-    INTC->pend_reg0 = 0x00000000;
-    INTC->pend_reg1 = 0x00000000;
+    INTC->pend_reg[0] = 0x00000000;
+    INTC->pend_reg[1] = 0x00000000;
     /* set priority */
-    INTC->resp_reg0 = 0x00000000;
-    INTC->resp_reg1 = 0x00000000;
+    INTC->resp_reg[0] = 0x00000000;
+    INTC->resp_reg[1] = 0x00000000;
     /* close fiq interrupt */
-    INTC->ff_reg0 = 0x00000000;
-    INTC->ff_reg1 = 0x00000000;
+    INTC->ff_reg[0] = 0x00000000;
+    INTC->ff_reg[1] = 0x00000000;
 }
 
 /**
@@ -85,20 +69,16 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-    rt_uint32_t mask_addr, data;
-
+    int index;
     if ((vector < 0) || (vector > INTERRUPTS_MAX))
     {
         return;
     }
 
-    mask_addr = (rt_uint32_t)(&INTC->mask_reg0);
-    mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
+    index = (vector & 0xE0) != 0;
+    vector = (vector & 0x1F);
 
-    vector &= 0x1F;
-    data = readl(mask_addr);
-    data |= 0x1 << vector;
-    writel(data, mask_addr);
+    INTC->mask_reg[index] |= 1 << vector;
 }
 
 /**
@@ -108,20 +88,16 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-    rt_uint32_t mask_addr, data;
-
+    int index;
     if ((vector < 0) || (vector > INTERRUPTS_MAX))
     {
         return;
     }
 
-    mask_addr = (rt_uint32_t)(&INTC->mask_reg0);
-    mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
+    index = (vector & 0xE0) != 0;
+    vector = (vector & 0x1F);
 
-    vector &= 0x1F;
-    data = readl(mask_addr);
-    data &= ~(0x1 << vector);
-    writel(data, mask_addr);
+    INTC->mask_reg[index] &= ~(1 << vector);
 }
 
 /**
@@ -136,7 +112,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
-    rt_uint32_t pend_addr, en_addr, data;
+    int index;
 
     if ((vector < 0) || (vector > INTERRUPTS_MAX))
     {
@@ -151,19 +127,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     isr_table[vector].handler = handler;
     isr_table[vector].param = param;
 
-    pend_addr = (rt_uint32_t)(&INTC->pend_reg0);
-    en_addr = (rt_uint32_t)(&INTC->en_reg0);
-    pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
-    en_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
-
-    vector &= 0x1F;
-    data = readl(pend_addr);
-    data &= ~(0x1 << vector);
-    writel(data, pend_addr);
+    index = (vector & 0xE0) != 0;
+    vector = (vector & 0x1F);
 
-    data = readl(en_addr);
-    data |= 0x1 << vector;
-    writel(data, en_addr);
+    INTC->pend_reg[index] &= ~(0x1 << vector);
+    INTC->en_reg[index] |= 0x1 << vector;
 
     return old_handler;
 }
@@ -173,7 +141,7 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
     void *param;
     int vector;
     rt_isr_handler_t isr_func;
-    rt_uint32_t pend_addr, data;
+    int index;
 
     vector = INTC->vector_reg - INTC->base_addr_reg;
     vector = vector >> 2;
@@ -184,13 +152,11 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
     /* jump to fun */
     isr_func(vector, param);
     /* clear pend bit */
-    pend_addr = (rt_uint32_t)(&INTC->pend_reg0);
-    pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
 
-    vector &= 0x1F;
-    data = readl(pend_addr);
-    data &= ~(0x1 << vector);
-    writel(data, pend_addr);
+    index = (vector & 0xE0) != 0;
+    vector = (vector & 0x1F);
+
+    INTC->pend_reg[index] &= ~(0x1 << vector);
 
 #ifdef RT_USING_INTERRUPT_INFO
     isr_table[vector].counter ++;

bsp/allwinner_tina/libcpu/interrupt.h

@@ -1,25 +1,12 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-02-08     RT-Thread    the first version
+ * 2020-03-2      Howard Su    Define same regsiters as an array
  */
 #ifndef __INTERRUPT_H__
 #define __INTERRUPT_H__
@@ -74,34 +61,21 @@ struct tina_intc
     volatile rt_uint32_t base_addr_reg;    /* 0x04 */
     volatile rt_uint32_t reserved0;
     volatile rt_uint32_t nmi_ctrl_reg;     /* 0x0C */
-    volatile rt_uint32_t pend_reg0;        /* 0x10 */
-    volatile rt_uint32_t pend_reg1;        /* 0x14 */
+    volatile rt_uint32_t pend_reg[2];        /* 0x10, 0x14 */
     volatile rt_uint32_t reserved1[2];
-    volatile rt_uint32_t en_reg0;          /* 0x20 */
-    volatile rt_uint32_t en_reg1;          /* 0x24 */
+    volatile rt_uint32_t en_reg[2];          /* 0x20, 0x24 */
     volatile rt_uint32_t reserved2[2];
-    volatile rt_uint32_t mask_reg0;        /* 0x30 */
-    volatile rt_uint32_t mask_reg1;        /* 0x34 */
+    volatile rt_uint32_t mask_reg[2];        /* 0x30, 0x34 */
     volatile rt_uint32_t reserved3[2];
-    volatile rt_uint32_t resp_reg0;        /* 0x40 */
-    volatile rt_uint32_t resp_reg1;        /* 0x44 */
+    volatile rt_uint32_t resp_reg[2];        /* 0x40, 0x44 */
     volatile rt_uint32_t reserved4[2];
-    volatile rt_uint32_t ff_reg0;          /* 0x50 */
-    volatile rt_uint32_t ff_reg1;          /* 0x54 */
+    volatile rt_uint32_t ff_reg[2];          /* 0x50, 0x54 */
     volatile rt_uint32_t reserved5[2];
-    volatile rt_uint32_t prio_reg0;        /* 0x60 */
-    volatile rt_uint32_t prio_reg1;        /* 0x64 */
-    volatile rt_uint32_t prio_reg2;        /* 0x68 */
-    volatile rt_uint32_t prio_reg3;        /* 0x6C */
+    volatile rt_uint32_t prio_reg[4];        /* 0x60 - 0x6c */
 } ;
 
 typedef struct tina_intc *tina_intc_t;
 
 #define INTC ((tina_intc_t)INTC_BASE_ADDR)
 
-void rt_hw_interrupt_init(void);
-void rt_hw_interrupt_mask(int vector);
-void rt_hw_interrupt_umask(int vector);
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
-
 #endif /* __INTERRUPT_H__ */

bsp/allwinner_tina/libcpu/mmu.c

@@ -1,21 +1,7 @@
 /*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/mmu.h

@@ -1,21 +1,7 @@
 /*
- * File      : mmu.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/rt_low_level_init.c

@@ -1,21 +1,7 @@
 /*
- * File      : rt_low_level_init.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/stack.c

@@ -1,21 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/allwinner_tina/libcpu/trap.c

@@ -1,21 +1,7 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/amebaz/applications/main.c

@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/amebaz/applications/smartconfig_app.c

@@ -1,21 +1,7 @@
 /*
- * File      : smartconfig_demo.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/amebaz/drivers/board.c

@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -44,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...)
      * length. */
     length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
     if (length > RT_CONSOLEBUF_SIZE - 1)
-        length = RT_CONSOLEBUF_SIZE - 1;    
+        length = RT_CONSOLEBUF_SIZE - 1;
     rt_kprintf("%s", rt_log_buf);
     va_end(args);
 }
@@ -89,11 +85,11 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_HEAP
         rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
-    
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-    
+
 #ifdef RT_USING_CONSOLE
     rt_hw_uart_init();
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

bsp/amebaz/drivers/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/amebaz/drivers/drv_uart.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -125,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial)
 {
     struct device_uart* uart = serial->parent.user_data;
 
-	if(!serial_readable(&uart->serial))
+    if(!serial_readable(&uart->serial))
         return -1;
 
     /* Receive Data Available */
@@ -140,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui
 static void ameba_uart_irq(uint32_t id, SerialIrq event)
 {
     struct rt_serial_device *serial = (struct rt_serial_device *)id;
-	if(event == RxIrq)
+    if(event == RxIrq)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-	}
-	else if(event == TxIrq)
+    }
+    else if(event == TxIrq)
     {
-	}
+    }
 }
 
 static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
@@ -155,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c);
 static int dbg_getc(struct rt_serial_device *serial);
 
 static struct rt_serial_device ameba_dbg_serial;
-const struct rt_uart_ops _ambed_dbg_ops = 
+const struct rt_uart_ops _ambed_dbg_ops =
 {
     dbg_configure,
     dbg_control,
@@ -177,7 +163,7 @@ void dbg_uart_irq_handler(void * data)
     DiagSetIsrEnReg(0);
 
     rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND);
-    
+
     DiagSetIsrEnReg(IrqEn);
 }
 
@@ -192,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg)
 
     case RT_DEVICE_CTRL_SET_INT:
         /* install interrupt */
-    	DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
+        DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
         /* Enable the UART Interrupt */
-    	NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
+        NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
         break;
     }
 
@@ -214,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial)
 
     if(!UART_Readable(UART2_DEV))
         return -1;
-    
+
     c = DiagGetChar(_FALSE);
 
     return c;
 }
- 
+
 /*
  * UART Initiation
  */
@@ -231,7 +217,7 @@ int rt_hw_uart_init(void)
 #ifdef BSP_USING_UART0
     {
         struct device_uart      *uart;
-        
+
         serial  = &serial0;
         uart    = &uart0;
 
@@ -256,7 +242,7 @@ int rt_hw_uart_init(void)
 
         serial->ops = &_ambed_dbg_ops;
         serial->config = config;
-        
+
         rt_hw_serial_register(serial,
                               RT_CONSOLE_DEVICE_NAME,
                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,

bsp/amebaz/drivers/drv_uart.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/amebaz/drivers/wlan/drv_wifi.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_wifi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -115,7 +101,7 @@ void netif_pre_sleep_processing(void)
 }
 
 unsigned char *rltk_wlan_get_ip(int idx)
-{   
+{
     struct ameba_wifi *wifi;
 
     wifi = rthw_wifi_get_dev(idx);
@@ -130,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx)
 
 int netif_is_valid_IP(int idx, unsigned char *ip_dest)
 {
-    LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, 
+    LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__,
         ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]);
     return 1;
 }
@@ -376,9 +362,9 @@ static rt_err_t rthw_wlan_join                 (struct rt_wlan_device *wlan, str
             ssid = &sta_info->ssid.val[0];
         if (sta_info->key.len > 0)
             key = &sta_info->key.val[0];
-            LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", 
+            LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d",
             sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5],
-            ssid, 
+            ssid,
             sta_info->ssid.len,
             key,
             sta_info->key.len
@@ -608,7 +594,7 @@ exit:
     return RT_EOK;
 }
 
-static const struct rt_wlan_dev_ops ops = 
+static const struct rt_wlan_dev_ops ops =
 {
     .wlan_init             =     rthw_wlan_init           ,
     .wlan_mode             =     rthw_wlan_mode           ,

bsp/amebaz/drivers/wlan/drv_wifi.h

@@ -1,27 +1,13 @@
 /*
- * File      : drv_wifi.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-5-30      Bernard      the first version
  */
- 
+
 #ifndef __DRV_WIFI_H__
 #define __DRV_WIFI_H__
 

bsp/amebaz/drivers/wlan/drv_wlan.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_wlan.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -151,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel)
         return -1;
     }
 
-    while(1) 
+    while(1)
     {
         char essid[33];
         if(wext_get_ssid(name, (unsigned char *) essid) > 0)
         {
-            if(strcmp((const char *) essid, (const char *)ssid) == 0) 
+            if(strcmp((const char *) essid, (const char *)ssid) == 0)
             {
                 rt_kprintf("%s started\n", ssid);
                 break;
             }
         }
-        if(timeout == 0) 
+        if(timeout == 0)
         {
-            rt_kprintf("Start AP timeout\n");   
+            rt_kprintf("Start AP timeout\n");
             return -1;
         }
         rt_thread_delay(1 * RT_TICK_PER_SECOND);
@@ -183,7 +169,7 @@ static int rthw_wifi_disconnect(char *name)
     if (name == RT_NULL)
         return -1;
 
-    if (wext_get_ssid(name, (unsigned char *) essid) < 0) 
+    if (wext_get_ssid(name, (unsigned char *) essid) < 0)
     {
         rt_kprintf("\nWIFI disconnected!\n");
         return -1;
@@ -203,7 +189,7 @@ static int rthw_wifi_disconnect(char *name)
             break;
         }
 
-        if(timeout == 0) 
+        if(timeout == 0)
         {
             rt_kprintf("ERROR: Deassoc timeout!\n");
             return -1;
@@ -259,7 +245,7 @@ int rthw_wifi_ap_disconnect(void)
 
 int rthw_wifi_rssi_get(void)
 {
-    int rssi = 0;   
+    int rssi = 0;
     wifi_get_rssi(&rssi);
     return rssi;
 }

bsp/amebaz/drivers/wlan/drv_wlan.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_wlan.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,14 +11,14 @@
 #ifndef __DRV_WLAN_H__
 #define __DRV_WLAN_H__
 
-typedef enum 
+typedef enum
 {
-	RTHW_MODE_NONE = 0,
-	RTHW_MODE_STA,
-	RTHW_MODE_AP,
-	RTHW_MODE_STA_AP,
-	RTHW_MODE_PROMISC,
-	RTHW_MODE_P2P
+    RTHW_MODE_NONE = 0,
+    RTHW_MODE_STA,
+    RTHW_MODE_AP,
+    RTHW_MODE_STA_AP,
+    RTHW_MODE_PROMISC,
+    RTHW_MODE_P2P
 }rthw_mode_t;
 
 #define SHARED_ENABLED  0x00008000
@@ -66,7 +52,7 @@ typedef enum {
 typedef enum {
     RTHW_WIFI_EVENT_CONNECT = 0,
     RTHW_WIFI_EVENT_DISCONNECT = 1,
-    RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,	
+    RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
     RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3,
     RTHW_WIFI_EVENT_SCAN_DONE = 4,
     RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5,

bsp/apollo2/applications/main.c

@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/adc.c

@@ -1,21 +1,7 @@
 /*
- * File      : adc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -32,15 +18,15 @@
 struct rt_messagequeue adcbat_mq;
 
 #define BATTERY_GPIO            35                        /* Battery */
-#define BATTERY_ADC_PIN         AM_HAL_PIN_35_ADCSE7 
-#define BATTERY_ADC_CHANNEL     AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */
-#define BATTERY_ADC_CHANNELNUM  7                         /* BATTERY ADC采集通道号 */
+#define BATTERY_ADC_PIN         AM_HAL_PIN_35_ADCSE7
+#define BATTERY_ADC_CHANNEL     AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC閲囬泦閫氶亾 */
+#define BATTERY_ADC_CHANNELNUM  7                         /* BATTERY ADC閲囬泦閫氶亾鍙� */
 
-#define ADC_CTIMER_NUM          3                         /* ADC使用定时器 */
+#define ADC_CTIMER_NUM          3                         /* ADC浣跨敤瀹氭椂鍣� */
 #define ADC_CTIMER_COUNT        (2048/512 - 1)
 
-#define ADC_CHANNEL_NUM         1                         /* ADC采集通道个数 */
-#define ADC_SAMPLE_NUM          8                         /* ADC采样个数 */
+#define ADC_CHANNEL_NUM         1                         /* ADC閲囬泦閫氶亾涓�暟 */
+#define ADC_SAMPLE_NUM          8                         /* ADC閲囨牱涓�暟 */
 
 rt_uint8_t bat_adc_cnt = 0;
 static rt_uint8_t am_adcbat_buffer_pool[256];
@@ -52,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz
 
     if (channel == BATTERY_ADC_CHANNELNUM)
     {
-        /* wait adc message forever */	
+        /* wait adc message forever */
         rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER);
     }
 

bsp/apollo2/board/adc.h

@@ -1,21 +1,7 @@
 /*
- * File      : adc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/flash.c

@@ -1,21 +1,7 @@
 /*
- * File      : flash.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -77,7 +63,7 @@ static rt_err_t rt_flash_control(rt_device_t dev, int cmd, void *args)
                 ui32CurrentPage =  AM_HAL_FLASH_ADDR2PAGE(erase->addrstart);
                 ui32CurrentBlock = AM_HAL_FLASH_ADDR2INST(erase->addrstart);
 
-                am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); //µ¥ÉÈÇø²Á³ýÃüÁî
+                am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); //�扇区擦除命令
                 erase->addrstart += 8192;
             }
         }

bsp/apollo2/board/flash.h

@@ -1,21 +1,7 @@
 /*
- * File      : flash.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/gpio.c

@@ -1,21 +1,7 @@
 /*
- * File      : gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -70,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     else if (value == PIN_HIGH)
     {
         am_hal_gpio_out_bit_set(pin);
-    }    
+    }
 }
 
 int am_pin_read(rt_device_t dev, rt_base_t pin)

bsp/apollo2/board/gpio.h

@@ -1,27 +1,13 @@
 /*
- * File      : gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-09-16     Haley        the first version
  */
- 
+
 #ifndef __GPIO_H
 #define __GPIO_H
 

bsp/apollo2/board/i2c.c

@@ -1,21 +1,7 @@
 /*
- * File      :_i2c.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -133,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops =
 };
 
 #ifdef RT_USING_I2C0
-static struct am_i2c_bus am_i2c_bus_0 = 
+static struct am_i2c_bus am_i2c_bus_0 =
 {
     {0},
     AM_I2C0_IOM_INST
@@ -141,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 =
 #endif
 
 #ifdef RT_USING_I2C1
-static struct am_i2c_bus am_i2c_bus_1 = 
+static struct am_i2c_bus am_i2c_bus_1 =
 {
     {1},
     AM_I2C1_IOM_INST
@@ -149,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 =
 #endif
 
 #ifdef RT_USING_I2C2
-static struct am_i2c_bus am_i2c_bus_2 = 
+static struct am_i2c_bus am_i2c_bus_2 =
 {
     {2},
     AM_I2C2_IOM_INST
@@ -157,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 =
 #endif
 
 #ifdef RT_USING_I2C3
-static struct am_i2c_bus am_i2c_bus_3 = 
+static struct am_i2c_bus am_i2c_bus_3 =
 {
     {3},
     AM_I2C3_IOM_INST
@@ -165,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 =
 #endif
 
 #ifdef RT_USING_I2C4
-static struct am_i2c_bus am_i2c_bus_4 = 
+static struct am_i2c_bus am_i2c_bus_4 =
 {
     {4},
     AM_I2C4_IOM_INST

bsp/apollo2/board/i2c.h

@@ -1,21 +1,7 @@
 /*
- * File      : i2c.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/led.c

@@ -1,21 +1,7 @@
 /*
- * File      :_led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/led.h

@@ -1,21 +1,7 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/pdm.c

@@ -1,21 +1,7 @@
 /*
- * File      :_pdm.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -66,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size)
 {
     rt_uint8_t pdm_rbufftemp[340];
 
-    /* wait pdm message forever */	
+    /* wait pdm message forever */
     rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER);
 
     /* copy the data */

bsp/apollo2/board/pdm.h

@@ -1,21 +1,7 @@
 /*
- * File      : pdm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/pwm.c

@@ -1,21 +1,7 @@
 /*
- * File      :_pwm.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/pwm.h

@@ -1,21 +1,7 @@
 /*
- * File      : pwm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/rtc.c

@@ -1,21 +1,7 @@
 /*
- * File      :_rtc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,6 +11,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "am_mcu_apollo.h"
+#include <sys/time.h>
 
 #define XT              1
 #define LFRC            2
@@ -78,13 +65,13 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
             /* Seconds 0-59 : the 0-59 range */
             time_temp.tm_sec = hal_time.ui32Second;
 
-            *time = mktime(&time_temp);
+            *time = timegm(&time_temp);
 
             break;
 
         case RT_DEVICE_CTRL_RTC_SET_TIME:
             time = (time_t *)args;
-            time_new = localtime(time);
+            time_new = gmtime(time);
 
             hal_time.ui32Hour = time_new->tm_hour;
             hal_time.ui32Minute = time_new->tm_min;
@@ -115,7 +102,7 @@ int rt_hw_rtc_init(void)
     /* Select LFRC for RTC clock source */
     am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
 #endif
-  
+
 #if RTC_CLK_SRC == XT
     /* Enable the XT for the RTC */
     am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT);
@@ -128,12 +115,12 @@ int rt_hw_rtc_init(void)
     am_hal_rtc_osc_enable();
 
     /* register rtc device */
-    rtc.type	= RT_Device_Class_RTC;
-    rtc.init 	= RT_NULL;
-    rtc.open 	= rt_rtc_open;
-    rtc.close	= RT_NULL;
-    rtc.read 	= rt_rtc_read;
-    rtc.write	= RT_NULL;
+    rtc.type    = RT_Device_Class_RTC;
+    rtc.init    = RT_NULL;
+    rtc.open    = rt_rtc_open;
+    rtc.close   = RT_NULL;
+    rtc.read    = rt_rtc_read;
+    rtc.write   = RT_NULL;
     rtc.control = rt_rtc_control;
 
     /* no private */

bsp/apollo2/board/rtc.h

@@ -1,27 +1,13 @@
 /*
- * File      : rtc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-09-14     Haley        the first version
  */
- 
+
 #ifndef __RTC_H
 #define __RTC_H
 

bsp/apollo2/board/smbus.c

@@ -1,21 +1,7 @@
 /*
- * File      : smbus.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -42,8 +28,8 @@
 #define mSDA_OUT()        am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT)                      /* Set SDA as Output */
 #define mSCL_OUT()        am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT)                      /* Set SCL as Output */
 
-#define ACK	      0
-#define	NACK      1
+#define ACK       0
+#define NACK      1
 
 /* SCL keep time */
 static void keep_delay(void)
@@ -60,7 +46,7 @@ static void few_delay(void)
 }
 
 static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit)
-{       
+{
     mSDA_OUT();
     few_delay();
 
@@ -128,7 +114,7 @@ static void am_smbus_stop_bit(void)
 
 static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte)
 {
-    int	i;
+    int i;
     rt_uint8_t ack_bit;
     rt_uint8_t bit_out;
 
@@ -176,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u
     int i;
 
     am_smbus_start_bit();                      /* Start condition */
-		
+
     if(am_smbus_tx_byte(SlaveAddress))         /* Send SlaveAddress and write */
         return 1;
 

bsp/apollo2/board/smbus.h

@@ -1,21 +1,7 @@
 /*
- * File      : smbus.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/apollo2/board/spi.c

@@ -1,21 +1,7 @@
 /*
- * File      : spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -180,7 +166,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
         am_hal_gpio_out_bit_clear(am_spi_cs->chip_select);
     }
 
-    // ¶ÁÊý¾Ý
+    // 读数�
     if (recv_ptr != RT_NULL)
     {
         while (u32BytesRemaining)
@@ -213,7 +199,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
         }
     }
 
-    // дÊý¾Ý
+    // 写数�
     else
     {
         while (u32BytesRemaining)
@@ -225,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
                 u32TransferSize = 64;
                 am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
                                     (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
-        
+
             }
             else
             {
@@ -257,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops =
 };
 
 #ifdef RT_USING_SPI0
-static struct am_spi_bus am_spi_bus_0 = 
+static struct am_spi_bus am_spi_bus_0 =
 {
     {0},
     AM_SPI0_IOM_INST

bsp/apollo2/board/spi.h

@@ -1,21 +1,7 @@
 /*
- * File      : spi.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -27,7 +13,7 @@
 
 #include <rtthread.h>
 
-/* ƬѡÐźŽṹÉùÃ÷ */
+/* 片选信�结构声明 */
 struct am_spi_cs
 {
     rt_uint32_t chip_select;

bsp/apollo2/board/uart.c

@@ -1,21 +1,7 @@
 /*
- * File      : uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -164,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf
     else if (cfg->stop_bits == STOP_BITS_2)
         uart_cfg.bTwoStopBits = true;
 
-    if (cfg->parity == PARITY_NONE)    
+    if (cfg->parity == PARITY_NONE)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE;
-    else if (cfg->parity == PARITY_ODD)    
+    else if (cfg->parity == PARITY_ODD)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD;
-    else if (cfg->parity == PARITY_EVEN)    
+    else if (cfg->parity == PARITY_EVEN)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN;
 
     uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE;

bsp/apollo2/board/uart.h

@@ -1,21 +1,7 @@
 /*
- * File      : uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_ertc.h

@@ -11,6 +11,9 @@
 #ifndef __AT32F4xx_ERTC_H
 #define __AT32F4xx_ERTC_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "at32f4xx.h"

bsp/at32/Libraries/rt_drivers/SConscript

@@ -43,9 +43,15 @@ if GetDepend('BSP_USING_SRAM'):
 if GetDepend('BSP_USING_RTC'):
     src += ['drv_rtc.c']
 
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['drv_flash.c']
+
 if GetDepend(['BSP_USING_WDT']):
     src += ['drv_wdt.c']
 
+if GetDepend(['BSP_USING_CAN']):
+    src += ['drv_can.c']
+
 if GetDepend(['BSP_USING_SDIO']):
     src += ['drv_sdio.c']
 

bsp/at32/Libraries/rt_drivers/drv_adc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 #include <drv_log.h>
 
 struct at32_adc
-{  
+{
     struct rt_adc_device at32_adc_device;
     ADC_Type *ADC_Handler;
     char *name;
@@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
     ADC_InitType ADC_InitStructure;
     RT_ASSERT(device != RT_NULL);
     at32_adc_handler = device->parent.user_data;
-  
+
     at32_msp_adc_init(at32_adc_handler);
-  
+
     /* ADCx configuration ------------------------------------------------------*/
     ADC_StructInit(&ADC_InitStructure);
     ADC_InitStructure.ADC_Mode              = ADC_Mode_Independent;
@@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
     ADC_InitStructure.ADC_DataAlign         = ADC_DataAlign_Right;
     ADC_InitStructure.ADC_NumOfChannel      = 1;
     ADC_Init(at32_adc_handler, &ADC_InitStructure);
-  
-    /* ADCx regular channels configuration */ 
-    ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); 
-    
+
+    /* ADCx regular channels configuration */
+    ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
+
     /* Enable ADCx */
     ADC_Ctrl(at32_adc_handler, ENABLE);
-  
-    /* Enable ADCx reset calibration register */   
+
+    /* Enable ADCx reset calibration register */
     ADC_RstCalibration(at32_adc_handler);
     /* Check the end of ADCx reset calibration register */
     while(ADC_GetResetCalibrationStatus(at32_adc_handler));
@@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha
 
     at32_adc_handler = device->parent.user_data;
 
-    /* Start ADCx Software Conversion */ 
+    /* Start ADCx Software Conversion */
     ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE);
 
     /* Wait for the ADC to convert */

bsp/at32/Libraries/rt_drivers/drv_adc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,32 +19,32 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
-  
+
 #ifndef ADC1_CONFIG
 #define ADC1_CONFIG                 \
     {                              \
        .ADC_Handler = ADC1,        \
        .name        = "adc1",      \
-    }  
+    }
 #endif /* ADC1_CONFIG */
-    
+
 #ifndef ADC2_CONFIG
 #define ADC2_CONFIG                \
     {                              \
        .ADC_Handler = ADC2,        \
        .name        = "adc2",      \
-    }  
+    }
 #endif /* ADC2_CONFIG */
-    
+
 #ifndef ADC3_CONFIG
 #define ADC3_CONFIG                \
     {                              \
        .ADC_Handler = ADC3,        \
        .name        = "adc3",      \
-    }  
-#endif /* ADC3_CONFIG */    
-    
-#endif  
+    }
+#endif /* ADC3_CONFIG */
+
+#endif
 
 
 #ifdef __cplusplus

bsp/at32/Libraries/rt_drivers/drv_can.c

@@ -0,0 +1,878 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#include "drv_can.h"
+#ifdef BSP_USING_CAN
+
+#define LOG_TAG    "drv_can"
+#include <drv_log.h>
+
+/* attention !!! baud calculation example: apbclk / ((ss + bs1 + bs2) * brp), ep: 120 / ((1 + 8 + 3) * 10) = 1MHz*/
+static const struct at32_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud,   CAN_SJW_2tq, CAN_BS1_8tq,  CAN_BS2_3tq, 10},
+    {CAN800kBaud, CAN_SJW_2tq, CAN_BS1_7tq,  CAN_BS2_2tq, 15},
+    {CAN500kBaud, CAN_SJW_2tq, CAN_BS1_9tq,  CAN_BS2_2tq, 20},
+    {CAN250kBaud, CAN_SJW_2tq, CAN_BS1_9tq,  CAN_BS2_2tq, 40},
+    {CAN125kBaud, CAN_SJW_2tq, CAN_BS1_9tq,  CAN_BS2_2tq, 80},
+    {CAN100kBaud, CAN_SJW_2tq, CAN_BS1_13tq, CAN_BS2_2tq, 75},
+    {CAN50kBaud,  CAN_SJW_2tq, CAN_BS1_13tq, CAN_BS2_2tq, 150},
+    {CAN20kBaud,  CAN_SJW_2tq, CAN_BS1_13tq, CAN_BS2_2tq, 375},
+    {CAN10kBaud,  CAN_SJW_2tq, CAN_BS1_13tq, CAN_BS2_2tq, 750}
+};
+
+#ifdef BSP_USING_CAN1
+static struct at32_can can_instance1 =
+{
+    .name = "can1",
+    .CanConfig.Instance = CAN1,
+};
+#endif
+
+#ifdef BSP_USING_CAN2
+static struct at32_can can_instance2 =
+{
+    .name = "can2",
+    .CanConfig.Instance = CAN2,
+};
+#endif
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+    rt_uint32_t len, index;
+
+    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+    for (index = 0; index < len; index++)
+    {
+        if (can_baud_rate_tab[index].baud_rate == baud)
+            return index;
+    }
+
+    return 0; /* default baud is CAN1MBaud */
+}
+
+static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
+{
+    struct at32_can *can_instance;
+    rt_uint32_t baud_index;
+
+    RT_ASSERT(can);
+    RT_ASSERT(cfg);
+    can_instance = (struct at32_can *)can->parent.user_data;
+    RT_ASSERT(can_instance);
+
+    at32_msp_can_init((void *)can_instance->CanConfig.Instance);
+
+    CAN_StructInit(&(can_instance->CanConfig.CanInit));
+
+    can_instance->CanConfig.CanInit.CAN_Mode = DISABLE;
+    can_instance->CanConfig.CanInit.CAN_ABO = ENABLE;
+    can_instance->CanConfig.CanInit.CAN_AWU = ENABLE;
+    can_instance->CanConfig.CanInit.CAN_NART = DISABLE;
+    can_instance->CanConfig.CanInit.CAN_RFL = DISABLE;
+    can_instance->CanConfig.CanInit.CAN_TFP = ENABLE;
+
+    switch (cfg->mode)
+    {
+    case RT_CAN_MODE_NORMAL:
+        can_instance->CanConfig.CanInit.CAN_Mode = CAN_Mode_Normal;
+        break;
+    case RT_CAN_MODE_LISEN:
+        can_instance->CanConfig.CanInit.CAN_Mode = CAN_Mode_Silent;
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        can_instance->CanConfig.CanInit.CAN_Mode = CAN_Mode_LoopBack;
+        break;
+    case RT_CAN_MODE_LOOPBACKANLISEN:
+        can_instance->CanConfig.CanInit.CAN_Mode = CAN_Mode_Silent_LoopBack;
+        break;
+    }
+
+    baud_index = get_can_baud_index(cfg->baud_rate);
+    can_instance->CanConfig.CanInit.CAN_SJW = can_baud_rate_tab[baud_index].sjw;
+    can_instance->CanConfig.CanInit.CAN_BS1 = can_baud_rate_tab[baud_index].bs1;
+    can_instance->CanConfig.CanInit.CAN_BS2 = can_baud_rate_tab[baud_index].bs2;
+    can_instance->CanConfig.CanInit.CAN_Prescaler = can_baud_rate_tab[baud_index].psc;
+
+    /* init can */
+    if (CAN_Init(can_instance->CanConfig.Instance, &(can_instance->CanConfig.CanInit)) != CAN_InitStatus_Success)
+    {
+        return -RT_ERROR;
+    }
+
+    /* default filter config */
+    CAN_FilterInit(can_instance->CanConfig.Instance, &can_instance->CanConfig.FilterConfig);
+
+    return RT_EOK;
+}
+
+static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+    rt_uint32_t argval;
+    NVIC_InitType NVIC_InitStruct;
+    struct at32_can *can_instance;
+    struct rt_can_filter_config *filter_cfg;
+
+    RT_ASSERT(can != RT_NULL);
+    can_instance = (struct at32_can *)can->parent.user_data;
+    RT_ASSERT(can_instance != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+
+                NVIC_InitStruct.NVIC_IRQChannel = CAN1_RX1_IRQn;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_RX0_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_RX1_IRQn;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFP0, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFFU0, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFOV0, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFP1, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFFU1, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFOV1, DISABLE);
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = USB_HP_CAN1_TX_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_TX_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_TSME, DISABLE);
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN1_SCE_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_SCE_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERG, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERP, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_BU, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_LEC, DISABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERR, DISABLE);
+        }
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFP0, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFFU0, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFOV0, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFP1, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFFU1, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_RFOV1, ENABLE);
+
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+
+                NVIC_InitStruct.NVIC_IRQChannel = CAN1_RX1_IRQn;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_RX0_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_RX1_IRQn;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_TSME, ENABLE);
+
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = USB_HP_CAN1_TX_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_TX_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERG, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERP, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_BU, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_LEC, ENABLE);
+            CAN_INTConfig(can_instance->CanConfig.Instance, CAN_INT_ERR, ENABLE);
+
+            if (CAN1 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN1_SCE_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#ifdef CAN2
+            if (CAN2 == can_instance->CanConfig.Instance)
+            {
+                NVIC_InitStruct.NVIC_IRQChannel = CAN2_SCE_IRQn;
+                NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+                NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
+                NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
+                NVIC_Init(&NVIC_InitStruct);
+            }
+#endif
+        }
+        break;
+    case RT_CAN_CMD_SET_FILTER:
+        if (RT_NULL == arg)
+        {
+            /* default filter config */
+            CAN_FilterInit(can_instance->CanConfig.Instance, &can_instance->CanConfig.FilterConfig);
+        }
+        else
+        {
+            filter_cfg = (struct rt_can_filter_config *)arg;
+            /* get default filter */
+            for (int i = 0; i < filter_cfg->count; i++)
+            {
+                can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU);
+                can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
+                can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
+                                                    (filter_cfg->items[i].ide << 2) |
+                                                    (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+                can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
+                can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF;
+                can_instance->CanConfig.FilterConfig.CAN_FilterMode = filter_cfg->items[i].mode;
+                /* Filter conf */
+                CAN_FilterInit(can_instance->CanConfig.Instance, &can_instance->CanConfig.FilterConfig);
+            }
+        }
+        break;
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL &&
+            argval != RT_CAN_MODE_LISEN &&
+            argval != RT_CAN_MODE_LOOPBACK &&
+            argval != RT_CAN_MODE_LOOPBACKANLISEN)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can_instance->device.config.mode)
+        {
+            can_instance->device.config.mode = argval;
+            return _can_config(&can_instance->device, &can_instance->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud &&
+            argval != CAN800kBaud &&
+            argval != CAN500kBaud &&
+            argval != CAN250kBaud &&
+            argval != CAN125kBaud &&
+            argval != CAN100kBaud &&
+            argval != CAN50kBaud  &&
+            argval != CAN20kBaud  &&
+            argval != CAN10kBaud)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can_instance->device.config.baud_rate)
+        {
+            can_instance->device.config.baud_rate = argval;
+            return _can_config(&can_instance->device, &can_instance->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_PRIV:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_PRIV &&
+            argval != RT_CAN_MODE_NOPRIV)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can_instance->device.config.privmode)
+        {
+            can_instance->device.config.privmode = argval;
+            return _can_config(&can_instance->device, &can_instance->device.config);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+    {
+        rt_uint32_t errtype;
+        errtype = can_instance->CanConfig.Instance->ESTS;
+        can_instance->device.status.rcverrcnt = errtype >> 24;
+        can_instance->device.status.snderrcnt = (errtype >> 16 & 0xFF);
+        can_instance->device.status.lasterrtype = errtype & 0x70;
+        can_instance->device.status.errcode = errtype & 0x07;
+
+        rt_memcpy(arg, &can_instance->device.status, sizeof(can_instance->device.status));
+    }
+    break;
+    }
+
+    return RT_EOK;
+}
+
+static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+    struct CAN_Handler *hcan;
+    hcan = &((struct at32_can *) can->parent.user_data)->CanConfig;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    CanTxMsg TxMessage;
+    rt_uint32_t i;
+
+    /* Check the parameters */
+    RT_ASSERT(IS_CAN_DLC(pmsg->len));
+
+    /*check select mailbox  is empty */
+    switch (1 << box_num)
+    {
+      case CAN_TX_MAILBOX0:
+        if ((hcan->Instance->TSTS & CAN_TSTS_TSME0) != CAN_TSTS_TSME0)
+        {
+            /* Return function status */
+            return -RT_ERROR;
+        }
+        break;
+    case CAN_TX_MAILBOX1:
+        if ((hcan->Instance->TSTS & CAN_TSTS_TSME1) != CAN_TSTS_TSME1)
+        {
+            /* Return function status */
+            return -RT_ERROR;
+        }
+        break;
+    case CAN_TX_MAILBOX2:
+        if ((hcan->Instance->TSTS & CAN_TSTS_TSME2) != CAN_TSTS_TSME2)
+        {
+            /* Return function status */
+            return -RT_ERROR;
+        }
+        break;
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+
+    if (RT_CAN_STDID == pmsg->ide)
+    {
+        TxMessage.IDT = CAN_ID_STD;
+        RT_ASSERT(IS_CAN_STDID(pmsg->id));
+        TxMessage.StdId = pmsg->id;
+    }
+    else
+    {
+        TxMessage.IDT = CAN_ID_EXT;
+        RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+        TxMessage.ExtId = pmsg->id;
+    }
+
+    if (RT_CAN_DTR == pmsg->rtr)
+    {
+        TxMessage.RTR = CAN_RTR_DATA;
+    }
+    else
+    {
+        TxMessage.RTR = CAN_RTR_REMOTE;
+    }
+
+    /* Set up the DLC */
+    TxMessage.DLC = pmsg->len & 0x0FU;
+    /* Set up the data field */
+    TxMessage.Data[0] = (uint32_t)pmsg->data[0];
+    TxMessage.Data[1] = (uint32_t)pmsg->data[1];
+    TxMessage.Data[2] = (uint32_t)pmsg->data[2];
+    TxMessage.Data[3] = (uint32_t)pmsg->data[3];
+    TxMessage.Data[4] = (uint32_t)pmsg->data[4];
+    TxMessage.Data[5] = (uint32_t)pmsg->data[5];
+    TxMessage.Data[6] = (uint32_t)pmsg->data[6];
+    TxMessage.Data[7] = (uint32_t)pmsg->data[7];
+
+    CAN_Transmit(hcan->Instance, &TxMessage);
+    while((CAN_TransmitStatus(hcan->Instance, box_num) != CANTXOK) && (i != 0xFFFF))
+    {
+        i++;
+    }
+
+    return RT_EOK;
+}
+
+static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+    struct CAN_Handler *hcan;
+    hcan = &((struct at32_can *) can->parent.user_data)->CanConfig;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    CanRxMsg RxMessage;
+
+    RT_ASSERT(can);
+
+    /* get data */
+    CAN_Receive(hcan->Instance, fifo, &RxMessage);
+
+    pmsg->data[0] = RxMessage.Data[0];
+    pmsg->data[1] = RxMessage.Data[1];
+    pmsg->data[2] = RxMessage.Data[2];
+    pmsg->data[3] = RxMessage.Data[3];
+    pmsg->data[4] = RxMessage.Data[4];
+    pmsg->data[5] = RxMessage.Data[5];
+    pmsg->data[6] = RxMessage.Data[6];
+    pmsg->data[7] = RxMessage.Data[7];
+
+    pmsg->len = RxMessage.DLC;
+    pmsg->id = RxMessage.IDT;
+
+    if (RxMessage.IDT == CAN_ID_STD)
+        pmsg->id = RxMessage.StdId;
+    else
+        pmsg->ide = RxMessage.ExtId;
+    pmsg->rtr = RxMessage.RTR;
+
+    return RT_EOK;
+}
+
+static const struct rt_can_ops _can_ops =
+{
+    _can_config,
+    _can_control,
+    _can_sendmsg,
+    _can_recvmsg,
+};
+
+static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
+{
+    struct CAN_Handler *hcan;
+    RT_ASSERT(can);
+    hcan = &((struct at32_can *) can->parent.user_data)->CanConfig;
+
+    switch (fifo)
+    {
+    case CAN_FIFO0:
+        /* save to user list */
+        if (CAN_MessagePending(hcan->Instance, CAN_FIFO0) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFP0))
+        {
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+        }
+        /* Check FULL flag for FIFO0 */
+        if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RFFU0) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFFU0))
+        {
+            /* Clear FIFO0 FULL Flag */
+            CAN_ClearFlag(hcan->Instance, CAN_FLAG_RFFU0);
+        }
+
+        /* Check Overrun flag for FIFO0 */
+        if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RFOV0) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFOV0))
+        {
+            /* Clear FIFO0 Overrun Flag */
+            CAN_ClearFlag(hcan->Instance, CAN_FLAG_RFOV0);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        break;
+    case CAN_FIFO1:
+        /* save to user list */
+        if (CAN_MessagePending(hcan->Instance, CAN_FIFO1) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFP1))
+        {
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+        }
+        /* Check FULL flag for FIFO1 */
+        if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RFFU1) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFFU1))
+        {
+            /* Clear FIFO1 FULL Flag */
+            CAN_ClearFlag(hcan->Instance, CAN_FLAG_RFFU1);
+        }
+
+        /* Check Overrun flag for FIFO1 */
+        if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RFOV1) && CAN_GetINTStatus(hcan->Instance, CAN_INT_RFOV1))
+        {
+            /* Clear FIFO1 Overrun Flag */
+            CAN_ClearFlag(hcan->Instance, CAN_FLAG_RFOV1);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        break;
+    }
+}
+
+#ifdef BSP_USING_CAN1
+/**
+ * @brief This function handles CAN1 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
+ */
+void USB_HP_CAN1_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    struct CAN_Handler *hcan;
+    hcan = &can_instance1.CanConfig;
+    if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP0))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK0) == CAN_TSTS_TOK0)
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC0;
+    }
+    else if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP1))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK1) == CAN_TSTS_TOK1)
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC1;
+    }
+    else if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP2))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK2) == CAN_TSTS_TOK2)
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC2;
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 RX0 interrupts.
+ */
+void USB_LP_CAN1_RX0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can_instance1.device, CAN_FIFO0);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 RX1 interrupts.
+ */
+void CAN1_RX1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can_instance1.device, CAN_FIFO1);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 SCE interrupts.
+ */
+void CAN1_SCE_IRQHandler(void)
+{
+    rt_uint32_t errtype;
+    struct CAN_Handler *hcan;
+
+    hcan = &can_instance1.CanConfig;
+    errtype = hcan->Instance->ESTS;
+
+    rt_interrupt_enter();
+
+    switch ((errtype & 0x70) >> 4)
+    {
+    case RT_CAN_BUS_BIT_PAD_ERR:
+        can_instance1.device.status.bitpaderrcnt++;
+        break;
+    case RT_CAN_BUS_FORMAT_ERR:
+        can_instance1.device.status.formaterrcnt++;
+        break;
+    case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
+        can_instance1.device.status.ackerrcnt++;
+        if (!(can_instance1.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        else if (!(can_instance1.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        else if (!(can_instance1.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        break;
+    case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+    case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+        can_instance1.device.status.biterrcnt++;
+        break;
+    case RT_CAN_BUS_CRC_ERR:
+        can_instance1.device.status.crcerrcnt++;
+        break;
+    }
+
+    can_instance1.device.status.lasterrtype = errtype & 0x70;
+    can_instance1.device.status.rcverrcnt = errtype >> 24;
+    can_instance1.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+    can_instance1.device.status.errcode = errtype & 0x07;
+    hcan->Instance->MSTS |= CAN_MSTS_ERIT;
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+/**
+ * @brief This function handles CAN2 TX interrupts.
+ */
+void CAN2_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    struct CAN_Handler *hcan;
+    hcan = &can_instance2.CanConfig;
+    if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP0))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK0) == CAN_TSTS_TOK0)
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC0;
+    }
+    else if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP1))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK1) == CAN_TSTS_TOK1)
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC1;
+    }
+    else if (CAN_GetFlagStatus(hcan->Instance, CAN_FLAG_RQCP2))
+    {
+        if ((hcan->Instance->TSTS & CAN_TSTS_TOK2) == CAN_TSTS_TOK2)
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        hcan->Instance->TSTS |= CAN_TSTS_RQC2;
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 RX0 interrupts.
+ */
+void CAN2_RX0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can_instance2.device, CAN_FIFO0);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 RX1 interrupts.
+ */
+void CAN2_RX1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can_instance2.device, CAN_FIFO1);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 SCE interrupts.
+ */
+void CAN2_SCE_IRQHandler(void)
+{
+    rt_uint32_t errtype;
+    struct CAN_Handler *hcan;
+
+    hcan = &can_instance2.CanConfig;
+    errtype = hcan->Instance->ESTS;
+
+    rt_interrupt_enter();
+
+    switch ((errtype & 0x70) >> 4)
+    {
+    case RT_CAN_BUS_BIT_PAD_ERR:
+        can_instance2.device.status.bitpaderrcnt++;
+        break;
+    case RT_CAN_BUS_FORMAT_ERR:
+        can_instance2.device.status.formaterrcnt++;
+        break;
+    case RT_CAN_BUS_ACK_ERR:
+        can_instance2.device.status.ackerrcnt++;
+        if (!(can_instance1.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        else if (!(can_instance2.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        else if (!(can_instance2.CanConfig.Instance->TSTS & CAN_TSTS_TOK0))
+            rt_hw_can_isr(&can_instance2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        break;
+    case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+    case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+        can_instance2.device.status.biterrcnt++;
+        break;
+    case RT_CAN_BUS_CRC_ERR:
+        can_instance2.device.status.crcerrcnt++;
+        break;
+    }
+
+    can_instance2.device.status.lasterrtype = errtype & 0x70;
+    can_instance2.device.status.rcverrcnt = errtype >> 24;
+    can_instance2.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+    can_instance2.device.status.errcode = errtype & 0x07;
+    hcan->Instance->MSTS |= CAN_MSTS_ERIT;
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN2 */
+
+/**
+ * @brief  Error CAN callback.
+ * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+ *         the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_ErrorCallback(struct CAN_Handler *hcan)
+{
+    CAN_INTConfig(hcan->Instance, CAN_INT_TSME |
+                        CAN_INT_RFP0  |
+                        CAN_INT_RFFU0 |
+                        CAN_INT_RFOV0 |
+                        CAN_INT_RFP1  |
+                        CAN_INT_RFFU1 |
+                        CAN_INT_RFOV1 |
+                        CAN_INT_ERG   |
+                        CAN_INT_ERP   |
+                        CAN_INT_LEC   |
+                        CAN_INT_ERR   |
+                        CAN_INT_WK, ENABLE);
+}
+
+int rt_hw_can_init(void)
+{
+    struct can_configure config = CANDEFAULTCONFIG;
+    config.privmode = RT_CAN_MODE_NOPRIV;
+    config.ticks = 50;
+#ifdef RT_CAN_USING_HDR
+    config.maxhdr = 14;
+#endif
+    /* config default filter */
+    CAN_FilterInitType filterConf = {0};
+    filterConf.CAN_FilterIdHigh = 0x0000;
+    filterConf.CAN_FilterIdLow = 0x0000;
+    filterConf.CAN_FilterMskIdHigh = 0x0000;
+    filterConf.CAN_FilterMskIdLow = 0x0000;
+    filterConf.CAN_FilterFIFOAssignment = CAN_Filter_FIFO0;
+    filterConf.CAN_FilterNumber = 0;
+    filterConf.CAN_FilterMode = CAN_FilterMode_IdMask;
+    filterConf.CAN_FilterScale = CAN_FilterScale_32bit;
+    filterConf.CAN_FilterActivation = ENABLE;
+
+#ifdef BSP_USING_CAN1
+    filterConf.CAN_FilterNumber = 0;
+
+    can_instance1.CanConfig.FilterConfig = filterConf;
+    can_instance1.device.config = config;
+    /* register CAN1 device */
+    rt_hw_can_register(&can_instance1.device,
+                       can_instance1.name,
+                       &_can_ops,
+                       &can_instance1);
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+    filterConf.CAN_FilterNumber = 0;
+
+    can_instance2.CanConfig.FilterConfig = filterConf;
+    can_instance2.device.config = config;
+    /* register CAN2 device */
+    rt_hw_can_register(&can_instance2.device,
+                       can_instance2.name,
+                       &_can_ops,
+                       &can_instance2);
+#endif /* BSP_USING_CAN2 */
+
+    return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+#endif /* BSP_USING_CAN */
+
+/************************** end of file ******************/

bsp/at32/Libraries/rt_drivers/drv_can.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
+#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
+#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
+
+struct at32_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t sjw;
+    rt_uint32_t bs1;
+    rt_uint32_t bs2;
+    rt_uint32_t psc;
+};
+
+struct CAN_Handler
+{
+    CAN_Type *Instance;
+    CAN_InitType CanInit;
+    CAN_FilterInitType FilterConfig;
+};
+
+/* at32 can device */
+struct at32_can
+{
+    char *name;
+    struct CAN_Handler CanConfig;
+    struct rt_can_device device;     /* inherit from can device */
+};
+
+int rt_hw_can_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_CAN_H__ */
+
+/************************** end of file ******************/

bsp/at32/Libraries/rt_drivers/drv_eth.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,8 +28,8 @@
 //#define DRV_DEBUG
 #define LOG_TAG             "drv.emac"
 
-#define ETH_RXBUFNB        	4
-#define ETH_TXBUFNB        	2
+#define ETH_RXBUFNB         4
+#define ETH_TXBUFNB         2
 
 #define LINK_THREAD_STACK_SIZE   256
 #define LINK_THREAD_PREORITY     21
@@ -131,14 +131,14 @@ void NVIC_Configuration(void)
     NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
 
     /* 2 bit for pre-emption priority, 2 bits for subpriority */
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); 
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
 
     /* Enable the Ethernet global Interrupt */
     NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);  
+    NVIC_Init(&NVIC_InitStructure);
 }
 
 /**
@@ -173,7 +173,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
-	/*MII Mode GPIO configuration*/
+    /*MII Mode GPIO configuration*/
 #ifdef MII_MODE
 /**********************MII Tx Pin Define****************************/
     /*
@@ -193,7 +193,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
-	/**********************MII Rx Pin Define****************************/
+    /**********************MII Rx Pin Define****************************/
 #if MII_RX_REMAP  /*IO PIN remaped*/
     /*
     ETH_MII_RX_DV-->PD8
@@ -208,7 +208,7 @@ void GPIO_Configuration(void)
     */
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-    GPIO_Init(GPIOD, &GPIO_InitStructure); 
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
 
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@@ -233,11 +233,11 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOA, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;   
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;  
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOB, &GPIO_InitStructure);
 
@@ -255,8 +255,8 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOB, &GPIO_InitStructure);
-	
-	/**********************RMII Rx Pin Define****************************/
+
+    /**********************RMII Rx Pin Define****************************/
 #if MII_RX_REMAP  /*IO PIN remaped*/
     /*
     ETH_RMII_RX_DV-->PD8
@@ -266,7 +266,7 @@ void GPIO_Configuration(void)
     */
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-    GPIO_Init(GPIOD, &GPIO_InitStructure); 
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
 
     GPIO_InitStructure.GPIO_Pins =  GPIO_Pins_1;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@@ -282,7 +282,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOA, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;   
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
@@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
 
     RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX |
                           RCC_AHBPERIPH_ETHMACRX, ENABLE);
-    
+
     /* MII/RMII Media interface selection ------------------------------------------*/
 #ifdef MII_MODE /* Mode MII with AT32F407-EVAL  */
     GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
@@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
     ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
 #endif
 
-    /*------------------------   DMA   -----------------------------------*/  
+    /*------------------------   DMA   -----------------------------------*/
 
-    /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 
-    the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 
+    /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
+    the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
     if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
-    ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; 
-    ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         
-    ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
-
-    ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
-    ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   
-    ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;                                                          
-    ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      
-    ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                
-    ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          
-    ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;                                                                 
+    ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
+    ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+    ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+
+    ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+    ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+    ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
+    ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+    ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
+    ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
+    ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
     ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
 
     /* Configure Ethernet, check error */
     if(ETH_Init(&ETH_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) {
         return RT_ERROR;
-    }    
+    }
 
     /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
-    ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);  
+    ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
 
     /* Initialize Tx Descriptors list: Chain Mode */
     ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
@@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
     ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]);
 
     /* Enable ETH transmition and recetion */
-    ETH_Start();    
+    ETH_Start();
 
     return RT_EOK;
 }
@@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev)
             {
                 rt_uint32_t i;
                 rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr);
-                
+
                 AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len);
                 for(i=0; i<p->tot_len; i++)
                 {

bsp/at32/Libraries/rt_drivers/drv_eth.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_flash.c

@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  addr: address of the flash memory
+  * @retval The page of a given address
+  */
+static rt_uint32_t get_page(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
+
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int at32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int at32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result        = RT_EOK;
+    rt_uint32_t end_addr   = addr + size;
+
+    if (addr % 4 != 0)
+    {
+        LOG_E("write addr must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if ((end_addr) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    FLASH_Unlock();
+
+    while (addr < end_addr)
+    {
+        if (FLASH_ProgramWord(addr, *((rt_uint32_t *)buf)) == FLASH_PRC_DONE)
+        {
+            if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            addr += 4;
+            buf  += 4;
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash .
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int at32_flash_erase(rt_uint32_t addr, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+
+    FLASH_Unlock();
+
+    if ((end_addr) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while(addr < end_addr)
+    {
+        page_addr = get_page(addr);
+
+        if(FLASH_ErasePage(page_addr) != FLASH_PRC_DONE)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += FLASH_PAGE_SIZE;
+    }
+
+        FLASH_Lock();
+
+__exit:
+    if(result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev at32_onchip_flash =
+{
+    "onchip_flash",
+    AT32_FLASH_START_ADRESS,
+    AT32_FLASH_SIZE,
+    FLASH_PAGE_SIZE,
+    {
+        NULL,
+        fal_flash_read,
+        fal_flash_write,
+        fal_flash_erase
+    }
+};
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return at32_flash_read(at32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return at32_flash_write(at32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+    return at32_flash_erase(at32_onchip_flash.addr + offset, size);
+}
+
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */

bsp/at32/Libraries/rt_drivers/drv_flash.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int at32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int at32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int at32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/at32/Libraries/rt_drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,7 +13,7 @@
 
 #ifdef RT_USING_PIN
 
-static const struct pin_index pins[] = 
+static const struct pin_index pins[] =
 {
 #if defined(GPIOA)
     __AT32_PIN(0 ,  A, 0 ),
@@ -414,7 +414,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         /* Configure GPIO_InitStructure */
         GPIO_StructInit(&GPIO_InitStruct);
         EXTI_StructInit(&EXTI_InitStruct);
-        GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;        
+        GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;
         GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
         EXTI_InitStruct.EXTI_Line = irqmap->pinbit;
         EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt;
@@ -462,24 +462,24 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 ))
         {
             if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9)))
-            {    
+            {
                 NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
             }
         }
         else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 ))
         {
             if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15)))
-            {    
+            {
                 NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
             }
         }
         else
         {
             NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
-        }        
+        }
 
         NVIC_Init(&NVIC_InitStruct);
-        rt_hw_interrupt_enable(level);  
+        rt_hw_interrupt_enable(level);
     }
     else
     {

bsp/at32/Libraries/rt_drivers/drv_gpio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_hwtimer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2020-03-16     Leo          first version
  */
- 
+
 #include <board.h>
 #include "drv_hwtimer.h"
 
@@ -20,35 +20,35 @@ enum
 {
 #ifdef BSP_USING_HWTMR1
     TMR1_INDEX,
-#endif 
-  
+#endif
+
 #ifdef BSP_USING_HWTMR2
     TMR2_INDEX,
-#endif 
-  
+#endif
+
 #ifdef BSP_USING_HWTMR3
     TMR3_INDEX,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR4
     TMR4_INDEX,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR5
     TMR5_INDEX,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR6
     TMR6_INDEX,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR7
     TMR7_INDEX,
-#endif 
+#endif
 
 #ifdef BSP_USING_HW_TMR8
     TMR8_INDEX,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR9
     TMR9_INDEX,
@@ -56,11 +56,11 @@ enum
 
 #ifdef BSP_USING_HWTMR10
     TMR10_INDEX,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR11
     TMR11_INDEX,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR12
     TMR12_INDEX,
@@ -68,11 +68,11 @@ enum
 
 #ifdef BSP_USING_HWTMR13
     TMR13_INDEX,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR14
     TMR14_INDEX,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR15
     TMR15_INDEX,
@@ -91,48 +91,48 @@ static struct at32_hwtimer at32_hwtimer_obj[] =
 {
 #ifdef BSP_USING_HWTMR1
     TMR1_CONFIG,
-#endif  
+#endif
 
 #ifdef BSP_USING_HWTMR2
     TMR2_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR3
     TMR3_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR4
     TMR4_CONFIG,
 #endif
 
 #ifdef BSP_USING_HWTMR5
     TMR5_CONFIG,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR6
     TMR6_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR7
     TMR7_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR8
     TMR8_CONFIG,
 #endif
 
 #ifdef BSP_USING_HWTMR9
     TMR9_CONFIG,
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR10
     TMR10_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR11
     TMR11_CONFIG,
 #endif
-  
+
 #ifdef BSP_USING_HWTMR12
     TMR12_CONFIG,
 #endif
@@ -164,20 +164,20 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
     {
         tim = (TMR_Type *)timer->parent.user_data;
         tim_device = (struct at32_hwtimer *)timer;
-        
+
         /* timer clock enable */
         at32_msp_hwtmr_init(tim);
-        
+
         /* timer init */
         RCC_GetClocksFreq(&RCC_ClockStruct);
         /* Set timer clock is 1Mhz */
         prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1;
-        
+
         TMR_TMReBaseStructure.TMR_Period = 10000 - 1;
         TMR_TMReBaseStructure.TMR_DIV = prescaler_value;
         TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1;
         TMR_TMReBaseStructure.TMR_RepetitionCounter = 0;
-        
+
         if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
         {
             TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up;
@@ -186,21 +186,21 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
         {
             TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down;
         }
-        
+
         TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure);
-        
+
         /* Enable the TMRx global Interrupt */
         NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn;
         NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
         NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
         NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
         NVIC_Init(&NVIC_InitStructure);
-        
+
         TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE);
         TMR_ClearITPendingBit(tim, TMR_INT_Overflow);
-        
+
         LOG_D("%s init success", tim_device->name);
-    }      
+    }
 }
 
 static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
@@ -211,7 +211,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
     RT_ASSERT(timer != RT_NULL);
 
     tim = (TMR_Type *)timer->parent.user_data;
-    
+
     /* set tim cnt */
     TMR_SetCounter(tim, 0);
     /* set tim arr */
@@ -225,10 +225,10 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
     {
         TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive);
     }
-    
+
     /* start timer */
     TMR_Cmd(tim, ENABLE);
-    
+
     return result;
 }
 
@@ -239,7 +239,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer)
     RT_ASSERT(timer != RT_NULL);
 
     tim = (TMR_Type *)timer->parent.user_data;
-    
+
     /* stop timer */
     TMR_Cmd(tim, ENABLE);
     /* set tim cnt */
@@ -253,7 +253,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer)
     RT_ASSERT(timer != RT_NULL);
 
     tim = (TMR_Type *)timer->parent.user_data;
-    
+
     return tim->CNT;
 }
 
@@ -267,22 +267,22 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
     RT_ASSERT(arg != RT_NULL);
 
     tim = (TMR_Type *)timer->parent.user_data;
-    
+
     switch(cmd)
     {
         case HWTIMER_CTRL_FREQ_SET:
         {
             rt_uint32_t freq;
             rt_uint16_t val;
-            
+
             /* set timer frequence */
             freq = *((rt_uint32_t *)arg);
-            
+
             /* time init */
             RCC_GetClocksFreq(&RCC_ClockStruct);
-            
+
             val = RCC_ClockStruct.SYSCLK_Freq / freq;
-            
+
             TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate);
         }
         break;
@@ -292,7 +292,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
         }
         break;
     }
-    
+
     return result;
 }
 
@@ -311,13 +311,13 @@ void TMR2_GLOBAL_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET)
     {
-    
+
         rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device);
         TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow);
-    
+
     }
     /* leave interrupt */
     rt_interrupt_leave();
@@ -329,13 +329,13 @@ void TMR3_GLOBAL_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET)
     {
-    
+
         rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device);
         TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow);
-    
+
     }
     /* leave interrupt */
     rt_interrupt_leave();
@@ -347,13 +347,13 @@ void TMR4_GLOBAL_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET)
     {
-    
+
         rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device);
         TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow);
-    
+
     }
     /* leave interrupt */
     rt_interrupt_leave();
@@ -365,13 +365,13 @@ void TMR5_GLOBAL_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET)
     {
-    
+
         rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device);
         TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow);
-    
+
     }
     /* leave interrupt */
     rt_interrupt_leave();

bsp/at32/Libraries/rt_drivers/drv_hwtimer.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
         .maxcnt  = 0xFFFF,                      \
         .cntmode = HWTIMER_CNTMODE_UP,          \
     }
-#endif /* TIM_DEV_INFO_CONFIG */  
+#endif /* TIM_DEV_INFO_CONFIG */
 
 #ifdef BSP_USING_HWTMR2
 #ifndef TMR2_CONFIG
@@ -36,9 +36,9 @@ extern "C" {
        .tim_irqn      = TMR2_GLOBAL_IRQn, \
        .name          = "timer2",     \
     }
-#endif /* TMR2_CONFIG */  
-#endif /* BSP_USING_HWTMR2 */ 
-  
+#endif /* TMR2_CONFIG */
+#endif /* BSP_USING_HWTMR2 */
+
 #ifdef BSP_USING_HWTMR3
 #ifndef TMR3_CONFIG
 #define TMR3_CONFIG                   \
@@ -47,8 +47,8 @@ extern "C" {
        .tim_irqn      = TMR3_GLOBAL_IRQn, \
        .name          = "timer3",     \
     }
-#endif /* TMR3_CONFIG */  
-#endif /* BSP_USING_HWTMR3 */  
+#endif /* TMR3_CONFIG */
+#endif /* BSP_USING_HWTMR3 */
 
 #ifdef BSP_USING_HWTMR4
 #ifndef TMR4_CONFIG
@@ -58,9 +58,9 @@ extern "C" {
        .tim_irqn      = TMR4_GLOBAL_IRQn, \
        .name          = "timer4",     \
     }
-#endif /* TMR4_CONFIG */  
+#endif /* TMR4_CONFIG */
 #endif /* BSP_USING_HWTMR4 */
-    
+
 #ifdef BSP_USING_HWTMR5
 #ifndef TMR5_CONFIG
 #define TMR5_CONFIG                   \
@@ -69,9 +69,9 @@ extern "C" {
        .tim_irqn      = TMR5_GLOBAL_IRQn, \
        .name          = "timer5",     \
     }
-#endif /* TMR5_CONFIG */  
-#endif /* BSP_USING_HWTMR5 */    
-    
+#endif /* TMR5_CONFIG */
+#endif /* BSP_USING_HWTMR5 */
+
 #ifdef __cplusplus
 }
 #endif

bsp/at32/Libraries/rt_drivers/drv_log.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_pwm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -37,52 +37,52 @@ struct at32_pwm
     char *name;
 };
 
-static struct at32_pwm at32_pwm_obj[] = 
+static struct at32_pwm at32_pwm_obj[] =
 {
   #ifdef BSP_USING_TMR1_CH1
     PWM1_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR1_CH2
     PWM2_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR1_CH3
     PWM3_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR1_CH4
     PWM4_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR2_CH1
     PWM5_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR2_CH2
     PWM6_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR2_CH3
     PWM7_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR2_CH4
     PWM8_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR3_CH1
     PWM9_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR3_CH2
     PWM10_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR3_CH3
     PWM11_CONFIG,
   #endif
-  
+
   #ifdef BSP_USING_TMR3_CH4
     PWM12_CONFIG,
   #endif
@@ -97,7 +97,7 @@ static struct rt_pwm_ops drv_ops =
 static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
 {
     /* Get the value of channel */
-    rt_uint32_t channel = configuration->channel;   
+    rt_uint32_t channel = configuration->channel;
 
     if (!enable)
     {
@@ -137,7 +137,7 @@ static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *conf
           TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
         }
     }
-    
+
     /* TMRx enable counter */
     TMR_Cmd(TMRx, ENABLE);
 
@@ -173,7 +173,7 @@ static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configu
       configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
     if(channel == 4)
       configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
-       
+
     return RT_EOK;
 }
 
@@ -185,15 +185,15 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
     rt_uint64_t psc;
     /* Get the channel number */
     rt_uint32_t channel = configuration->channel;
-    
+
     /* Init timer pin and enable clock */
     at32_msp_tmr_init(TMRx);
-  
+
     /* Convert nanosecond to frequency and duty cycle. */
     period = (unsigned long long)configuration->period ;
     psc = period / MAX_PERIOD + 1;
     period = period / psc;
-  
+
     /* TMRe base configuration */
     TMR_TimeBaseStructInit(&TMR_TMReBaseStructure);
     TMR_TMReBaseStructure.TMR_Period = period;
@@ -204,14 +204,14 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
     TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure);
 
     pulse = (unsigned long long)configuration->pulse;
-    
+
     /* PWM1 Mode configuration: Channel1 */
     TMR_OCStructInit(&TMR_OCInitStructure);
     TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1;
     TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable;
     TMR_OCInitStructure.TMR_Pulse = pulse;
     TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High;
-    
+
     if(channel == 1)
     {
       TMR_OC1Init(TMRx, &TMR_OCInitStructure);
@@ -232,7 +232,7 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
       TMR_OC4Init(TMRx, &TMR_OCInitStructure);
       TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable);
     }
-    
+
     TMR_ARPreloadConfig(TMRx, ENABLE);
 
 #if defined (SOC_SERIES_AT32F415)
@@ -271,7 +271,7 @@ static int rt_hw_pwm_init(void)
 {
     int i = 0;
     int result = RT_EOK;
- 
+
     for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
     {
         if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK)
@@ -280,9 +280,9 @@ static int rt_hw_pwm_init(void)
         }
         else
         {
-          LOG_D("%s register failed", at32_pwm_obj[i].name); 
-          result = -RT_ERROR; 
-        }            
+          LOG_D("%s register failed", at32_pwm_obj[i].name);
+          result = -RT_ERROR;
+        }
     }
 
     return result;

bsp/at32/Libraries/rt_drivers/drv_pwm.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ extern "C" {
   }
 #endif /* PWM1_CONFIG */
 #endif /* BSP_USING_TMR1_CH1 */
-  
+
 #ifdef BSP_USING_TMR1_CH2
 #ifndef PWM2_CONFIG
 #define PWM2_CONFIG              \
@@ -72,7 +72,7 @@ extern "C" {
   }
 #endif /* PWM5_CONFIG */
 #endif /* BSP_USING_TMR2_CH1 */
-  
+
 #ifdef BSP_USING_TMR2_CH2
 #ifndef PWM6_CONFIG
 #define PWM6_CONFIG              \
@@ -82,8 +82,8 @@ extern "C" {
     .channel      = 2            \
   }
 #endif /* PWM6_CONFIG */
-#endif /* BSP_USING_TMR2_CH2 */  
-  
+#endif /* BSP_USING_TMR2_CH2 */
+
 #ifdef BSP_USING_TMR2_CH3
 #ifndef PWM7_CONFIG
 #define PWM7_CONFIG              \
@@ -93,7 +93,7 @@ extern "C" {
     .channel      = 3            \
   }
 #endif /* PWM7_CONFIG */
-#endif /* BSP_USING_TMR2_CH3 */  
+#endif /* BSP_USING_TMR2_CH3 */
 
 #ifdef BSP_USING_TMR2_CH4
 #ifndef PWM8_CONFIG
@@ -115,7 +115,7 @@ extern "C" {
     .channel      = 1            \
   }
 #endif /* PWM9_CONFIG */
-#endif /* BSP_USING_TMR3_CH1 */   
+#endif /* BSP_USING_TMR3_CH1 */
 
 #ifdef BSP_USING_TMR3_CH2
 #ifndef PWM10_CONFIG
@@ -149,7 +149,7 @@ extern "C" {
   }
 #endif /* PWM12_CONFIG */
 #endif /* BSP_USING_TMR3_CH4 */
-  
+
 #ifdef __cplusplus
 }
 #endif

bsp/at32/Libraries/rt_drivers/drv_rtc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,6 +10,7 @@
 
 #include "board.h"
 #include <rtthread.h>
+#include <sys/time.h>
 
 #ifdef BSP_USING_RTC
 
@@ -42,7 +43,7 @@ static time_t get_rtc_timestamp(void)
     tm_new.tm_year = ERTC_DateStruct.ERTC_Year + 100;
 
     LOG_D("get rtc time.");
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 #else
     return RTC_GetCounter();
 #endif
@@ -56,7 +57,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
 
     struct tm *p_tm;
 
-    p_tm = localtime(&time_stamp);
+    p_tm = gmtime(&time_stamp);
     if (p_tm->tm_year < 100)
     {
         return -RT_ERROR;
@@ -78,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
         return -RT_ERROR;
     }
 #else
-	/* Set the RTC counter value */
-	RTC_SetCounter(time_stamp);
-	/* Wait until last write operation on RTC registers has finished */
-	RTC_WaitForLastTask();
+    /* Set the RTC counter value */
+    RTC_SetCounter(time_stamp);
+    /* Wait until last write operation on RTC registers has finished */
+    RTC_WaitForLastTask();
 #endif /* SOC_SERIES_AT32F415 */
     LOG_D("set rtc time.");
 #ifdef SOC_SERIES_AT32F415
@@ -116,7 +117,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
     ERTC_InitType ERTC_InitStructure;
 #endif
     /* Allow access to BKP Domain */
-    PWR_BackupAccessCtrl(ENABLE); 
+    PWR_BackupAccessCtrl(ENABLE);
 
 #ifdef SOC_SERIES_AT32F415
   #ifdef BSP_RTC_USING_LSI
@@ -147,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
 #else
     if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA)
 #endif
-  	{
+    {
         LOG_I("RTC hasn't been configured, please use <date> command to config.");
 #ifdef SOC_SERIES_AT32F415
         /* Configure the ERTC data register and ERTC prescaler */

bsp/at32/Libraries/rt_drivers/drv_sdio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_sdio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -205,10 +205,10 @@ int rt_hw_i2c_init(void)
         result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
         RT_ASSERT(result == RT_EOK);
         at32_i2c_bus_unlock(&soft_i2c_config[i]);
-        
+
         LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
-        soft_i2c_config[i].bus_name, 
-        soft_i2c_config[i].scl, 
+        soft_i2c_config[i].bus_name,
+        soft_i2c_config[i].scl,
         soft_i2c_config[i].sda);
     }
 

bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -37,7 +37,7 @@ struct at32_i2c
         .bus_name = "i2c1",                              \
     }
 #endif
-    
+
 #ifdef BSP_USING_I2C2
 #define i2c_bus_CONFIG                                   \
     {                                                    \
@@ -46,7 +46,7 @@ struct at32_i2c
         .bus_name = "i2c2",                              \
     }
 #endif
-    
+
 #ifdef BSP_USING_I2C3
 #define I2C3_BUS_CONFIG                                  \
     {                                                    \
@@ -55,7 +55,7 @@ struct at32_i2c
         .bus_name = "i2c3",                              \
     }
 #endif
-		
+
 #ifdef BSP_USING_I2C4
 #define I2C4_BUS_CONFIG                                  \
     {                                                    \

bsp/at32/Libraries/rt_drivers/drv_spi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2020-01-09     shelton      first version
  */
- 
+
 #include <board.h>
 #include "drv_spi.h"
 
@@ -24,7 +24,7 @@
 #ifdef DEBUG
 #define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
 #else
-#define DEBUG_PRINTF(...)   
+#define DEBUG_PRINTF(...)
 #endif
 
 /* private rt-thread spi ops function */
@@ -81,13 +81,13 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
 static rt_err_t configure(struct rt_spi_device* device,
                           struct rt_spi_configuration* configuration)
 {
-    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;	
+    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
     struct at32_spi *spi_instance = (struct at32_spi *)spi_bus->parent.user_data;
-    
+
     SPI_InitType SPI_InitStruct;
 
-	  RT_ASSERT(device != RT_NULL);
-	  RT_ASSERT(configuration != RT_NULL);
+      RT_ASSERT(device != RT_NULL);
+      RT_ASSERT(configuration != RT_NULL);
 
     at32_msp_spi_init(spi_instance->config->spix);
 
@@ -162,7 +162,7 @@ static rt_err_t configure(struct rt_spi_device* device,
             SPI_InitStruct.SPI_MCLKP = SPI_MCLKP_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -172,11 +172,11 @@ static rt_err_t configure(struct rt_spi_device* device,
     case RT_SPI_MODE_1:
         SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
         SPI_InitStruct.SPI_CPOL = SPI_CPOL_LOW;
-        break;        
+        break;
     case RT_SPI_MODE_2:
         SPI_InitStruct.SPI_CPHA = SPI_CPHA_1EDGE;
         SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
-        break;    
+        break;
     case RT_SPI_MODE_3:
         SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
         SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
@@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device,
     /* init SPI */
     SPI_Init(spi_instance->config->spix, &SPI_InitStruct);
     /* Enable SPI_MASTER */
-	  SPI_Enable(spi_instance->config->spix, ENABLE);
+      SPI_Enable(spi_instance->config->spix, ENABLE);
     SPI_CRCEN(spi_instance->config->spix, DISABLE);
 
     return RT_EOK;
@@ -213,9 +213,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     struct rt_spi_configuration * config = &device->config;
     struct at32_spi_cs * at32_spi_cs = device->parent.user_data;
 
-	  RT_ASSERT(device != NULL);
-	  RT_ASSERT(message != NULL);
-	
+      RT_ASSERT(device != NULL);
+      RT_ASSERT(message != NULL);
+
     /* take CS */
     if(message->cs_take)
     {
@@ -229,7 +229,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -240,12 +240,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by at32 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
                 // Send the byte
-				        SPI_I2S_TxData(spi_instance->config->spix, data);
+                        SPI_I2S_TxData(spi_instance->config->spix, data);
 
                 //Wait until a data is received
                 while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 //Wait until the transmit buffer is empty
                 while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
                 // Send the byte
-				        SPI_I2S_TxData(spi_instance->config->spix, data);
+                        SPI_I2S_TxData(spi_instance->config->spix, data);
 
                 //Wait until a data is received
                 while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     /* release CS */
     if(message->cs_release)
     {
-		    GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
+            GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
         DEBUG_PRINTF("spi release cs\n");
     }
 
@@ -306,7 +306,7 @@ static struct at32_spi_config configs[] = {
 #ifdef BSP_USING_SPI1
     {SPI1, "spi1"},
 #endif
-    
+
 #ifdef BSP_USING_SPI2
     {SPI2, "spi2"},
 #endif

bsp/at32/Libraries/rt_drivers/drv_spi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_sram.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ static int rt_hw_sram_Init(void)
 
     /* Init XMC pin */
     at32_msp_xmc_init(XMC);
-    
+
     /*-- FSMC Configuration ------------------------------------------------------*/
     p.XMC_AdrOpTime         = 0x04;
     p.XMC_AdrHoldTime       = 0x04;
@@ -53,7 +53,7 @@ static int rt_hw_sram_Init(void)
     XMC_NORSRAMInitStructure.XMC_Dev                    = XMC_Dev_SRAM;
     XMC_NORSRAMInitStructure.XMC_BusType                = XMC_BusType_16b;
     XMC_NORSRAMInitStructure.XMC_EnableBurstMode        = XMC_BurstMode_Disable;
-    XMC_NORSRAMInitStructure.XMC_EnableAsynWait         = XMC_AsynWait_Disable;  
+    XMC_NORSRAMInitStructure.XMC_EnableAsynWait         = XMC_AsynWait_Disable;
     XMC_NORSRAMInitStructure.XMC_WaitSignalLv           = XMC_WaitSignalLv_Low;
     XMC_NORSRAMInitStructure.XMC_EnableBurstModeSplit   = XMC_BurstModeSplit_Disable;
     XMC_NORSRAMInitStructure.XMC_WaitSignalConfig       = XMC_WaitSignalConfig_BeforeWaitState;
@@ -63,9 +63,9 @@ static int rt_hw_sram_Init(void)
     XMC_NORSRAMInitStructure.XMC_WriteBurstSyn          = XMC_WriteBurstSyn_Disable;
     XMC_NORSRAMInitStructure.XMC_RWTimingStruct         = &p;
     XMC_NORSRAMInitStructure.XMC_WTimingStruct          = &p;
-    
-    XMC_NORSRAMInit(&XMC_NORSRAMInitStructure); 
-    
+
+    XMC_NORSRAMInit(&XMC_NORSRAMInitStructure);
+
     /*!< Enable FSMC Bank1_SRAM Bank */
     XMC_NORSRAMCmd(XMC_Bank1_NORSRAM3, ENABLE);
 
@@ -73,7 +73,7 @@ static int rt_hw_sram_Init(void)
         /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
         rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, SRAM_LENGTH);
 #endif
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_sram_Init);
@@ -81,11 +81,11 @@ INIT_BOARD_EXPORT(rt_hw_sram_Init);
 #ifdef DRV_DEBUG
 #ifdef FINSH_USING_MSH
 /**
-  * @brief  Writes a Half-word buffer to the FSMC SRAM memory. 
-  * @param  pBuffer : pointer to buffer. 
-  * @param  WriteAddr : SRAM memory internal address from which the data will be 
+  * @brief  Writes a Half-word buffer to the FSMC SRAM memory.
+  * @param  pBuffer : pointer to buffer.
+  * @param  WriteAddr : SRAM memory internal address from which the data will be
   *         written.
-  * @param  NumHalfwordToWrite : number of half-words to write. 
+  * @param  NumHalfwordToWrite : number of half-words to write.
   * @retval None
   */
 static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
@@ -94,15 +94,15 @@ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t Num
   {
     /*!< Transfer data to the memory */
     *(uint16_t *) (EXT_SRAM_BEGIN + WriteAddr) = *pBuffer++;
-    
-    /*!< Increment the address*/  
+
+    /*!< Increment the address*/
     WriteAddr += 2;
-  }   
+  }
 }
 
 /**
   * @brief  Reads a block of data from the FSMC SRAM memory.
-  * @param  pBuffer : pointer to the buffer that receives the data read from the 
+  * @param  pBuffer : pointer to the buffer that receives the data read from the
   *         SRAM memory.
   * @param  ReadAddr : SRAM memory internal address to read from.
   * @param  NumHalfwordToRead : number of half-words to read.
@@ -115,9 +115,9 @@ static void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHa
     /*!< Read a half-word from the memory */
     *pBuffer++ = *(__IO uint16_t*) (EXT_SRAM_BEGIN + ReadAddr);
 
-    /*!< Increment the address*/  
+    /*!< Increment the address*/
     ReadAddr += 2;
-  }  
+  }
 }
 
 /**
@@ -146,9 +146,9 @@ int sram_test(void)
 
 
     /* Read data from XMC SRAM memory */
-    SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);  
+    SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);
 
-    /* Read back SRAM memory and check content correctness */   
+    /* Read back SRAM memory and check content correctness */
     for (Index = 0x00; (Index < RT_BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
     {
         if (RT_RxBuffer[Index] != RT_TxBuffer[Index])
@@ -156,7 +156,7 @@ int sram_test(void)
             WriteReadStatus = Index + 1;
         }
     }
-    
+
     if(WriteReadStatus == 0)
     {
         LOG_D("SRAM test success!");
@@ -165,7 +165,7 @@ int sram_test(void)
     {
         LOG_E("SRAM test failed!");
     }
-    
+
     return RT_EOK;
 }
 MSH_CMD_EXPORT(sram_test, sram test)

bsp/at32/Libraries/rt_drivers/drv_sram.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_usart.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
     !defined(BSP_USING_UART3)
     #error "Please define at least one BSP_USING_UARTx"
-    /* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
+    /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 #endif
 
 struct at32_usart {

bsp/at32/Libraries/rt_drivers/drv_usart.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_wdt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/at32f403a-start/.config

@@ -55,6 +55,7 @@ CONFIG_RT_USING_MEMHEAP=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -109,34 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
 #
 # Device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-CONFIG_RT_USING_DFS_ELMFAT=y
-
-#
-# elm-chan's FatFs, Generic FAT Filesystem Module
-#
-CONFIG_RT_DFS_ELM_CODE_PAGE=437
-CONFIG_RT_DFS_ELM_WORD_ACCESS=y
-# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
-CONFIG_RT_DFS_ELM_USE_LFN_3=y
-CONFIG_RT_DFS_ELM_USE_LFN=3
-CONFIG_RT_DFS_ELM_MAX_LFN=255
-CONFIG_RT_DFS_ELM_DRIVES=2
-CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
-# CONFIG_RT_DFS_ELM_USE_ERASE is not set
-CONFIG_RT_DFS_ELM_REENTRANT=y
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS is not set
 
 #
 # Device Drivers
@@ -151,8 +125,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
@@ -180,10 +156,6 @@ CONFIG_RT_USING_PIN=y
 #
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
 
 #
@@ -230,12 +202,15 @@ CONFIG_RT_USING_POSIX=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -262,6 +237,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -274,9 +250,10 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -295,6 +272,12 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 
 #
 # security packages
@@ -303,6 +286,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -319,6 +303,9 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 
 #
 # tools packages
@@ -330,13 +317,31 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
 
 #
 # system packages
@@ -348,6 +353,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -360,6 +366,27 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
 
 #
 # peripheral libraries and drivers
@@ -368,6 +395,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -377,6 +405,9 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -394,8 +425,30 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
 
 #
 # miscellaneous packages
@@ -405,6 +458,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -425,6 +479,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_NNOM is not set
 # CONFIG_PKG_USING_LIBANN is not set
 # CONFIG_PKG_USING_ELAPACK is not set
@@ -432,6 +487,20 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
 CONFIG_SOC_FAMILY_AT32=y
 CONFIG_SOC_SERIES_AT32F403A=y
 
@@ -449,6 +518,8 @@ CONFIG_BSP_USING_SERIAL=y
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_RTC is not set
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
 CONFIG_BSP_USING_UART2=y
@@ -458,4 +529,5 @@ CONFIG_BSP_USING_UART3=y
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_I2C1 is not set
 # CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_CAN is not set
 # CONFIG_BSP_USING_SDIO is not set

bsp/at32/at32f403a-start/README.md

@@ -46,8 +46,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PWM       | 支持     | TMR1/2                     |
 | HWTIMER   | 支持     | TMR3/4/5                   |
 | SDIO      | 支持     | SDIO1                      |
+| CAN       | 支持     | CAN1/2                     |
 | WDT       | 支持     |                            |
 | RTC       | 支持     |                            |
+| FLASH     | 支持     |                            |
 
 ### IO在板级支持包中的映射情况
 
@@ -88,6 +90,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PC3  | ADC1/2_IN13    |
 | PC4  | ADC1/2_IN14    |
 | PC5  | ADC1/2_IN15    |
+| PA11 | CAN1_RX        |
+| PA12 | CAN1_TX        |
+| PB5  | CAN2_RX        |
+| PB6  | CAN2_TX        |
 
 ## 使用说明
 

bsp/at32/at32f403a-start/applications/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/at32f403a-start/board/Kconfig

@@ -24,6 +24,10 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_PIN
         default y
 
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n 
+
     menuconfig BSP_USING_RTC
         bool "Enable RTC"
         select RT_USING_RTC
@@ -151,6 +155,19 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using CAN1"
+                default n
+            config BSP_USING_CAN2
+                bool "using CAN2"
+                default n
+        endif
+
     menuconfig BSP_USING_SDIO
         bool "Enable SDIO"
         default n

bsp/at32/at32f403a-start/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include <stdint.h>
 #include <rthw.h>
 #include <rtthread.h>

bsp/at32/at32f403a-start/board/board.h

@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2020-01-15     shelton      first version
+ * 2021-02-09     shelton      add flash macros
  */
 
 #ifndef __BOARD_H__
@@ -18,6 +19,12 @@
 extern "C" {
 #endif
 
+/* Just only support for AT32F40xxG */
+#define AT32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define FLASH_PAGE_SIZE             (2 * 1024)
+#define AT32_FLASH_SIZE             (1024 * 1024)
+#define AT32_FLASH_END_ADDRESS      ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
+
 /* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
 #define AT32_SRAM_SIZE      96
 #define AT32_SRAM_END       (0x20000000 + AT32_SRAM_SIZE * 1024)

bsp/at32/at32f403a-start/board/msp/at32_msp.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.c
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp source file
   ******************************************************************************
   * @attention
@@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance)
     GPIO_InitType GPIO_InitStruct;
     ADC_Type *ADCx = (ADC_Type *)Instance;
 
-#ifdef BSP_USING_ADC1  
+#ifdef BSP_USING_ADC1
     if(ADCx == ADC1)
-    {   
+    {
         /* ADC1 & GPIO clock enable */
         RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
-		
-        /* Configure ADC Channel as analog input */      
+
+        /* Configure ADC Channel as analog input */
         GPIO_StructInit(&GPIO_InitStruct);
         GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
         GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
         GPIO_Init(GPIOC, &GPIO_InitStruct);
-        
+
     }
 #endif
 
-#ifdef BSP_USING_ADC2  
+#ifdef BSP_USING_ADC2
     if(ADCx == ADC2)
     {
         /* ADC2 & GPIO clock enable */
         RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
-      
-        /* Configure ADC Channel as analog input */      
+
+        /* Configure ADC Channel as analog input */
         GPIO_StructInit(&GPIO_InitStruct);
         GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
         GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
         GPIO_Init(GPIOC, &GPIO_InitStruct);
     }
-#endif     
+#endif
 }
 #endif /* BSP_USING_ADC */
 
@@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance)
         /* TMR3 clock enable */
         RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE);
     }
-#endif 
+#endif
 
 #ifdef BSP_USING_HWTMR4
     if(TMRx == TMR4)
@@ -256,3 +256,44 @@ void at32_msp_hwtmr_init(void *Instance)
 #endif
 }
 #endif
+
+#ifdef BSP_USING_CAN
+void at32_msp_can_init(void *Instance)
+{
+    GPIO_InitType GPIO_InitStruct;
+    CAN_Type *CANx = (CAN_Type *)Instance;
+
+    GPIO_StructInit(&GPIO_InitStruct);
+    GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+#ifdef BSP_USING_CAN1
+    if(CAN1 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN1, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_11;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+    }
+#endif
+#ifdef BSP_USING_CAN2
+    if(CAN2 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN2, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
+        GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_6;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_5;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+    }
+#endif
+}
+#endif /* BSP_USING_CAN */

bsp/at32/at32f403a-start/board/msp/at32_msp.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.h
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp header file
   ******************************************************************************
   * @attention
@@ -29,5 +29,6 @@ void at32_msp_i2c_init(void *Instance);
 void at32_msp_sdio_init(void *Instance);
 void at32_msp_adc_init(void *Instance);
 void at32_msp_hwtmr_init(void *Instance);
+void at32_msp_can_init(void *Instance);
 
 #endif /* __AT32_MSP_H__ */

bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c

@@ -17,7 +17,7 @@
   *
   * <h2><center>&copy; COPYRIGHT 2018 ArteryTek</center></h2>
   ******************************************************************************
-  */ 
+  */
 
 /** @addtogroup CMSIS
   * @{
@@ -68,23 +68,23 @@
 
       Clock (MHz)
           PLL from HSE or HSI
-          SYSCLK	    HCLK	PCLK2	PCLK1
-          24	        24	    24	    24
-          36	        36	    36	    36
-          48	        48	    48	    24
-          56	        56	    56	    28
-          72	        72	    72	    36
-          96	        96	    48	    48
-          108	        108	    54	    54
-          120	        120	    60	    60
-          144	        144	    72	    72
-          150	        150	    75	    75
-          168	        168	    84	    84
-          176	        176	    88	    88
-          192	        192	    96	    96
-          200	        200	    100	    100
-          224	        224	    112	    112
-          240	        240	    120	    120
+          SYSCLK        HCLK    PCLK2   PCLK1
+          24            24      24      24
+          36            36      36      36
+          48            48      48      24
+          56            56      56      28
+          72            72      72      36
+          96            96      48      48
+          108           108     54      54
+          120           120     60      60
+          144           144     72      72
+          150           150     75      75
+          168           168     84      84
+          176           176     88      88
+          192           192     96      96
+          200           200     100     100
+          224           224     112     112
+          240           240     120     120
     */
 
 #if defined (AT32F403xx) || defined (AT32F413xx) || \
@@ -143,7 +143,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 This value must be a multiple of 0x200. */
 
 
@@ -573,7 +573,7 @@ static void SetSysClock(void)
 /**
   * @brief  Setup the external memory controller.
   *         Called in startup_at32f4xx_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted
+  *           This function configures the external SRAM mounted
   *         (AT32 High density devices). This SRAM will be used as program
   *         data memory (including heap and stack).
   * @param  None
@@ -654,7 +654,7 @@ static void SetSysClockToHSE(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -674,7 +674,7 @@ static void SetSysClockToHSE(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -725,7 +725,7 @@ static void SetSysClockTo24M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -745,7 +745,7 @@ static void SetSysClockTo24M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -811,7 +811,7 @@ static void SetSysClockTo36M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -831,7 +831,7 @@ static void SetSysClockTo36M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -897,7 +897,7 @@ static void SetSysClockTo48M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -917,7 +917,7 @@ static void SetSysClockTo48M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -984,7 +984,7 @@ static void SetSysClockTo56M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void)
 
     /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
     RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-    
+
 #if defined (AT32F415xx)
     RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
 #else
@@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void)
     StartUpCounter++;
   }
   while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx 
+#ifdef AT32F403xx
   WaitHseStbl(HSE_STABLE_DELAY);
 #endif
   if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void)
 
     /* Flash 1 wait state */
     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;    
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
 #endif
     /* HCLK = SYSCLK */
     RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void)
   * @}
   */
 
-/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ 
+/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/

bsp/at32/at32f403a-start/project.ewp

@@ -220,8 +220,8 @@
           <name>CCDefines</name>
           <state />
           <state>AT32F403AVGT7</state>
+          <state>__RTTHREAD__</state>
           <state>RT_USING_DLIBC</state>
-          <state>_DLIB_FILE_DESCRIPTOR</state>
           <state>USE_STDPERIPH_DRIVER</state>
         </option>
         <option>
@@ -348,22 +348,19 @@
         <option>
           <name>CCIncludePath2</name>
           <state />
-          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs</state>
           <state>$PROJ_DIR$\board\msp</state>
           <state>$PROJ_DIR$\..\..\..\components\finsh</state>
           <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
           <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
-          <state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
           <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
           <state>$PROJ_DIR$\..\Libraries\rt_drivers</state>
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
           <state>$PROJ_DIR$\applications</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\AT32F4xx_StdPeriph_Driver\inc</state>
           <state>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib</state>
           <state>$PROJ_DIR$\board</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\CMSIS</state>
-          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\CMSIS\AT32\AT32F4xx\inc</state>
           <state>$PROJ_DIR$\..\..\..\include</state>
         </option>
@@ -1260,8 +1257,8 @@
           <name>CCDefines</name>
           <state />
           <state>AT32F403AVGT7</state>
+          <state>__RTTHREAD__</state>
           <state>RT_USING_DLIBC</state>
-          <state>_DLIB_FILE_DESCRIPTOR</state>
           <state>USE_STDPERIPH_DRIVER</state>
         </option>
         <option>
@@ -1388,22 +1385,19 @@
         <option>
           <name>CCIncludePath2</name>
           <state />
-          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs</state>
           <state>$PROJ_DIR$\board\msp</state>
           <state>$PROJ_DIR$\..\..\..\components\finsh</state>
           <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
           <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
-          <state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
           <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
           <state>$PROJ_DIR$\..\Libraries\rt_drivers</state>
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
           <state>$PROJ_DIR$\applications</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\AT32F4xx_StdPeriph_Driver\inc</state>
           <state>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib</state>
           <state>$PROJ_DIR$\board</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\CMSIS</state>
-          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
           <state>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\CMSIS\AT32\AT32F4xx\inc</state>
           <state>$PROJ_DIR$\..\..\..\include</state>
         </option>
@@ -2081,57 +2075,57 @@
     </settings>
   </configuration>
   <group>
-    <name>Kernel</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
-    </file>
+    <name>Applications</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+      <name>$PROJ_DIR$\applications\main.c</name>
     </file>
+  </group>
+  <group>
+    <name>CPU</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S</name>
     </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\mem.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\completion.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\pipe.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\signal.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c</name>
     </file>
-  </group>
-  <group>
-    <name>Applications</name>
     <file>
-      <name>$PROJ_DIR$\applications\main.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c</name>
     </file>
   </group>
   <group>
@@ -2156,109 +2150,70 @@
     </file>
   </group>
   <group>
-    <name>cpu</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
-    </file>
+    <name>finsh</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S</name>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
     </file>
   </group>
   <group>
-    <name>Filesystem</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\poll.c</name>
-    </file>
+    <name>Kernel</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\src\select.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
     </file>
-  </group>
-  <group>
-    <name>DeviceDrivers</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\completion.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\mem.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\pipe.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
     </file>
   </group>
   <group>
-    <name>finsh</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
-    </file>
+    <name>libc</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\msh_file.c</name>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c</name>
     </file>
-  </group>
-  <group>
-    <name>libc</name>
     <file>
       <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c</name>
     </file>
-  </group>
-  <group>
-    <name>dlib</name>
     <file>
       <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
     </file>
@@ -2292,9 +2247,12 @@
     <file>
       <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
     </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+    </file>
   </group>
   <group>
-    <name>AT32_Lib</name>
+    <name>Libraries</name>
     <file>
       <name>$PROJ_DIR$\..\Libraries\AT32_Std_Driver\AT32F4xx_StdPeriph_Driver\src\at32f4xx_adc.c</name>
     </file>